diff --git a/.github/workflows/pandoc.yml b/.github/workflows/pandoc.yml index 92b155704..6a50938c0 100644 --- a/.github/workflows/pandoc.yml +++ b/.github/workflows/pandoc.yml @@ -17,12 +17,12 @@ concurrency: jobs: build: - runs-on: ubuntu-latest + runs-on: ubuntu-24.04 steps: - name: Checkout uses: actions/checkout@v4 - name: Install packages - run: sudo apt-get update && sudo apt-get -yq install inkscape pandoc pngquant + run: sudo apt-get update && sudo apt-get -yq install fonts-crosextra-carlito inkscape pandoc pngquant - name: Setup Pages id: pages uses: actions/configure-pages@v5 diff --git a/svg/antenna.svg b/svg/antenna.svg index b4d961a8e..9ffb43a31 100644 --- a/svg/antenna.svg +++ b/svg/antenna.svg @@ -5,9 +5,9 @@ - T1-1-X65+transformer - 2×J310amplifier - PLP-30+filter + T1-1-X65+transformer + 2×J310amplifier + PLP-30+filter @@ -21,20 +21,20 @@ - 5 m - 2.5 m + 5 m + 2.5 m - T1-1-X65+transformer - 2×J310amplifier - PLP-30+filter - 1.4 m + T1-1-X65+transformer + 2×J310amplifier + PLP-30+filter + 1.4 m - 1 m + 1 m diff --git a/svg/application-structure.svg b/svg/application-structure.svg index 747891458..a25462d74 100644 --- a/svg/application-structure.svg +++ b/svg/application-structure.svg @@ -8,11 +8,11 @@ - ADC interface - DSP + ADC interface + DSP - BRAM + BRAM @@ -28,13 +28,13 @@ - FIFO + FIFO - DAC interface + DAC interface @@ -48,13 +48,13 @@ - AXI4 hub - config register - status register - status register - CPU - to DAC - from ADC - from computer - to computer + AXI4 hub + config register + status register + status register + CPU + to DAC + from ADC + from computer + to computer diff --git a/svg/input-buffer.svg b/svg/input-buffer.svg index 614c3450d..e2c44f526 100644 --- a/svg/input-buffer.svg +++ b/svg/input-buffer.svg @@ -1,24 +1,24 @@ - + - in_valid + in_valid - in_ready - in_data + in_ready + in_data - out_valid + out_valid - out_ready - out_data + out_ready + out_data @@ -32,14 +32,14 @@ - D - Q - en + D + Q + en - D - en - Q + D + en + Q diff --git a/svg/interface-buffers.svg b/svg/interface-buffers.svg index e8b3bbadc..da8ef552c 100644 --- a/svg/interface-buffers.svg +++ b/svg/interface-buffers.svg @@ -1,64 +1,64 @@ - + - in_valid + in_valid - in_ready - in_data + in_ready + in_data - out_valid + out_valid - out_ready - out_data + out_ready + out_data - D - Q - en + D + Q + en - D - Q - en + D + Q + en - combinational logic + combinational logic - in_valid + in_valid - in_ready - in_data + in_ready + in_data - out_valid + out_valid - out_ready - out_data + out_ready + out_data - D - en - Q + D + en + Q - combinational logic + combinational logic diff --git a/svg/mcpha-gen.svg b/svg/mcpha-gen.svg index a5981a198..429c95e7a 100644 --- a/svg/mcpha-gen.svg +++ b/svg/mcpha-gen.svg @@ -8,22 +8,22 @@ - DAC interface + DAC interface - 125 MSPS 24 bits + 125 MSPS 24 bits - IIR - IIR - to OUT1 - 125 MSPS 16 bits - 125 MSPS 14 bits - FIFO + IIR + IIR + to OUT1 + 125 MSPS 16 bits + 125 MSPS 14 bits + FIFO - config register + config register - CPU - status register + CPU + status register @@ -32,7 +32,7 @@ - impulse generator + impulse generator diff --git a/svg/mcpha.svg b/svg/mcpha.svg index 2423abda7..1255b04eb 100644 --- a/svg/mcpha.svg +++ b/svg/mcpha.svg @@ -6,42 +6,42 @@ - CPU + CPU - from IN1 - ADC interface - FIR + from IN1 + ADC interface + FIR - from IN2 - 125 MSPS 14 bits - CIC ↓ 4–8192 + from IN2 + 125 MSPS 14 bits + CIC ↓ 4–8192 - ADC interface - FIR + ADC interface + FIR - 125 MSPS 14 bits - CIC ↓ 4–8192 + 125 MSPS 14 bits + CIC ↓ 4–8192 - pulse height analyzer + pulse height analyzer - pulse height analyzer + pulse height analyzer - trigger and oscilloscope + trigger and oscilloscope - histogram + histogram - histogram + histogram @@ -49,28 +49,28 @@ - FIR + FIR - CIC ↓ 4–8192 + CIC ↓ 4–8192 - pulse height analyzer + pulse height analyzer - FIFO + FIFO - FIR + FIR - CIC ↓ 4–8192 + CIC ↓ 4–8192 - pulse height analyzer + pulse height analyzer - FIFO + FIFO diff --git a/svg/output-buffer.svg b/svg/output-buffer.svg index 1f2aa350a..161ee8ed7 100644 --- a/svg/output-buffer.svg +++ b/svg/output-buffer.svg @@ -1,13 +1,13 @@ - + - in_valid + in_valid - in_ready - in_data + in_ready + in_data @@ -19,22 +19,22 @@ - out_valid + out_valid - out_ready - out_data + out_ready + out_data - D - Q - en + D + Q + en - D - Q - en + D + Q + en diff --git a/svg/output-buffers-dsp48.svg b/svg/output-buffers-dsp48.svg index 5c6cd5bf6..778915668 100644 --- a/svg/output-buffers-dsp48.svg +++ b/svg/output-buffers-dsp48.svg @@ -1,23 +1,23 @@ - + - in_valid + in_valid - in_ready + in_ready - in_data + in_data - CEA2 - CEB2 + CEA2 + CEB2 - CEM - CEP - DSP48E1 + CEM + CEP + DSP48E1 @@ -25,18 +25,18 @@ - out_valid + out_valid - out_ready - out_data + out_ready + out_data - D - Q - en + D + Q + en @@ -47,9 +47,9 @@ - D - Q - en + D + Q + en @@ -58,9 +58,9 @@ - D - Q - en + D + Q + en diff --git a/svg/playground.svg b/svg/playground.svg index 06ce07d7d..6cbc5675d 100644 --- a/svg/playground.svg +++ b/svg/playground.svg @@ -7,14 +7,14 @@ - FIFO + FIFO - from ADC + from ADC - multiplier + multiplier @@ -22,37 +22,37 @@ - config register - status register + config register + status register - counter + counter - to LEDs + to LEDs - port 0 - port 1 - port 2 - port 3 + port 0 + port 1 + port 2 + port 3 - Jupyter + Jupyter - CPU + CPU - ADC interface + ADC interface - BRAM + BRAM - DAC interface + DAC interface - to DAC - AXI4 hub + to DAC + AXI4 hub diff --git a/svg/pulsed-nmr-122-88.svg b/svg/pulsed-nmr-122-88.svg index bed31f7bb..4e214b391 100644 --- a/svg/pulsed-nmr-122-88.svg +++ b/svg/pulsed-nmr-122-88.svg @@ -5,71 +5,71 @@ - I - Q - 122.88 MSPS 16 bits - 122.88 MSPS 24 bits + I + Q + 122.88 MSPS 16 bits + 122.88 MSPS 24 bits - complex multiplier + complex multiplier - CIC ↓ 48–3072 - FIR ↓ 2 - CPU - 2560–40 kSPS 32 bits + CIC ↓ 48–3072 + FIR ↓ 2 + CPU + 2560–40 kSPS 32 bits - cos - -sin + cos + -sin - from ADC + from ADC - FIFO + FIFO - gate controller + gate controller - DDS + DDS - to DAC + to DAC - gate + gate - 1280–20 kSPS 32 bits + 1280–20 kSPS 32 bits - DDS - sin + DDS + sin - to DAC + to DAC - phase offset - I - Q + phase offset + I + Q - complex multiplier + complex multiplier - CIC ↓ 48–3072 - FIR ↓ 2 + CIC ↓ 48–3072 + FIR ↓ 2 - from ADC + from ADC - cos - -sin + cos + -sin diff --git a/svg/pulsed-nmr.svg b/svg/pulsed-nmr.svg index 564d931b2..a5664a6d9 100644 --- a/svg/pulsed-nmr.svg +++ b/svg/pulsed-nmr.svg @@ -5,71 +5,71 @@ - I - Q - 125 MSPS 14 bits - 125 MSPS 24 bits + I + Q + 125 MSPS 14 bits + 125 MSPS 24 bits - complex multiplier + complex multiplier - CIC ↓ 50–2500 - FIR ↓ 2 - CPU - 2500–50 kSPS 32 bits + CIC ↓ 50–2500 + FIR ↓ 2 + CPU + 2500–50 kSPS 32 bits - cos - -sin + cos + -sin - from ADC + from ADC - FIFO + FIFO - gate controller + gate controller - DDS + DDS - to DAC + to DAC - gate + gate - 1250–25 kSPS 32 bits + 1250–25 kSPS 32 bits - DDS - sin + DDS + sin - to DAC + to DAC - phase offset - I - Q + phase offset + I + Q - complex multiplier + complex multiplier - CIC ↓ 50–2500 - FIR ↓ 2 + CIC ↓ 50–2500 + FIR ↓ 2 - from ADC + from ADC - cos - -sin + cos + -sin diff --git a/svg/scanner.svg b/svg/scanner.svg index 3ff673c8f..e2952123f 100644 --- a/svg/scanner.svg +++ b/svg/scanner.svg @@ -5,41 +5,41 @@ - CPU + CPU - from IN1 + from IN1 - from IN2 - ADC interface + from IN2 + ADC interface - 125 MSPS 14 bits - accumulator + 125 MSPS 14 bits + accumulator - FIFO + FIFO - FIFO + FIFO - stepper + stepper - pulse generator + pulse generator - DAC interface + DAC interface - to OUT1 - 125 MSPS 14 bits + to OUT1 + 125 MSPS 14 bits - to E1 + to E1 - to OUT2 + to OUT2 diff --git a/svg/scripts.svg b/svg/scripts.svg index a92d49e97..30fec7259 100644 --- a/svg/scripts.svg +++ b/svg/scripts.svg @@ -1,38 +1,38 @@ - + - package IP cores + package IP cores - instantiate IP cores - connect IP cores - generate bitstream - patch and build Linux - build OS image - scripts - core.tcl - project.tcl - bitstream.tcl - Makefile - image.sh - arguments - axi_hub - led_blinker - led_blinker - NAME=led_blinker - xc7z010clg400-1 - xc7z010clg400-1 - ps7_cortexa9_0 - ps7_cortexa9_0 - all - 1024 - scripts/debian.sh - led-blinker.img + instantiate IP cores + connect IP cores + generate bitstream + patch and build Linux + build OS image + scripts + core.tcl + project.tcl + bitstream.tcl + Makefile + image.sh + arguments + axi_hub + led_blinker + led_blinker + NAME=led_blinker + xc7z010clg400-1 + xc7z010clg400-1 + ps7_cortexa9_0 + ps7_cortexa9_0 + all + 1024 + scripts/debian.sh + led-blinker.img @@ -42,23 +42,23 @@ - generate hardware definition - hwdef.tcl - led_blinker + generate hardware definition + hwdef.tcl + led_blinker - generate first stage boot loader - fsbl.tcl - led_blinker + generate first stage boot loader + fsbl.tcl + led_blinker - generate device tree - devicetree.tcl - led_blinker + generate device tree + devicetree.tcl + led_blinker - tmp/device-tree-xlnx-xilinx_v2023.1 + tmp/device-tree-xlnx-xilinx_v2023.1 diff --git a/svg/sdr-receiver-ft8-122-88.svg b/svg/sdr-receiver-ft8-122-88.svg index c898e4c80..1a2373e68 100644 --- a/svg/sdr-receiver-ft8-122-88.svg +++ b/svg/sdr-receiver-ft8-122-88.svg @@ -5,55 +5,55 @@ - I - Q - 122.88 MSPS 16 bits - 122.88 MSPS 24 bits + I + Q + 122.88 MSPS 16 bits + 122.88 MSPS 24 bits - complex multiplier + complex multiplier - CIC ↓ 128 + CIC ↓ 128 - 4000 SPS 32 bits - 960 kSPS 32 bits + 4000 SPS 32 bits + 960 kSPS 32 bits - FIFO - config register + FIFO + config register - CPU + CPU - status register + status register - fixed to float converter + fixed to float converter - 4000 SPS 32 bits + 4000 SPS 32 bits - CIC ↓ 120 - 8000 SPS 32 bits + CIC ↓ 120 + 8000 SPS 32 bits - FIR ↓ 2 + FIR ↓ 2 - DDS - cos - -sin + DDS + cos + -sin - from ADC + from ADC diff --git a/svg/sdr-receiver-ft8.svg b/svg/sdr-receiver-ft8.svg index 01a6a3c03..ba5192347 100644 --- a/svg/sdr-receiver-ft8.svg +++ b/svg/sdr-receiver-ft8.svg @@ -5,55 +5,55 @@ - I - Q - 125 MSPS 14 bits - 125 MSPS 24 bits + I + Q + 125 MSPS 14 bits + 125 MSPS 24 bits - complex multiplier + complex multiplier - CIC ↓ 125 + CIC ↓ 125 - 4000 SPS 32 bits - 1 MSPS 32 bits + 4000 SPS 32 bits + 1 MSPS 32 bits - FIFO - config register + FIFO + config register - CPU + CPU - status register + status register - fixed to float converter + fixed to float converter - 4000 SPS 32 bits + 4000 SPS 32 bits - CIC ↓ 125 - 8000 SPS 32 bits + CIC ↓ 125 + 8000 SPS 32 bits - FIR ↓ 2 + FIR ↓ 2 - DDS - cos - -sin + DDS + cos + -sin - from ADC + from ADC diff --git a/svg/sdr-receiver-hpsdr-ddc.svg b/svg/sdr-receiver-hpsdr-ddc.svg index 860052d34..b5c2e496c 100644 --- a/svg/sdr-receiver-hpsdr-ddc.svg +++ b/svg/sdr-receiver-hpsdr-ddc.svg @@ -11,44 +11,44 @@ - ADC interface - I - Q - 125 MSPS 24 bits + ADC interface + I + Q + 125 MSPS 24 bits - CIC ↓ 250–1000 + CIC ↓ 250–1000 - complex multiplier - DDS - cos - -sin - 125–500 kSPS 32 bits + complex multiplier + DDS + cos + -sin + 125–500 kSPS 32 bits - 120–480 kSPS 24 bits + 120–480 kSPS 24 bits - Xilinx IP cores - custom IP cores - 125 MSPS 14 bits - FIR ↓ 5/2 - FIR ↓ 25/24 - 48–192 kSPS 24 bits + Xilinx IP cores + custom IP cores + 125 MSPS 14 bits + FIR ↓ 5/2 + FIR ↓ 25/24 + 48–192 kSPS 24 bits - FIFO - config register + FIFO + config register - CPU + CPU - status register + status register @@ -58,5 +58,5 @@ - from ADC + from ADC diff --git a/svg/sdr-receiver-wspr-122-88.svg b/svg/sdr-receiver-wspr-122-88.svg index 115ee6027..d4570815d 100644 --- a/svg/sdr-receiver-wspr-122-88.svg +++ b/svg/sdr-receiver-wspr-122-88.svg @@ -5,55 +5,55 @@ - I - Q - 122.88 MSPS 16 bits - 122.88 MSPS 24 bits + I + Q + 122.88 MSPS 16 bits + 122.88 MSPS 24 bits - complex multiplier + complex multiplier - CIC ↓ 256 + CIC ↓ 256 - 375 SPS 32 bits - 480 kSPS 32 bits + 375 SPS 32 bits + 480 kSPS 32 bits - FIFO - config register + FIFO + config register - CPU + CPU - status register + status register - fixed to float converter + fixed to float converter - 375 SPS 32 bits + 375 SPS 32 bits - CIC ↓ 640 - 750 SPS 32 bits + CIC ↓ 640 + 750 SPS 32 bits - FIR ↓ 2 + FIR ↓ 2 - DDS - cos - -sin + DDS + cos + -sin - from ADC + from ADC diff --git a/svg/sdr-receiver-wspr.svg b/svg/sdr-receiver-wspr.svg index 467fbf398..535b7003e 100644 --- a/svg/sdr-receiver-wspr.svg +++ b/svg/sdr-receiver-wspr.svg @@ -5,60 +5,60 @@ - I - Q - 125 MSPS 14 bits - 125 MSPS 24 bits + I + Q + 125 MSPS 14 bits + 125 MSPS 24 bits - complex multiplier + complex multiplier - FIR ↓ 4/3 - CIC ↓ 250 + FIR ↓ 4/3 + CIC ↓ 250 - 375 SPS 32 bits - 500 kSPS 32 bits + 375 SPS 32 bits + 500 kSPS 32 bits - FIFO - config register + FIFO + config register - CPU + CPU - status register + status register - fixed to float converter + fixed to float converter - 375 SPS 32 bits + 375 SPS 32 bits - CIC ↓ 250 - 2000 SPS 32 bits + CIC ↓ 250 + 2000 SPS 32 bits - FIR ↓ 4 - 1500 SPS 32 bits + FIR ↓ 4 + 1500 SPS 32 bits - DDS - cos - -sin + DDS + cos + -sin - from ADC + from ADC diff --git a/svg/sdr-smem.svg b/svg/sdr-smem.svg index 5a35e76ed..aab0d247a 100644 --- a/svg/sdr-smem.svg +++ b/svg/sdr-smem.svg @@ -5,19 +5,19 @@ - sdr_receiver - tcp_smem - wave_smem - skimmer - intf_smem - skimsrv + sdr_receiver + tcp_smem + wave_smem + skimmer + intf_smem + skimsrv - extio_smem - hdsdr + extio_smem + hdsdr diff --git a/svg/sdr-transceiver-122-88.svg b/svg/sdr-transceiver-122-88.svg index eb4b3a7ee..56df71e0a 100644 --- a/svg/sdr-transceiver-122-88.svg +++ b/svg/sdr-transceiver-122-88.svg @@ -5,106 +5,106 @@ - ADC interface - FIR ↓ 2 + ADC interface + FIR ↓ 2 - I - Q - 122.88 MSPS 16 bits - CPU + I + Q + 122.88 MSPS 16 bits + CPU - from IN1 - 122.88 MSPS 24 bits + from IN1 + 122.88 MSPS 24 bits - DAC interface - CIC ↑ 40–2560 - FIR ↑ 2 + DAC interface + CIC ↑ 40–2560 + FIR ↑ 2 - to OUT1 + to OUT1 - 122.88 MSPS 24 bits - 122.88 MSPS 14 bits - I - Q + 122.88 MSPS 24 bits + 122.88 MSPS 14 bits + I + Q - CIC ↓ 40–2560 + CIC ↓ 40–2560 - complex multiplier + complex multiplier - DDS + DDS - cos - -sin + cos + -sin - complex multiplier + complex multiplier - DDS + DDS - cos - sin + cos + sin - 24–1536 kSPS 24 bits - 48–3072 kSPS 24 bits - ADC interface - FIR ↓ 2 + 24–1536 kSPS 24 bits + 48–3072 kSPS 24 bits + ADC interface + FIR ↓ 2 - I - Q + I + Q - from IN2 - 122.88 MSPS 24 bits + from IN2 + 122.88 MSPS 24 bits - DAC interface - CIC ↑ 40–2560 - FIR ↑ 2 + DAC interface + CIC ↑ 40–2560 + FIR ↑ 2 - to OUT2 + to OUT2 - 122.88 MSPS 24 bits - I - Q + 122.88 MSPS 24 bits + I + Q - CIC ↓ 40–2560 + CIC ↓ 40–2560 - complex multiplier + complex multiplier - DDS + DDS - cos - -sin + cos + -sin - complex multiplier + complex multiplier - DDS + DDS - cos - sin + cos + sin @@ -113,12 +113,12 @@ - 24–1536 kSPS 24 bits - 48–3072 kSPS 24 bits - 122.88 MSPS 16 bits + 24–1536 kSPS 24 bits + 48–3072 kSPS 24 bits + 122.88 MSPS 16 bits - 122.88 MSPS 14 bits + 122.88 MSPS 14 bits - to E1 + to E1 diff --git a/svg/sdr-transceiver-hpsdr-alex-interface.svg b/svg/sdr-transceiver-hpsdr-alex-interface.svg index 848e67d38..8913e67ab 100644 --- a/svg/sdr-transceiver-hpsdr-alex-interface.svg +++ b/svg/sdr-transceiver-hpsdr-alex-interface.svg @@ -1,6 +1,6 @@ - 1 + 1 @@ -24,25 +24,25 @@ - 2 - 3 - 4 - 5 - 6 - 7 - 8 - 9 - 10 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 20 + 19 + 18 + 17 + 16 + 15 + 14 + 13 + 12 + 11 @@ -107,68 +107,68 @@ - VCC - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - Serial Data - GND - GND - Serial Data - GND - GND - GND - GND - VCC - VCC - VCC - VCC - VCC - VCC - RX Strobe - RX Strobe - Clock - Clock - TX Strobe - TX Strobe - Clock - Clock - Yellow LED - 30/20m LPF - 60/40m LPF - 80m LPF - 160m LPF - Red LED - 6m LPF (Bypass) - 12/10m LPF - 17/15m LPF - TX 1 - TX 2 - TX 3 - T/R Relay - Yellow LED - 13MHz HPF - 20MHz HPF - 6M Preamp - 9.5MHz HPF - 6.5MHz HPF - 1.5MHz HPF - XVTR RX In - RX 2 In - RX 1 In - RX 1 Out - Bypass - 20dB Attenuator - 10dB Attenuator - Red LED - 1 + VCC + GND + GND + GND + GND + GND + GND + GND + GND + GND + GND + Serial Data + GND + GND + Serial Data + GND + GND + GND + GND + VCC + VCC + VCC + VCC + VCC + VCC + RX Strobe + RX Strobe + Clock + Clock + TX Strobe + TX Strobe + Clock + Clock + Yellow LED + 30/20m LPF + 60/40m LPF + 80m LPF + 160m LPF + Red LED + 6m LPF (Bypass) + 12/10m LPF + 17/15m LPF + TX 1 + TX 2 + TX 3 + T/R Relay + Yellow LED + 13MHz HPF + 20MHz HPF + 6M Preamp + 9.5MHz HPF + 6.5MHz HPF + 1.5MHz HPF + XVTR RX In + RX 2 In + RX 1 In + RX 1 Out + Bypass + 20dB Attenuator + 10dB Attenuator + Red LED + 1 @@ -192,26 +192,26 @@ - 2 - 3 - 4 - 5 - 6 - 7 - 8 - 9 - 10 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 20 + 19 + 18 + 17 + 16 + 15 + 14 + 13 + 12 + 11 + 1 @@ -235,26 +235,26 @@ - 2 - 3 - 4 - 5 - 6 - 7 - 8 - 9 - 10 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 20 + 19 + 18 + 17 + 16 + 15 + 14 + 13 + 12 + 11 + 1 @@ -278,26 +278,26 @@ - 2 - 3 - 4 - 5 - 6 - 7 - 8 - 9 - 10 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - VCC + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 20 + 19 + 18 + 17 + 16 + 15 + 14 + 13 + 12 + 11 + VCC diff --git a/svg/sdr-transceiver-hpsdr-ddc-122-88.svg b/svg/sdr-transceiver-hpsdr-ddc-122-88.svg index 796dabf3f..c73591343 100644 --- a/svg/sdr-transceiver-hpsdr-ddc-122-88.svg +++ b/svg/sdr-transceiver-hpsdr-ddc-122-88.svg @@ -10,21 +10,21 @@ - ADC interface - FIR ↓ 2 - I - Q - 122.88 MSPS 24 bits + ADC interface + FIR ↓ 2 + I + Q + 122.88 MSPS 24 bits - CIC ↓ 160–1280 - complex multiplier - DDS - cos - -sin - 96–768 kSPS 32 bits + CIC ↓ 160–1280 + complex multiplier + DDS + cos + -sin + 96–768 kSPS 32 bits @@ -32,18 +32,18 @@ - Xilinx IP cores - custom IP cores - 122.88 MSPS 16 bits - 48–384 kSPS 24 bits + Xilinx IP cores + custom IP cores + 122.88 MSPS 16 bits + 48–384 kSPS 24 bits - FIFO - config register + FIFO + config register - CPU + CPU - status register + status register @@ -51,7 +51,7 @@ - from ADC + from ADC diff --git a/svg/sdr-transceiver-hpsdr-ddc.svg b/svg/sdr-transceiver-hpsdr-ddc.svg index f23e7d273..1073ae77f 100644 --- a/svg/sdr-transceiver-hpsdr-ddc.svg +++ b/svg/sdr-transceiver-hpsdr-ddc.svg @@ -10,45 +10,45 @@ - ADC interface - I - Q - 125 MSPS 24 bits + ADC interface + I + Q + 125 MSPS 24 bits - CIC ↓ 125–1000 + CIC ↓ 125–1000 - complex multiplier - DDS - cos - -sin - 125–1000 kSPS 32 bits + complex multiplier + DDS + cos + -sin + 125–1000 kSPS 32 bits - 120–960 kSPS 24 bits + 120–960 kSPS 24 bits - Xilinx IP cores - custom IP cores - 125 MSPS 14 bits - FIR ↓ 5/2 + Xilinx IP cores + custom IP cores + 125 MSPS 14 bits + FIR ↓ 5/2 - FIR ↓ 25/24 - 48–384 kSPS 24 bits + FIR ↓ 25/24 + 48–384 kSPS 24 bits - FIFO - config register + FIFO + config register - CPU + CPU - status register + status register @@ -58,5 +58,5 @@ - from ADC + from ADC diff --git a/svg/sdr-transceiver-hpsdr-duc-122-88.svg b/svg/sdr-transceiver-hpsdr-duc-122-88.svg index eb95fae72..97ce53cd9 100644 --- a/svg/sdr-transceiver-hpsdr-duc-122-88.svg +++ b/svg/sdr-transceiver-hpsdr-duc-122-88.svg @@ -9,30 +9,30 @@ - DAC interface + DAC interface - I - Q - 122.88 MSPS 24 bits + I + Q + 122.88 MSPS 24 bits - CIC ↑ 1280 - complex multiplier - DDS - cos - sin - 48 kSPS 16 bits - 122.88 MSPS 14 bits - FIFO + CIC ↑ 1280 + complex multiplier + DDS + cos + sin + 48 kSPS 16 bits + 122.88 MSPS 14 bits + FIFO - config register + config register - CPU + CPU - status register + status register @@ -40,15 +40,15 @@ - FIR ↑ 2 + FIR ↑ 2 - 96 kSPS 24 bits + 96 kSPS 24 bits - Xilinx IP cores - custom IP cores - to DAC + Xilinx IP cores + custom IP cores + to DAC diff --git a/svg/sdr-transceiver-hpsdr-duc.svg b/svg/sdr-transceiver-hpsdr-duc.svg index 8c4f9b03c..65aafdafe 100644 --- a/svg/sdr-transceiver-hpsdr-duc.svg +++ b/svg/sdr-transceiver-hpsdr-duc.svg @@ -10,33 +10,33 @@ - DAC interface + DAC interface - I - Q - 125 MSPS 24 bits + I + Q + 125 MSPS 24 bits - CIC ↑ 1250 + CIC ↑ 1250 - complex multiplier - DDS - cos - sin - 48 kSPS 16 bits - 100 kSPS 24 bits - 125 MSPS 14 bits - FIFO + complex multiplier + DDS + cos + sin + 48 kSPS 16 bits + 100 kSPS 24 bits + 125 MSPS 14 bits + FIFO - config register + config register - CPU + CPU - status register + status register @@ -44,18 +44,18 @@ - FIR ↑ 2 + FIR ↑ 2 - 96 kSPS 24 bits + 96 kSPS 24 bits - FIR ↑ 25/24 + FIR ↑ 25/24 - Xilinx IP cores - custom IP cores - to DAC + Xilinx IP cores + custom IP cores + to DAC diff --git a/svg/sdr-transceiver-hpsdr-e1-pins.svg b/svg/sdr-transceiver-hpsdr-e1-pins.svg index 24cb68e77..1e886535a 100644 --- a/svg/sdr-transceiver-hpsdr-e1-pins.svg +++ b/svg/sdr-transceiver-hpsdr-e1-pins.svg @@ -1,50 +1,50 @@ - GND - GND - NC - NC - NC - NC - NC - NC - DIO7_N - DIO6_N - DIO5_N - DIO4_N - DIO3_N - DIO2_N - DIO1_N - DIO0_N - DIO7_P - DIO6_P - DIO5_P - DIO4_P - DIO3_P - DIO2_P - DIO1_P - DIO0_P - +3V3 - +3V3 - PTT, Out - Preamp, Out - 10 dB Attenuator, Out - TX Strobe, Out / ADCLRC, In - RX Strobe, Out / DACDAT, Out - Clock, Out / ADCDAT, In - Serial Data, Out / BCLK, In - 4 × 8-bit shift regs or I2S codec - PTT, In - Dash, In - Dot, In - GPS PPS, In - Connector E1 - Hermes Ctrl 1, Out - Hermes Ctrl 2, Out - Hermes Ctrl 3, Out - Hermes Ctrl 4, Out - 20 dB Attenuator, Out + GND + GND + NC + NC + NC + NC + NC + NC + DIO7_N + DIO6_N + DIO5_N + DIO4_N + DIO3_N + DIO2_N + DIO1_N + DIO0_N + DIO7_P + DIO6_P + DIO5_P + DIO4_P + DIO3_P + DIO2_P + DIO1_P + DIO0_P + +3V3 + +3V3 + PTT, Out + Preamp, Out + 10 dB Attenuator, Out + TX Strobe, Out / ADCLRC, In + RX Strobe, Out / DACDAT, Out + Clock, Out / ADCDAT, In + Serial Data, Out / BCLK, In + 4 × 8-bit shift regs or I2S codec + PTT, In + Dash, In + Dot, In + GPS PPS, In + Connector E1 + Hermes Ctrl 1, Out + Hermes Ctrl 2, Out + Hermes Ctrl 3, Out + Hermes Ctrl 4, Out + 20 dB Attenuator, Out diff --git a/svg/sdr-transceiver-wide.svg b/svg/sdr-transceiver-wide.svg index bc7a3f93f..7b79e1d9a 100644 --- a/svg/sdr-transceiver-wide.svg +++ b/svg/sdr-transceiver-wide.svg @@ -5,64 +5,64 @@ - ADC interface - FIR ↓ 2 + ADC interface + FIR ↓ 2 - I - Q - 125 MSPS 14 bits - CPU + I + Q + 125 MSPS 14 bits + CPU - from ADC - 125 MSPS 24 bits + from ADC + 125 MSPS 24 bits - DAC interface - CIC ↑ 25–3125 - FIR ↑ 2 + DAC interface + CIC ↑ 25–3125 + FIR ↑ 2 - to DAC + to DAC - 125 MSPS 24 bits - 125 MSPS 14 bits - I - Q + 125 MSPS 24 bits + 125 MSPS 14 bits + I + Q - CIC ↓ 25–3125 + CIC ↓ 25–3125 - complex multiplier + complex multiplier - DDS + DDS - cos - -sin + cos + -sin - complex multiplier + complex multiplier - DDS + DDS - cos - sin + cos + sin - 20–2500 kSPS 24 bits - 40–5000 kSPS 24 bits + 20–2500 kSPS 24 bits + 40–5000 kSPS 24 bits - to E1 + to E1 diff --git a/svg/sdr-transceiver.svg b/svg/sdr-transceiver.svg index 5bfe2aad6..2e05b2b75 100644 --- a/svg/sdr-transceiver.svg +++ b/svg/sdr-transceiver.svg @@ -5,106 +5,106 @@ - ADC interface - FIR ↓ 2 + ADC interface + FIR ↓ 2 - I - Q - 125 MSPS 14 bits - CPU + I + Q + 125 MSPS 14 bits + CPU - from IN1 - 125 MSPS 24 bits + from IN1 + 125 MSPS 24 bits - DAC interface - CIC ↑ 50–3125 - FIR ↑ 2 + DAC interface + CIC ↑ 50–3125 + FIR ↑ 2 - to OUT1 + to OUT1 - 125 MSPS 24 bits - 125 MSPS 14 bits - I - Q + 125 MSPS 24 bits + 125 MSPS 14 bits + I + Q - CIC ↓ 50–3125 + CIC ↓ 50–3125 - complex multiplier + complex multiplier - DDS + DDS - cos - -sin + cos + -sin - complex multiplier + complex multiplier - DDS + DDS - cos - sin + cos + sin - 20–1250 kSPS 24 bits - 40–2500 kSPS 24 bits - ADC interface - FIR ↓ 2 + 20–1250 kSPS 24 bits + 40–2500 kSPS 24 bits + ADC interface + FIR ↓ 2 - I - Q + I + Q - from IN2 - 125 MSPS 24 bits + from IN2 + 125 MSPS 24 bits - DAC interface - CIC ↑ 50–3125 - FIR ↑ 2 + DAC interface + CIC ↑ 50–3125 + FIR ↑ 2 - to OUT2 + to OUT2 - 125 MSPS 24 bits - I - Q + 125 MSPS 24 bits + I + Q - CIC ↓ 50–3125 + CIC ↓ 50–3125 - complex multiplier + complex multiplier - DDS + DDS - cos - -sin + cos + -sin - complex multiplier + complex multiplier - DDS + DDS - cos - sin + cos + sin @@ -113,12 +113,12 @@ - 20–1250 kSPS 24 bits - 40–2500 kSPS 24 bits - 125 MSPS 14 bits + 20–1250 kSPS 24 bits + 40–2500 kSPS 24 bits + 125 MSPS 14 bits - 125 MSPS 14 bits + 125 MSPS 14 bits - to E1 + to E1 diff --git a/svg/vna-122-88.svg b/svg/vna-122-88.svg index 3cc7f267f..ffd2f8b91 100644 --- a/svg/vna-122-88.svg +++ b/svg/vna-122-88.svg @@ -5,60 +5,60 @@ - I - Q - 122.88 MSPS 16 bits - 122.88 MSPS 24 bits + I + Q + 122.88 MSPS 16 bits + 122.88 MSPS 24 bits - complex multiplier + complex multiplier - CIC ↓ 2560 - FIFO - CPU - 48 kSPS 32 bits + CIC ↓ 2560 + FIFO + CPU + 48 kSPS 32 bits - cos - -sin + cos + -sin - from ADC + from ADC - FIFO + FIFO - interpolator + interpolator - DDS + DDS - to DAC + to DAC - I - Q + I + Q - complex multiplier + complex multiplier - CIC ↓ 2560 - FIFO + CIC ↓ 2560 + FIFO - from ADC + from ADC - cos - -sin + cos + -sin diff --git a/svg/vna.svg b/svg/vna.svg index d7a4fe065..6842703db 100644 --- a/svg/vna.svg +++ b/svg/vna.svg @@ -5,60 +5,60 @@ - I - Q - 125 MSPS 14 bits - 125 MSPS 24 bits + I + Q + 125 MSPS 14 bits + 125 MSPS 24 bits - complex multiplier + complex multiplier - CIC ↓ 2500 - FIFO - CPU - 50 kSPS 32 bits + CIC ↓ 2500 + FIFO + CPU + 50 kSPS 32 bits - cos - -sin + cos + -sin - from ADC + from ADC - FIFO + FIFO - interpolator + interpolator - DDS + DDS - to DAC + to DAC - I - Q + I + Q - complex multiplier + complex multiplier - CIC ↓ 2500 - FIFO + CIC ↓ 2500 + FIFO - from ADC + from ADC - cos - -sin + cos + -sin