- VHDL source: psi_common_sp_ram_be
- Testbench source: N.A
This component implements a single port RAM with byte enables. The RAM is described in a way that it utilizes RAM resources (Block-RAM and Distributed-RAM) available in FPGAs with commonly used tools.
The RAM is a synchronous RAM, so data is available at the read port one clock cycle after applying the address.
The RAM behavior (read-before-write or write-before-read) can be selected. This allows efficiently implementing RAMs for different technologies (some technologies implement one, some the other behavior).
| Name | type | Description |
|---|---|---|
| depth_g | positive | memory depth in sample |
| width_g | positive | data width in bit |
| ram_behavior_g | string | "rbw" = read-before-write, "wbr" = write-before-read |
| Signal | Direction | Width | Description |
|---|---|---|---|
| clk_i | I | 1 | Clock |
| addr_i | I | log2(Depth) | Access address |
| be_i | I | 1 | Byte enables (Be[0] corresponds do Din[7:0]) |
| wr_i | I | Width_g/8 | Write enables (active enable) |
| dat_i | I | Width_g | Write data |
| dat_o | O | Width_g | Read data |