Tofino SPI EEPROM Read/Write Size

[CommitThis]

Hello! Good to see that the SDE has been (or is in the process of being) open sourced.

So we (APS Networks) recently came across an issue with verifying the contents of the attached SPI EEPROM for (I think) PCIe link training or something similar. It appears that using the SPI functions in the lld module are set up for a 2-byte address space. However:

• In our later systems we have a 1Mbit part attached (I'm not sure how much this matters); and,
• The register map uses three bytes to control the target address; and,
• The SPI functions populate bytes 0 and 1 of these registers with the least significant second byte plus one and the least significant byte respectively; meaning that,
• The most significant byte in the target address register ends up being the second least significant address byte; and,
• The middle byte in the target address register ends up being the least significant byte of the intended address.

The consequence of this is that we were essentially getting garbage from an EEPROM dump using the aforementioned functions. We have copied and modified the code from the SDE to at least one of our BSPs, but if it is true that it was always intended to be three byte addressing irrespective of the supplied EEPROM part, then I could produce a PR for review.

Edit: So it may not be the case that, underneath the hood, this is not what happens with the registers, but the point is illustrative and modifying (at least) the address buffer to be three bytes and bit shifted accordingly addresses the issue.

[rrao-bfn]

Please note below define in lld_spi_if.h.
Modifications to support 1Mbit part should be fine.
Please ensure changes are backward compatible with 512 Kbits part.

/* SPI EEPROM constants /
#define BF_SPI_EEPROM_SIZE (512 * 1024 / 8) _/ 512 Kbits part */*_
#define BF_SPI_EEPROM_WR_SIZE 4 / write 4 bytes at a time /
#define BF_SPI_EEPROM_RD_CMD_SIZE
2 / bytes to write to issue a eeprom read
/
#define BF_SPI_EEPROM_RD_SIZE 4 / write 4 bytes at a time */