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| 1 | +/* Copyright (C) 2024 Povilas Kanapickas <povilas@radix.lt> |
| 2 | +
|
| 3 | + Distributed under the Boost Software License, Version 1.0. |
| 4 | + (See accompanying file LICENSE_1_0.txt or copy at |
| 5 | + http://www.boost.org/LICENSE_1_0.txt) |
| 6 | +*/ |
| 7 | + |
| 8 | +#ifndef LIBSIMDPP_SIMDPP_ALGORITHM_BITONIC_SORT |
| 9 | +#define LIBSIMDPP_SIMDPP_ALGORITHM_BITONIC_SORT |
| 10 | + |
| 11 | +#include <simdpp/simd.h> |
| 12 | + |
| 13 | +namespace simdpp { |
| 14 | +namespace SIMDPP_ARCH_NAMESPACE { |
| 15 | + |
| 16 | +namespace detail { |
| 17 | + |
| 18 | +template<unsigned N, class T> |
| 19 | +SIMDPP_INL T sort_4lane_2el_asc_2el_dec(const any_vec32<N,T>& a) |
| 20 | +{ |
| 21 | + auto& aw = a.wrapped(); |
| 22 | + |
| 23 | + T swapped = permute4<1, 0, 3, 2>(aw); |
| 24 | + |
| 25 | + T res_min = min(aw, swapped); |
| 26 | + T res_max = max(aw, swapped); |
| 27 | + |
| 28 | + return shuffle4x2<1, 4, 7, 2>(res_min, res_max); |
| 29 | +} |
| 30 | + |
| 31 | +template<unsigned N, class T> |
| 32 | +SIMDPP_INL T sort_4lane_2el_asc_2el_asc(const any_vec32<N,T>& a) |
| 33 | +{ |
| 34 | + auto& aw = a.wrapped(); |
| 35 | + |
| 36 | + T swapped = permute4<1, 0, 3, 2>(aw); |
| 37 | + |
| 38 | + T res_min = min(aw, swapped); |
| 39 | + T res_max = max(aw, swapped); |
| 40 | + |
| 41 | + return shuffle4x2<1, 4, 2, 7>(res_min, res_max); |
| 42 | +} |
| 43 | + |
| 44 | +template<unsigned N, class T> |
| 45 | +SIMDPP_INL T sort_4lane_2el_dec_2el_dec(const any_vec32<N,T>& a) |
| 46 | +{ |
| 47 | + auto& aw = a.wrapped(); |
| 48 | + |
| 49 | + T swapped = permute4<1, 0, 3, 2>(aw); |
| 50 | + |
| 51 | + T res_max = max(aw, swapped); |
| 52 | + T res_min = min(aw, swapped); |
| 53 | + |
| 54 | + return shuffle4x2<1, 4, 2, 7>(res_max, res_min); |
| 55 | +} |
| 56 | + |
| 57 | +template<unsigned N, class T> |
| 58 | +SIMDPP_INL T sort_4lane_corresponding_2el_asc(const any_vec32<N,T>& a) |
| 59 | +{ |
| 60 | + auto& aw = a.wrapped(); |
| 61 | + T swapped = permute4<2, 3, 0, 1>(aw); |
| 62 | + |
| 63 | + T res_min = min(aw, swapped); |
| 64 | + T res_max = max(aw, swapped); |
| 65 | + |
| 66 | + return shuffle4x2<0, 1, 4, 5>(res_min, res_max); |
| 67 | +} |
| 68 | + |
| 69 | +template<unsigned N, class T> |
| 70 | +SIMDPP_INL T sort_4lane_corresponding_2el_dec(const any_vec32<N,T>& a) |
| 71 | +{ |
| 72 | + auto& aw = a.wrapped(); |
| 73 | + T swapped = permute4<2, 3, 0, 1>(aw); |
| 74 | + |
| 75 | + T res_max = max(aw, swapped); |
| 76 | + T res_min = min(aw, swapped); |
| 77 | + |
| 78 | + return shuffle4x2<0, 1, 4, 5>(res_max, res_min); |
| 79 | +} |
| 80 | + |
| 81 | +template<unsigned N, class T> |
| 82 | +SIMDPP_INL T sort_8lane_corresponding_4el_asc(const any_vec32<N,T>& a) |
| 83 | +{ |
| 84 | + auto& aw = a.wrapped(); |
| 85 | + T lo = shuffle1_128<0, 0>(aw, aw); |
| 86 | + T hi = shuffle1_128<1, 1>(aw, aw); |
| 87 | + |
| 88 | + T res_min = min(lo, hi); |
| 89 | + T res_max = max(lo, hi); |
| 90 | + |
| 91 | + return shuffle1_128<0, 0>(res_min, res_max); |
| 92 | +} |
| 93 | + |
| 94 | +template<unsigned N, class T> |
| 95 | +SIMDPP_INL T sort_8lane_corresponding_4el_dec(const any_vec32<N,T>& a) |
| 96 | +{ |
| 97 | + auto& aw = a.wrapped(); |
| 98 | + T lo = shuffle1_128<0, 0>(aw, aw); |
| 99 | + T hi = shuffle1_128<1, 1>(aw, aw); |
| 100 | + |
| 101 | + T res_max = max(lo, hi); |
| 102 | + T res_min = min(lo, hi); |
| 103 | + |
| 104 | + return shuffle1_128<0, 0>(res_max, res_min); |
| 105 | +} |
| 106 | + |
| 107 | +template<unsigned N, class T> |
| 108 | +SIMDPP_INL T reverse_8lane_top4(const any_vec32<N,T>& a) |
| 109 | +{ |
| 110 | + auto& aw = a.wrapped(); |
| 111 | + |
| 112 | + T reversed = permute4<3, 2, 1, 0>(aw); |
| 113 | + |
| 114 | + return shuffle1_128<0, 1>(aw, reversed); |
| 115 | +} |
| 116 | + |
| 117 | +template<unsigned N, class T> |
| 118 | +SIMDPP_INL T reverse_8lane_bottom4(const any_vec32<N,T>& a) |
| 119 | +{ |
| 120 | + auto& aw = a.wrapped(); |
| 121 | + |
| 122 | + T reversed = permute4<3, 2, 1, 0>(aw); |
| 123 | + |
| 124 | + return shuffle1_128<0, 1>(reversed, aw); |
| 125 | +} |
| 126 | + |
| 127 | +template<unsigned N, class T> |
| 128 | +SIMDPP_INL T sort_8lane_4el_asc_4el_dec(const any_vec32<N,T>& a) |
| 129 | +{ |
| 130 | + auto& aw = a.wrapped(); |
| 131 | + |
| 132 | + T step1_res = sort_4lane_2el_asc_2el_dec(aw); |
| 133 | + T step2_res = sort_4lane_corresponding_2el_asc(step1_res); |
| 134 | + T step3_res = sort_4lane_2el_asc_2el_asc(step2_res); |
| 135 | + |
| 136 | + return reverse_8lane_top4(step3_res); |
| 137 | +} |
| 138 | + |
| 139 | +template<unsigned N, class T> |
| 140 | +SIMDPP_INL T sort_8lane_4el_dec_4el_asc(const any_vec32<N,T>& a) |
| 141 | +{ |
| 142 | + auto& aw = a.wrapped(); |
| 143 | + |
| 144 | + T step1_res = sort_4lane_2el_asc_2el_dec(aw); |
| 145 | + T step2_res = sort_4lane_corresponding_2el_asc(step1_res); |
| 146 | + T step3_res = sort_4lane_2el_asc_2el_asc(step2_res); |
| 147 | + |
| 148 | + return reverse_8lane_bottom4(step3_res); |
| 149 | +} |
| 150 | + |
| 151 | +template<unsigned N, class T> |
| 152 | +SIMDPP_INL T bitonic_sort_8lane_finalize_asc(const any_vec32<N, T>& a) |
| 153 | +{ |
| 154 | + auto& aw = a.wrapped(); |
| 155 | + |
| 156 | + T step1_res = sort_8lane_corresponding_4el_asc(aw); |
| 157 | + T step2_res = sort_4lane_corresponding_2el_asc(step1_res); |
| 158 | + return sort_4lane_2el_asc_2el_asc(step2_res); |
| 159 | +} |
| 160 | + |
| 161 | +template<unsigned N, class T> |
| 162 | +SIMDPP_INL T bitonic_sort_8lane_finalize_dec(const any_vec32<N, T>& a) |
| 163 | +{ |
| 164 | + auto& aw = a.wrapped(); |
| 165 | + |
| 166 | + T step1_res = sort_8lane_corresponding_4el_dec(aw); |
| 167 | + T step2_res = sort_4lane_corresponding_2el_dec(step1_res); |
| 168 | + return sort_4lane_2el_dec_2el_dec(step2_res); |
| 169 | +} |
| 170 | + |
| 171 | +} // namespace detail |
| 172 | + |
| 173 | +/** Sorts data in the given SIMD registers in increasing order. Sort is not stable. |
| 174 | +*/ |
| 175 | +template<class T> |
| 176 | +void bitonic_sort_asc(any_vec32<8,T>& a0) |
| 177 | +{ |
| 178 | + auto r = detail::sort_8lane_4el_asc_4el_dec(a0.wrapped()); |
| 179 | + a0.wrapped() = detail::bitonic_sort_8lane_finalize_asc(r); |
| 180 | +} |
| 181 | + |
| 182 | +template<class T> |
| 183 | +void bitonic_sort_dec(any_vec32<8,T>& a0) |
| 184 | +{ |
| 185 | + auto r = detail::sort_8lane_4el_dec_4el_asc(a0.wrapped()); |
| 186 | + a0.wrapped() = detail::bitonic_sort_8lane_finalize_dec(r); |
| 187 | +} |
| 188 | + |
| 189 | + |
| 190 | +template<class T> |
| 191 | +void bitonic_sort_asc(any_vec32<8,T>& a0, any_vec32<8,T>& a1) |
| 192 | +{ |
| 193 | + auto r0 = a0.wrapped(); |
| 194 | + auto r1 = a1.wrapped(); |
| 195 | + r0 = detail::sort_8lane_4el_asc_4el_dec(r0); |
| 196 | + r0 = detail::bitonic_sort_8lane_finalize_asc(r0); |
| 197 | + r1 = detail::sort_8lane_4el_asc_4el_dec(r1); |
| 198 | + r1 = detail::bitonic_sort_8lane_finalize_dec(r1); |
| 199 | + |
| 200 | + T res_max = max(r0, r1); |
| 201 | + T res_min = min(r0, r1); |
| 202 | + |
| 203 | + r0 = detail::bitonic_sort_8lane_finalize_asc(res_min); |
| 204 | + r1 = detail::bitonic_sort_8lane_finalize_asc(res_max); |
| 205 | + a0.wrapped() = r0; |
| 206 | + a1.wrapped() = r1; |
| 207 | +} |
| 208 | + |
| 209 | +template<class T> |
| 210 | +void bitonic_sort_dec(any_vec32<8,T>& a0, any_vec32<8,T>& a1) |
| 211 | +{ |
| 212 | + auto r0 = a0.wrapped(); |
| 213 | + auto r1 = a1.wrapped(); |
| 214 | + r0 = detail::sort_8lane_4el_dec_4el_asc(r0); |
| 215 | + r0 = detail::bitonic_sort_8lane_finalize_dec(r0); |
| 216 | + r1 = detail::sort_8lane_4el_dec_4el_asc(r1); |
| 217 | + r1 = detail::bitonic_sort_8lane_finalize_asc(r1); |
| 218 | + |
| 219 | + T res_max = max(r0, r1); |
| 220 | + T res_min = min(r0, r1); |
| 221 | + |
| 222 | + r0 = detail::bitonic_sort_8lane_finalize_dec(res_max); |
| 223 | + r1 = detail::bitonic_sort_8lane_finalize_dec(res_min); |
| 224 | + a0.wrapped() = r0; |
| 225 | + a1.wrapped() = r1; |
| 226 | +} |
| 227 | + |
| 228 | +} // namespace simdpp |
| 229 | +} // namespace SIMDPP_ARCH_NAMESPACE |
| 230 | + |
| 231 | +#endif // LIBSIMDPP_SIMDPP_ALGORITHM_BITONIC_SORT |
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