From 71baa6d4a83b383a23c65fe444e55b75a15f279a Mon Sep 17 00:00:00 2001 From: muhammadhamza15 Date: Wed, 27 Nov 2024 18:46:32 +0500 Subject: [PATCH] fixing typo in PLL specify block --- models_internal/verilog/PLL.v | 12 ++++++------ models_internal/verilog/inc/PLL.inc.v | 12 ++++++------ 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/models_internal/verilog/PLL.v b/models_internal/verilog/PLL.v index fabde84..a415a04 100644 --- a/models_internal/verilog/PLL.v +++ b/models_internal/verilog/PLL.v @@ -25,7 +25,7 @@ module PLL #( output LOCK // PLL lock signal ); -localparam FAST_LOCK = 0; // Reduce lock time + localparam FAST_LOCK = 0; // Reduce lock time localparam real REF_MAX_PERIOD = PLL_MULT_FRAC ? 100000: 200000; //10 MHz or 5 MHz localparam real REF_MIN_PERIOD = 833.33 ; //1200 MHz @@ -208,7 +208,7 @@ localparam FAST_LOCK = 0; // Reduce lock time end end - + `ifndef SYNTHESIS `ifdef TIMED_SIM specparam T1 = 5; @@ -222,10 +222,10 @@ localparam FAST_LOCK = 0; // Reduce lock time (CLK_IN => CLK_OUT_DIV4) = (T1); (CLK_IN => FAST_CLK) = (T1); - (negedge CLK_IN => (LOCKED +: 0)) = (T1); - (negedge PLL_EN => (LOCKED +: 0)) = (T1); - (posedge CLK_IN => (LOCKED +: 0)) = (T1); - (posedge PLL_EN => (LOCKED +: 0)) = (T1); + (negedge CLK_IN => (LOCK +: 0)) = (T1); + (negedge PLL_EN => (LOCK +: 0)) = (T1); + (posedge CLK_IN => (LOCK +: 0)) = (T1); + (posedge PLL_EN => (LOCK +: 0)) = (T1); $setuphold (posedge CLK_IN, negedge PLL_EN, T2, notifier); $setuphold (posedge CLK_IN, posedge PLL_EN, T2, notifier); diff --git a/models_internal/verilog/inc/PLL.inc.v b/models_internal/verilog/inc/PLL.inc.v index f636ff3..63c0a8c 100644 --- a/models_internal/verilog/inc/PLL.inc.v +++ b/models_internal/verilog/inc/PLL.inc.v @@ -1,5 +1,5 @@ -localparam FAST_LOCK = 0; // Reduce lock time + localparam FAST_LOCK = 0; // Reduce lock time localparam real REF_MAX_PERIOD = PLL_MULT_FRAC ? 100000: 200000; //10 MHz or 5 MHz localparam real REF_MIN_PERIOD = 833.33 ; //1200 MHz @@ -182,7 +182,7 @@ localparam FAST_LOCK = 0; // Reduce lock time end end - + `ifndef SYNTHESIS `ifdef TIMED_SIM specparam T1 = 5; @@ -196,10 +196,10 @@ localparam FAST_LOCK = 0; // Reduce lock time (CLK_IN => CLK_OUT_DIV4) = (T1); (CLK_IN => FAST_CLK) = (T1); - (negedge CLK_IN => (LOCKED +: 0)) = (T1); - (negedge PLL_EN => (LOCKED +: 0)) = (T1); - (posedge CLK_IN => (LOCKED +: 0)) = (T1); - (posedge PLL_EN => (LOCKED +: 0)) = (T1); + (negedge CLK_IN => (LOCK +: 0)) = (T1); + (negedge PLL_EN => (LOCK +: 0)) = (T1); + (posedge CLK_IN => (LOCK +: 0)) = (T1); + (posedge PLL_EN => (LOCK +: 0)) = (T1); $setuphold (posedge CLK_IN, negedge PLL_EN, T2, notifier); $setuphold (posedge CLK_IN, posedge PLL_EN, T2, notifier);