Merge pull request #78 from muhammadhamza15/mhamza_dev

Mhamza dev
os-fpga · Nov 26, 2024 · 750bfa3 · 750bfa3
2 parents d31c748 + 88c5bc0
commit 750bfa3
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/models_internal/verilog/tb/DLY_SEL_DECODER_tb.v b/models_internal/verilog/tb/DLY_SEL_DECODER_tb.v
@@ -31,7 +31,7 @@ module DLY_SEL_DECODER_tb;
 
 	integer error=0;
 
-  DLY_SEL_DCODER  DLY_SEL_DCODER_inst (
+  DLY_SEL_DECODER  DLY_SEL_DECODER_inst (
     .DLY_LOAD(DLY_LOAD),
     .DLY_ADJ(DLY_ADJ),
     .DLY_INCDEC(DLY_INCDEC),