Merge pull request #67 from muhammadhamza15/mhamza_dev

Name correction of dly sel decoder

models_internal/verilog/DLY_SEL_DECODER.v

@@ -0,0 +1,89 @@
+`timescale 1ps/1ps
+`celldefine
+//
+// DLY_SEL_DECODER simulation model
+// Address Decoder
+//
+// Copyright (c) 2023 Rapid Silicon, Inc.  All rights reserved.
+//
+
+module DLY_SEL_DECODER (
+  input DLY_LOAD, // Delay load input
+  input DLY_ADJ, // Delay adjust input
+  input DLY_INCDEC, // Delay increment / decrement input
+  input [4:0] DLY_ADDR, // Input Address
+  output reg [2:0] DLY0_CNTRL, // Output Bus
+  output reg [2:0] DLY1_CNTRL, // Output Bus
+  output reg [2:0] DLY2_CNTRL, // Output Bus
+  output reg [2:0] DLY3_CNTRL, // Output Bus
+  output reg [2:0] DLY4_CNTRL, // Output Bus
+  output reg [2:0] DLY5_CNTRL, // Output Bus
+  output reg [2:0] DLY6_CNTRL, // Output Bus
+  output reg [2:0] DLY7_CNTRL, // Output Bus
+  output reg [2:0] DLY8_CNTRL, // Output Bus
+  output reg [2:0] DLY9_CNTRL, // Output Bus
+  output reg [2:0] DLY10_CNTRL, // Output Bus
+  output reg [2:0] DLY11_CNTRL, // Output Bus
+  output reg [2:0] DLY12_CNTRL, // Output Bus
+  output reg [2:0] DLY13_CNTRL, // Output Bus
+  output reg [2:0] DLY14_CNTRL, // Output Bus
+  output reg [2:0] DLY15_CNTRL, // Output Bus
+  output reg [2:0] DLY16_CNTRL, // Output Bus
+  output reg [2:0] DLY17_CNTRL, // Output Bus
+  output reg [2:0] DLY18_CNTRL, // Output Bus
+  output reg [2:0] DLY19_CNTRL // Output Bus
+);
+
+
+always @(*) 
+begin
+  DLY0_CNTRL  = 3'b000;
+  DLY1_CNTRL  = 3'b000;
+  DLY2_CNTRL  = 3'b000;
+  DLY3_CNTRL  = 3'b000;
+  DLY4_CNTRL  = 3'b000;
+  DLY5_CNTRL  = 3'b000;
+  DLY6_CNTRL  = 3'b000;
+  DLY7_CNTRL  = 3'b000;
+  DLY8_CNTRL  = 3'b000;
+  DLY9_CNTRL  = 3'b000;
+  DLY10_CNTRL = 3'b000;
+  DLY11_CNTRL = 3'b000;
+  DLY12_CNTRL = 3'b000;
+  DLY13_CNTRL = 3'b000;
+  DLY14_CNTRL = 3'b000;
+  DLY15_CNTRL = 3'b000;
+  DLY16_CNTRL = 3'b000;
+  DLY17_CNTRL = 3'b000;
+  DLY18_CNTRL = 3'b000;
+  DLY19_CNTRL = 3'b000;
+
+  case(DLY_ADDR)
+    5'd0:  DLY0_CNTRL  = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
+    5'd1:  DLY1_CNTRL  = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
+    5'd2:  DLY2_CNTRL  = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
+    5'd3:  DLY3_CNTRL  = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
+    5'd4:  DLY4_CNTRL  = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
+    5'd5:  DLY5_CNTRL  = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
+    5'd6:  DLY6_CNTRL  = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
+    5'd7:  DLY7_CNTRL  = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
+    5'd8:  DLY8_CNTRL  = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
+    5'd9:  DLY9_CNTRL  = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
+    5'd10: DLY10_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
+    5'd11: DLY11_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
+    5'd12: DLY12_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
+    5'd13: DLY13_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
+    5'd14: DLY14_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
+    5'd15: DLY15_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
+    5'd16: DLY16_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
+    5'd17: DLY17_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
+    5'd18: DLY18_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
+    5'd19: DLY19_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
+
+  endcase
+
+end
+
+
+endmodule
+`endcelldefine

models_internal/verilog/tb/DLY_SEL_DECODER_tb.v

@@ -1,5 +1,5 @@
 
-module DLY_SEL_DCODER_tb;
+module DLY_SEL_DECODER_tb;
 
   // Parameters
 

models_internal/verilog_blackbox/cell_sim_blackbox.v

@@ -118,6 +118,42 @@ module DLY_SEL_DCODER (
 endmodule
 `endcelldefine
 //
+// DLY_SEL_DECODER black box model
+// Address Decoder
+//
+// Copyright (c) 2024 Rapid Silicon, Inc.  All rights reserved.
+//
+`celldefine
+(* blackbox *)
+module DLY_SEL_DECODER (
+  input logic DLY_LOAD,
+  input logic DLY_ADJ,
+  input logic DLY_INCDEC,
+  input logic [4:0] DLY_ADDR,
+  output reg [2:0] DLY0_CNTRL,
+  output reg [2:0] DLY1_CNTRL,
+  output reg [2:0] DLY2_CNTRL,
+  output reg [2:0] DLY3_CNTRL,
+  output reg [2:0] DLY4_CNTRL,
+  output reg [2:0] DLY5_CNTRL,
+  output reg [2:0] DLY6_CNTRL,
+  output reg [2:0] DLY7_CNTRL,
+  output reg [2:0] DLY8_CNTRL,
+  output reg [2:0] DLY9_CNTRL,
+  output reg [2:0] DLY10_CNTRL,
+  output reg [2:0] DLY11_CNTRL,
+  output reg [2:0] DLY12_CNTRL,
+  output reg [2:0] DLY13_CNTRL,
+  output reg [2:0] DLY14_CNTRL,
+  output reg [2:0] DLY15_CNTRL,
+  output reg [2:0] DLY16_CNTRL,
+  output reg [2:0] DLY17_CNTRL,
+  output reg [2:0] DLY18_CNTRL,
+  output reg [2:0] DLY19_CNTRL
+);
+endmodule
+`endcelldefine
+//
 // DLY_VALUE_MUX black box model
 // Multiplexer
 //

specs/DLY_SEL_DCODER.yaml → specs/DLY_SEL_DECODER.yaml

@@ -43,7 +43,7 @@
 #          - <enum_name>
 #
 # primitive name should match the filename root.
-name: DLY_SEL_DCODER
+name: DLY_SEL_DECODER
 desc: Address Decoder
 category: periphery
 timescale: 1ps/1ps