Merge pull request #5 from geochrist/main

Reformat blackbox models into original order
os-fpga · Feb 4, 2024 · 10bbe0b · 10bbe0b
2 parents 034cc75 + 0a62669
commit 10bbe0b
Showing 1 changed file with 57 additions and 57 deletions.
diff --git a/models_internal/verilog_blackbox/cell_sim_blackbox.v b/models_internal/verilog_blackbox/cell_sim_blackbox.v
@@ -254,44 +254,44 @@ module FIFO36K #(
 endmodule
 `endcelldefine
 //
-// I_BUF_DS black box model
-// input differential buffer
+// I_BUF black box model
+// Input buffer
 //
 // Copyright (c) 2024 Rapid Silicon, Inc.  All rights reserved.
 //
 `celldefine
 (* blackbox *)
-module I_BUF_DS #(
+module I_BUF #(
   parameter WEAK_KEEPER = "NONE" // Specify Pull-up/Pull-down on input (NONE/PULLUP/PULLDOWN)
 `ifdef RAPIDSILICON_INTERNAL
-  ,   parameter IOSTANDARD = "DEFAULT", // IO Standard
-  parameter DIFFERENTIAL_TERMINATION = "TRUE" // Enable differential termination
+  ,   parameter IOSTANDARD = "DEFAULT" // IO Standard
 `endif // RAPIDSILICON_INTERNAL
   ) (
-  input logic I_P,
-  input logic I_N,
+  input logic I,
   input logic EN,
-  output reg O
+  output logic O
 );
 endmodule
 `endcelldefine
 //
-// I_BUF black box model
-// Input buffer
+// I_BUF_DS black box model
+// input differential buffer
 //
 // Copyright (c) 2024 Rapid Silicon, Inc.  All rights reserved.
 //
 `celldefine
 (* blackbox *)
-module I_BUF #(
+module I_BUF_DS #(
   parameter WEAK_KEEPER = "NONE" // Specify Pull-up/Pull-down on input (NONE/PULLUP/PULLDOWN)
 `ifdef RAPIDSILICON_INTERNAL
-  ,   parameter IOSTANDARD = "DEFAULT" // IO Standard
+  ,   parameter IOSTANDARD = "DEFAULT", // IO Standard
+  parameter DIFFERENTIAL_TERMINATION = "TRUE" // Enable differential termination
 `endif // RAPIDSILICON_INTERNAL
   ) (
-  input logic I,
+  input logic I_P,
+  input logic I_N,
   input logic EN,
-  output logic O
+  output reg O
 );
 endmodule
 `endcelldefine
@@ -458,90 +458,90 @@ module LUT6 #(
 endmodule
 `endcelldefine
 //
-// O_BUF_DS black box model
-// Output differential buffer
+// O_BUF black box model
+// Output buffer
 //
 // Copyright (c) 2024 Rapid Silicon, Inc.  All rights reserved.
 //
 `celldefine
 (* blackbox *)
-module O_BUF_DS
+module O_BUF
 `ifdef RAPIDSILICON_INTERNAL
   #(
   parameter IOSTANDARD = "DEFAULT", // IO Standard
-  parameter DIFFERENTIAL_TERMINATION = "TRUE" // Enable differential termination
+  parameter DRIVE_STRENGTH = 2, // Drive strength in mA for LVCMOS standards
+  parameter SLEW_RATE = "SLOW" // Transition rate for LVCMOS standards
   )
 `endif // RAPIDSILICON_INTERNAL
   (
   input logic I,
-  output logic O_P,
-  output logic O_N
+  output logic O
 );
 endmodule
 `endcelldefine
 //
-// O_BUFT_DS black box model
-// Output differential tri-state buffer
+// O_BUFT black box model
+// Output tri-state buffer
 //
 // Copyright (c) 2024 Rapid Silicon, Inc.  All rights reserved.
 //
 `celldefine
 (* blackbox *)
-module O_BUFT_DS #(
+module O_BUFT #(
   parameter WEAK_KEEPER = "NONE" // Enable pull-up/pull-down on output (NONE/PULLUP/PULLDOWN)
 `ifdef RAPIDSILICON_INTERNAL
   ,   parameter IOSTANDARD = "DEFAULT", // IO Standard
-  parameter DIFFERENTIAL_TERMINATION = "TRUE" // Enable differential termination
+  parameter DRIVE_STRENGTH = 2, // Drive strength in mA for LVCMOS standards
+  parameter SLEW_RATE = "SLOW" // Transition rate for LVCMOS standards
 `endif // RAPIDSILICON_INTERNAL
   ) (
   input logic I,
   input logic T,
-  output logic O_P,
-  output logic O_N
+  output logic O
 );
 endmodule
 `endcelldefine
 //
-// O_BUFT black box model
-// Output tri-state buffer
+// O_BUFT_DS black box model
+// Output differential tri-state buffer
 //
 // Copyright (c) 2024 Rapid Silicon, Inc.  All rights reserved.
 //
 `celldefine
 (* blackbox *)
-module O_BUFT #(
+module O_BUFT_DS #(
   parameter WEAK_KEEPER = "NONE" // Enable pull-up/pull-down on output (NONE/PULLUP/PULLDOWN)
 `ifdef RAPIDSILICON_INTERNAL
   ,   parameter IOSTANDARD = "DEFAULT", // IO Standard
-  parameter DRIVE_STRENGTH = 2, // Drive strength in mA for LVCMOS standards
-  parameter SLEW_RATE = "SLOW" // Transition rate for LVCMOS standards
+  parameter DIFFERENTIAL_TERMINATION = "TRUE" // Enable differential termination
 `endif // RAPIDSILICON_INTERNAL
   ) (
   input logic I,
   input logic T,
-  output logic O
+  output logic O_P,
+  output logic O_N
 );
 endmodule
 `endcelldefine
 //
-// O_BUF black box model
-// Output buffer
+// O_BUF_DS black box model
+// Output differential buffer
 //
 // Copyright (c) 2024 Rapid Silicon, Inc.  All rights reserved.
 //
 `celldefine
 (* blackbox *)
-module O_BUF
+module O_BUF_DS
 `ifdef RAPIDSILICON_INTERNAL
   #(
   parameter IOSTANDARD = "DEFAULT", // IO Standard
-  parameter DRIVE_STRENGTH = 2, // Drive strength in mA for LVCMOS standards
-  parameter SLEW_RATE = "SLOW" // Transition rate for LVCMOS standards
+  parameter DIFFERENTIAL_TERMINATION = "TRUE" // Enable differential termination
   )
 `endif // RAPIDSILICON_INTERNAL
   (
   input logic I,
-  output logic O
+  output logic O_P,
+  output logic O_N
 );
 endmodule
 `endcelldefine
@@ -584,25 +584,6 @@ module O_DELAY #(
 endmodule
 `endcelldefine
 //
-// O_SERDES_CLK black box model
-// Output Serializer Clock
-//
-// Copyright (c) 2024 Rapid Silicon, Inc.  All rights reserved.
-//
-`celldefine
-(* blackbox *)
-module O_SERDES_CLK #(
-  parameter DATA_RATE = "SDR", // Single or double data rate (SDR/DDR)
-  parameter CLOCK_PHASE = 0 // Clock phase (0,90,180,270)
-  ) (
-  input logic CLK_EN,
-  output reg OUTPUT_CLK,
-  input logic PLL_LOCK,
-  input logic PLL_CLK
-);
-endmodule
-`endcelldefine
-//
 // O_SERDES black box model
 // Output Serializer
 //
@@ -629,6 +610,25 @@ module O_SERDES #(
 endmodule
 `endcelldefine
 //
+// O_SERDES_CLK black box model
+// Output Serializer Clock
+//
+// Copyright (c) 2024 Rapid Silicon, Inc.  All rights reserved.
+//
+`celldefine
+(* blackbox *)
+module O_SERDES_CLK #(
+  parameter DATA_RATE = "SDR", // Single or double data rate (SDR/DDR)
+  parameter CLOCK_PHASE = 0 // Clock phase (0,90,180,270)
+  ) (
+  input logic CLK_EN,
+  output reg OUTPUT_CLK,
+  input logic PLL_LOCK,
+  input logic PLL_CLK
+);
+endmodule
+`endcelldefine
+//
 // PLL black box model
 // Phase locked loop
 //