PLL_CLK handling for output primitives#2096

Merged

ravikiranchollangi merged 3 commits intomainfrom bug/EDA-3326/pll_clk_handling

Nov 18, 2024

+1-1

Commits on Nov 17, 2024

Updating yosys_verific_rs
behzadmehmood
committed

Commits on Nov 18, 2024

Embedding code to handle PLL_CLK signals on output primitives
behzadmehmood
committed
Merge branch 'main' of github.com:os-fpga/Raptor into bug/EDA-3326/pll_clk_handling
behzadmehmood
committed