Make sure data width is good (#2002)

* Make sure SERDES data with is good * Revert peer gearbox PEER_IS_ON setting * Port latest FOEDAG_rs and yosys_verific_rs
os-fpga · Sep 18, 2024 · 3cbde01 · 3cbde01
1 parent 1c3777f
commit 3cbde01
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Showing 6 changed files with 90 additions and 6 deletions.
diff --git a/FOEDAG_rs b/FOEDAG_rs
diff --git a/src/ConfigurationRaptor/CFGDeviceDatabase/Gemini/config_attributes.mapping.json b/src/ConfigurationRaptor/CFGDeviceDatabase/Gemini/config_attributes.mapping.json
@@ -438,7 +438,8 @@
       "g_boot_clock_resources = 0",
       "g_pin_resources = {}",
       "g_fabric_clock_resources = 0",
-      "g_pll_resources = []"
+      "g_pll_resources = []",
+      "g_gearbox_width = {}"
     ]
   },
   "__primary_validation__" : {
@@ -533,6 +534,7 @@
   "__secondary_validation__" : {
     "__seqeunce__" : [
       "__check_fabric_clock_resource__",
+      "__check_data_width_parameter__",
       "__check_data_rate_parameter__",
       "__check_dpa_mode_parameter__",
       "__check_clock_phase_parameter__",
@@ -546,6 +548,25 @@
         "pin_result = (__connectivity_count__ + g_fabric_clock_resources) <= MAX_FABRIC_CLOCK_RESOURCE"
       ]
     },
+    "__check_data_width_parameter__" : {
+      "__module__" : ["I_SERDES", "O_SERDES"],
+      "__parameter__" : ["WIDTH"],
+      "__equation__" : [
+        "import re",
+        "assert '__location__' in g_all_pins",
+        "m = re.search(r'H(P|R?)_(\\d?)(|_CC?)_(\\d+?)_(\\d\\d?)(P|N?)', '__location__')",
+        "assert m != None",
+        "pn = 'P' if m.group(6) == 'N' else 'N'",
+        "index = int(m.group(4)) & ~1",
+        "index += (1 if pn == 'N' else 0)",
+        "peer_location = 'H%s_%s%s_%d_%s%s' % (m.group(1), m.group(2), m.group(3), index, m.group(5), pn)",
+        "width = int('WIDTH')",
+        "pin_result = width >= 3 and width <= (10 if m.group(6) == 'P' else 5)",
+        "pin_result = pin_result and ((peer_location not in g_gearbox_width) or (g_gearbox_width[peer_location] <= 5 and width <=5))",
+        "g_gearbox_width['__location__' if pin_result else ''] = width",
+        "g_gearbox_width.pop('', None)"
+      ]
+    },
     "__check_data_rate_parameter__" : {
       "__module__" : ["I_SERDES", "O_SERDES", "O_SERDES_CLK"],
       "__parameter__" : ["DATA_RATE"],

diff --git a/src/ConfigurationRaptor/CFGDeviceDatabase/Virgo/config_attributes.mapping.json b/src/ConfigurationRaptor/CFGDeviceDatabase/Virgo/config_attributes.mapping.json
@@ -438,7 +438,8 @@
       "g_boot_clock_resources = 0",
       "g_pin_resources = {}",
       "g_fabric_clock_resources = 0",
-      "g_pll_resources = []"
+      "g_pll_resources = []",
+      "g_gearbox_width = {}"
     ]
   },
   "__primary_validation__" : {
@@ -533,6 +534,7 @@
   "__secondary_validation__" : {
     "__seqeunce__" : [
       "__check_fabric_clock_resource__",
+      "__check_data_width_parameter__",
       "__check_data_rate_parameter__",
       "__check_dpa_mode_parameter__",
       "__check_clock_phase_parameter__",
@@ -546,6 +548,25 @@
         "pin_result = (__connectivity_count__ + g_fabric_clock_resources) <= MAX_FABRIC_CLOCK_RESOURCE"
       ]
     },
+    "__check_data_width_parameter__" : {
+      "__module__" : ["I_SERDES", "O_SERDES"],
+      "__parameter__" : ["WIDTH"],
+      "__equation__" : [
+        "import re",
+        "assert '__location__' in g_all_pins",
+        "m = re.search(r'H(P|R?)_(\\d?)(|_CC?)_(\\d+?)_(\\d\\d?)(P|N?)', '__location__')",
+        "assert m != None",
+        "pn = 'P' if m.group(6) == 'N' else 'N'",
+        "index = int(m.group(4)) & ~1",
+        "index += (1 if pn == 'N' else 0)",
+        "peer_location = 'H%s_%s%s_%d_%s%s' % (m.group(1), m.group(2), m.group(3), index, m.group(5), pn)",
+        "width = int('WIDTH')",
+        "pin_result = width >= 3 and width <= (10 if m.group(6) == 'P' else 5)",
+        "pin_result = pin_result and ((peer_location not in g_gearbox_width) or (g_gearbox_width[peer_location] <= 5 and width <=5))",
+        "g_gearbox_width['__location__' if pin_result else ''] = width",
+        "g_gearbox_width.pop('', None)"
+      ]
+    },
     "__check_data_rate_parameter__" : {
       "__module__" : ["I_SERDES", "O_SERDES", "O_SERDES_CLK"],
       "__parameter__" : ["DATA_RATE"],

diff --git a/...gurationRaptor/CFGDeviceDatabase/Virgo/gemini_compact_10x8_config_attributes.mapping.json b/...gurationRaptor/CFGDeviceDatabase/Virgo/gemini_compact_10x8_config_attributes.mapping.json
@@ -438,7 +438,8 @@
       "g_boot_clock_resources = 0",
       "g_pin_resources = {}",
       "g_fabric_clock_resources = 0",
-      "g_pll_resources = []"
+      "g_pll_resources = []",
+      "g_gearbox_width = {}"
     ]
   },
   "__primary_validation__" : {
@@ -533,6 +534,7 @@
   "__secondary_validation__" : {
     "__seqeunce__" : [
       "__check_fabric_clock_resource__",
+      "__check_data_width_parameter__",
       "__check_data_rate_parameter__",
       "__check_dpa_mode_parameter__",
       "__check_clock_phase_parameter__",
@@ -546,6 +548,25 @@
         "pin_result = (__connectivity_count__ + g_fabric_clock_resources) <= MAX_FABRIC_CLOCK_RESOURCE"
       ]
     },
+    "__check_data_width_parameter__" : {
+      "__module__" : ["I_SERDES", "O_SERDES"],
+      "__parameter__" : ["WIDTH"],
+      "__equation__" : [
+        "import re",
+        "assert '__location__' in g_all_pins",
+        "m = re.search(r'H(P|R?)_(\\d?)(|_CC?)_(\\d+?)_(\\d\\d?)(P|N?)', '__location__')",
+        "assert m != None",
+        "pn = 'P' if m.group(6) == 'N' else 'N'",
+        "index = int(m.group(4)) & ~1",
+        "index += (1 if pn == 'N' else 0)",
+        "peer_location = 'H%s_%s%s_%d_%s%s' % (m.group(1), m.group(2), m.group(3), index, m.group(5), pn)",
+        "width = int('WIDTH')",
+        "pin_result = width >= 3 and width <= (10 if m.group(6) == 'P' else 5)",
+        "pin_result = pin_result and ((peer_location not in g_gearbox_width) or (g_gearbox_width[peer_location] <= 5 and width <=5))",
+        "g_gearbox_width['__location__' if pin_result else ''] = width",
+        "g_gearbox_width.pop('', None)"
+      ]
+    },
     "__check_data_rate_parameter__" : {
       "__module__" : ["I_SERDES", "O_SERDES", "O_SERDES_CLK"],
       "__parameter__" : ["DATA_RATE"],

diff --git a/...gurationRaptor/CFGDeviceDatabase/Virgo/gemini_compact_22x4_config_attributes.mapping.json b/...gurationRaptor/CFGDeviceDatabase/Virgo/gemini_compact_22x4_config_attributes.mapping.json
@@ -437,7 +437,8 @@
       "g_boot_clock_resources = 0",
       "g_pin_resources = {}",
       "g_fabric_clock_resources = 0",
-      "g_pll_resources = []"
+      "g_pll_resources = []",
+      "g_gearbox_width = {}"
     ]
   },
   "__primary_validation__" : {
@@ -532,6 +533,7 @@
   "__secondary_validation__" : {
     "__seqeunce__" : [
       "__check_fabric_clock_resource__",
+      "__check_data_width_parameter__",
       "__check_data_rate_parameter__",
       "__check_dpa_mode_parameter__",
       "__check_clock_phase_parameter__",
@@ -545,6 +547,25 @@
         "pin_result = (__connectivity_count__ + g_fabric_clock_resources) <= MAX_FABRIC_CLOCK_RESOURCE"
       ]
     },
+    "__check_data_width_parameter__" : {
+      "__module__" : ["I_SERDES", "O_SERDES"],
+      "__parameter__" : ["WIDTH"],
+      "__equation__" : [
+        "import re",
+        "assert '__location__' in g_all_pins",
+        "m = re.search(r'H(P|R?)_(\\d?)(|_CC?)_(\\d+?)_(\\d\\d?)(P|N?)', '__location__')",
+        "assert m != None",
+        "pn = 'P' if m.group(6) == 'N' else 'N'",
+        "index = int(m.group(4)) & ~1",
+        "index += (1 if pn == 'N' else 0)",
+        "peer_location = 'H%s_%s%s_%d_%s%s' % (m.group(1), m.group(2), m.group(3), index, m.group(5), pn)",
+        "width = int('WIDTH')",
+        "pin_result = width >= 3 and width <= (10 if m.group(6) == 'P' else 5)",
+        "pin_result = pin_result and ((peer_location not in g_gearbox_width) or (g_gearbox_width[peer_location] <= 5 and width <=5))",
+        "g_gearbox_width['__location__' if pin_result else ''] = width",
+        "g_gearbox_width.pop('', None)"
+      ]
+    },
     "__check_data_rate_parameter__" : {
       "__module__" : ["I_SERDES", "O_SERDES", "O_SERDES_CLK"],
       "__parameter__" : ["DATA_RATE"],

diff --git a/yosys_verific_rs b/yosys_verific_rs
+1 −1		CMakeLists.txt
+52 −8		design_edit/src/rs_design_edit.cc