Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

added placement error testcase #131

Merged
merged 1 commit into from
Apr 22, 2024
Merged

added placement error testcase #131

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
33 changes: 33 additions & 0 deletions EDA-2735/raptor.tcl
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,33 @@
create_design axi_lite_a32_d32
target_device 1GVTC
add_include_path ./rtl
add_library_path ./rtl
add_library_ext .v .sv
add_design_file ./rtl/axi_lite_a32_d32_master_concat.sv
add_design_file ./rtl/axi_lite_a32_d32_master_name.sv
add_design_file ./rtl/axi_lite_a32_d32_slave_concat.sv
add_design_file ./rtl/axi_lite_a32_d32_slave_name.sv
add_design_file ./rtl/axi_lite_a32_d32_slave_top.sv
add_design_file ./rtl/level_delay.sv
add_design_file ./rtl/ll_auto_sync.sv
add_design_file ./rtl/ll_receive.sv
add_design_file ./rtl/ll_rx_ctrl.sv
add_design_file ./rtl/ll_rx_push.sv
add_design_file ./rtl/ll_transmit.sv
add_design_file ./rtl/ll_tx_cred.sv
add_design_file ./rtl/ll_tx_ctrl.sv
add_design_file ./rtl/syncfifo_mem1r1w.sv
add_design_file ./rtl/syncfifo_ram.sv
add_design_file ./rtl/syncfifo_reg.sv
add_design_file ./rtl/axi_lite_a32_d32_master_top.sv
set_top_module axi_lite_a32_d32_master_top
add_constraint_file ./raptor_sdc.sdc
analyze
synth_options -effort high
synthesize delay
packing
place
route
sta
power
bitstream
4 changes: 4 additions & 0 deletions EDA-2735/raptor_sdc.sdc
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,4 @@
create_clock -period 2.5 clk_wr
set_input_delay 0 -clock clk_wr [get_ports {*}]
set_output_delay 0 -clock clk_wr [get_ports {*}]

106 changes: 106 additions & 0 deletions EDA-2735/results_dir/axi_lite_a32_d32/axi_lite_a32_d32.ospr
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,106 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- -->
<!--Copyright (c) 2021-2022 The Open-Source FPGA Foundation.-->
<Project Version="1.0.39">
<Configuration>
<Option Name="ID" Val="20240422123600538"/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="Project Type" Val="0"/>
</Configuration>
<CompilerConfig>
<Opt Name="LibPath" Val=".././rtl"/>
<Opt Name="IncludePath" Val=".././rtl"/>
<Opt Name="LibExt" Val=".v .sv"/>
<Opt Name="Macro" Val=""/>
</CompilerConfig>
<SimulationConfig>
<Opt Name="LibPath" Val=""/>
<Opt Name="IncludePath" Val=""/>
<Opt Name="LibExt" Val=""/>
<Opt Name="Macro" Val=""/>
</SimulationConfig>
<IpConfig>
<Option Name="InstancePaths" Val=""/>
<Option Name="CatalogPaths" Val=""/>
<Option Name="InstanceCmds" Val=""/>
</IpConfig>
<FileSets>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="run_1/axi_lite_a32_d32.srcs/constrs_1">
<File Path="$OSRCDIR/../../raptor_sdc.sdc"/>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="run_1/axi_lite_a32_d32.srcs/sim_1">
<Config>
<Option Name="TopModule" Val=""/>
<Option Name="TopModuleLib" Val=""/>
</Config>
</FileSet>
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="run_1/axi_lite_a32_d32.srcs/sources_1">
<File Path="$OSRCDIR/../../rtl/axi_lite_a32_d32_master_concat.sv"/>
<File Path="$OSRCDIR/../../rtl/axi_lite_a32_d32_master_name.sv"/>
<File Path="$OSRCDIR/../../rtl/axi_lite_a32_d32_slave_concat.sv"/>
<File Path="$OSRCDIR/../../rtl/axi_lite_a32_d32_slave_name.sv"/>
<File Path="$OSRCDIR/../../rtl/axi_lite_a32_d32_slave_top.sv"/>
<File Path="$OSRCDIR/../../rtl/level_delay.sv"/>
<File Path="$OSRCDIR/../../rtl/ll_auto_sync.sv"/>
<File Path="$OSRCDIR/../../rtl/ll_receive.sv"/>
<File Path="$OSRCDIR/../../rtl/ll_rx_ctrl.sv"/>
<File Path="$OSRCDIR/../../rtl/ll_rx_push.sv"/>
<File Path="$OSRCDIR/../../rtl/ll_transmit.sv"/>
<File Path="$OSRCDIR/../../rtl/ll_tx_cred.sv"/>
<File Path="$OSRCDIR/../../rtl/ll_tx_ctrl.sv"/>
<File Path="$OSRCDIR/../../rtl/syncfifo_mem1r1w.sv"/>
<File Path="$OSRCDIR/../../rtl/syncfifo_ram.sv"/>
<File Path="$OSRCDIR/../../rtl/syncfifo_reg.sv"/>
<File Path="$OSRCDIR/../../rtl/axi_lite_a32_d32_master_top.sv"/>
<Group Id="12" Name="unit_0" Files="$OSRCDIR/../../rtl/axi_lite_a32_d32_master_concat.sv" LibCommand="" LibName=""/>
<Group Id="12" Name="unit_1" Files="$OSRCDIR/../../rtl/axi_lite_a32_d32_master_name.sv" LibCommand="" LibName=""/>
<Group Id="12" Name="unit_2" Files="$OSRCDIR/../../rtl/axi_lite_a32_d32_slave_concat.sv" LibCommand="" LibName=""/>
<Group Id="12" Name="unit_3" Files="$OSRCDIR/../../rtl/axi_lite_a32_d32_slave_name.sv" LibCommand="" LibName=""/>
<Group Id="12" Name="unit_4" Files="$OSRCDIR/../../rtl/axi_lite_a32_d32_slave_top.sv" LibCommand="" LibName=""/>
<Group Id="12" Name="unit_5" Files="$OSRCDIR/../../rtl/level_delay.sv" LibCommand="" LibName=""/>
<Group Id="12" Name="unit_6" Files="$OSRCDIR/../../rtl/ll_auto_sync.sv" LibCommand="" LibName=""/>
<Group Id="12" Name="unit_7" Files="$OSRCDIR/../../rtl/ll_receive.sv" LibCommand="" LibName=""/>
<Group Id="12" Name="unit_8" Files="$OSRCDIR/../../rtl/ll_rx_ctrl.sv" LibCommand="" LibName=""/>
<Group Id="12" Name="unit_9" Files="$OSRCDIR/../../rtl/ll_rx_push.sv" LibCommand="" LibName=""/>
<Group Id="12" Name="unit_10" Files="$OSRCDIR/../../rtl/ll_transmit.sv" LibCommand="" LibName=""/>
<Group Id="12" Name="unit_11" Files="$OSRCDIR/../../rtl/ll_tx_cred.sv" LibCommand="" LibName=""/>
<Group Id="12" Name="unit_12" Files="$OSRCDIR/../../rtl/ll_tx_ctrl.sv" LibCommand="" LibName=""/>
<Group Id="12" Name="unit_13" Files="$OSRCDIR/../../rtl/syncfifo_mem1r1w.sv" LibCommand="" LibName=""/>
<Group Id="12" Name="unit_14" Files="$OSRCDIR/../../rtl/syncfifo_ram.sv" LibCommand="" LibName=""/>
<Group Id="12" Name="unit_15" Files="$OSRCDIR/../../rtl/syncfifo_reg.sv" LibCommand="" LibName=""/>
<Group Id="12" Name="unit_16" Files="$OSRCDIR/../../rtl/axi_lite_a32_d32_master_top.sv" LibCommand="" LibName=""/>
<Config>
<Option Name="TopModule" Val="axi_lite_a32_d32_master_top"/>
<Option Name="TopModuleLib" Val=""/>
</Config>
</FileSet>
</FileSets>
<Runs>
<Run Name="imple_1" Type="Implementation" SrcSet="sources_1" ConstrsSet="constrs_1" State="current" SynthRun="synth_1"/>
<Run Name="synth_1" Type="Synthesis" SrcSet="sources_1" ConstrsSet="constrs_1" State="current" SynthRun="">
<Option Name="Compilation Flow" Val="Classic Flow"/>
<Option Name="Device" Val="1GVTC"/>
<Option Name="Family" Val="Virgo"/>
<Option Name="LanguageVersion" Val="SYSTEMVERILOG_2005"/>
<Option Name="Package" Val="F484A"/>
<Option Name="Series" Val="Virgo"/>
<Option Name="TargetLanguage" Val="VERILOG"/>
</Run>
</Runs>
<Tasks Version="0.0.0">
<Task ID="0" Status="0" Enable="1"/>
<Task ID="1" Status="2" Enable="1"/>
<Task ID="6" Status="2" Enable="1"/>
<Task ID="10" Status="3" Enable="1"/>
<Task ID="15" Status="0" Enable="1"/>
<Task ID="19" Status="0" Enable="1"/>
<Task ID="20" Status="0" Enable="1"/>
<Task ID="21" Status="0" Enable="0"/>
<Task ID="23" Status="2" Enable="1"/>
<Task ID="28" Status="0" Enable="1"/>
<Task ID="31" Status="0" Enable="1"/>
<Task ID="34" Status="0" Enable="1"/>
<Task ID="37" Status="0" Enable="1"/>
</Tasks>
<Compiler Version="0.0.0" CompilerState="4"/>
</Project>
Empty file added ...s_dir/axi_lite_a32_d32/run_1/synth_1_1/impl_1_1_1/placement/axi_lite_a32_d32_openfpga.pcf
View file
Open in desktop
Empty file.
1 change: 1 addition & 0 deletions ...ts_dir/axi_lite_a32_d32/run_1/synth_1_1/impl_1_1_1/placement/axi_lite_a32_d32_pin_loc.cmd
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1 @@
/nfs_eda_sw/softwares/Raptor/instl_dir/04_21_2024_09_15_01/bin/pin_c --csv /nfs_eda_sw/softwares/Raptor/instl_dir/04_21_2024_09_15_01/share/raptor/etc/devices/gemini_compact_62x44/Virgo_Pin_Table.csv --blif /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os-fpga/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/axi_lite_a32_d32/results_dir/axi_lite_a32_d32/run_1/synth_1_1/synthesis/axi_lite_a32_d32_post_synth.eblif --output axi_lite_a32_d32_pin_loc.place --assign_unconstrained_pins in_define_order --edits /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os-fpga/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/axi_lite_a32_d32/results_dir/axi_lite_a32_d32/run_1/synth_1_1/synthesis/config.json
Loading
Loading