added designs with different pll usage

GJC-33/boot_clk_pll.v

@@ -0,0 +1,39 @@
+//***********************************************************
+// Functionality: Flip FLop design with boot clk as pll source
+// Author:        Azfar 
+//***********************************************************
+
+
+module boot_clk_pll (
+    input   wire data_i,
+    input   wire enable,
+    output  wire data_o
+);
+    wire const1;
+    wire clk_design;
+    wire clk_pll_in;
+    wire data_design;
+    wire enable_design;
+    reg  data_o_design;
+
+    assign const1 = 1;
+
+    I_BUF #(.WEAK_KEEPER("PULLDOWN")) data_i_buffer (.I(data_i), .EN(const1), .O(data_design));
+    I_BUF #(.WEAK_KEEPER("PULLDOWN")) enable_buffer (.I(enable), .EN(const1), .O(enable_design));
+    O_BUF data_o_buffer (.I(data_o_design), .O(data_o));
+
+
+    BOOT_CLOCK internal_osc (clk_pll_in);
+
+    PLL #(.PLL_MULT(40), .PLL_DIV(1), .PLL_POST_DIV(2)) clk_pll_gen (
+        .PLL_EN(const1), // PLL Enable
+        .CLK_IN(clk_pll_in), // Clock input
+        .CLK_OUT_DIV4(clk_design)
+        );
+
+
+    always @(posedge clk_design) begin
+        if(enable_design)data_o_design <= data_design;
+    end
+
+endmodule

GJC-33/constraints.sdc

@@ -0,0 +1,8 @@
+set_top_module boot_clk_pll
+
+create_clock -period 5 -name clk_design
+
+set_input_delay 2 -clock clk_design [get_ports {data_i}]
+set_input_delay 2 -clock clk_design [get_ports {enable}]
+set_output_delay 2 -clock clk_design [get_ports {data_o}]
+

GJC-33/pin_constraints.pin

@@ -0,0 +1,13 @@
+#set_clock_pin -device_clock clk[0] -design_clock boot_clk_pll.clk_design
+
+#set_property mode Mode_BP_SDR_A_RX HP_2_CC_10_5P
+#set_pin_loc clk HP_2_CC_10_5P
+
+set_property mode Mode_BP_SDR_A_RX HR_2_6_3P
+set_pin_loc data_i HR_2_6_3P
+
+set_property mode Mode_BP_SDR_A_TX HR_5_12_6P
+set_pin_loc data_o HR_5_12_6P
+
+set_property mode Mode_BP_SDR_A_RX HR_1_6_3P
+set_pin_loc enable HR_1_6_3P

GJC-33/raptor.tcl

@@ -0,0 +1,14 @@
+create_design boot_clk_pll
+add_design_file boot_clk_pll.v
+set_top_module boot_clk_pll
+add_constraint_file constraints.sdc
+add_constraint_file pin_constraints.pin
+target_device 1VG28
+
+analyze
+synthesize
+packing
+place
+route
+sta
+bitstream

GJC-34/pin_constraints.pin

@@ -0,0 +1,38 @@
+
+set_property mode Mode_BP_SDR_A_RX HR_1_0_0P
+set_pin_loc data_i[0] HR_1_0_0P
+
+set_property mode Mode_BP_SDR_A_RX HR_1_2_1P
+set_pin_loc data_i[1] HR_1_2_1P
+
+set_property mode Mode_BP_SDR_A_RX HR_1_4_2P
+set_pin_loc data_i[2] HR_1_4_2P
+
+set_property mode Mode_BP_SDR_A_RX HR_1_6_3P
+set_pin_loc data_i[3] HR_1_6_3P
+
+
+set_property mode Mode_BP_SDR_A_TX HR_1_8_4P
+set_pin_loc data_o[0] HR_1_8_4P
+
+set_property mode Mode_BP_SDR_A_TX HR_1_12_6P
+set_pin_loc data_o[1] HR_1_12_6P
+
+set_property mode Mode_BP_SDR_A_TX HR_1_14_7P
+set_pin_loc data_o[2] HR_1_14_7P
+
+set_property mode Mode_BP_SDR_A_TX HR_1_16_8P
+set_pin_loc data_o[3] HR_1_16_8P
+
+
+set_property mode Mode_BP_SDR_A_RX HR_1_18_9P
+set_pin_loc enable[0] HR_1_18_9P
+
+set_property mode Mode_BP_SDR_A_RX HR_1_20_10P
+set_pin_loc enable[1] HR_1_20_10P
+
+set_property mode Mode_BP_SDR_A_RX HR_1_22_11P
+set_pin_loc enable[2] HR_1_22_11P
+
+set_property mode Mode_BP_SDR_A_RX HR_1_24_12P
+set_pin_loc enable[3] HR_1_24_12P

GJC-34/pll_4_clocks_posedge.v

@@ -0,0 +1,66 @@
+//***********************************************************
+// Functionality: Flip FLop design with boot clk as pll source
+// Author:        Azfar 
+//***********************************************************
+
+
+module pll_4_clocks_posedge (
+    input   wire [3:0] data_i,
+    input   wire [3:0] enable,
+    output  wire [3:0] data_o
+);
+    wire const1;
+    wire clk_design0, clk_design1, clk_design2, clk_design3;
+    wire clk_pll_in;
+    wire [3:0] data_design;
+    wire [3:0] enable_design;
+    reg  [3:0] data_o_design;
+
+    assign const1 = 1;
+
+    I_BUF #(.WEAK_KEEPER("PULLDOWN")) data_i_buffer0 (.I(data_i[0]), .EN(const1), .O(data_design[0]));
+    I_BUF #(.WEAK_KEEPER("PULLDOWN")) enable_buffer0 (.I(enable[0]), .EN(const1), .O(enable_design[0]));
+    O_BUF data_o_buffer0 (.I(data_o_design[0]), .O(data_o[0]));
+
+    I_BUF #(.WEAK_KEEPER("PULLDOWN")) data_i_buffer1 (.I(data_i[1]), .EN(const1), .O(data_design[1]));
+    I_BUF #(.WEAK_KEEPER("PULLDOWN")) enable_buffer1 (.I(enable[1]), .EN(const1), .O(enable_design[1]));
+    O_BUF data_o_buffer1 (.I(data_o_design[1]), .O(data_o[1]));
+
+    I_BUF #(.WEAK_KEEPER("PULLDOWN")) data_i_buffer2 (.I(data_i[2]), .EN(const1), .O(data_design[2]));
+    I_BUF #(.WEAK_KEEPER("PULLDOWN")) enable_buffer2 (.I(enable[2]), .EN(const1), .O(enable_design[2]));
+    O_BUF data_o_buffer2 (.I(data_o_design[2]), .O(data_o[2]));
+
+    I_BUF #(.WEAK_KEEPER("PULLDOWN")) data_i_buffer3 (.I(data_i[3]), .EN(const1), .O(data_design[3]));
+    I_BUF #(.WEAK_KEEPER("PULLDOWN")) enable_buffer3 (.I(enable[3]), .EN(const1), .O(enable_design[3]));
+    O_BUF data_o_buffer3 (.I(data_o_design[3]), .O(data_o[3]));
+
+
+    BOOT_CLOCK internal_osc (clk_pll_in);
+
+    PLL #(.PLL_MULT(40), .PLL_DIV(1), .PLL_POST_DIV(2)) clk_pll_gen (
+        .PLL_EN(const1), // PLL Enable
+        .CLK_IN(clk_pll_in), // Clock input
+        .CLK_OUT(clk_design0),
+        .CLK_OUT_DIV2(clk_design1),
+        .CLK_OUT_DIV3(clk_design2),
+        .CLK_OUT_DIV4(clk_design3)
+        );
+
+
+    always @(posedge clk_design0) begin
+        if(enable_design[0])data_o_design[0] <= data_design[0];
+    end
+
+    always @(posedge clk_design1) begin
+        if(enable_design[1])data_o_design[1] <= data_design[1];
+    end
+
+    always @(posedge clk_design2) begin
+        if(enable_design[2])data_o_design[2] <= data_design[2];
+    end
+
+    always @(posedge clk_design3) begin
+        if(enable_design[3])data_o_design[3] <= data_design[3];
+    end
+
+endmodule

GJC-34/raptor.tcl

@@ -0,0 +1,14 @@
+create_design pll_4_clocks_posedge
+add_design_file pll_4_clocks_posedge.v
+set_top_module pll_4_clocks_posedge
+# add_constraint_file constraints.sdc
+add_constraint_file pin_constraints.pin
+target_device 1VG28
+
+analyze
+synthesize
+packing
+place
+route
+sta
+bitstream

GJC-35/pin_constraints.pin

@@ -0,0 +1,75 @@
+
+set_property mode Mode_BP_SDR_A_RX HR_1_0_0P
+set_pin_loc data_i[0] HR_1_0_0P
+
+set_property mode Mode_BP_SDR_A_RX HR_1_2_1P
+set_pin_loc data_i[1] HR_1_2_1P
+
+set_property mode Mode_BP_SDR_A_RX HR_1_4_2P
+set_pin_loc data_i[2] HR_1_4_2P
+
+set_property mode Mode_BP_SDR_A_RX HR_1_6_3P
+set_pin_loc data_i[3] HR_1_6_3P
+
+set_property mode Mode_BP_SDR_A_RX HR_2_0_0P
+set_pin_loc data_i[4] HR_2_0_0P
+
+set_property mode Mode_BP_SDR_A_RX HR_2_2_1P
+set_pin_loc data_i[5] HR_2_2_1P
+
+set_property mode Mode_BP_SDR_A_RX HR_2_4_2P
+set_pin_loc data_i[6] HR_2_4_2P
+
+set_property mode Mode_BP_SDR_A_RX HR_2_6_3P
+set_pin_loc data_i[7] HR_2_6_3P
+
+
+
+set_property mode Mode_BP_SDR_A_TX HR_1_8_4P
+set_pin_loc data_o[0] HR_1_8_4P
+
+set_property mode Mode_BP_SDR_A_TX HR_1_12_6P
+set_pin_loc data_o[1] HR_1_12_6P
+
+set_property mode Mode_BP_SDR_A_TX HR_1_14_7P
+set_pin_loc data_o[2] HR_1_14_7P
+
+set_property mode Mode_BP_SDR_A_TX HR_1_16_8P
+set_pin_loc data_o[3] HR_1_16_8P
+
+set_property mode Mode_BP_SDR_A_TX HR_2_8_4P
+set_pin_loc data_o[4] HR_2_8_4P
+
+set_property mode Mode_BP_SDR_A_TX HR_2_12_6P
+set_pin_loc data_o[5] HR_2_12_6P
+
+set_property mode Mode_BP_SDR_A_TX HR_2_14_7P
+set_pin_loc data_o[6] HR_2_14_7P
+
+set_property mode Mode_BP_SDR_A_TX HR_2_16_8P
+set_pin_loc data_o[7] HR_2_16_8P
+
+
+set_property mode Mode_BP_SDR_A_RX HR_1_18_9P
+set_pin_loc enable[0] HR_1_18_9P
+
+set_property mode Mode_BP_SDR_A_RX HR_1_20_10P
+set_pin_loc enable[1] HR_1_20_10P
+
+set_property mode Mode_BP_SDR_A_RX HR_1_22_11P
+set_pin_loc enable[2] HR_1_22_11P
+
+set_property mode Mode_BP_SDR_A_RX HR_1_24_12P
+set_pin_loc enable[3] HR_1_24_12P
+
+set_property mode Mode_BP_SDR_A_RX HR_2_18_9P
+set_pin_loc enable[4] HR_2_18_9P
+
+set_property mode Mode_BP_SDR_A_RX HR_2_20_10P
+set_pin_loc enable[5] HR_2_20_10P
+
+set_property mode Mode_BP_SDR_A_RX HR_2_22_11P
+set_pin_loc enable[6] HR_2_22_11P
+
+set_property mode Mode_BP_SDR_A_RX HR_2_24_12P
+set_pin_loc enable[7] HR_2_24_12P

GJC-35/pll_8_clocks_posedge.v

@@ -0,0 +1,108 @@
+//***********************************************************
+// Functionality: Flip FLop design with boot clk as pll source
+// Author:        Azfar 
+//***********************************************************
+
+
+module pll_8_clocks_posedge (
+    input   wire [7:0] data_i,
+    input   wire [7:0] enable,
+    output  wire [7:0] data_o
+);
+    wire const1;
+    wire clk_design0, clk_design1, clk_design2, clk_design3;
+    wire clk_design4, clk_design5, clk_design6, clk_design7;
+    wire clk_pll_in;
+    wire [7:0] data_design;
+    wire [7:0] enable_design;
+    reg  [7:0] data_o_design;
+
+    assign const1 = 1;
+
+    I_BUF #(.WEAK_KEEPER("PULLDOWN")) data_i_buffer0 (.I(data_i[0]), .EN(const1), .O(data_design[0]));
+    I_BUF #(.WEAK_KEEPER("PULLDOWN")) enable_buffer0 (.I(enable[0]), .EN(const1), .O(enable_design[0]));
+    O_BUF data_o_buffer0 (.I(data_o_design[0]), .O(data_o[0]));
+
+    I_BUF #(.WEAK_KEEPER("PULLDOWN")) data_i_buffer1 (.I(data_i[1]), .EN(const1), .O(data_design[1]));
+    I_BUF #(.WEAK_KEEPER("PULLDOWN")) enable_buffer1 (.I(enable[1]), .EN(const1), .O(enable_design[1]));
+    O_BUF data_o_buffer1 (.I(data_o_design[1]), .O(data_o[1]));
+
+    I_BUF #(.WEAK_KEEPER("PULLDOWN")) data_i_buffer2 (.I(data_i[2]), .EN(const1), .O(data_design[2]));
+    I_BUF #(.WEAK_KEEPER("PULLDOWN")) enable_buffer2 (.I(enable[2]), .EN(const1), .O(enable_design[2]));
+    O_BUF data_o_buffer2 (.I(data_o_design[2]), .O(data_o[2]));
+
+    I_BUF #(.WEAK_KEEPER("PULLDOWN")) data_i_buffer3 (.I(data_i[3]), .EN(const1), .O(data_design[3]));
+    I_BUF #(.WEAK_KEEPER("PULLDOWN")) enable_buffer3 (.I(enable[3]), .EN(const1), .O(enable_design[3]));
+    O_BUF data_o_buffer3 (.I(data_o_design[3]), .O(data_o[3]));
+
+    I_BUF #(.WEAK_KEEPER("PULLDOWN")) data_i_buffer4 (.I(data_i[4]), .EN(const1), .O(data_design[4]));
+    I_BUF #(.WEAK_KEEPER("PULLDOWN")) enable_buffer4 (.I(enable[4]), .EN(const1), .O(enable_design[4]));
+    O_BUF data_o_buffer4 (.I(data_o_design[4]), .O(data_o[4]));
+
+    I_BUF #(.WEAK_KEEPER("PULLDOWN")) data_i_buffer5 (.I(data_i[5]), .EN(const1), .O(data_design[5]));
+    I_BUF #(.WEAK_KEEPER("PULLDOWN")) enable_buffer5 (.I(enable[5]), .EN(const1), .O(enable_design[5]));
+    O_BUF data_o_buffer5 (.I(data_o_design[5]), .O(data_o[5]));
+
+    I_BUF #(.WEAK_KEEPER("PULLDOWN")) data_i_buffer6 (.I(data_i[6]), .EN(const1), .O(data_design[6]));
+    I_BUF #(.WEAK_KEEPER("PULLDOWN")) enable_buffer6 (.I(enable[6]), .EN(const1), .O(enable_design[6]));
+    O_BUF data_o_buffer6 (.I(data_o_design[6]), .O(data_o[6]));
+
+    I_BUF #(.WEAK_KEEPER("PULLDOWN")) data_i_buffer7 (.I(data_i[7]), .EN(const1), .O(data_design[7]));
+    I_BUF #(.WEAK_KEEPER("PULLDOWN")) enable_buffer7 (.I(enable[7]), .EN(const1), .O(enable_design[7]));
+    O_BUF data_o_buffer7 (.I(data_o_design[7]), .O(data_o[7]));
+
+
+    BOOT_CLOCK internal_osc (clk_pll_in);
+
+    PLL #(.PLL_MULT(40), .PLL_DIV(1), .PLL_POST_DIV(2)) clk_pll_gen0 (
+        .PLL_EN(const1), // PLL Enable
+        .CLK_IN(clk_pll_in), // Clock input
+        .CLK_OUT(clk_design0),
+        .CLK_OUT_DIV2(clk_design1),
+        .CLK_OUT_DIV3(clk_design2),
+        .CLK_OUT_DIV4(clk_design3)
+        );
+
+    PLL #(.PLL_MULT(46), .PLL_DIV(1), .PLL_POST_DIV(2)) clk_pll_gen1 (
+        .PLL_EN(const1), // PLL Enable
+        .CLK_IN(clk_pll_in), // Clock input
+        .CLK_OUT(clk_design4),
+        .CLK_OUT_DIV2(clk_design5),
+        .CLK_OUT_DIV3(clk_design6),
+        .CLK_OUT_DIV4(clk_design7)
+        );
+
+
+    always @(posedge clk_design0) begin
+        if(enable_design[0])data_o_design[0] <= data_design[0];
+    end
+
+    always @(posedge clk_design1) begin
+        if(enable_design[1])data_o_design[1] <= data_design[1];
+    end
+
+    always @(posedge clk_design2) begin
+        if(enable_design[2])data_o_design[2] <= data_design[2];
+    end
+
+    always @(posedge clk_design3) begin
+        if(enable_design[3])data_o_design[3] <= data_design[3];
+    end
+
+    always @(posedge clk_design4) begin
+        if(enable_design[4])data_o_design[4] <= data_design[4];
+    end
+
+    always @(posedge clk_design5) begin
+        if(enable_design[5])data_o_design[5] <= data_design[5];
+    end
+
+    always @(posedge clk_design6) begin
+        if(enable_design[6])data_o_design[6] <= data_design[6];
+    end
+
+    always @(posedge clk_design7) begin
+        if(enable_design[7])data_o_design[7] <= data_design[7];
+    end
+
+endmodule