From 94101be43cf939af4f19b4d05e94a698264444e0 Mon Sep 17 00:00:00 2001 From: valence-e Date: Wed, 17 Apr 2024 12:33:20 +0500 Subject: [PATCH 1/3] added designs with different pll usage --- GJC-33/boot_clk_pll.v | 39 ++++++++++++ GJC-33/constraints.sdc | 8 +++ GJC-33/pin_constraints.pin | 13 ++++ GJC-33/raptor.tcl | 14 +++++ GJC-34/pin_constraints.pin | 38 ++++++++++++ GJC-34/pll_4_clocks_posedge.v | 66 +++++++++++++++++++++ GJC-34/raptor.tcl | 14 +++++ GJC-35/pin_constraints.pin | 75 +++++++++++++++++++++++ GJC-35/pll_8_clocks_posedge.v | 108 ++++++++++++++++++++++++++++++++++ GJC-35/raptor.tcl | 14 +++++ GJC-36/pin_constraints.pin | 75 +++++++++++++++++++++++ GJC-36/pll_8_clocks_negedge.v | 108 ++++++++++++++++++++++++++++++++++ GJC-36/raptor.tcl | 14 +++++ 13 files changed, 586 insertions(+) create mode 100644 GJC-33/boot_clk_pll.v create mode 100644 GJC-33/constraints.sdc create mode 100644 GJC-33/pin_constraints.pin create mode 100644 GJC-33/raptor.tcl create mode 100644 GJC-34/pin_constraints.pin create mode 100644 GJC-34/pll_4_clocks_posedge.v create mode 100644 GJC-34/raptor.tcl create mode 100644 GJC-35/pin_constraints.pin create mode 100644 GJC-35/pll_8_clocks_posedge.v create mode 100644 GJC-35/raptor.tcl create mode 100644 GJC-36/pin_constraints.pin create mode 100644 GJC-36/pll_8_clocks_negedge.v create mode 100644 GJC-36/raptor.tcl diff --git a/GJC-33/boot_clk_pll.v b/GJC-33/boot_clk_pll.v new file mode 100644 index 00000000..6132b68d --- /dev/null +++ b/GJC-33/boot_clk_pll.v @@ -0,0 +1,39 @@ +//*********************************************************** +// Functionality: Flip FLop design with boot clk as pll source +// Author: Azfar +//*********************************************************** + + +module boot_clk_pll ( + input wire data_i, + input wire enable, + output wire data_o +); + wire const1; + wire clk_design; + wire clk_pll_in; + wire data_design; + wire enable_design; + reg data_o_design; + + assign const1 = 1; + + I_BUF #(.WEAK_KEEPER("PULLDOWN")) data_i_buffer (.I(data_i), .EN(const1), .O(data_design)); + I_BUF #(.WEAK_KEEPER("PULLDOWN")) enable_buffer (.I(enable), .EN(const1), .O(enable_design)); + O_BUF data_o_buffer (.I(data_o_design), .O(data_o)); + + + BOOT_CLOCK internal_osc (clk_pll_in); + + PLL #(.PLL_MULT(40), .PLL_DIV(1), .PLL_POST_DIV(2)) clk_pll_gen ( + .PLL_EN(const1), // PLL Enable + .CLK_IN(clk_pll_in), // Clock input + .CLK_OUT_DIV4(clk_design) + ); + + + always @(posedge clk_design) begin + if(enable_design)data_o_design <= data_design; + end + +endmodule \ No newline at end of file diff --git a/GJC-33/constraints.sdc b/GJC-33/constraints.sdc new file mode 100644 index 00000000..d8f0c27f --- /dev/null +++ b/GJC-33/constraints.sdc @@ -0,0 +1,8 @@ +set_top_module boot_clk_pll + +create_clock -period 5 -name clk_design + +set_input_delay 2 -clock clk_design [get_ports {data_i}] +set_input_delay 2 -clock clk_design [get_ports {enable}] +set_output_delay 2 -clock clk_design [get_ports {data_o}] + diff --git a/GJC-33/pin_constraints.pin b/GJC-33/pin_constraints.pin new file mode 100644 index 00000000..1d712ea8 --- /dev/null +++ b/GJC-33/pin_constraints.pin @@ -0,0 +1,13 @@ +#set_clock_pin -device_clock clk[0] -design_clock boot_clk_pll.clk_design + +#set_property mode Mode_BP_SDR_A_RX HP_2_CC_10_5P +#set_pin_loc clk HP_2_CC_10_5P + +set_property mode Mode_BP_SDR_A_RX HR_2_6_3P +set_pin_loc data_i HR_2_6_3P + +set_property mode Mode_BP_SDR_A_TX HR_5_12_6P +set_pin_loc data_o HR_5_12_6P + +set_property mode Mode_BP_SDR_A_RX HR_1_6_3P +set_pin_loc enable HR_1_6_3P diff --git a/GJC-33/raptor.tcl b/GJC-33/raptor.tcl new file mode 100644 index 00000000..b17dd3f7 --- /dev/null +++ b/GJC-33/raptor.tcl @@ -0,0 +1,14 @@ +create_design boot_clk_pll +add_design_file boot_clk_pll.v +set_top_module boot_clk_pll +add_constraint_file constraints.sdc +add_constraint_file pin_constraints.pin +target_device 1VG28 + +analyze +synthesize +packing +place +route +sta +bitstream diff --git a/GJC-34/pin_constraints.pin b/GJC-34/pin_constraints.pin new file mode 100644 index 00000000..f2e135f0 --- /dev/null +++ b/GJC-34/pin_constraints.pin @@ -0,0 +1,38 @@ + +set_property mode Mode_BP_SDR_A_RX HR_1_0_0P +set_pin_loc data_i[0] HR_1_0_0P + +set_property mode Mode_BP_SDR_A_RX HR_1_2_1P +set_pin_loc data_i[1] HR_1_2_1P + +set_property mode Mode_BP_SDR_A_RX HR_1_4_2P +set_pin_loc data_i[2] HR_1_4_2P + +set_property mode Mode_BP_SDR_A_RX HR_1_6_3P +set_pin_loc data_i[3] HR_1_6_3P + + +set_property mode Mode_BP_SDR_A_TX HR_1_8_4P +set_pin_loc data_o[0] HR_1_8_4P + +set_property mode Mode_BP_SDR_A_TX HR_1_12_6P +set_pin_loc data_o[1] HR_1_12_6P + +set_property mode Mode_BP_SDR_A_TX HR_1_14_7P +set_pin_loc data_o[2] HR_1_14_7P + +set_property mode Mode_BP_SDR_A_TX HR_1_16_8P +set_pin_loc data_o[3] HR_1_16_8P + + +set_property mode Mode_BP_SDR_A_RX HR_1_18_9P +set_pin_loc enable[0] HR_1_18_9P + +set_property mode Mode_BP_SDR_A_RX HR_1_20_10P +set_pin_loc enable[1] HR_1_20_10P + +set_property mode Mode_BP_SDR_A_RX HR_1_22_11P +set_pin_loc enable[2] HR_1_22_11P + +set_property mode Mode_BP_SDR_A_RX HR_1_24_12P +set_pin_loc enable[3] HR_1_24_12P \ No newline at end of file diff --git a/GJC-34/pll_4_clocks_posedge.v b/GJC-34/pll_4_clocks_posedge.v new file mode 100644 index 00000000..c4acfb8e --- /dev/null +++ b/GJC-34/pll_4_clocks_posedge.v @@ -0,0 +1,66 @@ +//*********************************************************** +// Functionality: Flip FLop design with boot clk as pll source +// Author: Azfar +//*********************************************************** + + +module pll_4_clocks_posedge ( + input wire [3:0] data_i, + input wire [3:0] enable, + output wire [3:0] data_o +); + wire const1; + wire clk_design0, clk_design1, clk_design2, clk_design3; + wire clk_pll_in; + wire [3:0] data_design; + wire [3:0] enable_design; + reg [3:0] data_o_design; + + assign const1 = 1; + + I_BUF #(.WEAK_KEEPER("PULLDOWN")) data_i_buffer0 (.I(data_i[0]), .EN(const1), .O(data_design[0])); + I_BUF #(.WEAK_KEEPER("PULLDOWN")) enable_buffer0 (.I(enable[0]), .EN(const1), .O(enable_design[0])); + O_BUF data_o_buffer0 (.I(data_o_design[0]), .O(data_o[0])); + + I_BUF #(.WEAK_KEEPER("PULLDOWN")) data_i_buffer1 (.I(data_i[1]), .EN(const1), .O(data_design[1])); + I_BUF #(.WEAK_KEEPER("PULLDOWN")) enable_buffer1 (.I(enable[1]), .EN(const1), .O(enable_design[1])); + O_BUF data_o_buffer1 (.I(data_o_design[1]), .O(data_o[1])); + + I_BUF #(.WEAK_KEEPER("PULLDOWN")) data_i_buffer2 (.I(data_i[2]), .EN(const1), .O(data_design[2])); + I_BUF #(.WEAK_KEEPER("PULLDOWN")) enable_buffer2 (.I(enable[2]), .EN(const1), .O(enable_design[2])); + O_BUF data_o_buffer2 (.I(data_o_design[2]), .O(data_o[2])); + + I_BUF #(.WEAK_KEEPER("PULLDOWN")) data_i_buffer3 (.I(data_i[3]), .EN(const1), .O(data_design[3])); + I_BUF #(.WEAK_KEEPER("PULLDOWN")) enable_buffer3 (.I(enable[3]), .EN(const1), .O(enable_design[3])); + O_BUF data_o_buffer3 (.I(data_o_design[3]), .O(data_o[3])); + + + BOOT_CLOCK internal_osc (clk_pll_in); + + PLL #(.PLL_MULT(40), .PLL_DIV(1), .PLL_POST_DIV(2)) clk_pll_gen ( + .PLL_EN(const1), // PLL Enable + .CLK_IN(clk_pll_in), // Clock input + .CLK_OUT(clk_design0), + .CLK_OUT_DIV2(clk_design1), + .CLK_OUT_DIV3(clk_design2), + .CLK_OUT_DIV4(clk_design3) + ); + + + always @(posedge clk_design0) begin + if(enable_design[0])data_o_design[0] <= data_design[0]; + end + + always @(posedge clk_design1) begin + if(enable_design[1])data_o_design[1] <= data_design[1]; + end + + always @(posedge clk_design2) begin + if(enable_design[2])data_o_design[2] <= data_design[2]; + end + + always @(posedge clk_design3) begin + if(enable_design[3])data_o_design[3] <= data_design[3]; + end + +endmodule \ No newline at end of file diff --git a/GJC-34/raptor.tcl b/GJC-34/raptor.tcl new file mode 100644 index 00000000..b675140b --- /dev/null +++ b/GJC-34/raptor.tcl @@ -0,0 +1,14 @@ +create_design pll_4_clocks_posedge +add_design_file pll_4_clocks_posedge.v +set_top_module pll_4_clocks_posedge +# add_constraint_file constraints.sdc +add_constraint_file pin_constraints.pin +target_device 1VG28 + +analyze +synthesize +packing +place +route +sta +bitstream diff --git a/GJC-35/pin_constraints.pin b/GJC-35/pin_constraints.pin new file mode 100644 index 00000000..2b62c380 --- /dev/null +++ b/GJC-35/pin_constraints.pin @@ -0,0 +1,75 @@ + +set_property mode Mode_BP_SDR_A_RX HR_1_0_0P +set_pin_loc data_i[0] HR_1_0_0P + +set_property mode Mode_BP_SDR_A_RX HR_1_2_1P +set_pin_loc data_i[1] HR_1_2_1P + +set_property mode Mode_BP_SDR_A_RX HR_1_4_2P +set_pin_loc data_i[2] HR_1_4_2P + +set_property mode Mode_BP_SDR_A_RX HR_1_6_3P +set_pin_loc data_i[3] HR_1_6_3P + +set_property mode Mode_BP_SDR_A_RX HR_2_0_0P +set_pin_loc data_i[4] HR_2_0_0P + +set_property mode Mode_BP_SDR_A_RX HR_2_2_1P +set_pin_loc data_i[5] HR_2_2_1P + +set_property mode Mode_BP_SDR_A_RX HR_2_4_2P +set_pin_loc data_i[6] HR_2_4_2P + +set_property mode Mode_BP_SDR_A_RX HR_2_6_3P +set_pin_loc data_i[7] HR_2_6_3P + + + +set_property mode Mode_BP_SDR_A_TX HR_1_8_4P +set_pin_loc data_o[0] HR_1_8_4P + +set_property mode Mode_BP_SDR_A_TX HR_1_12_6P +set_pin_loc data_o[1] HR_1_12_6P + +set_property mode Mode_BP_SDR_A_TX HR_1_14_7P +set_pin_loc data_o[2] HR_1_14_7P + +set_property mode Mode_BP_SDR_A_TX HR_1_16_8P +set_pin_loc data_o[3] HR_1_16_8P + +set_property mode Mode_BP_SDR_A_TX HR_2_8_4P +set_pin_loc data_o[4] HR_2_8_4P + +set_property mode Mode_BP_SDR_A_TX HR_2_12_6P +set_pin_loc data_o[5] HR_2_12_6P + +set_property mode Mode_BP_SDR_A_TX HR_2_14_7P +set_pin_loc data_o[6] HR_2_14_7P + +set_property mode Mode_BP_SDR_A_TX HR_2_16_8P +set_pin_loc data_o[7] HR_2_16_8P + + +set_property mode Mode_BP_SDR_A_RX HR_1_18_9P +set_pin_loc enable[0] HR_1_18_9P + +set_property mode Mode_BP_SDR_A_RX HR_1_20_10P +set_pin_loc enable[1] HR_1_20_10P + +set_property mode Mode_BP_SDR_A_RX HR_1_22_11P +set_pin_loc enable[2] HR_1_22_11P + +set_property mode Mode_BP_SDR_A_RX HR_1_24_12P +set_pin_loc enable[3] HR_1_24_12P + +set_property mode Mode_BP_SDR_A_RX HR_2_18_9P +set_pin_loc enable[4] HR_2_18_9P + +set_property mode Mode_BP_SDR_A_RX HR_2_20_10P +set_pin_loc enable[5] HR_2_20_10P + +set_property mode Mode_BP_SDR_A_RX HR_2_22_11P +set_pin_loc enable[6] HR_2_22_11P + +set_property mode Mode_BP_SDR_A_RX HR_2_24_12P +set_pin_loc enable[7] HR_2_24_12P \ No newline at end of file diff --git a/GJC-35/pll_8_clocks_posedge.v b/GJC-35/pll_8_clocks_posedge.v new file mode 100644 index 00000000..330fcbf3 --- /dev/null +++ b/GJC-35/pll_8_clocks_posedge.v @@ -0,0 +1,108 @@ +//*********************************************************** +// Functionality: Flip FLop design with boot clk as pll source +// Author: Azfar +//*********************************************************** + + +module pll_8_clocks_posedge ( + input wire [7:0] data_i, + input wire [7:0] enable, + output wire [7:0] data_o +); + wire const1; + wire clk_design0, clk_design1, clk_design2, clk_design3; + wire clk_design4, clk_design5, clk_design6, clk_design7; + wire clk_pll_in; + wire [7:0] data_design; + wire [7:0] enable_design; + reg [7:0] data_o_design; + + assign const1 = 1; + + I_BUF #(.WEAK_KEEPER("PULLDOWN")) data_i_buffer0 (.I(data_i[0]), .EN(const1), .O(data_design[0])); + I_BUF #(.WEAK_KEEPER("PULLDOWN")) enable_buffer0 (.I(enable[0]), .EN(const1), .O(enable_design[0])); + O_BUF data_o_buffer0 (.I(data_o_design[0]), .O(data_o[0])); + + I_BUF #(.WEAK_KEEPER("PULLDOWN")) data_i_buffer1 (.I(data_i[1]), .EN(const1), .O(data_design[1])); + I_BUF #(.WEAK_KEEPER("PULLDOWN")) enable_buffer1 (.I(enable[1]), .EN(const1), .O(enable_design[1])); + O_BUF data_o_buffer1 (.I(data_o_design[1]), .O(data_o[1])); + + I_BUF #(.WEAK_KEEPER("PULLDOWN")) data_i_buffer2 (.I(data_i[2]), .EN(const1), .O(data_design[2])); + I_BUF #(.WEAK_KEEPER("PULLDOWN")) enable_buffer2 (.I(enable[2]), .EN(const1), .O(enable_design[2])); + O_BUF data_o_buffer2 (.I(data_o_design[2]), .O(data_o[2])); + + I_BUF #(.WEAK_KEEPER("PULLDOWN")) data_i_buffer3 (.I(data_i[3]), .EN(const1), .O(data_design[3])); + I_BUF #(.WEAK_KEEPER("PULLDOWN")) enable_buffer3 (.I(enable[3]), .EN(const1), .O(enable_design[3])); + O_BUF data_o_buffer3 (.I(data_o_design[3]), .O(data_o[3])); + + I_BUF #(.WEAK_KEEPER("PULLDOWN")) data_i_buffer4 (.I(data_i[4]), .EN(const1), .O(data_design[4])); + I_BUF #(.WEAK_KEEPER("PULLDOWN")) enable_buffer4 (.I(enable[4]), .EN(const1), .O(enable_design[4])); + O_BUF data_o_buffer4 (.I(data_o_design[4]), .O(data_o[4])); + + I_BUF #(.WEAK_KEEPER("PULLDOWN")) data_i_buffer5 (.I(data_i[5]), .EN(const1), .O(data_design[5])); + I_BUF #(.WEAK_KEEPER("PULLDOWN")) enable_buffer5 (.I(enable[5]), .EN(const1), .O(enable_design[5])); + O_BUF data_o_buffer5 (.I(data_o_design[5]), .O(data_o[5])); + + I_BUF #(.WEAK_KEEPER("PULLDOWN")) data_i_buffer6 (.I(data_i[6]), .EN(const1), .O(data_design[6])); + I_BUF #(.WEAK_KEEPER("PULLDOWN")) enable_buffer6 (.I(enable[6]), .EN(const1), .O(enable_design[6])); + O_BUF data_o_buffer6 (.I(data_o_design[6]), .O(data_o[6])); + + I_BUF #(.WEAK_KEEPER("PULLDOWN")) data_i_buffer7 (.I(data_i[7]), .EN(const1), .O(data_design[7])); + I_BUF #(.WEAK_KEEPER("PULLDOWN")) enable_buffer7 (.I(enable[7]), .EN(const1), .O(enable_design[7])); + O_BUF data_o_buffer7 (.I(data_o_design[7]), .O(data_o[7])); + + + BOOT_CLOCK internal_osc (clk_pll_in); + + PLL #(.PLL_MULT(40), .PLL_DIV(1), .PLL_POST_DIV(2)) clk_pll_gen0 ( + .PLL_EN(const1), // PLL Enable + .CLK_IN(clk_pll_in), // Clock input + .CLK_OUT(clk_design0), + .CLK_OUT_DIV2(clk_design1), + .CLK_OUT_DIV3(clk_design2), + .CLK_OUT_DIV4(clk_design3) + ); + + PLL #(.PLL_MULT(46), .PLL_DIV(1), .PLL_POST_DIV(2)) clk_pll_gen1 ( + .PLL_EN(const1), // PLL Enable + .CLK_IN(clk_pll_in), // Clock input + .CLK_OUT(clk_design4), + .CLK_OUT_DIV2(clk_design5), + .CLK_OUT_DIV3(clk_design6), + .CLK_OUT_DIV4(clk_design7) + ); + + + always @(posedge clk_design0) begin + if(enable_design[0])data_o_design[0] <= data_design[0]; + end + + always @(posedge clk_design1) begin + if(enable_design[1])data_o_design[1] <= data_design[1]; + end + + always @(posedge clk_design2) begin + if(enable_design[2])data_o_design[2] <= data_design[2]; + end + + always @(posedge clk_design3) begin + if(enable_design[3])data_o_design[3] <= data_design[3]; + end + + always @(posedge clk_design4) begin + if(enable_design[4])data_o_design[4] <= data_design[4]; + end + + always @(posedge clk_design5) begin + if(enable_design[5])data_o_design[5] <= data_design[5]; + end + + always @(posedge clk_design6) begin + if(enable_design[6])data_o_design[6] <= data_design[6]; + end + + always @(posedge clk_design7) begin + if(enable_design[7])data_o_design[7] <= data_design[7]; + end + +endmodule \ No newline at end of file diff --git a/GJC-35/raptor.tcl b/GJC-35/raptor.tcl new file mode 100644 index 00000000..228cffbc --- /dev/null +++ b/GJC-35/raptor.tcl @@ -0,0 +1,14 @@ +create_design pll_8_clocks_posedge +add_design_file pll_8_clocks_posedge.v +set_top_module pll_8_clocks_posedge +# add_constraint_file constraints.sdc +add_constraint_file pin_constraints.pin +target_device 1VG28 + +analyze +synthesize +packing +place +route +sta +bitstream diff --git a/GJC-36/pin_constraints.pin b/GJC-36/pin_constraints.pin new file mode 100644 index 00000000..2b62c380 --- /dev/null +++ b/GJC-36/pin_constraints.pin @@ -0,0 +1,75 @@ + +set_property mode Mode_BP_SDR_A_RX HR_1_0_0P +set_pin_loc data_i[0] HR_1_0_0P + +set_property mode Mode_BP_SDR_A_RX HR_1_2_1P +set_pin_loc data_i[1] HR_1_2_1P + +set_property mode Mode_BP_SDR_A_RX HR_1_4_2P +set_pin_loc data_i[2] HR_1_4_2P + +set_property mode Mode_BP_SDR_A_RX HR_1_6_3P +set_pin_loc data_i[3] HR_1_6_3P + +set_property mode Mode_BP_SDR_A_RX HR_2_0_0P +set_pin_loc data_i[4] HR_2_0_0P + +set_property mode Mode_BP_SDR_A_RX HR_2_2_1P +set_pin_loc data_i[5] HR_2_2_1P + +set_property mode Mode_BP_SDR_A_RX HR_2_4_2P +set_pin_loc data_i[6] HR_2_4_2P + +set_property mode Mode_BP_SDR_A_RX HR_2_6_3P +set_pin_loc data_i[7] HR_2_6_3P + + + +set_property mode Mode_BP_SDR_A_TX HR_1_8_4P +set_pin_loc data_o[0] HR_1_8_4P + +set_property mode Mode_BP_SDR_A_TX HR_1_12_6P +set_pin_loc data_o[1] HR_1_12_6P + +set_property mode Mode_BP_SDR_A_TX HR_1_14_7P +set_pin_loc data_o[2] HR_1_14_7P + +set_property mode Mode_BP_SDR_A_TX HR_1_16_8P +set_pin_loc data_o[3] HR_1_16_8P + +set_property mode Mode_BP_SDR_A_TX HR_2_8_4P +set_pin_loc data_o[4] HR_2_8_4P + +set_property mode Mode_BP_SDR_A_TX HR_2_12_6P +set_pin_loc data_o[5] HR_2_12_6P + +set_property mode Mode_BP_SDR_A_TX HR_2_14_7P +set_pin_loc data_o[6] HR_2_14_7P + +set_property mode Mode_BP_SDR_A_TX HR_2_16_8P +set_pin_loc data_o[7] HR_2_16_8P + + +set_property mode Mode_BP_SDR_A_RX HR_1_18_9P +set_pin_loc enable[0] HR_1_18_9P + +set_property mode Mode_BP_SDR_A_RX HR_1_20_10P +set_pin_loc enable[1] HR_1_20_10P + +set_property mode Mode_BP_SDR_A_RX HR_1_22_11P +set_pin_loc enable[2] HR_1_22_11P + +set_property mode Mode_BP_SDR_A_RX HR_1_24_12P +set_pin_loc enable[3] HR_1_24_12P + +set_property mode Mode_BP_SDR_A_RX HR_2_18_9P +set_pin_loc enable[4] HR_2_18_9P + +set_property mode Mode_BP_SDR_A_RX HR_2_20_10P +set_pin_loc enable[5] HR_2_20_10P + +set_property mode Mode_BP_SDR_A_RX HR_2_22_11P +set_pin_loc enable[6] HR_2_22_11P + +set_property mode Mode_BP_SDR_A_RX HR_2_24_12P +set_pin_loc enable[7] HR_2_24_12P \ No newline at end of file diff --git a/GJC-36/pll_8_clocks_negedge.v b/GJC-36/pll_8_clocks_negedge.v new file mode 100644 index 00000000..cb0a3660 --- /dev/null +++ b/GJC-36/pll_8_clocks_negedge.v @@ -0,0 +1,108 @@ +//*********************************************************** +// Functionality: Flip FLop design with boot clk as pll source +// Author: Azfar +//*********************************************************** + + +module pll_8_clocks_negedge ( + input wire [7:0] data_i, + input wire [7:0] enable, + output wire [7:0] data_o +); + wire const1; + wire clk_design0, clk_design1, clk_design2, clk_design3; + wire clk_design4, clk_design5, clk_design6, clk_design7; + wire clk_pll_in; + wire [7:0] data_design; + wire [7:0] enable_design; + reg [7:0] data_o_design; + + assign const1 = 1; + + I_BUF #(.WEAK_KEEPER("PULLDOWN")) data_i_buffer0 (.I(data_i[0]), .EN(const1), .O(data_design[0])); + I_BUF #(.WEAK_KEEPER("PULLDOWN")) enable_buffer0 (.I(enable[0]), .EN(const1), .O(enable_design[0])); + O_BUF data_o_buffer0 (.I(data_o_design[0]), .O(data_o[0])); + + I_BUF #(.WEAK_KEEPER("PULLDOWN")) data_i_buffer1 (.I(data_i[1]), .EN(const1), .O(data_design[1])); + I_BUF #(.WEAK_KEEPER("PULLDOWN")) enable_buffer1 (.I(enable[1]), .EN(const1), .O(enable_design[1])); + O_BUF data_o_buffer1 (.I(data_o_design[1]), .O(data_o[1])); + + I_BUF #(.WEAK_KEEPER("PULLDOWN")) data_i_buffer2 (.I(data_i[2]), .EN(const1), .O(data_design[2])); + I_BUF #(.WEAK_KEEPER("PULLDOWN")) enable_buffer2 (.I(enable[2]), .EN(const1), .O(enable_design[2])); + O_BUF data_o_buffer2 (.I(data_o_design[2]), .O(data_o[2])); + + I_BUF #(.WEAK_KEEPER("PULLDOWN")) data_i_buffer3 (.I(data_i[3]), .EN(const1), .O(data_design[3])); + I_BUF #(.WEAK_KEEPER("PULLDOWN")) enable_buffer3 (.I(enable[3]), .EN(const1), .O(enable_design[3])); + O_BUF data_o_buffer3 (.I(data_o_design[3]), .O(data_o[3])); + + I_BUF #(.WEAK_KEEPER("PULLDOWN")) data_i_buffer4 (.I(data_i[4]), .EN(const1), .O(data_design[4])); + I_BUF #(.WEAK_KEEPER("PULLDOWN")) enable_buffer4 (.I(enable[4]), .EN(const1), .O(enable_design[4])); + O_BUF data_o_buffer4 (.I(data_o_design[4]), .O(data_o[4])); + + I_BUF #(.WEAK_KEEPER("PULLDOWN")) data_i_buffer5 (.I(data_i[5]), .EN(const1), .O(data_design[5])); + I_BUF #(.WEAK_KEEPER("PULLDOWN")) enable_buffer5 (.I(enable[5]), .EN(const1), .O(enable_design[5])); + O_BUF data_o_buffer5 (.I(data_o_design[5]), .O(data_o[5])); + + I_BUF #(.WEAK_KEEPER("PULLDOWN")) data_i_buffer6 (.I(data_i[6]), .EN(const1), .O(data_design[6])); + I_BUF #(.WEAK_KEEPER("PULLDOWN")) enable_buffer6 (.I(enable[6]), .EN(const1), .O(enable_design[6])); + O_BUF data_o_buffer6 (.I(data_o_design[6]), .O(data_o[6])); + + I_BUF #(.WEAK_KEEPER("PULLDOWN")) data_i_buffer7 (.I(data_i[7]), .EN(const1), .O(data_design[7])); + I_BUF #(.WEAK_KEEPER("PULLDOWN")) enable_buffer7 (.I(enable[7]), .EN(const1), .O(enable_design[7])); + O_BUF data_o_buffer7 (.I(data_o_design[7]), .O(data_o[7])); + + + BOOT_CLOCK internal_osc (clk_pll_in); + + PLL #(.PLL_MULT(40), .PLL_DIV(1), .PLL_POST_DIV(2)) clk_pll_gen0 ( + .PLL_EN(const1), // PLL Enable + .CLK_IN(clk_pll_in), // Clock input + .CLK_OUT(clk_design0), + .CLK_OUT_DIV2(clk_design1), + .CLK_OUT_DIV3(clk_design2), + .CLK_OUT_DIV4(clk_design3) + ); + + PLL #(.PLL_MULT(46), .PLL_DIV(1), .PLL_POST_DIV(2)) clk_pll_gen1 ( + .PLL_EN(const1), // PLL Enable + .CLK_IN(clk_pll_in), // Clock input + .CLK_OUT(clk_design4), + .CLK_OUT_DIV2(clk_design5), + .CLK_OUT_DIV3(clk_design6), + .CLK_OUT_DIV4(clk_design7) + ); + + + always @(negedge clk_design0) begin + if(enable_design[0])data_o_design[0] <= data_design[0]; + end + + always @(negedge clk_design1) begin + if(enable_design[1])data_o_design[1] <= data_design[1]; + end + + always @(negedge clk_design2) begin + if(enable_design[2])data_o_design[2] <= data_design[2]; + end + + always @(negedge clk_design3) begin + if(enable_design[3])data_o_design[3] <= data_design[3]; + end + + always @(negedge clk_design4) begin + if(enable_design[4])data_o_design[4] <= data_design[4]; + end + + always @(negedge clk_design5) begin + if(enable_design[5])data_o_design[5] <= data_design[5]; + end + + always @(negedge clk_design6) begin + if(enable_design[6])data_o_design[6] <= data_design[6]; + end + + always @(negedge clk_design7) begin + if(enable_design[7])data_o_design[7] <= data_design[7]; + end + +endmodule \ No newline at end of file diff --git a/GJC-36/raptor.tcl b/GJC-36/raptor.tcl new file mode 100644 index 00000000..d02203e0 --- /dev/null +++ b/GJC-36/raptor.tcl @@ -0,0 +1,14 @@ +create_design pll_8_clocks_negedge +add_design_file pll_8_clocks_negedge.v +set_top_module pll_8_clocks_negedge +# add_constraint_file constraints.sdc +add_constraint_file pin_constraints.pin +target_device 1VG28 + +analyze +synthesize +packing +place +route +sta +bitstream From caf2157818a1458f9c8292118a961abdfdfd81c7 Mon Sep 17 00:00:00 2001 From: valence-e Date: Tue, 23 Apr 2024 11:57:42 +0500 Subject: [PATCH 2/3] added new designs for o_serdes --- GJC-37/o_serdes_x3_o_delay_o_buf.v | 86 ++++++++++++++++++++++++++++++ GJC-37/pin_constraints.pin | 9 ++++ GJC-37/raptor.tcl | 14 +++++ GJC-38/o_serdes_x4_o_delay_o_buf.v | 86 ++++++++++++++++++++++++++++++ GJC-38/pin_constraints.pin | 9 ++++ GJC-38/raptor.tcl | 14 +++++ 6 files changed, 218 insertions(+) create mode 100644 GJC-37/o_serdes_x3_o_delay_o_buf.v create mode 100644 GJC-37/pin_constraints.pin create mode 100644 GJC-37/raptor.tcl create mode 100644 GJC-38/o_serdes_x4_o_delay_o_buf.v create mode 100644 GJC-38/pin_constraints.pin create mode 100644 GJC-38/raptor.tcl diff --git a/GJC-37/o_serdes_x3_o_delay_o_buf.v b/GJC-37/o_serdes_x3_o_delay_o_buf.v new file mode 100644 index 00000000..cec4c399 --- /dev/null +++ b/GJC-37/o_serdes_x3_o_delay_o_buf.v @@ -0,0 +1,86 @@ +//*********************************************************** +// Functionality: counter sending its count value out through o_serdes +// using a pll clock dividers +// Author: Azfar +//*********************************************************** + + +module o_serdes_x3_o_delay_o_buf ( + input wire reset, // asynchronous active high + input wire enable_n, // active low enable + output wire data_o +); + parameter WIDTH = 3; + + reg [WIDTH - 1:0] counter; + wire clk_pll_in; + wire const1; + wire pll_clk; + wire pll_clk_div3; + wire pll_lock; + wire reset_buf, reset_buf_n; + wire enable_buf_n,enable_buf; + wire buf_output_enable; + wire delay_in; + wire delay_out; + + assign const1 = 1; + assign reset_buf_n = ~reset_buf; + assign enable_buf = ~enable_buf_n; + + + + + I_BUF #(.WEAK_KEEPER("PULLDOWN")) reset_buffer0 (.I(reset), .EN(const1), .O(reset_buf)); + I_BUF #(.WEAK_KEEPER("PULLUP")) enable_buffer0 (.I(enable_n), .EN(const1), .O(enable_buf_n)); + + BOOT_CLOCK internal_osc (clk_pll_in); + + PLL #(.PLL_MULT(40), .PLL_DIV(1), .PLL_POST_DIV(2)) clk_pll_gen0 ( + .PLL_EN(const1), // PLL Enable + .CLK_IN(clk_pll_in), // Clock input + .CLK_OUT(pll_clk), + .CLK_OUT_DIV3(pll_clk_div3), + .LOCK(pll_lock) + ); + + O_SERDES #( + .DATA_RATE("SDR"), // Single or double data rate (SDR/DDR) + .WIDTH(WIDTH) // Width of input data to serializer (3-10) + ) counter_o_serdes ( + .D(counter), // D input bus + .RST(reset_buf_n), // Active-low, asynchronous reset + .LOAD_WORD(enable_buf), // Load word input + .CLK_IN(pll_clk_div3), // Fabric clock input + .OE_IN(enable_buf), // Output tri-state enable input + .OE_OUT(buf_output_enable), // Output tri-state enable output (conttect to O_BUFT or inferred tri-state signal) + .Q(delay_in), // Data output (Connect to output port, buffer or O_DELAY) + .PLL_LOCK(pll_lock), // PLL lock input + .PLL_CLK(pll_clk) // PLL clock input + ); + + O_DELAY #( + .DELAY(0) // TAP delay value (0-63) + ) counter_o_delay ( + .I(delay_in), // Data input + .DLY_LOAD(~const1), // Delay load input + .DLY_ADJ(~const1), // Delay adjust input + .DLY_INCDEC(~const1), // Delay increment / decrement input + .CLK_IN(pll_clk), // Clock input + .O(delay_out) // Data output + ); + + O_BUFT counter_o_buft ( + .I(delay_out), // Data input + .T(buf_output_enable), // Tri-state output + .O(data_o) // Data output (connect to top-level port) + ); + + + always @(posedge pll_clk_div3 or negedge reset_buf_n) begin + if(!reset_buf_n)counter <= 0; + else if(enable_buf) counter <= counter + 1; + end + + +endmodule \ No newline at end of file diff --git a/GJC-37/pin_constraints.pin b/GJC-37/pin_constraints.pin new file mode 100644 index 00000000..aefba0b1 --- /dev/null +++ b/GJC-37/pin_constraints.pin @@ -0,0 +1,9 @@ + +set_property mode Mode_BP_SDR_A_RX HR_1_0_0P +set_pin_loc reset HR_1_0_0P + +set_property mode Mode_BP_SDR_A_RX HR_1_2_1P +set_pin_loc enable_n HR_1_2_1P + +set_property mode Mode_BP_SDR_A_TX HR_1_8_4P +set_pin_loc data_o HR_1_8_4P diff --git a/GJC-37/raptor.tcl b/GJC-37/raptor.tcl new file mode 100644 index 00000000..718cac72 --- /dev/null +++ b/GJC-37/raptor.tcl @@ -0,0 +1,14 @@ +create_design o_serdes_x3_o_delay_o_buf +add_design_file o_serdes_x3_o_delay_o_buf.v +set_top_module o_serdes_x3_o_delay_o_buf +# add_constraint_file constraints.sdc +add_constraint_file pin_constraints.pin +target_device 1VG28 + +analyze +synthesize +packing +place +route +sta +bitstream diff --git a/GJC-38/o_serdes_x4_o_delay_o_buf.v b/GJC-38/o_serdes_x4_o_delay_o_buf.v new file mode 100644 index 00000000..66366553 --- /dev/null +++ b/GJC-38/o_serdes_x4_o_delay_o_buf.v @@ -0,0 +1,86 @@ +//*********************************************************** +// Functionality: counter sending its count value out through o_serdes +// using a pll clock dividers +// Author: Azfar +//*********************************************************** + + +module o_serdes_x4_o_delay_o_buf ( + input wire reset, // asynchronous active high + input wire enable_n, // active low enable + output wire data_o +); + parameter WIDTH = 4; + + reg [WIDTH - 1:0] counter; + wire clk_pll_in; + wire const1; + wire pll_clk; + wire pll_clk_div4; + wire pll_lock; + wire reset_buf, reset_buf_n; + wire enable_buf_n,enable_buf; + wire buf_output_enable; + wire delay_in; + wire delay_out; + + assign const1 = 1; + assign reset_buf_n = ~reset_buf; + assign enable_buf = ~enable_buf_n; + + + + + I_BUF #(.WEAK_KEEPER("PULLDOWN")) reset_buffer0 (.I(reset), .EN(const1), .O(reset_buf)); + I_BUF #(.WEAK_KEEPER("PULLUP")) enable_buffer0 (.I(enable_n), .EN(const1), .O(enable_buf_n)); + + BOOT_CLOCK internal_osc (clk_pll_in); + + PLL #(.PLL_MULT(40), .PLL_DIV(1), .PLL_POST_DIV(2)) clk_pll_gen0 ( + .PLL_EN(const1), // PLL Enable + .CLK_IN(clk_pll_in), // Clock input + .CLK_OUT(pll_clk), + .CLK_OUT_DIV4(pll_clk_div4), + .LOCK(pll_lock) + ); + + O_SERDES #( + .DATA_RATE("SDR"), // Single or double data rate (SDR/DDR) + .WIDTH(WIDTH) // Width of input data to serializer (3-10) + ) counter_o_serdes ( + .D(counter), // D input bus + .RST(reset_buf_n), // Active-low, asynchronous reset + .LOAD_WORD(enable_buf), // Load word input + .CLK_IN(pll_clk_div4), // Fabric clock input + .OE_IN(enable_buf), // Output tri-state enable input + .OE_OUT(buf_output_enable), // Output tri-state enable output (conttect to O_BUFT or inferred tri-state signal) + .Q(delay_in), // Data output (Connect to output port, buffer or O_DELAY) + .PLL_LOCK(pll_lock), // PLL lock input + .PLL_CLK(pll_clk) // PLL clock input + ); + + O_DELAY #( + .DELAY(0) // TAP delay value (0-63) + ) counter_o_delay ( + .I(delay_in), // Data input + .DLY_LOAD(~const1), // Delay load input + .DLY_ADJ(~const1), // Delay adjust input + .DLY_INCDEC(~const1), // Delay increment / decrement input + .CLK_IN(pll_clk), // Clock input + .O(delay_out) // Data output + ); + + O_BUFT counter_o_buft ( + .I(delay_out), // Data input + .T(buf_output_enable), // Tri-state output + .O(data_o) // Data output (connect to top-level port) + ); + + + always @(posedge pll_clk_div4 or negedge reset_buf_n) begin + if(!reset_buf_n)counter <= 0; + else if(enable_buf) counter <= counter + 1; + end + + +endmodule \ No newline at end of file diff --git a/GJC-38/pin_constraints.pin b/GJC-38/pin_constraints.pin new file mode 100644 index 00000000..aefba0b1 --- /dev/null +++ b/GJC-38/pin_constraints.pin @@ -0,0 +1,9 @@ + +set_property mode Mode_BP_SDR_A_RX HR_1_0_0P +set_pin_loc reset HR_1_0_0P + +set_property mode Mode_BP_SDR_A_RX HR_1_2_1P +set_pin_loc enable_n HR_1_2_1P + +set_property mode Mode_BP_SDR_A_TX HR_1_8_4P +set_pin_loc data_o HR_1_8_4P diff --git a/GJC-38/raptor.tcl b/GJC-38/raptor.tcl new file mode 100644 index 00000000..ee742361 --- /dev/null +++ b/GJC-38/raptor.tcl @@ -0,0 +1,14 @@ +create_design o_serdes_x4_o_delay_o_buf +add_design_file o_serdes_x4_o_delay_o_buf.v +set_top_module o_serdes_x4_o_delay_o_buf +# add_constraint_file constraints.sdc +add_constraint_file pin_constraints.pin +target_device 1VG28 + +analyze +synthesize +packing +place +route +sta +bitstream From 3b848bdc1dc96590f916ffd4400703160e193515 Mon Sep 17 00:00:00 2001 From: valence-e Date: Wed, 24 Apr 2024 12:21:30 +0500 Subject: [PATCH 3/3] added o_serdes clk design --- GJC-39/o_serdes_x4_o_delay_o_buf_o_clk.v | 98 ++++++++++++++++++++++++ GJC-39/pin_constraints.pin | 12 +++ GJC-39/raptor.tcl | 14 ++++ 3 files changed, 124 insertions(+) create mode 100644 GJC-39/o_serdes_x4_o_delay_o_buf_o_clk.v create mode 100644 GJC-39/pin_constraints.pin create mode 100644 GJC-39/raptor.tcl diff --git a/GJC-39/o_serdes_x4_o_delay_o_buf_o_clk.v b/GJC-39/o_serdes_x4_o_delay_o_buf_o_clk.v new file mode 100644 index 00000000..2e062cfe --- /dev/null +++ b/GJC-39/o_serdes_x4_o_delay_o_buf_o_clk.v @@ -0,0 +1,98 @@ +//*********************************************************** +// Functionality: counter sending its count value out through o_serdes +// using a pll clock dividers +// Author: Azfar +//*********************************************************** + + +module o_serdes_x4_o_delay_o_buf_o_clk ( + input wire reset, // asynchronous active high + input wire enable_n, // active low enable + output wire data_o, + output wire clk_o +); + parameter WIDTH = 4; + + reg [WIDTH - 1:0] counter; + wire clk_pll_in; + wire const1; + wire pll_clk; + wire pll_clk_div4; + wire pll_lock; + wire reset_buf, reset_buf_n; + wire enable_buf_n,enable_buf; + wire buf_output_enable; + wire delay_in; + wire delay_out; + wire clk_buf_in; + + assign const1 = 1; + assign reset_buf_n = ~reset_buf; + assign enable_buf = ~enable_buf_n; + + + + + I_BUF #(.WEAK_KEEPER("PULLDOWN")) reset_buffer0 (.I(reset), .EN(const1), .O(reset_buf)); + I_BUF #(.WEAK_KEEPER("PULLUP")) enable_buffer0 (.I(enable_n), .EN(const1), .O(enable_buf_n)); + + BOOT_CLOCK internal_osc (clk_pll_in); + + PLL #(.PLL_MULT(40), .PLL_DIV(1), .PLL_POST_DIV(2)) clk_pll_gen0 ( + .PLL_EN(const1), // PLL Enable + .CLK_IN(clk_pll_in), // Clock input + .CLK_OUT(pll_clk), + .CLK_OUT_DIV4(pll_clk_div4), + .LOCK(pll_lock) + ); + + O_SERDES #( + .DATA_RATE("SDR"), // Single or double data rate (SDR/DDR) + .WIDTH(WIDTH) // Width of input data to serializer (3-10) + ) counter_o_serdes ( + .D(counter), // D input bus + .RST(reset_buf_n), // Active-low, asynchronous reset + .LOAD_WORD(enable_buf), // Load word input + .CLK_IN(pll_clk_div4), // Fabric clock input + .OE_IN(enable_buf), // Output tri-state enable input + .OE_OUT(buf_output_enable), // Output tri-state enable output (conttect to O_BUFT or inferred tri-state signal) + .Q(delay_in), // Data output (Connect to output port, buffer or O_DELAY) + .PLL_LOCK(pll_lock), // PLL lock input + .PLL_CLK(pll_clk) // PLL clock input + ); + + O_DELAY #( + .DELAY(0) // TAP delay value (0-63) + ) counter_o_delay ( + .I(delay_in), // Data input + .DLY_LOAD(~const1), // Delay load input + .DLY_ADJ(~const1), // Delay adjust input + .DLY_INCDEC(~const1), // Delay increment / decrement input + .CLK_IN(pll_clk), // Clock input + .O(delay_out) // Data output + ); + + O_BUFT counter_o_buft ( + .I(delay_out), // Data input + .T(buf_output_enable), // Tri-state output + .O(data_o) // Data output (connect to top-level port) + ); + + + O_SERDES_CLK clock_output ( + .CLK_EN(const1), // Gates output OUTPUT_CLK + .OUTPUT_CLK(clk_buf_in), // Clock output (Connect to output port, buffer or O_DELAY) + .PLL_LOCK(pll_lock), // PLL lock input + .PLL_CLK(pll_clk) // PLL clock input + ); + + O_BUF output_clock_buffer (clk_buf_in,clk_o); + + + always @(posedge pll_clk_div4 or negedge reset_buf_n) begin + if(!reset_buf_n)counter <= 0; + else if(enable_buf) counter <= counter + 1; + end + + +endmodule \ No newline at end of file diff --git a/GJC-39/pin_constraints.pin b/GJC-39/pin_constraints.pin new file mode 100644 index 00000000..5dfe93b6 --- /dev/null +++ b/GJC-39/pin_constraints.pin @@ -0,0 +1,12 @@ + +set_property mode Mode_BP_SDR_A_RX HR_1_0_0P +set_pin_loc reset HR_1_0_0P + +set_property mode Mode_BP_SDR_A_RX HR_1_2_1P +set_pin_loc enable_n HR_1_2_1P + +set_property mode Mode_BP_SDR_A_TX HR_1_8_4P +set_pin_loc data_o HR_1_8_4P + +set_property mode Mode_BP_SDR_A_TX HP_2_CC_10_5P +set_pin_loc clk_o HP_2_CC_10_5P \ No newline at end of file diff --git a/GJC-39/raptor.tcl b/GJC-39/raptor.tcl new file mode 100644 index 00000000..e69204ec --- /dev/null +++ b/GJC-39/raptor.tcl @@ -0,0 +1,14 @@ +create_design o_serdes_x4_o_delay_o_buf_o_clk +add_design_file o_serdes_x4_o_delay_o_buf_o_clk.v +set_top_module o_serdes_x4_o_delay_o_buf_o_clk +# add_constraint_file constraints.sdc +add_constraint_file pin_constraints.pin +target_device 1VG28 + +analyze +synthesize +packing +place +route +sta +bitstream