diff --git a/EDA-3304/clk_buf_primitive_inst/clk_buf_primitive_inst.ospr b/EDA-3304/clk_buf_primitive_inst/clk_buf_primitive_inst.ospr new file mode 100644 index 00000000..c2a3bbee --- /dev/null +++ b/EDA-3304/clk_buf_primitive_inst/clk_buf_primitive_inst.ospr @@ -0,0 +1,76 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/analysis/analysis.rpt b/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/analysis/analysis.rpt new file mode 100644 index 00000000..f8d4b9b8 --- /dev/null +++ b/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/analysis/analysis.rpt @@ -0,0 +1,140 @@ +/******************************************************************************* +Copyright (c) 2022-2024 Rapid Silicon +This source code contains proprietary information belonging to Rapid Silicon +(the "licensor") released under license and non-disclosure agreement to the +recipient (the "licensee"). + +The information shared and protected by the license and non-disclosure agreement +includes but is not limited to the following: +* operational algorithms of the product +* logos, graphics, source code, and visual presentation of the product +* confidential operational information of the licensor + +The recipient of this source code is NOT permitted to publicly disclose, +re-use, archive beyond the period of the license agreement, transfer to a +sub-licensee, or re-implement any portion of the content covered by the license +and non-disclosure agreement without the prior written consent of the licensor. +*********************************************************************************/ + +Version : 2024.10 +Build : 1.2.18 +Hash : 82370d4 +Date : Oct 12 2024 +Type : Engineering +Log Time : Mon Oct 14 05:17:32 2024 GMT +/******************************************************************************* +Copyright (c) 2022-2024 Rapid Silicon +This source code contains proprietary information belonging to Rapid Silicon +(the "licensor") released under license and non-disclosure agreement to the +recipient (the "licensee"). + +The information shared and protected by the license and non-disclosure agreement +includes but is not limited to the following: +* operational algorithms of the product +* logos, graphics, source code, and visual presentation of the product +* confidential operational information of the licensor + +The recipient of this source code is NOT permitted to publicly disclose, +re-use, archive beyond the period of the license agreement, transfer to a +sub-licensee, or re-implement any portion of the content covered by the license +and non-disclosure agreement without the prior written consent of the licensor. +*********************************************************************************/ + +Version : 2024.10 +Build : 1.2.18 +Hash : 82370d4 +Date : Oct 12 2024 +Type : Engineering +Log Time : Mon Oct 14 05:17:32 2024 GMT + + /----------------------------------------------------------------------------\ + | yosys -- Yosys Open SYnthesis Suite | + | Copyright (C) 2012 - 2024 Claire Xenia Wolf | + | Distributed under an ISC-like license, type "license" to see terms | + \----------------------------------------------------------------------------/ + + Yosys 0.44 (git sha1 7a4a3768c, g++ 11.2.1 -fPIC -O3) + +-- Executing script file `/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/clk_buf_primitive_inst/run_1/synth_1_1/analysis/clk_buf_primitive_inst_analyzer.cmd' -- + +1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v +Parsing SystemVerilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v' to AST representation. +Generating RTLIL representation for module `\BOOT_CLOCK'. +Generating RTLIL representation for module `\CARRY'. +Generating RTLIL representation for module `\CLK_BUF'. +Generating RTLIL representation for module `\DFFNRE'. +Generating RTLIL representation for module `\DFFRE'. +Generating RTLIL representation for module `\DLY_SEL_DCODER'. +Generating RTLIL representation for module `\DLY_SEL_DECODER'. +Generating RTLIL representation for module `\DLY_VALUE_MUX'. +Generating RTLIL representation for module `\DSP19X2'. +Generating RTLIL representation for module `\DSP38'. +Generating RTLIL representation for module `\FCLK_BUF'. +Generating RTLIL representation for module `\FIFO18KX2'. +Generating RTLIL representation for module `\FIFO36K'. +Generating RTLIL representation for module `\I_BUF_DS'. +Generating RTLIL representation for module `\I_BUF'. +Generating RTLIL representation for module `\I_DDR'. +Generating RTLIL representation for module `\I_DELAY'. +Generating RTLIL representation for module `\I_FAB'. +Generating RTLIL representation for module `\I_SERDES'. +Generating RTLIL representation for module `\LATCHNR'. +Generating RTLIL representation for module `\LATCHNS'. +Generating RTLIL representation for module `\LATCHN'. +Generating RTLIL representation for module `\LATCHR'. +Generating RTLIL representation for module `\LATCHS'. +Generating RTLIL representation for module `\LATCH'. +Generating RTLIL representation for module `\LUT1'. +Generating RTLIL representation for module `\LUT2'. +Generating RTLIL representation for module `\LUT3'. +Generating RTLIL representation for module `\LUT4'. +Generating RTLIL representation for module `\LUT5'. +Generating RTLIL representation for module `\LUT6'. +Generating RTLIL representation for module `\MIPI_RX'. +Generating RTLIL representation for module `\MIPI_TX'. +Generating RTLIL representation for module `\O_BUF_DS'. +Generating RTLIL representation for module `\O_BUFT_DS'. +Generating RTLIL representation for module `\O_BUFT'. +Generating RTLIL representation for module `\O_BUF'. +Generating RTLIL representation for module `\O_DDR'. +Generating RTLIL representation for module `\O_DELAY'. +Generating RTLIL representation for module `\O_FAB'. +Generating RTLIL representation for module `\O_SERDES_CLK'. +Generating RTLIL representation for module `\O_SERDES'. +Generating RTLIL representation for module `\PLL'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AHB_M'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AHB_S'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AXI_M0'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AXI_M1'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_DMA'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_IRQ'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_JTAG'. +Generating RTLIL representation for module `\SOC_FPGA_TEMPERATURE'. +Generating RTLIL representation for module `\TDP_RAM18KX2'. +Generating RTLIL representation for module `\TDP_RAM36K'. +Successfully finished Verilog frontend. + +2. Executing Verilog-2005 frontend: /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v +Parsing Verilog input from `/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v' to AST representation. +Generating RTLIL representation for module `\clk_buf_primitive_inst'. +Successfully finished Verilog frontend. + +-- Running command `hierarchy -top clk_buf_primitive_inst' -- + +3. Executing HIERARCHY pass (managing design hierarchy). + +3.1. Analyzing design hierarchy.. +Top module: \clk_buf_primitive_inst + +3.2. Analyzing design hierarchy.. +Top module: \clk_buf_primitive_inst +Removed 0 unused modules. + +Dumping file hier_info.json ... + Process module "CLK_BUF" + Process module "I_BUF" +Dumping file port_info.json ... + +End of script. Logfile hash: 835a24a3cc, CPU: user 0.02s system 0.01s, MEM: 15.87 MB peak +Yosys 0.44 (git sha1 7a4a3768c, g++ 11.2.1 -fPIC -O3) +Time spent: 94% 4x read_verilog (0 sec), 4% 1x analyze (0 sec), ... diff --git a/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/analysis/clk_buf_primitive_inst_analyzer.cmd b/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/analysis/clk_buf_primitive_inst_analyzer.cmd new file mode 100644 index 00000000..b977dd2a --- /dev/null +++ b/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/analysis/clk_buf_primitive_inst_analyzer.cmd @@ -0,0 +1,5 @@ +read_verilog -sv /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v +verilog_defines +read_verilog -I../../../.././rtl -I../../../../ -I/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v + +analyze -top clk_buf_primitive_inst diff --git a/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/analysis/hier_info.json b/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/analysis/hier_info.json new file mode 100644 index 00000000..1af1933d --- /dev/null +++ b/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/analysis/hier_info.json @@ -0,0 +1,158 @@ +{ + "fileIDs": { + "1": "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v", + "2": "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v" + }, + "hierTree": [ + { + "file": "2", + "internalSignals": [ + { + "name": "wire1", + "range": { + "lsb": 0, + "msb": 0 + }, + "type": "LOGIC" + }, + { + "name": "wire2", + "range": { + "lsb": 0, + "msb": 0 + }, + "type": "LOGIC" + }, + { + "name": "wire_out_clk", + "range": { + "lsb": 0, + "msb": 0 + }, + "type": "LOGIC" + } + ], + "language": "SystemVerilog", + "line": 1, + "moduleInsts": [ + { + "file": "2", + "instName": "clk_buf_inst", + "line": 21, + "module": "CLK_BUF", + "parameters": [] + }, + { + "file": "2", + "instName": "i_buf_inst", + "line": 10, + "module": "I_BUF", + "parameters": [] + } + ], + "ports": [ + { + "direction": "Input", + "name": "clock_input", + "range": { + "lsb": 0, + "msb": 0 + }, + "type": "LOGIC" + }, + { + "direction": "Input", + "name": "ibuf_enable", + "range": { + "lsb": 0, + "msb": 0 + }, + "type": "LOGIC" + }, + { + "direction": "Output", + "name": "clock_output", + "range": { + "lsb": 0, + "msb": 0 + }, + "type": "LOGIC" + } + ], + "topModule": "clk_buf_primitive_inst" + } + ], + "modules": { + "CLK_BUF": { + "file": "1", + "language": "SystemVerilog", + "line": 41, + "module": "CLK_BUF", + "ports": [ + { + "direction": "Input", + "name": "I", + "range": { + "lsb": 0, + "msb": 0 + }, + "type": "LOGIC" + }, + { + "direction": "Output", + "name": "O", + "range": { + "lsb": 0, + "msb": 0 + }, + "type": "LOGIC" + } + ] + }, + "I_BUF": { + "file": "1", + "language": "SystemVerilog", + "line": 406, + "module": "I_BUF", + "parameters": [ + { + "name": "IOSTANDARD", + "value": 0 + }, + { + "name": "WEAK_KEEPER", + "value": 0 + } + ], + "ports": [ + { + "direction": "Input", + "name": "I", + "range": { + "lsb": 0, + "msb": 0 + }, + "type": "LOGIC" + }, + { + "direction": "Input", + "name": "EN", + "range": { + "lsb": 0, + "msb": 0 + }, + "type": "LOGIC" + }, + { + "direction": "Output", + "name": "O", + "range": { + "lsb": 0, + "msb": 0 + }, + "type": "LOGIC" + } + ] + } + } +} diff --git a/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/analysis/port_info.json b/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/analysis/port_info.json new file mode 100644 index 00000000..570875f0 --- /dev/null +++ b/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/analysis/port_info.json @@ -0,0 +1,34 @@ +[ + { + "ports": [ + { + "direction": "Input", + "name": "clock_input", + "range": { + "lsb": 0, + "msb": 0 + }, + "type": "LOGIC" + }, + { + "direction": "Input", + "name": "ibuf_enable", + "range": { + "lsb": 0, + "msb": 0 + }, + "type": "LOGIC" + }, + { + "direction": "Output", + "name": "clock_output", + "range": { + "lsb": 0, + "msb": 0 + }, + "type": "LOGIC" + } + ], + "topModule": "clk_buf_primitive_inst" + } +] diff --git a/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/simulate_gate/a.out b/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/simulate_gate/a.out new file mode 100755 index 00000000..4d6b1be5 --- /dev/null +++ b/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/simulate_gate/a.out @@ -0,0 +1,1792 @@ +#! /opt/iverilog/bin/vvp -v +:ivl_version "13.0 (devel)" "(s20221226-498-g52d049b51)"; +:ivl_delay_selection "TYPICAL"; +:vpi_time_precision - 12; +:vpi_module "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/HDL_simulator/iverilog/lib/ivl/system.vpi"; +:vpi_module "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/HDL_simulator/iverilog/lib/ivl/vhdl_sys.vpi"; +:vpi_module "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/HDL_simulator/iverilog/lib/ivl/vhdl_textio.vpi"; +:vpi_module "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/HDL_simulator/iverilog/lib/ivl/v2005_math.vpi"; +:vpi_module "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/HDL_simulator/iverilog/lib/ivl/va_math.vpi"; +:vpi_module "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/HDL_simulator/iverilog/lib/ivl/v2009.vpi"; +S_0x19c6360 .scope package, "$unit" "$unit" 2 1; + .timescale 0 0; +S_0x19bf380 .scope module, "co_sim_clk_buf_primitive_inst" "co_sim_clk_buf_primitive_inst" 3 2; + .timescale -9 -12; +v0x15cce20_0 .var "clock_input", 0 0; +v0x15ce100_0 .net "clock_output", 0 0, L_0x1668090; 1 drivers +v0x15ce250_0 .net "clock_output_netlist", 0 0, L_0x1665850; 1 drivers +v0x15ce3a0_0 .var "ibuf_enable", 0 0; +v0x15cf680_0 .var/i "mismatch", 31 0; +E_0x18397a0 .event negedge, v0x1825b10_0; +S_0x15e4500 .scope task, "compare" "compare" 3 59, 3 59 0, S_0x19bf380; + .timescale -9 -12; +TD_co_sim_clk_buf_primitive_inst.compare ; + %load/vec4 v0x15ce100_0; + %load/vec4 v0x15ce250_0; + %cmp/ne; + %jmp/0xz T_0.0, 6; + %vpi_call/w 3 61 "$display", "Data Mismatch: Actual output: %0d, Netlist Output %0d, Time: %0t ", v0x15ce100_0, v0x15ce250_0, $time {0 0 0}; + %load/vec4 v0x15cf680_0; + %addi 1, 0, 32; + %store/vec4 v0x15cf680_0, 0, 32; + %jmp T_0.1; +T_0.0 ; + %vpi_call/w 3 65 "$display", "Data Matched: Actual output: %0d, Netlist Output %0d, Time: %0t ", v0x15ce100_0, v0x15ce250_0, $time {0 0 0}; +T_0.1 ; + %end; +S_0x19e21b0 .scope module, "golden" "clk_buf_primitive_inst" 3 9, 4 1 0, S_0x19bf380; + .timescale -9 -12; + .port_info 0 /INPUT 1 "clock_input"; + .port_info 1 /INPUT 1 "ibuf_enable"; + .port_info 2 /OUTPUT 1 "clock_output"; +L_0x1668090 .functor BUFZ 1, v0x168de60_0, C4<0>, C4<0>, C4<0>; +v0x199bf80_0 .net "clock_input", 0 0, v0x15cce20_0; 1 drivers +v0x199c720_0 .net "clock_output", 0 0, L_0x1668090; alias, 1 drivers +v0x1834720_0 .net "ibuf_enable", 0 0, v0x15ce3a0_0; 1 drivers +v0x1837ac0_0 .net "wire1", 0 0, L_0x1663b90; 1 drivers +v0x1837c20_0 .net "wire2", 0 0, L_0x15cf7d0; 1 drivers +v0x168de60_0 .var "wire_out_clk", 0 0; +E_0x15d9040 .event posedge, v0x19e6200_0; +S_0x19c5ec0 .scope module, "clk_buf_inst" "CLK_BUF" 4 21, 5 10 1, S_0x19e21b0; + .timescale -9 -12; + .port_info 0 /INPUT 1 "I"; + .port_info 1 /OUTPUT 1 "O"; +L_0x1663b90 .functor BUFZ 1, L_0x15cf7d0, C4<0>, C4<0>, C4<0>; +v0x15c9a90_0 .net "I", 0 0, L_0x15cf7d0; alias, 1 drivers +v0x19e6200_0 .net "O", 0 0, L_0x1663b90; alias, 1 drivers +S_0x19d63d0 .scope module, "i_buf_inst" "I_BUF" 4 10, 6 10 1, S_0x19e21b0; + .timescale -9 -12; + .port_info 0 /INPUT 1 "I"; + .port_info 1 /INPUT 1 "EN"; + .port_info 2 /OUTPUT 1 "O"; +P_0x163d6e0 .param/str "IOSTANDARD" 0 6 12, "DEFAULT"; +P_0x163d720 .param/str "WEAK_KEEPER" 0 6 11, "NONE"; +v0x19e0640_0 .net "EN", 0 0, v0x15ce3a0_0; alias, 1 drivers +v0x1825b10_0 .net "I", 0 0, v0x15cce20_0; alias, 1 drivers +v0x182e060_0 .net "O", 0 0, L_0x15cf7d0; alias, 1 drivers +L_0x7f873cdf4018 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x182deb0_0 .net/2u *"_ivl_0", 0 0, L_0x7f873cdf4018; 1 drivers +L_0x15cf7d0 .functor MUXZ 1, L_0x7f873cdf4018, v0x15cce20_0, v0x15ce3a0_0, C4<>; +S_0x19ccfa0 .scope module, "synth_net" "clk_buf_primitive_inst_post_synth" 3 14, 7 3 0, S_0x19bf380; + .timescale -9 -12; + .port_info 0 /INPUT 1 "clock_input"; + .port_info 1 /INPUT 1 "ibuf_enable"; + .port_info 2 /OUTPUT 1 "clock_output"; +v0x15ca080_0 .net "$f2g_tx_out_wire_out_clk", 0 0, L_0x16655a0; 1 drivers +v0x15ca1d0_0 .net "$ibuf_ibuf_enable", 0 0, L_0x1669b30; 1 drivers +v0x15ca320_0 .net "clock_input", 0 0, v0x15cce20_0; alias, 1 drivers +v0x15cb600_0 .net "clock_output", 0 0, L_0x1665850; alias, 1 drivers +v0x15cb750_0 .net "ibuf_enable", 0 0, v0x15ce3a0_0; alias, 1 drivers +v0x15cb8a0_0 .net "wire1", 0 0, L_0x1665130; 1 drivers +v0x15ccb80_0 .net "wire2", 0 0, L_0x16652a0; 1 drivers +v0x15cccd0_0 .net "wire_out_clk", 0 0, v0x168eb80_0; 1 drivers +S_0x19c02a0 .scope module, "$abc$194$auto_195" "DFFRE" 7 37, 8 11 1, S_0x19ccfa0; + .timescale -9 -12; + .port_info 0 /INPUT 1 "D"; + .port_info 1 /INPUT 1 "R"; + .port_info 2 /INPUT 1 "E"; + .port_info 3 /INPUT 1 "C"; + .port_info 4 /OUTPUT 1 "Q"; +L_0x1664330 .functor AND 1, L_0x1665130, L_0x16652a0, C4<1>, C4<1>; +L_0x1663ec0 .functor AND 1, L_0x1665130, L_0x15cf920, C4<1>, C4<1>; +L_0x1664030 .functor AND 1, L_0x15d0c00, L_0x16652a0, C4<1>, C4<1>; +L_0x1664660 .functor AND 1, L_0x15d0d50, L_0x15d0ea0, C4<1>, C4<1>; +L_0x7f873cdf4060 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>; +L_0x1664990 .functor AND 1, L_0x7f873cdf4060, L_0x16652a0, C4<1>, C4<1>; +L_0x16694d0 .functor AND 1, L_0x7f873cdf4060, L_0x15d2180, C4<1>, C4<1>; +L_0x1664e00 .functor BUFZ 1, L_0x7f873cdf4060, C4<0>, C4<0>, C4<0>; +L_0x1667390 .functor BUFZ 1, L_0x16652a0, C4<0>, C4<0>, C4<0>; +v0x168d170_0 .net "C", 0 0, L_0x1665130; alias, 1 drivers +v0x168e450_0 .net "C_D_SDFCHK", 0 0, L_0x1664330; 1 drivers +v0x168e5c0_0 .net "C_nD_SDFCHK", 0 0, L_0x1663ec0; 1 drivers +v0x168e730_0 .net "D", 0 0, L_0x16652a0; alias, 1 drivers +v0x168e8a0_0 .net "D_SDFCHK", 0 0, L_0x1667390; 1 drivers +L_0x7f873cdf40a8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>; +v0x168ea10_0 .net "E", 0 0, L_0x7f873cdf40a8; 1 drivers +v0x168eb80_0 .var "Q", 0 0; +v0x168ecf0_0 .net "R", 0 0, L_0x7f873cdf4060; 1 drivers +v0x168ee60_0 .net "R_D_SDFCHK", 0 0, L_0x1664990; 1 drivers +v0x168efd0_0 .net "R_SDFCHK", 0 0, L_0x1664e00; 1 drivers +v0x168f140_0 .net "R_nD_SDFCHK", 0 0, L_0x16694d0; 1 drivers +v0x168d870_0 .net *"_ivl_11", 0 0, L_0x15d0d50; 1 drivers +v0x168d9e0_0 .net *"_ivl_13", 0 0, L_0x15d0ea0; 1 drivers +v0x168f2b0_0 .net *"_ivl_19", 0 0, L_0x15d2180; 1 drivers +v0x168f420_0 .net *"_ivl_3", 0 0, L_0x15cf920; 1 drivers +v0x168db50_0 .net *"_ivl_7", 0 0, L_0x15d0c00; 1 drivers +v0x168f590_0 .net "nC_D_SDFCHK", 0 0, L_0x1664030; 1 drivers +v0x168f700_0 .net "nC_nD_SDFCHK", 0 0, L_0x1664660; 1 drivers +E_0x183e400/0 .event negedge, v0x168ecf0_0; +E_0x183e400/1 .event posedge, v0x168d170_0; +E_0x183e400 .event/or E_0x183e400/0, E_0x183e400/1; +L_0x15cf920 .reduce/nor L_0x16652a0; +L_0x15d0c00 .reduce/nor L_0x1665130; +L_0x15d0d50 .reduce/nor L_0x1665130; +L_0x15d0ea0 .reduce/nor L_0x16652a0; +L_0x15d2180 .reduce/nor L_0x16652a0; +S_0x19bfab0 .scope module, "$f2g_tx_out_wire_out_clk_1" "O_FAB" 7 45, 9 10 1, S_0x19ccfa0; + .timescale -9 -12; + .port_info 0 /INPUT 1 "I"; + .port_info 1 /OUTPUT 1 "O"; +L_0x16655a0 .functor BUFZ 1, v0x168eb80_0, C4<0>, C4<0>, C4<0>; +v0x168f870_0 .net "I", 0 0, v0x168eb80_0; alias, 1 drivers +v0x168f9e0_0 .net "O", 0 0, L_0x16655a0; alias, 1 drivers +S_0x19c4fd0 .scope module, "$ibuf$clk_buf_primitive_inst.$ibuf_clock_input" "I_BUF" 7 54, 6 10 1, S_0x19ccfa0; + .timescale -9 -12; + .port_info 0 /INPUT 1 "I"; + .port_info 1 /INPUT 1 "EN"; + .port_info 2 /OUTPUT 1 "O"; +P_0x1881930 .param/str "IOSTANDARD" 0 6 12, "DEFAULT"; +P_0x1881970 .param/str "WEAK_KEEPER" 0 6 11, "NONE"; +L_0x16652a0 .functor BUFT 1, v0x15cce20_0, C4<0>, C4<0>, C4<0>; +L_0x7f873cdf40f0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>; +v0x18782a0_0 .net "EN", 0 0, L_0x7f873cdf40f0; 1 drivers +v0x18780f0_0 .net "I", 0 0, v0x15cce20_0; alias, 1 drivers +v0x1878410_0 .net "O", 0 0, L_0x16652a0; alias, 1 drivers +S_0x19c4c40 .scope module, "$ibuf$clk_buf_primitive_inst.$ibuf_ibuf_enable" "I_BUF" 7 64, 6 10 1, S_0x19ccfa0; + .timescale -9 -12; + .port_info 0 /INPUT 1 "I"; + .port_info 1 /INPUT 1 "EN"; + .port_info 2 /OUTPUT 1 "O"; +P_0x176caf0 .param/str "IOSTANDARD" 0 6 12, "DEFAULT"; +P_0x176cb30 .param/str "WEAK_KEEPER" 0 6 11, "NONE"; +L_0x1669b30 .functor BUFT 1, v0x15ce3a0_0, C4<0>, C4<0>, C4<0>; +L_0x7f873cdf4138 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>; +v0x17b6c80_0 .net "EN", 0 0, L_0x7f873cdf4138; 1 drivers +v0x17b7ba0_0 .net "I", 0 0, v0x15ce3a0_0; alias, 1 drivers +v0x17b6df0_0 .net "O", 0 0, L_0x1669b30; alias, 1 drivers +S_0x19c11c0 .scope module, "$obuf$clk_buf_primitive_inst.$obuf_clock_output" "O_BUFT" 7 72, 10 10 1, S_0x19ccfa0; + .timescale -9 -12; + .port_info 0 /INPUT 1 "I"; + .port_info 1 /INPUT 1 "T"; + .port_info 2 /OUTPUT 1 "O"; +P_0x17ea0c0 .param/l "DRIVE_STRENGTH" 0 10 13, +C4<00000000000000000000000000000010>; +P_0x17ea100 .param/str "IOSTANDARD" 0 10 12, "DEFAULT"; +P_0x17ea140 .param/str "SLEW_RATE" 0 10 14, "SLOW"; +P_0x17ea180 .param/str "WEAK_KEEPER" 0 10 11, "NONE"; +L_0x1665850 .functor BUFT 1, L_0x16655a0, C4<0>, C4<0>, C4<0>; +v0x17b7d10_0 .net "I", 0 0, L_0x16655a0; alias, 1 drivers +v0x17b69a0_0 .net "O", 0 0, L_0x1665850; alias, 1 drivers +L_0x7f873cdf4180 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>; +v0x17b78c0_0 .net "T", 0 0, L_0x7f873cdf4180; 1 drivers +S_0x19b7d10 .scope module, "clk_buf_inst" "CLK_BUF" 7 79, 5 10 1, S_0x19ccfa0; + .timescale -9 -12; + .port_info 0 /INPUT 1 "I"; + .port_info 1 /OUTPUT 1 "O"; +L_0x1665130 .functor BUFZ 1, L_0x16652a0, C4<0>, C4<0>, C4<0>; +v0x17b6b10_0 .net "I", 0 0, L_0x16652a0; alias, 1 drivers +v0x17b7a30_0 .net "O", 0 0, L_0x1665130; alias, 1 drivers + .scope S_0x19d63d0; +T_1 ; + %pushi/vec4 1313820229, 0, 64; + %dup/vec4; + %pushi/vec4 0, 0, 32; draw_string_vec4 + %pushi/vec4 1313820229, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_1.0, 6; + %dup/vec4; + %pushi/vec4 20565, 0, 32; draw_string_vec4 + %pushi/vec4 1280070992, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_1.1, 6; + %dup/vec4; + %pushi/vec4 1347767372, 0, 32; draw_string_vec4 + %pushi/vec4 1146050382, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_1.2, 6; + %vpi_call/w 6 41 "$fatal", 32'sb00000000000000000000000000000001, "\012Error: I_BUF instance %m has parameter WEAK_KEEPER set to %s. Valid values are NONE, PULLUP, PULLDOWN\012", P_0x163d720 {0 0 0}; + %jmp T_1.4; +T_1.0 ; + %jmp T_1.4; +T_1.1 ; + %jmp T_1.4; +T_1.2 ; + %jmp T_1.4; +T_1.4 ; + %pop/vec4 1; + %pushi/vec4 2290781314, 0, 81; + %concati/vec4 5590100, 0, 23; + %dup/vec4; + %pushi/vec4 0, 0, 32; draw_string_vec4 + %pushi/vec4 17477, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1178686796, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 84, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_1.5, 6; + %dup/vec4; + %pushi/vec4 0, 0, 32; draw_string_vec4 + %pushi/vec4 1280721741, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1330863921, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 50, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_1.6, 6; + %dup/vec4; + %pushi/vec4 0, 0, 32; draw_string_vec4 + %pushi/vec4 1280721741, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1330863921, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 53, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_1.7, 6; + %dup/vec4; + %pushi/vec4 5002819, 0, 32; draw_string_vec4 + %pushi/vec4 1297044319, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 825777992, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 80, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_1.8, 6; + %dup/vec4; + %pushi/vec4 5002819, 0, 32; draw_string_vec4 + %pushi/vec4 1297044319, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 825777992, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 82, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_1.9, 6; + %dup/vec4; + %pushi/vec4 0, 0, 32; draw_string_vec4 + %pushi/vec4 1280721741, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1330863922, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 53, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_1.10, 6; + %dup/vec4; + %pushi/vec4 0, 0, 32; draw_string_vec4 + %pushi/vec4 1280721741, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1330863923, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 51, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_1.11, 6; + %dup/vec4; + %pushi/vec4 0, 0, 32; draw_string_vec4 + %pushi/vec4 0, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1280726100, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 76, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_1.12, 6; + %dup/vec4; + %pushi/vec4 0, 0, 32; draw_string_vec4 + %pushi/vec4 1213420620, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1598644017, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 50, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_1.13, 6; + %dup/vec4; + %pushi/vec4 72, 0, 32; draw_string_vec4 + %pushi/vec4 1398033503, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1229545265, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 50, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_1.14, 6; + %dup/vec4; + %pushi/vec4 0, 0, 32; draw_string_vec4 + %pushi/vec4 1213420620, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1598644017, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 53, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_1.15, 6; + %dup/vec4; + %pushi/vec4 72, 0, 32; draw_string_vec4 + %pushi/vec4 1398033503, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1229545265, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 53, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_1.16, 6; + %dup/vec4; + %pushi/vec4 0, 0, 32; draw_string_vec4 + %pushi/vec4 18515, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1431068465, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 50, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_1.17, 6; + %dup/vec4; + %pushi/vec4 0, 0, 32; draw_string_vec4 + %pushi/vec4 0, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1346586934, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 54, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_1.18, 6; + %dup/vec4; + %pushi/vec4 0, 0, 32; draw_string_vec4 + %pushi/vec4 20547, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1230516531, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 51, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_1.19, 6; + %dup/vec4; + %pushi/vec4 0, 0, 32; draw_string_vec4 + %pushi/vec4 80, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1329880881, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 50, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_1.20, 6; + %dup/vec4; + %pushi/vec4 0, 0, 32; draw_string_vec4 + %pushi/vec4 1397969996, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1598644017, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 53, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_1.21, 6; + %dup/vec4; + %pushi/vec4 83, 0, 32; draw_string_vec4 + %pushi/vec4 1398033503, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1229545265, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 53, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_1.22, 6; + %dup/vec4; + %pushi/vec4 5460820, 0, 32; draw_string_vec4 + %pushi/vec4 1281313119, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 825777992, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 80, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_1.23, 6; + %dup/vec4; + %pushi/vec4 1397969996, 0, 32; draw_string_vec4 + %pushi/vec4 1598638431, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 825777992, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 80, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_1.24, 6; + %dup/vec4; + %pushi/vec4 5460820, 0, 32; draw_string_vec4 + %pushi/vec4 1281313119, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 825777992, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 82, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_1.25, 6; + %dup/vec4; + %pushi/vec4 1397969996, 0, 32; draw_string_vec4 + %pushi/vec4 1598638431, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 825777992, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 82, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_1.26, 6; + %dup/vec4; + %pushi/vec4 0, 0, 32; draw_string_vec4 + %pushi/vec4 1397969996, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1598644018, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 53, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_1.27, 6; + %dup/vec4; + %pushi/vec4 83, 0, 32; draw_string_vec4 + %pushi/vec4 1398033503, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1229545266, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 53, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_1.28, 6; + %dup/vec4; + %pushi/vec4 0, 0, 32; draw_string_vec4 + %pushi/vec4 1397969996, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1598644019, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 51, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_1.29, 6; + %dup/vec4; + %pushi/vec4 83, 0, 32; draw_string_vec4 + %pushi/vec4 1398033503, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1229545267, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 51, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_1.30, 6; + %vpi_call/w 6 73 "$fatal", 32'sb00000000000000000000000000000001, "\012Error: I_BUF instance %m has parameter IOSTANDARD set to %s. Valid values are DEFAULT, LVCMOS_12, LVCMOS_15, LVCMOS_18_HP, LVCMOS_18_HR, LVCMOS_25, LVCMOS_33, LVTTL, HSTL_I_12, HSTL_II_12, HSTL_I_15, HSTL_II_15, HSUL_12, PCI66, PCIX133, POD_12, SSTL_I_15, SSTL_II_15, SSTL_I_18_HP, SSTL_II_18_HP, SSTL_I_18_HR, SSTL_II_18_HR, SSTL_I_25, SSTL_II_25, SSTL_I_33, SSTL_II_33\012", P_0x163d6e0 {0 0 0}; + %jmp T_1.32; +T_1.5 ; + %jmp T_1.32; +T_1.6 ; + %jmp T_1.32; +T_1.7 ; + %jmp T_1.32; +T_1.8 ; + %jmp T_1.32; +T_1.9 ; + %jmp T_1.32; +T_1.10 ; + %jmp T_1.32; +T_1.11 ; + %jmp T_1.32; +T_1.12 ; + %jmp T_1.32; +T_1.13 ; + %jmp T_1.32; +T_1.14 ; + %jmp T_1.32; +T_1.15 ; + %jmp T_1.32; +T_1.16 ; + %jmp T_1.32; +T_1.17 ; + %jmp T_1.32; +T_1.18 ; + %jmp T_1.32; +T_1.19 ; + %jmp T_1.32; +T_1.20 ; + %jmp T_1.32; +T_1.21 ; + %jmp T_1.32; +T_1.22 ; + %jmp T_1.32; +T_1.23 ; + %jmp T_1.32; +T_1.24 ; + %jmp T_1.32; +T_1.25 ; + %jmp T_1.32; +T_1.26 ; + %jmp T_1.32; +T_1.27 ; + %jmp T_1.32; +T_1.28 ; + %jmp T_1.32; +T_1.29 ; + %jmp T_1.32; +T_1.30 ; + %jmp T_1.32; +T_1.32 ; + %pop/vec4 1; + %end; + .thread T_1; + .scope S_0x19e21b0; +T_2 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x168de60_0, 0, 1; + %end; + .thread T_2, $init; + .scope S_0x19e21b0; +T_3 ; + %wait E_0x15d9040; + %load/vec4 v0x1837c20_0; + %assign/vec4 v0x168de60_0, 0; + %jmp T_3; + .thread T_3; + .scope S_0x19c02a0; +T_4 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x168eb80_0, 0, 1; + %end; + .thread T_4, $init; + .scope S_0x19c02a0; +T_5 ; + %wait E_0x183e400; + %load/vec4 v0x168ecf0_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_5.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x168eb80_0, 0; + %jmp T_5.1; +T_5.0 ; + %load/vec4 v0x168ea10_0; + %flag_set/vec4 8; + %jmp/0xz T_5.2, 8; + %load/vec4 v0x168e730_0; + %assign/vec4 v0x168eb80_0, 0; +T_5.2 ; +T_5.1 ; + %jmp T_5; + .thread T_5; + .scope S_0x19c4fd0; +T_6 ; + %pushi/vec4 1313820229, 0, 64; + %dup/vec4; + %pushi/vec4 0, 0, 32; draw_string_vec4 + %pushi/vec4 1313820229, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_6.0, 6; + %dup/vec4; + %pushi/vec4 20565, 0, 32; draw_string_vec4 + %pushi/vec4 1280070992, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_6.1, 6; + %dup/vec4; + %pushi/vec4 1347767372, 0, 32; draw_string_vec4 + %pushi/vec4 1146050382, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_6.2, 6; + %vpi_call/w 6 41 "$fatal", 32'sb00000000000000000000000000000001, "\012Error: I_BUF instance %m has parameter WEAK_KEEPER set to %s. Valid values are NONE, PULLUP, PULLDOWN\012", P_0x1881970 {0 0 0}; + %jmp T_6.4; +T_6.0 ; + %jmp T_6.4; +T_6.1 ; + %jmp T_6.4; +T_6.2 ; + %jmp T_6.4; +T_6.4 ; + %pop/vec4 1; + %pushi/vec4 2290781314, 0, 81; + %concati/vec4 5590100, 0, 23; + %dup/vec4; + %pushi/vec4 0, 0, 32; draw_string_vec4 + %pushi/vec4 17477, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1178686796, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 84, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_6.5, 6; + %dup/vec4; + %pushi/vec4 0, 0, 32; draw_string_vec4 + %pushi/vec4 1280721741, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1330863921, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 50, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_6.6, 6; + %dup/vec4; + %pushi/vec4 0, 0, 32; draw_string_vec4 + %pushi/vec4 1280721741, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1330863921, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 53, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_6.7, 6; + %dup/vec4; + %pushi/vec4 5002819, 0, 32; draw_string_vec4 + %pushi/vec4 1297044319, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 825777992, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 80, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_6.8, 6; + %dup/vec4; + %pushi/vec4 5002819, 0, 32; draw_string_vec4 + %pushi/vec4 1297044319, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 825777992, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 82, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_6.9, 6; + %dup/vec4; + %pushi/vec4 0, 0, 32; draw_string_vec4 + %pushi/vec4 1280721741, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1330863922, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 53, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_6.10, 6; + %dup/vec4; + %pushi/vec4 0, 0, 32; draw_string_vec4 + %pushi/vec4 1280721741, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1330863923, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 51, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_6.11, 6; + %dup/vec4; + %pushi/vec4 0, 0, 32; draw_string_vec4 + %pushi/vec4 0, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1280726100, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 76, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_6.12, 6; + %dup/vec4; + %pushi/vec4 0, 0, 32; draw_string_vec4 + %pushi/vec4 1213420620, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1598644017, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 50, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_6.13, 6; + %dup/vec4; + %pushi/vec4 72, 0, 32; draw_string_vec4 + %pushi/vec4 1398033503, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1229545265, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 50, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_6.14, 6; + %dup/vec4; + %pushi/vec4 0, 0, 32; draw_string_vec4 + %pushi/vec4 1213420620, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1598644017, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 53, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_6.15, 6; + %dup/vec4; + %pushi/vec4 72, 0, 32; draw_string_vec4 + %pushi/vec4 1398033503, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1229545265, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 53, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_6.16, 6; + %dup/vec4; + %pushi/vec4 0, 0, 32; draw_string_vec4 + %pushi/vec4 18515, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1431068465, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 50, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_6.17, 6; + %dup/vec4; + %pushi/vec4 0, 0, 32; draw_string_vec4 + %pushi/vec4 0, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1346586934, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 54, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_6.18, 6; + %dup/vec4; + %pushi/vec4 0, 0, 32; draw_string_vec4 + %pushi/vec4 20547, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1230516531, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 51, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_6.19, 6; + %dup/vec4; + %pushi/vec4 0, 0, 32; draw_string_vec4 + %pushi/vec4 80, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1329880881, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 50, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_6.20, 6; + %dup/vec4; + %pushi/vec4 0, 0, 32; draw_string_vec4 + %pushi/vec4 1397969996, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1598644017, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 53, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_6.21, 6; + %dup/vec4; + %pushi/vec4 83, 0, 32; draw_string_vec4 + %pushi/vec4 1398033503, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1229545265, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 53, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_6.22, 6; + %dup/vec4; + %pushi/vec4 5460820, 0, 32; draw_string_vec4 + %pushi/vec4 1281313119, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 825777992, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 80, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_6.23, 6; + %dup/vec4; + %pushi/vec4 1397969996, 0, 32; draw_string_vec4 + %pushi/vec4 1598638431, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 825777992, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 80, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_6.24, 6; + %dup/vec4; + %pushi/vec4 5460820, 0, 32; draw_string_vec4 + %pushi/vec4 1281313119, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 825777992, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 82, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_6.25, 6; + %dup/vec4; + %pushi/vec4 1397969996, 0, 32; draw_string_vec4 + %pushi/vec4 1598638431, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 825777992, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 82, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_6.26, 6; + %dup/vec4; + %pushi/vec4 0, 0, 32; draw_string_vec4 + %pushi/vec4 1397969996, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1598644018, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 53, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_6.27, 6; + %dup/vec4; + %pushi/vec4 83, 0, 32; draw_string_vec4 + %pushi/vec4 1398033503, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1229545266, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 53, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_6.28, 6; + %dup/vec4; + %pushi/vec4 0, 0, 32; draw_string_vec4 + %pushi/vec4 1397969996, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1598644019, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 51, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_6.29, 6; + %dup/vec4; + %pushi/vec4 83, 0, 32; draw_string_vec4 + %pushi/vec4 1398033503, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1229545267, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 51, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_6.30, 6; + %vpi_call/w 6 73 "$fatal", 32'sb00000000000000000000000000000001, "\012Error: I_BUF instance %m has parameter IOSTANDARD set to %s. Valid values are DEFAULT, LVCMOS_12, LVCMOS_15, LVCMOS_18_HP, LVCMOS_18_HR, LVCMOS_25, LVCMOS_33, LVTTL, HSTL_I_12, HSTL_II_12, HSTL_I_15, HSTL_II_15, HSUL_12, PCI66, PCIX133, POD_12, SSTL_I_15, SSTL_II_15, SSTL_I_18_HP, SSTL_II_18_HP, SSTL_I_18_HR, SSTL_II_18_HR, SSTL_I_25, SSTL_II_25, SSTL_I_33, SSTL_II_33\012", P_0x1881930 {0 0 0}; + %jmp T_6.32; +T_6.5 ; + %jmp T_6.32; +T_6.6 ; + %jmp T_6.32; +T_6.7 ; + %jmp T_6.32; +T_6.8 ; + %jmp T_6.32; +T_6.9 ; + %jmp T_6.32; +T_6.10 ; + %jmp T_6.32; +T_6.11 ; + %jmp T_6.32; +T_6.12 ; + %jmp T_6.32; +T_6.13 ; + %jmp T_6.32; +T_6.14 ; + %jmp T_6.32; +T_6.15 ; + %jmp T_6.32; +T_6.16 ; + %jmp T_6.32; +T_6.17 ; + %jmp T_6.32; +T_6.18 ; + %jmp T_6.32; +T_6.19 ; + %jmp T_6.32; +T_6.20 ; + %jmp T_6.32; +T_6.21 ; + %jmp T_6.32; +T_6.22 ; + %jmp T_6.32; +T_6.23 ; + %jmp T_6.32; +T_6.24 ; + %jmp T_6.32; +T_6.25 ; + %jmp T_6.32; +T_6.26 ; + %jmp T_6.32; +T_6.27 ; + %jmp T_6.32; +T_6.28 ; + %jmp T_6.32; +T_6.29 ; + %jmp T_6.32; +T_6.30 ; + %jmp T_6.32; +T_6.32 ; + %pop/vec4 1; + %end; + .thread T_6; + .scope S_0x19c4c40; +T_7 ; + %pushi/vec4 1313820229, 0, 64; + %dup/vec4; + %pushi/vec4 0, 0, 32; draw_string_vec4 + %pushi/vec4 1313820229, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_7.0, 6; + %dup/vec4; + %pushi/vec4 20565, 0, 32; draw_string_vec4 + %pushi/vec4 1280070992, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_7.1, 6; + %dup/vec4; + %pushi/vec4 1347767372, 0, 32; draw_string_vec4 + %pushi/vec4 1146050382, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_7.2, 6; + %vpi_call/w 6 41 "$fatal", 32'sb00000000000000000000000000000001, "\012Error: I_BUF instance %m has parameter WEAK_KEEPER set to %s. Valid values are NONE, PULLUP, PULLDOWN\012", P_0x176cb30 {0 0 0}; + %jmp T_7.4; +T_7.0 ; + %jmp T_7.4; +T_7.1 ; + %jmp T_7.4; +T_7.2 ; + %jmp T_7.4; +T_7.4 ; + %pop/vec4 1; + %pushi/vec4 2290781314, 0, 81; + %concati/vec4 5590100, 0, 23; + %dup/vec4; + %pushi/vec4 0, 0, 32; draw_string_vec4 + %pushi/vec4 17477, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1178686796, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 84, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_7.5, 6; + %dup/vec4; + %pushi/vec4 0, 0, 32; draw_string_vec4 + %pushi/vec4 1280721741, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1330863921, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 50, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_7.6, 6; + %dup/vec4; + %pushi/vec4 0, 0, 32; draw_string_vec4 + %pushi/vec4 1280721741, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1330863921, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 53, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_7.7, 6; + %dup/vec4; + %pushi/vec4 5002819, 0, 32; draw_string_vec4 + %pushi/vec4 1297044319, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 825777992, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 80, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_7.8, 6; + %dup/vec4; + %pushi/vec4 5002819, 0, 32; draw_string_vec4 + %pushi/vec4 1297044319, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 825777992, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 82, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_7.9, 6; + %dup/vec4; + %pushi/vec4 0, 0, 32; draw_string_vec4 + %pushi/vec4 1280721741, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1330863922, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 53, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_7.10, 6; + %dup/vec4; + %pushi/vec4 0, 0, 32; draw_string_vec4 + %pushi/vec4 1280721741, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1330863923, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 51, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_7.11, 6; + %dup/vec4; + %pushi/vec4 0, 0, 32; draw_string_vec4 + %pushi/vec4 0, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1280726100, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 76, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_7.12, 6; + %dup/vec4; + %pushi/vec4 0, 0, 32; draw_string_vec4 + %pushi/vec4 1213420620, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1598644017, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 50, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_7.13, 6; + %dup/vec4; + %pushi/vec4 72, 0, 32; draw_string_vec4 + %pushi/vec4 1398033503, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1229545265, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 50, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_7.14, 6; + %dup/vec4; + %pushi/vec4 0, 0, 32; draw_string_vec4 + %pushi/vec4 1213420620, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1598644017, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 53, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_7.15, 6; + %dup/vec4; + %pushi/vec4 72, 0, 32; draw_string_vec4 + %pushi/vec4 1398033503, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1229545265, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 53, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_7.16, 6; + %dup/vec4; + %pushi/vec4 0, 0, 32; draw_string_vec4 + %pushi/vec4 18515, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1431068465, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 50, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_7.17, 6; + %dup/vec4; + %pushi/vec4 0, 0, 32; draw_string_vec4 + %pushi/vec4 0, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1346586934, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 54, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_7.18, 6; + %dup/vec4; + %pushi/vec4 0, 0, 32; draw_string_vec4 + %pushi/vec4 20547, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1230516531, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 51, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_7.19, 6; + %dup/vec4; + %pushi/vec4 0, 0, 32; draw_string_vec4 + %pushi/vec4 80, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1329880881, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 50, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_7.20, 6; + %dup/vec4; + %pushi/vec4 0, 0, 32; draw_string_vec4 + %pushi/vec4 1397969996, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1598644017, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 53, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_7.21, 6; + %dup/vec4; + %pushi/vec4 83, 0, 32; draw_string_vec4 + %pushi/vec4 1398033503, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1229545265, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 53, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_7.22, 6; + %dup/vec4; + %pushi/vec4 5460820, 0, 32; draw_string_vec4 + %pushi/vec4 1281313119, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 825777992, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 80, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_7.23, 6; + %dup/vec4; + %pushi/vec4 1397969996, 0, 32; draw_string_vec4 + %pushi/vec4 1598638431, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 825777992, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 80, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_7.24, 6; + %dup/vec4; + %pushi/vec4 5460820, 0, 32; draw_string_vec4 + %pushi/vec4 1281313119, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 825777992, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 82, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_7.25, 6; + %dup/vec4; + %pushi/vec4 1397969996, 0, 32; draw_string_vec4 + %pushi/vec4 1598638431, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 825777992, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 82, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_7.26, 6; + %dup/vec4; + %pushi/vec4 0, 0, 32; draw_string_vec4 + %pushi/vec4 1397969996, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1598644018, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 53, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_7.27, 6; + %dup/vec4; + %pushi/vec4 83, 0, 32; draw_string_vec4 + %pushi/vec4 1398033503, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1229545266, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 53, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_7.28, 6; + %dup/vec4; + %pushi/vec4 0, 0, 32; draw_string_vec4 + %pushi/vec4 1397969996, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1598644019, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 51, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_7.29, 6; + %dup/vec4; + %pushi/vec4 83, 0, 32; draw_string_vec4 + %pushi/vec4 1398033503, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1229545267, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 51, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_7.30, 6; + %vpi_call/w 6 73 "$fatal", 32'sb00000000000000000000000000000001, "\012Error: I_BUF instance %m has parameter IOSTANDARD set to %s. Valid values are DEFAULT, LVCMOS_12, LVCMOS_15, LVCMOS_18_HP, LVCMOS_18_HR, LVCMOS_25, LVCMOS_33, LVTTL, HSTL_I_12, HSTL_II_12, HSTL_I_15, HSTL_II_15, HSUL_12, PCI66, PCIX133, POD_12, SSTL_I_15, SSTL_II_15, SSTL_I_18_HP, SSTL_II_18_HP, SSTL_I_18_HR, SSTL_II_18_HR, SSTL_I_25, SSTL_II_25, SSTL_I_33, SSTL_II_33\012", P_0x176caf0 {0 0 0}; + %jmp T_7.32; +T_7.5 ; + %jmp T_7.32; +T_7.6 ; + %jmp T_7.32; +T_7.7 ; + %jmp T_7.32; +T_7.8 ; + %jmp T_7.32; +T_7.9 ; + %jmp T_7.32; +T_7.10 ; + %jmp T_7.32; +T_7.11 ; + %jmp T_7.32; +T_7.12 ; + %jmp T_7.32; +T_7.13 ; + %jmp T_7.32; +T_7.14 ; + %jmp T_7.32; +T_7.15 ; + %jmp T_7.32; +T_7.16 ; + %jmp T_7.32; +T_7.17 ; + %jmp T_7.32; +T_7.18 ; + %jmp T_7.32; +T_7.19 ; + %jmp T_7.32; +T_7.20 ; + %jmp T_7.32; +T_7.21 ; + %jmp T_7.32; +T_7.22 ; + %jmp T_7.32; +T_7.23 ; + %jmp T_7.32; +T_7.24 ; + %jmp T_7.32; +T_7.25 ; + %jmp T_7.32; +T_7.26 ; + %jmp T_7.32; +T_7.27 ; + %jmp T_7.32; +T_7.28 ; + %jmp T_7.32; +T_7.29 ; + %jmp T_7.32; +T_7.30 ; + %jmp T_7.32; +T_7.32 ; + %pop/vec4 1; + %end; + .thread T_7; + .scope S_0x19c11c0; +T_8 ; + %pushi/vec4 1313820229, 0, 64; + %dup/vec4; + %pushi/vec4 0, 0, 32; draw_string_vec4 + %pushi/vec4 1313820229, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_8.0, 6; + %dup/vec4; + %pushi/vec4 20565, 0, 32; draw_string_vec4 + %pushi/vec4 1280070992, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_8.1, 6; + %dup/vec4; + %pushi/vec4 1347767372, 0, 32; draw_string_vec4 + %pushi/vec4 1146050382, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_8.2, 6; + %vpi_call/w 10 37 "$fatal", 32'sb00000000000000000000000000000001, "\012Error: O_BUFT instance %m has parameter WEAK_KEEPER set to %s. Valid values are NONE, PULLUP, PULLDOWN\012", P_0x17ea180 {0 0 0}; + %jmp T_8.4; +T_8.0 ; + %jmp T_8.4; +T_8.1 ; + %jmp T_8.4; +T_8.2 ; + %jmp T_8.4; +T_8.4 ; + %pop/vec4 1; + %pushi/vec4 2290781314, 0, 81; + %concati/vec4 5590100, 0, 23; + %dup/vec4; + %pushi/vec4 0, 0, 32; draw_string_vec4 + %pushi/vec4 17477, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1178686796, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 84, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_8.5, 6; + %dup/vec4; + %pushi/vec4 0, 0, 32; draw_string_vec4 + %pushi/vec4 1280721741, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1330863921, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 50, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_8.6, 6; + %dup/vec4; + %pushi/vec4 0, 0, 32; draw_string_vec4 + %pushi/vec4 1280721741, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1330863921, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 53, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_8.7, 6; + %dup/vec4; + %pushi/vec4 5002819, 0, 32; draw_string_vec4 + %pushi/vec4 1297044319, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 825777992, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 80, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_8.8, 6; + %dup/vec4; + %pushi/vec4 5002819, 0, 32; draw_string_vec4 + %pushi/vec4 1297044319, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 825777992, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 82, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_8.9, 6; + %dup/vec4; + %pushi/vec4 0, 0, 32; draw_string_vec4 + %pushi/vec4 1280721741, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1330863922, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 53, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_8.10, 6; + %dup/vec4; + %pushi/vec4 0, 0, 32; draw_string_vec4 + %pushi/vec4 1280721741, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1330863923, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 51, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_8.11, 6; + %dup/vec4; + %pushi/vec4 0, 0, 32; draw_string_vec4 + %pushi/vec4 0, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1280726100, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 76, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_8.12, 6; + %dup/vec4; + %pushi/vec4 0, 0, 32; draw_string_vec4 + %pushi/vec4 1213420620, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1598644017, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 50, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_8.13, 6; + %dup/vec4; + %pushi/vec4 72, 0, 32; draw_string_vec4 + %pushi/vec4 1398033503, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1229545265, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 50, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_8.14, 6; + %dup/vec4; + %pushi/vec4 0, 0, 32; draw_string_vec4 + %pushi/vec4 1213420620, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1598644017, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 53, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_8.15, 6; + %dup/vec4; + %pushi/vec4 72, 0, 32; draw_string_vec4 + %pushi/vec4 1398033503, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1229545265, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 53, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_8.16, 6; + %dup/vec4; + %pushi/vec4 0, 0, 32; draw_string_vec4 + %pushi/vec4 18515, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1431068465, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 50, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_8.17, 6; + %dup/vec4; + %pushi/vec4 0, 0, 32; draw_string_vec4 + %pushi/vec4 0, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1346586934, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 54, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_8.18, 6; + %dup/vec4; + %pushi/vec4 0, 0, 32; draw_string_vec4 + %pushi/vec4 20547, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1230516531, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 51, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_8.19, 6; + %dup/vec4; + %pushi/vec4 0, 0, 32; draw_string_vec4 + %pushi/vec4 80, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1329880881, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 50, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_8.20, 6; + %dup/vec4; + %pushi/vec4 0, 0, 32; draw_string_vec4 + %pushi/vec4 1397969996, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1598644017, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 53, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_8.21, 6; + %dup/vec4; + %pushi/vec4 83, 0, 32; draw_string_vec4 + %pushi/vec4 1398033503, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1229545265, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 53, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_8.22, 6; + %dup/vec4; + %pushi/vec4 5460820, 0, 32; draw_string_vec4 + %pushi/vec4 1281313119, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 825777992, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 80, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_8.23, 6; + %dup/vec4; + %pushi/vec4 1397969996, 0, 32; draw_string_vec4 + %pushi/vec4 1598638431, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 825777992, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 80, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_8.24, 6; + %dup/vec4; + %pushi/vec4 5460820, 0, 32; draw_string_vec4 + %pushi/vec4 1281313119, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 825777992, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 82, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_8.25, 6; + %dup/vec4; + %pushi/vec4 1397969996, 0, 32; draw_string_vec4 + %pushi/vec4 1598638431, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 825777992, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 82, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_8.26, 6; + %dup/vec4; + %pushi/vec4 0, 0, 32; draw_string_vec4 + %pushi/vec4 1397969996, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1598644018, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 53, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_8.27, 6; + %dup/vec4; + %pushi/vec4 83, 0, 32; draw_string_vec4 + %pushi/vec4 1398033503, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1229545266, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 53, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_8.28, 6; + %dup/vec4; + %pushi/vec4 0, 0, 32; draw_string_vec4 + %pushi/vec4 1397969996, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1598644019, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 51, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_8.29, 6; + %dup/vec4; + %pushi/vec4 83, 0, 32; draw_string_vec4 + %pushi/vec4 1398033503, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 1229545267, 0, 32; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %pushi/vec4 51, 0, 8; draw_string_vec4 + %concat/vec4; draw_string_vec4 + %cmp/u; + %jmp/1 T_8.30, 6; + %vpi_call/w 10 69 "$fatal", 32'sb00000000000000000000000000000001, "\012Error: O_BUFT instance %m has parameter IOSTANDARD set to %s. Valid values are DEFAULT, LVCMOS_12, LVCMOS_15, LVCMOS_18_HP, LVCMOS_18_HR, LVCMOS_25, LVCMOS_33, LVTTL, HSTL_I_12, HSTL_II_12, HSTL_I_15, HSTL_II_15, HSUL_12, PCI66, PCIX133, POD_12, SSTL_I_15, SSTL_II_15, SSTL_I_18_HP, SSTL_II_18_HP, SSTL_I_18_HR, SSTL_II_18_HR, SSTL_I_25, SSTL_II_25, SSTL_I_33, SSTL_II_33\012", P_0x17ea100 {0 0 0}; + %jmp T_8.32; +T_8.5 ; + %jmp T_8.32; +T_8.6 ; + %jmp T_8.32; +T_8.7 ; + %jmp T_8.32; +T_8.8 ; + %jmp T_8.32; +T_8.9 ; + %jmp T_8.32; +T_8.10 ; + %jmp T_8.32; +T_8.11 ; + %jmp T_8.32; +T_8.12 ; + %jmp T_8.32; +T_8.13 ; + %jmp T_8.32; +T_8.14 ; + %jmp T_8.32; +T_8.15 ; + %jmp T_8.32; +T_8.16 ; + %jmp T_8.32; +T_8.17 ; + %jmp T_8.32; +T_8.18 ; + %jmp T_8.32; +T_8.19 ; + %jmp T_8.32; +T_8.20 ; + %jmp T_8.32; +T_8.21 ; + %jmp T_8.32; +T_8.22 ; + %jmp T_8.32; +T_8.23 ; + %jmp T_8.32; +T_8.24 ; + %jmp T_8.32; +T_8.25 ; + %jmp T_8.32; +T_8.26 ; + %jmp T_8.32; +T_8.27 ; + %jmp T_8.32; +T_8.28 ; + %jmp T_8.32; +T_8.29 ; + %jmp T_8.32; +T_8.30 ; + %jmp T_8.32; +T_8.32 ; + %pop/vec4 1; + %pushi/vec4 2, 0, 32; + %dup/vec4; + %pushi/vec4 2, 0, 32; + %cmp/u; + %jmp/1 T_8.33, 6; + %dup/vec4; + %pushi/vec4 4, 0, 32; + %cmp/u; + %jmp/1 T_8.34, 6; + %dup/vec4; + %pushi/vec4 6, 0, 32; + %cmp/u; + %jmp/1 T_8.35, 6; + %dup/vec4; + %pushi/vec4 8, 0, 32; + %cmp/u; + %jmp/1 T_8.36, 6; + %dup/vec4; + %pushi/vec4 12, 0, 32; + %cmp/u; + %jmp/1 T_8.37, 6; + %dup/vec4; + %pushi/vec4 16, 0, 32; + %cmp/u; + %jmp/1 T_8.38, 6; + %vpi_call/w 10 81 "$fatal", 32'sb00000000000000000000000000000001, "\012Error: O_BUFT instance %m has parameter DRIVE_STRENGTH set to %s. Valid values are 2, 4, 6, 8, 12, 16\012", P_0x17ea0c0 {0 0 0}; + %jmp T_8.40; +T_8.33 ; + %jmp T_8.40; +T_8.34 ; + %jmp T_8.40; +T_8.35 ; + %jmp T_8.40; +T_8.36 ; + %jmp T_8.40; +T_8.37 ; + %jmp T_8.40; +T_8.38 ; + %jmp T_8.40; +T_8.40 ; + %pop/vec4 1; + %pushi/vec4 1397509975, 0, 32; draw_string_vec4 + %dup/vec4; + %pushi/vec4 1397509975, 0, 32; draw_string_vec4 + %cmp/u; + %jmp/1 T_8.41, 6; + %dup/vec4; + %pushi/vec4 1178686292, 0, 32; draw_string_vec4 + %cmp/u; + %jmp/1 T_8.42, 6; + %vpi_call/w 10 89 "$fatal", 32'sb00000000000000000000000000000001, "\012Error: O_BUFT instance %m has parameter SLEW_RATE set to %s. Valid values are SLOW, FAST\012", P_0x17ea140 {0 0 0}; + %jmp T_8.44; +T_8.41 ; + %jmp T_8.44; +T_8.42 ; + %jmp T_8.44; +T_8.44 ; + %pop/vec4 1; + %end; + .thread T_8; + .scope S_0x19bf380; +T_9 ; + %pushi/vec4 0, 0, 32; + %store/vec4 v0x15cf680_0, 0, 32; + %end; + .thread T_9, $init; + .scope S_0x19bf380; +T_10 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x15cce20_0, 0, 1; +T_10.0 ; + %delay 5000, 0; + %load/vec4 v0x15cce20_0; + %inv; + %store/vec4 v0x15cce20_0, 0, 1; + %jmp T_10.0; +T_10.1 ; + %end; + .thread T_10; + .scope S_0x19bf380; +T_11 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x15ce3a0_0, 0; + %pushi/vec4 2, 0, 32; +T_11.0 %dup/vec4; + %pushi/vec4 0, 0, 32; + %cmp/s; + %jmp/1xz T_11.1, 5; + %jmp/1 T_11.1, 4; + %pushi/vec4 1, 0, 32; + %sub; + %wait E_0x18397a0; + %jmp T_11.0; +T_11.1 ; + %pop/vec4 1; + %fork TD_co_sim_clk_buf_primitive_inst.compare, S_0x15e4500; + %join; + %pushi/vec4 100, 0, 32; +T_11.2 %dup/vec4; + %pushi/vec4 0, 0, 32; + %cmp/s; + %jmp/1xz T_11.3, 5; + %jmp/1 T_11.3, 4; + %pushi/vec4 1, 0, 32; + %sub; + %wait E_0x18397a0; + %vpi_func 3 38 "$urandom" 32 {0 0 0}; + %pad/u 1; + %assign/vec4 v0x15ce3a0_0, 0; + %fork TD_co_sim_clk_buf_primitive_inst.compare, S_0x15e4500; + %join; + %jmp T_11.2; +T_11.3 ; + %pop/vec4 1; + %pushi/vec4 2, 0, 32; +T_11.4 %dup/vec4; + %pushi/vec4 0, 0, 32; + %cmp/s; + %jmp/1xz T_11.5, 5; + %jmp/1 T_11.5, 4; + %pushi/vec4 1, 0, 32; + %sub; + %wait E_0x18397a0; + %jmp T_11.4; +T_11.5 ; + %pop/vec4 1; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x15ce3a0_0, 0; + %pushi/vec4 2, 0, 32; +T_11.6 %dup/vec4; + %pushi/vec4 0, 0, 32; + %cmp/s; + %jmp/1xz T_11.7, 5; + %jmp/1 T_11.7, 4; + %pushi/vec4 1, 0, 32; + %sub; + %wait E_0x18397a0; + %jmp T_11.6; +T_11.7 ; + %pop/vec4 1; + %fork TD_co_sim_clk_buf_primitive_inst.compare, S_0x15e4500; + %join; + %load/vec4 v0x15cf680_0; + %cmpi/e 0, 0, 32; + %jmp/0xz T_11.8, 4; + %vpi_call/w 3 49 "$display", "**** All Comparison Matched *** \012\011\011Simulation Passed\012" {0 0 0}; + %jmp T_11.9; +T_11.8 ; + %vpi_call/w 3 52 "$display", "%0d comparison(s) mismatched\012ERROR: SIM: Simulation Failed", v0x15cf680_0 {0 0 0}; + %vpi_call/w 3 53 "$fatal", 32'sb00000000000000000000000000000001 {0 0 0}; +T_11.9 ; + %delay 200000, 0; + %vpi_call/w 3 56 "$finish" {0 0 0}; + %end; + .thread T_11; + .scope S_0x19bf380; +T_12 ; + %vpi_call/w 3 69 "$dumpfile", "tb.vcd" {0 0 0}; + %vpi_call/w 3 70 "$dumpvars" {0 0 0}; + %end; + .thread T_12; +# The file index is used to find the file name in the following table. +:file_names 11; + "N/A"; + ""; + "-"; + "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./sim/co_sim_tb/co_sim_clk_buf_primitive_inst.v"; + "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v"; + "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CLK_BUF.v"; + "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/I_BUF.v"; + "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/clk_buf_primitive_inst/run_1/synth_1_1/synthesis/clk_buf_primitive_inst_post_synth.v"; + "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v"; + "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_FAB.v"; + "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_BUFT.v"; diff --git a/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/simulate_gate/clk_buf_primitive_inst_comp_simulation.cmd b/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/simulate_gate/clk_buf_primitive_inst_comp_simulation.cmd new file mode 100644 index 00000000..2449aa4e --- /dev/null +++ b/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/simulate_gate/clk_buf_primitive_inst_comp_simulation.cmd @@ -0,0 +1 @@ +/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/HDL_simulator/iverilog/bin/iverilog -DIVERILOG=1 -v -DGATE_SIM=1 -s co_sim_clk_buf_primitive_inst -I../../../.././rtl -I/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl -I/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./sim/co_sim_tb -g2012 /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./sim/co_sim_tb/co_sim_clk_buf_primitive_inst.v /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/clk_buf_primitive_inst/run_1/synth_1_1/synthesis/clk_buf_primitive_inst_post_synth.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/simlib.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/brams_sim.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/llatches_sim.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DSP19X2.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/SOC_FPGA_INTF_AXI_M0.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/FCLK_BUF.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/PLL.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_BUFT_DS.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT5.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT4.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/I_BUF_DS.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/MIPI_TX.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/SOC_FPGA_INTF_AXI_M1.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/I_FAB.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/I_DDR.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/SOC_FPGA_INTF_DMA.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_DELAY.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_BUF_DS.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT6.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DSP38.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/I_BUF.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DLY_VALUE_MUX.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/MIPI_RX.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DLY_SEL_DCODER.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/TDP_RAM18KX2.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/SOC_FPGA_INTF_IRQ.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_DDR.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/SOC_FPGA_INTF_AHB_S.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/I_SERDES.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_FAB.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_SERDES_CLK.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/TDP_RAM36K.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/I_DELAY.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT3.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT2.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_BUF.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/SOC_FPGA_INTF_AHB_M.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DLY_SEL_DECODER.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/FIFO18KX2.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/BOOT_CLOCK.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/FIFO36K.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT1.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CLK_BUF.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/SOC_FPGA_TEMPERATURE.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/SOC_FPGA_INTF_JTAG.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_SERDES.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CARRY.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_BUFT.v diff --git a/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/simulate_gate/clk_buf_primitive_inst_simulation.cmd b/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/simulate_gate/clk_buf_primitive_inst_simulation.cmd new file mode 100644 index 00000000..924b8fae --- /dev/null +++ b/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/simulate_gate/clk_buf_primitive_inst_simulation.cmd @@ -0,0 +1 @@ +/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/HDL_simulator/iverilog/bin/vvp ./a.out -fst diff --git a/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/simulate_gate/simulation_gate.rpt b/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/simulate_gate/simulation_gate.rpt new file mode 100644 index 00000000..3a20de77 --- /dev/null +++ b/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/simulate_gate/simulation_gate.rpt @@ -0,0 +1,216 @@ +/******************************************************************************* +Copyright (c) 2022-2024 Rapid Silicon +This source code contains proprietary information belonging to Rapid Silicon +(the "licensor") released under license and non-disclosure agreement to the +recipient (the "licensee"). + +The information shared and protected by the license and non-disclosure agreement +includes but is not limited to the following: +* operational algorithms of the product +* logos, graphics, source code, and visual presentation of the product +* confidential operational information of the licensor + +The recipient of this source code is NOT permitted to publicly disclose, +re-use, archive beyond the period of the license agreement, transfer to a +sub-licensee, or re-implement any portion of the content covered by the license +and non-disclosure agreement without the prior written consent of the licensor. +*********************************************************************************/ + +Version : 2024.10 +Build : 1.2.18 +Hash : 82370d4 +Date : Oct 12 2024 +Type : Engineering +Log Time : Mon Oct 14 05:17:34 2024 GMT +Icarus Verilog Preprocessor version 13.0 (devel) (s20221226-498-g52d049b51) + +Copyright (c) 1999-2024 Stephen Williams (steve@icarus.com) + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +Using language generation: IEEE1800-2012,no-specify,no-interconnect,xtypes,icarus-misc +PARSING INPUT +/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v:64: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v:65: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v:66: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v:67: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v:68: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v:69: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v:70: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v:71: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v:73: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v:74: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v:75: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v:76: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v:64: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v:65: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v:66: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v:67: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v:68: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v:69: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v:70: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v:71: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v:73: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v:74: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v:75: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v:76: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v:77: warning: Timing checks are not supported. + ... done, ELABORATING DESIGN +0.02 seconds. +RUNNING FUNCTORS + ... Iteration detected 3 optimizations. + ... Iteration detected 0 optimizations. + ... Look for dangling constants + ... done + ... done, 0 seconds. + -F cprop ... + -F nodangle ... + ... scan for dangling signal and event nodes. (scomplete=F, ecomplete=F) + ... 1 iterations deleted 24 dangling signals and 0 events. + ... scan for dangling signal and event nodes. (scomplete=T, ecomplete=F) + ... 2 iterations deleted 24 dangling signals and 3 events. + ... done +CALCULATING ISLANDS + ... done, 0 seconds. +CODE GENERATION + ... invoking target_design + ... done, 0.01 seconds. +STATISTICS +lex_string: add_count=5198 hit_count=32063 +Icarus Verilog version 13.0 (devel) (s20221226-498-g52d049b51) + +Copyright (c) 2000-2024 Stephen Williams (steve@icarus.com) + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + +translate: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/HDL_simulator/iverilog/lib/ivl/ivlpp -v -L -F"/tmp/ivrlg2667e83e2" -f"/tmp/ivrlg667e83e2" -p"/tmp/ivrli667e83e2" |/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/HDL_simulator/iverilog/lib/ivl/ivl -v -C"/tmp/ivrlh667e83e2" -C"/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/HDL_simulator/iverilog/lib/ivl/vvp.conf" -- - +FST info: dumpfile tb.vcd opened for output. +Data Mismatch: Actual output: 0, Netlist Output 1, Time: 20000 +Data Mismatch: Actual output: 0, Netlist Output 1, Time: 30000 +Data Mismatch: Actual output: 0, Netlist Output 1, Time: 40000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 50000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 60000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 70000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 80000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 90000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 100000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 110000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 120000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 130000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 140000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 150000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 160000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 170000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 180000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 190000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 200000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 210000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 220000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 230000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 240000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 250000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 260000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 270000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 280000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 290000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 300000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 310000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 320000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 330000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 340000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 350000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 360000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 370000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 380000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 390000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 400000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 410000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 420000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 430000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 440000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 450000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 460000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 470000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 480000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 490000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 500000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 510000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 520000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 530000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 540000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 550000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 560000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 570000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 580000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 590000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 600000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 610000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 620000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 630000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 640000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 650000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 660000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 670000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 680000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 690000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 700000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 710000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 720000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 730000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 740000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 750000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 760000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 770000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 780000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 790000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 800000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 810000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 820000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 830000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 840000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 850000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 860000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 870000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 880000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 890000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 900000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 910000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 920000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 930000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 940000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 950000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 960000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 970000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 980000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 990000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 1000000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 1010000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 1020000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 1060000 +3 comparison(s) mismatched +ERROR: SIM: Simulation Failed +FATAL: /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./sim/co_sim_tb/co_sim_clk_buf_primitive_inst.v:53: + Time: 1060000 Scope: co_sim_clk_buf_primitive_inst diff --git a/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/simulate_gate/tb.vcd b/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/simulate_gate/tb.vcd new file mode 100644 index 00000000..f4077d8e Binary files /dev/null and b/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/simulate_gate/tb.vcd differ diff --git a/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/synthesis/clk_buf_primitive_inst.ys b/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/synthesis/clk_buf_primitive_inst.ys new file mode 100644 index 00000000..4633ebc5 --- /dev/null +++ b/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/synthesis/clk_buf_primitive_inst.ys @@ -0,0 +1,26 @@ + +# Yosys synthesis script for clk_buf_primitive_inst +# Read source files +read_verilog -sv /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v +verilog_defines +read_verilog -I../../../.././rtl -I../../../../ -I/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v + + +# Technology mapping +hierarchy -top clk_buf_primitive_inst + + + +plugin -i synth-rs + +synth_rs -post_cleanup 1 -legalize_ram_clk_ports -new_iobuf_map 3 -iofab_map 1 -tech genesis3 -de -goal delay -effort high -carry auto -keep_tribuf -new_dsp19x2 -new_tdp36k -max_lut 17472 -max_reg 34944 -max_device_dsp 56 -max_device_bram 56 -max_device_carry_length 336 -max_dsp 56 -max_bram 56 -max_carry_length 336 -fsm_encoding onehot -de_max_threads -1 + +write_verilog -noexpr -nodec -norename -v clk_buf_primitive_inst_post_synth.v +write_blif -param clk_buf_primitive_inst_post_synth.eblif + +plugin -i design-edit +design_edit -tech genesis3 -sdc pin_location_clk_buf_primitive_inst.sdc -json config.json -w wrapper_clk_buf_primitive_inst_post_synth.v wrapper_clk_buf_primitive_inst_post_synth.eblif -pr post_pnr_wrapper_clk_buf_primitive_inst_post_synth.v post_pnr_wrapper_clk_buf_primitive_inst_post_synth.eblif +write_verilog -noexpr -nodec -norename -v fabric_clk_buf_primitive_inst_post_synth.v +write_blif -param fabric_clk_buf_primitive_inst_post_synth.eblif + + \ No newline at end of file diff --git a/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/synthesis/clk_buf_primitive_inst_post_synth.eblif b/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/synthesis/clk_buf_primitive_inst_post_synth.eblif new file mode 100644 index 00000000..f6a7aaa2 --- /dev/null +++ b/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/synthesis/clk_buf_primitive_inst_post_synth.eblif @@ -0,0 +1,18 @@ +# Generated by Yosys 0.44 (git sha1 7a4a3768c, g++ 11.2.1 -fPIC -O3) + +.model clk_buf_primitive_inst +.inputs clock_input ibuf_enable +.outputs clock_output +.names $false +.names $true +1 +.names $undef +.subckt DFFRE C=wire1 D=wire2 E=$true Q=wire_out_clk R=$true +.subckt O_FAB I=wire_out_clk O=$f2g_tx_out_wire_out_clk +.subckt I_BUF EN=$true I=clock_input O=wire2 +.param WEAK_KEEPER "NONE" +.subckt I_BUF EN=$true I=ibuf_enable O=$ibuf_ibuf_enable +.param WEAK_KEEPER "NONE" +.subckt O_BUFT I=$f2g_tx_out_wire_out_clk O=clock_output T=$true +.subckt CLK_BUF I=wire2 O=wire1 +.end diff --git a/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/synthesis/clk_buf_primitive_inst_post_synth.v b/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/synthesis/clk_buf_primitive_inst_post_synth.v new file mode 100644 index 00000000..48484ab0 --- /dev/null +++ b/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/synthesis/clk_buf_primitive_inst_post_synth.v @@ -0,0 +1,84 @@ +/* Generated by Yosys 0.44 (git sha1 7a4a3768c, g++ 11.2.1 -fPIC -O3) */ + +module clk_buf_primitive_inst_post_synth(clock_input, ibuf_enable, clock_output); + input clock_input; + output clock_output; + input ibuf_enable; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:8.5-8.17" *) + wire \$f2g_tx_out_wire_out_clk ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:3.9-3.20" *) + (* unused_bits = "0" *) + wire \$ibuf_ibuf_enable ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:2.9-2.20" *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:2.9-2.20" *) + wire clock_input; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:4.10-4.22" *) + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:4.10-4.22" *) + wire clock_output; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:3.9-3.20" *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:3.9-3.20" *) + wire ibuf_enable; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:7.6-7.11" *) + wire wire1; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:7.13-7.18" *) + wire wire2; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:8.5-8.17" *) + wire wire_out_clk; + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:10.11-10.70" *) + DFFRE \$abc$194$auto_195 ( + .C(wire1), + .D(wire2), + .E(1'h1), + .Q(wire_out_clk), + .R(1'h1) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_wire_out_clk_1 ( + .I(wire_out_clk), + .O(\$f2g_tx_out_wire_out_clk ) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$clk_buf_primitive_inst.$ibuf_clock_input ( + .EN(1'h1), + .I(clock_input), + .O(wire2) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$clk_buf_primitive_inst.$ibuf_ibuf_enable ( + .EN(1'h1), + .I(ibuf_enable), + .O(\$ibuf_ibuf_enable ) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) + O_BUFT \$obuf$clk_buf_primitive_inst.$obuf_clock_output ( + .I(\$f2g_tx_out_wire_out_clk ), + .O(clock_output), + .T(1'h1) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:21.11-24.4" *) + CLK_BUF clk_buf_inst ( + .I(wire2), + .O(wire1) + ); +endmodule + diff --git a/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/synthesis/clk_buf_primitive_inst_synth.log b/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/synthesis/clk_buf_primitive_inst_synth.log new file mode 100644 index 00000000..29b11693 --- /dev/null +++ b/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/synthesis/clk_buf_primitive_inst_synth.log @@ -0,0 +1,2264 @@ + + /----------------------------------------------------------------------------\ + | yosys -- Yosys Open SYnthesis Suite | + | Copyright (C) 2012 - 2024 Claire Xenia Wolf | + | Distributed under an ISC-like license, type "license" to see terms | + \----------------------------------------------------------------------------/ + + Yosys 0.44 (git sha1 7a4a3768c, g++ 11.2.1 -fPIC -O3) + +-- Executing script file `clk_buf_primitive_inst.ys' -- + +1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v +Parsing SystemVerilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v' to AST representation. +Generating RTLIL representation for module `\BOOT_CLOCK'. +Generating RTLIL representation for module `\CARRY'. +Generating RTLIL representation for module `\CLK_BUF'. +Generating RTLIL representation for module `\DFFNRE'. +Generating RTLIL representation for module `\DFFRE'. +Generating RTLIL representation for module `\DLY_SEL_DCODER'. +Generating RTLIL representation for module `\DLY_SEL_DECODER'. +Generating RTLIL representation for module `\DLY_VALUE_MUX'. +Generating RTLIL representation for module `\DSP19X2'. +Generating RTLIL representation for module `\DSP38'. +Generating RTLIL representation for module `\FCLK_BUF'. +Generating RTLIL representation for module `\FIFO18KX2'. +Generating RTLIL representation for module `\FIFO36K'. +Generating RTLIL representation for module `\I_BUF_DS'. +Generating RTLIL representation for module `\I_BUF'. +Generating RTLIL representation for module `\I_DDR'. +Generating RTLIL representation for module `\I_DELAY'. +Generating RTLIL representation for module `\I_FAB'. +Generating RTLIL representation for module `\I_SERDES'. +Generating RTLIL representation for module `\LATCHNR'. +Generating RTLIL representation for module `\LATCHNS'. +Generating RTLIL representation for module `\LATCHN'. +Generating RTLIL representation for module `\LATCHR'. +Generating RTLIL representation for module `\LATCHS'. +Generating RTLIL representation for module `\LATCH'. +Generating RTLIL representation for module `\LUT1'. +Generating RTLIL representation for module `\LUT2'. +Generating RTLIL representation for module `\LUT3'. +Generating RTLIL representation for module `\LUT4'. +Generating RTLIL representation for module `\LUT5'. +Generating RTLIL representation for module `\LUT6'. +Generating RTLIL representation for module `\MIPI_RX'. +Generating RTLIL representation for module `\MIPI_TX'. +Generating RTLIL representation for module `\O_BUF_DS'. +Generating RTLIL representation for module `\O_BUFT_DS'. +Generating RTLIL representation for module `\O_BUFT'. +Generating RTLIL representation for module `\O_BUF'. +Generating RTLIL representation for module `\O_DDR'. +Generating RTLIL representation for module `\O_DELAY'. +Generating RTLIL representation for module `\O_FAB'. +Generating RTLIL representation for module `\O_SERDES_CLK'. +Generating RTLIL representation for module `\O_SERDES'. +Generating RTLIL representation for module `\PLL'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AHB_M'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AHB_S'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AXI_M0'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AXI_M1'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_DMA'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_IRQ'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_JTAG'. +Generating RTLIL representation for module `\SOC_FPGA_TEMPERATURE'. +Generating RTLIL representation for module `\TDP_RAM18KX2'. +Generating RTLIL representation for module `\TDP_RAM36K'. +Successfully finished Verilog frontend. + +2. Executing Verilog-2005 frontend: /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v +Parsing Verilog input from `/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v' to AST representation. +Generating RTLIL representation for module `\clk_buf_primitive_inst'. +Successfully finished Verilog frontend. + +3. Executing HIERARCHY pass (managing design hierarchy). + +3.1. Analyzing design hierarchy.. +Top module: \clk_buf_primitive_inst + +3.2. Analyzing design hierarchy.. +Top module: \clk_buf_primitive_inst +Removed 0 unused modules. + +4. Executing synth_rs pass: v0.4.218 + +4.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/common/cells_sim.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/common/cells_sim.v' to AST representation. +Generating RTLIL representation for module `\inv'. +Generating RTLIL representation for module `\buff'. +Generating RTLIL representation for module `\logic_0'. +Generating RTLIL representation for module `\logic_1'. +Generating RTLIL representation for module `\gclkbuff'. +Successfully finished Verilog frontend. + +4.2. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CARRY.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CARRY.v' to AST representation. +Replacing existing blackbox module `\CARRY' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CARRY.v:10.1-33.10. +Generating RTLIL representation for module `\CARRY'. +Successfully finished Verilog frontend. + +4.3. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v' to AST representation. +Replacing existing blackbox module `\LATCH' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:20.1-34.10. +Generating RTLIL representation for module `\LATCH'. +Replacing existing blackbox module `\LATCHN' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:48.1-62.10. +Generating RTLIL representation for module `\LATCHN'. +Replacing existing blackbox module `\LATCHR' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:81.1-97.10. +Generating RTLIL representation for module `\LATCHR'. +Replacing existing blackbox module `\LATCHS' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:115.1-131.10. +Generating RTLIL representation for module `\LATCHS'. +Replacing existing blackbox module `\LATCHNR' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:150.1-166.10. +Generating RTLIL representation for module `\LATCHNR'. +Replacing existing blackbox module `\LATCHNS' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:184.1-200.10. +Generating RTLIL representation for module `\LATCHNS'. +Generating RTLIL representation for module `\LATCHSRE'. +Generating RTLIL representation for module `\LATCHNSRE'. +Successfully finished Verilog frontend. + +4.4. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v' to AST representation. +Replacing existing blackbox module `\DFFRE' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v:11.1-81.10. +Generating RTLIL representation for module `\DFFRE'. +Successfully finished Verilog frontend. + +4.5. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v' to AST representation. +Replacing existing blackbox module `\DFFNRE' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v:11.1-80.10. +Generating RTLIL representation for module `\DFFNRE'. +Successfully finished Verilog frontend. + +4.6. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT1.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT1.v' to AST representation. +Replacing existing blackbox module `\LUT1' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT1.v:10.1-20.10. +Generating RTLIL representation for module `\LUT1'. +Successfully finished Verilog frontend. + +4.7. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT2.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT2.v' to AST representation. +Replacing existing blackbox module `\LUT2' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT2.v:10.1-21.10. +Generating RTLIL representation for module `\LUT2'. +Successfully finished Verilog frontend. + +4.8. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT3.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT3.v' to AST representation. +Replacing existing blackbox module `\LUT3' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT3.v:10.1-22.10. +Generating RTLIL representation for module `\LUT3'. +Successfully finished Verilog frontend. + +4.9. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT4.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT4.v' to AST representation. +Replacing existing blackbox module `\LUT4' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT4.v:11.1-25.10. +Generating RTLIL representation for module `\LUT4'. +Successfully finished Verilog frontend. + +4.10. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT5.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT5.v' to AST representation. +Replacing existing blackbox module `\LUT5' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT5.v:10.1-24.10. +Generating RTLIL representation for module `\LUT5'. +Successfully finished Verilog frontend. + +4.11. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT6.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT6.v' to AST representation. +Replacing existing blackbox module `\LUT6' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT6.v:10.1-25.10. +Generating RTLIL representation for module `\LUT6'. +Successfully finished Verilog frontend. + +4.12. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CLK_BUF.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CLK_BUF.v' to AST representation. +Replacing existing blackbox module `\CLK_BUF' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CLK_BUF.v:10.1-25.10. +Generating RTLIL representation for module `\CLK_BUF'. +Successfully finished Verilog frontend. + +4.13. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_BUF.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_BUF.v' to AST representation. +Replacing existing blackbox module `\O_BUF' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_BUF.v:10.1-84.10. +Generating RTLIL representation for module `\O_BUF'. +Successfully finished Verilog frontend. + +4.14. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DSP38.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DSP38.v' to AST representation. +Replacing existing blackbox module `\DSP38' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DSP38.v:10.1-341.10. +Generating RTLIL representation for module `\DSP38'. +Successfully finished Verilog frontend. + +4.15. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v' to AST representation. +Replacing existing blackbox module `\TDP_RAM36K' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v:2.1-29.10. +Generating RTLIL representation for module `\TDP_RAM36K'. +Replacing existing blackbox module `\TDP_RAM18KX2' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v:33.1-84.10. +Generating RTLIL representation for module `\TDP_RAM18KX2'. +Generating RTLIL representation for module `\RS_DSP3'. +Replacing existing blackbox module `\DSP19X2' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v:116.1-149.10. +Generating RTLIL representation for module `\DSP19X2'. +Successfully finished Verilog frontend. + +4.16. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v' to AST representation. +Generating RTLIL representation for module `\TDP_BRAM18'. +Generating RTLIL representation for module `\BRAM2x18_TDP'. +Generating RTLIL representation for module `\BRAM2x18_SDP'. +Generating RTLIL representation for module `\_$_mem_v2_asymmetric'. +Successfully finished Verilog frontend. + +4.17. Executing HIERARCHY pass (managing design hierarchy). + +4.17.1. Analyzing design hierarchy.. +Top module: \clk_buf_primitive_inst + +4.17.2. Analyzing design hierarchy.. +Top module: \clk_buf_primitive_inst +Removed 0 unused modules. + +4.18. Executing PROC pass (convert processes to netlists). + +4.18.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +4.18.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Removed a total of 0 dead cases. + +4.18.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 0 redundant assignments. +Promoted 2 assignments to connections. + +4.18.4. Executing PROC_INIT pass (extract init attributes). +Found init rule in `\clk_buf_primitive_inst.$proc$/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:8$2'. + Set init value: \wire_out_clk = 1'0 + +4.18.5. Executing PROC_ARST pass (detect async resets in processes). + +4.18.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. + +4.18.7. Executing PROC_MUX pass (convert decision trees to multiplexers). +Creating decoders for process `\clk_buf_primitive_inst.$proc$/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:8$2'. +Creating decoders for process `\clk_buf_primitive_inst.$proc$/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:16$1'. + +4.18.8. Executing PROC_DLATCH pass (convert process syncs to latches). + +4.18.9. Executing PROC_DFF pass (convert process syncs to FFs). +Creating register for signal `\clk_buf_primitive_inst.\wire_out_clk' using process `\clk_buf_primitive_inst.$proc$/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:16$1'. + created $dff cell `$procdff$3' with positive edge clock. + +4.18.10. Executing PROC_MEMWR pass (convert process memory writes to cells). + +4.18.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Removing empty process `clk_buf_primitive_inst.$proc$/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:8$2'. +Removing empty process `clk_buf_primitive_inst.$proc$/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:16$1'. +Cleaned up 0 empty switches. + +4.18.12. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.19. Executing FLATTEN pass (flatten design). + +# -------------------- +# Design entry stats +# -------------------- + +4.20. Printing statistics. + +=== clk_buf_primitive_inst === + + Number of wires: 8 + Number of wire bits: 8 + Number of public wires: 6 + Number of public wire bits: 6 + Number of ports: 3 + Number of port bits: 3 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $dff 1 + CLK_BUF 1 + I_BUF 1 + +4.21. Executing SPLITNETS pass (splitting up multi-bit signals). + +4.22. Executing DEMUXMAP pass. + +4.23. Executing FLATTEN pass (flatten design). + +4.24. Executing DEMUXMAP pass. + +4.25. Executing TRIBUF pass. +Warning: Ignored -no_iobuf because -keep_tribuf is used. + +4.26. Executing DEMINOUT pass (demote inout ports to input or output). + +4.27. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.28. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. +Removed 0 unused cells and 2 unused wires. + + +4.29. Executing CHECK pass (checking for obvious problems). +Checking module clk_buf_primitive_inst... +Found and reported 0 problems. + +4.30. Printing statistics. + +=== clk_buf_primitive_inst === + + Number of wires: 6 + Number of wire bits: 6 + Number of public wires: 6 + Number of public wire bits: 6 + Number of ports: 3 + Number of port bits: 3 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $dff 1 + CLK_BUF 1 + I_BUF 1 + +FF init value for cell $procdff$3 ($dff): \wire_out_clk = 1'0 + +4.31. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.32. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.33. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \clk_buf_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.34. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \clk_buf_primitive_inst. +Performed a total of 0 changes. + +4.35. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.36. Executing OPT_SHARE pass. + +4.37. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.38. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.39. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.40. Executing FSM pass (extract and optimize FSM). + +4.40.1. Executing FSM_DETECT pass (finding FSMs in design). + +4.40.2. Executing FSM_EXTRACT pass (extracting FSM from design). + +4.40.3. Executing FSM_OPT pass (simple optimizations of FSMs). + +4.40.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.40.5. Executing FSM_OPT pass (simple optimizations of FSMs). + +4.40.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). + +4.40.7. Executing FSM_INFO pass (dumping all available information on FSM cells). + +4.40.8. Executing FSM_MAP pass (mapping FSMs to basic logic). + +4.41. Executing WREDUCE pass (reducing word size of cells). + +4.42. Executing PEEPOPT pass (run peephole optimizers). + +4.43. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.44. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.45. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.46. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \clk_buf_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.47. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \clk_buf_primitive_inst. +Performed a total of 0 changes. + +4.48. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.49. Executing OPT_SHARE pass. + +4.50. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.51. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.52. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.53. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.54. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.55. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \clk_buf_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.56. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \clk_buf_primitive_inst. +Performed a total of 0 changes. + +4.57. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.58. Executing OPT_SHARE pass. + +4.59. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.60. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.61. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.62. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.63. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.64. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \clk_buf_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.65. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \clk_buf_primitive_inst. +Performed a total of 0 changes. + +4.66. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.67. Executing OPT_SHARE pass. + +4.68. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.69. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=1, #remove=0, time=0.00 sec.] + +4.70. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.71. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.72. Executing WREDUCE pass (reducing word size of cells). + +4.73. Executing PEEPOPT pass (run peephole optimizers). + +4.74. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.75. Executing DEMUXMAP pass. + +4.76. Executing SPLITNETS pass (splitting up multi-bit signals). + +4.77. Printing statistics. + +=== clk_buf_primitive_inst === + + Number of wires: 6 + Number of wire bits: 6 + Number of public wires: 6 + Number of public wire bits: 6 + Number of ports: 3 + Number of port bits: 3 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $dff 1 + CLK_BUF 1 + I_BUF 1 + +4.78. Executing RS_DSP_MULTADD pass. + +4.79. Executing WREDUCE pass (reducing word size of cells). + +4.80. Executing RS_DSP_MACC pass. + +4.81. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.82. Executing TECHMAP pass (map to technology primitives). + +4.82.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/mul2dsp_check_maxwidth.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/mul2dsp_check_maxwidth.v' to AST representation. +Generating RTLIL representation for module `\_80_mul'. +Generating RTLIL representation for module `\_90_soft_mul'. +Successfully finished Verilog frontend. + +4.82.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.83. Printing statistics. + +=== clk_buf_primitive_inst === + + Number of wires: 6 + Number of wire bits: 6 + Number of public wires: 6 + Number of public wire bits: 6 + Number of ports: 3 + Number of port bits: 3 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $dff 1 + CLK_BUF 1 + I_BUF 1 + +4.84. Executing TECHMAP pass (map to technology primitives). + +4.84.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/mul2dsp_check_maxwidth.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/mul2dsp_check_maxwidth.v' to AST representation. +Generating RTLIL representation for module `\_80_mul'. +Generating RTLIL representation for module `\_90_soft_mul'. +Successfully finished Verilog frontend. + +4.84.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.85. Printing statistics. + +=== clk_buf_primitive_inst === + + Number of wires: 6 + Number of wire bits: 6 + Number of public wires: 6 + Number of public wire bits: 6 + Number of ports: 3 + Number of port bits: 3 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $dff 1 + CLK_BUF 1 + I_BUF 1 + +4.86. Executing TECHMAP pass (map to technology primitives). + +4.86.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/mul2dsp.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/mul2dsp.v' to AST representation. +Generating RTLIL representation for module `\_80_mul'. +Generating RTLIL representation for module `\_90_soft_mul'. +Successfully finished Verilog frontend. + +4.86.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.87. Executing TECHMAP pass (map to technology primitives). + +4.87.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/mul2dsp.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/mul2dsp.v' to AST representation. +Generating RTLIL representation for module `\_80_mul'. +Generating RTLIL representation for module `\_90_soft_mul'. +Successfully finished Verilog frontend. + +4.87.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.88. Executing TECHMAP pass (map to technology primitives). + +4.88.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/dsp_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/dsp_map.v' to AST representation. +Generating RTLIL representation for module `\$__RS_MUL20X18'. +Generating RTLIL representation for module `\$__RS_MUL10X9'. +Successfully finished Verilog frontend. + +4.88.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.89. Executing RS_DSP_SIMD pass. + +4.90. Executing TECHMAP pass (map to technology primitives). + +4.90.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/dsp_final_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/dsp_final_map.v' to AST representation. +Generating RTLIL representation for module `\dsp_t1_20x18x64_cfg_ports'. +Generating RTLIL representation for module `\dsp_t1_10x9x32_cfg_params'. +Successfully finished Verilog frontend. + +4.90.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.91. Executing TECHMAP pass (map to technology primitives). + +4.91.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/dsp19x2_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/dsp19x2_map.v' to AST representation. +Generating RTLIL representation for module `\RS_DSPX2_MULTACC'. +Generating RTLIL representation for module `\RS_DSPX2_MULT'. +Generating RTLIL representation for module `\RS_DSPX2_MULT_REGIN'. +Generating RTLIL representation for module `\RS_DSPX2_MULT_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULT_REGIN_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULTADD'. +Generating RTLIL representation for module `\RS_DSPX2_MULTADD_REGIN'. +Generating RTLIL representation for module `\RS_DSPX2_MULTADD_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULTADD_REGIN_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULTACC_REGIN'. +Generating RTLIL representation for module `\RS_DSPX2_MULTACC_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULTACC_REGIN_REGOUT'. +Generating RTLIL representation for module `\RS_DSP3'. +Successfully finished Verilog frontend. + +4.91.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.92. Executing rs_pack_dsp_regs pass. + +4.93. Executing RS_DSP_IO_REGS pass. + +4.94. Executing TECHMAP pass (map to technology primitives). + +4.94.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/dsp38_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/dsp38_map.v' to AST representation. +Generating RTLIL representation for module `\RS_DSP_MULTACC'. +Generating RTLIL representation for module `\RS_DSP_MULT'. +Generating RTLIL representation for module `\RS_DSP_MULT_REGIN'. +Generating RTLIL representation for module `\RS_DSP_MULT_REGOUT'. +Generating RTLIL representation for module `\RS_DSP_MULT_REGIN_REGOUT'. +Generating RTLIL representation for module `\RS_DSP_MULTADD'. +Generating RTLIL representation for module `\RS_DSP_MULTADD_REGIN'. +Generating RTLIL representation for module `\RS_DSP_MULTADD_REGOUT'. +Generating RTLIL representation for module `\RS_DSP_MULTADD_REGIN_REGOUT'. +Generating RTLIL representation for module `\RS_DSP_MULTACC_REGIN'. +Generating RTLIL representation for module `\RS_DSP_MULTACC_REGOUT'. +Generating RTLIL representation for module `\RS_DSP_MULTACC_REGIN_REGOUT'. +Successfully finished Verilog frontend. + +4.94.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.95. Executing TECHMAP pass (map to technology primitives). + +4.95.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/dsp19x2_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/dsp19x2_map.v' to AST representation. +Generating RTLIL representation for module `\RS_DSPX2_MULTACC'. +Generating RTLIL representation for module `\RS_DSPX2_MULT'. +Generating RTLIL representation for module `\RS_DSPX2_MULT_REGIN'. +Generating RTLIL representation for module `\RS_DSPX2_MULT_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULT_REGIN_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULTADD'. +Generating RTLIL representation for module `\RS_DSPX2_MULTADD_REGIN'. +Generating RTLIL representation for module `\RS_DSPX2_MULTADD_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULTADD_REGIN_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULTACC_REGIN'. +Generating RTLIL representation for module `\RS_DSPX2_MULTACC_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULTACC_REGIN_REGOUT'. +Generating RTLIL representation for module `\RS_DSP3'. +Successfully finished Verilog frontend. + +4.95.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.96. Printing statistics. + +=== clk_buf_primitive_inst === + + Number of wires: 6 + Number of wire bits: 6 + Number of public wires: 6 + Number of public wire bits: 6 + Number of ports: 3 + Number of port bits: 3 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $dff 1 + CLK_BUF 1 + I_BUF 1 + +4.97. Executing ALUMACC pass (create $alu and $macc cells). +Extracting $alu and $macc cells in module clk_buf_primitive_inst: + created 0 $alu and 0 $macc cells. + +4.98. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.99. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.100. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \clk_buf_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.101. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \clk_buf_primitive_inst. +Performed a total of 0 changes. + +4.102. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.103. Executing OPT_SHARE pass. + +4.104. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.105. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.106. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.107. Printing statistics. + +=== clk_buf_primitive_inst === + + Number of wires: 6 + Number of wire bits: 6 + Number of public wires: 6 + Number of public wire bits: 6 + Number of ports: 3 + Number of port bits: 3 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $dff 1 + CLK_BUF 1 + I_BUF 1 + +4.108. Executing MEMORY pass. + +4.108.1. Executing OPT_MEM pass (optimize memories). +Performed a total of 0 transformations. + +4.108.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). +Performed a total of 0 transformations. + +4.108.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). + +4.108.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). + +4.108.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). + +4.108.6. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.108.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). + +4.108.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). +Performed a total of 0 transformations. + +4.108.9. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.108.10. Executing MEMORY_COLLECT pass (generating $mem cells). + +4.109. Printing statistics. + +=== clk_buf_primitive_inst === + + Number of wires: 6 + Number of wire bits: 6 + Number of public wires: 6 + Number of public wire bits: 6 + Number of ports: 3 + Number of port bits: 3 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $dff 1 + CLK_BUF 1 + I_BUF 1 + +4.110. Executing MUXPACK pass ($mux cell cascades to $pmux). +Converted 0 (p)mux cells into 0 pmux cells. + +4.111. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.112. Executing MEMORY_LIBMAP pass (mapping memories to cells). + +4.113. Executing MEMORY_LIBMAP pass (mapping memories to cells). + +4.114. Executing Rs_BRAM_Split pass. + +4.115. Executing TECHMAP pass (map to technology primitives). + +4.115.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_map_new_version.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_map_new_version.v' to AST representation. +Generating RTLIL representation for module `\$__RS_FACTOR_BRAM36_TDP'. +Generating RTLIL representation for module `\$__RS_FACTOR_BRAM18_TDP'. +Generating RTLIL representation for module `\$__RS_FACTOR_BRAM18_SDP'. +Generating RTLIL representation for module `\$__RS_FACTOR_BRAM36_SDP'. +Successfully finished Verilog frontend. + +4.115.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.116. Executing TECHMAP pass (map to technology primitives). + +4.116.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_final_map_new_version.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_final_map_new_version.v' to AST representation. +Generating RTLIL representation for module `\BRAM2x18_TDP'. +Generating RTLIL representation for module `\BRAM2x18_SDP'. +Successfully finished Verilog frontend. + +4.116.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.117. Executing DFFUNMAP pass (unmap clock enable and synchronous reset from FFs). + +4.118. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.119. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.120. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \clk_buf_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.121. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \clk_buf_primitive_inst. +Performed a total of 0 changes. + +4.122. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.123. Executing OPT_SHARE pass. + +4.124. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.125. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.126. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.127. Executing PMUXTREE pass. + +4.128. Executing MUXPACK pass ($mux cell cascades to $pmux). +Converted 0 (p)mux cells into 0 pmux cells. + +4.129. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). + +4.130. Executing TECHMAP pass (map to technology primitives). + +4.130.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/techmap.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu_brent_kung'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. + +4.130.2. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/arith_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/arith_map.v' to AST representation. +Generating RTLIL representation for module `\_80_rs_alu'. +Successfully finished Verilog frontend. + +4.130.3. Continuing TECHMAP pass. +Using extmapper simplemap for cells of type $dff. +No more expansions possible. + + +4.131. Printing statistics. + +=== clk_buf_primitive_inst === + + Number of wires: 6 + Number of wire bits: 6 + Number of public wires: 6 + Number of public wire bits: 6 + Number of ports: 3 + Number of port bits: 3 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $_DFF_P_ 1 + CLK_BUF 1 + I_BUF 1 + +4.132. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.133. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.134. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \clk_buf_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.135. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \clk_buf_primitive_inst. +Performed a total of 0 changes. + +4.136. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.137. Executing OPT_SHARE pass. + +4.138. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.139. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.140. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.141. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.142. Executing TECHMAP pass (map to technology primitives). + +4.142.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/techmap.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu_brent_kung'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. + +4.142.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.143. Printing statistics. + +=== clk_buf_primitive_inst === + + Number of wires: 6 + Number of wire bits: 6 + Number of public wires: 6 + Number of public wire bits: 6 + Number of ports: 3 + Number of port bits: 3 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $_DFF_P_ 1 + CLK_BUF 1 + I_BUF 1 + +4.144. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.145. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.146. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \clk_buf_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.147. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \clk_buf_primitive_inst. +Performed a total of 0 changes. + +4.148. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.149. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.150. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.151. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.152. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.153. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.154. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \clk_buf_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.155. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \clk_buf_primitive_inst. +Performed a total of 0 changes. + +4.156. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.157. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.158. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.159. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.160. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.161. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.162. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \clk_buf_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.163. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \clk_buf_primitive_inst. +Performed a total of 0 changes. + +4.164. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.165. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.166. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=1, #remove=0, time=0.00 sec.] + +4.167. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.168. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.169. Printing statistics. + +=== clk_buf_primitive_inst === + + Number of wires: 6 + Number of wire bits: 6 + Number of public wires: 6 + Number of public wire bits: 6 + Number of ports: 3 + Number of port bits: 3 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $_DFF_P_ 1 + CLK_BUF 1 + I_BUF 1 + + Number of Generic REGs: 1 + +ABC-DFF iteration : 1 + +4.170. Executing ABC pass (technology mapping using ABC). + +4.170.1. Summary of detected clock domains: + 3 cells in clk=\wire1, en={ }, arst={ }, srst={ } + + #logic partitions = 1 + +4.170.2. Extracting gate netlist of module `\clk_buf_primitive_inst' to `/input.blif'.. +Found matching posedge clock domain: \wire1 +Extracted 1 gates and 2 wires to a netlist network with 1 inputs and 1 outputs (dfl=1). + +4.170.2.1. Executing ABC. +[Time = 0.04 sec.] + +4.171. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.172. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.173. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \clk_buf_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.174. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \clk_buf_primitive_inst. +Performed a total of 0 changes. + +4.175. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.176. Executing OPT_SHARE pass. + +4.177. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.178. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. +Removed 0 unused cells and 4 unused wires. + + +4.179. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +ABC-DFF iteration : 2 + +4.180. Executing ABC pass (technology mapping using ABC). + +4.180.1. Summary of detected clock domains: + 3 cells in clk=\wire1, en={ }, arst={ }, srst={ } + + #logic partitions = 1 + +4.180.2. Extracting gate netlist of module `\clk_buf_primitive_inst' to `/input.blif'.. +Found matching posedge clock domain: \wire1 +Extracted 1 gates and 2 wires to a netlist network with 1 inputs and 1 outputs (dfl=1). + +4.180.2.1. Executing ABC. +[Time = 0.04 sec.] + +4.181. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.182. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.183. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \clk_buf_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.184. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \clk_buf_primitive_inst. +Performed a total of 0 changes. + +4.185. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.186. Executing OPT_SHARE pass. + +4.187. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.188. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. +Removed 0 unused cells and 4 unused wires. + + +4.189. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +ABC-DFF iteration : 3 + +4.190. Executing ABC pass (technology mapping using ABC). + +4.190.1. Summary of detected clock domains: + 3 cells in clk=\wire1, en={ }, arst={ }, srst={ } + + #logic partitions = 1 + +4.190.2. Extracting gate netlist of module `\clk_buf_primitive_inst' to `/input.blif'.. +Found matching posedge clock domain: \wire1 +Extracted 1 gates and 2 wires to a netlist network with 1 inputs and 1 outputs (dfl=2). + +4.190.2.1. Executing ABC. +[Time = 0.06 sec.] + +4.191. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.192. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.193. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \clk_buf_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.194. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \clk_buf_primitive_inst. +Performed a total of 0 changes. + +4.195. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.196. Executing OPT_SHARE pass. + +4.197. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.198. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. +Removed 0 unused cells and 4 unused wires. + + +4.199. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +ABC-DFF iteration : 4 + +4.200. Executing ABC pass (technology mapping using ABC). + +4.200.1. Summary of detected clock domains: + 3 cells in clk=\wire1, en={ }, arst={ }, srst={ } + + #logic partitions = 1 + +4.200.2. Extracting gate netlist of module `\clk_buf_primitive_inst' to `/input.blif'.. +Found matching posedge clock domain: \wire1 +Extracted 1 gates and 2 wires to a netlist network with 1 inputs and 1 outputs (dfl=2). + +4.200.2.1. Executing ABC. +[Time = 0.06 sec.] + +4.201. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.202. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.203. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \clk_buf_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.204. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \clk_buf_primitive_inst. +Performed a total of 0 changes. + +4.205. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.206. Executing OPT_SHARE pass. + +4.207. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.208. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. +Removed 0 unused cells and 4 unused wires. + + +4.209. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 +select with DFL2 synthesis (thresh-logic=0.920000, thresh_dff=0.980000) + +4.210. Executing OPT_FFINV pass (push inverters through FFs). +Discovering LUTs. +Pushed 0 inverters. + +4.211. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.212. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.213. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \clk_buf_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.214. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \clk_buf_primitive_inst. +Performed a total of 0 changes. + +4.215. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.216. Executing OPT_SHARE pass. + +4.217. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.218. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.219. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.220. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.221. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.222. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \clk_buf_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.223. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \clk_buf_primitive_inst. +Performed a total of 0 changes. + +4.224. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.225. Executing OPT_SHARE pass. + +4.226. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.227. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.228. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.229. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.230. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.231. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \clk_buf_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.232. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \clk_buf_primitive_inst. +Performed a total of 0 changes. + +4.233. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.234. Executing OPT_SHARE pass. + +4.235. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.236. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=1, #remove=0, time=0.00 sec.] + +4.237. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.238. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.239. Executing BMUXMAP pass. + +4.240. Executing DEMUXMAP pass. + +4.241. Executing SPLITNETS pass (splitting up multi-bit signals). + +4.242. Executing ABC pass (technology mapping using ABC). + +4.242.1. Extracting gate netlist of module `\clk_buf_primitive_inst' to `/input.blif'.. +Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs (dfl=1). +Don't call ABC as there is nothing to map. + +4.243. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.244. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.245. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \clk_buf_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.246. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \clk_buf_primitive_inst. +Performed a total of 0 changes. + +4.247. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.248. Executing OPT_SHARE pass. + +4.249. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.250. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.251. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.252. Executing OPT_FFINV pass (push inverters through FFs). +Discovering LUTs. +Pushed 0 inverters. + +4.253. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.254. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.255. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \clk_buf_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.256. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \clk_buf_primitive_inst. +Performed a total of 0 changes. + +4.257. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.258. Executing OPT_SHARE pass. + +4.259. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.260. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.261. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.262. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.263. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.264. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \clk_buf_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.265. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \clk_buf_primitive_inst. +Performed a total of 0 changes. + +4.266. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.267. Executing OPT_SHARE pass. + +4.268. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.269. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=1, #remove=0, time=0.00 sec.] + +4.270. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.271. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.272. Printing statistics. + +=== clk_buf_primitive_inst === + + Number of wires: 6 + Number of wire bits: 6 + Number of public wires: 6 + Number of public wire bits: 6 + Number of ports: 3 + Number of port bits: 3 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $_DFF_P_ 1 + CLK_BUF 1 + I_BUF 1 + +4.273. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). + +4.274. Executing RS_DFFSR_CONV pass. + +4.275. Printing statistics. + +=== clk_buf_primitive_inst === + + Number of wires: 6 + Number of wire bits: 6 + Number of public wires: 6 + Number of public wire bits: 6 + Number of ports: 3 + Number of port bits: 3 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $_DFF_P_ 1 + CLK_BUF 1 + I_BUF 1 + +4.276. Executing TECHMAP pass (map to technology primitives). + +4.276.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/techmap.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu_brent_kung'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. + +4.276.2. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v' to AST representation. +Generating RTLIL representation for module `\$_DFF_P_'. +Generating RTLIL representation for module `\$_DFF_PP0_'. +Generating RTLIL representation for module `\$_DFF_PN0_'. +Generating RTLIL representation for module `\$_DFF_PP1_'. +Generating RTLIL representation for module `\$_DFF_PN1_'. +Generating RTLIL representation for module `\$_DFFE_PP_'. +Generating RTLIL representation for module `\$_DFFE_PN_'. +Generating RTLIL representation for module `\$_DFFE_PP0P_'. +Generating RTLIL representation for module `\$_DFFE_PP0N_'. +Generating RTLIL representation for module `\$_DFFE_PN0P_'. +Generating RTLIL representation for module `\$_DFFE_PN0N_'. +Generating RTLIL representation for module `\$_DFFE_PP1P_'. +Generating RTLIL representation for module `\$_DFFE_PP1N_'. +Generating RTLIL representation for module `\$_DFFE_PN1P_'. +Generating RTLIL representation for module `\$_DFFE_PN1N_'. +Generating RTLIL representation for module `\$_DFF_N_'. +Generating RTLIL representation for module `\$_DFF_NP0_'. +Generating RTLIL representation for module `\$_DFF_NN0_'. +Generating RTLIL representation for module `\$_DFF_NP1_'. +Generating RTLIL representation for module `\$_DFF_NN1_'. +Generating RTLIL representation for module `\$_DFFE_NP_'. +Generating RTLIL representation for module `\$_DFFE_NN_'. +Generating RTLIL representation for module `\$_DFFE_NP0P_'. +Generating RTLIL representation for module `\$_DFFE_NP0N_'. +Generating RTLIL representation for module `\$_DFFE_NN0P_'. +Generating RTLIL representation for module `\$_DFFE_NN0N_'. +Generating RTLIL representation for module `\$_DFFE_NP1P_'. +Generating RTLIL representation for module `\$_DFFE_NP1N_'. +Generating RTLIL representation for module `\$_DFFE_NN1P_'. +Generating RTLIL representation for module `\$_DFFE_NN1N_'. +Generating RTLIL representation for module `\$__SHREG_DFF_P_'. +Generating RTLIL representation for module `\$_SDFF_PP0_'. +Generating RTLIL representation for module `\$_SDFF_PN0_'. +Generating RTLIL representation for module `\$_SDFF_NP0_'. +Generating RTLIL representation for module `\$_SDFF_NN0_'. +Generating RTLIL representation for module `\$_SDFF_PP1_'. +Generating RTLIL representation for module `\$_SDFF_PN1_'. +Generating RTLIL representation for module `\$_SDFF_NP1_'. +Generating RTLIL representation for module `\$_SDFF_NN1_'. +Generating RTLIL representation for module `\$_DLATCH_P_'. +Generating RTLIL representation for module `\$_DLATCH_N_'. +Generating RTLIL representation for module `\$_DLATCH_PP0_'. +Generating RTLIL representation for module `\$_DLATCH_PN0_'. +Generating RTLIL representation for module `\$_DLATCH_NP0_'. +Generating RTLIL representation for module `\$_DLATCH_NN0_'. +Generating RTLIL representation for module `\$_DLATCH_PP1_'. +Generating RTLIL representation for module `\$_DLATCH_PN1_'. +Generating RTLIL representation for module `\$_DLATCH_NP1_'. +Generating RTLIL representation for module `\$_DLATCH_NN1_'. +Successfully finished Verilog frontend. + +4.276.3. Continuing TECHMAP pass. +No more expansions possible. + + +4.277. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.278. Executing SIMPLEMAP pass (map simple cells to gate primitives). + +4.279. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.280. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.281. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=0, #solve=0, #remove=0, time=0.00 sec.] + +4.282. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. +Removed 0 unused cells and 3 unused wires. + + +4.283. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.284. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.285. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \clk_buf_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.286. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \clk_buf_primitive_inst. +Performed a total of 0 changes. + +4.287. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.288. Executing OPT_SHARE pass. + +4.289. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=0, #solve=0, #remove=0, time=0.00 sec.] + +4.290. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.291. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.292. Executing TECHMAP pass (map to technology primitives). + +4.292.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/techmap.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu_brent_kung'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. + +4.292.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.293. Executing ABC pass (technology mapping using ABC). + +4.293.1. Extracting gate netlist of module `\clk_buf_primitive_inst' to `/input.blif'.. +Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs (dfl=1). +Don't call ABC as there is nothing to map. + +4.294. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.295. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.296. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \clk_buf_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.297. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \clk_buf_primitive_inst. +Performed a total of 0 changes. + +4.298. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.299. Executing OPT_SHARE pass. + +4.300. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=0, #solve=0, #remove=0, time=0.00 sec.] + +4.301. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.302. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.303. Executing HIERARCHY pass (managing design hierarchy). + +4.303.1. Analyzing design hierarchy.. +Top module: \clk_buf_primitive_inst + +4.303.2. Analyzing design hierarchy.. +Top module: \clk_buf_primitive_inst +Removed 0 unused modules. + +4.304. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.305. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v +Parsing SystemVerilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v' to AST representation. +Generating RTLIL representation for module `\rs__CLK_BUF'. +Generating RTLIL representation for module `\rs__I_BUF'. +Generating RTLIL representation for module `\rs__O_BUF'. +Generating RTLIL representation for module `\rs__IO_BUF'. +Generating RTLIL representation for module `\rs__O_BUFT'. +Successfully finished Verilog frontend. + +4.306. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v +Parsing SystemVerilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v' to AST representation. +Replacing existing blackbox module `\BOOT_CLOCK' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:9.1-14.10. +Generating RTLIL representation for module `\BOOT_CLOCK'. +Replacing existing blackbox module `\CARRY' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:24.1-31.10. +Generating RTLIL representation for module `\CARRY'. +Replacing existing blackbox module `\CLK_BUF' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:41.1-46.10. +Generating RTLIL representation for module `\CLK_BUF'. +Replacing existing blackbox module `\DFFNRE' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:56.1-64.10. +Generating RTLIL representation for module `\DFFNRE'. +Replacing existing blackbox module `\DFFRE' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:74.1-82.10. +Generating RTLIL representation for module `\DFFRE'. +Replacing existing blackbox module `\DLY_SEL_DCODER' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:92.1-118.10. +Generating RTLIL representation for module `\DLY_SEL_DCODER'. +Replacing existing blackbox module `\DLY_SEL_DECODER' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:128.1-154.10. +Generating RTLIL representation for module `\DLY_SEL_DECODER'. +Replacing existing blackbox module `\DLY_VALUE_MUX' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:164.1-188.10. +Generating RTLIL representation for module `\DLY_VALUE_MUX'. +Replacing existing blackbox module `\DSP19X2' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:198.1-232.10. +Generating RTLIL representation for module `\DSP19X2'. +Replacing existing blackbox module `\DSP38' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:242.1-268.10. +Generating RTLIL representation for module `\DSP38'. +Replacing existing blackbox module `\FCLK_BUF' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:278.1-282.10. +Generating RTLIL representation for module `\FCLK_BUF'. +Replacing existing blackbox module `\FIFO18KX2' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:292.1-339.10. +Generating RTLIL representation for module `\FIFO18KX2'. +Replacing existing blackbox module `\FIFO36K' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:349.1-374.10. +Generating RTLIL representation for module `\FIFO36K'. +Replacing existing blackbox module `\I_BUF_DS' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:384.1-396.10. +Generating RTLIL representation for module `\I_BUF_DS'. +Replacing existing blackbox module `\I_BUF' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:406.1-415.10. +Generating RTLIL representation for module `\I_BUF'. +Replacing existing blackbox module `\I_DDR' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:425.1-433.10. +Generating RTLIL representation for module `\I_DDR'. +Replacing existing blackbox module `\I_DELAY' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:443.1-455.10. +Generating RTLIL representation for module `\I_DELAY'. +Replacing existing blackbox module `\I_FAB' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:465.1-469.10. +Generating RTLIL representation for module `\I_FAB'. +Replacing existing blackbox module `\I_SERDES' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:479.1-498.10. +Generating RTLIL representation for module `\I_SERDES'. +Replacing existing blackbox module `\LATCHNR' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:508.1-514.10. +Generating RTLIL representation for module `\LATCHNR'. +Replacing existing blackbox module `\LATCHNS' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:524.1-530.10. +Generating RTLIL representation for module `\LATCHNS'. +Replacing existing blackbox module `\LATCHN' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:540.1-545.10. +Generating RTLIL representation for module `\LATCHN'. +Replacing existing blackbox module `\LATCHR' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:555.1-561.10. +Generating RTLIL representation for module `\LATCHR'. +Replacing existing blackbox module `\LATCHS' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:571.1-577.10. +Generating RTLIL representation for module `\LATCHS'. +Replacing existing blackbox module `\LATCH' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:587.1-592.10. +Generating RTLIL representation for module `\LATCH'. +Replacing existing blackbox module `\LUT1' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:602.1-608.10. +Generating RTLIL representation for module `\LUT1'. +Replacing existing blackbox module `\LUT2' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:618.1-624.10. +Generating RTLIL representation for module `\LUT2'. +Replacing existing blackbox module `\LUT3' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:634.1-640.10. +Generating RTLIL representation for module `\LUT3'. +Replacing existing blackbox module `\LUT4' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:650.1-656.10. +Generating RTLIL representation for module `\LUT4'. +Replacing existing blackbox module `\LUT5' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:666.1-672.10. +Generating RTLIL representation for module `\LUT5'. +Replacing existing blackbox module `\LUT6' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:682.1-688.10. +Generating RTLIL representation for module `\LUT6'. +Replacing existing blackbox module `\MIPI_RX' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:698.1-724.10. +Generating RTLIL representation for module `\MIPI_RX'. +Replacing existing blackbox module `\MIPI_TX' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:734.1-761.10. +Generating RTLIL representation for module `\MIPI_TX'. +Replacing existing blackbox module `\O_BUF_DS' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:771.1-783.10. +Generating RTLIL representation for module `\O_BUF_DS'. +Replacing existing blackbox module `\O_BUFT_DS' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:793.1-805.10. +Generating RTLIL representation for module `\O_BUFT_DS'. +Replacing existing blackbox module `\O_BUFT' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:815.1-826.10. +Generating RTLIL representation for module `\O_BUFT'. +Replacing existing blackbox module `\O_BUF' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:836.1-847.10. +Generating RTLIL representation for module `\O_BUF'. +Replacing existing blackbox module `\O_DDR' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:857.1-865.10. +Generating RTLIL representation for module `\O_DDR'. +Replacing existing blackbox module `\O_DELAY' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:875.1-887.10. +Generating RTLIL representation for module `\O_DELAY'. +Replacing existing blackbox module `\O_FAB' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:897.1-901.10. +Generating RTLIL representation for module `\O_FAB'. +Replacing existing blackbox module `\O_SERDES_CLK' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:911.1-920.10. +Generating RTLIL representation for module `\O_SERDES_CLK'. +Replacing existing blackbox module `\O_SERDES' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:930.1-947.10. +Generating RTLIL representation for module `\O_SERDES'. +Replacing existing blackbox module `\PLL' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:957.1-975.10. +Generating RTLIL representation for module `\PLL'. +Replacing existing blackbox module `\SOC_FPGA_INTF_AHB_M' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:985.1-999.10. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AHB_M'. +Replacing existing blackbox module `\SOC_FPGA_INTF_AHB_S' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1009.1-1026.10. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AHB_S'. +Replacing existing blackbox module `\SOC_FPGA_INTF_AXI_M0' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1036.1-1075.10. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AXI_M0'. +Replacing existing blackbox module `\SOC_FPGA_INTF_AXI_M1' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1085.1-1124.10. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AXI_M1'. +Replacing existing blackbox module `\SOC_FPGA_INTF_DMA' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1134.1-1140.10. +Generating RTLIL representation for module `\SOC_FPGA_INTF_DMA'. +Replacing existing blackbox module `\SOC_FPGA_INTF_IRQ' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1150.1-1156.10. +Generating RTLIL representation for module `\SOC_FPGA_INTF_IRQ'. +Replacing existing blackbox module `\SOC_FPGA_INTF_JTAG' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1166.1-1174.10. +Generating RTLIL representation for module `\SOC_FPGA_INTF_JTAG'. +Replacing existing blackbox module `\SOC_FPGA_TEMPERATURE' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1184.1-1192.10. +Generating RTLIL representation for module `\SOC_FPGA_TEMPERATURE'. +Replacing existing blackbox module `\TDP_RAM18KX2' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1202.1-1257.10. +Generating RTLIL representation for module `\TDP_RAM18KX2'. +Replacing existing blackbox module `\TDP_RAM36K' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1267.1-1296.10. +Generating RTLIL representation for module `\TDP_RAM36K'. +Successfully finished Verilog frontend. + ********************************* + Removing Input/Output Buffers + ********************************* + +4.307. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + *************************** + Inserting Input Buffers + *************************** +WARNING: port '\clock_input' has no associated I_BUF +WARNING: port '\ibuf_enable' has no associated I_BUF + *************************** + Inserting Clock Buffers + *************************** + ***************************** + Inserting Output Buffers + ***************************** +WARNING: OUTPUT port '\clock_output' has no associated O_BUF + ***************************** + Mapping Tri-state Buffers + ***************************** + +4.308. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. +Removed 0 unused cells and 1 unused wires. + + +4.309. Executing TECHMAP pass (map to technology primitives). + +4.309.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v' to AST representation. +Generating RTLIL representation for module `\rs__CLK_BUF'. +Generating RTLIL representation for module `\rs__I_BUF'. +Generating RTLIL representation for module `\rs__O_BUF'. +Generating RTLIL representation for module `\rs__O_BUFT'. +Successfully finished Verilog frontend. + +4.309.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.310. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. +Removed 0 unused cells and 9 unused wires. + + +4.311. Printing statistics. + +=== clk_buf_primitive_inst === + + Number of wires: 8 + Number of wire bits: 8 + Number of public wires: 6 + Number of public wire bits: 6 + Number of ports: 3 + Number of port bits: 3 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 5 + CLK_BUF 1 + DFFRE 1 + I_BUF 2 + O_BUF 1 + +4.312. Executing TECHMAP pass (map to technology primitives). + +4.312.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v' to AST representation. +Generating RTLIL representation for module `\$lut'. +Successfully finished Verilog frontend. + +4.312.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.313. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.314. Printing statistics. + +=== clk_buf_primitive_inst === + + Number of wires: 8 + Number of wire bits: 8 + Number of public wires: 6 + Number of public wire bits: 6 + Number of ports: 3 + Number of port bits: 3 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 5 + CLK_BUF 1 + DFFRE 1 + I_BUF 2 + O_BUF 1 + + ***************************** + Rewire_Obuft + ***************************** + +========================== +Post Design clean up ... + +Split to bits ... + +4.315. Executing SPLITNETS pass (splitting up multi-bit signals). + +Split into bits ... [0.00 sec.] +Building Sig2cells ... [0.00 sec.] +Building Sig2sig ... [0.00 sec.] +Backward clean up ... [0.00 sec.] +Before cleanup : + +4.316. Printing statistics. + +=== clk_buf_primitive_inst === + + Number of wires: 8 + Number of wire bits: 8 + Number of public wires: 6 + Number of public wire bits: 6 + Number of ports: 3 + Number of port bits: 3 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 5 + CLK_BUF 1 + DFFRE 1 + I_BUF 2 + O_BUFT 1 + + -------------------------- + Removed assigns : 1 + Removed wires : 1 + Removed cells : 0 + -------------------------- +After cleanup : + +4.317. Printing statistics. + +=== clk_buf_primitive_inst === + + Number of wires: 7 + Number of wire bits: 7 + Number of public wires: 6 + Number of public wire bits: 6 + Number of ports: 3 + Number of port bits: 3 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 5 + CLK_BUF 1 + DFFRE 1 + I_BUF 2 + O_BUFT 1 + + +Total time for 'obs_clean' ... + [0.00 sec.] + +4.318. Executing SPLITNETS pass (splitting up multi-bit signals). + +4.319. Executing HIERARCHY pass (managing design hierarchy). + +4.319.1. Analyzing design hierarchy.. +Top module: \clk_buf_primitive_inst + +4.319.2. Analyzing design hierarchy.. +Top module: \clk_buf_primitive_inst +Removed 0 unused modules. + +Dumping port properties into 'netlist_info.json' file. + +Inserting I_FAB/O_FAB cells ... + + +Inserting I_FAB/O_FAB cells done. + +4.320. Printing statistics. + +=== clk_buf_primitive_inst === + + Number of wires: 8 + Number of wire bits: 8 + Number of public wires: 6 + Number of public wire bits: 6 + Number of ports: 3 + Number of port bits: 3 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 6 + CLK_BUF 1 + DFFRE 1 + I_BUF 2 + O_BUFT 1 + O_FAB 1 + + Number of LUTs: 0 + Number of REGs: 1 + Number of CARRY ADDERs: 0 + +4.321. Executing Verilog backend. +Dumping module `\clk_buf_primitive_inst'. + +# -------------------- +# Core Synthesis done +# -------------------- + +4.322. Executing Verilog backend. +Dumping module `\clk_buf_primitive_inst'. + +4.322.1. Executing BLIF backend. +Extracting primitives + +-- Running command `write_rtlil design.rtlil' -- + +4.322.2. Executing RTLIL backend. +Output filename: design.rtlil +Running SplitNets + +4.322.3. Executing SPLITNETS pass (splitting up multi-bit signals). +Gathering Wires Data +Adding wires between directly connected input and output primitives +Upgrading fabric wires to ports +Handling I_BUF->Fabric->CLK_BUF +Handling Dangling outs +Deleting primitive cells and extra wires +Deleting non-primitive cells and upgrading wires to ports in interface module +Handling I_BUF->Fabric->CLK_BUF in interface module +Removing extra wires from interface module +Cleaning fabric netlist +Removing cells from wrapper module +Instantiating fabric and interface modules +Removing extra wires from wrapper module +Fixing wrapper ports +Flattening wrapper module + +4.322.4. Executing FLATTEN pass (flatten design). +Deleting now unused module interface_clk_buf_primitive_inst. + +Removing extra assigns from wrapper module + +4.322.5. Executing Verilog backend. +Dumping module `\clk_buf_primitive_inst'. + +4.322.5.1. Executing BLIF backend. + +4.322.5.2. Executing Verilog backend. +Dumping module `\clk_buf_primitive_inst'. + +4.322.5.2.1. Executing BLIF backend. +Dumping config.json +Updating sdc + +4.322.5.2.2. Executing Verilog backend. +Dumping module `\fabric_clk_buf_primitive_inst'. + +4.322.5.2.2.1. Executing BLIF backend. + +Warnings: 1 unique messages, 1 total +End of script. Logfile hash: 6e65b550f6, CPU: user 0.42s system 0.05s, MEM: 29.48 MB peak +Yosys 0.44 (git sha1 7a4a3768c, g++ 11.2.1 -fPIC -O3) +Time spent: 32% 43x read_verilog (0 sec), 28% 6x abc (0 sec), ... diff --git a/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/synthesis/clk_pin.xml b/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/synthesis/clk_pin.xml new file mode 100644 index 00000000..dd5d9d1e --- /dev/null +++ b/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/synthesis/clk_pin.xml @@ -0,0 +1,18 @@ + + + + + + + + + + + + + + + + + + diff --git a/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/synthesis/config.json b/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/synthesis/config.json new file mode 100644 index 00000000..7796a901 --- /dev/null +++ b/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/synthesis/config.json @@ -0,0 +1,64 @@ +{ + "instances": [ + { + "connectivity": { + "I": "wire2", + "O": "wire1" + }, + "direction": "IN", + "index": 1, + "linked_object": "clock_input", + "module": "CLK_BUF", + "name": "$auto_420.clk_buf_inst" + }, + { + "connectivity": { + "EN": "$auto_416", + "I": "clock_input", + "O": "wire2" + }, + "direction": "IN", + "index": 0, + "linked_object": "clock_input", + "module": "I_BUF", + "name": "$flatten$auto_420.$ibuf$clk_buf_primitive_inst.$ibuf_clock_input" + }, + { + "connectivity": { + "EN": "$auto_417", + "I": "ibuf_enable", + "O": "$ibuf_ibuf_enable" + }, + "direction": "IN", + "index": 0, + "linked_object": "ibuf_enable", + "module": "I_BUF", + "name": "$flatten$auto_420.$ibuf$clk_buf_primitive_inst.$ibuf_ibuf_enable" + }, + { + "connectivity": { + "I": "$f2g_tx_out_wire_out_clk", + "O": "clock_output", + "T": "$auto_418" + }, + "direction": "OUT", + "index": 0, + "linked_object": "clock_output", + "module": "O_BUFT", + "name": "$flatten$auto_420.$obuf$clk_buf_primitive_inst.$obuf_clock_output" + }, + { + "connectivity": { + "$auto_416": "$auto_416", + "$auto_417": "$auto_417", + "$auto_418": "$auto_418", + "$f2g_tx_out_wire_out_clk": "$f2g_tx_out_wire_out_clk", + "$ibuf_ibuf_enable": "$ibuf_ibuf_enable", + "wire1": "wire1", + "wire2": "wire2" + }, + "module": "fabric_clk_buf_primitive_inst", + "name": "fabric_instance" + } + ] +} diff --git a/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/synthesis/core_synthesis.v b/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/synthesis/core_synthesis.v new file mode 100644 index 00000000..ddec1a6f --- /dev/null +++ b/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/synthesis/core_synthesis.v @@ -0,0 +1,49 @@ +/* Generated by Yosys 0.44 (git sha1 7a4a3768c, g++ 11.2.1 -fPIC -O3) */ + +module clk_buf_primitive_inst(clock_input, ibuf_enable, clock_output); + input clock_input; + output clock_output; + input ibuf_enable; + wire _0_; + wire _1_; + wire clock_input; + wire clock_output; + wire ibuf_enable; + wire wire1; + wire wire2; + wire wire_out_clk; + DFFRE _2_ ( + .C(wire1), + .D(wire2), + .E(1'b1), + .Q(wire_out_clk), + .R(1'b1) + ); + O_FAB _3_ ( + .I(wire_out_clk), + .O(_0_) + ); + I_BUF #( + .WEAK_KEEPER("NONE") + ) _4_ ( + .EN(1'b1), + .I(clock_input), + .O(wire2) + ); + I_BUF #( + .WEAK_KEEPER("NONE") + ) _5_ ( + .EN(1'b1), + .I(ibuf_enable), + .O(_1_) + ); + O_BUFT _6_ ( + .I(_0_), + .O(clock_output), + .T(1'b1) + ); + CLK_BUF clk_buf_inst ( + .I(wire2), + .O(wire1) + ); +endmodule diff --git a/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/synthesis/design.rtlil b/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/synthesis/design.rtlil new file mode 100644 index 00000000..cd3cc187 --- /dev/null +++ b/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/synthesis/design.rtlil @@ -0,0 +1,1932 @@ +# Generated by Yosys 0.44 (git sha1 7a4a3768c, g++ 11.2.1 -fPIC -O3) +autoidx 416 +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:9.1-14.10" +module \BOOT_CLOCK + parameter \PERIOD 25 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:12.14-12.15" + wire output 1 \O +end +attribute \dynports 1 +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:542.1-951.10" +module \BRAM2x18_SDP + parameter \CFG_ABITS 11 + parameter \CFG_DBITS 18 + parameter \CFG_ENABLE_B 2 + parameter \CFG_ENABLE_D 2 + parameter \CLKPOL2 1 + parameter \CLKPOL3 1 + parameter \INIT0 18432'x + parameter \INIT1 18432'x + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:563.27-563.33" + wire width 11 input 1 \A1ADDR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:564.28-564.34" + wire width 18 output 2 \A1DATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:565.11-565.15" + wire input 3 \A1EN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:567.27-567.33" + wire width 11 input 4 \B1ADDR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:570.30-570.34" + wire width 2 input 7 \B1BE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:568.27-568.33" + wire width 18 input 5 \B1DATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:569.11-569.15" + wire input 6 \B1EN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:572.27-572.33" + wire width 11 input 8 \C1ADDR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:573.28-573.34" + wire width 18 output 9 \C1DATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:574.11-574.15" + wire input 10 \C1EN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:560.11-560.15" + wire input 11 \CLK1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:561.11-561.15" + wire input 12 \CLK2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:576.27-576.33" + wire width 11 input 13 \D1ADDR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:579.30-579.34" + wire width 2 input 16 \D1BE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:577.27-577.33" + wire width 18 input 14 \D1DATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:578.11-578.15" + wire input 15 \D1EN +end +attribute \dynports 1 +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:112.1-540.10" +module \BRAM2x18_TDP + parameter \CFG_ABITS 11 + parameter \CFG_DBITS 18 + parameter \CFG_ENABLE_B 2 + parameter \CFG_ENABLE_D 2 + parameter \CFG_ENABLE_F 2 + parameter \CFG_ENABLE_H 2 + parameter \CLKPOL2 1 + parameter \CLKPOL3 1 + parameter \INIT0 18432'x + parameter \INIT1 18432'x + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:137.27-137.33" + wire width 11 input 1 \A1ADDR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:138.28-138.34" + wire width 18 output 2 \A1DATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:139.11-139.15" + wire input 3 \A1EN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:141.27-141.33" + wire width 11 input 4 \B1ADDR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:144.30-144.34" + wire width 2 input 7 \B1BE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:142.27-142.33" + wire width 18 input 5 \B1DATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:143.11-143.15" + wire input 6 \B1EN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:146.27-146.33" + wire width 11 input 8 \C1ADDR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:147.28-147.34" + wire width 18 output 9 \C1DATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:148.11-148.15" + wire input 10 \C1EN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:132.11-132.15" + wire input 11 \CLK1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:133.11-133.15" + wire input 12 \CLK2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:134.11-134.15" + wire input 13 \CLK3 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:135.11-135.15" + wire input 14 \CLK4 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:150.27-150.33" + wire width 11 input 15 \D1ADDR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:153.30-153.34" + wire width 2 input 18 \D1BE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:151.27-151.33" + wire width 18 input 16 \D1DATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:152.11-152.15" + wire input 17 \D1EN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:155.27-155.33" + wire width 11 input 19 \E1ADDR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:156.28-156.34" + wire width 18 output 20 \E1DATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:157.11-157.15" + wire input 21 \E1EN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:159.27-159.33" + wire width 11 input 22 \F1ADDR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:162.30-162.34" + wire width 2 input 25 \F1BE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:160.27-160.33" + wire width 18 input 23 \F1DATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:161.11-161.15" + wire input 24 \F1EN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:164.27-164.33" + wire width 11 input 26 \G1ADDR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:165.28-165.34" + wire width 18 output 27 \G1DATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:166.11-166.15" + wire input 28 \G1EN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:168.27-168.33" + wire width 11 input 29 \H1ADDR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:171.30-171.34" + wire width 2 input 32 \H1BE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:169.27-169.33" + wire width 18 input 30 \H1DATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:170.11-170.15" + wire input 31 \H1EN +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:24.1-31.10" +module \CARRY + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:27.15-27.18" + wire input 3 \CIN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:29.16-29.20" + wire output 5 \COUT + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:26.15-26.16" + wire input 2 \G + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:28.16-28.17" + wire output 4 \O + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:25.15-25.16" + wire input 1 \P +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:41.1-46.10" +module \CLK_BUF + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:42.15-42.16" + wire input 1 \I + attribute \clkbuf_driver 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:44.16-44.17" + wire output 2 \O +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:56.1-64.10" +module \DFFNRE + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:61.15-61.16" + wire input 4 \C + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:57.15-57.16" + wire input 1 \D + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:59.15-59.16" + wire input 3 \E + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:62.14-62.15" + wire output 5 \Q + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:58.15-58.16" + wire input 2 \R +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:74.1-82.10" +module \DFFRE + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:79.15-79.16" + wire input 4 \C + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:75.15-75.16" + wire input 1 \D + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:77.15-77.16" + wire input 3 \E + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:80.14-80.15" + wire output 5 \Q + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:76.15-76.16" + wire input 2 \R +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:92.1-118.10" +module \DLY_SEL_DCODER + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:97.20-97.30" + wire width 3 output 5 \DLY0_CNTRL + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:107.20-107.31" + wire width 3 output 15 \DLY10_CNTRL + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:108.20-108.31" + wire width 3 output 16 \DLY11_CNTRL + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:109.20-109.31" + wire width 3 output 17 \DLY12_CNTRL + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:110.20-110.31" + wire width 3 output 18 \DLY13_CNTRL + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:111.20-111.31" + wire width 3 output 19 \DLY14_CNTRL + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:112.20-112.31" + wire width 3 output 20 \DLY15_CNTRL + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:113.20-113.31" + wire width 3 output 21 \DLY16_CNTRL + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:114.20-114.31" + wire width 3 output 22 \DLY17_CNTRL + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:115.20-115.31" + wire width 3 output 23 \DLY18_CNTRL + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:116.20-116.31" + wire width 3 output 24 \DLY19_CNTRL + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:98.20-98.30" + wire width 3 output 6 \DLY1_CNTRL + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:99.20-99.30" + wire width 3 output 7 \DLY2_CNTRL + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:100.20-100.30" + wire width 3 output 8 \DLY3_CNTRL + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:101.20-101.30" + wire width 3 output 9 \DLY4_CNTRL + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:102.20-102.30" + wire width 3 output 10 \DLY5_CNTRL + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:103.20-103.30" + wire width 3 output 11 \DLY6_CNTRL + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:104.20-104.30" + wire width 3 output 12 \DLY7_CNTRL + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:105.20-105.30" + wire width 3 output 13 \DLY8_CNTRL + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:106.20-106.30" + wire width 3 output 14 \DLY9_CNTRL + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:96.21-96.29" + wire width 5 input 4 \DLY_ADDR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:94.15-94.22" + wire input 2 \DLY_ADJ + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:95.15-95.25" + wire input 3 \DLY_INCDEC + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:93.15-93.23" + wire input 1 \DLY_LOAD +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:128.1-154.10" +module \DLY_SEL_DECODER + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:133.20-133.30" + wire width 3 output 5 \DLY0_CNTRL + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:143.20-143.31" + wire width 3 output 15 \DLY10_CNTRL + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:144.20-144.31" + wire width 3 output 16 \DLY11_CNTRL + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:145.20-145.31" + wire width 3 output 17 \DLY12_CNTRL + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:146.20-146.31" + wire width 3 output 18 \DLY13_CNTRL + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:147.20-147.31" + wire width 3 output 19 \DLY14_CNTRL + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:148.20-148.31" + wire width 3 output 20 \DLY15_CNTRL + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:149.20-149.31" + wire width 3 output 21 \DLY16_CNTRL + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:150.20-150.31" + wire width 3 output 22 \DLY17_CNTRL + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:151.20-151.31" + wire width 3 output 23 \DLY18_CNTRL + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:152.20-152.31" + wire width 3 output 24 \DLY19_CNTRL + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:134.20-134.30" + wire width 3 output 6 \DLY1_CNTRL + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:135.20-135.30" + wire width 3 output 7 \DLY2_CNTRL + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:136.20-136.30" + wire width 3 output 8 \DLY3_CNTRL + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:137.20-137.30" + wire width 3 output 9 \DLY4_CNTRL + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:138.20-138.30" + wire width 3 output 10 \DLY5_CNTRL + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:139.20-139.30" + wire width 3 output 11 \DLY6_CNTRL + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:140.20-140.30" + wire width 3 output 12 \DLY7_CNTRL + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:141.20-141.30" + wire width 3 output 13 \DLY8_CNTRL + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:142.20-142.30" + wire width 3 output 14 \DLY9_CNTRL + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:132.21-132.29" + wire width 5 input 4 \DLY_ADDR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:130.15-130.22" + wire input 2 \DLY_ADJ + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:131.15-131.25" + wire input 3 \DLY_INCDEC + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:129.15-129.23" + wire input 1 \DLY_LOAD +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:164.1-188.10" +module \DLY_VALUE_MUX + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:185.21-185.29" + wire width 5 input 21 \DLY_ADDR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:165.21-165.33" + wire width 6 input 1 \DLY_TAP0_VAL + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:175.21-175.34" + wire width 6 input 11 \DLY_TAP10_VAL + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:176.21-176.34" + wire width 6 input 12 \DLY_TAP11_VAL + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:177.21-177.34" + wire width 6 input 13 \DLY_TAP12_VAL + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:178.21-178.34" + wire width 6 input 14 \DLY_TAP13_VAL + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:179.21-179.34" + wire width 6 input 15 \DLY_TAP14_VAL + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:180.21-180.34" + wire width 6 input 16 \DLY_TAP15_VAL + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:181.21-181.34" + wire width 6 input 17 \DLY_TAP16_VAL + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:182.21-182.34" + wire width 6 input 18 \DLY_TAP17_VAL + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:183.21-183.34" + wire width 6 input 19 \DLY_TAP18_VAL + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:184.21-184.34" + wire width 6 input 20 \DLY_TAP19_VAL + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:166.21-166.33" + wire width 6 input 2 \DLY_TAP1_VAL + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:167.21-167.33" + wire width 6 input 3 \DLY_TAP2_VAL + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:168.21-168.33" + wire width 6 input 4 \DLY_TAP3_VAL + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:169.21-169.33" + wire width 6 input 5 \DLY_TAP4_VAL + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:170.21-170.33" + wire width 6 input 6 \DLY_TAP5_VAL + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:171.21-171.33" + wire width 6 input 7 \DLY_TAP6_VAL + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:172.21-172.33" + wire width 6 input 8 \DLY_TAP7_VAL + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:173.21-173.33" + wire width 6 input 9 \DLY_TAP8_VAL + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:174.21-174.33" + wire width 6 input 10 \DLY_TAP9_VAL + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:186.20-186.33" + wire width 6 output 22 \DLY_TAP_VALUE +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:198.1-232.10" +module \DSP19X2 + parameter \DSP_MODE "MULTIPLY_ACCUMULATE" + parameter \COEFF1_0 10'0000000000 + parameter \COEFF1_1 10'0000000000 + parameter \COEFF1_2 10'0000000000 + parameter \COEFF1_3 10'0000000000 + parameter \COEFF2_0 10'0000000000 + parameter \COEFF2_1 10'0000000000 + parameter \COEFF2_2 10'0000000000 + parameter \COEFF2_3 10'0000000000 + parameter \OUTPUT_REG_EN "TRUE" + parameter \INPUT_REG_EN "TRUE" + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:211.21-211.23" + wire width 10 input 1 \A1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:215.21-215.23" + wire width 10 input 5 \A2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:222.21-222.28" + wire width 5 input 11 \ACC_FIR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:212.21-212.23" + wire width 9 input 2 \B1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:216.21-216.23" + wire width 9 input 6 \B2 + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:220.15-220.18" + wire input 9 \CLK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:214.22-214.28" + wire width 9 output 4 \DLY_B1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:218.22-218.28" + wire width 9 output 8 \DLY_B2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:223.21-223.29" + wire width 3 input 12 \FEEDBACK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:224.15-224.23" + wire input 13 \LOAD_ACC + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:221.15-221.20" + wire input 10 \RESET + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:229.15-229.20" + wire input 18 \ROUND + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:227.15-227.23" + wire input 16 \SATURATE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:228.21-228.32" + wire width 5 input 17 \SHIFT_RIGHT + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:230.15-230.23" + wire input 19 \SUBTRACT + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:225.15-225.25" + wire input 14 \UNSIGNED_A + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:226.15-226.25" + wire input 15 \UNSIGNED_B + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:213.23-213.25" + wire width 19 output 3 \Z1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:217.23-217.25" + wire width 19 output 7 \Z2 +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:242.1-268.10" +module \DSP38 + parameter \DSP_MODE "MULTIPLY_ACCUMULATE" + parameter \COEFF_0 20'00000000000000000000 + parameter \COEFF_1 20'00000000000000000000 + parameter \COEFF_2 20'00000000000000000000 + parameter \COEFF_3 20'00000000000000000000 + parameter \OUTPUT_REG_EN "TRUE" + parameter \INPUT_REG_EN "TRUE" + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:251.22-251.23" + wire width 20 input 1 \A + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:253.21-253.28" + wire width 6 input 3 \ACC_FIR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:252.22-252.23" + wire width 18 input 2 \B + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:257.15-257.18" + wire input 6 \CLK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:255.21-255.26" + wire width 18 output 5 \DLY_B + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:259.21-259.29" + wire width 3 input 8 \FEEDBACK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:260.15-260.23" + wire input 9 \LOAD_ACC + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:258.15-258.20" + wire input 7 \RESET + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:263.15-263.20" + wire input 12 \ROUND + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:261.15-261.23" + wire input 10 \SATURATE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:262.21-262.32" + wire width 6 input 11 \SHIFT_RIGHT + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:264.15-264.23" + wire input 13 \SUBTRACT + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:265.15-265.25" + wire input 14 \UNSIGNED_A + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:266.15-266.25" + wire input 15 \UNSIGNED_B + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:254.23-254.24" + wire width 38 output 4 \Z +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:278.1-282.10" +module \FCLK_BUF + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:279.15-279.16" + wire input 1 \I + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:280.16-280.17" + wire output 2 \O +end +attribute \dynports 1 +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:292.1-339.10" +module \FIFO18KX2 + parameter \DATA_WRITE_WIDTH1 18 + parameter \DATA_READ_WIDTH1 18 + parameter \FIFO_TYPE1 "SYNCHRONOUS" + parameter \PROG_EMPTY_THRESH1 11'00000000100 + parameter \PROG_FULL_THRESH1 11'11111111010 + parameter \DATA_WRITE_WIDTH2 18 + parameter \DATA_READ_WIDTH2 18 + parameter \FIFO_TYPE2 "SYNCHRONOUS" + parameter \PROG_EMPTY_THRESH2 11'00000000100 + parameter \PROG_FULL_THRESH2 11'11111111010 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:315.14-315.27" + wire output 10 \ALMOST_EMPTY1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:332.14-332.27" + wire output 25 \ALMOST_EMPTY2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:316.14-316.26" + wire output 11 \ALMOST_FULL1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:333.14-333.26" + wire output 26 \ALMOST_FULL2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:313.14-313.20" + wire output 8 \EMPTY1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:330.14-330.20" + wire output 23 \EMPTY2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:314.14-314.19" + wire output 9 \FULL1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:331.14-331.19" + wire output 24 \FULL2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:319.14-319.23" + wire output 14 \OVERFLOW1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:336.14-336.23" + wire output 29 \OVERFLOW2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:317.14-317.25" + wire output 12 \PROG_EMPTY1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:334.14-334.25" + wire output 27 \PROG_EMPTY2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:318.14-318.24" + wire output 13 \PROG_FULL1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:335.14-335.24" + wire output 28 \PROG_FULL2 + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:308.15-308.22" + wire input 3 \RD_CLK1 + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:325.15-325.22" + wire input 18 \RD_CLK2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:312.39-312.47" + wire width 18 output 7 \RD_DATA1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:329.39-329.47" + wire width 18 output 22 \RD_DATA2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:310.15-310.21" + wire input 5 \RD_EN1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:327.15-327.21" + wire input 20 \RD_EN2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:304.15-304.21" + wire input 1 \RESET1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:321.15-321.21" + wire input 16 \RESET2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:320.14-320.24" + wire output 15 \UNDERFLOW1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:337.14-337.24" + wire output 30 \UNDERFLOW2 + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:306.15-306.22" + wire input 2 \WR_CLK1 + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:323.15-323.22" + wire input 17 \WR_CLK2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:311.39-311.47" + wire width 18 input 6 \WR_DATA1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:328.39-328.47" + wire width 18 input 21 \WR_DATA2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:309.15-309.21" + wire input 4 \WR_EN1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:326.15-326.21" + wire input 19 \WR_EN2 +end +attribute \dynports 1 +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:349.1-374.10" +module \FIFO36K + parameter \DATA_WRITE_WIDTH 36 + parameter \DATA_READ_WIDTH 36 + parameter \FIFO_TYPE "SYNCHRONOUS" + parameter \PROG_EMPTY_THRESH 12'000000000100 + parameter \PROG_FULL_THRESH 12'111111111010 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:367.14-367.26" + wire output 10 \ALMOST_EMPTY + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:368.14-368.25" + wire output 11 \ALMOST_FULL + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:365.14-365.19" + wire output 8 \EMPTY + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:366.14-366.18" + wire output 9 \FULL + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:371.14-371.22" + wire output 14 \OVERFLOW + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:369.14-369.24" + wire output 12 \PROG_EMPTY + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:370.14-370.23" + wire output 13 \PROG_FULL + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:360.15-360.21" + wire input 3 \RD_CLK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:364.38-364.45" + wire width 36 output 7 \RD_DATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:362.15-362.20" + wire input 5 \RD_EN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:356.15-356.20" + wire input 1 \RESET + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:372.14-372.23" + wire output 15 \UNDERFLOW + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:358.15-358.21" + wire input 2 \WR_CLK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:363.38-363.45" + wire width 36 input 6 \WR_DATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:361.15-361.20" + wire input 4 \WR_EN +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:406.1-415.10" +module \I_BUF + parameter \WEAK_KEEPER "NONE" + parameter \IOSTANDARD "DEFAULT" + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:412.15-412.17" + wire input 2 \EN + attribute \iopad_external_pin 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:411.15-411.16" + wire input 1 \I + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:413.16-413.17" + wire output 3 \O +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:384.1-396.10" +module \I_BUF_DS + parameter \WEAK_KEEPER "NONE" + parameter \IOSTANDARD "DEFAULT" + parameter \DIFFERENTIAL_TERMINATION "TRUE" + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:393.15-393.17" + wire input 3 \EN + attribute \iopad_external_pin 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:392.15-392.18" + wire input 2 \I_N + attribute \iopad_external_pin 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:390.15-390.18" + wire input 1 \I_P + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:394.14-394.15" + wire output 4 \O +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:425.1-433.10" +module \I_DDR + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:430.15-430.16" + wire input 4 \C + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:426.15-426.16" + wire input 1 \D + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:428.15-428.16" + wire input 3 \E + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:431.20-431.21" + wire width 2 output 5 \Q + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:427.15-427.16" + wire input 2 \R +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:443.1-455.10" +module \I_DELAY + parameter \DELAY 0 + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:452.15-452.21" + wire input 6 \CLK_IN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:448.15-448.22" + wire input 3 \DLY_ADJ + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:449.15-449.25" + wire input 4 \DLY_INCDEC + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:447.15-447.23" + wire input 2 \DLY_LOAD + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:450.22-450.35" + wire width 6 output 5 \DLY_TAP_VALUE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:446.15-446.16" + wire input 1 \I + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:453.16-453.17" + wire output 7 \O +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:465.1-469.10" +module \I_FAB + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:466.15-466.16" + wire input 1 \I + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:467.16-467.17" + wire output 2 \O +end +attribute \dynports 1 +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:479.1-498.10" +module \I_SERDES + parameter \DATA_RATE "SDR" + parameter \WIDTH 4 + parameter \DPA_MODE "NONE" + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:486.15-486.26" + wire input 3 \BITSLIP_ADJ + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:489.15-489.21" + wire input 5 \CLK_IN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:490.16-490.23" + wire output 6 \CLK_OUT + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:484.15-484.16" + wire input 1 \D + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:492.16-492.26" + wire output 8 \DATA_VALID + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:494.16-494.25" + wire output 10 \DPA_ERROR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:493.16-493.24" + wire output 9 \DPA_LOCK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:487.15-487.17" + wire input 4 \EN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:496.15-496.22" + wire input 12 \PLL_CLK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:495.15-495.23" + wire input 11 \PLL_LOCK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:491.28-491.29" + wire width 4 output 7 \Q + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:485.15-485.18" + wire input 2 \RST +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:587.1-592.10" +module \LATCH + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:588.15-588.16" + wire input 1 \D + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:589.15-589.16" + wire input 2 \G + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:590.16-590.17" + wire output 3 \Q +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:540.1-545.10" +module \LATCHN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:541.15-541.16" + wire input 1 \D + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:542.15-542.16" + wire input 2 \G + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:543.16-543.17" + wire output 3 \Q +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:508.1-514.10" +module \LATCHNR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:509.15-509.16" + wire input 1 \D + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:510.15-510.16" + wire input 2 \G + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:512.16-512.17" + wire output 4 \Q + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:511.15-511.16" + wire input 3 \R +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:524.1-530.10" +module \LATCHNS + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:525.15-525.16" + wire input 1 \D + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:526.15-526.16" + wire input 2 \G + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:528.16-528.17" + wire output 4 \Q + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:527.15-527.16" + wire input 3 \R +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:265.1-285.10" +module \LATCHNSRE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:266.9-266.10" + wire input 4 \D + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:267.9-267.10" + wire input 6 \E + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:268.9-268.10" + wire input 5 \G + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:269.10-269.11" + wire output 1 \Q + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:270.9-270.10" + wire input 3 \R + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:271.9-271.10" + wire input 2 \S +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:555.1-561.10" +module \LATCHR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:556.15-556.16" + wire input 1 \D + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:557.15-557.16" + wire input 2 \G + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:559.16-559.17" + wire output 4 \Q + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:558.15-558.16" + wire input 3 \R +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:571.1-577.10" +module \LATCHS + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:572.15-572.16" + wire input 1 \D + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:573.15-573.16" + wire input 2 \G + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:575.16-575.17" + wire output 4 \Q + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:574.15-574.16" + wire input 3 \R +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:223.1-243.10" +module \LATCHSRE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:224.9-224.10" + wire input 4 \D + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:225.9-225.10" + wire input 6 \E + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:226.9-226.10" + wire input 5 \G + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:227.10-227.11" + wire output 1 \Q + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:228.9-228.10" + wire input 3 \R + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:229.9-229.10" + wire input 2 \S +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:602.1-608.10" +module \LUT1 + parameter \INIT_VALUE 2'00 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:605.15-605.16" + wire input 1 \A + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:606.16-606.17" + wire output 2 \Y +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:618.1-624.10" +module \LUT2 + parameter \INIT_VALUE 4'0000 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:621.21-621.22" + wire width 2 input 1 \A + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:622.16-622.17" + wire output 2 \Y +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:634.1-640.10" +module \LUT3 + parameter \INIT_VALUE 8'00000000 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:637.21-637.22" + wire width 3 input 1 \A + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:638.16-638.17" + wire output 2 \Y +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:650.1-656.10" +module \LUT4 + parameter \INIT_VALUE 16'0000000000000000 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:653.21-653.22" + wire width 4 input 1 \A + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:654.16-654.17" + wire output 2 \Y +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:666.1-672.10" +module \LUT5 + parameter \INIT_VALUE 0 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:669.21-669.22" + wire width 5 input 1 \A + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:670.16-670.17" + wire output 2 \Y +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:682.1-688.10" +module \LUT6 + parameter \INIT_VALUE 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:685.21-685.22" + wire width 6 input 1 \A + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:686.16-686.17" + wire output 2 \Y +end +attribute \dynports 1 +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:698.1-724.10" +module \MIPI_RX + parameter \WIDTH 4 + parameter \EN_IDLY "FALSE" + parameter \DELAY 0 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:713.15-713.26" + wire input 10 \BITSLIP_ADJ + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:707.15-707.21" + wire input 4 \CLK_IN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:715.15-715.22" + wire input 12 \DLY_ADJ + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:716.15-716.25" + wire input 13 \DLY_INCDEC + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:714.15-714.23" + wire input 11 \DLY_LOAD + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:717.22-717.35" + wire width 6 output 14 \DLY_TAP_VALUE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:710.15-710.20" + wire input 7 \HS_EN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:719.16-719.28" + wire output 16 \HS_RXD_VALID + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:718.28-718.38" + wire width 4 output 15 \HS_RX_DATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:711.15-711.20" + wire input 8 \LP_EN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:722.16-722.24" + wire output 19 \LP_RX_DN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:721.16-721.24" + wire output 18 \LP_RX_DP + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:705.15-705.23" + wire input 3 \PLL_LOCK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:703.15-703.18" + wire input 1 \RST + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:704.15-704.21" + wire input 2 \RX_CLK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:709.15-709.20" + wire input 6 \RX_DN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:708.15-708.20" + wire input 5 \RX_DP + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:720.16-720.21" + wire output 17 \RX_OE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:712.15-712.25" + wire input 9 \RX_TERM_EN +end +attribute \dynports 1 +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:734.1-761.10" +module \MIPI_TX + parameter \WIDTH 4 + parameter \EN_ODLY "FALSE" + parameter \LANE_MODE "Master" + parameter \DELAY 0 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:758.15-758.35" + wire input 18 \CHANNEL_BOND_SYNC_IN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:759.16-759.37" + wire output 19 \CHANNEL_BOND_SYNC_OUT + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:744.15-744.21" + wire input 4 \CLK_IN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:753.15-753.22" + wire input 13 \DLY_ADJ + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:754.15-754.25" + wire input 14 \DLY_INCDEC + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:752.15-752.23" + wire input 12 \DLY_LOAD + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:747.15-747.20" + wire input 7 \HS_EN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:746.15-746.27" + wire input 6 \HS_TXD_VALID + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:745.27-745.37" + wire width 4 input 5 \HS_TX_DATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:750.15-750.20" + wire input 10 \LP_EN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:742.15-742.23" + wire input 3 \PLL_LOCK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:740.15-740.18" + wire input 1 \RST + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:741.15-741.21" + wire input 2 \RX_CLK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:757.16-757.21" + wire output 17 \TX_DN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:756.16-756.21" + wire output 16 \TX_DP + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:749.15-749.23" + wire input 9 \TX_LP_DN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:748.15-748.23" + wire input 8 \TX_LP_DP + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:751.15-751.24" + wire input 11 \TX_ODT_EN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:755.16-755.21" + wire output 15 \TX_OE +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:836.1-847.10" +module \O_BUF + parameter \IOSTANDARD "DEFAULT" + parameter \DRIVE_STRENGTH 2 + parameter \SLEW_RATE "SLOW" + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:843.15-843.16" + wire input 1 \I + attribute \iopad_external_pin 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:845.16-845.17" + wire output 2 \O +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:815.1-826.10" +module \O_BUFT + parameter \WEAK_KEEPER "NONE" + parameter \IOSTANDARD "DEFAULT" + parameter \DRIVE_STRENGTH 2 + parameter \SLEW_RATE "SLOW" + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:821.15-821.16" + wire input 1 \I + attribute \iopad_external_pin 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:824.16-824.17" + wire output 3 \O + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:822.15-822.16" + wire input 2 \T +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:793.1-805.10" +module \O_BUFT_DS + parameter \WEAK_KEEPER "NONE" + parameter \IOSTANDARD "DEFAULT" + parameter \DIFFERENTIAL_TERMINATION "TRUE" + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:798.15-798.16" + wire input 1 \I + attribute \iopad_external_pin 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:803.16-803.19" + wire output 4 \O_N + attribute \iopad_external_pin 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:801.16-801.19" + wire output 3 \O_P + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:799.15-799.16" + wire input 2 \T +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:771.1-783.10" +module \O_BUF_DS + parameter \IOSTANDARD "DEFAULT" + parameter \DIFFERENTIAL_TERMINATION "TRUE" + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:777.15-777.16" + wire input 1 \I + attribute \iopad_external_pin 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:781.16-781.19" + wire output 3 \O_N + attribute \iopad_external_pin 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:779.16-779.19" + wire output 2 \O_P +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:857.1-865.10" +module \O_DDR + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:862.15-862.16" + wire input 4 \C + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:858.21-858.22" + wire width 2 input 1 \D + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:860.15-860.16" + wire input 3 \E + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:863.14-863.15" + wire output 5 \Q + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:859.15-859.16" + wire input 2 \R +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:875.1-887.10" +module \O_DELAY + parameter \DELAY 0 + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:884.15-884.21" + wire input 6 \CLK_IN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:880.15-880.22" + wire input 3 \DLY_ADJ + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:881.15-881.25" + wire input 4 \DLY_INCDEC + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:879.15-879.23" + wire input 2 \DLY_LOAD + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:882.22-882.35" + wire width 6 output 5 \DLY_TAP_VALUE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:878.15-878.16" + wire input 1 \I + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:885.16-885.17" + wire output 7 \O +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:897.1-901.10" +module \O_FAB + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:898.15-898.16" + wire input 1 \I + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:899.16-899.17" + wire output 2 \O +end +attribute \dynports 1 +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:930.1-947.10" +module \O_SERDES + parameter \DATA_RATE "SDR" + parameter \WIDTH 4 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:942.15-942.35" + wire input 8 \CHANNEL_BOND_SYNC_IN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:943.16-943.37" + wire output 9 \CHANNEL_BOND_SYNC_OUT + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:938.15-938.21" + wire input 4 \CLK_IN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:934.27-934.28" + wire width 4 input 1 \D + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:936.15-936.25" + wire input 3 \DATA_VALID + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:939.15-939.20" + wire input 5 \OE_IN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:940.16-940.22" + wire output 6 \OE_OUT + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:945.15-945.22" + wire input 11 \PLL_CLK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:944.15-944.23" + wire input 10 \PLL_LOCK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:941.16-941.17" + wire output 7 \Q + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:935.15-935.18" + wire input 2 \RST +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:911.1-920.10" +module \O_SERDES_CLK + parameter \DATA_RATE "SDR" + parameter \CLOCK_PHASE 0 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:915.15-915.21" + wire input 1 \CLK_EN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:916.14-916.24" + wire output 2 \OUTPUT_CLK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:918.15-918.22" + wire input 4 \PLL_CLK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:917.15-917.23" + wire input 3 \PLL_LOCK +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:957.1-975.10" +module \PLL + parameter \DEV_FAMILY "VIRGO" + parameter \DIVIDE_CLK_IN_BY_2 "FALSE" + parameter \PLL_MULT 16 + parameter \PLL_DIV 1 + parameter \PLL_MULT_FRAC 0 + parameter \PLL_POST_DIV 17 + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:967.15-967.21" + wire input 2 \CLK_IN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:968.16-968.23" + wire output 3 \CLK_OUT + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:969.16-969.28" + wire output 4 \CLK_OUT_DIV2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:970.16-970.28" + wire output 5 \CLK_OUT_DIV3 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:971.16-971.28" + wire output 6 \CLK_OUT_DIV4 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:972.16-972.24" + wire output 7 \FAST_CLK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:973.16-973.20" + wire output 8 \LOCK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:965.15-965.21" + wire input 1 \PLL_EN +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v:89.1-111.10" +module \RS_DSP3 + parameter \MODE_BITS 93'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \DSP_CLK "" + parameter \DSP_RST "" + parameter \DSP_RST_POL "" + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v:90.24-90.25" + wire width 20 input 1 \a + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v:92.24-92.31" + wire width 6 input 3 \acc_fir + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v:91.24-91.25" + wire width 18 input 2 \b + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v:97.23-97.26" + wire input 6 \clk + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v:94.24-94.29" + wire width 18 output 5 \dly_b + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v:100.23-100.31" + wire width 3 input 8 \feedback + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v:101.23-101.31" + wire input 9 \load_acc + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v:98.23-98.28" + wire input 7 \reset + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v:104.23-104.31" + wire input 12 \subtract + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v:102.23-102.33" + wire input 10 \unsigned_a + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v:103.23-103.33" + wire input 11 \unsigned_b + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v:93.24-93.25" + wire width 38 output 4 \z +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:985.1-999.10" +module \SOC_FPGA_INTF_AHB_M + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:987.22-987.27" + wire width 32 input 2 \HADDR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:988.21-988.27" + wire width 3 input 3 \HBURST + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:997.15-997.19" + wire input 12 \HCLK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:989.21-989.26" + wire width 4 input 4 \HPROT + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:994.23-994.29" + wire width 32 output 9 \HRDATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:995.16-995.22" + wire output 10 \HREADY + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:986.15-986.24" + wire input 1 \HRESETN_I + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:996.16-996.21" + wire output 11 \HRESP + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:990.21-990.26" + wire width 3 input 5 \HSIZE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:991.21-991.27" + wire width 3 input 6 \HTRANS + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:992.22-992.28" + wire width 32 input 7 \HWDATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:993.15-993.22" + wire input 8 \HWWRITE +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1009.1-1026.10" +module \SOC_FPGA_INTF_AHB_S + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1011.23-1011.28" + wire width 32 output 2 \HADDR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1012.22-1012.28" + wire width 3 output 3 \HBURST + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1024.15-1024.19" + wire input 15 \HCLK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1013.16-1013.25" + wire output 4 \HMASTLOCK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1015.22-1015.27" + wire width 4 output 6 \HPROT + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1016.22-1016.28" + wire width 32 input 7 \HRDATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1014.15-1014.21" + wire input 5 \HREADY + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1010.16-1010.25" + wire output 1 \HRESETN_I + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1017.15-1017.20" + wire input 8 \HRESP + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1018.16-1018.20" + wire output 9 \HSEL + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1019.22-1019.27" + wire width 3 output 10 \HSIZE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1020.22-1020.28" + wire width 2 output 11 \HTRANS + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1021.22-1021.26" + wire width 4 output 12 \HWBE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1022.23-1022.29" + wire width 32 output 13 \HWDATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1023.16-1023.22" + wire output 14 \HWRITE +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1036.1-1075.10" +module \SOC_FPGA_INTF_AXI_M0 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1072.15-1072.22" + wire input 36 \M0_ACLK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1037.22-1037.31" + wire width 32 input 1 \M0_ARADDR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1038.21-1038.31" + wire width 2 input 2 \M0_ARBURST + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1039.21-1039.31" + wire width 4 input 3 \M0_ARCACHE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1073.16-1073.28" + wire output 37 \M0_ARESETN_I + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1040.21-1040.28" + wire width 4 input 4 \M0_ARID + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1041.21-1041.29" + wire width 3 input 5 \M0_ARLEN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1042.15-1042.24" + wire input 6 \M0_ARLOCK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1043.21-1043.30" + wire width 3 input 7 \M0_ARPROT + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1044.16-1044.26" + wire output 8 \M0_ARREADY + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1045.21-1045.30" + wire width 3 input 9 \M0_ARSIZE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1046.15-1046.25" + wire input 10 \M0_ARVALID + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1047.22-1047.31" + wire width 32 input 11 \M0_AWADDR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1048.21-1048.31" + wire width 2 input 12 \M0_AWBURST + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1049.21-1049.31" + wire width 4 input 13 \M0_AWCACHE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1050.21-1050.28" + wire width 4 input 14 \M0_AWID + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1051.21-1051.29" + wire width 3 input 15 \M0_AWLEN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1052.15-1052.24" + wire input 16 \M0_AWLOCK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1053.21-1053.30" + wire width 3 input 17 \M0_AWPROT + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1054.16-1054.26" + wire output 18 \M0_AWREADY + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1055.21-1055.30" + wire width 3 input 19 \M0_AWSIZE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1056.15-1056.25" + wire input 20 \M0_AWVALID + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1057.22-1057.28" + wire width 4 output 21 \M0_BID + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1058.15-1058.24" + wire input 22 \M0_BREADY + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1059.22-1059.30" + wire width 2 output 23 \M0_BRESP + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1060.16-1060.25" + wire output 24 \M0_BVALID + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1061.23-1061.31" + wire width 64 output 25 \M0_RDATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1062.22-1062.28" + wire width 4 output 26 \M0_RID + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1063.16-1063.24" + wire output 27 \M0_RLAST + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1064.15-1064.24" + wire input 28 \M0_RREADY + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1065.22-1065.30" + wire width 2 output 29 \M0_RRESP + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1066.16-1066.25" + wire output 30 \M0_RVALID + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1067.22-1067.30" + wire width 64 input 31 \M0_WDATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1068.15-1068.23" + wire input 32 \M0_WLAST + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1069.16-1069.25" + wire output 33 \M0_WREADY + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1070.21-1070.29" + wire width 8 input 34 \M0_WSTRB + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1071.15-1071.24" + wire input 35 \M0_WVALID +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1085.1-1124.10" +module \SOC_FPGA_INTF_AXI_M1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1121.15-1121.22" + wire input 36 \M1_ACLK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1086.22-1086.31" + wire width 32 input 1 \M1_ARADDR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1087.21-1087.31" + wire width 2 input 2 \M1_ARBURST + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1088.21-1088.31" + wire width 4 input 3 \M1_ARCACHE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1122.16-1122.28" + wire output 37 \M1_ARESETN_I + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1089.21-1089.28" + wire width 4 input 4 \M1_ARID + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1090.21-1090.29" + wire width 3 input 5 \M1_ARLEN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1091.15-1091.24" + wire input 6 \M1_ARLOCK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1092.21-1092.30" + wire width 3 input 7 \M1_ARPROT + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1093.16-1093.26" + wire output 8 \M1_ARREADY + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1094.21-1094.30" + wire width 3 input 9 \M1_ARSIZE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1095.15-1095.25" + wire input 10 \M1_ARVALID + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1096.22-1096.31" + wire width 32 input 11 \M1_AWADDR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1097.21-1097.31" + wire width 2 input 12 \M1_AWBURST + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1098.21-1098.31" + wire width 4 input 13 \M1_AWCACHE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1099.21-1099.28" + wire width 4 input 14 \M1_AWID + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1100.21-1100.29" + wire width 3 input 15 \M1_AWLEN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1101.15-1101.24" + wire input 16 \M1_AWLOCK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1102.21-1102.30" + wire width 3 input 17 \M1_AWPROT + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1103.16-1103.26" + wire output 18 \M1_AWREADY + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1104.21-1104.30" + wire width 3 input 19 \M1_AWSIZE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1105.15-1105.25" + wire input 20 \M1_AWVALID + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1106.22-1106.28" + wire width 4 output 21 \M1_BID + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1107.15-1107.24" + wire input 22 \M1_BREADY + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1108.22-1108.30" + wire width 2 output 23 \M1_BRESP + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1109.16-1109.25" + wire output 24 \M1_BVALID + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1110.23-1110.31" + wire width 64 output 25 \M1_RDATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1111.22-1111.28" + wire width 4 output 26 \M1_RID + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1112.16-1112.24" + wire output 27 \M1_RLAST + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1113.15-1113.24" + wire input 28 \M1_RREADY + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1114.22-1114.30" + wire width 2 output 29 \M1_RRESP + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1115.16-1115.25" + wire output 30 \M1_RVALID + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1116.22-1116.30" + wire width 64 input 31 \M1_WDATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1117.15-1117.23" + wire input 32 \M1_WLAST + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1118.16-1118.25" + wire output 33 \M1_WREADY + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1119.21-1119.29" + wire width 8 input 34 \M1_WSTRB + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1120.15-1120.24" + wire input 35 \M1_WVALID +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1134.1-1140.10" +module \SOC_FPGA_INTF_DMA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1136.22-1136.29" + wire width 4 output 2 \DMA_ACK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1137.15-1137.22" + wire input 3 \DMA_CLK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1135.21-1135.28" + wire width 4 input 1 \DMA_REQ + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1138.15-1138.24" + wire input 4 \DMA_RST_N +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1150.1-1156.10" +module \SOC_FPGA_INTF_IRQ + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1153.15-1153.22" + wire input 3 \IRQ_CLK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1154.15-1154.24" + wire input 4 \IRQ_RST_N + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1152.23-1152.30" + wire width 16 output 2 \IRQ_SET + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1151.22-1151.29" + wire width 16 input 1 \IRQ_SRC +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1166.1-1174.10" +module \SOC_FPGA_INTF_JTAG + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1172.15-1172.27" + wire input 6 \BOOT_JTAG_EN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1167.15-1167.28" + wire input 1 \BOOT_JTAG_TCK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1168.14-1168.27" + wire output 2 \BOOT_JTAG_TDI + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1169.15-1169.28" + wire input 3 \BOOT_JTAG_TDO + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1170.14-1170.27" + wire output 4 \BOOT_JTAG_TMS + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1171.14-1171.29" + wire output 5 \BOOT_JTAG_TRSTN +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1184.1-1192.10" +module \SOC_FPGA_TEMPERATURE + parameter \INITIAL_TEMPERATURE 25 + parameter \TEMPERATURE_FILE "" + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1190.14-1190.19" + wire output 3 \ERROR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1188.20-1188.31" + wire width 8 output 1 \TEMPERATURE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1189.14-1189.19" + wire output 2 \VALID +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:7.1-110.10" +module \TDP_BRAM18 + parameter \INITP_00 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INITP_01 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INITP_02 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INITP_03 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INITP_04 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INITP_05 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INITP_06 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INITP_07 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_00 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_01 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_02 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_03 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_04 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_05 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_06 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_07 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_08 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_09 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_0A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_0B 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_0C 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_0D 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_0E 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_0F 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_10 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_11 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_12 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_13 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_14 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_15 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_16 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_17 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_18 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_19 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_1A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_1B 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_1C 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_1D 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_1E 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_1F 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_20 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_21 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_22 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_23 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_24 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_25 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_26 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_27 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_28 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_29 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_2A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_2B 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_2C 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_2D 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_2E 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_2F 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_30 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_31 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_32 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_33 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_34 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_35 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_36 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_37 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_38 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_39 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_3A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_3B 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_3C 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_3D 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_3E 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_3F 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \READ_WIDTH_A 0 + parameter \READ_WIDTH_B 0 + parameter \WRITE_WIDTH_A 0 + parameter \WRITE_WIDTH_B 0 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:14.23-14.28" + wire width 14 input 5 \ADDRA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:15.23-15.28" + wire width 14 input 6 \ADDRB + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:22.22-22.33" + wire width 2 input 13 \BYTEENABLEA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:23.22-23.33" + wire width 2 input 14 \BYTEENABLEB + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:9.16-9.22" + wire input 1 \CLOCKA + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:11.16-11.22" + wire input 2 \CLOCKB + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:28.24-28.33" + wire width 16 output 15 \READDATAA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:30.23-30.33" + wire width 2 output 17 \READDATAAP + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:29.24-29.33" + wire width 16 output 16 \READDATAB + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:31.23-31.33" + wire width 2 output 18 \READDATABP + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:12.16-12.27" + wire input 3 \READENABLEA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:13.16-13.27" + wire input 4 \READENABLEB + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:16.23-16.33" + wire width 16 input 7 \WRITEDATAA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:18.22-18.33" + wire width 2 input 9 \WRITEDATAAP + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:17.23-17.33" + wire width 16 input 8 \WRITEDATAB + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:19.22-19.33" + wire width 2 input 10 \WRITEDATABP + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:20.16-20.28" + wire input 11 \WRITEENABLEA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:21.16-21.28" + wire input 12 \WRITEENABLEB +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1202.1-1257.10" +module \TDP_RAM18KX2 + parameter \INIT1 16384'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000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0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT1_PARITY 2048'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \WRITE_WIDTH_A1 18 + parameter \WRITE_WIDTH_B1 18 + parameter \READ_WIDTH_A1 18 + parameter \READ_WIDTH_B1 18 + parameter \INIT2 16384'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000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+ parameter \INIT2_PARITY 2048'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \WRITE_WIDTH_A2 18 + parameter \WRITE_WIDTH_B2 18 + parameter \READ_WIDTH_A2 18 + parameter \READ_WIDTH_B2 18 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1226.22-1226.29" + wire width 14 input 9 \ADDR_A1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1246.22-1246.29" + wire width 14 input 27 \ADDR_A2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1227.22-1227.29" + wire width 14 input 10 \ADDR_B1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1247.22-1247.29" + wire width 14 input 28 \ADDR_B2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1224.21-1224.26" + wire width 2 input 7 \BE_A1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1244.21-1244.26" + wire width 2 input 25 \BE_A2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1225.21-1225.26" + wire width 2 input 8 \BE_B1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1245.21-1245.26" + wire width 2 input 26 \BE_B2 + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1221.15-1221.21" + wire input 5 \CLK_A1 + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1241.15-1241.21" + wire input 23 \CLK_A2 + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1223.15-1223.21" + wire input 6 \CLK_B1 + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1243.15-1243.21" + wire input 24 \CLK_B2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1232.21-1232.29" + wire width 16 output 15 \RDATA_A1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1252.21-1252.29" + wire width 16 output 33 \RDATA_A2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1234.21-1234.29" + wire width 16 output 17 \RDATA_B1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1254.21-1254.29" + wire width 16 output 35 \RDATA_B2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1218.15-1218.21" + wire input 3 \REN_A1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1238.15-1238.21" + wire input 21 \REN_A2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1219.15-1219.21" + wire input 4 \REN_B1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1239.15-1239.21" + wire input 22 \REN_B2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1233.20-1233.30" + wire width 2 output 16 \RPARITY_A1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1253.20-1253.30" + wire width 2 output 34 \RPARITY_A2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1235.20-1235.30" + wire width 2 output 18 \RPARITY_B1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1255.20-1255.30" + wire width 2 output 36 \RPARITY_B2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1228.22-1228.30" + wire width 16 input 11 \WDATA_A1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1248.22-1248.30" + wire width 16 input 29 \WDATA_A2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1230.22-1230.30" + wire width 16 input 13 \WDATA_B1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1250.22-1250.30" + wire width 16 input 31 \WDATA_B2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1216.15-1216.21" + wire input 1 \WEN_A1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1236.15-1236.21" + wire input 19 \WEN_A2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1217.15-1217.21" + wire input 2 \WEN_B1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1237.15-1237.21" + wire input 20 \WEN_B2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1229.21-1229.31" + wire width 2 input 12 \WPARITY_A1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1249.21-1249.31" + wire width 2 input 30 \WPARITY_A2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1231.21-1231.31" + wire width 2 input 14 \WPARITY_B1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1251.21-1251.31" + wire width 2 input 32 \WPARITY_B2 +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1267.1-1296.10" +module \TDP_RAM36K + parameter \INIT 32768'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000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+ parameter \INIT_PARITY 4096'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \WRITE_WIDTH_A 36 + parameter \READ_WIDTH_A 36 + parameter \WRITE_WIDTH_B 36 + parameter \READ_WIDTH_B 36 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1285.22-1285.28" + wire width 15 input 9 \ADDR_A + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1286.22-1286.28" + wire width 15 input 10 \ADDR_B + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1283.21-1283.25" + wire width 4 input 7 \BE_A + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1284.21-1284.25" + wire width 4 input 8 \BE_B + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1280.15-1280.20" + wire input 5 \CLK_A + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1282.15-1282.20" + wire input 6 \CLK_B + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1291.21-1291.28" + wire width 32 output 15 \RDATA_A + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1293.21-1293.28" + wire width 32 output 17 \RDATA_B + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1277.15-1277.20" + wire input 3 \REN_A + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1278.15-1278.20" + wire input 4 \REN_B + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1292.20-1292.29" + wire width 4 output 16 \RPARITY_A + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1294.20-1294.29" + wire width 4 output 18 \RPARITY_B + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1287.22-1287.29" + wire width 32 input 11 \WDATA_A + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1289.22-1289.29" + wire width 32 input 13 \WDATA_B + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1275.15-1275.20" + wire input 1 \WEN_A + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1276.15-1276.20" + wire input 2 \WEN_B + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1288.21-1288.30" + wire width 4 input 12 \WPARITY_A + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1290.21-1290.30" + wire width 4 input 14 \WPARITY_B +end +attribute \dynports 1 +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:953.1-1356.10" +module \_$_mem_v2_asymmetric + parameter \CFG_ABITS 10 + parameter \CFG_DBITS 36 + parameter \CFG_ENABLE_B 4 + parameter \READ_ADDR_WIDTH 11 + parameter \READ_DATA_WIDTH 16 + parameter \WRITE_ADDR_WIDTH 10 + parameter \WRITE_DATA_WIDTH 32 + parameter \ABITS 0 + parameter \MEMID 0 + parameter \INIT 36864'x + parameter \OFFSET 0 + parameter \RD_ARST_VALUE 0 + parameter \RD_CE_OVER_SRST 0 + parameter \RD_CLK_ENABLE 0 + parameter \RD_CLK_POLARITY 0 + parameter \RD_COLLISION_X_MASK 0 + parameter \RD_PORTS 0 + parameter \RD_SRST_VALUE 0 + parameter \RD_TRANSPARENCY_MASK 0 + parameter \RD_WIDE_CONTINUATION 0 + parameter \SIZE 0 + parameter \WIDTH 0 + parameter \WR_CLK_ENABLE 0 + parameter \WR_CLK_POLARITY 0 + parameter \WR_PORTS 0 + parameter \WR_PRIORITY_MASK 0 + parameter \WR_WIDE_CONTINUATION 0 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:998.27-998.34" + wire width 10 input 1 \RD_ADDR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:995.11-995.18" + wire input 2 \RD_ARST + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:993.11-993.17" + wire input 3 \RD_CLK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:999.28-999.35" + wire width 36 output 4 \RD_DATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:1000.11-1000.16" + wire input 5 \RD_EN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:996.11-996.18" + wire input 6 \RD_SRST + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:1002.27-1002.34" + wire width 10 input 7 \WR_ADDR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:994.11-994.17" + wire input 8 \WR_CLK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:1003.27-1003.34" + wire width 36 input 9 \WR_DATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:1004.30-1004.35" + wire width 4 input 10 \WR_EN +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/common/cells_sim.v:11.1-16.10" +module \buff + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/common/cells_sim.v:13.12-13.13" + wire input 2 \A + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/common/cells_sim.v:12.12-12.13" + wire output 1 \Q +end +attribute \top 1 +attribute \src "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:1.1-29.10" +module \clk_buf_primitive_inst + attribute \init 1'0 + attribute \keep 1 + attribute \src "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:8.5-8.17" + wire $f2g_tx_out_wire_out_clk + attribute \src "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:3.9-3.20" + attribute \unused_bits "0" + wire $ibuf_ibuf_enable + attribute \src "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:2.9-2.20" + wire input 1 \clock_input + attribute \init 1'0 + attribute \keep 1 + attribute \src "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:4.10-4.22" + wire output 3 \clock_output + attribute \src "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:3.9-3.20" + wire input 2 \ibuf_enable + attribute \src "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:7.6-7.11" + wire \wire1 + attribute \src "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:7.13-7.18" + wire \wire2 + attribute \init 1'0 + attribute \keep 1 + attribute \src "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:8.5-8.17" + wire \wire_out_clk + attribute \module_not_derived 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:10.11-10.70" + cell \DFFRE $abc$194$auto_195 + connect \C \wire1 + connect \D \wire2 + connect \E 1'1 + connect \Q \wire_out_clk + connect \R 1'1 + end + attribute \keep 1 + cell \O_FAB $f2g_tx_out_wire_out_clk_1 + connect \I \wire_out_clk + connect \O $f2g_tx_out_wire_out_clk + end + attribute \keep 1 + attribute \module_not_derived 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" + cell \I_BUF $ibuf$clk_buf_primitive_inst.$ibuf_clock_input + parameter \WEAK_KEEPER "NONE" + connect \EN 1'1 + connect \I \clock_input + connect \O \wire2 + end + attribute \keep 1 + attribute \module_not_derived 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" + cell \I_BUF $ibuf$clk_buf_primitive_inst.$ibuf_ibuf_enable + parameter \WEAK_KEEPER "NONE" + connect \EN 1'1 + connect \I \ibuf_enable + connect \O $ibuf_ibuf_enable + end + attribute \keep 1 + attribute \module_not_derived 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" + cell \O_BUFT $obuf$clk_buf_primitive_inst.$obuf_clock_output + connect \I $f2g_tx_out_wire_out_clk + connect \O \clock_output + connect \T 1'1 + end + attribute \module_not_derived 1 + attribute \src "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:21.11-24.4" + cell \CLK_BUF \clk_buf_inst + connect \I \wire2 + connect \O \wire1 + end +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/common/cells_sim.v:31.1-38.10" +module \gclkbuff + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/common/cells_sim.v:32.12-32.13" + wire input 1 \A + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/common/cells_sim.v:33.12-33.13" + wire output 2 \Z +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/common/cells_sim.v:4.1-9.10" +module \inv + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/common/cells_sim.v:6.12-6.13" + wire input 2 \A + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/common/cells_sim.v:5.12-5.13" + wire output 1 \Q +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/common/cells_sim.v:18.1-22.10" +module \logic_0 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/common/cells_sim.v:19.12-19.13" + wire output 1 \a +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/common/cells_sim.v:24.1-28.10" +module \logic_1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/common/cells_sim.v:25.12-25.13" + wire output 1 \a +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v:8.1-15.12" +module \rs__CLK_BUF + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v:9.13-9.14" + wire input 1 \I + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v:10.13-10.14" + wire output 2 \O +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v:54.1-64.10" +module \rs__IO_BUF + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v:56.13-56.14" + wire input 1 \I + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v:58.13-58.15" + wire inout 3 \IO + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v:59.13-59.14" + wire output 4 \O + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v:57.13-57.14" + wire input 2 \T +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v:23.3-34.10" +module \rs__I_BUF + parameter \WEAK_KEEPER "NONE" + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v:27.12-27.14" + wire input 2 \EN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v:26.12-26.13" + wire input 1 \I + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v:28.13-28.14" + wire output 3 \O +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v:41.1-48.10" +module \rs__O_BUF + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v:42.9-42.10" + wire input 1 \I + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v:43.10-43.11" + wire output 2 \O +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v:70.1-80.10" +module \rs__O_BUFT + parameter \WEAK_KEEPER "NONE" + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v:73.13-73.14" + wire input 1 \I + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v:75.13-75.14" + wire output 3 \O + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v:74.13-74.14" + wire input 2 \T +end diff --git a/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/synthesis/design_edit.sdc b/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/synthesis/design_edit.sdc new file mode 100644 index 00000000..d0cd4e8b --- /dev/null +++ b/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/synthesis/design_edit.sdc @@ -0,0 +1,55 @@ +############# +# +# Fabric clock assignment +# +############# +# This clock need to route to fabric slot #0 +# set_clock_pin -device_clock clk[0] -design_clock clock_input (Physical port name, clock module: CLK_BUF clk_buf_inst) +# set_clock_pin -device_clock clk[0] -design_clock wire1 (Original clock primitive out-net to fabric) +set_clock_pin -device_clock clk[0] -design_clock wire1 + +############# +# +# Each pin mode and location assignment +# +############# +# Pin location is not assigned +# Pin clock_input :: I_BUF |-> CLK_BUF + +# Pin location is not assigned +# Pin ibuf_enable :: I_BUF + +# Pin location is not assigned +# Pin clock_output :: O_BUFT + +############# +# +# Internal Control Signals +# +############# +# Module: I_BUF +# LinkedObject: clock_input +# Location: +# Port: EN +# Signal: in:f2g_in_en_{A|B} +# Skip: Location is not assigned + +# Module: I_BUF +# LinkedObject: ibuf_enable +# Location: +# Port: EN +# Signal: in:f2g_in_en_{A|B} +# Skip: Location is not assigned + +# Module: O_BUFT +# LinkedObject: clock_output +# Location: +# Port: T +# Signal: in:f2g_tx_oe_{A|B} +# Skip: Location is not assigned + +############# +# +# Each gearbox core clock +# +############# diff --git a/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/synthesis/fabric_clk_buf_primitive_inst_post_synth.eblif b/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/synthesis/fabric_clk_buf_primitive_inst_post_synth.eblif new file mode 100644 index 00000000..8d70ffdf --- /dev/null +++ b/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/synthesis/fabric_clk_buf_primitive_inst_post_synth.eblif @@ -0,0 +1,19 @@ +# Generated by Yosys 0.44 (git sha1 7a4a3768c, g++ 11.2.1 -fPIC -O3) + +.model fabric_clk_buf_primitive_inst +.inputs $ibuf_ibuf_enable wire1 wire2 +.outputs $auto_416 $auto_417 $auto_418 $auto_419 $f2g_tx_out_wire_out_clk +.names $false +.names $true +1 +.names $undef +.subckt DFFRE C=wire1 D=wire2 E=$true Q=$f2g_tx_out_wire_out_clk R=$true +.names $true $auto_416 +1 1 +.names $true $auto_418 +1 1 +.names $true $auto_417 +1 1 +.names $ibuf_ibuf_enable $auto_419 +1 1 +.end diff --git a/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/synthesis/fabric_clk_buf_primitive_inst_post_synth.v b/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/synthesis/fabric_clk_buf_primitive_inst_post_synth.v new file mode 100644 index 00000000..9063284a --- /dev/null +++ b/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/synthesis/fabric_clk_buf_primitive_inst_post_synth.v @@ -0,0 +1,45 @@ +/* Generated by Yosys 0.44 (git sha1 7a4a3768c, g++ 11.2.1 -fPIC -O3) */ + +module fabric_clk_buf_primitive_inst(\$auto_416 , \$auto_417 , \$auto_418 , \$auto_419 , \$f2g_tx_out_wire_out_clk , \$ibuf_ibuf_enable , wire1, wire2); + output \$auto_416 ; + output \$auto_417 ; + output \$auto_418 ; + output \$auto_419 ; + output \$f2g_tx_out_wire_out_clk ; + input \$ibuf_ibuf_enable ; + input wire1; + input wire2; + wire \$auto_416 ; + wire \$auto_417 ; + wire \$auto_418 ; + wire \$auto_419 ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:8.5-8.17" *) + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:8.5-8.17" *) + wire \$f2g_tx_out_wire_out_clk ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:3.9-3.20" *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:3.9-3.20" *) + wire \$ibuf_ibuf_enable ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:7.6-7.11" *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:7.6-7.11" *) + wire wire1; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:7.13-7.18" *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:7.13-7.18" *) + wire wire2; + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:10.11-10.70" *) + DFFRE \$abc$194$auto_195 ( + .C(wire1), + .D(wire2), + .E(1'h1), + .Q(\$f2g_tx_out_wire_out_clk ), + .R(1'h1) + ); + assign \$auto_416 = 1'h1; + assign \$auto_418 = 1'h1; + assign \$auto_417 = 1'h1; + assign \$auto_419 = \$ibuf_ibuf_enable ; +endmodule diff --git a/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/synthesis/fabric_netlist_info.json b/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/synthesis/fabric_netlist_info.json new file mode 100644 index 00000000..e50e9096 --- /dev/null +++ b/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/synthesis/fabric_netlist_info.json @@ -0,0 +1,9 @@ +{ + "ports": [ + { + "clock": "active_high", + "direction": "input", + "name": "wire1" + } + ] +} diff --git a/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/synthesis/io_config.json b/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/synthesis/io_config.json new file mode 100644 index 00000000..4e201a9e --- /dev/null +++ b/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/synthesis/io_config.json @@ -0,0 +1,267 @@ +{ + "status": true, + "messages": [ + "Start of IO Analysis", + " Get Ports", + " Detect input port \\clock_input (index=0, width=1, offset=0)", + " Detect output port \\clock_output (index=0, width=1, offset=0)", + " Detect input port \\ibuf_enable (index=0, width=1, offset=0)", + " Get Port/Standalone Primitives", + " Get important connection of cell \\I_BUF $ibuf$clk_buf_primitive_inst.$ibuf_clock_input", + " Cell port \\I is connected to input port \\clock_input", + " Parameter \\WEAK_KEEPER: \"NONE\"", + " Data Width: -2", + " Get important connection of cell \\I_BUF $ibuf$clk_buf_primitive_inst.$ibuf_ibuf_enable", + " Cell port \\I is connected to input port \\ibuf_enable", + " Parameter \\WEAK_KEEPER: \"NONE\"", + " Data Width: -2", + " Get important connection of cell \\O_BUFT $obuf$clk_buf_primitive_inst.$obuf_clock_output", + " Cell port \\O is connected to output port \\clock_output", + " Data Width: -2", + " Trace \\I_BUF --> \\CLK_BUF", + " Try \\I_BUF $ibuf$clk_buf_primitive_inst.$ibuf_clock_input out connection: \\wire2 -> \\clk_buf_inst", + " Connected \\clk_buf_inst", + " Data Width: -2", + " Trace \\I_BUF_DS --> \\CLK_BUF", + " Trace \\CLK_BUF --> \\PLL", + " Trace \\BOOT_CLOCK --> \\PLL", + " Trace \\I_BUF --> \\I_DELAY", + " Trace \\I_BUF --> \\I_DDR", + " Trace \\I_BUF --> \\I_SERDES", + " Trace \\I_BUF_DS --> \\I_DELAY", + " Trace \\I_BUF_DS --> \\I_DDR", + " Trace \\I_BUF_DS --> \\I_SERDES", + " Trace \\I_DELAY --> \\I_DDR", + " Trace \\I_DELAY --> \\I_SERDES", + " Trace \\O_BUF --> \\O_DELAY", + " Trace \\O_BUF --> \\O_DDR", + " Trace \\O_BUF --> \\O_SERDES", + " Trace \\O_BUFT --> \\O_DELAY", + " Trace \\O_BUFT --> \\O_DDR", + " Trace \\O_BUFT --> \\O_SERDES", + " Trace \\O_BUF_DS --> \\O_DELAY", + " Trace \\O_BUF_DS --> \\O_DDR", + " Trace \\O_BUF_DS --> \\O_SERDES", + " Trace \\O_BUFT_DS --> \\O_DELAY", + " Trace \\O_BUFT_DS --> \\O_DDR", + " Trace \\O_BUFT_DS --> \\O_SERDES", + " Trace \\O_DELAY --> \\O_DDR", + " Trace \\O_DELAY --> \\O_SERDES", + " Trace \\O_BUF --> \\O_SERDES_CLK", + " Trace \\O_BUFT --> \\O_SERDES_CLK", + " Trace \\O_BUF_DS --> \\O_SERDES_CLK", + " Trace \\O_BUFT_DS --> \\O_SERDES_CLK", + " Trace fabric clock buffer", + " Trace gearbox fast clock source", + " Trace Core/Fabric Clock", + " Module \\CLK_BUF \\clk_buf_inst: clock port \\O, net \\wire1", + " Connected to cell \\DFFRE $abc$194$auto_195", + " Which is not a IO primitive. Send to fabric", + " Use slot 0", + " Double check Core/Fabric Clock", + " Summary", + " |-------------------------------------------------------------------------------|", + " | **************************************************** |", + " IN | clock_input * I_BUF |-> CLK_BUF * |", + " IN | ibuf_enable * I_BUF * |", + " OUT | * O_BUFT * clock_output |", + " | **************************************************** |", + " |-------------------------------------------------------------------------------|", + " Final checking is good", + " Cross-check instances vs wrapped-instances", + " Finalize instance location", + " Generate SDC", + " Determine fabric clock", + " Determine data pin mode and location", + " Pin object=clock_input, location: ", + " Pin location is not assigned", + " Pin object=ibuf_enable, location: ", + " Pin location is not assigned", + " Pin object=clock_output, location: ", + " Pin location is not assigned", + " Determine internal control signals", + " Group signals by location", + " Process output fabric signal f2g_in_en", + " Look for primitive \\I_SERDES port \\EN", + " Look for primitive \\I_DDR port \\E", + " Look for primitive \\O_SERDES port \\OE_IN", + " Look for primitive \\I_BUF port \\EN", + " Instance $ibuf$clk_buf_primitive_inst.$ibuf_clock_input location ", + " Skip: Location is not assigned", + " Instance $ibuf$clk_buf_primitive_inst.$ibuf_ibuf_enable location ", + " Skip: Location is not assigned", + " Look for primitive \\I_BUF_DS port \\EN", + " Process output fabric signal f2g_tx_oe", + " Look for primitive \\O_DDR port \\E", + " Look for primitive \\O_BUFT port \\T", + " Instance $obuf$clk_buf_primitive_inst.$obuf_clock_output location ", + " Skip: Location is not assigned", + " Look for primitive \\O_BUFT_DS port \\T", + " Process output fabric signal f2g_trx_dly_ld", + " Look for primitive \\I_DELAY port \\DLY_LOAD", + " Look for primitive \\O_DELAY port \\DLY_LOAD", + " Process output fabric signal f2g_trx_dly_adj", + " Look for primitive \\I_DELAY port \\DLY_ADJ", + " Look for primitive \\O_DELAY port \\DLY_ADJ", + " Process output fabric signal f2g_trx_dly_inc", + " Look for primitive \\I_DELAY port \\DLY_INCDEC", + " Look for primitive \\O_DELAY port \\DLY_INCDEC", + " Process input fabric signal g2f_trx_dly_tap", + " Look for primitive \\I_DELAY port \\DLY_TAP_VALUE", + " Look for primitive \\O_DELAY port \\DLY_TAP_VALUE", + " Process output fabric signal f2g_trx_reset_n", + " Look for primitive \\I_SERDES port \\RST", + " Look for primitive \\O_SERDES port \\RST", + " Look for primitive \\I_DDR port \\R", + " Look for primitive \\O_DDR port \\R", + " Process input fabric signal g2f_rx_dvalid", + " Look for primitive \\I_SERDES port \\DATA_VALID", + " Process output fabric signal f2g_rx_bitslip_adj", + " Look for primitive \\I_SERDES port \\BITSLIP_ADJ", + " Process input fabric signal g2f_rx_dpa_lock", + " Look for primitive \\I_SERDES port \\DPA_LOCK", + " Process input fabric signal g2f_rx_dpa_error", + " Look for primitive \\I_SERDES port \\DPA_ERROR", + " Process output fabric signal f2g_tx_dvalid", + " Look for primitive \\O_SERDES port \\DATA_VALID", + " Process output fabric signal f2g_tx_clk_en", + " Look for primitive \\O_SERDES_CLK port \\CLK_EN", + " Write out SDC", + " Module=I_BUF LinkedObject=clock_input Location= Port=EN Signal=in:f2g_in_en_{A|B}", + " Skip: Location is not assigned", + " Module=I_BUF LinkedObject=ibuf_enable Location= Port=EN Signal=in:f2g_in_en_{A|B}", + " Skip: Location is not assigned", + " Module=O_BUFT LinkedObject=clock_output Location= Port=T Signal=in:f2g_tx_oe_{A|B}", + " Skip: Location is not assigned", + " Determine gearbox core clock", + "End of IO Analysis" + ], + "instances": [ + { + "module": "I_BUF", + "name": "$ibuf$clk_buf_primitive_inst.$ibuf_clock_input", + "location_object": "clock_input", + "location": "", + "linked_object": "clock_input", + "linked_objects": { + "clock_input": { + "location": "", + "properties": { + } + } + }, + "connectivity": { + "I": "clock_input", + "O": "wire2" + }, + "parameters": { + "WEAK_KEEPER": "NONE" + }, + "flags": [ + "I_BUF" + ], + "pre_primitive": "", + "post_primitives": [ + "CLK_BUF" + ], + "route_clock_to": { + }, + "errors": [ + ] + }, + { + "module": "CLK_BUF", + "name": "clk_buf_inst", + "location_object": "clock_input", + "location": "", + "linked_object": "clock_input", + "linked_objects": { + "clock_input": { + "location": "", + "properties": { + "ROUTE_TO_FABRIC_CLK": "0" + } + } + }, + "connectivity": { + "I": "wire2", + "O": "wire1" + }, + "parameters": { + "ROUTE_TO_FABRIC_CLK": "0" + }, + "flags": [ + "CLK_BUF", + "PIN_CLOCK_CORE_ONLY" + ], + "pre_primitive": "I_BUF", + "post_primitives": [ + ], + "route_clock_to": { + }, + "errors": [ + ] + }, + { + "module": "I_BUF", + "name": "$ibuf$clk_buf_primitive_inst.$ibuf_ibuf_enable", + "location_object": "ibuf_enable", + "location": "", + "linked_object": "ibuf_enable", + "linked_objects": { + "ibuf_enable": { + "location": "", + "properties": { + } + } + }, + "connectivity": { + "I": "ibuf_enable", + "O": "$ibuf_ibuf_enable" + }, + "parameters": { + "WEAK_KEEPER": "NONE" + }, + "flags": [ + "I_BUF" + ], + "pre_primitive": "", + "post_primitives": [ + ], + "route_clock_to": { + }, + "errors": [ + ] + }, + { + "module": "O_BUFT", + "name": "$obuf$clk_buf_primitive_inst.$obuf_clock_output", + "location_object": "clock_output", + "location": "", + "linked_object": "clock_output", + "linked_objects": { + "clock_output": { + "location": "", + "properties": { + } + } + }, + "connectivity": { + "I": "$f2g_tx_out_wire_out_clk", + "O": "clock_output" + }, + "parameters": { + }, + "flags": [ + "O_BUFT" + ], + "pre_primitive": "", + "post_primitives": [ + ], + "route_clock_to": { + }, + "errors": [ + ] + } + ] +} diff --git a/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/synthesis/netlist_checker.log b/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/synthesis/netlist_checker.log new file mode 100644 index 00000000..734108e5 --- /dev/null +++ b/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/synthesis/netlist_checker.log @@ -0,0 +1,6 @@ +Checking Buffer connections +All IO connections are correct. + +Checking FCLK_BUF connections +================================================================ +================================================================ diff --git a/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/synthesis/netlist_info.json b/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/synthesis/netlist_info.json new file mode 100644 index 00000000..67981eea --- /dev/null +++ b/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/synthesis/netlist_info.json @@ -0,0 +1,18 @@ +{ + "top" : "clk_buf_primitive_inst", + "ports" : [ + { + "name": "clock_input", + "direction": "input", + "clock": "active_high" + }, + { + "name": "clock_output", + "direction": "output" + }, + { + "name": "ibuf_enable", + "direction": "input" + } + ] +} diff --git a/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/synthesis/pin_location_clk_buf_primitive_inst.sdc b/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/synthesis/pin_location_clk_buf_primitive_inst.sdc new file mode 100644 index 00000000..e69de29b diff --git a/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/synthesis/post_pnr_wrapper_clk_buf_primitive_inst_post_synth.eblif b/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/synthesis/post_pnr_wrapper_clk_buf_primitive_inst_post_synth.eblif new file mode 100644 index 00000000..a957da01 --- /dev/null +++ b/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/synthesis/post_pnr_wrapper_clk_buf_primitive_inst_post_synth.eblif @@ -0,0 +1,17 @@ +# Generated by Yosys 0.44 (git sha1 7a4a3768c, g++ 11.2.1 -fPIC -O3) + +.model clk_buf_primitive_inst +.inputs clock_input ibuf_enable +.outputs clock_output +.names $false +.names $true +1 +.names $undef +.subckt CLK_BUF I=wire2 O=wire1 +.subckt I_BUF EN=$auto_416 I=clock_input O=wire2 +.param WEAK_KEEPER "NONE" +.subckt I_BUF EN=$auto_417 I=ibuf_enable O=$ibuf_ibuf_enable +.param WEAK_KEEPER "NONE" +.subckt O_BUFT I=$f2g_tx_out_wire_out_clk O=clock_output T=$auto_418 +.subckt fabric_clk_buf_primitive_inst $auto_416=$auto_416 $auto_417=$auto_417 $auto_418=$auto_418 $f2g_tx_out_wire_out_clk=$f2g_tx_out_wire_out_clk $ibuf_ibuf_enable=$ibuf_ibuf_enable wire1=wire1 wire2=wire2 +.end diff --git a/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/synthesis/post_pnr_wrapper_clk_buf_primitive_inst_post_synth.v b/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/synthesis/post_pnr_wrapper_clk_buf_primitive_inst_post_synth.v new file mode 100644 index 00000000..db9c20b2 --- /dev/null +++ b/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/synthesis/post_pnr_wrapper_clk_buf_primitive_inst_post_synth.v @@ -0,0 +1,100 @@ +/* Generated by Yosys 0.44 (git sha1 7a4a3768c, g++ 11.2.1 -fPIC -O3) */ + +module clk_buf_primitive_inst_post_route(clock_input, ibuf_enable, clock_output); + input clock_input; + output clock_output; + input ibuf_enable; + wire \$auto_416 ; + wire \$auto_417 ; + wire \$auto_418 ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:2.9-2.20" *) + wire \$auto_420.clock_input ; + (* init = 1'h0 *) + (* keep = 32'sd1 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:4.10-4.22" *) + wire \$auto_420.clock_output ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:3.9-3.20" *) + wire \$auto_420.ibuf_enable ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:7.6-7.11" *) + wire \$auto_420.wire1 ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:7.13-7.18" *) + wire \$auto_420.wire2 ; + (* init = 1'h0 *) + (* keep = 32'sd1 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:8.5-8.17" *) + wire \$f2g_tx_out_wire_out_clk ; + wire \$flatten$auto_420.$auto_416 ; + wire \$flatten$auto_420.$auto_417 ; + wire \$flatten$auto_420.$auto_418 ; + (* init = 1'h0 *) + (* keep = 32'sd1 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:8.5-8.17" *) + wire \$flatten$auto_420.$f2g_tx_out_wire_out_clk ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:3.9-3.20" *) + (* unused_bits = "0" *) + wire \$flatten$auto_420.$ibuf_ibuf_enable ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:3.9-3.20" *) + (* unused_bits = "0" *) + wire \$ibuf_ibuf_enable ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:2.9-2.20" *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:2.9-2.20" *) + wire clock_input; + (* init = 1'h0 *) + (* keep = 32'sd1 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:4.10-4.22" *) + (* init = 1'h0 *) + (* keep = 32'sd1 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:4.10-4.22" *) + wire clock_output; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:3.9-3.20" *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:3.9-3.20" *) + wire ibuf_enable; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:7.6-7.11" *) + wire wire1; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:7.13-7.18" *) + wire wire2; + (* module_not_derived = 32'sd1 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:21.11-24.4" *) + CLK_BUF \$auto_420.clk_buf_inst ( + .I(wire2), + .O(wire1) + ); + (* keep = 32'sd1 *) + (* module_not_derived = 32'sd1 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$flatten$auto_420.$ibuf$clk_buf_primitive_inst.$ibuf_clock_input ( + .EN(\$auto_416 ), + .I(clock_input), + .O(wire2) + ); + (* keep = 32'sd1 *) + (* module_not_derived = 32'sd1 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$flatten$auto_420.$ibuf$clk_buf_primitive_inst.$ibuf_ibuf_enable ( + .EN(\$auto_417 ), + .I(ibuf_enable), + .O(\$ibuf_ibuf_enable ) + ); + (* keep = 32'sd1 *) + (* module_not_derived = 32'sd1 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) + O_BUFT \$flatten$auto_420.$obuf$clk_buf_primitive_inst.$obuf_clock_output ( + .I(\$f2g_tx_out_wire_out_clk ), + .O(clock_output), + .T(\$auto_418 ) + ); + fabric_clk_buf_primitive_inst fabric_instance ( + .\$auto_416 (\$auto_416 ), + .\$auto_417 (\$auto_417 ), + .\$auto_418 (\$auto_418 ), + .\$f2g_tx_out_wire_out_clk (\$f2g_tx_out_wire_out_clk ), + .\$ibuf_ibuf_enable (\$ibuf_ibuf_enable ), + .wire1(wire1), + .wire2(wire2) + ); +endmodule + diff --git a/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/synthesis/reports/synth_design_stat.json b/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/synthesis/reports/synth_design_stat.json new file mode 100644 index 00000000..5684716e --- /dev/null +++ b/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/synthesis/reports/synth_design_stat.json @@ -0,0 +1,40 @@ +[ + { + "": { + "header": [ + "Design statistics", + "" + ], + "data": [ + [ + "CLB LUT packing percentage", + "0 %" + ], + [ + "CLB Register packing percentage", + "0 %" + ], + [ + "Wires", + "0" + ], + [ + "Max Fanout", + "0" + ], + [ + "Average Fanout", + "0" + ], + [ + "Maximum logic level", + "0" + ], + [ + "Average logic level", + "0" + ] + ] + } + } +] \ No newline at end of file diff --git a/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/synthesis/reports/synth_utilization.json b/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/synthesis/reports/synth_utilization.json new file mode 100644 index 00000000..6414d8f2 --- /dev/null +++ b/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/synthesis/reports/synth_utilization.json @@ -0,0 +1,148 @@ +[ + { + "": { + "header": [ + "Logic", + "Used", + "Available", + "%" + ], + "data": [ + [ + "CLB", + "0", + "2184", + "0" + ], + [ + " LUTs", + "0", + "17472", + "0" + ], + [ + " Registers", + "1", + "34944", + "0" + ], + [ + " Flip Flop", + "1", + "34944", + "0" + ], + [ + " Adder Carry", + "0", + "17472", + "0" + ] + ] + } + }, + { + "": { + "header": [ + "Block RAM", + "Used", + "Available", + "%" + ], + "data": [ + [ + "BRAM", + "0", + "56", + "0" + ], + [ + " 18k", + "0", + "112", + "0" + ], + [ + " 36k", + "0", + "56", + "0" + ] + ] + } + }, + { + "": { + "header": [ + "DSP", + "Used", + "Available", + "%" + ], + "data": [ + [ + "DSP Block", + "0", + "56", + "0" + ], + [ + " 9x10", + "0", + "56", + "0" + ], + [ + " 18x20", + "0", + "112", + "0" + ] + ] + } + }, + { + "": { + "header": [ + "I/O", + "Used", + "Available", + "%" + ], + "data": [ + [ + "I/O", + "0", + "240", + "0" + ], + [ + " Inputs", + "0", + "240", + "0" + ], + [ + " Outputs", + "0", + "240", + "0" + ] + ] + } + }, + { + "": { + "header": [ + "Clock", + "Used" + ], + "data": [ + [ + "Clock", + "0" + ] + ] + } + } +] \ No newline at end of file diff --git a/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/synthesis/synthesis.rpt b/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/synthesis/synthesis.rpt new file mode 100644 index 00000000..3ae48d4f --- /dev/null +++ b/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/synthesis/synthesis.rpt @@ -0,0 +1,2288 @@ +/******************************************************************************* +Copyright (c) 2022-2024 Rapid Silicon +This source code contains proprietary information belonging to Rapid Silicon +(the "licensor") released under license and non-disclosure agreement to the +recipient (the "licensee"). + +The information shared and protected by the license and non-disclosure agreement +includes but is not limited to the following: +* operational algorithms of the product +* logos, graphics, source code, and visual presentation of the product +* confidential operational information of the licensor + +The recipient of this source code is NOT permitted to publicly disclose, +re-use, archive beyond the period of the license agreement, transfer to a +sub-licensee, or re-implement any portion of the content covered by the license +and non-disclosure agreement without the prior written consent of the licensor. +*********************************************************************************/ + +Version : 2024.10 +Build : 1.2.18 +Hash : 82370d4 +Date : Oct 12 2024 +Type : Engineering +Log Time : Mon Oct 14 05:17:33 2024 GMT + + /----------------------------------------------------------------------------\ + | yosys -- Yosys Open SYnthesis Suite | + | Copyright (C) 2012 - 2024 Claire Xenia Wolf | + | Distributed under an ISC-like license, type "license" to see terms | + \----------------------------------------------------------------------------/ + + Yosys 0.44 (git sha1 7a4a3768c, g++ 11.2.1 -fPIC -O3) + +-- Executing script file `clk_buf_primitive_inst.ys' -- + +1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v +Parsing SystemVerilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v' to AST representation. +Generating RTLIL representation for module `\BOOT_CLOCK'. +Generating RTLIL representation for module `\CARRY'. +Generating RTLIL representation for module `\CLK_BUF'. +Generating RTLIL representation for module `\DFFNRE'. +Generating RTLIL representation for module `\DFFRE'. +Generating RTLIL representation for module `\DLY_SEL_DCODER'. +Generating RTLIL representation for module `\DLY_SEL_DECODER'. +Generating RTLIL representation for module `\DLY_VALUE_MUX'. +Generating RTLIL representation for module `\DSP19X2'. +Generating RTLIL representation for module `\DSP38'. +Generating RTLIL representation for module `\FCLK_BUF'. +Generating RTLIL representation for module `\FIFO18KX2'. +Generating RTLIL representation for module `\FIFO36K'. +Generating RTLIL representation for module `\I_BUF_DS'. +Generating RTLIL representation for module `\I_BUF'. +Generating RTLIL representation for module `\I_DDR'. +Generating RTLIL representation for module `\I_DELAY'. +Generating RTLIL representation for module `\I_FAB'. +Generating RTLIL representation for module `\I_SERDES'. +Generating RTLIL representation for module `\LATCHNR'. +Generating RTLIL representation for module `\LATCHNS'. +Generating RTLIL representation for module `\LATCHN'. +Generating RTLIL representation for module `\LATCHR'. +Generating RTLIL representation for module `\LATCHS'. +Generating RTLIL representation for module `\LATCH'. +Generating RTLIL representation for module `\LUT1'. +Generating RTLIL representation for module `\LUT2'. +Generating RTLIL representation for module `\LUT3'. +Generating RTLIL representation for module `\LUT4'. +Generating RTLIL representation for module `\LUT5'. +Generating RTLIL representation for module `\LUT6'. +Generating RTLIL representation for module `\MIPI_RX'. +Generating RTLIL representation for module `\MIPI_TX'. +Generating RTLIL representation for module `\O_BUF_DS'. +Generating RTLIL representation for module `\O_BUFT_DS'. +Generating RTLIL representation for module `\O_BUFT'. +Generating RTLIL representation for module `\O_BUF'. +Generating RTLIL representation for module `\O_DDR'. +Generating RTLIL representation for module `\O_DELAY'. +Generating RTLIL representation for module `\O_FAB'. +Generating RTLIL representation for module `\O_SERDES_CLK'. +Generating RTLIL representation for module `\O_SERDES'. +Generating RTLIL representation for module `\PLL'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AHB_M'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AHB_S'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AXI_M0'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AXI_M1'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_DMA'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_IRQ'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_JTAG'. +Generating RTLIL representation for module `\SOC_FPGA_TEMPERATURE'. +Generating RTLIL representation for module `\TDP_RAM18KX2'. +Generating RTLIL representation for module `\TDP_RAM36K'. +Successfully finished Verilog frontend. + +2. Executing Verilog-2005 frontend: /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v +Parsing Verilog input from `/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v' to AST representation. +Generating RTLIL representation for module `\clk_buf_primitive_inst'. +Successfully finished Verilog frontend. + +3. Executing HIERARCHY pass (managing design hierarchy). + +3.1. Analyzing design hierarchy.. +Top module: \clk_buf_primitive_inst + +3.2. Analyzing design hierarchy.. +Top module: \clk_buf_primitive_inst +Removed 0 unused modules. + +4. Executing synth_rs pass: v0.4.218 + +4.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/common/cells_sim.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/common/cells_sim.v' to AST representation. +Generating RTLIL representation for module `\inv'. +Generating RTLIL representation for module `\buff'. +Generating RTLIL representation for module `\logic_0'. +Generating RTLIL representation for module `\logic_1'. +Generating RTLIL representation for module `\gclkbuff'. +Successfully finished Verilog frontend. + +4.2. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CARRY.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CARRY.v' to AST representation. +Replacing existing blackbox module `\CARRY' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CARRY.v:10.1-33.10. +Generating RTLIL representation for module `\CARRY'. +Successfully finished Verilog frontend. + +4.3. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v' to AST representation. +Replacing existing blackbox module `\LATCH' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:20.1-34.10. +Generating RTLIL representation for module `\LATCH'. +Replacing existing blackbox module `\LATCHN' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:48.1-62.10. +Generating RTLIL representation for module `\LATCHN'. +Replacing existing blackbox module `\LATCHR' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:81.1-97.10. +Generating RTLIL representation for module `\LATCHR'. +Replacing existing blackbox module `\LATCHS' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:115.1-131.10. +Generating RTLIL representation for module `\LATCHS'. +Replacing existing blackbox module `\LATCHNR' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:150.1-166.10. +Generating RTLIL representation for module `\LATCHNR'. +Replacing existing blackbox module `\LATCHNS' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:184.1-200.10. +Generating RTLIL representation for module `\LATCHNS'. +Generating RTLIL representation for module `\LATCHSRE'. +Generating RTLIL representation for module `\LATCHNSRE'. +Successfully finished Verilog frontend. + +4.4. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v' to AST representation. +Replacing existing blackbox module `\DFFRE' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v:11.1-81.10. +Generating RTLIL representation for module `\DFFRE'. +Successfully finished Verilog frontend. + +4.5. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v' to AST representation. +Replacing existing blackbox module `\DFFNRE' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v:11.1-80.10. +Generating RTLIL representation for module `\DFFNRE'. +Successfully finished Verilog frontend. + +4.6. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT1.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT1.v' to AST representation. +Replacing existing blackbox module `\LUT1' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT1.v:10.1-20.10. +Generating RTLIL representation for module `\LUT1'. +Successfully finished Verilog frontend. + +4.7. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT2.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT2.v' to AST representation. +Replacing existing blackbox module `\LUT2' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT2.v:10.1-21.10. +Generating RTLIL representation for module `\LUT2'. +Successfully finished Verilog frontend. + +4.8. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT3.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT3.v' to AST representation. +Replacing existing blackbox module `\LUT3' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT3.v:10.1-22.10. +Generating RTLIL representation for module `\LUT3'. +Successfully finished Verilog frontend. + +4.9. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT4.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT4.v' to AST representation. +Replacing existing blackbox module `\LUT4' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT4.v:11.1-25.10. +Generating RTLIL representation for module `\LUT4'. +Successfully finished Verilog frontend. + +4.10. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT5.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT5.v' to AST representation. +Replacing existing blackbox module `\LUT5' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT5.v:10.1-24.10. +Generating RTLIL representation for module `\LUT5'. +Successfully finished Verilog frontend. + +4.11. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT6.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT6.v' to AST representation. +Replacing existing blackbox module `\LUT6' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT6.v:10.1-25.10. +Generating RTLIL representation for module `\LUT6'. +Successfully finished Verilog frontend. + +4.12. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CLK_BUF.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CLK_BUF.v' to AST representation. +Replacing existing blackbox module `\CLK_BUF' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CLK_BUF.v:10.1-25.10. +Generating RTLIL representation for module `\CLK_BUF'. +Successfully finished Verilog frontend. + +4.13. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_BUF.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_BUF.v' to AST representation. +Replacing existing blackbox module `\O_BUF' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_BUF.v:10.1-84.10. +Generating RTLIL representation for module `\O_BUF'. +Successfully finished Verilog frontend. + +4.14. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DSP38.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DSP38.v' to AST representation. +Replacing existing blackbox module `\DSP38' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DSP38.v:10.1-341.10. +Generating RTLIL representation for module `\DSP38'. +Successfully finished Verilog frontend. + +4.15. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v' to AST representation. +Replacing existing blackbox module `\TDP_RAM36K' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v:2.1-29.10. +Generating RTLIL representation for module `\TDP_RAM36K'. +Replacing existing blackbox module `\TDP_RAM18KX2' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v:33.1-84.10. +Generating RTLIL representation for module `\TDP_RAM18KX2'. +Generating RTLIL representation for module `\RS_DSP3'. +Replacing existing blackbox module `\DSP19X2' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v:116.1-149.10. +Generating RTLIL representation for module `\DSP19X2'. +Successfully finished Verilog frontend. + +4.16. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v' to AST representation. +Generating RTLIL representation for module `\TDP_BRAM18'. +Generating RTLIL representation for module `\BRAM2x18_TDP'. +Generating RTLIL representation for module `\BRAM2x18_SDP'. +Generating RTLIL representation for module `\_$_mem_v2_asymmetric'. +Successfully finished Verilog frontend. + +4.17. Executing HIERARCHY pass (managing design hierarchy). + +4.17.1. Analyzing design hierarchy.. +Top module: \clk_buf_primitive_inst + +4.17.2. Analyzing design hierarchy.. +Top module: \clk_buf_primitive_inst +Removed 0 unused modules. + +4.18. Executing PROC pass (convert processes to netlists). + +4.18.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +4.18.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Removed a total of 0 dead cases. + +4.18.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 0 redundant assignments. +Promoted 2 assignments to connections. + +4.18.4. Executing PROC_INIT pass (extract init attributes). +Found init rule in `\clk_buf_primitive_inst.$proc$/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:8$2'. + Set init value: \wire_out_clk = 1'0 + +4.18.5. Executing PROC_ARST pass (detect async resets in processes). + +4.18.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. + +4.18.7. Executing PROC_MUX pass (convert decision trees to multiplexers). +Creating decoders for process `\clk_buf_primitive_inst.$proc$/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:8$2'. +Creating decoders for process `\clk_buf_primitive_inst.$proc$/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:16$1'. + +4.18.8. Executing PROC_DLATCH pass (convert process syncs to latches). + +4.18.9. Executing PROC_DFF pass (convert process syncs to FFs). +Creating register for signal `\clk_buf_primitive_inst.\wire_out_clk' using process `\clk_buf_primitive_inst.$proc$/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:16$1'. + created $dff cell `$procdff$3' with positive edge clock. + +4.18.10. Executing PROC_MEMWR pass (convert process memory writes to cells). + +4.18.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Removing empty process `clk_buf_primitive_inst.$proc$/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:8$2'. +Removing empty process `clk_buf_primitive_inst.$proc$/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:16$1'. +Cleaned up 0 empty switches. + +4.18.12. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.19. Executing FLATTEN pass (flatten design). + +# -------------------- +# Design entry stats +# -------------------- + +4.20. Printing statistics. + +=== clk_buf_primitive_inst === + + Number of wires: 8 + Number of wire bits: 8 + Number of public wires: 6 + Number of public wire bits: 6 + Number of ports: 3 + Number of port bits: 3 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $dff 1 + CLK_BUF 1 + I_BUF 1 + +4.21. Executing SPLITNETS pass (splitting up multi-bit signals). + +4.22. Executing DEMUXMAP pass. + +4.23. Executing FLATTEN pass (flatten design). + +4.24. Executing DEMUXMAP pass. + +4.25. Executing TRIBUF pass. +Warning: Ignored -no_iobuf because -keep_tribuf is used. + +4.26. Executing DEMINOUT pass (demote inout ports to input or output). + +4.27. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.28. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. +Removed 0 unused cells and 2 unused wires. + + +4.29. Executing CHECK pass (checking for obvious problems). +Checking module clk_buf_primitive_inst... +Found and reported 0 problems. + +4.30. Printing statistics. + +=== clk_buf_primitive_inst === + + Number of wires: 6 + Number of wire bits: 6 + Number of public wires: 6 + Number of public wire bits: 6 + Number of ports: 3 + Number of port bits: 3 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $dff 1 + CLK_BUF 1 + I_BUF 1 + +FF init value for cell $procdff$3 ($dff): \wire_out_clk = 1'0 + +4.31. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.32. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.33. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \clk_buf_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.34. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \clk_buf_primitive_inst. +Performed a total of 0 changes. + +4.35. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.36. Executing OPT_SHARE pass. + +4.37. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.38. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.39. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.40. Executing FSM pass (extract and optimize FSM). + +4.40.1. Executing FSM_DETECT pass (finding FSMs in design). + +4.40.2. Executing FSM_EXTRACT pass (extracting FSM from design). + +4.40.3. Executing FSM_OPT pass (simple optimizations of FSMs). + +4.40.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.40.5. Executing FSM_OPT pass (simple optimizations of FSMs). + +4.40.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). + +4.40.7. Executing FSM_INFO pass (dumping all available information on FSM cells). + +4.40.8. Executing FSM_MAP pass (mapping FSMs to basic logic). + +4.41. Executing WREDUCE pass (reducing word size of cells). + +4.42. Executing PEEPOPT pass (run peephole optimizers). + +4.43. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.44. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.45. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.46. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \clk_buf_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.47. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \clk_buf_primitive_inst. +Performed a total of 0 changes. + +4.48. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.49. Executing OPT_SHARE pass. + +4.50. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.51. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.52. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.53. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.54. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.55. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \clk_buf_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.56. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \clk_buf_primitive_inst. +Performed a total of 0 changes. + +4.57. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.58. Executing OPT_SHARE pass. + +4.59. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.60. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.61. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.62. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.63. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.64. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \clk_buf_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.65. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \clk_buf_primitive_inst. +Performed a total of 0 changes. + +4.66. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.67. Executing OPT_SHARE pass. + +4.68. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.69. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=1, #remove=0, time=0.00 sec.] + +4.70. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.71. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.72. Executing WREDUCE pass (reducing word size of cells). + +4.73. Executing PEEPOPT pass (run peephole optimizers). + +4.74. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.75. Executing DEMUXMAP pass. + +4.76. Executing SPLITNETS pass (splitting up multi-bit signals). + +4.77. Printing statistics. + +=== clk_buf_primitive_inst === + + Number of wires: 6 + Number of wire bits: 6 + Number of public wires: 6 + Number of public wire bits: 6 + Number of ports: 3 + Number of port bits: 3 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $dff 1 + CLK_BUF 1 + I_BUF 1 + +4.78. Executing RS_DSP_MULTADD pass. + +4.79. Executing WREDUCE pass (reducing word size of cells). + +4.80. Executing RS_DSP_MACC pass. + +4.81. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.82. Executing TECHMAP pass (map to technology primitives). + +4.82.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/mul2dsp_check_maxwidth.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/mul2dsp_check_maxwidth.v' to AST representation. +Generating RTLIL representation for module `\_80_mul'. +Generating RTLIL representation for module `\_90_soft_mul'. +Successfully finished Verilog frontend. + +4.82.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.83. Printing statistics. + +=== clk_buf_primitive_inst === + + Number of wires: 6 + Number of wire bits: 6 + Number of public wires: 6 + Number of public wire bits: 6 + Number of ports: 3 + Number of port bits: 3 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $dff 1 + CLK_BUF 1 + I_BUF 1 + +4.84. Executing TECHMAP pass (map to technology primitives). + +4.84.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/mul2dsp_check_maxwidth.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/mul2dsp_check_maxwidth.v' to AST representation. +Generating RTLIL representation for module `\_80_mul'. +Generating RTLIL representation for module `\_90_soft_mul'. +Successfully finished Verilog frontend. + +4.84.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.85. Printing statistics. + +=== clk_buf_primitive_inst === + + Number of wires: 6 + Number of wire bits: 6 + Number of public wires: 6 + Number of public wire bits: 6 + Number of ports: 3 + Number of port bits: 3 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $dff 1 + CLK_BUF 1 + I_BUF 1 + +4.86. Executing TECHMAP pass (map to technology primitives). + +4.86.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/mul2dsp.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/mul2dsp.v' to AST representation. +Generating RTLIL representation for module `\_80_mul'. +Generating RTLIL representation for module `\_90_soft_mul'. +Successfully finished Verilog frontend. + +4.86.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.87. Executing TECHMAP pass (map to technology primitives). + +4.87.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/mul2dsp.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/mul2dsp.v' to AST representation. +Generating RTLIL representation for module `\_80_mul'. +Generating RTLIL representation for module `\_90_soft_mul'. +Successfully finished Verilog frontend. + +4.87.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.88. Executing TECHMAP pass (map to technology primitives). + +4.88.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/dsp_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/dsp_map.v' to AST representation. +Generating RTLIL representation for module `\$__RS_MUL20X18'. +Generating RTLIL representation for module `\$__RS_MUL10X9'. +Successfully finished Verilog frontend. + +4.88.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.89. Executing RS_DSP_SIMD pass. + +4.90. Executing TECHMAP pass (map to technology primitives). + +4.90.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/dsp_final_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/dsp_final_map.v' to AST representation. +Generating RTLIL representation for module `\dsp_t1_20x18x64_cfg_ports'. +Generating RTLIL representation for module `\dsp_t1_10x9x32_cfg_params'. +Successfully finished Verilog frontend. + +4.90.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.91. Executing TECHMAP pass (map to technology primitives). + +4.91.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/dsp19x2_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/dsp19x2_map.v' to AST representation. +Generating RTLIL representation for module `\RS_DSPX2_MULTACC'. +Generating RTLIL representation for module `\RS_DSPX2_MULT'. +Generating RTLIL representation for module `\RS_DSPX2_MULT_REGIN'. +Generating RTLIL representation for module `\RS_DSPX2_MULT_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULT_REGIN_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULTADD'. +Generating RTLIL representation for module `\RS_DSPX2_MULTADD_REGIN'. +Generating RTLIL representation for module `\RS_DSPX2_MULTADD_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULTADD_REGIN_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULTACC_REGIN'. +Generating RTLIL representation for module `\RS_DSPX2_MULTACC_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULTACC_REGIN_REGOUT'. +Generating RTLIL representation for module `\RS_DSP3'. +Successfully finished Verilog frontend. + +4.91.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.92. Executing rs_pack_dsp_regs pass. + +4.93. Executing RS_DSP_IO_REGS pass. + +4.94. Executing TECHMAP pass (map to technology primitives). + +4.94.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/dsp38_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/dsp38_map.v' to AST representation. +Generating RTLIL representation for module `\RS_DSP_MULTACC'. +Generating RTLIL representation for module `\RS_DSP_MULT'. +Generating RTLIL representation for module `\RS_DSP_MULT_REGIN'. +Generating RTLIL representation for module `\RS_DSP_MULT_REGOUT'. +Generating RTLIL representation for module `\RS_DSP_MULT_REGIN_REGOUT'. +Generating RTLIL representation for module `\RS_DSP_MULTADD'. +Generating RTLIL representation for module `\RS_DSP_MULTADD_REGIN'. +Generating RTLIL representation for module `\RS_DSP_MULTADD_REGOUT'. +Generating RTLIL representation for module `\RS_DSP_MULTADD_REGIN_REGOUT'. +Generating RTLIL representation for module `\RS_DSP_MULTACC_REGIN'. +Generating RTLIL representation for module `\RS_DSP_MULTACC_REGOUT'. +Generating RTLIL representation for module `\RS_DSP_MULTACC_REGIN_REGOUT'. +Successfully finished Verilog frontend. + +4.94.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.95. Executing TECHMAP pass (map to technology primitives). + +4.95.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/dsp19x2_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/dsp19x2_map.v' to AST representation. +Generating RTLIL representation for module `\RS_DSPX2_MULTACC'. +Generating RTLIL representation for module `\RS_DSPX2_MULT'. +Generating RTLIL representation for module `\RS_DSPX2_MULT_REGIN'. +Generating RTLIL representation for module `\RS_DSPX2_MULT_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULT_REGIN_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULTADD'. +Generating RTLIL representation for module `\RS_DSPX2_MULTADD_REGIN'. +Generating RTLIL representation for module `\RS_DSPX2_MULTADD_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULTADD_REGIN_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULTACC_REGIN'. +Generating RTLIL representation for module `\RS_DSPX2_MULTACC_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULTACC_REGIN_REGOUT'. +Generating RTLIL representation for module `\RS_DSP3'. +Successfully finished Verilog frontend. + +4.95.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.96. Printing statistics. + +=== clk_buf_primitive_inst === + + Number of wires: 6 + Number of wire bits: 6 + Number of public wires: 6 + Number of public wire bits: 6 + Number of ports: 3 + Number of port bits: 3 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $dff 1 + CLK_BUF 1 + I_BUF 1 + +4.97. Executing ALUMACC pass (create $alu and $macc cells). +Extracting $alu and $macc cells in module clk_buf_primitive_inst: + created 0 $alu and 0 $macc cells. + +4.98. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.99. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.100. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \clk_buf_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.101. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \clk_buf_primitive_inst. +Performed a total of 0 changes. + +4.102. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.103. Executing OPT_SHARE pass. + +4.104. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.105. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.106. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.107. Printing statistics. + +=== clk_buf_primitive_inst === + + Number of wires: 6 + Number of wire bits: 6 + Number of public wires: 6 + Number of public wire bits: 6 + Number of ports: 3 + Number of port bits: 3 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $dff 1 + CLK_BUF 1 + I_BUF 1 + +4.108. Executing MEMORY pass. + +4.108.1. Executing OPT_MEM pass (optimize memories). +Performed a total of 0 transformations. + +4.108.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). +Performed a total of 0 transformations. + +4.108.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). + +4.108.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). + +4.108.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). + +4.108.6. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.108.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). + +4.108.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). +Performed a total of 0 transformations. + +4.108.9. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.108.10. Executing MEMORY_COLLECT pass (generating $mem cells). + +4.109. Printing statistics. + +=== clk_buf_primitive_inst === + + Number of wires: 6 + Number of wire bits: 6 + Number of public wires: 6 + Number of public wire bits: 6 + Number of ports: 3 + Number of port bits: 3 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $dff 1 + CLK_BUF 1 + I_BUF 1 + +4.110. Executing MUXPACK pass ($mux cell cascades to $pmux). +Converted 0 (p)mux cells into 0 pmux cells. + +4.111. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.112. Executing MEMORY_LIBMAP pass (mapping memories to cells). + +4.113. Executing MEMORY_LIBMAP pass (mapping memories to cells). + +4.114. Executing Rs_BRAM_Split pass. + +4.115. Executing TECHMAP pass (map to technology primitives). + +4.115.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_map_new_version.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_map_new_version.v' to AST representation. +Generating RTLIL representation for module `\$__RS_FACTOR_BRAM36_TDP'. +Generating RTLIL representation for module `\$__RS_FACTOR_BRAM18_TDP'. +Generating RTLIL representation for module `\$__RS_FACTOR_BRAM18_SDP'. +Generating RTLIL representation for module `\$__RS_FACTOR_BRAM36_SDP'. +Successfully finished Verilog frontend. + +4.115.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.116. Executing TECHMAP pass (map to technology primitives). + +4.116.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_final_map_new_version.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_final_map_new_version.v' to AST representation. +Generating RTLIL representation for module `\BRAM2x18_TDP'. +Generating RTLIL representation for module `\BRAM2x18_SDP'. +Successfully finished Verilog frontend. + +4.116.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.117. Executing DFFUNMAP pass (unmap clock enable and synchronous reset from FFs). + +4.118. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.119. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.120. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \clk_buf_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.121. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \clk_buf_primitive_inst. +Performed a total of 0 changes. + +4.122. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.123. Executing OPT_SHARE pass. + +4.124. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.125. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.126. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.127. Executing PMUXTREE pass. + +4.128. Executing MUXPACK pass ($mux cell cascades to $pmux). +Converted 0 (p)mux cells into 0 pmux cells. + +4.129. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). + +4.130. Executing TECHMAP pass (map to technology primitives). + +4.130.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/techmap.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu_brent_kung'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. + +4.130.2. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/arith_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/arith_map.v' to AST representation. +Generating RTLIL representation for module `\_80_rs_alu'. +Successfully finished Verilog frontend. + +4.130.3. Continuing TECHMAP pass. +Using extmapper simplemap for cells of type $dff. +No more expansions possible. + + +4.131. Printing statistics. + +=== clk_buf_primitive_inst === + + Number of wires: 6 + Number of wire bits: 6 + Number of public wires: 6 + Number of public wire bits: 6 + Number of ports: 3 + Number of port bits: 3 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $_DFF_P_ 1 + CLK_BUF 1 + I_BUF 1 + +4.132. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.133. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.134. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \clk_buf_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.135. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \clk_buf_primitive_inst. +Performed a total of 0 changes. + +4.136. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.137. Executing OPT_SHARE pass. + +4.138. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.139. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.140. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.141. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.142. Executing TECHMAP pass (map to technology primitives). + +4.142.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/techmap.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu_brent_kung'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. + +4.142.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.143. Printing statistics. + +=== clk_buf_primitive_inst === + + Number of wires: 6 + Number of wire bits: 6 + Number of public wires: 6 + Number of public wire bits: 6 + Number of ports: 3 + Number of port bits: 3 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $_DFF_P_ 1 + CLK_BUF 1 + I_BUF 1 + +4.144. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.145. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.146. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \clk_buf_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.147. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \clk_buf_primitive_inst. +Performed a total of 0 changes. + +4.148. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.149. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.150. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.151. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.152. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.153. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.154. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \clk_buf_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.155. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \clk_buf_primitive_inst. +Performed a total of 0 changes. + +4.156. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.157. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.158. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.159. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.160. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.161. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.162. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \clk_buf_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.163. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \clk_buf_primitive_inst. +Performed a total of 0 changes. + +4.164. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.165. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.166. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=1, #remove=0, time=0.00 sec.] + +4.167. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.168. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.169. Printing statistics. + +=== clk_buf_primitive_inst === + + Number of wires: 6 + Number of wire bits: 6 + Number of public wires: 6 + Number of public wire bits: 6 + Number of ports: 3 + Number of port bits: 3 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $_DFF_P_ 1 + CLK_BUF 1 + I_BUF 1 + + Number of Generic REGs: 1 + +ABC-DFF iteration : 1 + +4.170. Executing ABC pass (technology mapping using ABC). + +4.170.1. Summary of detected clock domains: + 3 cells in clk=\clock_input, en={ }, arst={ }, srst={ } + + #logic partitions = 1 + +4.170.2. Extracting gate netlist of module `\clk_buf_primitive_inst' to `/input.blif'.. +Found matching posedge clock domain: \clock_input +Extracted 1 gates and 2 wires to a netlist network with 1 inputs and 1 outputs (dfl=1). + +4.170.2.1. Executing ABC. +[Time = 0.04 sec.] + +4.171. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.172. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.173. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \clk_buf_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.174. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \clk_buf_primitive_inst. +Performed a total of 0 changes. + +4.175. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.176. Executing OPT_SHARE pass. + +4.177. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.178. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. +Removed 0 unused cells and 4 unused wires. + + +4.179. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +ABC-DFF iteration : 2 + +4.180. Executing ABC pass (technology mapping using ABC). + +4.180.1. Summary of detected clock domains: + 3 cells in clk=\clock_input, en={ }, arst={ }, srst={ } + + #logic partitions = 1 + +4.180.2. Extracting gate netlist of module `\clk_buf_primitive_inst' to `/input.blif'.. +Found matching posedge clock domain: \clock_input +Extracted 1 gates and 2 wires to a netlist network with 1 inputs and 1 outputs (dfl=1). + +4.180.2.1. Executing ABC. +[Time = 0.04 sec.] + +4.181. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.182. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.183. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \clk_buf_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.184. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \clk_buf_primitive_inst. +Performed a total of 0 changes. + +4.185. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.186. Executing OPT_SHARE pass. + +4.187. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.188. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. +Removed 0 unused cells and 4 unused wires. + + +4.189. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +ABC-DFF iteration : 3 + +4.190. Executing ABC pass (technology mapping using ABC). + +4.190.1. Summary of detected clock domains: + 3 cells in clk=\clock_input, en={ }, arst={ }, srst={ } + + #logic partitions = 1 + +4.190.2. Extracting gate netlist of module `\clk_buf_primitive_inst' to `/input.blif'.. +Found matching posedge clock domain: \clock_input +Extracted 1 gates and 2 wires to a netlist network with 1 inputs and 1 outputs (dfl=2). + +4.190.2.1. Executing ABC. +[Time = 0.06 sec.] + +4.191. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.192. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.193. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \clk_buf_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.194. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \clk_buf_primitive_inst. +Performed a total of 0 changes. + +4.195. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.196. Executing OPT_SHARE pass. + +4.197. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.198. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. +Removed 0 unused cells and 4 unused wires. + + +4.199. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +ABC-DFF iteration : 4 + +4.200. Executing ABC pass (technology mapping using ABC). + +4.200.1. Summary of detected clock domains: + 3 cells in clk=\clock_input, en={ }, arst={ }, srst={ } + + #logic partitions = 1 + +4.200.2. Extracting gate netlist of module `\clk_buf_primitive_inst' to `/input.blif'.. +Found matching posedge clock domain: \clock_input +Extracted 1 gates and 2 wires to a netlist network with 1 inputs and 1 outputs (dfl=2). + +4.200.2.1. Executing ABC. +[Time = 0.06 sec.] + +4.201. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.202. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.203. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \clk_buf_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.204. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \clk_buf_primitive_inst. +Performed a total of 0 changes. + +4.205. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.206. Executing OPT_SHARE pass. + +4.207. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.208. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. +Removed 0 unused cells and 4 unused wires. + + +4.209. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 +select with DFL2 synthesis (thresh-logic=0.920000, thresh_dff=0.980000) + +4.210. Executing OPT_FFINV pass (push inverters through FFs). +Discovering LUTs. +Pushed 0 inverters. + +4.211. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.212. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.213. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \clk_buf_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.214. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \clk_buf_primitive_inst. +Performed a total of 0 changes. + +4.215. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.216. Executing OPT_SHARE pass. + +4.217. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.218. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.219. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.220. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.221. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.222. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \clk_buf_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.223. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \clk_buf_primitive_inst. +Performed a total of 0 changes. + +4.224. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.225. Executing OPT_SHARE pass. + +4.226. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.227. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.228. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.229. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.230. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.231. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \clk_buf_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.232. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \clk_buf_primitive_inst. +Performed a total of 0 changes. + +4.233. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.234. Executing OPT_SHARE pass. + +4.235. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.236. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=1, #remove=0, time=0.00 sec.] + +4.237. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.238. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.239. Executing BMUXMAP pass. + +4.240. Executing DEMUXMAP pass. + +4.241. Executing SPLITNETS pass (splitting up multi-bit signals). + +4.242. Executing ABC pass (technology mapping using ABC). + +4.242.1. Extracting gate netlist of module `\clk_buf_primitive_inst' to `/input.blif'.. +Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs (dfl=1). +Don't call ABC as there is nothing to map. + +4.243. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.244. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.245. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \clk_buf_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.246. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \clk_buf_primitive_inst. +Performed a total of 0 changes. + +4.247. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.248. Executing OPT_SHARE pass. + +4.249. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.250. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.251. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.252. Executing OPT_FFINV pass (push inverters through FFs). +Discovering LUTs. +Pushed 0 inverters. + +4.253. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.254. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.255. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \clk_buf_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.256. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \clk_buf_primitive_inst. +Performed a total of 0 changes. + +4.257. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.258. Executing OPT_SHARE pass. + +4.259. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.260. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.261. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.262. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.263. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.264. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \clk_buf_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.265. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \clk_buf_primitive_inst. +Performed a total of 0 changes. + +4.266. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.267. Executing OPT_SHARE pass. + +4.268. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.269. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=1, #remove=0, time=0.00 sec.] + +4.270. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.271. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.272. Printing statistics. + +=== clk_buf_primitive_inst === + + Number of wires: 6 + Number of wire bits: 6 + Number of public wires: 6 + Number of public wire bits: 6 + Number of ports: 3 + Number of port bits: 3 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $_DFF_P_ 1 + CLK_BUF 1 + I_BUF 1 + +4.273. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). + +4.274. Executing RS_DFFSR_CONV pass. + +4.275. Printing statistics. + +=== clk_buf_primitive_inst === + + Number of wires: 6 + Number of wire bits: 6 + Number of public wires: 6 + Number of public wire bits: 6 + Number of ports: 3 + Number of port bits: 3 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $_DFF_P_ 1 + CLK_BUF 1 + I_BUF 1 + +4.276. Executing TECHMAP pass (map to technology primitives). + +4.276.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/techmap.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu_brent_kung'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. + +4.276.2. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v' to AST representation. +Generating RTLIL representation for module `\$_DFF_P_'. +Generating RTLIL representation for module `\$_DFF_PP0_'. +Generating RTLIL representation for module `\$_DFF_PN0_'. +Generating RTLIL representation for module `\$_DFF_PP1_'. +Generating RTLIL representation for module `\$_DFF_PN1_'. +Generating RTLIL representation for module `\$_DFFE_PP_'. +Generating RTLIL representation for module `\$_DFFE_PN_'. +Generating RTLIL representation for module `\$_DFFE_PP0P_'. +Generating RTLIL representation for module `\$_DFFE_PP0N_'. +Generating RTLIL representation for module `\$_DFFE_PN0P_'. +Generating RTLIL representation for module `\$_DFFE_PN0N_'. +Generating RTLIL representation for module `\$_DFFE_PP1P_'. +Generating RTLIL representation for module `\$_DFFE_PP1N_'. +Generating RTLIL representation for module `\$_DFFE_PN1P_'. +Generating RTLIL representation for module `\$_DFFE_PN1N_'. +Generating RTLIL representation for module `\$_DFF_N_'. +Generating RTLIL representation for module `\$_DFF_NP0_'. +Generating RTLIL representation for module `\$_DFF_NN0_'. +Generating RTLIL representation for module `\$_DFF_NP1_'. +Generating RTLIL representation for module `\$_DFF_NN1_'. +Generating RTLIL representation for module `\$_DFFE_NP_'. +Generating RTLIL representation for module `\$_DFFE_NN_'. +Generating RTLIL representation for module `\$_DFFE_NP0P_'. +Generating RTLIL representation for module `\$_DFFE_NP0N_'. +Generating RTLIL representation for module `\$_DFFE_NN0P_'. +Generating RTLIL representation for module `\$_DFFE_NN0N_'. +Generating RTLIL representation for module `\$_DFFE_NP1P_'. +Generating RTLIL representation for module `\$_DFFE_NP1N_'. +Generating RTLIL representation for module `\$_DFFE_NN1P_'. +Generating RTLIL representation for module `\$_DFFE_NN1N_'. +Generating RTLIL representation for module `\$__SHREG_DFF_P_'. +Generating RTLIL representation for module `\$_SDFF_PP0_'. +Generating RTLIL representation for module `\$_SDFF_PN0_'. +Generating RTLIL representation for module `\$_SDFF_NP0_'. +Generating RTLIL representation for module `\$_SDFF_NN0_'. +Generating RTLIL representation for module `\$_SDFF_PP1_'. +Generating RTLIL representation for module `\$_SDFF_PN1_'. +Generating RTLIL representation for module `\$_SDFF_NP1_'. +Generating RTLIL representation for module `\$_SDFF_NN1_'. +Generating RTLIL representation for module `\$_DLATCH_P_'. +Generating RTLIL representation for module `\$_DLATCH_N_'. +Generating RTLIL representation for module `\$_DLATCH_PP0_'. +Generating RTLIL representation for module `\$_DLATCH_PN0_'. +Generating RTLIL representation for module `\$_DLATCH_NP0_'. +Generating RTLIL representation for module `\$_DLATCH_NN0_'. +Generating RTLIL representation for module `\$_DLATCH_PP1_'. +Generating RTLIL representation for module `\$_DLATCH_PN1_'. +Generating RTLIL representation for module `\$_DLATCH_NP1_'. +Generating RTLIL representation for module `\$_DLATCH_NN1_'. +Successfully finished Verilog frontend. + +4.276.3. Continuing TECHMAP pass. +No more expansions possible. + + +4.277. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.278. Executing SIMPLEMAP pass (map simple cells to gate primitives). + +4.279. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.280. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.281. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=0, #solve=0, #remove=0, time=0.00 sec.] + +4.282. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. +Removed 0 unused cells and 3 unused wires. + + +4.283. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.284. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.285. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \clk_buf_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.286. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \clk_buf_primitive_inst. +Performed a total of 0 changes. + +4.287. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.288. Executing OPT_SHARE pass. + +4.289. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=0, #solve=0, #remove=0, time=0.00 sec.] + +4.290. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.291. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.292. Executing TECHMAP pass (map to technology primitives). + +4.292.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/techmap.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu_brent_kung'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. + +4.292.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.293. Executing ABC pass (technology mapping using ABC). + +4.293.1. Extracting gate netlist of module `\clk_buf_primitive_inst' to `/input.blif'.. +Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs (dfl=1). +Don't call ABC as there is nothing to map. + +4.294. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.295. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.296. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \clk_buf_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.297. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \clk_buf_primitive_inst. +Performed a total of 0 changes. + +4.298. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.299. Executing OPT_SHARE pass. + +4.300. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=0, #solve=0, #remove=0, time=0.00 sec.] + +4.301. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.302. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.303. Executing HIERARCHY pass (managing design hierarchy). + +4.303.1. Analyzing design hierarchy.. +Top module: \clk_buf_primitive_inst + +4.303.2. Analyzing design hierarchy.. +Top module: \clk_buf_primitive_inst +Removed 0 unused modules. + +4.304. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.305. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v +Parsing SystemVerilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v' to AST representation. +Generating RTLIL representation for module `\rs__CLK_BUF'. +Generating RTLIL representation for module `\rs__I_BUF'. +Generating RTLIL representation for module `\rs__O_BUF'. +Generating RTLIL representation for module `\rs__IO_BUF'. +Generating RTLIL representation for module `\rs__O_BUFT'. +Successfully finished Verilog frontend. + +4.306. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v +Parsing SystemVerilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v' to AST representation. +Replacing existing blackbox module `\BOOT_CLOCK' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:9.1-14.10. +Generating RTLIL representation for module `\BOOT_CLOCK'. +Replacing existing blackbox module `\CARRY' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:24.1-31.10. +Generating RTLIL representation for module `\CARRY'. +Replacing existing blackbox module `\CLK_BUF' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:41.1-46.10. +Generating RTLIL representation for module `\CLK_BUF'. +Replacing existing blackbox module `\DFFNRE' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:56.1-64.10. +Generating RTLIL representation for module `\DFFNRE'. +Replacing existing blackbox module `\DFFRE' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:74.1-82.10. +Generating RTLIL representation for module `\DFFRE'. +Replacing existing blackbox module `\DLY_SEL_DCODER' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:92.1-118.10. +Generating RTLIL representation for module `\DLY_SEL_DCODER'. +Replacing existing blackbox module `\DLY_SEL_DECODER' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:128.1-154.10. +Generating RTLIL representation for module `\DLY_SEL_DECODER'. +Replacing existing blackbox module `\DLY_VALUE_MUX' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:164.1-188.10. +Generating RTLIL representation for module `\DLY_VALUE_MUX'. +Replacing existing blackbox module `\DSP19X2' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:198.1-232.10. +Generating RTLIL representation for module `\DSP19X2'. +Replacing existing blackbox module `\DSP38' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:242.1-268.10. +Generating RTLIL representation for module `\DSP38'. +Replacing existing blackbox module `\FCLK_BUF' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:278.1-282.10. +Generating RTLIL representation for module `\FCLK_BUF'. +Replacing existing blackbox module `\FIFO18KX2' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:292.1-339.10. +Generating RTLIL representation for module `\FIFO18KX2'. +Replacing existing blackbox module `\FIFO36K' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:349.1-374.10. +Generating RTLIL representation for module `\FIFO36K'. +Replacing existing blackbox module `\I_BUF_DS' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:384.1-396.10. +Generating RTLIL representation for module `\I_BUF_DS'. +Replacing existing blackbox module `\I_BUF' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:406.1-415.10. +Generating RTLIL representation for module `\I_BUF'. +Replacing existing blackbox module `\I_DDR' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:425.1-433.10. +Generating RTLIL representation for module `\I_DDR'. +Replacing existing blackbox module `\I_DELAY' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:443.1-455.10. +Generating RTLIL representation for module `\I_DELAY'. +Replacing existing blackbox module `\I_FAB' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:465.1-469.10. +Generating RTLIL representation for module `\I_FAB'. +Replacing existing blackbox module `\I_SERDES' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:479.1-498.10. +Generating RTLIL representation for module `\I_SERDES'. +Replacing existing blackbox module `\LATCHNR' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:508.1-514.10. +Generating RTLIL representation for module `\LATCHNR'. +Replacing existing blackbox module `\LATCHNS' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:524.1-530.10. +Generating RTLIL representation for module `\LATCHNS'. +Replacing existing blackbox module `\LATCHN' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:540.1-545.10. +Generating RTLIL representation for module `\LATCHN'. +Replacing existing blackbox module `\LATCHR' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:555.1-561.10. +Generating RTLIL representation for module `\LATCHR'. +Replacing existing blackbox module `\LATCHS' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:571.1-577.10. +Generating RTLIL representation for module `\LATCHS'. +Replacing existing blackbox module `\LATCH' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:587.1-592.10. +Generating RTLIL representation for module `\LATCH'. +Replacing existing blackbox module `\LUT1' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:602.1-608.10. +Generating RTLIL representation for module `\LUT1'. +Replacing existing blackbox module `\LUT2' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:618.1-624.10. +Generating RTLIL representation for module `\LUT2'. +Replacing existing blackbox module `\LUT3' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:634.1-640.10. +Generating RTLIL representation for module `\LUT3'. +Replacing existing blackbox module `\LUT4' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:650.1-656.10. +Generating RTLIL representation for module `\LUT4'. +Replacing existing blackbox module `\LUT5' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:666.1-672.10. +Generating RTLIL representation for module `\LUT5'. +Replacing existing blackbox module `\LUT6' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:682.1-688.10. +Generating RTLIL representation for module `\LUT6'. +Replacing existing blackbox module `\MIPI_RX' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:698.1-724.10. +Generating RTLIL representation for module `\MIPI_RX'. +Replacing existing blackbox module `\MIPI_TX' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:734.1-761.10. +Generating RTLIL representation for module `\MIPI_TX'. +Replacing existing blackbox module `\O_BUF_DS' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:771.1-783.10. +Generating RTLIL representation for module `\O_BUF_DS'. +Replacing existing blackbox module `\O_BUFT_DS' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:793.1-805.10. +Generating RTLIL representation for module `\O_BUFT_DS'. +Replacing existing blackbox module `\O_BUFT' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:815.1-826.10. +Generating RTLIL representation for module `\O_BUFT'. +Replacing existing blackbox module `\O_BUF' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:836.1-847.10. +Generating RTLIL representation for module `\O_BUF'. +Replacing existing blackbox module `\O_DDR' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:857.1-865.10. +Generating RTLIL representation for module `\O_DDR'. +Replacing existing blackbox module `\O_DELAY' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:875.1-887.10. +Generating RTLIL representation for module `\O_DELAY'. +Replacing existing blackbox module `\O_FAB' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:897.1-901.10. +Generating RTLIL representation for module `\O_FAB'. +Replacing existing blackbox module `\O_SERDES_CLK' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:911.1-920.10. +Generating RTLIL representation for module `\O_SERDES_CLK'. +Replacing existing blackbox module `\O_SERDES' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:930.1-947.10. +Generating RTLIL representation for module `\O_SERDES'. +Replacing existing blackbox module `\PLL' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:957.1-975.10. +Generating RTLIL representation for module `\PLL'. +Replacing existing blackbox module `\SOC_FPGA_INTF_AHB_M' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:985.1-999.10. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AHB_M'. +Replacing existing blackbox module `\SOC_FPGA_INTF_AHB_S' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1009.1-1026.10. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AHB_S'. +Replacing existing blackbox module `\SOC_FPGA_INTF_AXI_M0' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1036.1-1075.10. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AXI_M0'. +Replacing existing blackbox module `\SOC_FPGA_INTF_AXI_M1' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1085.1-1124.10. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AXI_M1'. +Replacing existing blackbox module `\SOC_FPGA_INTF_DMA' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1134.1-1140.10. +Generating RTLIL representation for module `\SOC_FPGA_INTF_DMA'. +Replacing existing blackbox module `\SOC_FPGA_INTF_IRQ' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1150.1-1156.10. +Generating RTLIL representation for module `\SOC_FPGA_INTF_IRQ'. +Replacing existing blackbox module `\SOC_FPGA_INTF_JTAG' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1166.1-1174.10. +Generating RTLIL representation for module `\SOC_FPGA_INTF_JTAG'. +Replacing existing blackbox module `\SOC_FPGA_TEMPERATURE' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1184.1-1192.10. +Generating RTLIL representation for module `\SOC_FPGA_TEMPERATURE'. +Replacing existing blackbox module `\TDP_RAM18KX2' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1202.1-1257.10. +Generating RTLIL representation for module `\TDP_RAM18KX2'. +Replacing existing blackbox module `\TDP_RAM36K' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1267.1-1296.10. +Generating RTLIL representation for module `\TDP_RAM36K'. +Successfully finished Verilog frontend. + ********************************* + Removing Input/Output Buffers + ********************************* + +4.307. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + *************************** + Inserting Input Buffers + *************************** +WARNING: port '\clock_input' has no associated I_BUF +WARNING: port '\ibuf_enable' has no associated I_BUF + *************************** + Inserting Clock Buffers + *************************** + ***************************** + Inserting Output Buffers + ***************************** +WARNING: OUTPUT port '\clock_output' has no associated O_BUF + ***************************** + Mapping Tri-state Buffers + ***************************** + +4.308. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. +Removed 0 unused cells and 1 unused wires. + + +4.309. Executing TECHMAP pass (map to technology primitives). + +4.309.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v' to AST representation. +Generating RTLIL representation for module `\rs__CLK_BUF'. +Generating RTLIL representation for module `\rs__I_BUF'. +Generating RTLIL representation for module `\rs__O_BUF'. +Generating RTLIL representation for module `\rs__O_BUFT'. +Successfully finished Verilog frontend. + +4.309.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.310. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. +Removed 0 unused cells and 9 unused wires. + + +4.311. Printing statistics. + +=== clk_buf_primitive_inst === + + Number of wires: 8 + Number of wire bits: 8 + Number of public wires: 6 + Number of public wire bits: 6 + Number of ports: 3 + Number of port bits: 3 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 5 + CLK_BUF 1 + DFFRE 1 + I_BUF 2 + O_BUF 1 + +4.312. Executing TECHMAP pass (map to technology primitives). + +4.312.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v' to AST representation. +Generating RTLIL representation for module `\$lut'. +Successfully finished Verilog frontend. + +4.312.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.313. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.314. Printing statistics. + +=== clk_buf_primitive_inst === + + Number of wires: 8 + Number of wire bits: 8 + Number of public wires: 6 + Number of public wire bits: 6 + Number of ports: 3 + Number of port bits: 3 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 5 + CLK_BUF 1 + DFFRE 1 + I_BUF 2 + O_BUF 1 + + ***************************** + Rewire_Obuft + ***************************** + +========================== +Post Design clean up ... + +Split to bits ... + +4.315. Executing SPLITNETS pass (splitting up multi-bit signals). + +Split into bits ... [0.00 sec.] +Building Sig2cells ... [0.00 sec.] +Building Sig2sig ... [0.00 sec.] +Backward clean up ... [0.00 sec.] +Before cleanup : + +4.316. Printing statistics. + +=== clk_buf_primitive_inst === + + Number of wires: 8 + Number of wire bits: 8 + Number of public wires: 6 + Number of public wire bits: 6 + Number of ports: 3 + Number of port bits: 3 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 5 + CLK_BUF 1 + DFFRE 1 + I_BUF 2 + O_BUFT 1 + + -------------------------- + Removed assigns : 1 + Removed wires : 1 + Removed cells : 0 + -------------------------- +After cleanup : + +4.317. Printing statistics. + +=== clk_buf_primitive_inst === + + Number of wires: 7 + Number of wire bits: 7 + Number of public wires: 6 + Number of public wire bits: 6 + Number of ports: 3 + Number of port bits: 3 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 5 + CLK_BUF 1 + DFFRE 1 + I_BUF 2 + O_BUFT 1 + + +Total time for 'obs_clean' ... + [0.00 sec.] + +4.318. Executing SPLITNETS pass (splitting up multi-bit signals). + +4.319. Executing HIERARCHY pass (managing design hierarchy). + +4.319.1. Analyzing design hierarchy.. +Top module: \clk_buf_primitive_inst + +4.319.2. Analyzing design hierarchy.. +Top module: \clk_buf_primitive_inst +Removed 0 unused modules. + +Dumping port properties into 'netlist_info.json' file. + +Inserting I_FAB/O_FAB cells ... + + +Inserting I_FAB/O_FAB cells done. + +4.320. Printing statistics. + +=== clk_buf_primitive_inst === + + Number of wires: 8 + Number of wire bits: 8 + Number of public wires: 6 + Number of public wire bits: 6 + Number of ports: 3 + Number of port bits: 3 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 6 + CLK_BUF 1 + DFFRE 1 + I_BUF 2 + O_BUFT 1 + O_FAB 1 + + Number of LUTs: 0 + Number of REGs: 1 + Number of CARRY ADDERs: 0 + +4.321. Executing Verilog backend. +Dumping module `\clk_buf_primitive_inst'. + +# -------------------- +# Core Synthesis done +# -------------------- + +4.322. Executing Verilog backend. +Dumping module `\clk_buf_primitive_inst'. + +4.322.1. Executing BLIF backend. +Extracting primitives + +-- Running command `write_rtlil design.rtlil' -- + +4.322.2. Executing RTLIL backend. +Output filename: design.rtlil +Running SplitNets + +4.322.3. Executing SPLITNETS pass (splitting up multi-bit signals). +Gathering Wires Data +Adding wires between directly connected input and output primitives +Upgrading fabric wires to ports +Handling I_BUF->Fabric->CLK_BUF +Handling Dangling outs +Deleting primitive cells and extra wires +Deleting non-primitive cells and upgrading wires to ports in interface module +Handling I_BUF->Fabric->CLK_BUF in interface module +Removing extra wires from interface module +Cleaning fabric netlist +Removing cells from wrapper module +Instantiating fabric and interface modules +Removing extra wires from wrapper module +Fixing wrapper ports +Flattening wrapper module + +4.322.4. Executing FLATTEN pass (flatten design). +Deleting now unused module interface_clk_buf_primitive_inst. + +Removing extra assigns from wrapper module + +4.322.5. Executing Verilog backend. +Dumping module `\clk_buf_primitive_inst'. + +4.322.5.1. Executing BLIF backend. + +4.322.5.2. Executing Verilog backend. +Dumping module `\clk_buf_primitive_inst'. + +4.322.5.2.1. Executing BLIF backend. +Dumping config.json +Updating sdc + +4.322.5.2.2. Executing Verilog backend. +Dumping module `\fabric_clk_buf_primitive_inst'. + +4.322.5.2.2.1. Executing BLIF backend. + +Warnings: 1 unique messages, 1 total +End of script. Logfile hash: 6e65b550f6, CPU: user 0.42s system 0.05s, MEM: 29.48 MB peak +Yosys 0.44 (git sha1 7a4a3768c, g++ 11.2.1 -fPIC -O3) +Time spent: 32% 43x read_verilog (0 sec), 28% 6x abc (0 sec), ... diff --git a/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/synthesis/wrapper_clk_buf_primitive_inst_post_synth.eblif b/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/synthesis/wrapper_clk_buf_primitive_inst_post_synth.eblif new file mode 100644 index 00000000..a957da01 --- /dev/null +++ b/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/synthesis/wrapper_clk_buf_primitive_inst_post_synth.eblif @@ -0,0 +1,17 @@ +# Generated by Yosys 0.44 (git sha1 7a4a3768c, g++ 11.2.1 -fPIC -O3) + +.model clk_buf_primitive_inst +.inputs clock_input ibuf_enable +.outputs clock_output +.names $false +.names $true +1 +.names $undef +.subckt CLK_BUF I=wire2 O=wire1 +.subckt I_BUF EN=$auto_416 I=clock_input O=wire2 +.param WEAK_KEEPER "NONE" +.subckt I_BUF EN=$auto_417 I=ibuf_enable O=$ibuf_ibuf_enable +.param WEAK_KEEPER "NONE" +.subckt O_BUFT I=$f2g_tx_out_wire_out_clk O=clock_output T=$auto_418 +.subckt fabric_clk_buf_primitive_inst $auto_416=$auto_416 $auto_417=$auto_417 $auto_418=$auto_418 $f2g_tx_out_wire_out_clk=$f2g_tx_out_wire_out_clk $ibuf_ibuf_enable=$ibuf_ibuf_enable wire1=wire1 wire2=wire2 +.end diff --git a/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/synthesis/wrapper_clk_buf_primitive_inst_post_synth.v b/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/synthesis/wrapper_clk_buf_primitive_inst_post_synth.v new file mode 100644 index 00000000..9c9037be --- /dev/null +++ b/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/synthesis/wrapper_clk_buf_primitive_inst_post_synth.v @@ -0,0 +1,99 @@ +/* Generated by Yosys 0.44 (git sha1 7a4a3768c, g++ 11.2.1 -fPIC -O3) */ + +module clk_buf_primitive_inst(clock_input, ibuf_enable, clock_output); + input clock_input; + output clock_output; + input ibuf_enable; + wire \$auto_416 ; + wire \$auto_417 ; + wire \$auto_418 ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:2.9-2.20" *) + wire \$auto_420.clock_input ; + (* init = 1'h0 *) + (* keep = 32'sd1 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:4.10-4.22" *) + wire \$auto_420.clock_output ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:3.9-3.20" *) + wire \$auto_420.ibuf_enable ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:7.6-7.11" *) + wire \$auto_420.wire1 ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:7.13-7.18" *) + wire \$auto_420.wire2 ; + (* init = 1'h0 *) + (* keep = 32'sd1 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:8.5-8.17" *) + wire \$f2g_tx_out_wire_out_clk ; + wire \$flatten$auto_420.$auto_416 ; + wire \$flatten$auto_420.$auto_417 ; + wire \$flatten$auto_420.$auto_418 ; + (* init = 1'h0 *) + (* keep = 32'sd1 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:8.5-8.17" *) + wire \$flatten$auto_420.$f2g_tx_out_wire_out_clk ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:3.9-3.20" *) + (* unused_bits = "0" *) + wire \$flatten$auto_420.$ibuf_ibuf_enable ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:3.9-3.20" *) + (* unused_bits = "0" *) + wire \$ibuf_ibuf_enable ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:2.9-2.20" *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:2.9-2.20" *) + wire clock_input; + (* init = 1'h0 *) + (* keep = 32'sd1 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:4.10-4.22" *) + (* init = 1'h0 *) + (* keep = 32'sd1 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:4.10-4.22" *) + wire clock_output; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:3.9-3.20" *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:3.9-3.20" *) + wire ibuf_enable; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:7.6-7.11" *) + wire wire1; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:7.13-7.18" *) + wire wire2; + (* module_not_derived = 32'sd1 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:21.11-24.4" *) + CLK_BUF \$auto_420.clk_buf_inst ( + .I(wire2), + .O(wire1) + ); + (* keep = 32'sd1 *) + (* module_not_derived = 32'sd1 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$flatten$auto_420.$ibuf$clk_buf_primitive_inst.$ibuf_clock_input ( + .EN(\$auto_416 ), + .I(clock_input), + .O(wire2) + ); + (* keep = 32'sd1 *) + (* module_not_derived = 32'sd1 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$flatten$auto_420.$ibuf$clk_buf_primitive_inst.$ibuf_ibuf_enable ( + .EN(\$auto_417 ), + .I(ibuf_enable), + .O(\$ibuf_ibuf_enable ) + ); + (* keep = 32'sd1 *) + (* module_not_derived = 32'sd1 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) + O_BUFT \$flatten$auto_420.$obuf$clk_buf_primitive_inst.$obuf_clock_output ( + .I(\$f2g_tx_out_wire_out_clk ), + .O(clock_output), + .T(\$auto_418 ) + ); + fabric_clk_buf_primitive_inst fabric_instance ( + .\$auto_416 (\$auto_416 ), + .\$auto_417 (\$auto_417 ), + .\$auto_418 (\$auto_418 ), + .\$f2g_tx_out_wire_out_clk (\$f2g_tx_out_wire_out_clk ), + .\$ibuf_ibuf_enable (\$ibuf_ibuf_enable ), + .wire1(wire1), + .wire2(wire2) + ); +endmodule diff --git a/EDA-3304/raptor.log b/EDA-3304/raptor.log new file mode 100644 index 00000000..241a03d8 --- /dev/null +++ b/EDA-3304/raptor.log @@ -0,0 +1,2633 @@ +/******************************************************************************* +Copyright (c) 2022-2024 Rapid Silicon +This source code contains proprietary information belonging to Rapid Silicon +(the "licensor") released under license and non-disclosure agreement to the +recipient (the "licensee"). + +The information shared and protected by the license and non-disclosure agreement +includes but is not limited to the following: +* operational algorithms of the product +* logos, graphics, source code, and visual presentation of the product +* confidential operational information of the licensor + +The recipient of this source code is NOT permitted to publicly disclose, +re-use, archive beyond the period of the license agreement, transfer to a +sub-licensee, or re-implement any portion of the content covered by the license +and non-disclosure agreement without the prior written consent of the licensor. +*********************************************************************************/ + +Version : 2024.10 +Build : 1.2.18 +Hash : 82370d4 +Date : Oct 12 2024 +Type : Engineering +Log Time : Mon Oct 14 05:17:32 2024 GMT + +INFO: Created design: clk_buf_primitive_inst. Project type: rtl +INFO: Target device: 1VG28 +INFO: Device version: v1.6.244 +INFO: Adding VERILOG_2001 /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v +INFO: ANL: ################################################## +INFO: ANL: Analysis for design: clk_buf_primitive_inst +INFO: ANL: ################################################## +INFO: ANL: Analyze command: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/yosys -s /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/clk_buf_primitive_inst/run_1/synth_1_1/analysis/clk_buf_primitive_inst_analyzer.cmd +Command: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/yosys -s /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/clk_buf_primitive_inst/run_1/synth_1_1/analysis/clk_buf_primitive_inst_analyzer.cmd + + /----------------------------------------------------------------------------\ + | yosys -- Yosys Open SYnthesis Suite | + | Copyright (C) 2012 - 2024 Claire Xenia Wolf | + | Distributed under an ISC-like license, type "license" to see terms | + \----------------------------------------------------------------------------/ + + Yosys 0.44 (git sha1 7a4a3768c, g++ 11.2.1 -fPIC -O3) + +-- Executing script file `/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/clk_buf_primitive_inst/run_1/synth_1_1/analysis/clk_buf_primitive_inst_analyzer.cmd' -- + +1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v +Parsing SystemVerilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v' to AST representation. +Generating RTLIL representation for module `\BOOT_CLOCK'. +Generating RTLIL representation for module `\CARRY'. +Generating RTLIL representation for module `\CLK_BUF'. +Generating RTLIL representation for module `\DFFNRE'. +Generating RTLIL representation for module `\DFFRE'. +Generating RTLIL representation for module `\DLY_SEL_DCODER'. +Generating RTLIL representation for module `\DLY_SEL_DECODER'. +Generating RTLIL representation for module `\DLY_VALUE_MUX'. +Generating RTLIL representation for module `\DSP19X2'. +Generating RTLIL representation for module `\DSP38'. +Generating RTLIL representation for module `\FCLK_BUF'. +Generating RTLIL representation for module `\FIFO18KX2'. +Generating RTLIL representation for module `\FIFO36K'. +Generating RTLIL representation for module `\I_BUF_DS'. +Generating RTLIL representation for module `\I_BUF'. +Generating RTLIL representation for module `\I_DDR'. +Generating RTLIL representation for module `\I_DELAY'. +Generating RTLIL representation for module `\I_FAB'. +Generating RTLIL representation for module `\I_SERDES'. +Generating RTLIL representation for module `\LATCHNR'. +Generating RTLIL representation for module `\LATCHNS'. +Generating RTLIL representation for module `\LATCHN'. +Generating RTLIL representation for module `\LATCHR'. +Generating RTLIL representation for module `\LATCHS'. +Generating RTLIL representation for module `\LATCH'. +Generating RTLIL representation for module `\LUT1'. +Generating RTLIL representation for module `\LUT2'. +Generating RTLIL representation for module `\LUT3'. +Generating RTLIL representation for module `\LUT4'. +Generating RTLIL representation for module `\LUT5'. +Generating RTLIL representation for module `\LUT6'. +Generating RTLIL representation for module `\MIPI_RX'. +Generating RTLIL representation for module `\MIPI_TX'. +Generating RTLIL representation for module `\O_BUF_DS'. +Generating RTLIL representation for module `\O_BUFT_DS'. +Generating RTLIL representation for module `\O_BUFT'. +Generating RTLIL representation for module `\O_BUF'. +Generating RTLIL representation for module `\O_DDR'. +Generating RTLIL representation for module `\O_DELAY'. +Generating RTLIL representation for module `\O_FAB'. +Generating RTLIL representation for module `\O_SERDES_CLK'. +Generating RTLIL representation for module `\O_SERDES'. +Generating RTLIL representation for module `\PLL'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AHB_M'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AHB_S'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AXI_M0'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AXI_M1'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_DMA'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_IRQ'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_JTAG'. +Generating RTLIL representation for module `\SOC_FPGA_TEMPERATURE'. +Generating RTLIL representation for module `\TDP_RAM18KX2'. +Generating RTLIL representation for module `\TDP_RAM36K'. +Successfully finished Verilog frontend. + +2. Executing Verilog-2005 frontend: /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v +Parsing Verilog input from `/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v' to AST representation. +Generating RTLIL representation for module `\clk_buf_primitive_inst'. +Successfully finished Verilog frontend. + +-- Running command `hierarchy -top clk_buf_primitive_inst' -- + +3. Executing HIERARCHY pass (managing design hierarchy). + +3.1. Analyzing design hierarchy.. +Top module: \clk_buf_primitive_inst + +3.2. Analyzing design hierarchy.. +Top module: \clk_buf_primitive_inst +Removed 0 unused modules. + +Dumping file hier_info.json ... + Process module "CLK_BUF" + Process module "I_BUF" +Dumping file port_info.json ... + +End of script. Logfile hash: 835a24a3cc, CPU: user 0.02s system 0.01s, MEM: 15.87 MB peak +Yosys 0.44 (git sha1 7a4a3768c, g++ 11.2.1 -fPIC -O3) +Time spent: 94% 4x read_verilog (0 sec), 4% 1x analyze (0 sec), ... +INFO: ANL: Design clk_buf_primitive_inst is analyzed +INFO: ANL: Top Modules: clk_buf_primitive_inst + +INFO: SYN: ################################################## +INFO: SYN: Synthesis for design: clk_buf_primitive_inst +INFO: SYN: ################################################## +INFO: SYN: RS Synthesis +INFO: SYN: Synthesis command: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/yosys -s clk_buf_primitive_inst.ys -l clk_buf_primitive_inst_synth.log +Command: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/yosys -s clk_buf_primitive_inst.ys -l clk_buf_primitive_inst_synth.log + + /----------------------------------------------------------------------------\ + | yosys -- Yosys Open SYnthesis Suite | + | Copyright (C) 2012 - 2024 Claire Xenia Wolf | + | Distributed under an ISC-like license, type "license" to see terms | + \----------------------------------------------------------------------------/ + + Yosys 0.44 (git sha1 7a4a3768c, g++ 11.2.1 -fPIC -O3) + +-- Executing script file `clk_buf_primitive_inst.ys' -- + +1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v +Parsing SystemVerilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v' to AST representation. +Generating RTLIL representation for module `\BOOT_CLOCK'. +Generating RTLIL representation for module `\CARRY'. +Generating RTLIL representation for module `\CLK_BUF'. +Generating RTLIL representation for module `\DFFNRE'. +Generating RTLIL representation for module `\DFFRE'. +Generating RTLIL representation for module `\DLY_SEL_DCODER'. +Generating RTLIL representation for module `\DLY_SEL_DECODER'. +Generating RTLIL representation for module `\DLY_VALUE_MUX'. +Generating RTLIL representation for module `\DSP19X2'. +Generating RTLIL representation for module `\DSP38'. +Generating RTLIL representation for module `\FCLK_BUF'. +Generating RTLIL representation for module `\FIFO18KX2'. +Generating RTLIL representation for module `\FIFO36K'. +Generating RTLIL representation for module `\I_BUF_DS'. +Generating RTLIL representation for module `\I_BUF'. +Generating RTLIL representation for module `\I_DDR'. +Generating RTLIL representation for module `\I_DELAY'. +Generating RTLIL representation for module `\I_FAB'. +Generating RTLIL representation for module `\I_SERDES'. +Generating RTLIL representation for module `\LATCHNR'. +Generating RTLIL representation for module `\LATCHNS'. +Generating RTLIL representation for module `\LATCHN'. +Generating RTLIL representation for module `\LATCHR'. +Generating RTLIL representation for module `\LATCHS'. +Generating RTLIL representation for module `\LATCH'. +Generating RTLIL representation for module `\LUT1'. +Generating RTLIL representation for module `\LUT2'. +Generating RTLIL representation for module `\LUT3'. +Generating RTLIL representation for module `\LUT4'. +Generating RTLIL representation for module `\LUT5'. +Generating RTLIL representation for module `\LUT6'. +Generating RTLIL representation for module `\MIPI_RX'. +Generating RTLIL representation for module `\MIPI_TX'. +Generating RTLIL representation for module `\O_BUF_DS'. +Generating RTLIL representation for module `\O_BUFT_DS'. +Generating RTLIL representation for module `\O_BUFT'. +Generating RTLIL representation for module `\O_BUF'. +Generating RTLIL representation for module `\O_DDR'. +Generating RTLIL representation for module `\O_DELAY'. +Generating RTLIL representation for module `\O_FAB'. +Generating RTLIL representation for module `\O_SERDES_CLK'. +Generating RTLIL representation for module `\O_SERDES'. +Generating RTLIL representation for module `\PLL'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AHB_M'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AHB_S'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AXI_M0'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AXI_M1'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_DMA'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_IRQ'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_JTAG'. +Generating RTLIL representation for module `\SOC_FPGA_TEMPERATURE'. +Generating RTLIL representation for module `\TDP_RAM18KX2'. +Generating RTLIL representation for module `\TDP_RAM36K'. +Successfully finished Verilog frontend. + +2. Executing Verilog-2005 frontend: /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v +Parsing Verilog input from `/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v' to AST representation. +Generating RTLIL representation for module `\clk_buf_primitive_inst'. +Successfully finished Verilog frontend. + +3. Executing HIERARCHY pass (managing design hierarchy). + +3.1. Analyzing design hierarchy.. +Top module: \clk_buf_primitive_inst + +3.2. Analyzing design hierarchy.. +Top module: \clk_buf_primitive_inst +Removed 0 unused modules. + +4. Executing synth_rs pass: v0.4.218 + +4.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/common/cells_sim.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/common/cells_sim.v' to AST representation. +Generating RTLIL representation for module `\inv'. +Generating RTLIL representation for module `\buff'. +Generating RTLIL representation for module `\logic_0'. +Generating RTLIL representation for module `\logic_1'. +Generating RTLIL representation for module `\gclkbuff'. +Successfully finished Verilog frontend. + +4.2. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CARRY.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CARRY.v' to AST representation. +Replacing existing blackbox module `\CARRY' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CARRY.v:10.1-33.10. +Generating RTLIL representation for module `\CARRY'. +Successfully finished Verilog frontend. + +4.3. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v' to AST representation. +Replacing existing blackbox module `\LATCH' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:20.1-34.10. +Generating RTLIL representation for module `\LATCH'. +Replacing existing blackbox module `\LATCHN' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:48.1-62.10. +Generating RTLIL representation for module `\LATCHN'. +Replacing existing blackbox module `\LATCHR' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:81.1-97.10. +Generating RTLIL representation for module `\LATCHR'. +Replacing existing blackbox module `\LATCHS' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:115.1-131.10. +Generating RTLIL representation for module `\LATCHS'. +Replacing existing blackbox module `\LATCHNR' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:150.1-166.10. +Generating RTLIL representation for module `\LATCHNR'. +Replacing existing blackbox module `\LATCHNS' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:184.1-200.10. +Generating RTLIL representation for module `\LATCHNS'. +Generating RTLIL representation for module `\LATCHSRE'. +Generating RTLIL representation for module `\LATCHNSRE'. +Successfully finished Verilog frontend. + +4.4. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v' to AST representation. +Replacing existing blackbox module `\DFFRE' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v:11.1-81.10. +Generating RTLIL representation for module `\DFFRE'. +Successfully finished Verilog frontend. + +4.5. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v' to AST representation. +Replacing existing blackbox module `\DFFNRE' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v:11.1-80.10. +Generating RTLIL representation for module `\DFFNRE'. +Successfully finished Verilog frontend. + +4.6. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT1.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT1.v' to AST representation. +Replacing existing blackbox module `\LUT1' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT1.v:10.1-20.10. +Generating RTLIL representation for module `\LUT1'. +Successfully finished Verilog frontend. + +4.7. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT2.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT2.v' to AST representation. +Replacing existing blackbox module `\LUT2' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT2.v:10.1-21.10. +Generating RTLIL representation for module `\LUT2'. +Successfully finished Verilog frontend. + +4.8. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT3.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT3.v' to AST representation. +Replacing existing blackbox module `\LUT3' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT3.v:10.1-22.10. +Generating RTLIL representation for module `\LUT3'. +Successfully finished Verilog frontend. + +4.9. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT4.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT4.v' to AST representation. +Replacing existing blackbox module `\LUT4' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT4.v:11.1-25.10. +Generating RTLIL representation for module `\LUT4'. +Successfully finished Verilog frontend. + +4.10. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT5.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT5.v' to AST representation. +Replacing existing blackbox module `\LUT5' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT5.v:10.1-24.10. +Generating RTLIL representation for module `\LUT5'. +Successfully finished Verilog frontend. + +4.11. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT6.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT6.v' to AST representation. +Replacing existing blackbox module `\LUT6' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT6.v:10.1-25.10. +Generating RTLIL representation for module `\LUT6'. +Successfully finished Verilog frontend. + +4.12. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CLK_BUF.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CLK_BUF.v' to AST representation. +Replacing existing blackbox module `\CLK_BUF' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CLK_BUF.v:10.1-25.10. +Generating RTLIL representation for module `\CLK_BUF'. +Successfully finished Verilog frontend. + +4.13. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_BUF.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_BUF.v' to AST representation. +Replacing existing blackbox module `\O_BUF' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_BUF.v:10.1-84.10. +Generating RTLIL representation for module `\O_BUF'. +Successfully finished Verilog frontend. + +4.14. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DSP38.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DSP38.v' to AST representation. +Replacing existing blackbox module `\DSP38' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DSP38.v:10.1-341.10. +Generating RTLIL representation for module `\DSP38'. +Successfully finished Verilog frontend. + +4.15. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v' to AST representation. +Replacing existing blackbox module `\TDP_RAM36K' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v:2.1-29.10. +Generating RTLIL representation for module `\TDP_RAM36K'. +Replacing existing blackbox module `\TDP_RAM18KX2' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v:33.1-84.10. +Generating RTLIL representation for module `\TDP_RAM18KX2'. +Generating RTLIL representation for module `\RS_DSP3'. +Replacing existing blackbox module `\DSP19X2' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v:116.1-149.10. +Generating RTLIL representation for module `\DSP19X2'. +Successfully finished Verilog frontend. + +4.16. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v' to AST representation. +Generating RTLIL representation for module `\TDP_BRAM18'. +Generating RTLIL representation for module `\BRAM2x18_TDP'. +Generating RTLIL representation for module `\BRAM2x18_SDP'. +Generating RTLIL representation for module `\_$_mem_v2_asymmetric'. +Successfully finished Verilog frontend. + +4.17. Executing HIERARCHY pass (managing design hierarchy). + +4.17.1. Analyzing design hierarchy.. +Top module: \clk_buf_primitive_inst + +4.17.2. Analyzing design hierarchy.. +Top module: \clk_buf_primitive_inst +Removed 0 unused modules. + +4.18. Executing PROC pass (convert processes to netlists). + +4.18.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +4.18.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Removed a total of 0 dead cases. + +4.18.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 0 redundant assignments. +Promoted 2 assignments to connections. + +4.18.4. Executing PROC_INIT pass (extract init attributes). +Found init rule in `\clk_buf_primitive_inst.$proc$/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:8$2'. + Set init value: \wire_out_clk = 1'0 + +4.18.5. Executing PROC_ARST pass (detect async resets in processes). + +4.18.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. + +4.18.7. Executing PROC_MUX pass (convert decision trees to multiplexers). +Creating decoders for process `\clk_buf_primitive_inst.$proc$/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:8$2'. +Creating decoders for process `\clk_buf_primitive_inst.$proc$/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:16$1'. + +4.18.8. Executing PROC_DLATCH pass (convert process syncs to latches). + +4.18.9. Executing PROC_DFF pass (convert process syncs to FFs). +Creating register for signal `\clk_buf_primitive_inst.\wire_out_clk' using process `\clk_buf_primitive_inst.$proc$/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:16$1'. + created $dff cell `$procdff$3' with positive edge clock. + +4.18.10. Executing PROC_MEMWR pass (convert process memory writes to cells). + +4.18.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Removing empty process `clk_buf_primitive_inst.$proc$/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:8$2'. +Removing empty process `clk_buf_primitive_inst.$proc$/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v:16$1'. +Cleaned up 0 empty switches. + +4.18.12. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.19. Executing FLATTEN pass (flatten design). + +# -------------------- +# Design entry stats +# -------------------- + +4.20. Printing statistics. + +=== clk_buf_primitive_inst === + + Number of wires: 8 + Number of wire bits: 8 + Number of public wires: 6 + Number of public wire bits: 6 + Number of ports: 3 + Number of port bits: 3 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $dff 1 + CLK_BUF 1 + I_BUF 1 + +4.21. Executing SPLITNETS pass (splitting up multi-bit signals). + +4.22. Executing DEMUXMAP pass. + +4.23. Executing FLATTEN pass (flatten design). + +4.24. Executing DEMUXMAP pass. + +4.25. Executing TRIBUF pass. +Warning: Ignored -no_iobuf because -keep_tribuf is used. + +4.26. Executing DEMINOUT pass (demote inout ports to input or output). + +4.27. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.28. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. +Removed 0 unused cells and 2 unused wires. + + +4.29. Executing CHECK pass (checking for obvious problems). +Checking module clk_buf_primitive_inst... +Found and reported 0 problems. + +4.30. Printing statistics. + +=== clk_buf_primitive_inst === + + Number of wires: 6 + Number of wire bits: 6 + Number of public wires: 6 + Number of public wire bits: 6 + Number of ports: 3 + Number of port bits: 3 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $dff 1 + CLK_BUF 1 + I_BUF 1 + +FF init value for cell $procdff$3 ($dff): \wire_out_clk = 1'0 + +4.31. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.32. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.33. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \clk_buf_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.34. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \clk_buf_primitive_inst. +Performed a total of 0 changes. + +4.35. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.36. Executing OPT_SHARE pass. + +4.37. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.38. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.39. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.40. Executing FSM pass (extract and optimize FSM). + +4.40.1. Executing FSM_DETECT pass (finding FSMs in design). + +4.40.2. Executing FSM_EXTRACT pass (extracting FSM from design). + +4.40.3. Executing FSM_OPT pass (simple optimizations of FSMs). + +4.40.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.40.5. Executing FSM_OPT pass (simple optimizations of FSMs). + +4.40.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). + +4.40.7. Executing FSM_INFO pass (dumping all available information on FSM cells). + +4.40.8. Executing FSM_MAP pass (mapping FSMs to basic logic). + +4.41. Executing WREDUCE pass (reducing word size of cells). + +4.42. Executing PEEPOPT pass (run peephole optimizers). + +4.43. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.44. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.45. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.46. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \clk_buf_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.47. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \clk_buf_primitive_inst. +Performed a total of 0 changes. + +4.48. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.49. Executing OPT_SHARE pass. + +4.50. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.51. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.52. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.53. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.54. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.55. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \clk_buf_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.56. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \clk_buf_primitive_inst. +Performed a total of 0 changes. + +4.57. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.58. Executing OPT_SHARE pass. + +4.59. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.60. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.61. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.62. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.63. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.64. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \clk_buf_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.65. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \clk_buf_primitive_inst. +Performed a total of 0 changes. + +4.66. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.67. Executing OPT_SHARE pass. + +4.68. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.69. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=1, #remove=0, time=0.00 sec.] + +4.70. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.71. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.72. Executing WREDUCE pass (reducing word size of cells). + +4.73. Executing PEEPOPT pass (run peephole optimizers). + +4.74. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.75. Executing DEMUXMAP pass. + +4.76. Executing SPLITNETS pass (splitting up multi-bit signals). + +4.77. Printing statistics. + +=== clk_buf_primitive_inst === + + Number of wires: 6 + Number of wire bits: 6 + Number of public wires: 6 + Number of public wire bits: 6 + Number of ports: 3 + Number of port bits: 3 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $dff 1 + CLK_BUF 1 + I_BUF 1 + +4.78. Executing RS_DSP_MULTADD pass. + +4.79. Executing WREDUCE pass (reducing word size of cells). + +4.80. Executing RS_DSP_MACC pass. + +4.81. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.82. Executing TECHMAP pass (map to technology primitives). + +4.82.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/mul2dsp_check_maxwidth.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/mul2dsp_check_maxwidth.v' to AST representation. +Generating RTLIL representation for module `\_80_mul'. +Generating RTLIL representation for module `\_90_soft_mul'. +Successfully finished Verilog frontend. + +4.82.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.83. Printing statistics. + +=== clk_buf_primitive_inst === + + Number of wires: 6 + Number of wire bits: 6 + Number of public wires: 6 + Number of public wire bits: 6 + Number of ports: 3 + Number of port bits: 3 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $dff 1 + CLK_BUF 1 + I_BUF 1 + +4.84. Executing TECHMAP pass (map to technology primitives). + +4.84.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/mul2dsp_check_maxwidth.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/mul2dsp_check_maxwidth.v' to AST representation. +Generating RTLIL representation for module `\_80_mul'. +Generating RTLIL representation for module `\_90_soft_mul'. +Successfully finished Verilog frontend. + +4.84.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.85. Printing statistics. + +=== clk_buf_primitive_inst === + + Number of wires: 6 + Number of wire bits: 6 + Number of public wires: 6 + Number of public wire bits: 6 + Number of ports: 3 + Number of port bits: 3 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $dff 1 + CLK_BUF 1 + I_BUF 1 + +4.86. Executing TECHMAP pass (map to technology primitives). + +4.86.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/mul2dsp.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/mul2dsp.v' to AST representation. +Generating RTLIL representation for module `\_80_mul'. +Generating RTLIL representation for module `\_90_soft_mul'. +Successfully finished Verilog frontend. + +4.86.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.87. Executing TECHMAP pass (map to technology primitives). + +4.87.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/mul2dsp.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/mul2dsp.v' to AST representation. +Generating RTLIL representation for module `\_80_mul'. +Generating RTLIL representation for module `\_90_soft_mul'. +Successfully finished Verilog frontend. + +4.87.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.88. Executing TECHMAP pass (map to technology primitives). + +4.88.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/dsp_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/dsp_map.v' to AST representation. +Generating RTLIL representation for module `\$__RS_MUL20X18'. +Generating RTLIL representation for module `\$__RS_MUL10X9'. +Successfully finished Verilog frontend. + +4.88.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.89. Executing RS_DSP_SIMD pass. + +4.90. Executing TECHMAP pass (map to technology primitives). + +4.90.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/dsp_final_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/dsp_final_map.v' to AST representation. +Generating RTLIL representation for module `\dsp_t1_20x18x64_cfg_ports'. +Generating RTLIL representation for module `\dsp_t1_10x9x32_cfg_params'. +Successfully finished Verilog frontend. + +4.90.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.91. Executing TECHMAP pass (map to technology primitives). + +4.91.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/dsp19x2_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/dsp19x2_map.v' to AST representation. +Generating RTLIL representation for module `\RS_DSPX2_MULTACC'. +Generating RTLIL representation for module `\RS_DSPX2_MULT'. +Generating RTLIL representation for module `\RS_DSPX2_MULT_REGIN'. +Generating RTLIL representation for module `\RS_DSPX2_MULT_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULT_REGIN_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULTADD'. +Generating RTLIL representation for module `\RS_DSPX2_MULTADD_REGIN'. +Generating RTLIL representation for module `\RS_DSPX2_MULTADD_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULTADD_REGIN_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULTACC_REGIN'. +Generating RTLIL representation for module `\RS_DSPX2_MULTACC_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULTACC_REGIN_REGOUT'. +Generating RTLIL representation for module `\RS_DSP3'. +Successfully finished Verilog frontend. + +4.91.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.92. Executing rs_pack_dsp_regs pass. + +4.93. Executing RS_DSP_IO_REGS pass. + +4.94. Executing TECHMAP pass (map to technology primitives). + +4.94.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/dsp38_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/dsp38_map.v' to AST representation. +Generating RTLIL representation for module `\RS_DSP_MULTACC'. +Generating RTLIL representation for module `\RS_DSP_MULT'. +Generating RTLIL representation for module `\RS_DSP_MULT_REGIN'. +Generating RTLIL representation for module `\RS_DSP_MULT_REGOUT'. +Generating RTLIL representation for module `\RS_DSP_MULT_REGIN_REGOUT'. +Generating RTLIL representation for module `\RS_DSP_MULTADD'. +Generating RTLIL representation for module `\RS_DSP_MULTADD_REGIN'. +Generating RTLIL representation for module `\RS_DSP_MULTADD_REGOUT'. +Generating RTLIL representation for module `\RS_DSP_MULTADD_REGIN_REGOUT'. +Generating RTLIL representation for module `\RS_DSP_MULTACC_REGIN'. +Generating RTLIL representation for module `\RS_DSP_MULTACC_REGOUT'. +Generating RTLIL representation for module `\RS_DSP_MULTACC_REGIN_REGOUT'. +Successfully finished Verilog frontend. + +4.94.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.95. Executing TECHMAP pass (map to technology primitives). + +4.95.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/dsp19x2_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/dsp19x2_map.v' to AST representation. +Generating RTLIL representation for module `\RS_DSPX2_MULTACC'. +Generating RTLIL representation for module `\RS_DSPX2_MULT'. +Generating RTLIL representation for module `\RS_DSPX2_MULT_REGIN'. +Generating RTLIL representation for module `\RS_DSPX2_MULT_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULT_REGIN_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULTADD'. +Generating RTLIL representation for module `\RS_DSPX2_MULTADD_REGIN'. +Generating RTLIL representation for module `\RS_DSPX2_MULTADD_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULTADD_REGIN_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULTACC_REGIN'. +Generating RTLIL representation for module `\RS_DSPX2_MULTACC_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULTACC_REGIN_REGOUT'. +Generating RTLIL representation for module `\RS_DSP3'. +Successfully finished Verilog frontend. + +4.95.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.96. Printing statistics. + +=== clk_buf_primitive_inst === + + Number of wires: 6 + Number of wire bits: 6 + Number of public wires: 6 + Number of public wire bits: 6 + Number of ports: 3 + Number of port bits: 3 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $dff 1 + CLK_BUF 1 + I_BUF 1 + +4.97. Executing ALUMACC pass (create $alu and $macc cells). +Extracting $alu and $macc cells in module clk_buf_primitive_inst: + created 0 $alu and 0 $macc cells. + +4.98. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.99. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.100. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \clk_buf_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.101. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \clk_buf_primitive_inst. +Performed a total of 0 changes. + +4.102. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.103. Executing OPT_SHARE pass. + +4.104. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.105. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.106. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.107. Printing statistics. + +=== clk_buf_primitive_inst === + + Number of wires: 6 + Number of wire bits: 6 + Number of public wires: 6 + Number of public wire bits: 6 + Number of ports: 3 + Number of port bits: 3 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $dff 1 + CLK_BUF 1 + I_BUF 1 + +4.108. Executing MEMORY pass. + +4.108.1. Executing OPT_MEM pass (optimize memories). +Performed a total of 0 transformations. + +4.108.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). +Performed a total of 0 transformations. + +4.108.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). + +4.108.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). + +4.108.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). + +4.108.6. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.108.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). + +4.108.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). +Performed a total of 0 transformations. + +4.108.9. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.108.10. Executing MEMORY_COLLECT pass (generating $mem cells). + +4.109. Printing statistics. + +=== clk_buf_primitive_inst === + + Number of wires: 6 + Number of wire bits: 6 + Number of public wires: 6 + Number of public wire bits: 6 + Number of ports: 3 + Number of port bits: 3 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $dff 1 + CLK_BUF 1 + I_BUF 1 + +4.110. Executing MUXPACK pass ($mux cell cascades to $pmux). +Converted 0 (p)mux cells into 0 pmux cells. + +4.111. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.112. Executing MEMORY_LIBMAP pass (mapping memories to cells). + +4.113. Executing MEMORY_LIBMAP pass (mapping memories to cells). + +4.114. Executing Rs_BRAM_Split pass. + +4.115. Executing TECHMAP pass (map to technology primitives). + +4.115.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_map_new_version.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_map_new_version.v' to AST representation. +Generating RTLIL representation for module `\$__RS_FACTOR_BRAM36_TDP'. +Generating RTLIL representation for module `\$__RS_FACTOR_BRAM18_TDP'. +Generating RTLIL representation for module `\$__RS_FACTOR_BRAM18_SDP'. +Generating RTLIL representation for module `\$__RS_FACTOR_BRAM36_SDP'. +Successfully finished Verilog frontend. + +4.115.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.116. Executing TECHMAP pass (map to technology primitives). + +4.116.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_final_map_new_version.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_final_map_new_version.v' to AST representation. +Generating RTLIL representation for module `\BRAM2x18_TDP'. +Generating RTLIL representation for module `\BRAM2x18_SDP'. +Successfully finished Verilog frontend. + +4.116.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.117. Executing DFFUNMAP pass (unmap clock enable and synchronous reset from FFs). + +4.118. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.119. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.120. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \clk_buf_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.121. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \clk_buf_primitive_inst. +Performed a total of 0 changes. + +4.122. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.123. Executing OPT_SHARE pass. + +4.124. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.125. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.126. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.127. Executing PMUXTREE pass. + +4.128. Executing MUXPACK pass ($mux cell cascades to $pmux). +Converted 0 (p)mux cells into 0 pmux cells. + +4.129. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). + +4.130. Executing TECHMAP pass (map to technology primitives). + +4.130.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/techmap.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu_brent_kung'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. + +4.130.2. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/arith_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/arith_map.v' to AST representation. +Generating RTLIL representation for module `\_80_rs_alu'. +Successfully finished Verilog frontend. + +4.130.3. Continuing TECHMAP pass. +Using extmapper simplemap for cells of type $dff. +No more expansions possible. + + +4.131. Printing statistics. + +=== clk_buf_primitive_inst === + + Number of wires: 6 + Number of wire bits: 6 + Number of public wires: 6 + Number of public wire bits: 6 + Number of ports: 3 + Number of port bits: 3 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $_DFF_P_ 1 + CLK_BUF 1 + I_BUF 1 + +4.132. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.133. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.134. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \clk_buf_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.135. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \clk_buf_primitive_inst. +Performed a total of 0 changes. + +4.136. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.137. Executing OPT_SHARE pass. + +4.138. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.139. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.140. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.141. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.142. Executing TECHMAP pass (map to technology primitives). + +4.142.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/techmap.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu_brent_kung'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. + +4.142.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.143. Printing statistics. + +=== clk_buf_primitive_inst === + + Number of wires: 6 + Number of wire bits: 6 + Number of public wires: 6 + Number of public wire bits: 6 + Number of ports: 3 + Number of port bits: 3 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $_DFF_P_ 1 + CLK_BUF 1 + I_BUF 1 + +4.144. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.145. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.146. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \clk_buf_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.147. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \clk_buf_primitive_inst. +Performed a total of 0 changes. + +4.148. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.149. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.150. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.151. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.152. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.153. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.154. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \clk_buf_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.155. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \clk_buf_primitive_inst. +Performed a total of 0 changes. + +4.156. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.157. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.158. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.159. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.160. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.161. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.162. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \clk_buf_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.163. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \clk_buf_primitive_inst. +Performed a total of 0 changes. + +4.164. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.165. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.166. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=1, #remove=0, time=0.00 sec.] + +4.167. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.168. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.169. Printing statistics. + +=== clk_buf_primitive_inst === + + Number of wires: 6 + Number of wire bits: 6 + Number of public wires: 6 + Number of public wire bits: 6 + Number of ports: 3 + Number of port bits: 3 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $_DFF_P_ 1 + CLK_BUF 1 + I_BUF 1 + + Number of Generic REGs: 1 + +ABC-DFF iteration : 1 + +4.170. Executing ABC pass (technology mapping using ABC). + +4.170.1. Summary of detected clock domains: + 3 cells in clk=\wire1, en={ }, arst={ }, srst={ } + + #logic partitions = 1 + +4.170.2. Extracting gate netlist of module `\clk_buf_primitive_inst' to `/input.blif'.. +Found matching posedge clock domain: \wire1 +Extracted 1 gates and 2 wires to a netlist network with 1 inputs and 1 outputs (dfl=1). + +4.170.2.1. Executing ABC. +[Time = 0.04 sec.] + +4.171. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.172. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.173. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \clk_buf_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.174. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \clk_buf_primitive_inst. +Performed a total of 0 changes. + +4.175. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.176. Executing OPT_SHARE pass. + +4.177. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.178. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. +Removed 0 unused cells and 4 unused wires. + + +4.179. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +ABC-DFF iteration : 2 + +4.180. Executing ABC pass (technology mapping using ABC). + +4.180.1. Summary of detected clock domains: + 3 cells in clk=\wire1, en={ }, arst={ }, srst={ } + + #logic partitions = 1 + +4.180.2. Extracting gate netlist of module `\clk_buf_primitive_inst' to `/input.blif'.. +Found matching posedge clock domain: \wire1 +Extracted 1 gates and 2 wires to a netlist network with 1 inputs and 1 outputs (dfl=1). + +4.180.2.1. Executing ABC. +[Time = 0.04 sec.] + +4.181. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.182. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.183. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \clk_buf_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.184. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \clk_buf_primitive_inst. +Performed a total of 0 changes. + +4.185. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.186. Executing OPT_SHARE pass. + +4.187. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.188. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. +Removed 0 unused cells and 4 unused wires. + + +4.189. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +ABC-DFF iteration : 3 + +4.190. Executing ABC pass (technology mapping using ABC). + +4.190.1. Summary of detected clock domains: + 3 cells in clk=\wire1, en={ }, arst={ }, srst={ } + + #logic partitions = 1 + +4.190.2. Extracting gate netlist of module `\clk_buf_primitive_inst' to `/input.blif'.. +Found matching posedge clock domain: \wire1 +Extracted 1 gates and 2 wires to a netlist network with 1 inputs and 1 outputs (dfl=2). + +4.190.2.1. Executing ABC. +[Time = 0.06 sec.] + +4.191. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.192. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.193. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \clk_buf_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.194. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \clk_buf_primitive_inst. +Performed a total of 0 changes. + +4.195. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.196. Executing OPT_SHARE pass. + +4.197. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.198. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. +Removed 0 unused cells and 4 unused wires. + + +4.199. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +ABC-DFF iteration : 4 + +4.200. Executing ABC pass (technology mapping using ABC). + +4.200.1. Summary of detected clock domains: + 3 cells in clk=\wire1, en={ }, arst={ }, srst={ } + + #logic partitions = 1 + +4.200.2. Extracting gate netlist of module `\clk_buf_primitive_inst' to `/input.blif'.. +Found matching posedge clock domain: \wire1 +Extracted 1 gates and 2 wires to a netlist network with 1 inputs and 1 outputs (dfl=2). + +4.200.2.1. Executing ABC. +[Time = 0.06 sec.] + +4.201. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.202. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.203. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \clk_buf_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.204. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \clk_buf_primitive_inst. +Performed a total of 0 changes. + +4.205. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.206. Executing OPT_SHARE pass. + +4.207. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.208. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. +Removed 0 unused cells and 4 unused wires. + + +4.209. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 +select with DFL2 synthesis (thresh-logic=0.920000, thresh_dff=0.980000) + +4.210. Executing OPT_FFINV pass (push inverters through FFs). +Discovering LUTs. +Pushed 0 inverters. + +4.211. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.212. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.213. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \clk_buf_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.214. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \clk_buf_primitive_inst. +Performed a total of 0 changes. + +4.215. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.216. Executing OPT_SHARE pass. + +4.217. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.218. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.219. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.220. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.221. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.222. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \clk_buf_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.223. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \clk_buf_primitive_inst. +Performed a total of 0 changes. + +4.224. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.225. Executing OPT_SHARE pass. + +4.226. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.227. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.228. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.229. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.230. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.231. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \clk_buf_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.232. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \clk_buf_primitive_inst. +Performed a total of 0 changes. + +4.233. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.234. Executing OPT_SHARE pass. + +4.235. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.236. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=1, #remove=0, time=0.00 sec.] + +4.237. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.238. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.239. Executing BMUXMAP pass. + +4.240. Executing DEMUXMAP pass. + +4.241. Executing SPLITNETS pass (splitting up multi-bit signals). + +4.242. Executing ABC pass (technology mapping using ABC). + +4.242.1. Extracting gate netlist of module `\clk_buf_primitive_inst' to `/input.blif'.. +Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs (dfl=1). +Don't call ABC as there is nothing to map. + +4.243. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.244. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.245. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \clk_buf_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.246. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \clk_buf_primitive_inst. +Performed a total of 0 changes. + +4.247. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.248. Executing OPT_SHARE pass. + +4.249. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.250. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.251. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.252. Executing OPT_FFINV pass (push inverters through FFs). +Discovering LUTs. +Pushed 0 inverters. + +4.253. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.254. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.255. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \clk_buf_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.256. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \clk_buf_primitive_inst. +Performed a total of 0 changes. + +4.257. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.258. Executing OPT_SHARE pass. + +4.259. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.260. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.261. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.262. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.263. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.264. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \clk_buf_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.265. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \clk_buf_primitive_inst. +Performed a total of 0 changes. + +4.266. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.267. Executing OPT_SHARE pass. + +4.268. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.269. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=1, #remove=0, time=0.00 sec.] + +4.270. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.271. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.272. Printing statistics. + +=== clk_buf_primitive_inst === + + Number of wires: 6 + Number of wire bits: 6 + Number of public wires: 6 + Number of public wire bits: 6 + Number of ports: 3 + Number of port bits: 3 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $_DFF_P_ 1 + CLK_BUF 1 + I_BUF 1 + +4.273. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). + +4.274. Executing RS_DFFSR_CONV pass. + +4.275. Printing statistics. + +=== clk_buf_primitive_inst === + + Number of wires: 6 + Number of wire bits: 6 + Number of public wires: 6 + Number of public wire bits: 6 + Number of ports: 3 + Number of port bits: 3 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $_DFF_P_ 1 + CLK_BUF 1 + I_BUF 1 + +4.276. Executing TECHMAP pass (map to technology primitives). + +4.276.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/techmap.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu_brent_kung'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. + +4.276.2. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v' to AST representation. +Generating RTLIL representation for module `\$_DFF_P_'. +Generating RTLIL representation for module `\$_DFF_PP0_'. +Generating RTLIL representation for module `\$_DFF_PN0_'. +Generating RTLIL representation for module `\$_DFF_PP1_'. +Generating RTLIL representation for module `\$_DFF_PN1_'. +Generating RTLIL representation for module `\$_DFFE_PP_'. +Generating RTLIL representation for module `\$_DFFE_PN_'. +Generating RTLIL representation for module `\$_DFFE_PP0P_'. +Generating RTLIL representation for module `\$_DFFE_PP0N_'. +Generating RTLIL representation for module `\$_DFFE_PN0P_'. +Generating RTLIL representation for module `\$_DFFE_PN0N_'. +Generating RTLIL representation for module `\$_DFFE_PP1P_'. +Generating RTLIL representation for module `\$_DFFE_PP1N_'. +Generating RTLIL representation for module `\$_DFFE_PN1P_'. +Generating RTLIL representation for module `\$_DFFE_PN1N_'. +Generating RTLIL representation for module `\$_DFF_N_'. +Generating RTLIL representation for module `\$_DFF_NP0_'. +Generating RTLIL representation for module `\$_DFF_NN0_'. +Generating RTLIL representation for module `\$_DFF_NP1_'. +Generating RTLIL representation for module `\$_DFF_NN1_'. +Generating RTLIL representation for module `\$_DFFE_NP_'. +Generating RTLIL representation for module `\$_DFFE_NN_'. +Generating RTLIL representation for module `\$_DFFE_NP0P_'. +Generating RTLIL representation for module `\$_DFFE_NP0N_'. +Generating RTLIL representation for module `\$_DFFE_NN0P_'. +Generating RTLIL representation for module `\$_DFFE_NN0N_'. +Generating RTLIL representation for module `\$_DFFE_NP1P_'. +Generating RTLIL representation for module `\$_DFFE_NP1N_'. +Generating RTLIL representation for module `\$_DFFE_NN1P_'. +Generating RTLIL representation for module `\$_DFFE_NN1N_'. +Generating RTLIL representation for module `\$__SHREG_DFF_P_'. +Generating RTLIL representation for module `\$_SDFF_PP0_'. +Generating RTLIL representation for module `\$_SDFF_PN0_'. +Generating RTLIL representation for module `\$_SDFF_NP0_'. +Generating RTLIL representation for module `\$_SDFF_NN0_'. +Generating RTLIL representation for module `\$_SDFF_PP1_'. +Generating RTLIL representation for module `\$_SDFF_PN1_'. +Generating RTLIL representation for module `\$_SDFF_NP1_'. +Generating RTLIL representation for module `\$_SDFF_NN1_'. +Generating RTLIL representation for module `\$_DLATCH_P_'. +Generating RTLIL representation for module `\$_DLATCH_N_'. +Generating RTLIL representation for module `\$_DLATCH_PP0_'. +Generating RTLIL representation for module `\$_DLATCH_PN0_'. +Generating RTLIL representation for module `\$_DLATCH_NP0_'. +Generating RTLIL representation for module `\$_DLATCH_NN0_'. +Generating RTLIL representation for module `\$_DLATCH_PP1_'. +Generating RTLIL representation for module `\$_DLATCH_PN1_'. +Generating RTLIL representation for module `\$_DLATCH_NP1_'. +Generating RTLIL representation for module `\$_DLATCH_NN1_'. +Successfully finished Verilog frontend. + +4.276.3. Continuing TECHMAP pass. +No more expansions possible. + + +4.277. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.278. Executing SIMPLEMAP pass (map simple cells to gate primitives). + +4.279. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.280. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.281. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=0, #solve=0, #remove=0, time=0.00 sec.] + +4.282. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. +Removed 0 unused cells and 3 unused wires. + + +4.283. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.284. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.285. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \clk_buf_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.286. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \clk_buf_primitive_inst. +Performed a total of 0 changes. + +4.287. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.288. Executing OPT_SHARE pass. + +4.289. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=0, #solve=0, #remove=0, time=0.00 sec.] + +4.290. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.291. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.292. Executing TECHMAP pass (map to technology primitives). + +4.292.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/techmap.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu_brent_kung'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. + +4.292.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.293. Executing ABC pass (technology mapping using ABC). + +4.293.1. Extracting gate netlist of module `\clk_buf_primitive_inst' to `/input.blif'.. +Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs (dfl=1). +Don't call ABC as there is nothing to map. + +4.294. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +4.295. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.296. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \clk_buf_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.297. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \clk_buf_primitive_inst. +Performed a total of 0 changes. + +4.298. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\clk_buf_primitive_inst'. +Removed a total of 0 cells. + +4.299. Executing OPT_SHARE pass. + +4.300. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=0, #solve=0, #remove=0, time=0.00 sec.] + +4.301. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.302. Executing OPT_EXPR pass (perform const folding). +Optimizing module clk_buf_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.303. Executing HIERARCHY pass (managing design hierarchy). + +4.303.1. Analyzing design hierarchy.. +Top module: \clk_buf_primitive_inst + +4.303.2. Analyzing design hierarchy.. +Top module: \clk_buf_primitive_inst +Removed 0 unused modules. + +4.304. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.305. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v +Parsing SystemVerilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v' to AST representation. +Generating RTLIL representation for module `\rs__CLK_BUF'. +Generating RTLIL representation for module `\rs__I_BUF'. +Generating RTLIL representation for module `\rs__O_BUF'. +Generating RTLIL representation for module `\rs__IO_BUF'. +Generating RTLIL representation for module `\rs__O_BUFT'. +Successfully finished Verilog frontend. + +4.306. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v +Parsing SystemVerilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v' to AST representation. +Replacing existing blackbox module `\BOOT_CLOCK' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:9.1-14.10. +Generating RTLIL representation for module `\BOOT_CLOCK'. +Replacing existing blackbox module `\CARRY' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:24.1-31.10. +Generating RTLIL representation for module `\CARRY'. +Replacing existing blackbox module `\CLK_BUF' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:41.1-46.10. +Generating RTLIL representation for module `\CLK_BUF'. +Replacing existing blackbox module `\DFFNRE' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:56.1-64.10. +Generating RTLIL representation for module `\DFFNRE'. +Replacing existing blackbox module `\DFFRE' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:74.1-82.10. +Generating RTLIL representation for module `\DFFRE'. +Replacing existing blackbox module `\DLY_SEL_DCODER' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:92.1-118.10. +Generating RTLIL representation for module `\DLY_SEL_DCODER'. +Replacing existing blackbox module `\DLY_SEL_DECODER' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:128.1-154.10. +Generating RTLIL representation for module `\DLY_SEL_DECODER'. +Replacing existing blackbox module `\DLY_VALUE_MUX' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:164.1-188.10. +Generating RTLIL representation for module `\DLY_VALUE_MUX'. +Replacing existing blackbox module `\DSP19X2' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:198.1-232.10. +Generating RTLIL representation for module `\DSP19X2'. +Replacing existing blackbox module `\DSP38' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:242.1-268.10. +Generating RTLIL representation for module `\DSP38'. +Replacing existing blackbox module `\FCLK_BUF' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:278.1-282.10. +Generating RTLIL representation for module `\FCLK_BUF'. +Replacing existing blackbox module `\FIFO18KX2' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:292.1-339.10. +Generating RTLIL representation for module `\FIFO18KX2'. +Replacing existing blackbox module `\FIFO36K' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:349.1-374.10. +Generating RTLIL representation for module `\FIFO36K'. +Replacing existing blackbox module `\I_BUF_DS' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:384.1-396.10. +Generating RTLIL representation for module `\I_BUF_DS'. +Replacing existing blackbox module `\I_BUF' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:406.1-415.10. +Generating RTLIL representation for module `\I_BUF'. +Replacing existing blackbox module `\I_DDR' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:425.1-433.10. +Generating RTLIL representation for module `\I_DDR'. +Replacing existing blackbox module `\I_DELAY' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:443.1-455.10. +Generating RTLIL representation for module `\I_DELAY'. +Replacing existing blackbox module `\I_FAB' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:465.1-469.10. +Generating RTLIL representation for module `\I_FAB'. +Replacing existing blackbox module `\I_SERDES' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:479.1-498.10. +Generating RTLIL representation for module `\I_SERDES'. +Replacing existing blackbox module `\LATCHNR' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:508.1-514.10. +Generating RTLIL representation for module `\LATCHNR'. +Replacing existing blackbox module `\LATCHNS' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:524.1-530.10. +Generating RTLIL representation for module `\LATCHNS'. +Replacing existing blackbox module `\LATCHN' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:540.1-545.10. +Generating RTLIL representation for module `\LATCHN'. +Replacing existing blackbox module `\LATCHR' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:555.1-561.10. +Generating RTLIL representation for module `\LATCHR'. +Replacing existing blackbox module `\LATCHS' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:571.1-577.10. +Generating RTLIL representation for module `\LATCHS'. +Replacing existing blackbox module `\LATCH' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:587.1-592.10. +Generating RTLIL representation for module `\LATCH'. +Replacing existing blackbox module `\LUT1' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:602.1-608.10. +Generating RTLIL representation for module `\LUT1'. +Replacing existing blackbox module `\LUT2' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:618.1-624.10. +Generating RTLIL representation for module `\LUT2'. +Replacing existing blackbox module `\LUT3' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:634.1-640.10. +Generating RTLIL representation for module `\LUT3'. +Replacing existing blackbox module `\LUT4' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:650.1-656.10. +Generating RTLIL representation for module `\LUT4'. +Replacing existing blackbox module `\LUT5' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:666.1-672.10. +Generating RTLIL representation for module `\LUT5'. +Replacing existing blackbox module `\LUT6' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:682.1-688.10. +Generating RTLIL representation for module `\LUT6'. +Replacing existing blackbox module `\MIPI_RX' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:698.1-724.10. +Generating RTLIL representation for module `\MIPI_RX'. +Replacing existing blackbox module `\MIPI_TX' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:734.1-761.10. +Generating RTLIL representation for module `\MIPI_TX'. +Replacing existing blackbox module `\O_BUF_DS' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:771.1-783.10. +Generating RTLIL representation for module `\O_BUF_DS'. +Replacing existing blackbox module `\O_BUFT_DS' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:793.1-805.10. +Generating RTLIL representation for module `\O_BUFT_DS'. +Replacing existing blackbox module `\O_BUFT' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:815.1-826.10. +Generating RTLIL representation for module `\O_BUFT'. +Replacing existing blackbox module `\O_BUF' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:836.1-847.10. +Generating RTLIL representation for module `\O_BUF'. +Replacing existing blackbox module `\O_DDR' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:857.1-865.10. +Generating RTLIL representation for module `\O_DDR'. +Replacing existing blackbox module `\O_DELAY' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:875.1-887.10. +Generating RTLIL representation for module `\O_DELAY'. +Replacing existing blackbox module `\O_FAB' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:897.1-901.10. +Generating RTLIL representation for module `\O_FAB'. +Replacing existing blackbox module `\O_SERDES_CLK' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:911.1-920.10. +Generating RTLIL representation for module `\O_SERDES_CLK'. +Replacing existing blackbox module `\O_SERDES' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:930.1-947.10. +Generating RTLIL representation for module `\O_SERDES'. +Replacing existing blackbox module `\PLL' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:957.1-975.10. +Generating RTLIL representation for module `\PLL'. +Replacing existing blackbox module `\SOC_FPGA_INTF_AHB_M' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:985.1-999.10. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AHB_M'. +Replacing existing blackbox module `\SOC_FPGA_INTF_AHB_S' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1009.1-1026.10. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AHB_S'. +Replacing existing blackbox module `\SOC_FPGA_INTF_AXI_M0' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1036.1-1075.10. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AXI_M0'. +Replacing existing blackbox module `\SOC_FPGA_INTF_AXI_M1' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1085.1-1124.10. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AXI_M1'. +Replacing existing blackbox module `\SOC_FPGA_INTF_DMA' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1134.1-1140.10. +Generating RTLIL representation for module `\SOC_FPGA_INTF_DMA'. +Replacing existing blackbox module `\SOC_FPGA_INTF_IRQ' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1150.1-1156.10. +Generating RTLIL representation for module `\SOC_FPGA_INTF_IRQ'. +Replacing existing blackbox module `\SOC_FPGA_INTF_JTAG' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1166.1-1174.10. +Generating RTLIL representation for module `\SOC_FPGA_INTF_JTAG'. +Replacing existing blackbox module `\SOC_FPGA_TEMPERATURE' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1184.1-1192.10. +Generating RTLIL representation for module `\SOC_FPGA_TEMPERATURE'. +Replacing existing blackbox module `\TDP_RAM18KX2' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1202.1-1257.10. +Generating RTLIL representation for module `\TDP_RAM18KX2'. +Replacing existing blackbox module `\TDP_RAM36K' at /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1267.1-1296.10. +Generating RTLIL representation for module `\TDP_RAM36K'. +Successfully finished Verilog frontend. + ********************************* + Removing Input/Output Buffers + ********************************* + +4.307. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + *************************** + Inserting Input Buffers + *************************** +WARNING: port '\clock_input' has no associated I_BUF +WARNING: port '\ibuf_enable' has no associated I_BUF + *************************** + Inserting Clock Buffers + *************************** + ***************************** + Inserting Output Buffers + ***************************** +WARNING: OUTPUT port '\clock_output' has no associated O_BUF + ***************************** + Mapping Tri-state Buffers + ***************************** + +4.308. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. +Removed 0 unused cells and 1 unused wires. + + +4.309. Executing TECHMAP pass (map to technology primitives). + +4.309.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v' to AST representation. +Generating RTLIL representation for module `\rs__CLK_BUF'. +Generating RTLIL representation for module `\rs__I_BUF'. +Generating RTLIL representation for module `\rs__O_BUF'. +Generating RTLIL representation for module `\rs__O_BUFT'. +Successfully finished Verilog frontend. + +4.309.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.310. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. +Removed 0 unused cells and 9 unused wires. + + +4.311. Printing statistics. + +=== clk_buf_primitive_inst === + + Number of wires: 8 + Number of wire bits: 8 + Number of public wires: 6 + Number of public wire bits: 6 + Number of ports: 3 + Number of port bits: 3 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 5 + CLK_BUF 1 + DFFRE 1 + I_BUF 2 + O_BUF 1 + +4.312. Executing TECHMAP pass (map to technology primitives). + +4.312.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v' to AST representation. +Generating RTLIL representation for module `\$lut'. +Successfully finished Verilog frontend. + +4.312.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.313. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \clk_buf_primitive_inst.. + +4.314. Printing statistics. + +=== clk_buf_primitive_inst === + + Number of wires: 8 + Number of wire bits: 8 + Number of public wires: 6 + Number of public wire bits: 6 + Number of ports: 3 + Number of port bits: 3 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 5 + CLK_BUF 1 + DFFRE 1 + I_BUF 2 + O_BUF 1 + + ***************************** + Rewire_Obuft + ***************************** + +========================== +Post Design clean up ... + +Split to bits ... + +4.315. Executing SPLITNETS pass (splitting up multi-bit signals). + +Split into bits ... [0.00 sec.] +Building Sig2cells ... [0.00 sec.] +Building Sig2sig ... [0.00 sec.] +Backward clean up ... [0.00 sec.] +Before cleanup : + +4.316. Printing statistics. + +=== clk_buf_primitive_inst === + + Number of wires: 8 + Number of wire bits: 8 + Number of public wires: 6 + Number of public wire bits: 6 + Number of ports: 3 + Number of port bits: 3 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 5 + CLK_BUF 1 + DFFRE 1 + I_BUF 2 + O_BUFT 1 + + -------------------------- + Removed assigns : 1 + Removed wires : 1 + Removed cells : 0 + -------------------------- +After cleanup : + +4.317. Printing statistics. + +=== clk_buf_primitive_inst === + + Number of wires: 7 + Number of wire bits: 7 + Number of public wires: 6 + Number of public wire bits: 6 + Number of ports: 3 + Number of port bits: 3 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 5 + CLK_BUF 1 + DFFRE 1 + I_BUF 2 + O_BUFT 1 + + +Total time for 'obs_clean' ... + [0.00 sec.] + +4.318. Executing SPLITNETS pass (splitting up multi-bit signals). + +4.319. Executing HIERARCHY pass (managing design hierarchy). + +4.319.1. Analyzing design hierarchy.. +Top module: \clk_buf_primitive_inst + +4.319.2. Analyzing design hierarchy.. +Top module: \clk_buf_primitive_inst +Removed 0 unused modules. + +Dumping port properties into 'netlist_info.json' file. + +Inserting I_FAB/O_FAB cells ... + + +Inserting I_FAB/O_FAB cells done. + +4.320. Printing statistics. + +=== clk_buf_primitive_inst === + + Number of wires: 8 + Number of wire bits: 8 + Number of public wires: 6 + Number of public wire bits: 6 + Number of ports: 3 + Number of port bits: 3 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 6 + CLK_BUF 1 + DFFRE 1 + I_BUF 2 + O_BUFT 1 + O_FAB 1 + + Number of LUTs: 0 + Number of REGs: 1 + Number of CARRY ADDERs: 0 + +4.321. Executing Verilog backend. +Dumping module `\clk_buf_primitive_inst'. + +# -------------------- +# Core Synthesis done +# -------------------- + +4.322. Executing Verilog backend. +Dumping module `\clk_buf_primitive_inst'. + +4.322.1. Executing BLIF backend. +Extracting primitives + +-- Running command `write_rtlil design.rtlil' -- + +4.322.2. Executing RTLIL backend. +Output filename: design.rtlil +[0.0189764 sec.] +Running SplitNets + +4.322.3. Executing SPLITNETS pass (splitting up multi-bit signals). +[6.4915e-05 sec.] +Gathering Wires Data +[9.1016e-05 sec.] +Adding wires between directly connected input and output primitives +[2.1329e-05 sec.] +Upgrading fabric wires to ports +[1.9761e-05 sec.] +Handling I_BUF->Fabric->CLK_BUF +[1.4244e-05 sec.] +Handling Dangling outs +[2.5637e-05 sec.] +Deleting primitive cells and extra wires +[3.5652e-05 sec.] +Deleting non-primitive cells and upgrading wires to ports in interface module +[1.993e-05 sec.] +Handling I_BUF->Fabric->CLK_BUF in interface module +[1.3599e-05 sec.] +Removing extra wires from interface module +[8.217e-06 sec.] +Cleaning fabric netlist +[0.000934178 sec.] +Removing cells from wrapper module +[2.7855e-05 sec.] +Instantiating fabric and interface modules +[3.9412e-05 sec.] +Removing extra wires from wrapper module +[1.2695e-05 sec.] +Fixing wrapper ports +[7.078e-06 sec.] +Flattening wrapper module + +4.322.4. Executing FLATTEN pass (flatten design). +Deleting now unused module interface_clk_buf_primitive_inst. + +[0.00014896 sec.] +Removing extra assigns from wrapper module +[3.0769e-05 sec.] + +4.322.5. Executing Verilog backend. +Dumping module `\clk_buf_primitive_inst'. + +4.322.5.1. Executing BLIF backend. +Run Script + +4.322.5.2. Executing Verilog backend. +Dumping module `\clk_buf_primitive_inst'. + +4.322.5.2.1. Executing BLIF backend. +Dumping config.json +[0.00330591 sec.] +Updating sdc +[0.0105099 sec.] +Time elapsed in design editing : [0.0569561 sec.] + +4.322.5.2.2. Executing Verilog backend. +Dumping module `\fabric_clk_buf_primitive_inst'. + +4.322.5.2.2.1. Executing BLIF backend. + +Warnings: 1 unique messages, 1 total +End of script. Logfile hash: 6e65b550f6, CPU: user 0.42s system 0.05s, MEM: 29.48 MB peak +Yosys 0.44 (git sha1 7a4a3768c, g++ 11.2.1 -fPIC -O3) +Time spent: 32% 43x read_verilog (0 sec), 28% 6x abc (0 sec), ... +INFO: SYN: Design clk_buf_primitive_inst is synthesized +INFO: Setting up the LEC Simulation +INFO: Adding SV_2012 /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./sim/co_sim_tb/co_sim_clk_buf_primitive_inst.v +INFO: Adding SV_2012 /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v +INFO: Modifying clk_buf_primitive_inst/run_1/synth_1_1/synthesis/clk_buf_primitive_inst_post_synth.v +INFO: Modification completed. +INFO: Modifying clk_buf_primitive_inst/run_1/synth_1_1/synthesis/post_pnr_wrapper_clk_buf_primitive_inst_post_synth.v +INFO: Modification completed. +INFO: SGT: ################################################## +INFO: SGT: Gate simulation for design: clk_buf_primitive_inst +INFO: SGT: ################################################## +Command: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/HDL_simulator/iverilog/bin/iverilog -DIVERILOG=1 -v -DGATE_SIM=1 -s co_sim_clk_buf_primitive_inst -I../../../.././rtl -I/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl -I/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./sim/co_sim_tb -g2012 /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./sim/co_sim_tb/co_sim_clk_buf_primitive_inst.v /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/clk_buf_primitive_inst/run_1/synth_1_1/synthesis/clk_buf_primitive_inst_post_synth.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/simlib.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/brams_sim.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/llatches_sim.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DSP19X2.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/SOC_FPGA_INTF_AXI_M0.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/FCLK_BUF.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/PLL.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_BUFT_DS.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT5.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT4.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/I_BUF_DS.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/MIPI_TX.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/SOC_FPGA_INTF_AXI_M1.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/I_FAB.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/I_DDR.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/SOC_FPGA_INTF_DMA.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_DELAY.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_BUF_DS.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT6.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DSP38.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/I_BUF.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DLY_VALUE_MUX.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/MIPI_RX.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DLY_SEL_DCODER.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/TDP_RAM18KX2.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/SOC_FPGA_INTF_IRQ.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_DDR.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/SOC_FPGA_INTF_AHB_S.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/I_SERDES.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_FAB.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_SERDES_CLK.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/TDP_RAM36K.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/I_DELAY.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT3.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT2.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_BUF.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/SOC_FPGA_INTF_AHB_M.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DLY_SEL_DECODER.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/FIFO18KX2.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/BOOT_CLOCK.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/FIFO36K.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT1.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CLK_BUF.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/SOC_FPGA_TEMPERATURE.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/SOC_FPGA_INTF_JTAG.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_SERDES.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CARRY.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_BUFT.v +Icarus Verilog Preprocessor version 13.0 (devel) (s20221226-498-g52d049b51) + +Copyright (c) 1999-2024 Stephen Williams (steve@icarus.com) + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +Using language generation: IEEE1800-2012,no-specify,no-interconnect,xtypes,icarus-misc +PARSING INPUT +/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v:64: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v:65: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v:66: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v:67: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v:68: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v:69: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v:70: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v:71: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v:73: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v:74: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v:75: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v:76: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v:64: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v:65: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v:66: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v:67: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v:68: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v:69: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v:70: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v:71: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v:73: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v:74: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v:75: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v:76: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v:77: warning: Timing checks are not supported. + ... done, ELABORATING DESIGN +0.02 seconds. +RUNNING FUNCTORS + ... Iteration detected 3 optimizations. + ... Iteration detected 0 optimizations. + ... Look for dangling constants + ... done + ... done, 0 seconds. + -F cprop ... + -F nodangle ... + ... scan for dangling signal and event nodes. (scomplete=F, ecomplete=F) + ... 1 iterations deleted 24 dangling signals and 0 events. + ... scan for dangling signal and event nodes. (scomplete=T, ecomplete=F) + ... 2 iterations deleted 24 dangling signals and 3 events. + ... done +CALCULATING ISLANDS + ... done, 0 seconds. +CODE GENERATION + ... invoking target_design + ... done, 0.01 seconds. +STATISTICS +lex_string: add_count=5198 hit_count=32063 +Icarus Verilog version 13.0 (devel) (s20221226-498-g52d049b51) + +Copyright (c) 2000-2024 Stephen Williams (steve@icarus.com) + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + +translate: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/HDL_simulator/iverilog/lib/ivl/ivlpp -v -L -F"/tmp/ivrlg2667e83e2" -f"/tmp/ivrlg667e83e2" -p"/tmp/ivrli667e83e2" |/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/HDL_simulator/iverilog/lib/ivl/ivl -v -C"/tmp/ivrlh667e83e2" -C"/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/HDL_simulator/iverilog/lib/ivl/vvp.conf" -- - +Command: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/HDL_simulator/iverilog/bin/vvp ./a.out -fst +FST info: dumpfile tb.vcd opened for output. +Data Mismatch: Actual output: 0, Netlist Output 1, Time: 20000 +Data Mismatch: Actual output: 0, Netlist Output 1, Time: 30000 +Data Mismatch: Actual output: 0, Netlist Output 1, Time: 40000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 50000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 60000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 70000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 80000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 90000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 100000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 110000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 120000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 130000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 140000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 150000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 160000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 170000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 180000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 190000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 200000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 210000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 220000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 230000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 240000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 250000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 260000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 270000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 280000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 290000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 300000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 310000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 320000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 330000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 340000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 350000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 360000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 370000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 380000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 390000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 400000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 410000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 420000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 430000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 440000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 450000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 460000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 470000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 480000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 490000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 500000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 510000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 520000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 530000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 540000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 550000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 560000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 570000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 580000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 590000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 600000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 610000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 620000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 630000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 640000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 650000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 660000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 670000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 680000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 690000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 700000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 710000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 720000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 730000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 740000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 750000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 760000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 770000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 780000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 790000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 800000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 810000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 820000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 830000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 840000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 850000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 860000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 870000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 880000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 890000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 900000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 910000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 920000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 930000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 940000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 950000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 960000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 970000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 980000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 990000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 1000000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 1010000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 1020000 +Data Matched: Actual output: 1, Netlist Output 1, Time: 1060000 +3 comparison(s) mismatched +ERROR: SIM: Simulation Failed +FATAL: /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./sim/co_sim_tb/co_sim_clk_buf_primitive_inst.v:53: + Time: 1060000 Scope: co_sim_clk_buf_primitive_inst +ERROR: SGT: Design clk_buf_primitive_inst simulation failed! + +Design clk_buf_primitive_inst simulation failed! + + while executing +"simulate gate icarus" + (file "raptor.tcl" line 9) diff --git a/EDA-3304/raptor.tcl b/EDA-3304/raptor.tcl new file mode 100644 index 00000000..ec6f00ef --- /dev/null +++ b/EDA-3304/raptor.tcl @@ -0,0 +1,16 @@ +create_design clk_buf_primitive_inst +target_device 1VG28 +add_include_path ./rtl +add_design_file ./rtl/clk_buf_primitive_inst.v +set_top_module clk_buf_primitive_inst +analyze +synthesize delay +setup_lec_sim +simulate gate icarus +packing +place +route +simulate pnr icarus +sta +power +bitstream diff --git a/EDA-3304/raptor_cmd.tcl b/EDA-3304/raptor_cmd.tcl new file mode 100644 index 00000000..4e4159d8 --- /dev/null +++ b/EDA-3304/raptor_cmd.tcl @@ -0,0 +1,23 @@ +# /******************************************************************************* +# Copyright (c) 2022-2024 Rapid Silicon +# This source code contains proprietary information belonging to Rapid Silicon +# (the "licensor") released under license and non-disclosure agreement to the +# recipient (the "licensee"). +# The information shared and protected by the license and non-disclosure agreement +# includes but is not limited to the following: +# * operational algorithms of the product +# * logos, graphics, source code, and visual presentation of the product +# * confidential operational information of the licensor +# The recipient of this source code is NOT permitted to publicly disclose, +# re-use, archive beyond the period of the license agreement, transfer to a +# sub-licensee, or re-implement any portion of the content covered by the license +# and non-disclosure agreement without the prior written consent of the licensor. +# *********************************************************************************/ +# Version : 2024.10 +# Build : 1.2.18 +# Hash : 82370d4 +# Date : Oct 12 2024 +# Type : Engineering +# Log Time : Mon Oct 14 05:17:32 2024 GMT +source /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/etc/init/sim_helpers.tcl +source /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/etc/init/flow.tcl diff --git a/EDA-3304/raptor_perf.log b/EDA-3304/raptor_perf.log new file mode 100644 index 00000000..8fc0171f --- /dev/null +++ b/EDA-3304/raptor_perf.log @@ -0,0 +1,36 @@ +/******************************************************************************* +Copyright (c) 2022-2024 Rapid Silicon +This source code contains proprietary information belonging to Rapid Silicon +(the "licensor") released under license and non-disclosure agreement to the +recipient (the "licensee"). + +The information shared and protected by the license and non-disclosure agreement +includes but is not limited to the following: +* operational algorithms of the product +* logos, graphics, source code, and visual presentation of the product +* confidential operational information of the licensor + +The recipient of this source code is NOT permitted to publicly disclose, +re-use, archive beyond the period of the license agreement, transfer to a +sub-licensee, or re-implement any portion of the content covered by the license +and non-disclosure agreement without the prior written consent of the licensor. +*********************************************************************************/ + +Version : 2024.10 +Build : 1.2.18 +Hash : 82370d4 +Date : Oct 12 2024 +Type : Engineering +Log Time : Mon Oct 14 05:17:32 2024 GMT + +[ 10:17:32 ] Analysis has started +[ 10:17:32 ] Command: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/yosys -s /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/clk_buf_primitive_inst/run_1/synth_1_1/analysis/clk_buf_primitive_inst_analyzer.cmd +[ 10:17:32 ] Duration: 57 ms. Max utilization: 53 MB +[ 10:17:32 ] Synthesize has started +[ 10:17:32 ] Command: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/yosys -s clk_buf_primitive_inst.ys -l clk_buf_primitive_inst_synth.log +[ 10:17:33 ] Duration: 780 ms. Max utilization: 77 MB +[ 10:17:33 ] Gate Simulation has started +[ 10:17:33 ] Command: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/HDL_simulator/iverilog/bin/iverilog -DIVERILOG=1 -v -DGATE_SIM=1 -s co_sim_clk_buf_primitive_inst -I../../../.././rtl -I/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl -I/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./sim/co_sim_tb -g2012 /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./sim/co_sim_tb/co_sim_clk_buf_primitive_inst.v /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/clk_buf_primitive_inst/run_1/synth_1_1/synthesis/clk_buf_primitive_inst_post_synth.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/simlib.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/brams_sim.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/llatches_sim.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DSP19X2.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/SOC_FPGA_INTF_AXI_M0.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/FCLK_BUF.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/PLL.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_BUFT_DS.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT5.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT4.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/I_BUF_DS.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/MIPI_TX.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/SOC_FPGA_INTF_AXI_M1.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/I_FAB.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/I_DDR.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/SOC_FPGA_INTF_DMA.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_DELAY.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_BUF_DS.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT6.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DSP38.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/I_BUF.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DLY_VALUE_MUX.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/MIPI_RX.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DLY_SEL_DCODER.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/TDP_RAM18KX2.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/SOC_FPGA_INTF_IRQ.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_DDR.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/SOC_FPGA_INTF_AHB_S.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/I_SERDES.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_FAB.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_SERDES_CLK.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/TDP_RAM36K.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/I_DELAY.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT3.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT2.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_BUF.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/SOC_FPGA_INTF_AHB_M.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DLY_SEL_DECODER.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/FIFO18KX2.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/BOOT_CLOCK.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/FIFO36K.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT1.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CLK_BUF.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/SOC_FPGA_TEMPERATURE.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/SOC_FPGA_INTF_JTAG.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_SERDES.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CARRY.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_BUFT.v +[ 10:17:33 ] Duration: 106 ms. Max utilization: 4 MB +[ 10:17:33 ] Command: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/HDL_simulator/iverilog/bin/vvp ./a.out -fst +[ 10:17:34 ] Duration: 45 ms. Max utilization: 163 MB diff --git a/EDA-3304/rtl/clk_buf_primitive_inst.v b/EDA-3304/rtl/clk_buf_primitive_inst.v new file mode 100644 index 00000000..8069f007 --- /dev/null +++ b/EDA-3304/rtl/clk_buf_primitive_inst.v @@ -0,0 +1,29 @@ +module clk_buf_primitive_inst ( + input clock_input, // Clock input (connect to your input signal) + input ibuf_enable, + output clock_output // Clock output +); + +wire wire1, wire2; +reg wire_out_clk=0; + +I_BUF i_buf_inst ( + .I(clock_input), + .EN(ibuf_enable), + .O(wire2) +); + +always @(posedge wire1) begin + wire_out_clk <= wire2; +end + + // Instantiate the CLK_BUF module + CLK_BUF clk_buf_inst ( + .I(wire2), + .O(wire1) + ); + +assign clock_output = wire_out_clk; + // You can also perform other logic or processing here as needed + +endmodule