added jira test-case

os-fpga · Apr 23, 2024 · 4c6347a · 4c6347a
1 parent 1daa953
commit 4c6347a
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diff --git a/EDA-2739/Virgo_Pin_Table.csv b/EDA-2739/Virgo_Pin_Table.csv
diff --git a/EDA-2739/and2_design/and2.pin b/EDA-2739/and2_design/and2.pin
@@ -0,0 +1,6 @@
+set_property mode Mode_BP_SDR_A_RX HP_2_0_0P
+set_pin_loc a HP_2_0_0P
+set_property mode Mode_BP_SDR_A_RX HP_2_2_1P
+set_pin_loc b HP_2_2_1P
+set_property mode  Mode_BP_SDR_A_TX HP_1_0_0P
+set_pin_loc c HP_1_0_0P
diff --git a/EDA-2739/and2_design/and2.v b/EDA-2739/and2_design/and2.v
@@ -0,0 +1,9 @@
+module and2(
+	input wire a,
+	input wire b,
+	output wire c
+
+);
+assign c = a & b;
+
+endmodule 
diff --git a/EDA-2739/and2_design/and2_old.pin b/EDA-2739/and2_design/and2_old.pin
@@ -0,0 +1,11 @@
+set_pin_loc c  HP_1_0_0P 	            f2g_tx_out[0]_A
+set_pin_loc a  HP_2_0_0P 			    g2f_rx_in[0]_A
+set_pin_loc b  HP_2_2_1P 			    g2f_rx_in[0]_A
+
+set_pin_loc c_oen      HP_1_0_0P 		f2g_tx_oe_A
+set_pin_loc in_oen[0]  HP_2_0_0P 	    f2g_in_en_A
+set_pin_loc in_oen[1]  HP_2_2_1P 	    f2g_in_en_A
+
+set_mode Mode_BP_DIR_A_TX HP_1_0_0P
+set_mode Mode_BP_DIR_A_RX HP_2_0_0P
+set_mode Mode_BP_DIR_A_RX HP_2_2_1P
diff --git a/EDA-2739/and2_design/and2_old.v b/EDA-2739/and2_design/and2_old.v
@@ -0,0 +1,13 @@
+module and2(
+	input wire a,
+	input wire b,
+	output wire c_oen,
+	output wire [1:0] in_oen,
+	output wire c
+
+);
+assign c = a & b;
+assign c_oen = 1'b1;
+assign in_oen = {(2){1'b1}};
+
+endmodule 
diff --git a/EDA-2739/and2_design/raptor.tcl b/EDA-2739/and2_design/raptor.tcl
@@ -0,0 +1,14 @@
+create_design and2
+target_device 1VG28
+add_design_file ./and2.v
+set_top_module and2
+add_constraint_file and2.pin
+analyze
+synthesize
+packing
+place
+route
+sta
+power
+bitstream write_xml
+
diff --git a/EDA-2739/pinMapping.csv b/EDA-2739/pinMapping.csv
diff --git a/EDA-2739/raptor.tcl b/EDA-2739/raptor.tcl