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Updated Summary for IO Configurator #288

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merged 4 commits into from
Dec 3, 2024
Merged

Updated Summary for IO Configurator #288

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234dd2e
simulation updated for io_config
moinijaz Dec 3, 2024
a44040f
summary updated in io_config for delays
moinijaz Dec 3, 2024
14afa58
updated defines for consistency
moinijaz Dec 3, 2024
9db29d5
Merge branch 'main' into io_config
bilal458 Dec 3, 2024
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29 changes: 24 additions & 5 deletions rapidsilicon/ip/io_configurator/v1_0/io_configurator_gen.py
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Original file line number Diff line number Diff line change
Expand Up @@ -3338,8 +3338,20 @@ def main():
elif (args.io_mode == "PULLDOWN"):
summary["IO_MODE"] = "Logic low in the absence of an external connection"

if (args.io_model in ["I_SERDES", "O_SERDES", "I_DDR", "O_DDR", "I_DELAY", "O_DELAY"]):
# CLOCK
if (args.io_model in ["I_SERDES", "O_SERDES", "I_DDR", "O_DDR", "IO_DELAY"]):
if (args.io_model == "IO_DELAY"):
if (args.io_type == "SINGLE_ENDED"):
summary["IO_TYPE"] = "Unidirectional data flow"
elif (args.io_type == "DIFFERENTIAL"):
summary["IO_TYPE"] = "Noise-resistant data transfer"

if (args.io_mode == "NONE"):
summary["IO_MODE"] = "No internal pull-up or pull-down resistor enabled"
elif (args.io_mode == "PULLUP"):
summary["IO_MODE"] = "Logic high in the absence of an external connection"
elif (args.io_mode == "PULLDOWN"):
summary["IO_MODE"] = "Logic low in the absence of an external connection"
# CLOCK
if (args.clocking == "RX_CLOCK"):
summary["CLOCK"] = "IOPAD provides the clock signal"
elif (args.clocking == "PLL"):
Expand Down Expand Up @@ -3384,8 +3396,15 @@ def main():
if (args.io_model == "O_SERDES"):
summary["CLOCK_FORWARDING"] = args.clock_forwarding

elif (args.io_model in ["I_DELAY", "I_DELAY_I_SERDES", "I_DELAY_I_DDR", "O_DELAY", "O_DELAY_O_SERDES", "O_DELAY_O_DDR"]):
elif (args.io_model in ["IO_DELAY"]):
summary["TAP_DELAY_VALUE"] = args.delay
if (args.direction == "UNIDIRECTIONAL"):
if (args.combination in ["I_DELAY", "I_DELAY_I_SERDES", "I_DELAY_I_DDR"]):
summary["UTILIZATION"] = str(args.num_idly) + " " + args.combination
elif (args.combination in ["O_DELAY", "O_DELAY_O_SERDES", "O_DELAY_O_DDR"]):
summary["UTILIZATION"] = str(args.num_odly) + " " + args.combination
elif (args.direction == "BIDIRECTIONAL"):
summary["UTILIZATION"] = str(args.num_dly) + " " + args.combination

# Export JSON Template (Optional) --------------------------------------------------------------
if args.json_template:
Expand Down Expand Up @@ -3470,7 +3489,7 @@ def main():

# io models defines
if (args.direction == "UNIDIRECTIONAL"):
defines.append("`define unidirectional\n")
defines.append("`define UNIDIRECTIONAL\n")
if (args.combination == "I_DELAY"):
defines.append("`define I_DELAY\n")

Expand All @@ -3490,7 +3509,7 @@ def main():
defines.append("`define O_DDR_O_DELAY\n")

elif (args.direction == "BIDIRECTIONAL"):
defines.append("`define bidirectional\n")
defines.append("`define BIDIRECTIONAL\n")
if (args.combination == "I_DELAY+O_DELAY"):
defines.append("`define I_DELAY_O_DELAY\n")

Expand Down
2 changes: 0 additions & 2 deletions rapidsilicon/ip/io_configurator/v1_0/sim/Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -2,8 +2,6 @@
#
# SPDX-License-Identifier: MIT

MODULE_NAME ?= on_chip_memory

OUT_DIR ?= $(PWD)

all:
Expand Down
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