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Add a FAISS_OPT_LEVEL=avx512_spr build mode. #2404
Add a FAISS_OPT_LEVEL=avx512_spr build mode. #2404
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- avx512_spr enables advanced avx512 instructions available since Intel(R) Sapphire Rapids. Signed-off-by: Mulugeta Mammo <mulugeta.mammo@intel.com>
Signed-off-by: Assane Diop <assane.diop@intel.com>
DEVELOPER_GUIDE.md
Outdated
# else if (system_supports_avx512) generate_avx512_binaries() | ||
# else if (system_supports_ avx2) generate_avx2_binaries() | ||
# else() generate_generic_binaries() | ||
./gradlew build -Davx2.enabled=true |
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I think we can remove this line
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You mean lines 294-298?
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no, line 298
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Removed.
@mulugetam Thanks for making these changes. Can you fix the failing CI and add CHANGELOG |
@naveentatikonda Looks like the CI is using gcc 10.5.0 (we need 12.1+). Will proceed with fixing the other issues (which are mainly formatting). |
Co-authored-by: Naveen Tatikonda <navtat@amazon.com> Signed-off-by: mulugetam <mulugeta.mammo@intel.com>
Co-authored-by: Naveen Tatikonda <navtat@amazon.com> Signed-off-by: mulugetam <mulugeta.mammo@intel.com>
Signed-off-by: Mulugeta Mammo <mulugeta.mammo@intel.com>
Signed-off-by: Mulugeta Mammo <mulugeta.mammo@intel.com>
@mulugetam also pls fix the failing unit test related to avx512_spr. Thanks! |
Signed-off-by: Mulugeta Mammo <mulugeta.mammo@intel.com>
Signed-off-by: Mulugeta Mammo <mulugeta.mammo@intel.com>
Thanks! Could you re-run CI? |
Signed-off-by: Naveen Tatikonda <navtat@amazon.com>
I tried to cherry-pick these changes and built them on Peter's custom image with GCC 12.4 without any compile-time or runtime issues when tested with some sample curl commands. |
BWC framework is flaky and the failing BWC tests not related to these changes |
Pending opensearch-project/opensearch-build#5241 to be merged and images to be pushed before new tests would take effect. |
@mulugetam can you pls share some performance benchmarking results when tested from opensearch comparing avx512_spr results with avx512 and avx2 atleast for a couple of datasets ? |
@naveentatikonda We're currently working on that and will share it when its ready. For a quick check, you may run hamming bench with |
New image is online we can retry the test on this PR. Thanks. |
90fdad4
into
opensearch-project:main
* Add avx512_spr option to FAISS_OPT_LEVEL. - avx512_spr enables advanced avx512 instructions available since Intel(R) Sapphire Rapids. Signed-off-by: Mulugeta Mammo <mulugeta.mammo@intel.com> * Fix documentation. Signed-off-by: Assane Diop <assane.diop@intel.com> * Update scripts/build.sh Co-authored-by: Naveen Tatikonda <navtat@amazon.com> Signed-off-by: mulugetam <mulugeta.mammo@intel.com> * Update scripts/build.sh Co-authored-by: Naveen Tatikonda <navtat@amazon.com> Signed-off-by: mulugetam <mulugeta.mammo@intel.com> * Fix formatting issues. Signed-off-by: Mulugeta Mammo <mulugeta.mammo@intel.com> * Update CHANGELOG.md for avx512_spr build mode. Signed-off-by: Mulugeta Mammo <mulugeta.mammo@intel.com> * Fix bugs in build options and avx512_spr flag testing. Signed-off-by: Mulugeta Mammo <mulugeta.mammo@intel.com> * Upgrade gcc version to 12.4. Signed-off-by: Mulugeta Mammo <mulugeta.mammo@intel.com> --------- Signed-off-by: Mulugeta Mammo <mulugeta.mammo@intel.com> Signed-off-by: Assane Diop <assane.diop@intel.com> Signed-off-by: mulugetam <mulugeta.mammo@intel.com> Signed-off-by: Naveen Tatikonda <navtat@amazon.com> Co-authored-by: Assane Diop <assane.diop@intel.com> Co-authored-by: Naveen Tatikonda <navtat@amazon.com> (cherry picked from commit 90fdad4)
* Add a FAISS_OPT_LEVEL=avx512_spr build mode. (#2404) * Add avx512_spr option to FAISS_OPT_LEVEL. - avx512_spr enables advanced avx512 instructions available since Intel(R) Sapphire Rapids. Signed-off-by: Mulugeta Mammo <mulugeta.mammo@intel.com> * Fix documentation. Signed-off-by: Assane Diop <assane.diop@intel.com> * Update scripts/build.sh Co-authored-by: Naveen Tatikonda <navtat@amazon.com> Signed-off-by: mulugetam <mulugeta.mammo@intel.com> * Update scripts/build.sh Co-authored-by: Naveen Tatikonda <navtat@amazon.com> Signed-off-by: mulugetam <mulugeta.mammo@intel.com> * Fix formatting issues. Signed-off-by: Mulugeta Mammo <mulugeta.mammo@intel.com> * Update CHANGELOG.md for avx512_spr build mode. Signed-off-by: Mulugeta Mammo <mulugeta.mammo@intel.com> * Fix bugs in build options and avx512_spr flag testing. Signed-off-by: Mulugeta Mammo <mulugeta.mammo@intel.com> * Upgrade gcc version to 12.4. Signed-off-by: Mulugeta Mammo <mulugeta.mammo@intel.com> --------- Signed-off-by: Mulugeta Mammo <mulugeta.mammo@intel.com> Signed-off-by: Assane Diop <assane.diop@intel.com> Signed-off-by: mulugetam <mulugeta.mammo@intel.com> Signed-off-by: Naveen Tatikonda <navtat@amazon.com> Co-authored-by: Assane Diop <assane.diop@intel.com> Co-authored-by: Naveen Tatikonda <navtat@amazon.com> (cherry picked from commit 90fdad4) * Fix failing rolling upgrade workflow Signed-off-by: Naveen Tatikonda <navtat@amazon.com> * Update init-faiss.cmake Signed-off-by: Naveen Tatikonda <navtat@amazon.com> --------- Signed-off-by: Naveen Tatikonda <navtat@amazon.com> Co-authored-by: mulugetam <mulugeta.mammo@intel.com> Co-authored-by: Naveen Tatikonda <navtat@amazon.com>
* Add avx512_spr option to FAISS_OPT_LEVEL. - avx512_spr enables advanced avx512 instructions available since Intel(R) Sapphire Rapids. Signed-off-by: Mulugeta Mammo <mulugeta.mammo@intel.com> * Fix documentation. Signed-off-by: Assane Diop <assane.diop@intel.com> * Update scripts/build.sh Co-authored-by: Naveen Tatikonda <navtat@amazon.com> Signed-off-by: mulugetam <mulugeta.mammo@intel.com> * Update scripts/build.sh Co-authored-by: Naveen Tatikonda <navtat@amazon.com> Signed-off-by: mulugetam <mulugeta.mammo@intel.com> * Fix formatting issues. Signed-off-by: Mulugeta Mammo <mulugeta.mammo@intel.com> * Update CHANGELOG.md for avx512_spr build mode. Signed-off-by: Mulugeta Mammo <mulugeta.mammo@intel.com> * Fix bugs in build options and avx512_spr flag testing. Signed-off-by: Mulugeta Mammo <mulugeta.mammo@intel.com> * Upgrade gcc version to 12.4. Signed-off-by: Mulugeta Mammo <mulugeta.mammo@intel.com> --------- Signed-off-by: Mulugeta Mammo <mulugeta.mammo@intel.com> Signed-off-by: Assane Diop <assane.diop@intel.com> Signed-off-by: mulugetam <mulugeta.mammo@intel.com> Signed-off-by: Naveen Tatikonda <navtat@amazon.com> Co-authored-by: Assane Diop <assane.diop@intel.com> Co-authored-by: Naveen Tatikonda <navtat@amazon.com>
Description
FAISS recently added a new build mode,
avx512_spr
, which enables the use of advanced AVX512 instructions available since Intel® Sapphire Rapids. These instructions includeavx512_fp16
,avx512_bf16
,avx512_vpopcntdq
, and many others. Some optimizations leveraging these instructions, such as speeding up Hamming distance evaluation for binary vectors, have already been implemented and merged. Additional optimizations are also in the pipeline. This PR enables K-NN to utilize this newavx512_spr
build mode.The code changes are implemented such that, by default, if the underlying system is an Intel® Sapphire Rapids or a newer-generation processor,
avx512_spr
binaries are generated. Otherwise, depending on the features available in the system and consistent with the existing implementation,avx512
,avx2
, orgeneric
binaries may be generated.Check List
--signoff
.By submitting this pull request, I confirm that my contribution is made under the terms of the Apache 2.0 license.
For more information on following Developer Certificate of Origin and signing off your commits, please check here.