Add a peripheral with an interrupt source

[librlib]

Hi,

I have tried to setup a shared memory on the Ariane CVA6 SoC next to the ariane_xilinx top level SV file, and would like to connect it with AXI bus and an interrupt signal (used because that memory will be a mailbox, generating an interrupt when a message is received on the shared memory). But the way the PLIC is setup is confusing: should I just take one of the unused irq_signals (above the 4 timers interrupts), or do I have to connect my memory in some way to the APB bus that goes into the PLIC ?

I am not very familiar with the peculiarities of interrupts in the RISCV ISA (especially priorities and such, which seem to be what the APB signals going into the PLIC aim to control).

Thank you for your help, ++