From 239467aaf94082cc26185d818dbeb23a84fe0d94 Mon Sep 17 00:00:00 2001 From: deepakala-k Date: Wed, 19 Feb 2025 10:23:53 -0600 Subject: [PATCH] Add P12 backend device tree --- Makefile.am | 4 +- bmc-kernel-rainiest.dts.m4 | 314 ++++++++++++++++++++++++++++++++++++ bmc-sbefifo-rainiest.dts.m4 | 297 ++++++++++++++++++++++++++++++++++ libpdbg/dtb.c | 33 +++- libpdbg/libpdbg.h | 1 + libpdbg/sbefifo.c | 4 + libpdbg/target.h | 1 + 7 files changed, 651 insertions(+), 3 deletions(-) create mode 100644 bmc-kernel-rainiest.dts.m4 create mode 100644 bmc-sbefifo-rainiest.dts.m4 diff --git a/Makefile.am b/Makefile.am index dea961b41..6328b1b95 100644 --- a/Makefile.am +++ b/Makefile.am @@ -63,8 +63,8 @@ DT = fake.dts fake-backend.dts fake2.dts fake2-backend.dts \ p8-cronus.dts cronus.dts \ p8-fsi.dts p8-i2c.dts p8-kernel.dts \ p9w-fsi.dts p9r-fsi.dts p9z-fsi.dts \ - bmc-kernel.dts bmc-kernel-rainier.dts bmc-kernel-everest.dts \ - bmc-sbefifo.dts bmc-sbefifo-rainier.dts bmc-sbefifo-everest.dts \ + bmc-kernel.dts bmc-kernel-rainier.dts bmc-kernel-rainiest.dts bmc-kernel-everest.dts \ + bmc-sbefifo.dts bmc-sbefifo-rainier.dts bmc-sbefifo-rainiest.dts bmc-sbefifo-everest.dts \ p8-host.dts p9-host.dts p10-host.dts p8.dts p9.dts p10.dts DT_sources = $(DT:.dts=.dtb.S) diff --git a/bmc-kernel-rainiest.dts.m4 b/bmc-kernel-rainiest.dts.m4 new file mode 100644 index 000000000..f96086a75 --- /dev/null +++ b/bmc-kernel-rainiest.dts.m4 @@ -0,0 +1,314 @@ +dnl +dnl PIB([addr], [index], [path-index]) +dnl +define(`PIB', +` + pib@$1 { + #address-cells = <0x2>; + #size-cells = <0x1>; + reg = <0x0 0x$1 0x7>; + compatible = "ibm,kernel-pib"; + index = <0x$2>; + device-path = "/dev/scom$3"; + + system-path = "/backplane0/proc_module0/hub_chip$2/pib"; + }; +')dnl + +dnl +dnl COMPUTE_CHIP_PIB([addr], [index], [path-index]) +dnl +define(`COMPUTE_CHIP_PIB', +` + compute_chip_pib@$1 { + #address-cells = <0x2>; + #size-cells = <0x1>; + reg = <0x0 0x$1 0x7>; + compatible = "ibm,kernel-pib"; + index = <0x1$2>; + device-path = "/dev/scom$3"; + + system-path = "/backplane0/proc_module0/compute_chip$2/pib"; + }; +')dnl + +dnl +dnl PIB_ODY([index], [proc], [path-index], port) +dnl +define(`PIB_ODY', +` + pib_ody@$3$4 { + #address-cells = <0x2>; + #size-cells = <0x1>; + reg = <0x0 0x$1 0x8000>; /*dummy to fix dts warning*/ + compatible = "ibm,kernel-pib-ody"; + index = <0x$1>; + proc = <0x$2>; + port = <$4>; + device-path = "/dev/scom$3$4"; + system-path = "/proc$2/ocmb$1"; + }; +')dnl + + +dnl +dnl SBEFIFO([index], [path-index]) +dnl +define(`SBEFIFO', +` + sbefifo@2400 { /* Bogus address */ + reg = <0x0 0x2400 0x7>; + compatible = "ibm,kernel-sbefifo"; + index = <0x$1>; + device-path = "/dev/sbefifo$2"; + + sbefifo-chipop { + compatible = "ibm,sbefifo-chipop"; + index = <0x$1>; + }; + }; +')dnl + +dnl +dnl COMPUTE_CHIP_SBEFIFO([index], [path-index]) +dnl +define(`COMPUTE_CHIP_SBEFIFO', +` + compute_chip_sbefifo@2400 { /* Bogus address */ + reg = <0x0 0x2400 0x7>; + compatible = "ibm,kernel-sbefifo"; + index = <0x1$1>; + device-path = "/dev/sbefifo$2"; + + sbefifo-chipop { + compatible = "ibm,sbefifo-chipop"; + index = <0x1$1>; + }; + }; +')dnl + +dnl +dnl FSI_PRE([addr], [index], [path-index]) +dnl +define(`FSI_PRE', +` + fsi@$1 { + #address-cells = <0x2>; + #size-cells = <0x1>; + reg = <0x0 0x$1 0x8000>; + compatible = "ibm,kernel-fsi"; + device-path = "/fsi0/slave@00:00/raw"; + index = <0x$2>; + system-path = "/backplane0/proc_module0/hub_chip$2/fsi"; + status = "mustexist"; + + PIB(1000, $2, $3) + SBEFIFO($2, $3) +')dnl + +dnl +dnl FSI_POST() +dnl +define(`FSI_POST', +` + }; +')dnl + +dnl +dnl COMPUTE_CHIP_FSI_PRE([addr], [index], [path-index]) +dnl +define(`COMPUTE_CHIP_FSI_PRE', +` + compute_chip_fsi@$1 { + #address-cells = <0x2>; + #size-cells = <0x1>; + reg = <0x0 0x$1 0x8000>; + compatible = "ibm,kernel-fsi"; + device-path = "/fsi0/slave@00:00/raw"; + index = <0x$2>; + system-path = "/backplane0/proc_module0/compute_chip$2/fsi"; + status = "mustexist"; + + COMPUTE_CHIP_PIB(1000, $2, $3) + COMPUTE_CHIP_SBEFIFO($2, $3) +')dnl + +dnl +dnl COMPUTE_CHIP_FSI_POST() +dnl +define(`COMPUTE_CHIP_FSI_POST', +` + }; +')dnl + +dnl +dnl BMC_I2CBUS([index]) +dnl +define(`BMC_I2CBUS', +` + bmc-i2c-bus$1 { + #address-cells = <0x1>; + #size-cells = <0x0>; + index = <$1>; + compatible = "ibm,kernel-i2c-bus"; + device-path = "/dev/i2c-$1"; + system-path = "/bmc0/i2c-$1"; + }; +')dnl + + +dnl +dnl HMFSI([addr], [port], [index], [path-index]) +dnl +define(`HMFSI', +` + hmfsi@$1 { + #address-cells = <0x2>; + #size-cells = <0x1>; + reg = <0x0 0x$1 0x8000>; + compatible = "ibm,fsi-hmfsi"; + port = <0x$2>; + index = <0x$3>; + system-path = "/backplane0/proc_module0/hub_chip$3/fsi"; + + PIB(1000, $3, $4) + SBEFIFO($3, $4) + }; +')dnl + + +dnl +dnl COMPUTE_CHIP_HMFSI([addr], [port], [index], [path-index]) +dnl +define(`COMPUTE_CHIP_HMFSI', +` + compute_chip_hmfsi@$1 { + #address-cells = <0x2>; + #size-cells = <0x1>; + reg = <0x0 0x$1 0x8000>; + compatible = "ibm,fsi-hmfsi"; + port = <0x$2>; + index = <0x$3>; + system-path = "/backplane0/proc_module0/hub_chip$3/fsi"; + + COMPUTE_CHIP_PIB(1000, $3, $4) + COMPUTE_CHIP_SBEFIFO($3, $4) + }; +')dnl + +//ody ocmb chips are defined in system device tree. The pdbg targets +//that captures the device path to communicate with system ody ocmb +//chips will be defined in backend device tree. + +//ody ocmb system device tree targets need to be mapped to backend +//ody pib device tree targets for communication with the ody ocmb targets. +//Mapping is done based on proc, ocmb chip index of the ody ocmb system target +//with the proc, ocmb index and port number defined in the backend kernel device +//tree + +//for get or put scom in kernel mode device path defined in PIBODY will be used +//for cfam device-path specified in HMFSIODY will be used +dnl +dnl HMFSI_ODY([index], [proc], [path-index], [port]) +dnl +define(`HMFSI_ODY', +` + hmfsi-ody@$3$4 { + #address-cells = <0x2>; + #size-cells = <0x1>; + compatible = "ibm,kernel-fsi-ody"; + device-path = "/i2cr$3$4/slave@00:00/raw"; + reg = <0x0 0x$1 0x8000>; /*dummy to fix dts warning*/ + index = <0x$1>; + proc = <0x$2>; + port = <$4>; + system-path = "/proc$2/ocmb$1/fsi"; + + PIB_ODY($1, $2, $3, $4) + /*SBE_FIFO not required in kernel mode */ + }; +')dnl + +/dts-v1/; + +/ { + #address-cells = <0x1>; + #size-cells = <0x0>; + + BMC_I2CBUS(0) + BMC_I2CBUS(1) + BMC_I2CBUS(2) + BMC_I2CBUS(3) + BMC_I2CBUS(4) + BMC_I2CBUS(5) + BMC_I2CBUS(6) + BMC_I2CBUS(7) + BMC_I2CBUS(8) + BMC_I2CBUS(9) + BMC_I2CBUS(10) + BMC_I2CBUS(11) + BMC_I2CBUS(12) + BMC_I2CBUS(13) + BMC_I2CBUS(14) + BMC_I2CBUS(15) + + FSI_PRE(0, 0, 1) + + HMFSI(100000, 1, 1, 2) + HMFSI(180000, 2, 2, 3) + HMFSI(200000, 3, 3, 4) + HMFSI(280000, 4, 4, 5) + HMFSI(300000, 5, 5, 6) + HMFSI(380000, 6, 6, 7) + HMFSI(400000, 7, 7, 8) + + FSI_POST() + + COMPUTE_CHIP_FSI_PRE(0, 0, 1) + + COMPUTE_CHIP_HMFSI(100000, 1, 1, 2) + COMPUTE_CHIP_HMFSI(180000, 2, 2, 3) + COMPUTE_CHIP_HMFSI(200000, 3, 3, 4) + COMPUTE_CHIP_HMFSI(280000, 4, 4, 5) + COMPUTE_CHIP_HMFSI(300000, 5, 5, 6) + COMPUTE_CHIP_HMFSI(380000, 6, 6, 7) + COMPUTE_CHIP_HMFSI(400000, 7, 7, 8) + + COMPUTE_CHIP_FSI_POST() + + HMFSI_ODY(0, 0, 1, 11) + HMFSI_ODY(1, 0, 1, 10) + HMFSI_ODY(2, 0, 1, 12) + HMFSI_ODY(3, 0, 1, 13) + HMFSI_ODY(4, 0, 1, 15) + HMFSI_ODY(5, 0, 1, 00) + HMFSI_ODY(6, 0, 1, 14) + HMFSI_ODY(7, 0, 1, 01) + + HMFSI_ODY(0, 1, 2, 02) + HMFSI_ODY(1, 1, 2, 10) + HMFSI_ODY(2, 1, 2, 14) + HMFSI_ODY(3, 1, 2, 17) + HMFSI_ODY(4, 1, 2, 15) + HMFSI_ODY(5, 1, 2, 11) + HMFSI_ODY(6, 1, 2, 03) + HMFSI_ODY(7, 1, 2, 16) + + HMFSI_ODY(0, 2, 3, 11) + HMFSI_ODY(1, 2, 3, 10) + HMFSI_ODY(2, 2, 3, 12) + HMFSI_ODY(3, 2, 3, 13) + HMFSI_ODY(4, 2, 3, 15) + HMFSI_ODY(5, 2, 3, 00) + HMFSI_ODY(6, 2, 3, 14) + HMFSI_ODY(7, 2, 3, 01) + + HMFSI_ODY(0, 3, 4, 02) + HMFSI_ODY(1, 3, 4, 10) + HMFSI_ODY(2, 3, 4, 14) + HMFSI_ODY(3, 3, 4, 17) + HMFSI_ODY(4, 3, 4, 15) + HMFSI_ODY(5, 3, 4, 11) + HMFSI_ODY(6, 3, 4, 03) + HMFSI_ODY(7, 3, 4, 16) +}; diff --git a/bmc-sbefifo-rainiest.dts.m4 b/bmc-sbefifo-rainiest.dts.m4 new file mode 100644 index 000000000..54586a712 --- /dev/null +++ b/bmc-sbefifo-rainiest.dts.m4 @@ -0,0 +1,297 @@ +dnl +dnl SBEFIFO([index], [path-index]) +dnl +define(`SBEFIFO', +` + sbefifo@2400 { /* Bogus address */ + reg = <0x0 0x2400 0x7>; + compatible = "ibm,kernel-sbefifo"; + index = <0x$1>; + device-path = "/dev/sbefifo$2"; + + sbefifo-pib { + #address-cells = <0x2>; + #size-cells = <0x1>; + compatible = "ibm,sbefifo-pib"; + index = <0x$1>; + system-path = "/backplane0/proc_module0/hub_chip$1/pib"; + }; + + sbefifo-chipop { + compatible = "ibm,sbefifo-chipop"; + index = <0x$1>; + }; + }; +')dnl + +dnl +dnl FSI_PRE([addr], [index], [path-index]) +dnl +define(`FSI_PRE', +` + fsi@$1 { + #address-cells = <0x2>; + #size-cells = <0x1>; + compatible = "ibm,kernel-fsi"; + device-path = "/fsi0/slave@00:00/raw"; + reg = <0x0 0x$1 0x8000>; + index = <0x$2>; + status = "mustexist"; + system-path = "/backplane0/proc_module0/hub_chip$2/fsi"; + + SBEFIFO($2, $3) +')dnl + +dnl +dnl FSI_POST() +dnl +define(`FSI_POST', +` + }; +')dnl + +dnl +dnl HMFSI([addr], [port], [index], [path-index]) +dnl +define(`HMFSI', +` + hmfsi@$1 { + #address-cells = <0x2>; + #size-cells = <0x1>; + compatible = "ibm,kernel-fsi"; + device-path = "/fsi1/slave@0$2:00/raw"; + reg = <0x0 0x$1 0x8000>; + port = <0x$2>; + index = <0x$3>; + system-path = "/backplane0/proc_module0/hub_chip$3/fsi"; + + SBEFIFO($3, $4) + }; +')dnl + + + +dnl +dnl COMPUTE_CHIP_SBEFIFO([index], [path-index]) +dnl +define(`COMPUTE_CHIP_SBEFIFO', +` + computechip_sbefifo@2400 { /* Bogus address */ + reg = <0x0 0x2400 0x7>; + compatible = "ibm,kernel-sbefifo"; + index = <0x1$1>; + device-path = "/dev/sbefifo$2"; + + computechip_sbefifo-pib { + #address-cells = <0x2>; + #size-cells = <0x1>; + compatible = "ibm,sbefifo-pib"; + index = <0x1$1>; + system-path = "/backplane0/proc_module0/compute_chip$1/pib"; + }; + + computechip_sbefifo-chipop { + compatible = "ibm,sbefifo-chipop"; + index = <0x1$1>; + }; + }; +')dnl + +dnl +dnl COMPUTE_CHIP_FSI_PRE([addr], [index], [path-index]) +dnl +define(`COMPUTE_CHIP_FSI_PRE', +` + computechip_fsi@$1 { + #address-cells = <0x2>; + #size-cells = <0x1>; + compatible = "ibm,kernel-fsi"; + device-path = "/fsi0/slave@00:00/raw"; + reg = <0x0 0x$1 0x8000>; + index = <0x$2>; + status = "mustexist"; + system-path = "/backplane0/proc_module0/compute_chip$2/fsi"; + + COMPUTE_CHIP_SBEFIFO($2, $3) +')dnl + +dnl +dnl COMPUTE_CHIP_FSI_POST() +dnl +define(`COMPUTE_CHIP_FSI_POST', +` + }; +')dnl + +dnl +dnl COMPUTE_CHIP_HMFSI([addr], [port], [index], [path-index]) +dnl +define(`COMPUTE_CHIP_HMFSI', +` + computechip_hmfsi@$1 { + #address-cells = <0x2>; + #size-cells = <0x1>; + compatible = "ibm,kernel-fsi"; + device-path = "/fsi1/slave@0$2:00/raw"; + reg = <0x0 0x$1 0x8000>; + port = <0x$2>; + index = <0x$3>; + system-path = "/backplane0/proc_module0/compute_chip$3/fsi"; + + COMPUTE_CHIP_SBEFIFO($3, $4) + }; +')dnl + +//ocmb ody ddr5 chip SBE instance will be mapped to /dev/sbefifoXYY +//device path where X is proc and YY is port. BMC need to use this +//path for get/put scom to SBE instance of the ocmb ddr5 chip. + +//ody ocmb chips will be defined in system device tree, where as how +//the sbe instances of these ody ocmb chips will be defined in this +//backend device tree + +//ody ocmb system device tree targets will be mapped to backend +//ody sbefifo device tree targets based on proc, ocmb chip index +dnl +dnl HMFSI_ODY([index], [proc], [path-index], [port]) +dnl +define(`HMFSI_ODY', +` + hmfsi-ody@$3$4 { + #address-cells = <0x2>; + #size-cells = <0x1>; + compatible = "ibm,kernel-fsi-ody"; + device-path = "/i2cr$3$4/slave@00:00/raw"; + reg = <0x0 0x$1 0x8000>; /*dummy to fix dts warning*/ + index = <0x$1>; + proc = <0x$2>; + port = <$4>; + + SBEFIFO_ODY($1, $2, $3, $4) + }; +')dnl + +dnl +dnl SBEFIFO_ODY([index], [proc], [path-index], [port] []) +dnl +define(`SBEFIFO_ODY', +` + sbefifo-ody@$3$4{ /* Bogus address */ + #address-cells = <0x2>; + #size-cells = <0x1>; + compatible = "ibm,kernel-sbefifo-ody"; + reg = <0x0 0x$1 0x8000>; /*dummy to fix dts warning*/ + index = <0x$1>; + proc = <0x$2>; + port = <$4>; + device-path = "/dev/sbefifo$3$4"; + + sbefifo-chipop-ody { + compatible = "ibm,sbefifo-chipop-ody"; + index = <0x$1>; + proc = <0x$2>; + port = <$4>; + }; + }; + +')dnl + +dnl +dnl BMC_I2CBUS([index]) +dnl +define(`BMC_I2CBUS', +` + bmc-i2c-bus$1 { + #address-cells = <0x1>; + #size-cells = <0x0>; + index = <$1>; + compatible = "ibm,kernel-i2c-bus"; + device-path = "/dev/i2c-$1"; + system-path = "/bmc0/i2c-$1"; + }; +')dnl + + +/dts-v1/; + +/ { + #address-cells = <0x1>; + #size-cells = <0x0>; + + BMC_I2CBUS(0) + BMC_I2CBUS(1) + BMC_I2CBUS(2) + BMC_I2CBUS(3) + BMC_I2CBUS(4) + BMC_I2CBUS(5) + BMC_I2CBUS(6) + BMC_I2CBUS(7) + BMC_I2CBUS(8) + BMC_I2CBUS(9) + BMC_I2CBUS(10) + BMC_I2CBUS(11) + BMC_I2CBUS(12) + BMC_I2CBUS(13) + BMC_I2CBUS(14) + BMC_I2CBUS(15) + + FSI_PRE(0, 0, 1) + + HMFSI(100000, 1, 1, 2) + HMFSI(180000, 2, 2, 3) + HMFSI(200000, 3, 3, 4) + HMFSI(280000, 4, 4, 5) + HMFSI(300000, 5, 5, 6) + HMFSI(380000, 6, 6, 7) + HMFSI(400000, 7, 7, 8) + + FSI_POST() + + COMPUTE_CHIP_FSI_PRE(0, 0, 1) + + COMPUTE_CHIP_HMFSI(100000, 1, 1, 2) + COMPUTE_CHIP_HMFSI(180000, 2, 2, 3) + COMPUTE_CHIP_HMFSI(200000, 3, 3, 4) + COMPUTE_CHIP_HMFSI(280000, 4, 4, 5) + COMPUTE_CHIP_HMFSI(300000, 5, 5, 6) + COMPUTE_CHIP_HMFSI(380000, 6, 6, 7) + COMPUTE_CHIP_HMFSI(400000, 7, 7, 8) + + COMPUTE_CHIP_FSI_POST() + + HMFSI_ODY(0, 0, 1, 11) + HMFSI_ODY(1, 0, 1, 10) + HMFSI_ODY(2, 0, 1, 12) + HMFSI_ODY(3, 0, 1, 13) + HMFSI_ODY(4, 0, 1, 15) + HMFSI_ODY(5, 0, 1, 00) + HMFSI_ODY(6, 0, 1, 14) + HMFSI_ODY(7, 0, 1, 01) + + HMFSI_ODY(0, 1, 2, 02) + HMFSI_ODY(1, 1, 2, 10) + HMFSI_ODY(2, 1, 2, 14) + HMFSI_ODY(3, 1, 2, 17) + HMFSI_ODY(4, 1, 2, 15) + HMFSI_ODY(5, 1, 2, 11) + HMFSI_ODY(6, 1, 2, 03) + HMFSI_ODY(7, 1, 2, 16) + + HMFSI_ODY(0, 2, 3, 11) + HMFSI_ODY(1, 2, 3, 10) + HMFSI_ODY(2, 2, 3, 12) + HMFSI_ODY(3, 2, 3, 13) + HMFSI_ODY(4, 2, 3, 15) + HMFSI_ODY(5, 2, 3, 00) + HMFSI_ODY(6, 2, 3, 14) + HMFSI_ODY(7, 2, 3, 01) + + HMFSI_ODY(0, 3, 4, 02) + HMFSI_ODY(1, 3, 4, 10) + HMFSI_ODY(2, 3, 4, 14) + HMFSI_ODY(3, 3, 4, 17) + HMFSI_ODY(4, 3, 4, 15) + HMFSI_ODY(5, 3, 4, 11) + HMFSI_ODY(6, 3, 4, 03) + HMFSI_ODY(7, 3, 4, 16) +}; diff --git a/libpdbg/dtb.c b/libpdbg/dtb.c index a201202ad..12a5f9393 100644 --- a/libpdbg/dtb.c +++ b/libpdbg/dtb.c @@ -40,6 +40,7 @@ #include "p9r-fsi.dt.h" #include "p9z-fsi.dt.h" #include "bmc-kernel.dt.h" +#include "bmc-kernel-rainiest.dt.h" #include "bmc-kernel-rainier.dt.h" #include "bmc-kernel-everest.dt.h" #include "p8-host.dt.h" @@ -48,6 +49,7 @@ #include "p8-cronus.dt.h" #include "cronus.dt.h" #include "bmc-sbefifo.dt.h" +#include "bmc-sbefifo-rainiest.dt.h" #include "bmc-sbefifo-rainier.dt.h" #include "bmc-sbefifo-everest.dt.h" #include "p8.dt.h" @@ -344,6 +346,10 @@ static void bmc_target(struct pdbg_dtb *dtb) } if (!dtb->system.fdt) dtb->system.fdt = &_binary_p10_dtb_o_start; + } else if (!strcmp(pdbg_backend_option, "p12")) { + pdbg_proc = PDBG_PROC_P12; + pdbg_log(PDBG_INFO, "bmc_target - loading bmc kernel rainiest target"); + dtb->backend.fdt = &_binary_bmc_kernel_rainiest_dtb_o_start; } else { pdbg_log(PDBG_ERROR, "Invalid system type %s\n", pdbg_backend_option); pdbg_log(PDBG_ERROR, "Use 'p8', 'p9' or 'p10'\n"); @@ -378,6 +384,16 @@ static void bmc_target(struct pdbg_dtb *dtb) if (!dtb->system.fdt) dtb->system.fdt = &_binary_p10_dtb_o_start; break; + case CHIP_ID_P12: + pdbg_log(PDBG_INFO, "Found a POWER10 OpenBMC based system\n"); + pdbg_proc = PDBG_PROC_P12; + if (!dtb->backend.fdt) { + pdbg_log(PDBG_INFO, "bmc_target - loading bmc kernel rainiest target"); + dtb->backend.fdt = &_binary_bmc_kernel_rainiest_dtb_o_start; + } + if (!dtb->system.fdt) //TODO:P12 - This may not be needed. + dtb->system.fdt = &_binary_p10_dtb_o_start; + break; case CHIP_ID_P9: case CHIP_ID_P9P: @@ -437,7 +453,14 @@ static void sbefifo_target(struct pdbg_dtb *dtb) } if (!dtb->system.fdt) dtb->system.fdt = &_binary_p10_dtb_o_start; - } else { + } else if (!strcmp(pdbg_backend_option, "p12")) { + pdbg_proc = PDBG_PROC_P12; + if (!dtb->backend.fdt) + dtb->backend.fdt = &_binary_bmc_sbefifo_rainiest_dtb_o_start; + if (!dtb->system.fdt) + dtb->system.fdt = &_binary_p10_dtb_o_start; //TODO:P12 Need to remove this + } + else { pdbg_log(PDBG_ERROR, "Invalid system type %s\n", pdbg_backend_option); pdbg_log(PDBG_ERROR, "Use 'p9' or 'p10'\n"); } @@ -473,6 +496,14 @@ static void sbefifo_target(struct pdbg_dtb *dtb) if (!dtb->system.fdt) dtb->system.fdt = &_binary_p10_dtb_o_start; break; + case CHIP_ID_P12: + pdbg_proc = PDBG_PROC_P12; + pdbg_log(PDBG_INFO, "Found a POWER12 OpenBMC based system\n"); + if (!dtb->backend.fdt) + dtb->backend.fdt = &_binary_bmc_sbefifo_rainiest_dtb_o_start; + if (!dtb->system.fdt) + dtb->system.fdt = &_binary_p10_dtb_o_start; //TODO:P12 + break; case CHIP_ID_P9: case CHIP_ID_P9P: diff --git a/libpdbg/libpdbg.h b/libpdbg/libpdbg.h index 0dea113c3..b5ceb7119 100644 --- a/libpdbg/libpdbg.h +++ b/libpdbg/libpdbg.h @@ -54,6 +54,7 @@ enum pdbg_proc { PDBG_PROC_P8, /**< POWER8 processor */ PDBG_PROC_P9, /**< POWER9 processor */ PDBG_PROC_P10, /**< POWER10 processor */ + PDBG_PROC_P12, /**< POWER12 processor */ }; /** diff --git a/libpdbg/sbefifo.c b/libpdbg/sbefifo.c index 7dc0d9bb5..9a082c16e 100644 --- a/libpdbg/sbefifo.c +++ b/libpdbg/sbefifo.c @@ -847,6 +847,10 @@ static int sbefifo_probe(struct pdbg_target *target) proc = SBEFIFO_PROC_P10; break; + case PDBG_PROC_P12: + proc = SBEFIFO_PROC_P10; //TODO:P12 update it to the appropriate value + break; + default: PR_ERROR("SBEFIFO driver not supported\n"); return -1; diff --git a/libpdbg/target.h b/libpdbg/target.h index 7d8cdb65a..66ee6a17b 100644 --- a/libpdbg/target.h +++ b/libpdbg/target.h @@ -30,6 +30,7 @@ #define CHIP_ID_P9 0xd1 #define CHIP_ID_P9P 0xd9 #define CHIP_ID_P10 0xda +#define CHIP_ID_P12 0xde enum chip_type {CHIP_UNKNOWN, CHIP_P8, CHIP_P8NV, CHIP_P9, CHIP_P10};