count.vcd

$date
	Fri Oct  4 07:14:45 2024
$end
$version
	Icarus Verilog
$end
$timescale
	1s
$end
$scope module Testbench $end
$var wire 4 ! Count [3:0] $end
$var reg 1 " Clock $end
$var reg 1 # Reset $end
$scope module I1 $end
$var wire 1 " CLK $end
$var wire 1 # RST $end
$var reg 4 $ OUT [3:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
$dumpall
$end
#0
$dumpvars
bx $
1#
0"
bx !
$end
#50
b0 !
b0 $
1"
#100
0"
0#
#150
b1 !
b1 $
1"
#200
0"
#250
b10 !
b10 $
1"
#300
0"
#350
b11 !
b11 $
1"
#400
0"
#450
b100 !
b100 $
1"
#500
0"
#550
b101 !
b101 $
1"
#600
0"
#650
b110 !
b110 $
1"
#700
0"
#750
b111 !
b111 $
1"
#800
0"
#850
b1000 !
b1000 $
1"
#900
0"
#950
b1001 !
b1001 $
1"
#1000
0"
#1050
b1010 !
b1010 $
1"
#1100
0"
#1150
b1011 !
b1011 $
1"
#1200
0"
#1250
b1100 !
b1100 $
1"
#1300
0"
#1350
b1101 !
b1101 $
1"
#1400
0"
#1450
b1110 !
b1110 $
1"
#1500
0"
#1550
b1111 !
b1111 $
1"
#1600
0"
#1650
b0 !
b0 $
1"
#1700
0"
#1750
b1 !
b1 $
1"
#1800
0"
#1850
b10 !
b10 $
1"
#1900
0"
#1950
b11 !
b11 $
1"
#2000
0"
#2050
b100 !
b100 $
1"
#2100
0"
1#
#2150
b0 !
b0 $
1"
#2200
0"
#2250
1"
#2300
0"
#2350
1"
#2400
0"
#2450
1"
#2500
0"