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Update STM32WBA headers to v1.4.0
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modm update bot committed Aug 1, 2024
1 parent 0bb080d commit b9ce36b
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Showing 7 changed files with 180 additions and 132 deletions.
2 changes: 1 addition & 1 deletion README.md
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Expand Up @@ -26,7 +26,7 @@ as the Cube release version in braces:
- [H5: v1.3.0 created 05-June-2024](https://github.com/STMicroelectronics/STM32CubeH5)
- [H7: v1.10.4 created 15-March-2024](https://github.com/STMicroelectronics/STM32CubeH7)
- [WB: v1.12.2 created 05-June-2024](https://github.com/STMicroelectronics/STM32CubeWB)
- [WBA: v1.3.0 created 07-February-2024](https://github.com/STMicroelectronics/STM32CubeWBA)
- [WBA: v1.4.0 created 05-June-2024](https://github.com/STMicroelectronics/STM32CubeWBA)
- [WL: v1.2.0 created 09-November-2022](https://github.com/STMicroelectronics/STM32CubeWL)
- [U0: v1.1.0 created 05-June-2024](https://github.com/STMicroelectronics/STM32CubeU0)
- [U5: v1.4.0 created 13-February-2024](https://github.com/STMicroelectronics/STM32CubeU5)
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57 changes: 30 additions & 27 deletions stm32wbaxx/Include/stm32wba50xx.h
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Expand Up @@ -253,14 +253,14 @@ typedef struct
*/
typedef struct
{
__IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
__IO uint32_t SCR; /*!< Debug MCU status and configuration register, Address offset: 0x04 */
__IO uint32_t APB1LFZR; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */
__IO uint32_t APB1HFZR; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */
__IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */
uint32_t RESERVED1[4];/*!< Reserved, 0x14 - 0x20 */
__IO uint32_t APB7FZR; /*!< Debug MCU APB7 freeze register, Address offset: 0x24 */
__IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x28 */
__IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
__IO uint32_t SCR; /*!< Debug MCU status and configuration register, Address offset: 0x04 */
__IO uint32_t APB1LFZR; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */
__IO uint32_t APB1HFZR; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */
__IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */
uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x14 - 0x20 */
__IO uint32_t APB7FZR; /*!< Debug MCU APB7 freeze register, Address offset: 0x24 */
__IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x28 */
} DBGMCU_TypeDef;

/**
Expand Down Expand Up @@ -617,11 +617,11 @@ typedef struct
*/
typedef struct
{
__IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
__IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
__IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
__IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
__IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
__IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
uint32_t RESERVED;
__IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */
__IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */
} RNG_TypeDef;

/*
Expand Down Expand Up @@ -693,18 +693,18 @@ typedef struct
*/
typedef struct
{
__IO uint32_t SECCFGR; /*!< SYSCFG secure configuration register, Address offset: 0x00 */
__IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */
__IO uint32_t FPUIMR; /*!< SYSCFG FPU interrupt mask register, Address offset: 0x08 */
__IO uint32_t CNSLCKR; /*!< SYSCFG CPU non-secure lock register, Address offset: 0x0C */
__IO uint32_t CSLCKR; /*!< SYSCFG CPU secure lock register, Address offset: 0x10 */
__IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x14 */
__IO uint32_t MESR; /*!< SYSCFG Memory Erase Status register, Address offset: 0x18 */
__IO uint32_t CCCSR; /*!< SYSCFG Conpensaion Cell Control&Status register, Address offset: 0x1C */
__IO uint32_t CCVR; /*!< SYSCFG Conpensaion Cell value register, Address offset: 0x20 */
__IO uint32_t CCCR; /*!< SYSCFG Conpensaion Cell Code register, Address offset: 0x24 */
uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x28 */
__IO uint32_t RSSCMDR; /*!< SYSCFG RSS command mode register, Address offset: 0x2C */
__IO uint32_t SECCFGR; /*!< SYSCFG secure configuration register, Address offset: 0x00 */
__IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */
__IO uint32_t FPUIMR; /*!< SYSCFG FPU interrupt mask register, Address offset: 0x08 */
__IO uint32_t CNSLCKR; /*!< SYSCFG CPU non-secure lock register, Address offset: 0x0C */
__IO uint32_t CSLCKR; /*!< SYSCFG CPU secure lock register, Address offset: 0x10 */
__IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x14 */
__IO uint32_t MESR; /*!< SYSCFG Memory Erase Status register, Address offset: 0x18 */
__IO uint32_t CCCSR; /*!< SYSCFG Conpensaion Cell Control&Status register, Address offset: 0x1C */
__IO uint32_t CCVR; /*!< SYSCFG Conpensaion Cell value register, Address offset: 0x20 */
__IO uint32_t CCCR; /*!< SYSCFG Conpensaion Cell Code register, Address offset: 0x24 */
uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x28 */
__IO uint32_t RSSCMDR; /*!< SYSCFG RSS command mode register, Address offset: 0x2C */
} SYSCFG_TypeDef;

/**
Expand Down Expand Up @@ -4256,7 +4256,7 @@ typedef struct
#define I2C_CR1_ADDRACLR_Pos (30U)
#define I2C_CR1_ADDRACLR_Msk (0x1UL << I2C_CR1_ADDRACLR_Pos) /*!< 0x40000000 */
#define I2C_CR1_ADDRACLR I2C_CR1_ADDRACLR_Msk /*!< ADDRACLR enable */
#define I2C_CR1_STOPFACLR_Pos (30U)
#define I2C_CR1_STOPFACLR_Pos (31U)
#define I2C_CR1_STOPFACLR_Msk (0x1UL << I2C_CR1_STOPFACLR_Pos) /*!< 0x80000000 */
#define I2C_CR1_STOPFACLR I2C_CR1_STOPFACLR_Msk /*!< STOPFACLR enable */

Expand Down Expand Up @@ -4942,7 +4942,6 @@ typedef struct
#define LPTIM_CCR2_CCR2_Msk (0xFFFFUL << LPTIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
#define LPTIM_CCR2_CCR2 LPTIM_CCR2_CCR2_Msk /*!< Compare register 2 */


/******************************************************************************/
/* */
/* Public Key Accelerator (PKA) */
Expand Down Expand Up @@ -6669,6 +6668,9 @@ typedef struct
#define RNG_HTCR_HTCFG_Pos (0U)
#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */
#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk
/******************** RNG Nist Compliance Values *******************/
#define RNG_CR_NIST_VALUE (0x00F02D00U)
#define RNG_HTCR_NIST_VALUE (0xAAC7U)


/******************************************************************************/
Expand Down Expand Up @@ -10293,7 +10295,8 @@ typedef struct

/****************** TIM Instances : supporting OCxREF clear *******************/
#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
((INSTANCE) == TIM2_NS))
((INSTANCE) == TIM2_NS) || \
((INSTANCE) == TIM16_NS))

/********* TIM Instances : supporting bitfield OCCS in SMCR register **********/
#define IS_TIM_OCCS_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
Expand Down
58 changes: 31 additions & 27 deletions stm32wbaxx/Include/stm32wba52xx.h
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Expand Up @@ -267,14 +267,14 @@ typedef struct
*/
typedef struct
{
__IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
__IO uint32_t SCR; /*!< Debug MCU status and configuration register, Address offset: 0x04 */
__IO uint32_t APB1LFZR; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */
__IO uint32_t APB1HFZR; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */
__IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */
uint32_t RESERVED1[4];/*!< Reserved, 0x14 - 0x20 */
__IO uint32_t APB7FZR; /*!< Debug MCU APB7 freeze register, Address offset: 0x24 */
__IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x28 */
__IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
__IO uint32_t SCR; /*!< Debug MCU status and configuration register, Address offset: 0x04 */
__IO uint32_t APB1LFZR; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */
__IO uint32_t APB1HFZR; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */
__IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */
uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x14 - 0x20 */
__IO uint32_t APB7FZR; /*!< Debug MCU APB7 freeze register, Address offset: 0x24 */
__IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x28 */
} DBGMCU_TypeDef;

/**
Expand Down Expand Up @@ -710,11 +710,11 @@ typedef struct
*/
typedef struct
{
__IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
__IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
__IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
__IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
__IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
__IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
uint32_t RESERVED;
__IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */
__IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */
} RNG_TypeDef;

/*
Expand Down Expand Up @@ -787,18 +787,18 @@ typedef struct
*/
typedef struct
{
__IO uint32_t SECCFGR; /*!< SYSCFG secure configuration register, Address offset: 0x00 */
__IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */
__IO uint32_t FPUIMR; /*!< SYSCFG FPU interrupt mask register, Address offset: 0x08 */
__IO uint32_t CNSLCKR; /*!< SYSCFG CPU non-secure lock register, Address offset: 0x0C */
__IO uint32_t CSLCKR; /*!< SYSCFG CPU secure lock register, Address offset: 0x10 */
__IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x14 */
__IO uint32_t MESR; /*!< SYSCFG Memory Erase Status register, Address offset: 0x18 */
__IO uint32_t CCCSR; /*!< SYSCFG Conpensaion Cell Control&Status register, Address offset: 0x1C */
__IO uint32_t CCVR; /*!< SYSCFG Conpensaion Cell value register, Address offset: 0x20 */
__IO uint32_t CCCR; /*!< SYSCFG Conpensaion Cell Code register, Address offset: 0x24 */
uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x28 */
__IO uint32_t RSSCMDR; /*!< SYSCFG RSS command mode register, Address offset: 0x2C */
__IO uint32_t SECCFGR; /*!< SYSCFG secure configuration register, Address offset: 0x00 */
__IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */
__IO uint32_t FPUIMR; /*!< SYSCFG FPU interrupt mask register, Address offset: 0x08 */
__IO uint32_t CNSLCKR; /*!< SYSCFG CPU non-secure lock register, Address offset: 0x0C */
__IO uint32_t CSLCKR; /*!< SYSCFG CPU secure lock register, Address offset: 0x10 */
__IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x14 */
__IO uint32_t MESR; /*!< SYSCFG Memory Erase Status register, Address offset: 0x18 */
__IO uint32_t CCCSR; /*!< SYSCFG Conpensaion Cell Control&Status register, Address offset: 0x1C */
__IO uint32_t CCVR; /*!< SYSCFG Conpensaion Cell value register, Address offset: 0x20 */
__IO uint32_t CCCR; /*!< SYSCFG Conpensaion Cell Code register, Address offset: 0x24 */
uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x28 */
__IO uint32_t RSSCMDR; /*!< SYSCFG RSS command mode register, Address offset: 0x2C */
} SYSCFG_TypeDef;

/**
Expand Down Expand Up @@ -7856,7 +7856,7 @@ typedef struct
#define I2C_CR1_ADDRACLR_Pos (30U)
#define I2C_CR1_ADDRACLR_Msk (0x1UL << I2C_CR1_ADDRACLR_Pos) /*!< 0x40000000 */
#define I2C_CR1_ADDRACLR I2C_CR1_ADDRACLR_Msk /*!< ADDRACLR enable */
#define I2C_CR1_STOPFACLR_Pos (30U)
#define I2C_CR1_STOPFACLR_Pos (31U)
#define I2C_CR1_STOPFACLR_Msk (0x1UL << I2C_CR1_STOPFACLR_Pos) /*!< 0x80000000 */
#define I2C_CR1_STOPFACLR I2C_CR1_STOPFACLR_Msk /*!< STOPFACLR enable */

Expand Down Expand Up @@ -8542,7 +8542,6 @@ typedef struct
#define LPTIM_CCR2_CCR2_Msk (0xFFFFUL << LPTIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
#define LPTIM_CCR2_CCR2 LPTIM_CCR2_CCR2_Msk /*!< Compare register 2 */


/******************************************************************************/
/* */
/* Public Key Accelerator (PKA) */
Expand Down Expand Up @@ -10570,6 +10569,9 @@ typedef struct
#define RNG_HTCR_HTCFG_Pos (0U)
#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */
#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk
/******************** RNG Nist Compliance Values *******************/
#define RNG_CR_NIST_VALUE (0x00F02D00U)
#define RNG_HTCR_NIST_VALUE (0xAAC7U)


/******************************************************************************/
Expand Down Expand Up @@ -14527,7 +14529,9 @@ typedef struct
/****************** TIM Instances : supporting OCxREF clear *******************/
#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \
((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \
((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S))
((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \
((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \
((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S))

/****************** TIM Instances : supporting bitfield OCCS in SMCR register *******************/
#define IS_TIM_OCCS_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \
Expand Down
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