Update STM32C0 headers to v1.3.0

modm-io · Nov 20, 2024 · 9a74498 · 9a74498
1 parent f8a7e36
commit 9a74498
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Showing 9 changed files with 22,339 additions and 22 deletions.
diff --git a/README.md b/README.md
@@ -20,7 +20,7 @@ as the Cube release version in braces:
 - [F3: v2.3.8 created 29-March-2024](https://github.com/STMicroelectronics/STM32CubeF3)
 - [F4: v2.6.10 created 31-May-2024](https://github.com/STMicroelectronics/STM32CubeF4)
 - [F7: v1.2.9 created 10-May-2024](https://github.com/STMicroelectronics/STM32CubeF7)
-- [C0: v1.2.0 created 05-June-2024](https://github.com/STMicroelectronics/STM32CubeC0)
+- [C0: v1.3.0 created 30-October-2024](https://github.com/STMicroelectronics/STM32CubeC0)
 - [G0: v1.4.4 created 15-December-2023](https://github.com/STMicroelectronics/STM32CubeG0)
 - [G4: v1.2.5 created 25-September-2024](https://github.com/STMicroelectronics/STM32CubeG4)
 - [H5: v1.3.0 created 05-June-2024](https://github.com/STMicroelectronics/STM32CubeH5)

diff --git a/stm32c0xx/Include/stm32c011xx.h b/stm32c0xx/Include/stm32c011xx.h
@@ -570,6 +570,11 @@ typedef struct
 #define UID_BASE              (0x1FFF7550UL)        /*!< Unique device ID register base address */
 #define FLASHSIZE_BASE        (0x1FFF75A0UL)        /*!< Flash size data register base address  */
 
+/*!< Bootloader Firmware */
+
+/************ Bootloader Exit Secure Memory Firmware *************/
+#define BL_EXIT_SEC_MEM_BASE    (0x1FFF1600UL)
+
 /**
   * @}
   */
@@ -3796,12 +3801,6 @@ typedef struct
 /******************************************************************************/
 
 /********************  Bit definition for RCC_CR register  *****************/
-#define RCC_CR_SYSDIV_Pos                (2U)
-#define RCC_CR_SYSDIV_Msk                (0x7UL << RCC_CR_SYSDIV_Pos)          /*!< 0x0000001C */
-#define RCC_CR_SYSDIV                    RCC_CR_SYSDIV_Msk                     /*!< Clock division factor for system clock */
-#define RCC_CR_SYSDIV_0                  (0x1UL << RCC_CR_SYSDIV_Pos)          /*!< 0x00000004 */
-#define RCC_CR_SYSDIV_1                  (0x2UL << RCC_CR_SYSDIV_Pos)          /*!< 0x00000008 */
-#define RCC_CR_SYSDIV_2                  (0x4UL << RCC_CR_SYSDIV_Pos)          /*!< 0x00000010 */
 #define RCC_CR_HSIKERDIV_Pos             (5U)
 #define RCC_CR_HSIKERDIV_Msk             (0x7UL << RCC_CR_HSIKERDIV_Pos)       /*!< 0x000000E0 */
 #define RCC_CR_HSIKERDIV                 RCC_CR_HSIKERDIV_Msk                  /*!< HSI48 clock division factor for HSI kernel clocks inputs */

diff --git a/stm32c0xx/Include/stm32c031xx.h b/stm32c0xx/Include/stm32c031xx.h
@@ -573,6 +573,11 @@ typedef struct
 #define UID_BASE              (0x1FFF7550UL)        /*!< Unique device ID register base address */
 #define FLASHSIZE_BASE        (0x1FFF75A0UL)        /*!< Flash size data register base address  */
 
+/*!< Bootloader Firmware */
+
+/************ Bootloader Exit Secure Memory Firmware *************/
+#define BL_EXIT_SEC_MEM_BASE    (0x1FFF1600UL)
+
 /**
   * @}
   */
@@ -3950,12 +3955,6 @@ typedef struct
 /******************************************************************************/
 
 /********************  Bit definition for RCC_CR register  *****************/
-#define RCC_CR_SYSDIV_Pos                (2U)
-#define RCC_CR_SYSDIV_Msk                (0x7UL << RCC_CR_SYSDIV_Pos)          /*!< 0x0000001C */
-#define RCC_CR_SYSDIV                    RCC_CR_SYSDIV_Msk                     /*!< Clock division factor for system clock */
-#define RCC_CR_SYSDIV_0                  (0x1UL << RCC_CR_SYSDIV_Pos)          /*!< 0x00000004 */
-#define RCC_CR_SYSDIV_1                  (0x2UL << RCC_CR_SYSDIV_Pos)          /*!< 0x00000008 */
-#define RCC_CR_SYSDIV_2                  (0x4UL << RCC_CR_SYSDIV_Pos)          /*!< 0x00000010 */
 #define RCC_CR_HSIKERDIV_Pos             (5U)
 #define RCC_CR_HSIKERDIV_Msk             (0x7UL << RCC_CR_HSIKERDIV_Pos)       /*!< 0x000000E0 */
 #define RCC_CR_HSIKERDIV                 RCC_CR_HSIKERDIV_Msk                  /*!< HSI48 clock division factor for HSI kernel clocks inputs */

diff --git a/stm32c0xx/Include/stm32c051xx.h b/stm32c0xx/Include/stm32c051xx.h
diff --git a/stm32c0xx/Include/stm32c071xx.h b/stm32c0xx/Include/stm32c071xx.h
@@ -640,6 +640,11 @@ typedef struct
 #define UID_BASE              (0x1FFF7550UL)        /*!< Unique device ID register base address */
 #define FLASHSIZE_BASE        (0x1FFF75A0UL)        /*!< Flash size data register base address  */
 
+/*!< Bootloader Firmware */
+
+/************ Bootloader Exit Secure Memory Firmware *************/
+#define BL_EXIT_SEC_MEM_BASE    (0x1FFF6000UL)
+
 /**
   * @}
   */

diff --git a/stm32c0xx/Include/stm32c091xx.h b/stm32c0xx/Include/stm32c091xx.h
diff --git a/stm32c0xx/Include/stm32c092xx.h b/stm32c0xx/Include/stm32c092xx.h
diff --git a/stm32c0xx/Include/stm32c0xx.h b/stm32c0xx/Include/stm32c0xx.h
@@ -56,10 +56,15 @@
    application
   */
 
-#if !defined (STM32C011xx) && !defined (STM32C031xx) && !defined (STM32C071xx)
+#if !defined (STM32C011xx) && !defined (STM32C031xx) \
+    && !defined (STM32C051xx) && !defined (STM32C071xx) \
+    && !defined (STM32C091xx) && !defined (STM32C092xx)
   /* #define STM32C011xx */   /*!< STM32C011xx Devices */
   /* #define STM32C031xx */   /*!< STM32C031xx Devices */
+  /* #define STM32C051xx */   /*!< STM32C051xx Devices */
   /* #define STM32C071xx */   /*!< STM32C071xx Devices */
+  /* #define STM32C091xx */   /*!< STM32C091xx Devices */
+  /* #define STM32C092xx */   /*!< STM32C092xx Devices */
 #endif
 
 /*  Tip: To avoid modifying this file each time you need to switch between these
@@ -78,7 +83,7 @@
   * @brief CMSIS Device version number V1.0.0
   */
 #define __STM32C0_CMSIS_VERSION_MAIN   (0x01U) /*!< [31:24] main version */
-#define __STM32C0_CMSIS_VERSION_SUB1   (0x02U) /*!< [23:16] sub1 version */
+#define __STM32C0_CMSIS_VERSION_SUB1   (0x03U) /*!< [23:16] sub1 version */
 #define __STM32C0_CMSIS_VERSION_SUB2   (0x00U) /*!< [15:8]  sub2 version */
 #define __STM32C0_CMSIS_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */
 #define __STM32C0_CMSIS_VERSION        ((__STM32C0_CMSIS_VERSION_MAIN << 24)\
@@ -98,8 +103,14 @@
   #include "stm32c011xx.h"
 #elif defined(STM32C031xx)
   #include "stm32c031xx.h"
+#elif defined(STM32C051xx)
+  #include "stm32c051xx.h"
 #elif defined(STM32C071xx)
   #include "stm32c071xx.h"
+#elif defined(STM32C091xx)
+  #include "stm32c091xx.h"
+#elif defined(STM32C092xx)
+  #include "stm32c092xx.h"
 #else
  #error "Please select first the target STM32C0xx device used in your application (in stm32c0xx.h file)"
 #endif

diff --git a/stm32c0xx/Release_Notes.html b/stm32c0xx/Release_Notes.html
@@ -43,19 +43,60 @@ <h1 id="release-notes-for-stm32c0xx-cmsis">Release Notes for
 <section id="update-history" class="col-sm-12 col-lg-8">
 <h1><strong>Update History</strong></h1>
 <div class="collapse">
-<input type="checkbox" id="collapse-section3" checked aria-hidden="true">
-<label for="collapse-section3" checked aria-hidden="true"><strong>V1.2.0
-/ 05-June-2024</strong></label>
+<input type="checkbox" id="collapse-section4" checked aria-hidden="true">
+<label for="collapse-section4" checked aria-hidden="true"><strong>V1.3.0
+/ 30-October-2024</strong></label>
 <div>
 <h2 id="main-changes">Main Changes</h2>
 <ul>
+<li>Official release of STM32C0xx CMSIS drivers to support
+<strong>STM32C051xx</strong> and <strong>STM32C091/92xx</strong>
+devices</li>
+<li>General updates to fix known defects and enhance implementation</li>
+<li>Align version of bit and registers definition with the STM32C0
+reference manual</li>
+</ul>
+<h2 id="contents">Contents</h2>
+<ul>
+<li><strong>Support of STM32C051xx and STM32C091/92xx devices</strong>:
+<ul>
+<li>Add “stm32c051xx.h” , “stm32c091xx.h”, and “stm32c092xx.h”
+files</li>
+<li>Add startup files “startup_stm32c051xx.s”, “startup_stm32c091xx.s”
+and “startup_stm32c092xx.s” for EWARM, STM32CubeIDE and MDK-ARM
+toolchains</li>
+<li>Add STM32C051xx and STM32C091/92xx devices linker files for EWARM
+and STM32CubeIDE toolchains</li>
+</ul></li>
+<li><strong>Registers and bit field definitions updates</strong> :
+<ul>
+<li>Add BL_EXIT_SEC_MEM_BASE Bootloader Exit Secure Memory Firmware
+addresses</li>
+<li>Remove RCC_CR_SYSDIV bit definition from C031xx and C011xx CMSIS
+files as undefined</li>
+</ul></li>
+</ul>
+<h2 id="supported-devices">Supported Devices</h2>
+<ul>
+<li>STM32C011xx, STM32C031xx, <strong>STM32C051xx</strong>, STM32C071xx
+and <strong>STM32C091/92xx</strong> devices</li>
+</ul>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section3" aria-hidden="true">
+<label for="collapse-section3" aria-hidden="true"><strong>V1.2.0 /
+05-June-2024</strong></label>
+<div>
+<h2 id="main-changes-1">Main Changes</h2>
+<ul>
 <li>First official release of STM32C0xx CMSIS drivers to support
 <strong>STM32C071xx</strong> devices</li>
 <li>General updates to fix known defects and enhance implementation</li>
 <li>Align version of bit and registers definition with the STM32C0
 reference manual</li>
 </ul>
-<h2 id="contents">Contents</h2>
+<h2 id="contents-1">Contents</h2>
 <ul>
 <li><strong>Support of STM32C071xx devices</strong>:
 <ul>
@@ -102,7 +143,7 @@ <h2 id="contents">Contents</h2>
 </ul></li>
 </ul></li>
 </ul>
-<h2 id="supported-devices">Supported Devices</h2>
+<h2 id="supported-devices-1">Supported Devices</h2>
 <ul>
 <li>STM32C011xx, STM32C031xx and STM32C071xx devices</li>
 </ul>
@@ -112,14 +153,14 @@ <h2 id="supported-devices">Supported Devices</h2>
 <input type="checkbox" id="collapse-section2" aria-hidden="true">
 <label for="collapse-section2" aria-hidden="true"><strong>V1.1.0 /
 07-June-2023</strong></label>
-<h2 id="main-changes-1">Main Changes</h2>
+<h2 id="main-changes-2">Main Changes</h2>
 <p>Align flash register address with STM32C0 reference manual</p>
 </div>
 <div class="collapse">
 <input type="checkbox" id="collapse-section1" aria-hidden="true">
 <label for="collapse-section1" aria-hidden="true"><strong>V1.0.0 /
 09-February-2022</strong></label>
-<h2 id="main-changes-2">Main Changes</h2>
+<h2 id="main-changes-3">Main Changes</h2>
 <p>First official release version of bits and registers definition
 aligned with STM32C0 reference manual</p>
 </div>