From 61af968bd8692c1887273772e16756f7ce0ee4fb Mon Sep 17 00:00:00 2001 From: modm update bot Date: Fri, 17 Mar 2023 21:57:10 +0000 Subject: [PATCH] Update STM32F0 headers to v2.3.7 --- README.md | 2 +- stm32f0xx/Include/stm32f030x6.h | 32 +++--- stm32f0xx/Include/stm32f030x8.h | 32 +++--- stm32f0xx/Include/stm32f030xc.h | 34 +++---- stm32f0xx/Include/stm32f031x6.h | 38 ++++--- stm32f0xx/Include/stm32f038xx.h | 30 +++--- stm32f0xx/Include/stm32f042x6.h | 50 +++++----- stm32f0xx/Include/stm32f048xx.h | 50 +++++----- stm32f0xx/Include/stm32f051x8.h | 44 ++++---- stm32f0xx/Include/stm32f058xx.h | 44 ++++---- stm32f0xx/Include/stm32f070x6.h | 30 +++--- stm32f0xx/Include/stm32f070xb.h | 38 ++++--- stm32f0xx/Include/stm32f071xb.h | 46 ++++----- stm32f0xx/Include/stm32f072xb.h | 58 +++++------ stm32f0xx/Include/stm32f078xx.h | 50 +++++----- stm32f0xx/Include/stm32f091xc.h | 46 ++++----- stm32f0xx/Include/stm32f098xx.h | 58 +++++------ stm32f0xx/Include/stm32f0xx.h | 28 ++---- stm32f0xx/Include/system_stm32f0xx.h | 14 ++- stm32f0xx/Release_Notes.html | 144 ++++++++++++++++++--------- 20 files changed, 450 insertions(+), 418 deletions(-) diff --git a/README.md b/README.md index 6645814..812569e 100644 --- a/README.md +++ b/README.md @@ -14,7 +14,7 @@ as the Cube release version in braces: - [L1: v2.3.2 created 21-May-2021](https://github.com/STMicroelectronics/STM32CubeL1) - [L4: v1.7.2 created 26-November-2021](https://github.com/STMicroelectronics/STM32CubeL4) - [L5: v1.0.5 created 04-November-2022](https://github.com/STMicroelectronics/STM32CubeL5) -- [F0: v2.3.6 created 23-July-2021](https://github.com/STMicroelectronics/STM32CubeF0) +- [F0: v2.3.7 created 27-January-2023](https://github.com/STMicroelectronics/STM32CubeF0) - [F1: v4.3.3 created 21-May-2021](https://github.com/STMicroelectronics/STM32CubeF1) - [F2: v2.2.5 created 21-May-2021](https://github.com/STMicroelectronics/STM32CubeF2) - [F3: v2.3.6 created 23-July-2021](https://github.com/STMicroelectronics/STM32CubeF3) diff --git a/stm32f0xx/Include/stm32f030x6.h b/stm32f0xx/Include/stm32f030x6.h index ee791d2..ef0b7cc 100644 --- a/stm32f0xx/Include/stm32f030x6.h +++ b/stm32f0xx/Include/stm32f030x6.h @@ -9,22 +9,20 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ - /** @addtogroup CMSIS * @{ */ @@ -70,7 +68,7 @@ typedef enum /****** Cortex-M0 Processor Exceptions Numbers **************************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ - SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ @@ -549,7 +547,7 @@ typedef struct /******************************************************************************/ /* - * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) + * @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ /* Note: No specific macro feature on this device */ @@ -637,7 +635,7 @@ typedef struct #define ADC_CFGR1_ALIGN_Pos (5U) #define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ -#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignement */ +#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignment */ #define ADC_CFGR1_EXTSEL_Pos (6U) #define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ @@ -2731,7 +2729,7 @@ typedef struct /* */ /*****************************************************************************/ /* -* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) +* @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ /******************** Bit definition for RCC_CR register *******************/ @@ -3290,7 +3288,7 @@ typedef struct /* */ /*****************************************************************************/ /* -* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) +* @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ #define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */ #define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */ @@ -3750,7 +3748,7 @@ typedef struct /*****************************************************************************/ /* - * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) + * @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ /* Note: No specific macro feature on this device */ @@ -5337,17 +5335,18 @@ typedef struct #define ADC1_COMP_IRQn ADC1_IRQn #define DMA1_Ch1_IRQn DMA1_Channel1_IRQn #define DMA1_Ch2_3_DMA2_Ch1_2_IRQn DMA1_Channel2_3_IRQn -#define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn #define DMA1_Ch4_7_DMA2_Ch3_5_IRQn DMA1_Channel4_5_IRQn +#define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn #define RCC_CRS_IRQn RCC_IRQn +#define SVC_IRQn SVCall_IRQn /* Aliases for __IRQHandler */ #define ADC1_COMP_IRQHandler ADC1_IRQHandler #define DMA1_Ch1_IRQHandler DMA1_Channel1_IRQHandler #define DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler DMA1_Channel2_3_IRQHandler -#define DMA1_Channel4_5_6_7_IRQHandler DMA1_Channel4_5_IRQHandler #define DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler DMA1_Channel4_5_IRQHandler +#define DMA1_Channel4_5_6_7_IRQHandler DMA1_Channel4_5_IRQHandler #define RCC_CRS_IRQHandler RCC_IRQHandler @@ -5365,4 +5364,3 @@ typedef struct * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm32f0xx/Include/stm32f030x8.h b/stm32f0xx/Include/stm32f030x8.h index 2a35502..4babed7 100644 --- a/stm32f0xx/Include/stm32f030x8.h +++ b/stm32f0xx/Include/stm32f030x8.h @@ -9,22 +9,20 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ - /** @addtogroup CMSIS * @{ */ @@ -70,7 +68,7 @@ typedef enum /****** Cortex-M0 Processor Exceptions Numbers **************************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ - SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ @@ -565,7 +563,7 @@ typedef struct /******************************************************************************/ /* - * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) + * @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ /* Note: No specific macro feature on this device */ @@ -653,7 +651,7 @@ typedef struct #define ADC_CFGR1_ALIGN_Pos (5U) #define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ -#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignement */ +#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignment */ #define ADC_CFGR1_EXTSEL_Pos (6U) #define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ @@ -2761,7 +2759,7 @@ typedef struct /* */ /*****************************************************************************/ /* -* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) +* @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ /******************** Bit definition for RCC_CR register *******************/ @@ -3334,7 +3332,7 @@ typedef struct /* */ /*****************************************************************************/ /* -* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) +* @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ #define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */ #define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */ @@ -3794,7 +3792,7 @@ typedef struct /*****************************************************************************/ /* - * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) + * @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ /* Note: No specific macro feature on this device */ @@ -5402,18 +5400,19 @@ typedef struct #define ADC1_COMP_IRQn ADC1_IRQn #define DMA1_Ch1_IRQn DMA1_Channel1_IRQn #define DMA1_Ch2_3_DMA2_Ch1_2_IRQn DMA1_Channel2_3_IRQn -#define DMA1_Ch4_7_DMA2_Ch3_5_IRQn DMA1_Channel4_5_IRQn #define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn +#define DMA1_Ch4_7_DMA2_Ch3_5_IRQn DMA1_Channel4_5_IRQn #define RCC_CRS_IRQn RCC_IRQn #define TIM6_DAC_IRQn TIM6_IRQn +#define SVC_IRQn SVCall_IRQn /* Aliases for __IRQHandler */ #define ADC1_COMP_IRQHandler ADC1_IRQHandler #define DMA1_Ch1_IRQHandler DMA1_Channel1_IRQHandler #define DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler DMA1_Channel2_3_IRQHandler -#define DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler DMA1_Channel4_5_IRQHandler #define DMA1_Channel4_5_6_7_IRQHandler DMA1_Channel4_5_IRQHandler +#define DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler DMA1_Channel4_5_IRQHandler #define RCC_CRS_IRQHandler RCC_IRQHandler #define TIM6_DAC_IRQHandler TIM6_IRQHandler @@ -5432,4 +5431,3 @@ typedef struct * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm32f0xx/Include/stm32f030xc.h b/stm32f0xx/Include/stm32f030xc.h index a718ecf..ab3d5f4 100644 --- a/stm32f0xx/Include/stm32f030xc.h +++ b/stm32f0xx/Include/stm32f030xc.h @@ -9,22 +9,20 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ - /** @addtogroup CMSIS * @{ */ @@ -70,7 +68,7 @@ typedef enum /****** Cortex-M0 Processor Exceptions Numbers **************************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ - SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ @@ -581,7 +579,7 @@ typedef struct /******************************************************************************/ /* - * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) + * @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ /* Note: No specific macro feature on this device */ @@ -669,7 +667,7 @@ typedef struct #define ADC_CFGR1_ALIGN_Pos (5U) #define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ -#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignement */ +#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignment */ #define ADC_CFGR1_EXTSEL_Pos (6U) #define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ @@ -3024,7 +3022,7 @@ typedef struct /* */ /*****************************************************************************/ /* -* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) +* @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ #define RCC_PLLSRC_PREDIV1_SUPPORT /*!< PREDIV support used as PLL source input */ @@ -3140,8 +3138,8 @@ typedef struct #define RCC_CFGR_PPRE_DIV16_Msk (0x7UL << RCC_CFGR_PPRE_DIV16_Pos) /*!< 0x00000700 */ #define RCC_CFGR_PPRE_DIV16 RCC_CFGR_PPRE_DIV16_Msk /*!< HCLK divided by 16 */ -#define RCC_CFGR_PLLSRC_Pos (16U) -#define RCC_CFGR_PLLSRC_Msk (0x1UL << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */ +#define RCC_CFGR_PLLSRC_Pos (15U) +#define RCC_CFGR_PLLSRC_Msk (0x3UL << RCC_CFGR_PLLSRC_Pos) /*!< 0x00018000 */ #define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */ #define RCC_CFGR_PLLSRC_HSI_DIV2 (0x00000000U) /*!< HSI clock divided by 2 selected as PLL entry clock source */ #define RCC_CFGR_PLLSRC_HSI_PREDIV (0x00008000U) /*!< HSI/PREDIV clock selected as PLL entry clock source */ @@ -3636,7 +3634,7 @@ typedef struct /* */ /*****************************************************************************/ /* -* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) +* @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ #define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */ #define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */ @@ -4120,7 +4118,7 @@ typedef struct /*****************************************************************************/ /* - * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) + * @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ /* Note: No specific macro feature on this device */ @@ -5092,7 +5090,7 @@ typedef struct /******************************************************************************/ /* -* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) +* @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ /* Support of 7 bits data length feature */ @@ -5784,6 +5782,7 @@ typedef struct #define USART3_8_IRQn USART3_6_IRQn #define USART3_4_IRQn USART3_6_IRQn +#define SVC_IRQn SVCall_IRQn /* Aliases for __IRQHandler */ #define ADC1_COMP_IRQHandler ADC1_IRQHandler @@ -5811,4 +5810,3 @@ typedef struct * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm32f0xx/Include/stm32f031x6.h b/stm32f0xx/Include/stm32f031x6.h index ae1784e..900e85a 100644 --- a/stm32f0xx/Include/stm32f031x6.h +++ b/stm32f0xx/Include/stm32f031x6.h @@ -9,22 +9,20 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ - /** @addtogroup CMSIS * @{ */ @@ -70,7 +68,7 @@ typedef enum /****** Cortex-M0 Processor Exceptions Numbers **************************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ - SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ @@ -559,7 +557,7 @@ typedef struct /******************************************************************************/ /* - * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) + * @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ #define ADC_CHANNEL_VBAT_SUPPORT /*!< ADC feature available only on specific devices: ADC internal channel Vbat */ @@ -647,7 +645,7 @@ typedef struct #define ADC_CFGR1_ALIGN_Pos (5U) #define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ -#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignement */ +#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignment */ #define ADC_CFGR1_EXTSEL_Pos (6U) #define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ @@ -2857,7 +2855,7 @@ typedef struct /* */ /*****************************************************************************/ /* -* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) +* @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ /******************** Bit definition for RCC_CR register *******************/ @@ -3416,7 +3414,7 @@ typedef struct /* */ /*****************************************************************************/ /* -* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) +* @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ #define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */ #define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */ @@ -3905,7 +3903,7 @@ typedef struct /*****************************************************************************/ /* - * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) + * @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ #define SPI_I2S_SUPPORT /*!< I2S support */ @@ -4926,7 +4924,7 @@ typedef struct /******************************************************************************/ /* -* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) +* @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ /* Support of LIN feature */ @@ -5659,21 +5657,22 @@ typedef struct #define ADC1_COMP_IRQn ADC1_IRQn #define DMA1_Ch1_IRQn DMA1_Channel1_IRQn #define DMA1_Ch2_3_DMA2_Ch1_2_IRQn DMA1_Channel2_3_IRQn -#define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn #define DMA1_Ch4_7_DMA2_Ch3_5_IRQn DMA1_Channel4_5_IRQn -#define PVD_VDDIO2_IRQn PVD_IRQn +#define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn #define VDDIO2_IRQn PVD_IRQn +#define PVD_VDDIO2_IRQn PVD_IRQn #define RCC_CRS_IRQn RCC_IRQn +#define SVC_IRQn SVCall_IRQn /* Aliases for __IRQHandler */ #define ADC1_COMP_IRQHandler ADC1_IRQHandler #define DMA1_Ch1_IRQHandler DMA1_Channel1_IRQHandler #define DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler DMA1_Channel2_3_IRQHandler -#define DMA1_Channel4_5_6_7_IRQHandler DMA1_Channel4_5_IRQHandler #define DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler DMA1_Channel4_5_IRQHandler -#define PVD_VDDIO2_IRQHandler PVD_IRQHandler +#define DMA1_Channel4_5_6_7_IRQHandler DMA1_Channel4_5_IRQHandler #define VDDIO2_IRQHandler PVD_IRQHandler +#define PVD_VDDIO2_IRQHandler PVD_IRQHandler #define RCC_CRS_IRQHandler RCC_IRQHandler @@ -5691,4 +5690,3 @@ typedef struct * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm32f0xx/Include/stm32f038xx.h b/stm32f0xx/Include/stm32f038xx.h index 7cc29df..ceb7e42 100644 --- a/stm32f0xx/Include/stm32f038xx.h +++ b/stm32f0xx/Include/stm32f038xx.h @@ -9,22 +9,20 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ - /** @addtogroup CMSIS * @{ */ @@ -70,7 +68,7 @@ typedef enum /****** Cortex-M0 Processor Exceptions Numbers **************************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ - SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ @@ -558,7 +556,7 @@ typedef struct /******************************************************************************/ /* - * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) + * @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ #define ADC_CHANNEL_VBAT_SUPPORT /*!< ADC feature available only on specific devices: ADC internal channel Vbat */ @@ -646,7 +644,7 @@ typedef struct #define ADC_CFGR1_ALIGN_Pos (5U) #define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ -#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignement */ +#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignment */ #define ADC_CFGR1_EXTSEL_Pos (6U) #define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ @@ -2832,7 +2830,7 @@ typedef struct /* */ /*****************************************************************************/ /* -* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) +* @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ /******************** Bit definition for RCC_CR register *******************/ @@ -3388,7 +3386,7 @@ typedef struct /* */ /*****************************************************************************/ /* -* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) +* @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ #define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */ #define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */ @@ -3877,7 +3875,7 @@ typedef struct /*****************************************************************************/ /* - * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) + * @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ #define SPI_I2S_SUPPORT /*!< I2S support */ @@ -4895,7 +4893,7 @@ typedef struct /******************************************************************************/ /* -* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) +* @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ /* Support of LIN feature */ @@ -5632,6 +5630,7 @@ typedef struct #define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn #define RCC_CRS_IRQn RCC_IRQn +#define SVC_IRQn SVCall_IRQn /* Aliases for __IRQHandler */ #define ADC1_COMP_IRQHandler ADC1_IRQHandler @@ -5656,4 +5655,3 @@ typedef struct * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm32f0xx/Include/stm32f042x6.h b/stm32f0xx/Include/stm32f042x6.h index 82d0a3e..931cffc 100644 --- a/stm32f0xx/Include/stm32f042x6.h +++ b/stm32f0xx/Include/stm32f042x6.h @@ -9,22 +9,20 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ - /** @addtogroup CMSIS * @{ */ @@ -70,7 +68,7 @@ typedef enum /****** Cortex-M0 Processor Exceptions Numbers **************************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ - SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ @@ -728,7 +726,7 @@ typedef struct /******************************************************************************/ /* - * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) + * @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ #define ADC_CHANNEL_VBAT_SUPPORT /*!< ADC feature available only on specific devices: ADC internal channel Vbat */ @@ -816,7 +814,7 @@ typedef struct #define ADC_CFGR1_ALIGN_Pos (5U) #define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ -#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignement */ +#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignment */ #define ADC_CFGR1_EXTSEL_Pos (6U) #define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ @@ -4741,10 +4739,13 @@ typedef struct #define CEC_TXDR_TXD CEC_TXDR_TXD_Msk /*!< CEC Tx Data */ /******************* Bit definition for CEC_RXDR register *******************/ -#define CEC_TXDR_RXD_Pos (0U) -#define CEC_TXDR_RXD_Msk (0xFFUL << CEC_TXDR_RXD_Pos) /*!< 0x000000FF */ -#define CEC_TXDR_RXD CEC_TXDR_RXD_Msk /*!< CEC Rx Data */ - +#define CEC_RXDR_RXD_Pos (0U) +#define CEC_RXDR_RXD_Msk (0xFFUL << CEC_RXDR_RXD_Pos) /*!< 0x000000FF */ +#define CEC_RXDR_RXD CEC_RXDR_RXD_Msk /*!< CEC Rx Data */ +/* Legacy aliases */ +#define CEC_TXDR_RXD_Pos CEC_RXDR_RXD_Pos +#define CEC_TXDR_RXD_Msk CEC_RXDR_RXD_Msk +#define CEC_TXDR_RXD CEC_RXDR_RXD /******************* Bit definition for CEC_ISR register ********************/ #define CEC_ISR_RXBR_Pos (0U) #define CEC_ISR_RXBR_Msk (0x1UL << CEC_ISR_RXBR_Pos) /*!< 0x00000001 */ @@ -7016,7 +7017,7 @@ typedef struct /* */ /*****************************************************************************/ /* -* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) +* @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ #define RCC_HSI48_SUPPORT /*!< HSI48 feature support */ #define RCC_PLLSRC_PREDIV1_SUPPORT /*!< PREDIV support used as PLL source input */ @@ -7673,7 +7674,7 @@ typedef struct /* */ /*****************************************************************************/ /* -* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) +* @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ #define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */ #define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */ @@ -8162,7 +8163,7 @@ typedef struct /*****************************************************************************/ /* - * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) + * @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ #define SPI_I2S_SUPPORT /*!< I2S support */ @@ -9730,7 +9731,7 @@ typedef struct /******************************************************************************/ /* -* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) +* @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ /* Support of 7 bits data length feature */ @@ -10642,24 +10643,24 @@ typedef struct #define ADC1_COMP_IRQn ADC1_IRQn #define DMA1_Ch1_IRQn DMA1_Channel1_IRQn #define DMA1_Ch2_3_DMA2_Ch1_2_IRQn DMA1_Channel2_3_IRQn -#define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn #define DMA1_Ch4_7_DMA2_Ch3_5_IRQn DMA1_Channel4_5_IRQn -#define VDDIO2_IRQn PVD_VDDIO2_IRQn +#define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn #define PVD_IRQn PVD_VDDIO2_IRQn +#define VDDIO2_IRQn PVD_VDDIO2_IRQn #define RCC_IRQn RCC_CRS_IRQn +#define SVC_IRQn SVCall_IRQn /* Aliases for __IRQHandler */ #define ADC1_COMP_IRQHandler ADC1_IRQHandler #define DMA1_Ch1_IRQHandler DMA1_Channel1_IRQHandler #define DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler DMA1_Channel2_3_IRQHandler -#define DMA1_Channel4_5_6_7_IRQHandler DMA1_Channel4_5_IRQHandler #define DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler DMA1_Channel4_5_IRQHandler -#define VDDIO2_IRQHandler PVD_VDDIO2_IRQHandler +#define DMA1_Channel4_5_6_7_IRQHandler DMA1_Channel4_5_IRQHandler #define PVD_IRQHandler PVD_VDDIO2_IRQHandler +#define VDDIO2_IRQHandler PVD_VDDIO2_IRQHandler #define RCC_IRQHandler RCC_CRS_IRQHandler - #ifdef __cplusplus } #endif /* __cplusplus */ @@ -10674,4 +10675,3 @@ typedef struct * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm32f0xx/Include/stm32f048xx.h b/stm32f0xx/Include/stm32f048xx.h index 0a7e466..a80fa9b 100644 --- a/stm32f0xx/Include/stm32f048xx.h +++ b/stm32f0xx/Include/stm32f048xx.h @@ -9,22 +9,20 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ - /** @addtogroup CMSIS * @{ */ @@ -70,7 +68,7 @@ typedef enum /****** Cortex-M0 Processor Exceptions Numbers **************************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ - SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ @@ -728,7 +726,7 @@ typedef struct /******************************************************************************/ /* - * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) + * @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ #define ADC_CHANNEL_VBAT_SUPPORT /*!< ADC feature available only on specific devices: ADC internal channel Vbat */ @@ -816,7 +814,7 @@ typedef struct #define ADC_CFGR1_ALIGN_Pos (5U) #define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ -#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignement */ +#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignment */ #define ADC_CFGR1_EXTSEL_Pos (6U) #define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ @@ -4741,10 +4739,13 @@ typedef struct #define CEC_TXDR_TXD CEC_TXDR_TXD_Msk /*!< CEC Tx Data */ /******************* Bit definition for CEC_RXDR register *******************/ -#define CEC_TXDR_RXD_Pos (0U) -#define CEC_TXDR_RXD_Msk (0xFFUL << CEC_TXDR_RXD_Pos) /*!< 0x000000FF */ -#define CEC_TXDR_RXD CEC_TXDR_RXD_Msk /*!< CEC Rx Data */ - +#define CEC_RXDR_RXD_Pos (0U) +#define CEC_RXDR_RXD_Msk (0xFFUL << CEC_RXDR_RXD_Pos) /*!< 0x000000FF */ +#define CEC_RXDR_RXD CEC_RXDR_RXD_Msk /*!< CEC Rx Data */ +/* Legacy aliases */ +#define CEC_TXDR_RXD_Pos CEC_RXDR_RXD_Pos +#define CEC_TXDR_RXD_Msk CEC_RXDR_RXD_Msk +#define CEC_TXDR_RXD CEC_RXDR_RXD /******************* Bit definition for CEC_ISR register ********************/ #define CEC_ISR_RXBR_Pos (0U) #define CEC_ISR_RXBR_Msk (0x1UL << CEC_ISR_RXBR_Pos) /*!< 0x00000001 */ @@ -6992,7 +6993,7 @@ typedef struct /* */ /*****************************************************************************/ /* -* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) +* @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ #define RCC_HSI48_SUPPORT /*!< HSI48 feature support */ #define RCC_PLLSRC_PREDIV1_SUPPORT /*!< PREDIV support used as PLL source input */ @@ -7646,7 +7647,7 @@ typedef struct /* */ /*****************************************************************************/ /* -* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) +* @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ #define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */ #define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */ @@ -8135,7 +8136,7 @@ typedef struct /*****************************************************************************/ /* - * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) + * @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ #define SPI_I2S_SUPPORT /*!< I2S support */ @@ -9694,7 +9695,7 @@ typedef struct /******************************************************************************/ /* -* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) +* @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ /* Support of 7 bits data length feature */ @@ -10606,23 +10607,23 @@ typedef struct #define ADC1_COMP_IRQn ADC1_IRQn #define DMA1_Ch1_IRQn DMA1_Channel1_IRQn #define DMA1_Ch2_3_DMA2_Ch1_2_IRQn DMA1_Channel2_3_IRQn -#define DMA1_Ch4_7_DMA2_Ch3_5_IRQn DMA1_Channel4_5_IRQn #define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn +#define DMA1_Ch4_7_DMA2_Ch3_5_IRQn DMA1_Channel4_5_IRQn #define RCC_IRQn RCC_CRS_IRQn -#define PVD_IRQn VDDIO2_IRQn #define PVD_VDDIO2_IRQn VDDIO2_IRQn +#define PVD_IRQn VDDIO2_IRQn +#define SVC_IRQn SVCall_IRQn /* Aliases for __IRQHandler */ #define ADC1_COMP_IRQHandler ADC1_IRQHandler #define DMA1_Ch1_IRQHandler DMA1_Channel1_IRQHandler #define DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler DMA1_Channel2_3_IRQHandler -#define DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler DMA1_Channel4_5_IRQHandler #define DMA1_Channel4_5_6_7_IRQHandler DMA1_Channel4_5_IRQHandler +#define DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler DMA1_Channel4_5_IRQHandler #define RCC_IRQHandler RCC_CRS_IRQHandler -#define PVD_IRQHandler VDDIO2_IRQHandler #define PVD_VDDIO2_IRQHandler VDDIO2_IRQHandler - +#define PVD_IRQHandler VDDIO2_IRQHandler #ifdef __cplusplus } @@ -10638,4 +10639,3 @@ typedef struct * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm32f0xx/Include/stm32f051x8.h b/stm32f0xx/Include/stm32f051x8.h index 9d4b5dc..57fea2d 100644 --- a/stm32f0xx/Include/stm32f051x8.h +++ b/stm32f0xx/Include/stm32f051x8.h @@ -9,22 +9,20 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ - /** @addtogroup CMSIS * @{ */ @@ -70,7 +68,7 @@ typedef enum /****** Cortex-M0 Processor Exceptions Numbers **************************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ - SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ @@ -665,7 +663,7 @@ typedef struct /******************************************************************************/ /* - * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) + * @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ #define ADC_CHANNEL_VBAT_SUPPORT /*!< ADC feature available only on specific devices: ADC internal channel Vbat */ @@ -753,7 +751,7 @@ typedef struct #define ADC_CFGR1_ALIGN_Pos (5U) #define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ -#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignement */ +#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignment */ #define ADC_CFGR1_EXTSEL_Pos (6U) #define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ @@ -1023,10 +1021,13 @@ typedef struct #define CEC_TXDR_TXD CEC_TXDR_TXD_Msk /*!< CEC Tx Data */ /******************* Bit definition for CEC_RXDR register *******************/ -#define CEC_TXDR_RXD_Pos (0U) -#define CEC_TXDR_RXD_Msk (0xFFUL << CEC_TXDR_RXD_Pos) /*!< 0x000000FF */ -#define CEC_TXDR_RXD CEC_TXDR_RXD_Msk /*!< CEC Rx Data */ - +#define CEC_RXDR_RXD_Pos (0U) +#define CEC_RXDR_RXD_Msk (0xFFUL << CEC_RXDR_RXD_Pos) /*!< 0x000000FF */ +#define CEC_RXDR_RXD CEC_RXDR_RXD_Msk /*!< CEC Rx Data */ +/* Legacy aliases */ +#define CEC_TXDR_RXD_Pos CEC_RXDR_RXD_Pos +#define CEC_TXDR_RXD_Msk CEC_RXDR_RXD_Msk +#define CEC_TXDR_RXD CEC_RXDR_RXD /******************* Bit definition for CEC_ISR register ********************/ #define CEC_ISR_RXBR_Pos (0U) #define CEC_ISR_RXBR_Msk (0x1UL << CEC_ISR_RXBR_Pos) /*!< 0x00000001 */ @@ -1265,7 +1266,7 @@ typedef struct /******************************************************************************/ /* - * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) + * @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ /* Note: No specific macro feature on this device */ @@ -3303,7 +3304,7 @@ typedef struct /* */ /*****************************************************************************/ /* -* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) +* @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ /******************** Bit definition for RCC_CR register *******************/ @@ -3913,7 +3914,7 @@ typedef struct /* */ /*****************************************************************************/ /* -* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) +* @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ #define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */ #define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */ @@ -4402,7 +4403,7 @@ typedef struct /*****************************************************************************/ /* - * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) + * @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ #define SPI_I2S_SUPPORT /*!< I2S support */ @@ -5955,7 +5956,7 @@ typedef struct /******************************************************************************/ /* -* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) +* @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ /* Support of LIN feature */ @@ -6746,6 +6747,7 @@ typedef struct #define RCC_CRS_IRQn RCC_IRQn #define TIM6_IRQn TIM6_DAC_IRQn +#define SVC_IRQn SVCall_IRQn /* Aliases for __IRQHandler */ #define ADC1_IRQHandler ADC1_COMP_IRQHandler @@ -6758,7 +6760,6 @@ typedef struct #define RCC_CRS_IRQHandler RCC_IRQHandler #define TIM6_IRQHandler TIM6_DAC_IRQHandler - #ifdef __cplusplus } #endif /* __cplusplus */ @@ -6773,4 +6774,3 @@ typedef struct * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm32f0xx/Include/stm32f058xx.h b/stm32f0xx/Include/stm32f058xx.h index 7843a28..c6f1653 100644 --- a/stm32f0xx/Include/stm32f058xx.h +++ b/stm32f0xx/Include/stm32f058xx.h @@ -9,22 +9,20 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ - /** @addtogroup CMSIS * @{ */ @@ -70,7 +68,7 @@ typedef enum /****** Cortex-M0 Processor Exceptions Numbers **************************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ - SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ @@ -664,7 +662,7 @@ typedef struct /******************************************************************************/ /* - * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) + * @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ #define ADC_CHANNEL_VBAT_SUPPORT /*!< ADC feature available only on specific devices: ADC internal channel Vbat */ @@ -752,7 +750,7 @@ typedef struct #define ADC_CFGR1_ALIGN_Pos (5U) #define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ -#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignement */ +#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignment */ #define ADC_CFGR1_EXTSEL_Pos (6U) #define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ @@ -1022,10 +1020,13 @@ typedef struct #define CEC_TXDR_TXD CEC_TXDR_TXD_Msk /*!< CEC Tx Data */ /******************* Bit definition for CEC_RXDR register *******************/ -#define CEC_TXDR_RXD_Pos (0U) -#define CEC_TXDR_RXD_Msk (0xFFUL << CEC_TXDR_RXD_Pos) /*!< 0x000000FF */ -#define CEC_TXDR_RXD CEC_TXDR_RXD_Msk /*!< CEC Rx Data */ - +#define CEC_RXDR_RXD_Pos (0U) +#define CEC_RXDR_RXD_Msk (0xFFUL << CEC_RXDR_RXD_Pos) /*!< 0x000000FF */ +#define CEC_RXDR_RXD CEC_RXDR_RXD_Msk /*!< CEC Rx Data */ +/* Legacy aliases */ +#define CEC_TXDR_RXD_Pos CEC_RXDR_RXD_Pos +#define CEC_TXDR_RXD_Msk CEC_RXDR_RXD_Msk +#define CEC_TXDR_RXD CEC_RXDR_RXD /******************* Bit definition for CEC_ISR register ********************/ #define CEC_ISR_RXBR_Pos (0U) #define CEC_ISR_RXBR_Msk (0x1UL << CEC_ISR_RXBR_Pos) /*!< 0x00000001 */ @@ -1264,7 +1265,7 @@ typedef struct /******************************************************************************/ /* - * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) + * @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ /* Note: No specific macro feature on this device */ @@ -3278,7 +3279,7 @@ typedef struct /* */ /*****************************************************************************/ /* -* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) +* @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ /******************** Bit definition for RCC_CR register *******************/ @@ -3885,7 +3886,7 @@ typedef struct /* */ /*****************************************************************************/ /* -* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) +* @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ #define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */ #define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */ @@ -4374,7 +4375,7 @@ typedef struct /*****************************************************************************/ /* - * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) + * @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ #define SPI_I2S_SUPPORT /*!< I2S support */ @@ -5924,7 +5925,7 @@ typedef struct /******************************************************************************/ /* -* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) +* @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ /* Support of LIN feature */ @@ -6713,6 +6714,7 @@ typedef struct #define RCC_CRS_IRQn RCC_IRQn #define TIM6_IRQn TIM6_DAC_IRQn +#define SVC_IRQn SVCall_IRQn /* Aliases for __IRQHandler */ #define ADC1_IRQHandler ADC1_COMP_IRQHandler @@ -6723,7 +6725,6 @@ typedef struct #define RCC_CRS_IRQHandler RCC_IRQHandler #define TIM6_IRQHandler TIM6_DAC_IRQHandler - #ifdef __cplusplus } #endif /* __cplusplus */ @@ -6738,4 +6739,3 @@ typedef struct * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm32f0xx/Include/stm32f070x6.h b/stm32f0xx/Include/stm32f070x6.h index 42d68fa..b624bd5 100644 --- a/stm32f0xx/Include/stm32f070x6.h +++ b/stm32f0xx/Include/stm32f070x6.h @@ -9,22 +9,20 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ - /** @addtogroup CMSIS * @{ */ @@ -70,7 +68,7 @@ typedef enum /****** Cortex-M0 Processor Exceptions Numbers **************************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ - SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ @@ -594,7 +592,7 @@ typedef struct /******************************************************************************/ /* - * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) + * @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ /* Note: No specific macro feature on this device */ @@ -682,7 +680,7 @@ typedef struct #define ADC_CFGR1_ALIGN_Pos (5U) #define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ -#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignement */ +#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignment */ #define ADC_CFGR1_EXTSEL_Pos (6U) #define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ @@ -2784,7 +2782,7 @@ typedef struct /* */ /*****************************************************************************/ /* -* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) +* @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ #define RCC_PLLSRC_PREDIV1_SUPPORT /*!< PREDIV support used as PLL source input */ @@ -3370,7 +3368,7 @@ typedef struct /* */ /*****************************************************************************/ /* -* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) +* @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ #define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */ #define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */ @@ -3830,7 +3828,7 @@ typedef struct /*****************************************************************************/ /* - * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) + * @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ /* Note: No specific macro feature on this device */ @@ -4807,7 +4805,7 @@ typedef struct /******************************************************************************/ /* -* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) +* @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ /* Support of 7 bits data length feature */ @@ -5593,6 +5591,7 @@ typedef struct #define DMA1_Ch4_7_DMA2_Ch3_5_IRQn DMA1_Channel4_5_IRQn #define RCC_CRS_IRQn RCC_IRQn +#define SVC_IRQn SVCall_IRQn /* Aliases for __IRQHandler */ #define ADC1_COMP_IRQHandler ADC1_IRQHandler @@ -5617,4 +5616,3 @@ typedef struct * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm32f0xx/Include/stm32f070xb.h b/stm32f0xx/Include/stm32f070xb.h index 08e4707..7b6c6f9 100644 --- a/stm32f0xx/Include/stm32f070xb.h +++ b/stm32f0xx/Include/stm32f070xb.h @@ -9,22 +9,20 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ - /** @addtogroup CMSIS * @{ */ @@ -70,7 +68,7 @@ typedef enum /****** Cortex-M0 Processor Exceptions Numbers **************************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ - SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ @@ -617,7 +615,7 @@ typedef struct /******************************************************************************/ /* - * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) + * @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ /* Note: No specific macro feature on this device */ @@ -705,7 +703,7 @@ typedef struct #define ADC_CFGR1_ALIGN_Pos (5U) #define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ -#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignement */ +#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignment */ #define ADC_CFGR1_EXTSEL_Pos (6U) #define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ @@ -2876,7 +2874,7 @@ typedef struct /* */ /*****************************************************************************/ /* -* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) +* @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ #define RCC_PLLSRC_PREDIV1_SUPPORT /*!< PREDIV support used as PLL source input */ @@ -3504,7 +3502,7 @@ typedef struct /* */ /*****************************************************************************/ /* -* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) +* @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ #define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */ #define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */ @@ -3988,7 +3986,7 @@ typedef struct /*****************************************************************************/ /* - * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) + * @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ /* Note: No specific macro feature on this device */ @@ -4959,7 +4957,7 @@ typedef struct /******************************************************************************/ /* -* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) +* @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ /* Support of 7 bits data length feature */ @@ -5769,24 +5767,25 @@ typedef struct #define ADC1_COMP_IRQn ADC1_IRQn #define DMA1_Ch1_IRQn DMA1_Channel1_IRQn #define DMA1_Ch2_3_DMA2_Ch1_2_IRQn DMA1_Channel2_3_IRQn -#define DMA1_Ch4_7_DMA2_Ch3_5_IRQn DMA1_Channel4_5_IRQn #define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn +#define DMA1_Ch4_7_DMA2_Ch3_5_IRQn DMA1_Channel4_5_IRQn #define RCC_CRS_IRQn RCC_IRQn #define TIM6_DAC_IRQn TIM6_IRQn -#define USART3_8_IRQn USART3_4_IRQn #define USART3_6_IRQn USART3_4_IRQn +#define USART3_8_IRQn USART3_4_IRQn +#define SVC_IRQn SVCall_IRQn /* Aliases for __IRQHandler */ #define ADC1_COMP_IRQHandler ADC1_IRQHandler #define DMA1_Ch1_IRQHandler DMA1_Channel1_IRQHandler #define DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler DMA1_Channel2_3_IRQHandler -#define DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler DMA1_Channel4_5_IRQHandler #define DMA1_Channel4_5_6_7_IRQHandler DMA1_Channel4_5_IRQHandler +#define DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler DMA1_Channel4_5_IRQHandler #define RCC_CRS_IRQHandler RCC_IRQHandler #define TIM6_DAC_IRQHandler TIM6_IRQHandler -#define USART3_8_IRQHandler USART3_4_IRQHandler #define USART3_6_IRQHandler USART3_4_IRQHandler +#define USART3_8_IRQHandler USART3_4_IRQHandler #ifdef __cplusplus @@ -5803,4 +5802,3 @@ typedef struct * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm32f0xx/Include/stm32f071xb.h b/stm32f0xx/Include/stm32f071xb.h index 7694ebb..1e093c5 100644 --- a/stm32f0xx/Include/stm32f071xb.h +++ b/stm32f0xx/Include/stm32f071xb.h @@ -9,22 +9,20 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ - /** @addtogroup CMSIS * @{ */ @@ -70,7 +68,7 @@ typedef enum /****** Cortex-M0 Processor Exceptions Numbers **************************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ - SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ @@ -699,7 +697,7 @@ typedef struct /******************************************************************************/ /* - * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) + * @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ #define ADC_CHANNEL_VBAT_SUPPORT /*!< ADC feature available only on specific devices: ADC internal channel Vbat */ @@ -787,7 +785,7 @@ typedef struct #define ADC_CFGR1_ALIGN_Pos (5U) #define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ -#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignement */ +#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignment */ #define ADC_CFGR1_EXTSEL_Pos (6U) #define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ @@ -1057,10 +1055,13 @@ typedef struct #define CEC_TXDR_TXD CEC_TXDR_TXD_Msk /*!< CEC Tx Data */ /******************* Bit definition for CEC_RXDR register *******************/ -#define CEC_TXDR_RXD_Pos (0U) -#define CEC_TXDR_RXD_Msk (0xFFUL << CEC_TXDR_RXD_Pos) /*!< 0x000000FF */ -#define CEC_TXDR_RXD CEC_TXDR_RXD_Msk /*!< CEC Rx Data */ - +#define CEC_RXDR_RXD_Pos (0U) +#define CEC_RXDR_RXD_Msk (0xFFUL << CEC_RXDR_RXD_Pos) /*!< 0x000000FF */ +#define CEC_RXDR_RXD CEC_RXDR_RXD_Msk /*!< CEC Rx Data */ +/* Legacy aliases */ +#define CEC_TXDR_RXD_Pos CEC_RXDR_RXD_Pos +#define CEC_TXDR_RXD_Msk CEC_RXDR_RXD_Msk +#define CEC_TXDR_RXD CEC_RXDR_RXD /******************* Bit definition for CEC_ISR register ********************/ #define CEC_ISR_RXBR_Pos (0U) #define CEC_ISR_RXBR_Msk (0x1UL << CEC_ISR_RXBR_Pos) /*!< 0x00000001 */ @@ -1268,7 +1269,7 @@ typedef struct /******************************************************************************/ /* -* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) +* @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ /* Support of Programmable Polynomial size and value feature */ @@ -1416,7 +1417,7 @@ typedef struct /******************************************************************************/ /* - * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) + * @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ #define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: availability of DAC channel 2 */ @@ -3693,7 +3694,7 @@ typedef struct /* */ /*****************************************************************************/ /* -* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) +* @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ #define RCC_HSI48_SUPPORT /*!< HSI48 feature support */ #define RCC_PLLSRC_PREDIV1_SUPPORT /*!< PREDIV support used as PLL source input */ @@ -4389,7 +4390,7 @@ typedef struct /* */ /*****************************************************************************/ /* -* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) +* @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ #define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */ #define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */ @@ -4912,7 +4913,7 @@ typedef struct /*****************************************************************************/ /* - * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) + * @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ #define SPI_I2S_SUPPORT /*!< I2S support */ @@ -6508,7 +6509,7 @@ typedef struct /******************************************************************************/ /* -* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) +* @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ /* Support of 7 bits data length feature */ @@ -7342,6 +7343,7 @@ typedef struct #define USART3_6_IRQn USART3_4_IRQn #define USART3_8_IRQn USART3_4_IRQn +#define SVC_IRQn SVCall_IRQn /* Aliases for __IRQHandler */ #define ADC1_IRQHandler ADC1_COMP_IRQHandler @@ -7356,7 +7358,6 @@ typedef struct #define USART3_6_IRQHandler USART3_4_IRQHandler #define USART3_8_IRQHandler USART3_4_IRQHandler - #ifdef __cplusplus } #endif /* __cplusplus */ @@ -7371,4 +7372,3 @@ typedef struct * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm32f0xx/Include/stm32f072xb.h b/stm32f0xx/Include/stm32f072xb.h index 52ca444..9ed1de8 100644 --- a/stm32f0xx/Include/stm32f072xb.h +++ b/stm32f0xx/Include/stm32f072xb.h @@ -9,22 +9,20 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ - /** @addtogroup CMSIS * @{ */ @@ -70,7 +68,7 @@ typedef enum /****** Cortex-M0 Processor Exceptions Numbers **************************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ - SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ @@ -803,7 +801,7 @@ typedef struct /******************************************************************************/ /* - * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) + * @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ #define ADC_CHANNEL_VBAT_SUPPORT /*!< ADC feature available only on specific devices: ADC internal channel Vbat */ @@ -891,7 +889,7 @@ typedef struct #define ADC_CFGR1_ALIGN_Pos (5U) #define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ -#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignement */ +#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignment */ #define ADC_CFGR1_EXTSEL_Pos (6U) #define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ @@ -4816,10 +4814,13 @@ typedef struct #define CEC_TXDR_TXD CEC_TXDR_TXD_Msk /*!< CEC Tx Data */ /******************* Bit definition for CEC_RXDR register *******************/ -#define CEC_TXDR_RXD_Pos (0U) -#define CEC_TXDR_RXD_Msk (0xFFUL << CEC_TXDR_RXD_Pos) /*!< 0x000000FF */ -#define CEC_TXDR_RXD CEC_TXDR_RXD_Msk /*!< CEC Rx Data */ - +#define CEC_RXDR_RXD_Pos (0U) +#define CEC_RXDR_RXD_Msk (0xFFUL << CEC_RXDR_RXD_Pos) /*!< 0x000000FF */ +#define CEC_RXDR_RXD CEC_RXDR_RXD_Msk /*!< CEC Rx Data */ +/* Legacy aliases */ +#define CEC_TXDR_RXD_Pos CEC_RXDR_RXD_Pos +#define CEC_TXDR_RXD_Msk CEC_RXDR_RXD_Msk +#define CEC_TXDR_RXD CEC_RXDR_RXD /******************* Bit definition for CEC_ISR register ********************/ #define CEC_ISR_RXBR_Pos (0U) #define CEC_ISR_RXBR_Msk (0x1UL << CEC_ISR_RXBR_Pos) /*!< 0x00000001 */ @@ -5027,7 +5028,7 @@ typedef struct /******************************************************************************/ /* -* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) +* @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ /* Support of Programmable Polynomial size and value feature */ @@ -5175,7 +5176,7 @@ typedef struct /******************************************************************************/ /* - * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) + * @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ #define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: availability of DAC channel 2 */ @@ -7463,7 +7464,7 @@ typedef struct /* */ /*****************************************************************************/ /* -* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) +* @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ #define RCC_HSI48_SUPPORT /*!< HSI48 feature support */ #define RCC_PLLSRC_PREDIV1_SUPPORT /*!< PREDIV support used as PLL source input */ @@ -8186,7 +8187,7 @@ typedef struct /* */ /*****************************************************************************/ /* -* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) +* @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ #define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */ #define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */ @@ -8709,7 +8710,7 @@ typedef struct /*****************************************************************************/ /* - * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) + * @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ #define SPI_I2S_SUPPORT /*!< I2S support */ @@ -10305,7 +10306,7 @@ typedef struct /******************************************************************************/ /* -* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) +* @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ /* Support of 7 bits data length feature */ @@ -11266,29 +11267,29 @@ typedef struct #define ADC1_IRQn ADC1_COMP_IRQn #define DMA1_Ch1_IRQn DMA1_Channel1_IRQn #define DMA1_Ch2_3_DMA2_Ch1_2_IRQn DMA1_Channel2_3_IRQn -#define DMA1_Channel4_5_IRQn DMA1_Channel4_5_6_7_IRQn #define DMA1_Ch4_7_DMA2_Ch3_5_IRQn DMA1_Channel4_5_6_7_IRQn -#define VDDIO2_IRQn PVD_VDDIO2_IRQn +#define DMA1_Channel4_5_IRQn DMA1_Channel4_5_6_7_IRQn #define PVD_IRQn PVD_VDDIO2_IRQn +#define VDDIO2_IRQn PVD_VDDIO2_IRQn #define RCC_IRQn RCC_CRS_IRQn #define TIM6_IRQn TIM6_DAC_IRQn -#define USART3_8_IRQn USART3_4_IRQn #define USART3_6_IRQn USART3_4_IRQn +#define USART3_8_IRQn USART3_4_IRQn +#define SVC_IRQn SVCall_IRQn /* Aliases for __IRQHandler */ #define ADC1_IRQHandler ADC1_COMP_IRQHandler #define DMA1_Ch1_IRQHandler DMA1_Channel1_IRQHandler #define DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler DMA1_Channel2_3_IRQHandler -#define DMA1_Channel4_5_IRQHandler DMA1_Channel4_5_6_7_IRQHandler #define DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler DMA1_Channel4_5_6_7_IRQHandler -#define VDDIO2_IRQHandler PVD_VDDIO2_IRQHandler +#define DMA1_Channel4_5_IRQHandler DMA1_Channel4_5_6_7_IRQHandler #define PVD_IRQHandler PVD_VDDIO2_IRQHandler +#define VDDIO2_IRQHandler PVD_VDDIO2_IRQHandler #define RCC_IRQHandler RCC_CRS_IRQHandler #define TIM6_IRQHandler TIM6_DAC_IRQHandler -#define USART3_8_IRQHandler USART3_4_IRQHandler #define USART3_6_IRQHandler USART3_4_IRQHandler - +#define USART3_8_IRQHandler USART3_4_IRQHandler #ifdef __cplusplus } @@ -11304,4 +11305,3 @@ typedef struct * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm32f0xx/Include/stm32f078xx.h b/stm32f0xx/Include/stm32f078xx.h index 7e99f49..7e029fe 100644 --- a/stm32f0xx/Include/stm32f078xx.h +++ b/stm32f0xx/Include/stm32f078xx.h @@ -9,22 +9,20 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ - /** @addtogroup CMSIS * @{ */ @@ -70,7 +68,7 @@ typedef enum /****** Cortex-M0 Processor Exceptions Numbers **************************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ - SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ @@ -803,7 +801,7 @@ typedef struct /******************************************************************************/ /* - * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) + * @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ #define ADC_CHANNEL_VBAT_SUPPORT /*!< ADC feature available only on specific devices: ADC internal channel Vbat */ @@ -891,7 +889,7 @@ typedef struct #define ADC_CFGR1_ALIGN_Pos (5U) #define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ -#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignement */ +#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignment */ #define ADC_CFGR1_EXTSEL_Pos (6U) #define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ @@ -4816,10 +4814,13 @@ typedef struct #define CEC_TXDR_TXD CEC_TXDR_TXD_Msk /*!< CEC Tx Data */ /******************* Bit definition for CEC_RXDR register *******************/ -#define CEC_TXDR_RXD_Pos (0U) -#define CEC_TXDR_RXD_Msk (0xFFUL << CEC_TXDR_RXD_Pos) /*!< 0x000000FF */ -#define CEC_TXDR_RXD CEC_TXDR_RXD_Msk /*!< CEC Rx Data */ - +#define CEC_RXDR_RXD_Pos (0U) +#define CEC_RXDR_RXD_Msk (0xFFUL << CEC_RXDR_RXD_Pos) /*!< 0x000000FF */ +#define CEC_RXDR_RXD CEC_RXDR_RXD_Msk /*!< CEC Rx Data */ +/* Legacy aliases */ +#define CEC_TXDR_RXD_Pos CEC_RXDR_RXD_Pos +#define CEC_TXDR_RXD_Msk CEC_RXDR_RXD_Msk +#define CEC_TXDR_RXD CEC_RXDR_RXD /******************* Bit definition for CEC_ISR register ********************/ #define CEC_ISR_RXBR_Pos (0U) #define CEC_ISR_RXBR_Msk (0x1UL << CEC_ISR_RXBR_Pos) /*!< 0x00000001 */ @@ -5027,7 +5028,7 @@ typedef struct /******************************************************************************/ /* -* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) +* @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ /* Support of Programmable Polynomial size and value feature */ @@ -5175,7 +5176,7 @@ typedef struct /******************************************************************************/ /* - * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) + * @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ #define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: availability of DAC channel 2 */ @@ -7439,7 +7440,7 @@ typedef struct /* */ /*****************************************************************************/ /* -* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) +* @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ #define RCC_HSI48_SUPPORT /*!< HSI48 feature support */ #define RCC_PLLSRC_PREDIV1_SUPPORT /*!< PREDIV support used as PLL source input */ @@ -8159,7 +8160,7 @@ typedef struct /* */ /*****************************************************************************/ /* -* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) +* @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ #define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */ #define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */ @@ -8682,7 +8683,7 @@ typedef struct /*****************************************************************************/ /* - * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) + * @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ #define SPI_I2S_SUPPORT /*!< I2S support */ @@ -10275,7 +10276,7 @@ typedef struct /******************************************************************************/ /* -* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) +* @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ /* Support of 7 bits data length feature */ @@ -11240,11 +11241,12 @@ typedef struct #define DMA1_Ch4_7_DMA2_Ch3_5_IRQn DMA1_Channel4_5_6_7_IRQn #define RCC_IRQn RCC_CRS_IRQn #define TIM6_IRQn TIM6_DAC_IRQn -#define USART3_8_IRQn USART3_4_IRQn #define USART3_6_IRQn USART3_4_IRQn +#define USART3_8_IRQn USART3_4_IRQn #define PVD_IRQn VDDIO2_IRQn #define PVD_VDDIO2_IRQn VDDIO2_IRQn +#define SVC_IRQn SVCall_IRQn /* Aliases for __IRQHandler */ #define ADC1_IRQHandler ADC1_COMP_IRQHandler @@ -11254,12 +11256,11 @@ typedef struct #define DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler DMA1_Channel4_5_6_7_IRQHandler #define RCC_IRQHandler RCC_CRS_IRQHandler #define TIM6_IRQHandler TIM6_DAC_IRQHandler -#define USART3_8_IRQHandler USART3_4_IRQHandler #define USART3_6_IRQHandler USART3_4_IRQHandler +#define USART3_8_IRQHandler USART3_4_IRQHandler #define PVD_IRQHandler VDDIO2_IRQHandler #define PVD_VDDIO2_IRQHandler VDDIO2_IRQHandler - #ifdef __cplusplus } #endif /* __cplusplus */ @@ -11274,4 +11275,3 @@ typedef struct * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm32f0xx/Include/stm32f091xc.h b/stm32f0xx/Include/stm32f091xc.h index b5ef517..a6c15c4 100644 --- a/stm32f0xx/Include/stm32f091xc.h +++ b/stm32f0xx/Include/stm32f091xc.h @@ -9,22 +9,20 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ - /** @addtogroup CMSIS * @{ */ @@ -70,7 +68,7 @@ typedef enum /****** Cortex-M0 Processor Exceptions Numbers **************************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ - SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ @@ -785,7 +783,7 @@ typedef struct /******************************************************************************/ /* - * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) + * @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ #define ADC_CHANNEL_VBAT_SUPPORT /*!< ADC feature available only on specific devices: ADC internal channel Vbat */ @@ -873,7 +871,7 @@ typedef struct #define ADC_CFGR1_ALIGN_Pos (5U) #define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ -#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignement */ +#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignment */ #define ADC_CFGR1_EXTSEL_Pos (6U) #define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ @@ -4798,10 +4796,13 @@ typedef struct #define CEC_TXDR_TXD CEC_TXDR_TXD_Msk /*!< CEC Tx Data */ /******************* Bit definition for CEC_RXDR register *******************/ -#define CEC_TXDR_RXD_Pos (0U) -#define CEC_TXDR_RXD_Msk (0xFFUL << CEC_TXDR_RXD_Pos) /*!< 0x000000FF */ -#define CEC_TXDR_RXD CEC_TXDR_RXD_Msk /*!< CEC Rx Data */ - +#define CEC_RXDR_RXD_Pos (0U) +#define CEC_RXDR_RXD_Msk (0xFFUL << CEC_RXDR_RXD_Pos) /*!< 0x000000FF */ +#define CEC_RXDR_RXD CEC_RXDR_RXD_Msk /*!< CEC Rx Data */ +/* Legacy aliases */ +#define CEC_TXDR_RXD_Pos CEC_RXDR_RXD_Pos +#define CEC_TXDR_RXD_Msk CEC_RXDR_RXD_Msk +#define CEC_TXDR_RXD CEC_RXDR_RXD /******************* Bit definition for CEC_ISR register ********************/ #define CEC_ISR_RXBR_Pos (0U) #define CEC_ISR_RXBR_Msk (0x1UL << CEC_ISR_RXBR_Pos) /*!< 0x00000001 */ @@ -5009,7 +5010,7 @@ typedef struct /******************************************************************************/ /* -* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) +* @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ /* Support of Programmable Polynomial size and value feature */ @@ -5157,7 +5158,7 @@ typedef struct /******************************************************************************/ /* - * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) + * @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ #define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: availability of DAC channel 2 */ @@ -7926,7 +7927,7 @@ typedef struct /* */ /*****************************************************************************/ /* -* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) +* @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ #define RCC_HSI48_SUPPORT /*!< HSI48 feature support */ #define RCC_PLLSRC_PREDIV1_SUPPORT /*!< PREDIV support used as PLL source input */ @@ -8659,7 +8660,7 @@ typedef struct /* */ /*****************************************************************************/ /* -* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) +* @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ #define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */ #define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */ @@ -9182,7 +9183,7 @@ typedef struct /*****************************************************************************/ /* - * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) + * @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ #define SPI_I2S_SUPPORT /*!< I2S support */ @@ -10962,7 +10963,7 @@ typedef struct /******************************************************************************/ /* -* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) +* @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ /* Support of 7 bits data length feature */ @@ -11826,6 +11827,7 @@ typedef struct #define USART3_6_IRQn USART3_8_IRQn #define USART3_4_IRQn USART3_8_IRQn +#define SVC_IRQn SVCall_IRQn /* Aliases for __IRQHandler */ #define ADC1_IRQHandler ADC1_COMP_IRQHandler @@ -11840,7 +11842,6 @@ typedef struct #define USART3_6_IRQHandler USART3_8_IRQHandler #define USART3_4_IRQHandler USART3_8_IRQHandler - #ifdef __cplusplus } #endif /* __cplusplus */ @@ -11855,4 +11856,3 @@ typedef struct * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm32f0xx/Include/stm32f098xx.h b/stm32f0xx/Include/stm32f098xx.h index 16873ba..cf4d0d6 100644 --- a/stm32f0xx/Include/stm32f098xx.h +++ b/stm32f0xx/Include/stm32f098xx.h @@ -9,22 +9,20 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ - /** @addtogroup CMSIS * @{ */ @@ -70,7 +68,7 @@ typedef enum /****** Cortex-M0 Processor Exceptions Numbers **************************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ - SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ @@ -785,7 +783,7 @@ typedef struct /******************************************************************************/ /* - * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) + * @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ #define ADC_CHANNEL_VBAT_SUPPORT /*!< ADC feature available only on specific devices: ADC internal channel Vbat */ @@ -873,7 +871,7 @@ typedef struct #define ADC_CFGR1_ALIGN_Pos (5U) #define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ -#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignement */ +#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignment */ #define ADC_CFGR1_EXTSEL_Pos (6U) #define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ @@ -4798,10 +4796,13 @@ typedef struct #define CEC_TXDR_TXD CEC_TXDR_TXD_Msk /*!< CEC Tx Data */ /******************* Bit definition for CEC_RXDR register *******************/ -#define CEC_TXDR_RXD_Pos (0U) -#define CEC_TXDR_RXD_Msk (0xFFUL << CEC_TXDR_RXD_Pos) /*!< 0x000000FF */ -#define CEC_TXDR_RXD CEC_TXDR_RXD_Msk /*!< CEC Rx Data */ - +#define CEC_RXDR_RXD_Pos (0U) +#define CEC_RXDR_RXD_Msk (0xFFUL << CEC_RXDR_RXD_Pos) /*!< 0x000000FF */ +#define CEC_RXDR_RXD CEC_RXDR_RXD_Msk /*!< CEC Rx Data */ +/* Legacy aliases */ +#define CEC_TXDR_RXD_Pos CEC_RXDR_RXD_Pos +#define CEC_TXDR_RXD_Msk CEC_RXDR_RXD_Msk +#define CEC_TXDR_RXD CEC_RXDR_RXD /******************* Bit definition for CEC_ISR register ********************/ #define CEC_ISR_RXBR_Pos (0U) #define CEC_ISR_RXBR_Msk (0x1UL << CEC_ISR_RXBR_Pos) /*!< 0x00000001 */ @@ -5009,7 +5010,7 @@ typedef struct /******************************************************************************/ /* -* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) +* @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ /* Support of Programmable Polynomial size and value feature */ @@ -5157,7 +5158,7 @@ typedef struct /******************************************************************************/ /* - * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) + * @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ #define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: availability of DAC channel 2 */ @@ -7902,7 +7903,7 @@ typedef struct /* */ /*****************************************************************************/ /* -* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) +* @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ #define RCC_HSI48_SUPPORT /*!< HSI48 feature support */ #define RCC_PLLSRC_PREDIV1_SUPPORT /*!< PREDIV support used as PLL source input */ @@ -8632,7 +8633,7 @@ typedef struct /* */ /*****************************************************************************/ /* -* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) +* @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ #define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */ #define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */ @@ -9155,7 +9156,7 @@ typedef struct /*****************************************************************************/ /* - * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) + * @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ #define SPI_I2S_SUPPORT /*!< I2S support */ @@ -10929,7 +10930,7 @@ typedef struct /******************************************************************************/ /* -* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) +* @brief Specific device feature definitions (not present on all devices in the STM32F0 series) */ /* Support of 7 bits data length feature */ @@ -11784,29 +11785,29 @@ typedef struct #define ADC1_IRQn ADC1_COMP_IRQn #define DMA1_Channel1_IRQn DMA1_Ch1_IRQn #define DMA1_Channel2_3_IRQn DMA1_Ch2_3_DMA2_Ch1_2_IRQn -#define DMA1_Channel4_5_IRQn DMA1_Ch4_7_DMA2_Ch3_5_IRQn #define DMA1_Channel4_5_6_7_IRQn DMA1_Ch4_7_DMA2_Ch3_5_IRQn +#define DMA1_Channel4_5_IRQn DMA1_Ch4_7_DMA2_Ch3_5_IRQn #define RCC_IRQn RCC_CRS_IRQn #define TIM6_IRQn TIM6_DAC_IRQn -#define USART3_4_IRQn USART3_8_IRQn #define USART3_6_IRQn USART3_8_IRQn -#define PVD_IRQn VDDIO2_IRQn +#define USART3_4_IRQn USART3_8_IRQn #define PVD_VDDIO2_IRQn VDDIO2_IRQn +#define PVD_IRQn VDDIO2_IRQn +#define SVC_IRQn SVCall_IRQn /* Aliases for __IRQHandler */ #define ADC1_IRQHandler ADC1_COMP_IRQHandler #define DMA1_Channel1_IRQHandler DMA1_Ch1_IRQHandler #define DMA1_Channel2_3_IRQHandler DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler -#define DMA1_Channel4_5_IRQHandler DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler #define DMA1_Channel4_5_6_7_IRQHandler DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler +#define DMA1_Channel4_5_IRQHandler DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler #define RCC_IRQHandler RCC_CRS_IRQHandler #define TIM6_IRQHandler TIM6_DAC_IRQHandler -#define USART3_4_IRQHandler USART3_8_IRQHandler #define USART3_6_IRQHandler USART3_8_IRQHandler -#define PVD_IRQHandler VDDIO2_IRQHandler +#define USART3_4_IRQHandler USART3_8_IRQHandler #define PVD_VDDIO2_IRQHandler VDDIO2_IRQHandler - +#define PVD_IRQHandler VDDIO2_IRQHandler #ifdef __cplusplus } @@ -11822,4 +11823,3 @@ typedef struct * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm32f0xx/Include/stm32f0xx.h b/stm32f0xx/Include/stm32f0xx.h index 1b88a51..4c2e41a 100644 --- a/stm32f0xx/Include/stm32f0xx.h +++ b/stm32f0xx/Include/stm32f0xx.h @@ -8,25 +8,23 @@ * is using in the C source code, usually in main.c. This file contains: * - Configuration section that allows to select: * - The STM32F0xx device used in the target application - * - To use or not the peripherals drivers in application code(i.e. - * code will be based on direct access to peripherals registers + * - To use or not the peripheral's drivers in application code(i.e. + * code will be based on direct access to peripheral's registers * rather than drivers API), this option is controlled by * "#define USE_HAL_DRIVER" * ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ - /** @addtogroup CMSIS * @{ */ @@ -59,8 +57,8 @@ * - IRQ channel definition * - Peripheral memory mapping and physical registers address definition * - Peripheral pointer declaration and driver header file inclusion - * - Product miscellaneous configuration: assert macros - * Note: These CMSIS drivers (stm32f0xxxx.h) are always supporting features of the sub-familys superset. + * - Product miscellaneous configuration: assert macros, + * Note: These CMSIS drivers (stm32f0xxxx.h) are always supporting features of the sub-family's superset. */ #if !defined (STM32F030x6) && !defined (STM32F030x8) && \ @@ -104,11 +102,11 @@ #endif /* USE_HAL_DRIVER */ /** - * @brief CMSIS Device version number V2.3.6 + * @brief CMSIS Device version number V2.3.7 */ #define __STM32F0_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */ #define __STM32F0_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */ -#define __STM32F0_DEVICE_VERSION_SUB2 (0x06) /*!< [15:8] sub2 version */ +#define __STM32F0_DEVICE_VERSION_SUB2 (0x07) /*!< [15:8] sub2 version */ #define __STM32F0_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F0_DEVICE_VERSION ((__STM32F0_DEVICE_VERSION_MAIN << 24)\ |(__STM32F0_DEVICE_VERSION_SUB1 << 16)\ @@ -269,7 +267,3 @@ typedef enum * @} */ - - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm32f0xx/Include/system_stm32f0xx.h b/stm32f0xx/Include/system_stm32f0xx.h index ecc2d09..a20c527 100644 --- a/stm32f0xx/Include/system_stm32f0xx.h +++ b/stm32f0xx/Include/system_stm32f0xx.h @@ -6,17 +6,15 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ - /** @addtogroup CMSIS * @{ */ @@ -102,4 +100,4 @@ extern void SystemCoreClockUpdate(void); /** * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/stm32f0xx/Release_Notes.html b/stm32f0xx/Release_Notes.html index 7420dda..6200ca9 100644 --- a/stm32f0xx/Release_Notes.html +++ b/stm32f0xx/Release_Notes.html @@ -5,14 +5,11 @@ Release Notes for STM32F0xx CMSIS -