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Update STM32F0 headers to v2.3.7
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modm update bot committed Mar 17, 2023
1 parent a896f6c commit 61af968
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Showing 20 changed files with 450 additions and 418 deletions.
2 changes: 1 addition & 1 deletion README.md
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Expand Up @@ -14,7 +14,7 @@ as the Cube release version in braces:
- [L1: v2.3.2 created 21-May-2021](https://github.com/STMicroelectronics/STM32CubeL1)
- [L4: v1.7.2 created 26-November-2021](https://github.com/STMicroelectronics/STM32CubeL4)
- [L5: v1.0.5 created 04-November-2022](https://github.com/STMicroelectronics/STM32CubeL5)
- [F0: v2.3.6 created 23-July-2021](https://github.com/STMicroelectronics/STM32CubeF0)
- [F0: v2.3.7 created 27-January-2023](https://github.com/STMicroelectronics/STM32CubeF0)
- [F1: v4.3.3 created 21-May-2021](https://github.com/STMicroelectronics/STM32CubeF1)
- [F2: v2.2.5 created 21-May-2021](https://github.com/STMicroelectronics/STM32CubeF2)
- [F3: v2.3.6 created 23-July-2021](https://github.com/STMicroelectronics/STM32CubeF3)
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32 changes: 15 additions & 17 deletions stm32f0xx/Include/stm32f030x6.h
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Original file line number Diff line number Diff line change
Expand Up @@ -9,22 +9,20 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
* - Macros to access peripherals registers hardware
* - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/

/** @addtogroup CMSIS
* @{
*/
Expand Down Expand Up @@ -70,7 +68,7 @@ typedef enum
/****** Cortex-M0 Processor Exceptions Numbers **************************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */

Expand Down Expand Up @@ -549,7 +547,7 @@ typedef struct
/******************************************************************************/

/*
* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
*/
/* Note: No specific macro feature on this device */

Expand Down Expand Up @@ -637,7 +635,7 @@ typedef struct

#define ADC_CFGR1_ALIGN_Pos (5U)
#define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */
#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignement */
#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignment */

#define ADC_CFGR1_EXTSEL_Pos (6U)
#define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */
Expand Down Expand Up @@ -2731,7 +2729,7 @@ typedef struct
/* */
/*****************************************************************************/
/*
* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
*/

/******************** Bit definition for RCC_CR register *******************/
Expand Down Expand Up @@ -3290,7 +3288,7 @@ typedef struct
/* */
/*****************************************************************************/
/*
* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
*/
#define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */
#define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
Expand Down Expand Up @@ -3750,7 +3748,7 @@ typedef struct
/*****************************************************************************/

/*
* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
*/
/* Note: No specific macro feature on this device */

Expand Down Expand Up @@ -5337,17 +5335,18 @@ typedef struct
#define ADC1_COMP_IRQn ADC1_IRQn
#define DMA1_Ch1_IRQn DMA1_Channel1_IRQn
#define DMA1_Ch2_3_DMA2_Ch1_2_IRQn DMA1_Channel2_3_IRQn
#define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn
#define DMA1_Ch4_7_DMA2_Ch3_5_IRQn DMA1_Channel4_5_IRQn
#define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn
#define RCC_CRS_IRQn RCC_IRQn

#define SVC_IRQn SVCall_IRQn

/* Aliases for __IRQHandler */
#define ADC1_COMP_IRQHandler ADC1_IRQHandler
#define DMA1_Ch1_IRQHandler DMA1_Channel1_IRQHandler
#define DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler DMA1_Channel2_3_IRQHandler
#define DMA1_Channel4_5_6_7_IRQHandler DMA1_Channel4_5_IRQHandler
#define DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler DMA1_Channel4_5_IRQHandler
#define DMA1_Channel4_5_6_7_IRQHandler DMA1_Channel4_5_IRQHandler
#define RCC_CRS_IRQHandler RCC_IRQHandler


Expand All @@ -5365,4 +5364,3 @@ typedef struct
* @}
*/

/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
32 changes: 15 additions & 17 deletions stm32f0xx/Include/stm32f030x8.h
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Original file line number Diff line number Diff line change
Expand Up @@ -9,22 +9,20 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
* - Macros to access peripherals registers hardware
* - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/

/** @addtogroup CMSIS
* @{
*/
Expand Down Expand Up @@ -70,7 +68,7 @@ typedef enum
/****** Cortex-M0 Processor Exceptions Numbers **************************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */

Expand Down Expand Up @@ -565,7 +563,7 @@ typedef struct
/******************************************************************************/

/*
* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
*/
/* Note: No specific macro feature on this device */

Expand Down Expand Up @@ -653,7 +651,7 @@ typedef struct

#define ADC_CFGR1_ALIGN_Pos (5U)
#define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */
#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignement */
#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignment */

#define ADC_CFGR1_EXTSEL_Pos (6U)
#define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */
Expand Down Expand Up @@ -2761,7 +2759,7 @@ typedef struct
/* */
/*****************************************************************************/
/*
* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
*/

/******************** Bit definition for RCC_CR register *******************/
Expand Down Expand Up @@ -3334,7 +3332,7 @@ typedef struct
/* */
/*****************************************************************************/
/*
* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
*/
#define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */
#define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
Expand Down Expand Up @@ -3794,7 +3792,7 @@ typedef struct
/*****************************************************************************/

/*
* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
*/
/* Note: No specific macro feature on this device */

Expand Down Expand Up @@ -5402,18 +5400,19 @@ typedef struct
#define ADC1_COMP_IRQn ADC1_IRQn
#define DMA1_Ch1_IRQn DMA1_Channel1_IRQn
#define DMA1_Ch2_3_DMA2_Ch1_2_IRQn DMA1_Channel2_3_IRQn
#define DMA1_Ch4_7_DMA2_Ch3_5_IRQn DMA1_Channel4_5_IRQn
#define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn
#define DMA1_Ch4_7_DMA2_Ch3_5_IRQn DMA1_Channel4_5_IRQn
#define RCC_CRS_IRQn RCC_IRQn
#define TIM6_DAC_IRQn TIM6_IRQn

#define SVC_IRQn SVCall_IRQn

/* Aliases for __IRQHandler */
#define ADC1_COMP_IRQHandler ADC1_IRQHandler
#define DMA1_Ch1_IRQHandler DMA1_Channel1_IRQHandler
#define DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler DMA1_Channel2_3_IRQHandler
#define DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler DMA1_Channel4_5_IRQHandler
#define DMA1_Channel4_5_6_7_IRQHandler DMA1_Channel4_5_IRQHandler
#define DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler DMA1_Channel4_5_IRQHandler
#define RCC_CRS_IRQHandler RCC_IRQHandler
#define TIM6_DAC_IRQHandler TIM6_IRQHandler

Expand All @@ -5432,4 +5431,3 @@ typedef struct
* @}
*/

/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
34 changes: 16 additions & 18 deletions stm32f0xx/Include/stm32f030xc.h
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Original file line number Diff line number Diff line change
Expand Up @@ -9,22 +9,20 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
* - Macros to access peripherals registers hardware
* - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/

/** @addtogroup CMSIS
* @{
*/
Expand Down Expand Up @@ -70,7 +68,7 @@ typedef enum
/****** Cortex-M0 Processor Exceptions Numbers **************************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */

Expand Down Expand Up @@ -581,7 +579,7 @@ typedef struct
/******************************************************************************/

/*
* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
*/
/* Note: No specific macro feature on this device */

Expand Down Expand Up @@ -669,7 +667,7 @@ typedef struct

#define ADC_CFGR1_ALIGN_Pos (5U)
#define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */
#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignement */
#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignment */

#define ADC_CFGR1_EXTSEL_Pos (6U)
#define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */
Expand Down Expand Up @@ -3024,7 +3022,7 @@ typedef struct
/* */
/*****************************************************************************/
/*
* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
*/
#define RCC_PLLSRC_PREDIV1_SUPPORT /*!< PREDIV support used as PLL source input */

Expand Down Expand Up @@ -3140,8 +3138,8 @@ typedef struct
#define RCC_CFGR_PPRE_DIV16_Msk (0x7UL << RCC_CFGR_PPRE_DIV16_Pos) /*!< 0x00000700 */
#define RCC_CFGR_PPRE_DIV16 RCC_CFGR_PPRE_DIV16_Msk /*!< HCLK divided by 16 */

#define RCC_CFGR_PLLSRC_Pos (16U)
#define RCC_CFGR_PLLSRC_Msk (0x1UL << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
#define RCC_CFGR_PLLSRC_Pos (15U)
#define RCC_CFGR_PLLSRC_Msk (0x3UL << RCC_CFGR_PLLSRC_Pos) /*!< 0x00018000 */
#define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */
#define RCC_CFGR_PLLSRC_HSI_DIV2 (0x00000000U) /*!< HSI clock divided by 2 selected as PLL entry clock source */
#define RCC_CFGR_PLLSRC_HSI_PREDIV (0x00008000U) /*!< HSI/PREDIV clock selected as PLL entry clock source */
Expand Down Expand Up @@ -3636,7 +3634,7 @@ typedef struct
/* */
/*****************************************************************************/
/*
* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
*/
#define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */
#define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
Expand Down Expand Up @@ -4120,7 +4118,7 @@ typedef struct
/*****************************************************************************/

/*
* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
*/
/* Note: No specific macro feature on this device */

Expand Down Expand Up @@ -5092,7 +5090,7 @@ typedef struct
/******************************************************************************/

/*
* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
*/

/* Support of 7 bits data length feature */
Expand Down Expand Up @@ -5784,6 +5782,7 @@ typedef struct
#define USART3_8_IRQn USART3_6_IRQn
#define USART3_4_IRQn USART3_6_IRQn

#define SVC_IRQn SVCall_IRQn

/* Aliases for __IRQHandler */
#define ADC1_COMP_IRQHandler ADC1_IRQHandler
Expand Down Expand Up @@ -5811,4 +5810,3 @@ typedef struct
* @}
*/

/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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