Simulator for engine-V
Designed from scratch on saturday, simulator to pass the RISCV requirements as set by the RISCV SoftCPU Contest 2018.
Compiled with Delphi XE7, should compile under Tokyo too (not tested)
Get free Delphi Community Edition if you want to try out.
Test binaries included https://github.com/micro-FPGA/engine-V-simulator/tree/master/Win32/Debug/images
Status:
- passes all RV32I tests
- runs Dhrystone
- runs Zephyr Hello World, Philosophers and Synchronization
Binary files are loaded to address 0
Console UART is byte write to address 0xC000 (C as in Console)