add registers for unused vals?

makslevental · Mar 15, 2024 · a23f5f5 · a23f5f5
1 parent e9b5383
commit a23f5f5
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Showing 2 changed files with 3 additions and 2 deletions.
diff --git a/openhls/ir/parse.py b/openhls/ir/parse.py
@@ -102,6 +102,7 @@ def parse_mlir_module(module_str):
                 value_float = float(str(value).split(":")[0])
                 csts[res_val] = value_float
             else:
+                vals.add(res_val)
                 vals.update(set(args))
 
             start_time = reg_start_time.findall(line)

diff --git a/openhls/rtl/emit_verilog.py b/openhls/rtl/emit_verilog.py
@@ -53,7 +53,7 @@ def make_pe_always(fsm, pe, op_datas: list[Op], vals, input_wires, ip_res_val_ma
     not_latches = set()
     for op in op_datas:
         if DEBUG:
-            tree_conds.append(f"\n\t// {op.emit()} start")
+            tree_conds.append(f"\n\t// {op.emit()} start"[:100])
         ip = getattr(pe, op.type.value, None)
         args = op.args
         start_time = op.attrs["start_time"]
@@ -103,7 +103,7 @@ def make_pe_always(fsm, pe, op_datas: list[Op], vals, input_wires, ip_res_val_ma
             raise NotImplementedError(str(op))
 
         if DEBUG:
-            tree_conds.append(f"\t// {op.emit()} end\n")
+            tree_conds.append(f"\t// {op.emit()} end\n"[:100])
 
     return make_always_tree(tree_conds, not_latches)