Merge branch 'devel'

lnls-dig · Aug 30, 2017 · be19bc6 · be19bc6
2 parents d4341f4 + 04f8cd5
commit be19bc6
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Showing 5 changed files with 621 additions and 403 deletions.
diff --git a/hdl/ip_cores/dsp-cores b/hdl/ip_cores/dsp-cores
diff --git a/hdl/ip_cores/general-cores b/hdl/ip_cores/general-cores
+ −		doc/wb_onewire_master.pdf
+ −		doc/wb_spi.pdf
+3 −1		modules/common/Manifest.py
+185 −0		modules/common/gc_async_signals_input_stage.vhd
+10 −6		modules/common/gc_bicolor_led_ctrl.vhd
+7 −7		modules/common/gc_frequency_meter.vhd
+57 −49		modules/common/gc_i2c_slave.vhd
+39 −101		modules/common/gc_moving_average.vhd
+5 −3		modules/common/gc_serial_dac.vhd
+126 −0		modules/common/gc_single_reset_gen.vhd
+11 −2		modules/common/gc_sync_ffs.vhd
+14 −0		modules/common/gc_sync_register.vhd
+63 −12		modules/common/gencores_pkg.vhd
+0 −3		modules/genrams/altera/gc_shiftreg.vhd
+1 −1		modules/genrams/common/generic_shiftreg_fifo.vhd
+19 −31		modules/genrams/common/inferred_sync_fifo.vhd
+15 −1		modules/genrams/genram_pkg.vhd
+177 −128		modules/genrams/memory_loader_pkg.vhd
+1 −0		modules/genrams/xilinx/Manifest.py
+58 −2		modules/genrams/xilinx/generic_dpram.vhd
+31 −12		modules/genrams/xilinx/generic_dpram_dualclock.vhd
+96 −38		modules/genrams/xilinx/generic_dpram_sameclock.vhd
+233 −0		modules/genrams/xilinx/generic_dpram_split.vhd
+4 −2		modules/wishbone/Manifest.py
+5 −0		modules/wishbone/wb_axi4lite_bridge/Manifest.py
+224 −0		modules/wishbone/wb_axi4lite_bridge/axi4_pkg.vhd
+102 −0		modules/wishbone/wb_axi4lite_bridge/wb_axi4lite_bridge.vhd
+167 −0		modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd
+7 −0		modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd
+1 −0		modules/wishbone/wb_crossbar/Manifest.py
+96 −26		modules/wishbone/wb_crossbar/sdb_rom.vhd
+77 −0		modules/wishbone/wb_crossbar/wb_skidpad.vhd
+40 −14		modules/wishbone/wb_crossbar/xwb_crossbar.vhd
+47 −24		modules/wishbone/wb_crossbar/xwb_register_link.vhd
+127 −88		modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd
+1 −2		modules/wishbone/wb_dpram/Manifest.py
+7 −52		modules/wishbone/wb_dpram/xwb_dpram.vhd
+31 −20		modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd
+22 −14		modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd
+24 −15		modules/wishbone/wb_i2c_master/i2c_master_top.vhd
+6 −1		modules/wishbone/wb_i2c_master/wb_i2c_master.vhd
+10 −1		modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd
+1 −0		modules/wishbone/wb_lm32/README.txt
+23 −6		modules/wishbone/wb_lm32/gen_lmcores.py
+81,981 −694		modules/wishbone/wb_lm32/generated/lm32_allprofiles.v
+84 −3		modules/wishbone/wb_lm32/generated/xwb_lm32.vhd
+2 −1		modules/wishbone/wb_lm32/lm32.profiles
+163 −46		modules/wishbone/wb_lm32/src/lm32_cpu.v
+29 −0		modules/wishbone/wb_lm32/src/lm32_debug.v
+6 −1		modules/wishbone/wb_lm32/src/lm32_include.v
+286 −313		modules/wishbone/wb_lm32/src/lm32_instruction_unit.v
+97 −165		modules/wishbone/wb_lm32/src/lm32_load_store_unit.v
+9 −4		modules/wishbone/wb_onewire_master/sockit_owm.v
+17 −3		modules/wishbone/wb_onewire_master/wb_onewire_master.vhd
+18 −3		modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd
+7 −1		modules/wishbone/wb_spi/spi_clgen.v
+11 −5		modules/wishbone/wb_spi/spi_shift.v
+13 −8		modules/wishbone/wb_spi/spi_top.v
+9 −0		modules/wishbone/wb_spi/wb_spi.vhd
+8 −0		modules/wishbone/wb_spi/xwb_spi.vhd
+8 −8		modules/wishbone/wb_uart/simple_uart_pkg.vhd
+2 −12		modules/wishbone/wb_uart/simple_uart_wb.vhd
+5 −1		modules/wishbone/wb_uart/wb_simple_uart.vhd
+3 −1		modules/wishbone/wb_uart/xwb_simple_uart.vhd
+23 −4		modules/wishbone/wb_vic/wb_vic.vhd
+6 −3		modules/wishbone/wb_vic/xwb_vic.vhd
+4 −0		modules/wishbone/wbgenplus/Manifest.py
+143 −0		modules/wishbone/wbgenplus/wbgenplus_pkg.vhd
+290 −77		modules/wishbone/wishbone_pkg.vhd
+4 −2		platform/altera/networks/arria2gx/dual_region.txt
+3 −2		platform/altera/networks/arria2gx/global_region.txt
+4 −2		platform/altera/networks/arria2gx/single_region.txt
+8 −6		platform/altera/wb_pcie/arria2_pcie_hip.txt
+7 −4		platform/altera/wb_pcie/arria2_pcie_reconf.txt
+3 −3		platform/altera/wb_pcie/pcie_wb.vhd
+1 −4		platform/altera/wb_pcie/pcie_wb_pkg.vhd
+4 −0		testbench/wishbone/lm32_testsys/Manifest.py