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Submodule dsp-cores
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79 files
Submodule general-cores
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Submodule infra-cores
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Original file line number | Diff line number | Diff line change |
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library UNISIM; | ||
use UNISIM.vcomponents.all; | ||
|
||
library ieee; | ||
use ieee.std_logic_1164.all; | ||
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entity clk_gen_mgt is | ||
port( | ||
sys_clk_p_i : in std_logic; | ||
sys_clk_n_i : in std_logic; | ||
sys_clk_o : out std_logic; | ||
sys_clk_bufg_o : out std_logic | ||
); | ||
end clk_gen_mgt; | ||
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architecture syn of clk_gen_mgt is | ||
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-- Internal clock signal | ||
signal s_sys_clk : std_logic; | ||
signal s_sys_clk_ibuf_p : std_logic; | ||
signal s_sys_clk_ibuf_n : std_logic; | ||
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begin | ||
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cmp_ibuf_clk_gen_mgt_p : IBUF | ||
generic map ( | ||
IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards | ||
IOSTANDARD => "DEFAULT" | ||
) | ||
port map ( | ||
O => s_sys_clk_ibuf_p, -- Buffer output | ||
I => sys_clk_p_i -- Buffer input (connect directly to top-level port) | ||
); | ||
|
||
cmp_ibuf_clk_gen_mgt_n : IBUF | ||
generic map ( | ||
IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards | ||
IOSTANDARD => "DEFAULT" | ||
) | ||
port map ( | ||
O => s_sys_clk_ibuf_n, -- Buffer output | ||
I => sys_clk_n_i -- Buffer input (connect directly to top-level port) | ||
); | ||
|
||
cpm_ibufgds_clk_gen_mgt : IBUFDS_GTE2 | ||
port map ( | ||
O => s_sys_clk, -- Clock buffer output | ||
ODIV2 => open, | ||
CEB => '0', | ||
I => s_sys_clk_ibuf_p, -- Diff_p clock buffer input (connect directly to top-level port) | ||
IB => s_sys_clk_ibuf_n -- Diff_n clock buffer input (connect directly to top-level port) | ||
); | ||
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sys_clk_o <= s_sys_clk; | ||
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cmp_bufg_clk_gen_mgt : BUFG | ||
port map ( | ||
O => sys_clk_bufg_o, -- 1-bit output: Clock buffer output | ||
I => s_sys_clk -- 1-bit input: Clock buffer input | ||
); | ||
|
||
end syn; |
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