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lerwys committed Apr 3, 2019
2 parents e0a2f39 + 6cff95f commit 6c17bfc
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2 changes: 1 addition & 1 deletion hdl/ip_cores/dsp-cores
Submodule dsp-cores updated 79 files
+18 −0 .gitignore
+8 −4 hdl/modules/cic/cic_dual.vhd
+177 −25 hdl/modules/cic/cic_dyn.vhd
+1 −0 hdl/modules/downconv/downconv.vhd
+26 −5 hdl/modules/dsp_cores_pkg.vhd
+5 −0 hdl/modules/input_gen/input_gen.vhd
+6 −3 hdl/modules/machine/sirius_bo_250M/Manifest.py
+181 −0 hdl/modules/machine/sirius_bo_250M/cos_lut_sirius_52_181/cos_lut_sirius_52_181.mif
+122 −5 hdl/modules/machine/sirius_bo_250M/cos_lut_sirius_52_181/cos_lut_sirius_52_181.xci
+353 −0 hdl/modules/machine/sirius_bo_250M/cos_lut_sirius_52_181/synth/cos_lut_sirius_52_181.vhd
+32 −11 hdl/modules/machine/sirius_bo_250M/dds_cos_lut.vhd
+32 −11 hdl/modules/machine/sirius_bo_250M/dds_sin_lut.vhd
+181 −0 hdl/modules/machine/sirius_bo_250M/sin_lut_sirius_52_181/sin_lut_sirius_52_181.mif
+122 −5 hdl/modules/machine/sirius_bo_250M/sin_lut_sirius_52_181/sin_lut_sirius_52_181.xci
+353 −0 hdl/modules/machine/sirius_bo_250M/sin_lut_sirius_52_181/synth/sin_lut_sirius_52_181.vhd
+140 −5 hdl/modules/machine/sirius_bo_250M/sw_windowing_n_251_tukey_0_2/sw_windowing_n_251_tukey_0_2.xci
+353 −0 hdl/modules/machine/sirius_bo_250M/sw_windowing_n_251_tukey_0_2/synth/sw_windowing_n_251_tukey_0_2.vhd
+6 −3 hdl/modules/machine/sirius_sr_130M/Manifest.py
+203 −0 hdl/modules/machine/sirius_sr_130M/cos_lut_sirius_52_203/cos_lut_sirius_52_203.mif
+128 −5 hdl/modules/machine/sirius_sr_130M/cos_lut_sirius_52_203/cos_lut_sirius_52_203.xci
+353 −0 hdl/modules/machine/sirius_sr_130M/cos_lut_sirius_52_203/synth/cos_lut_sirius_52_203.vhd
+32 −11 hdl/modules/machine/sirius_sr_130M/dds_cos_lut.vhd
+32 −11 hdl/modules/machine/sirius_sr_130M/dds_sin_lut.vhd
+203 −0 hdl/modules/machine/sirius_sr_130M/sin_lut_sirius_52_203/sin_lut_sirius_52_203.mif
+128 −5 hdl/modules/machine/sirius_sr_130M/sin_lut_sirius_52_203/sin_lut_sirius_52_203.xci
+353 −0 hdl/modules/machine/sirius_sr_130M/sin_lut_sirius_52_203/synth/sin_lut_sirius_52_203.vhd
+251 −0 hdl/modules/machine/sirius_sr_130M/sw_windowing_n_251_tukey_0_2/sw_windowing_n_251_tukey_0_2.mif
+311 −181 hdl/modules/machine/sirius_sr_130M/sw_windowing_n_251_tukey_0_2/sw_windowing_n_251_tukey_0_2.xci
+353 −0 hdl/modules/machine/sirius_sr_130M/sw_windowing_n_251_tukey_0_2/synth/sw_windowing_n_251_tukey_0_2.vhd
+6 −3 hdl/modules/machine/sirius_sr_250M/Manifest.py
+191 −0 hdl/modules/machine/sirius_sr_250M/cos_lut_sirius_50_191/cos_lut_sirius_50_191.mif
+122 −5 hdl/modules/machine/sirius_sr_250M/cos_lut_sirius_50_191/cos_lut_sirius_50_191.xci
+353 −0 hdl/modules/machine/sirius_sr_250M/cos_lut_sirius_50_191/synth/cos_lut_sirius_50_191.vhd
+32 −11 hdl/modules/machine/sirius_sr_250M/dds_cos_lut.vhd
+32 −11 hdl/modules/machine/sirius_sr_250M/dds_sin_lut.vhd
+191 −0 hdl/modules/machine/sirius_sr_250M/sin_lut_sirius_50_191/sin_lut_sirius_50_191.mif
+122 −5 hdl/modules/machine/sirius_sr_250M/sin_lut_sirius_50_191/sin_lut_sirius_50_191.xci
+353 −0 hdl/modules/machine/sirius_sr_250M/sin_lut_sirius_50_191/synth/sin_lut_sirius_50_191.vhd
+251 −0 hdl/modules/machine/sirius_sr_250M/sw_windowing_n_251_tukey_0_2/sw_windowing_n_251_tukey_0_2.mif
+140 −5 hdl/modules/machine/sirius_sr_250M/sw_windowing_n_251_tukey_0_2/sw_windowing_n_251_tukey_0_2.xci
+353 −0 hdl/modules/machine/sirius_sr_250M/sw_windowing_n_251_tukey_0_2/synth/sw_windowing_n_251_tukey_0_2.vhd
+6 −3 hdl/modules/machine/uvx_sr_130M/Manifest.py
+148 −0 hdl/modules/machine/uvx_sr_130M/cos_lut_uvx_35_148/cos_lut_uvx_35_148.mif
+307 −181 hdl/modules/machine/uvx_sr_130M/cos_lut_uvx_35_148/cos_lut_uvx_35_148.xci
+353 −0 hdl/modules/machine/uvx_sr_130M/cos_lut_uvx_35_148/synth/cos_lut_uvx_35_148.vhd
+32 −11 hdl/modules/machine/uvx_sr_130M/dds_cos_lut.vhd
+36 −15 hdl/modules/machine/uvx_sr_130M/dds_sin_lut.vhd
+148 −0 hdl/modules/machine/uvx_sr_130M/sin_lut_uvx_35_148/sin_lut_uvx_35_148.mif
+307 −181 hdl/modules/machine/uvx_sr_130M/sin_lut_uvx_35_148/sin_lut_uvx_35_148.xci
+353 −0 hdl/modules/machine/uvx_sr_130M/sin_lut_uvx_35_148/synth/sin_lut_uvx_35_148.vhd
+251 −0 hdl/modules/machine/uvx_sr_130M/sw_windowing_n_251_tukey_0_2/sw_windowing_n_251_tukey_0_2.mif
+311 −181 hdl/modules/machine/uvx_sr_130M/sw_windowing_n_251_tukey_0_2/sw_windowing_n_251_tukey_0_2.xci
+353 −0 hdl/modules/machine/uvx_sr_130M/sw_windowing_n_251_tukey_0_2/synth/sw_windowing_n_251_tukey_0_2.vhd
+6 −3 hdl/modules/machine/uvx_sr_250M/Manifest.py
+65 −0 hdl/modules/machine/uvx_sr_250M/cos_lut_uvx_18_65/cos_lut_uvx_18_65.mif
+122 −5 hdl/modules/machine/uvx_sr_250M/cos_lut_uvx_18_65/cos_lut_uvx_18_65.xci
+353 −0 hdl/modules/machine/uvx_sr_250M/cos_lut_uvx_18_65/synth/cos_lut_uvx_18_65.vhd
+32 −11 hdl/modules/machine/uvx_sr_250M/dds_cos_lut.vhd
+16 −5 hdl/modules/machine/uvx_sr_250M/dds_sin_lut.vhd
+65 −0 hdl/modules/machine/uvx_sr_250M/sin_lut_uvx_18_65/sin_lut_uvx_18_65.mif
+122 −4 hdl/modules/machine/uvx_sr_250M/sin_lut_uvx_18_65/sin_lut_uvx_18_65.xci
+353 −0 hdl/modules/machine/uvx_sr_250M/sin_lut_uvx_18_65/synth/sin_lut_uvx_18_65.vhd
+139 −4 hdl/modules/machine/uvx_sr_250M/sw_windowing_n_251_tukey_0_2/sw_windowing_n_251_tukey_0_2.xci
+3 −0 hdl/modules/part_delta_sigma/part_delta_sigma.vhd
+43 −13 hdl/modules/position_calc/position_calc.vhd
+4 −0 hdl/modules/sw_windowing/input_conditioner.vhd
+2 −1 hdl/modules/wb_position_calc/Manifest.py
+19 −0 hdl/modules/wb_position_calc/position_calc_core_pkg.vhd
+127 −0 hdl/modules/wb_position_calc/trigger2tag.vhd
+87 −34 hdl/modules/wb_position_calc/wb_position_calc_core.vhd
+1,330 −298 hdl/modules/wb_position_calc/wbgen/doc/pos_calc_regs_wb.html
+36 −2 hdl/modules/wb_position_calc/wbgen/pos_calc_regs.h
+391 −181 hdl/modules/wb_position_calc/wbgen/wb_pos_calc_regs.vhd
+83 −0 hdl/modules/wb_position_calc/wbgen/wb_pos_calc_regs.wb
+21 −11 hdl/modules/wb_position_calc/wbgen/wb_pos_calc_regs_pkg.vhd
+12 −0 hdl/modules/wb_position_calc/xwb_position_calc_core.vhd
+13 −0 hdl/sim/regs/wb_pos_calc_regs.vh
+7 −3 hdl/testbench/cic/cic_bench.vhd
+18 −6 hdl/testbench/cic/wave.do
2 changes: 1 addition & 1 deletion hdl/ip_cores/general-cores
Submodule general-cores updated 59 files
+4 −3 modules/common/Manifest.py
+671 −0 modules/common/gc_dec_8b10b.vhd
+114 −0 modules/common/gc_delay_line.vhd
+10 −7 modules/common/gc_extend_pulse.vhd
+29 −0 modules/common/gc_frequency_meter.vhd
+16 −35 modules/common/gc_moving_average.vhd
+28 −0 modules/common/gc_prio_encoder.vhd
+33 −15 modules/common/gc_pulse_synchronizer.vhd
+33 −15 modules/common/gc_pulse_synchronizer2.vhd
+29 −1 modules/common/gc_reset.vhd
+29 −0 modules/common/gc_rr_arbiter.vhd
+1 −0 modules/common/gc_single_reset_gen.vhd
+27 −0 modules/common/gc_sync_register.vhd
+19 −3 modules/common/gencores_pkg.vhd
+3 −3 modules/genrams/common/generic_rom.vhd
+6 −6 modules/genrams/memory_loader_pkg.vhd
+0 −18 modules/genrams/xilinx/generic_dpram_dualclock.vhd
+1 −39 modules/genrams/xilinx/generic_dpram_sameclock.vhd
+17 −1 modules/wishbone/wb_async_bridge/wb_async_bridge.vhd
+30 −0 modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd
+253 −224 modules/wishbone/wb_axi4lite_bridge/axi4_pkg.vhd
+131 −102 modules/wishbone/wb_axi4lite_bridge/wb_axi4lite_bridge.vhd
+196 −167 modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd
+6 −4 modules/wishbone/wb_crossbar/sdb_rom.vhd
+4 −2 modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd
+18 −2 modules/wishbone/wb_dpram/xwb_dpram.vhd
+21 −5 modules/wishbone/wb_gpio_port/wb_gpio_port.vhd
+30 −0 modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd
+18 −2 modules/wishbone/wb_simple_timer/wb_tics.vhd
+30 −0 modules/wishbone/wb_simple_timer/xwb_tics.vhd
+31 −0 modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd
+28 −0 modules/wishbone/wb_spi/wb_spi.vhd
+28 −0 modules/wishbone/wb_spi/xwb_spi.vhd
+29 −0 modules/wishbone/wb_uart/uart_async_rx.vhd
+29 −0 modules/wishbone/wb_uart/uart_async_tx.vhd
+29 −0 modules/wishbone/wb_uart/uart_baud_gen.vhd
+16 −0 modules/wishbone/wb_uart/wb_simple_uart.vhd
+16 −0 modules/wishbone/wb_uart/xwb_simple_uart.vhd
+17 −1 modules/wishbone/wb_vic/wb_vic.vhd
+17 −1 modules/wishbone/wb_vic/xwb_vic.vhd
+29 −0 modules/wishbone/wbgen2/wbgen2_dpssram.vhd
+29 −0 modules/wishbone/wbgen2/wbgen2_eic.vhd
+29 −0 modules/wishbone/wbgen2/wbgen2_fifo_async.vhd
+28 −0 modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd
+29 −0 modules/wishbone/wbgen2/wbgen2_pkg.vhd
+56 −16 modules/wishbone/wishbone_pkg.vhd
+2 −0 testbench/common/gc_bicolor_led_ctrl/.gitignore
+18 −0 testbench/common/gc_bicolor_led_ctrl/Manifest.py
+237 −0 testbench/common/gc_bicolor_led_ctrl/gc_bicolor_led_ctrl_tb.vhd
+12 −0 testbench/common/gc_bicolor_led_ctrl/run.do
+39 −0 testbench/common/gc_bicolor_led_ctrl/wave.do
+4 −0 testbench/common/gc_moving_average/.gitignore
+18 −0 testbench/common/gc_moving_average/Manifest.py
+119 −0 testbench/common/gc_moving_average/gc_moving_average_tb.vhd
+2 −0 testbench/wishbone/wb_gpio_port/.gitignore
+22 −0 testbench/wishbone/wb_gpio_port/Manifest.py
+70 −0 testbench/wishbone/wb_gpio_port/main.sv
+6 −0 testbench/wishbone/wb_gpio_port/run.do
+15 −0 testbench/wishbone/wb_gpio_port/wave.do
2 changes: 1 addition & 1 deletion hdl/ip_cores/infra-cores
Submodule infra-cores updated 190 files
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@ set -e
# Check for uninitialized variables
set -u

COMMAND="(./build_synthesis_sdb.sh; hdlmake; time make; date) 2>&1 | tee make_output &"
COMMAND="(./build_synthesis_sdb.sh; hdlmake -a makefile; time make; date) 2>&1 | tee make_output &"

echo $COMMAND
eval $COMMAND
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@ set -e
# Check for uninitialized variables
set -u

COMMAND="(./build_synthesis_sdb.sh; hdlmake; time make; date) 2>&1 | tee make_output &"
COMMAND="(./build_synthesis_sdb.sh; hdlmake -a makefile; time make; date) 2>&1 | tee make_output &"

echo $COMMAND
eval $COMMAND
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@ set -e
# Check for uninitialized variables
set -u

COMMAND="(./build_synthesis_sdb.sh; hdlmake; time make; date) 2>&1 | tee make_output &"
COMMAND="(./build_synthesis_sdb.sh; hdlmake -a makefile; time make; date) 2>&1 | tee make_output &"

echo $COMMAND
eval $COMMAND
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@ set -e
# Check for uninitialized variables
set -u

COMMAND="(./build_synthesis_sdb.sh; hdlmake; time make; date) 2>&1 | tee make_output &"
COMMAND="(./build_synthesis_sdb.sh; hdlmake -a makefile; time make; date) 2>&1 | tee make_output &"

echo $COMMAND
eval $COMMAND
2 changes: 1 addition & 1 deletion hdl/syn/afc_v3/vivado/dbe_pbpm/build_bitstream_local.sh
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@ set -e
# Check for uninitialized variables
set -u

COMMAND="(./build_synthesis_sdb.sh; hdlmake; time make; date) 2>&1 | tee make_output &"
COMMAND="(./build_synthesis_sdb.sh; hdlmake -a makefile; time make; date) 2>&1 | tee make_output &"

echo $COMMAND
eval $COMMAND
15 changes: 10 additions & 5 deletions hdl/top/afc_v3/vivado/dbe_bpm/Manifest.py
Original file line number Diff line number Diff line change
@@ -1,8 +1,13 @@
files = [ "dbe_bpm.vhd",
"dbe_bpm.xdc",
"pcie_core.xdc",
"ddr_core.xdc",
"dbe_bpm.xcf" ];
filenames = ['pcie_core.xdc', 'ddr_core.xdc', 'dbe_bpm.xdc']
with open('dbe_bpm_gen.xdc', 'w') as outfile:
for fname in filenames:
with open(fname) as infile:
outfile.write(infile.read())

files = [ "dbe_bpm.xcf",
"dbe_bpm_gen.xdc",
"dbe_bpm.vhd"
];

modules = { "local" :
["../../../..",
Expand Down
9 changes: 9 additions & 0 deletions hdl/top/afc_v3/vivado/dbe_bpm/dbe_bpm.vhd
Original file line number Diff line number Diff line change
Expand Up @@ -35,6 +35,9 @@ port(
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;

aux_clk_p_i : in std_logic;
aux_clk_n_i : in std_logic;

-----------------------------------------
-- Reset Button
-----------------------------------------
Expand Down Expand Up @@ -300,6 +303,9 @@ architecture rtl of dbe_bpm is
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;

aux_clk_p_i : in std_logic;
aux_clk_n_i : in std_logic;

-----------------------------------------
-- Reset Button
-----------------------------------------
Expand Down Expand Up @@ -794,6 +800,9 @@ begin
sys_clk_p_i => sys_clk_p_i,
sys_clk_n_i => sys_clk_n_i,

aux_clk_p_i => aux_clk_p_i,
aux_clk_n_i => aux_clk_n_i,

-----------------------------------------
-- Reset Button
-----------------------------------------
Expand Down
28 changes: 25 additions & 3 deletions hdl/top/afc_v3/vivado/dbe_bpm/dbe_bpm.xdc
Original file line number Diff line number Diff line change
Expand Up @@ -10,6 +10,11 @@ set_property PACKAGE_PIN AL7 [get_ports sys_clk_n_i]
set_property IOSTANDARD DIFF_SSTL15 [get_ports sys_clk_n_i]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports sys_clk_n_i]

# LINK01_CLK1_P
set_property PACKAGE_PIN AG18 [get_ports aux_clk_p_i]
# LINK01_CLK1_N
set_property PACKAGE_PIN AH18 [get_ports aux_clk_n_i]

#// TXD IO_25_34
set_property PACKAGE_PIN AB11 [get_ports rs232_txd_o]
set_property IOSTANDARD LVCMOS25 [get_ports rs232_txd_o]
Expand Down Expand Up @@ -932,13 +937,20 @@ set_property IDELAY_VALUE 26 [get_cells -hier -filter {NAME =~ *cmp2_xwb_fmc130m
# 125 MHz AMC TCLKB input clock
create_clock -period 8.000 -name sys_clk_p_i [get_ports sys_clk_p_i]

# 64.440 MHz AMC TCLKB input clock
create_clock -period 14.400 -name aux_clk_p_i [get_ports aux_clk_p_i]

## 100 MHz wihsbone clock
create_generated_clock -name clk_sys [get_pins -hier -filter {NAME =~ *cmp_sys_pll_inst/cmp_sys_pll/CLKOUT0}]
set clk_sys_period [get_property PERIOD [get_clocks clk_sys]]
# 200 MHz DDR3 and IDELAY CONTROL clock
create_generated_clock -name clk_200mhz [get_pins -hier -filter {NAME =~ *cmp_sys_pll_inst/cmp_sys_pll/CLKOUT1}]
set clk_200mhz_period [get_property PERIOD [get_clocks clk_200mhz]]

## 64.440 MHz aux clock
create_generated_clock -name clk_aux [get_pins -hier -filter {NAME =~ *cmp_aux_sys_pll_inst/cmp_sys_pll/CLKOUT0}]
set clk_aux_period [get_property PERIOD [get_clocks clk_aux]]

# DDR3 clock generated by IP
set clk_pll_ddr_period [get_property PERIOD [get_clocks clk_pll_i]]
set clk_pll_ddr_period_less [expr $clk_pll_ddr_period - 1.000]
Expand Down Expand Up @@ -985,8 +997,14 @@ set fmc2_ref_clk_2x_period [get_property PERIOD [get_clo
# Reset synchronization path.
set_false_path -through [get_pins -hier -filter {NAME =~ *cmp_reset/master_rstn_reg/C}]
# Get the cell driving the corresponding net
set reset_ffs [get_nets -hier -filter {NAME =~ *cmp_reset*/master_rstn*}]
set_property ASYNC_REG TRUE [get_cells [all_fanin -flat -only_cells -startpoints_only [get_pins -of_objects [get_nets $reset_ffs]]]]
set reset_sys_ffs [get_nets -hier -filter {NAME =~ *cmp_reset*/master_rstn*}]
set_property ASYNC_REG TRUE [get_cells [all_fanin -flat -only_cells -startpoints_only [get_pins -of_objects [get_nets $reset_sys_ffs]]]]

# Reset synchronization path.
set_false_path -through [get_pins -hier -filter {NAME =~ *cmp_aux_reset/master_rstn_reg/C}]
# Get the cell driving the corresponding net
set reset_aux_ffs [get_nets -hier -filter {NAME =~ *cmp_aux_reset*/master_rstn*}]
set_property ASYNC_REG TRUE [get_cells [all_fanin -flat -only_cells -startpoints_only [get_pins -of_objects [get_nets $reset_aux_ffs]]]]

# DDR 3 temperature monitor reset path
# chain of FFs synched with clk_sys.
Expand Down Expand Up @@ -1122,6 +1140,10 @@ set_max_delay -datapath_only -from [get_pins -hier -filter {NAME =~ *acq_core/*/
# destination clock period
set_max_delay -datapath_only -from [get_pins -hier -filter {NAME =~ *acq_core/*acq_core_regs/*/C}] -to [get_clocks clk_sys] $clk_sys_period

# Aux clock to Sys clock. Path used to/from registers
set_max_delay -datapath_only -from [get_clocks clk_sys] -to [get_clocks clk_aux] $clk_sys_period
set_max_delay -datapath_only -from [get_clocks clk_aux] -to [get_clocks clk_sys] $clk_sys_period

# Use Distributed RAM, as these FIFOs are small and sparse through the module
# Cannot make this work with hierarchical matching... only by specifying the
# whole topology
Expand All @@ -1131,7 +1153,7 @@ set_property RAM_STYLE DISTRIBUTED [get_cells -hier -filter {NAME =~ */cmp_posit
set_property RAM_STYLE DISTRIBUTED [get_cells -hier -filter {NAME =~ */cmp_fmc_adc_iface/*/cmp_adc_data_async_fifo/mem_reg*}]

# Use Distributed RAMs for FMC ACQ FIFOs. They are small and sparse.
set_property RAM_STYLE DISTRIBUTED [get_cells -hier -filter {NAME =~ */cmp_acq_fc_fifo/cmp_fc_source/*.*/*.*/mem_reg*}]
set_property RAM_STYLE DISTRIBUTED [get_cells -hier -filter {NAME =~ */cmp_acq_fc_fifo/cmp_fc_source/*/*ram_reg*}]

#######################################################################
## Placement Constraints ##
Expand Down
5 changes: 4 additions & 1 deletion hdl/top/afc_v3/vivado/dbe_bpm/ddr_core.xdc
Original file line number Diff line number Diff line change
Expand Up @@ -487,7 +487,10 @@ set_false_path -through [get_pins -filter {NAME =~ */DQSFOUND} -of [get_cells -h
set_multicycle_path -through [get_pins -filter {NAME =~ */OSERDESRST} -of [get_cells -hier -filter {REF_NAME == PHASER_OUT_PHY}]] -setup 2 -start
set_multicycle_path -through [get_pins -filter {NAME =~ */OSERDESRST} -of [get_cells -hier -filter {REF_NAME == PHASER_OUT_PHY}]] -hold 1 -start

set_max_delay -datapath_only -from [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/device_temp_sync_r1*}] 20
#set_max_delay -datapath_only -from [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/device_temp_sync_r1*}] 20
set_max_delay -to [get_pins -hier -include_replicated_objects -filter {NAME =~ *temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[*]/D}] 20
set_max_delay -from [get_cells -hier *rstdiv0_sync_r1_reg*] -to [get_pins -filter {NAME =~ */RESET} -of [get_cells -hier -filter {REF_NAME == PHY_CONTROL}]] -datapath_only 5
#set_false_path -through [get_pins -hier -filter {NAME =~ */u_iodelay_ctrl/sys_rst}]
set_false_path -through [get_nets -hier -filter {NAME =~ */u_iodelay_ctrl/sys_rst_i}]

set_max_delay -datapath_only -from [get_cells -hier -filter {NAME =~ *ddr3_infrastructure/rstdiv0_sync_r1_reg*}] -to [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1*}] 20
15 changes: 10 additions & 5 deletions hdl/top/afc_v3/vivado/dbe_bpm2/Manifest.py
Original file line number Diff line number Diff line change
@@ -1,8 +1,13 @@
files = [ "dbe_bpm2.vhd",
"dbe_bpm2.xdc",
"pcie_core.xdc",
"ddr_core.xdc",
"dbe_bpm2.xcf" ];
filenames = ['pcie_core.xdc', 'ddr_core.xdc', 'dbe_bpm2.xdc']
with open('dbe_bpm2_gen.xdc', 'w') as outfile:
for fname in filenames:
with open(fname) as infile:
outfile.write(infile.read())

files = [ "dbe_bpm2.xcf",
"dbe_bpm2_gen.xdc",
"dbe_bpm2.vhd"
];

modules = { "local" :
["../../../..",
Expand Down
9 changes: 9 additions & 0 deletions hdl/top/afc_v3/vivado/dbe_bpm2/dbe_bpm2.vhd
Original file line number Diff line number Diff line change
Expand Up @@ -35,6 +35,9 @@ port(
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;

aux_clk_p_i : in std_logic;
aux_clk_n_i : in std_logic;

-----------------------------------------
-- Reset Button
-----------------------------------------
Expand Down Expand Up @@ -323,6 +326,9 @@ architecture rtl of dbe_bpm2 is
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;

aux_clk_p_i : in std_logic;
aux_clk_n_i : in std_logic;

-----------------------------------------
-- Reset Button
-----------------------------------------
Expand Down Expand Up @@ -817,6 +823,9 @@ begin
sys_clk_p_i => sys_clk_p_i,
sys_clk_n_i => sys_clk_n_i,

aux_clk_p_i => aux_clk_p_i,
aux_clk_n_i => aux_clk_n_i,

-----------------------------------------
-- Reset Button
-----------------------------------------
Expand Down
28 changes: 25 additions & 3 deletions hdl/top/afc_v3/vivado/dbe_bpm2/dbe_bpm2.xdc
Original file line number Diff line number Diff line change
Expand Up @@ -10,6 +10,11 @@ set_property PACKAGE_PIN AL7 [get_ports sys_clk_n_i]
set_property IOSTANDARD DIFF_SSTL15 [get_ports sys_clk_n_i]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports sys_clk_n_i]

# LINK01_CLK1_P
set_property PACKAGE_PIN AG18 [get_ports aux_clk_p_i]
# LINK01_CLK1_N
set_property PACKAGE_PIN AH18 [get_ports aux_clk_n_i]

# TXD IO_25_34
set_property PACKAGE_PIN AB11 [get_ports rs232_txd_o]
set_property IOSTANDARD LVCMOS25 [get_ports rs232_txd_o]
Expand Down Expand Up @@ -1051,13 +1056,20 @@ set_property IDELAY_VALUE 0 [get_cells -hier -filter {NAME =~ *cmp2_xwb_fmc250m_
# 125 MHz AMC TCLKB input clock
create_clock -period 8.000 -name sys_clk_p_i [get_ports sys_clk_p_i]

# 64.440 MHz AMC TCLKB input clock
create_clock -period 14.400 -name aux_clk_p_i [get_ports aux_clk_p_i]

## 100 MHz wihsbone clock
create_generated_clock -name clk_sys [get_pins -hier -filter {NAME =~ *cmp_sys_pll_inst/cmp_sys_pll/CLKOUT0}]
set clk_sys_period [get_property PERIOD [get_clocks clk_sys]]
# 200 MHz DDR3 and IDELAY CONTROL clock
create_generated_clock -name clk_200mhz [get_pins -hier -filter {NAME =~ *cmp_sys_pll_inst/cmp_sys_pll/CLKOUT1}]
set clk_200mhz_period [get_property PERIOD [get_clocks clk_200mhz]]

## 64.440 MHz aux clock
create_generated_clock -name clk_aux [get_pins -hier -filter {NAME =~ *cmp_aux_sys_pll_inst/cmp_sys_pll/CLKOUT0}]
set clk_aux_period [get_property PERIOD [get_clocks clk_aux]]

# DDR3 clock generated by IP
set clk_pll_ddr_period [get_property PERIOD [get_clocks clk_pll_i]]
set clk_pll_ddr_period_less [expr $clk_pll_ddr_period - 1.000]
Expand Down Expand Up @@ -1104,8 +1116,14 @@ set fmc2_ref_clk_2x_period [get_property PERIOD [get_clo
# Reset synchronization path.
set_false_path -through [get_pins -hier -filter {NAME =~ *cmp_reset/master_rstn_reg/C}]
# Get the cell driving the corresponding net
set reset_ffs [get_nets -hier -filter {NAME =~ *cmp_reset*/master_rstn*}]
set_property ASYNC_REG TRUE [get_cells [all_fanin -flat -only_cells -startpoints_only [get_pins -of_objects [get_nets $reset_ffs]]]]
set reset_sys_ffs [get_nets -hier -filter {NAME =~ *cmp_reset*/master_rstn*}]
set_property ASYNC_REG TRUE [get_cells [all_fanin -flat -only_cells -startpoints_only [get_pins -of_objects [get_nets $reset_sys_ffs]]]]

# Reset synchronization path.
set_false_path -through [get_pins -hier -filter {NAME =~ *cmp_aux_reset/master_rstn_reg/C}]
# Get the cell driving the corresponding net
set reset_aux_ffs [get_nets -hier -filter {NAME =~ *cmp_aux_reset*/master_rstn*}]
set_property ASYNC_REG TRUE [get_cells [all_fanin -flat -only_cells -startpoints_only [get_pins -of_objects [get_nets $reset_aux_ffs]]]]

# DDR 3 temperature monitor reset path
# chain of FFs synched with clk_sys.
Expand Down Expand Up @@ -1286,6 +1304,10 @@ set_max_delay -datapath_only -from [get_pins -hier -filter {NAME =~ *acq_core/*/
# destination clock period
set_max_delay -datapath_only -from [get_pins -hier -filter {NAME =~ *acq_core/*acq_core_regs/*/C}] -to [get_clocks clk_sys] $clk_sys_period

# Aux clock to Sys clock. Path used to/from registers
set_max_delay -datapath_only -from [get_clocks clk_sys] -to [get_clocks clk_aux] $clk_sys_period
set_max_delay -datapath_only -from [get_clocks clk_aux] -to [get_clocks clk_sys] $clk_sys_period

# Use Distributed RAM, as these FIFOs are small and sparse through the module
# Cannot make this work with hierarchical matching... only by specifying the
# whole topology
Expand All @@ -1295,7 +1317,7 @@ set_property RAM_STYLE DISTRIBUTED [get_cells -hier -filter {NAME =~ */cmp_posit
set_property RAM_STYLE DISTRIBUTED [get_cells -hier -filter {NAME =~ */cmp_fmc_adc_iface/*/cmp_adc_data_async_fifo/mem_reg*}]

# Use Distributed RAMs for FMC ACQ FIFOs. They are small and sparse.
set_property RAM_STYLE DISTRIBUTED [get_cells -hier -filter {NAME =~ */cmp_acq_fc_fifo/cmp_fc_source/*.*/*.*/mem_reg*}]
set_property RAM_STYLE DISTRIBUTED [get_cells -hier -filter {NAME =~ */cmp_acq_fc_fifo/cmp_fc_source/*/*ram_reg*}]

#######################################################################
## Placement Constraints ##
Expand Down
5 changes: 4 additions & 1 deletion hdl/top/afc_v3/vivado/dbe_bpm2/ddr_core.xdc
Original file line number Diff line number Diff line change
Expand Up @@ -487,7 +487,10 @@ set_false_path -through [get_pins -filter {NAME =~ */DQSFOUND} -of [get_cells -h
set_multicycle_path -through [get_pins -filter {NAME =~ */OSERDESRST} -of [get_cells -hier -filter {REF_NAME == PHASER_OUT_PHY}]] -setup 2 -start
set_multicycle_path -through [get_pins -filter {NAME =~ */OSERDESRST} -of [get_cells -hier -filter {REF_NAME == PHASER_OUT_PHY}]] -hold 1 -start

set_max_delay -datapath_only -from [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/device_temp_sync_r1*}] 20
#set_max_delay -datapath_only -from [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/device_temp_sync_r1*}] 20
set_max_delay -to [get_pins -hier -include_replicated_objects -filter {NAME =~ *temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[*]/D}] 20
set_max_delay -from [get_cells -hier *rstdiv0_sync_r1_reg*] -to [get_pins -filter {NAME =~ */RESET} -of [get_cells -hier -filter {REF_NAME == PHY_CONTROL}]] -datapath_only 5
#set_false_path -through [get_pins -hier -filter {NAME =~ */u_iodelay_ctrl/sys_rst}]
set_false_path -through [get_nets -hier -filter {NAME =~ */u_iodelay_ctrl/sys_rst_i}]

set_max_delay -datapath_only -from [get_cells -hier -filter {NAME =~ *ddr3_infrastructure/rstdiv0_sync_r1_reg*}] -to [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1*}] 20
3 changes: 2 additions & 1 deletion hdl/top/afc_v3/vivado/dbe_bpm_gen/Manifest.py
Original file line number Diff line number Diff line change
@@ -1,6 +1,7 @@
files = [ "dbe_bpm_gen.vhd",
"sys_pll.vhd",
"clk_gen.vhd"
"clk_gen.vhd",
"clk_gen_mgt.vhd"
];

modules = { "local" :
Expand Down
62 changes: 62 additions & 0 deletions hdl/top/afc_v3/vivado/dbe_bpm_gen/clk_gen_mgt.vhd
Original file line number Diff line number Diff line change
@@ -0,0 +1,62 @@
library UNISIM;
use UNISIM.vcomponents.all;

library ieee;
use ieee.std_logic_1164.all;

entity clk_gen_mgt is
port(
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
sys_clk_o : out std_logic;
sys_clk_bufg_o : out std_logic
);
end clk_gen_mgt;

architecture syn of clk_gen_mgt is

-- Internal clock signal
signal s_sys_clk : std_logic;
signal s_sys_clk_ibuf_p : std_logic;
signal s_sys_clk_ibuf_n : std_logic;

begin

cmp_ibuf_clk_gen_mgt_p : IBUF
generic map (
IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DEFAULT"
)
port map (
O => s_sys_clk_ibuf_p, -- Buffer output
I => sys_clk_p_i -- Buffer input (connect directly to top-level port)
);

cmp_ibuf_clk_gen_mgt_n : IBUF
generic map (
IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DEFAULT"
)
port map (
O => s_sys_clk_ibuf_n, -- Buffer output
I => sys_clk_n_i -- Buffer input (connect directly to top-level port)
);

cpm_ibufgds_clk_gen_mgt : IBUFDS_GTE2
port map (
O => s_sys_clk, -- Clock buffer output
ODIV2 => open,
CEB => '0',
I => s_sys_clk_ibuf_p, -- Diff_p clock buffer input (connect directly to top-level port)
IB => s_sys_clk_ibuf_n -- Diff_n clock buffer input (connect directly to top-level port)
);

sys_clk_o <= s_sys_clk;

cmp_bufg_clk_gen_mgt : BUFG
port map (
O => sys_clk_bufg_o, -- 1-bit output: Clock buffer output
I => s_sys_clk -- 1-bit input: Clock buffer input
);

end syn;
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