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@lerwys
lerwys committed Oct 2, 2020
2 parents c63e829 + 4d1d059 commit 21fab0b
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Showing 3 changed files with 71 additions and 38 deletions.
87 changes: 60 additions & 27 deletions hdl/modules/position_calc/position_calc.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -400,6 +400,9 @@ architecture rtl of position_calc is
signal tbt_x_pre, tbt_y_pre, tbt_q_pre, tbt_sum_pre :
std_logic_vector(g_tbt_decim_width-1 downto 0) := (others => '0');

signal monit1_pos_x_int, monit1_pos_y_int, monit1_pos_q_int, monit1_pos_sum_int :
std_logic_vector(g_monit_decim_width-1 downto 0) := (others => '0');

signal monit_x_pre, monit_y_pre, monit_q_pre, monit_sum_pre :
std_logic_vector(g_monit_decim_width-1 downto 0) := (others => '0');

Expand All @@ -422,7 +425,7 @@ architecture rtl of position_calc is
signal valid_tbt, valid_tbt_cordic, valid_fofb, valid_fofb_cordic, valid_monit1, valid_monit2 : ce_sl := (others => '0');
signal ce_adc, ce_monit1, ce_monit2, ce_tbt_cordic, ce_fofb_cordic : ce_sl := (others => '0');

signal valid_fofb_ds, valid_tbt_ds : std_logic;
signal valid_monit1_ds, valid_fofb_ds, valid_tbt_ds : std_logic;

attribute max_fanout : string;
attribute max_fanout of ce_adc, ce_monit1, ce_monit2 : signal is "50";
Expand Down Expand Up @@ -798,28 +801,58 @@ begin
-- fractional length = g_width - (integer length)
cmp_fofb_ds : delta_sigma
generic map (
g_width => g_fofb_decim_width,
g_k_width => g_k_width,
g_width => g_fofb_decim_width,
g_k_width => g_k_width,
g_offset_width => g_offset_width)
port map (
a_i => fofb_mag(0),
b_i => fofb_mag(1),
c_i => fofb_mag(2),
d_i => fofb_mag(3),
kx_i => kx_i,
ky_i => ky_i,
ksum_i => ksum_i,
offset_x_i => offset_x_i,
offset_y_i => offset_y_i,
clk_i => clk_i,
ce_i => ce_fofb_cordic(0),
valid_i => valid_fofb_cordic(0),
valid_o => valid_fofb_ds,
rst_i => rst_i,
x_o => fofb_pos_x_int,
y_o => fofb_pos_y_int,
q_o => fofb_pos_q_int,
sum_o => fofb_pos_sum_int);

-- x, y, and q are fixed point with:
-- sign bit = MSB
-- word length = g_width
-- integer length = g_k_width + 1
-- fractional length = g_width - (integer length)
cmp_monit1_ds : delta_sigma
generic map (
g_width => g_monit_decim_width,
g_k_width => g_k_width,
g_offset_width => g_offset_width)
port map (
a_i => fofb_mag(0),
b_i => fofb_mag(1),
c_i => fofb_mag(2),
d_i => fofb_mag(3),
kx_i => kx_i,
ky_i => ky_i,
ksum_i => ksum_i,
offset_x_i => offset_x_i,
offset_y_i => offset_y_i,
clk_i => clk_i,
ce_i => ce_fofb_cordic(0),
valid_i => valid_fofb_cordic(0),
valid_o => valid_fofb_ds,
rst_i => rst_i,
x_o => fofb_pos_x_int,
y_o => fofb_pos_y_int,
q_o => fofb_pos_q_int,
sum_o => fofb_pos_sum_int);
a_i => monit1_mag(0),
b_i => monit1_mag(1),
c_i => monit1_mag(2),
d_i => monit1_mag(3),
kx_i => kx_i,
ky_i => ky_i,
ksum_i => ksum_i,
offset_x_i => offset_x_i,
offset_y_i => offset_y_i,
clk_i => clk_i,
ce_i => ce_monit1(0),
valid_i => valid_monit1(0),
valid_o => valid_monit1_ds,
rst_i => rst_i,
x_o => monit1_pos_x_int,
y_o => monit1_pos_y_int,
q_o => monit1_pos_q_int,
sum_o => monit1_pos_sum_int);

-- desync counters. Use only one of the channels as a sample
tbt_tag_desync_cnt_o <= tbt_tag_desync_cnt(0);
Expand Down Expand Up @@ -921,13 +954,13 @@ begin
tbt_pos_q_o <= (others => '0');
tbt_pos_sum_o <= (others => '0');

monit1_pos_valid_o <= '0';
monit1_pos_ce_o <= '0';
monit1_pos_valid_o <= valid_monit1_ds;
monit1_pos_ce_o <= ce_monit1(0);

monit1_pos_x_o <= (others => '0');
monit1_pos_y_o <= (others => '0');
monit1_pos_q_o <= (others => '0');
monit1_pos_sum_o <= (others => '0');
monit1_pos_x_o <= std_logic_vector(shift_right(signed(monit1_pos_x_int), g_monit_decim_width-g_k_width));
monit1_pos_y_o <= std_logic_vector(shift_right(signed(monit1_pos_y_int), g_monit_decim_width-g_k_width));
monit1_pos_q_o <= std_logic_vector(shift_right(signed(monit1_pos_q_int), g_monit_decim_width-g_k_width));
monit1_pos_sum_o <= monit1_pos_sum_int;

monit_pos_valid_o <= '0';
monit_pos_ce_o <= '0';
Expand Down
2 changes: 1 addition & 1 deletion hdl/modules/wb_position_calc/wb_position_calc_core.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -2375,7 +2375,7 @@ begin
monit1_pos_y_o <= fifo_monit1_pos_out(2*g_monit_decim_width-1 downto g_monit_decim_width);
monit1_pos_x_o <= fifo_monit1_pos_out(g_monit_decim_width-1 downto 0);

monit1_pos_valid_o <= fifo_monit_pos_valid_out;
monit1_pos_valid_o <= fifo_monit1_pos_valid_out;

p_reg_monit1_pos_sync_wb : process(clk_i)
begin
Expand Down
20 changes: 10 additions & 10 deletions hdl/top/afc_v3/vivado/dbe_bpm_gen/dbe_bpm_gen.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -4285,11 +4285,11 @@ begin
adc_ds_tag_i => dsp1_adc_tag,
adc_ds_swap_valid_i => dsp1_adc_valid,

decim_ds_pos_x_i => dsp1_fofb_pos_x,
decim_ds_pos_y_i => dsp1_fofb_pos_y,
decim_ds_pos_q_i => dsp1_fofb_pos_q,
decim_ds_pos_sum_i => dsp1_fofb_pos_sum,
decim_ds_pos_valid_i => dsp1_fofb_pos_valid,
decim_ds_pos_x_i => dsp1_monit1_pos_x,
decim_ds_pos_y_i => dsp1_monit1_pos_y,
decim_ds_pos_q_i => dsp1_monit1_pos_q,
decim_ds_pos_sum_i => dsp1_monit1_pos_sum,
decim_ds_pos_valid_i => dsp1_monit1_pos_valid,

-----------------------------
-- Upstream ADC and position signals
Expand All @@ -4304,11 +4304,11 @@ begin
adc_us_tag_i => dsp2_adc_tag,
adc_us_swap_valid_i => dsp2_adc_valid,

decim_us_pos_x_i => dsp2_fofb_pos_x,
decim_us_pos_y_i => dsp2_fofb_pos_y,
decim_us_pos_q_i => dsp2_fofb_pos_q,
decim_us_pos_sum_i => dsp2_fofb_pos_sum,
decim_us_pos_valid_i => dsp2_fofb_pos_valid,
decim_us_pos_x_i => dsp2_monit1_pos_x,
decim_us_pos_y_i => dsp2_monit1_pos_y,
decim_us_pos_q_i => dsp2_monit1_pos_q,
decim_us_pos_sum_i => dsp2_monit1_pos_sum,
decim_us_pos_valid_i => dsp2_monit1_pos_valid,

-----------------------------
-- Interlock outputs
Expand Down

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