mmap: Add write functionality #70
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@enjoy-digital should the CSR functionality also be tested? If so, is there any recommended approach? |
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With this change, it is possible to memory map e.g. PSRAM. When setting with_write to "csr", it can also be used to support faster flash writing via etherbone. For flash, only False and "csr" should be used, as the some other logic or application needs to make sure that the flash is erased ahead of time. True is only meant for use with RAM chips. Signed-off-by: Matthias Breithaupt <m.breithaupt@vogl-electronic.com>
With this change, it is possible compensate the memory map origin using offset. E.g. for spi flash, the following line would suffice `self.comb += self.spiflash_core.mmap.offset.eq(self.bus.regions.get(name, None).origin)` Signed-off-by: Matthias Breithaupt <m.breithaupt@vogl-electronic.com>
This change prevents accidental shorts during the wait period in QSPI, as the SoC should not be driving data lines while waiting for the memory chip to get ready. Signed-off-by: Matthias Breithaupt <m.breithaupt@vogl-electronic.com>
Add a minimal test for mmap write Signed-off-by: Matthias Breithaupt <m.breithaupt@vogl-electronic.com>
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
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@enjoy-digital do you think you would find some time to review this soon? |
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@m-byte: Thanks for the PR and sorry for the delay...! I'll review it before the end of the week. |
enjoy-digital
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Jul 31, 2024
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Thanks @m-byte, this make sense and the code look fine, let's merge. Thanks also for the test-bench, really appreciated and help a lot for future maintenance!
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Thank you! |
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With this change, it is possible to memory map e.g. PSRAM. When setting with_write to "csr", it can also be used to support faster flash writing via etherbone. For flash, only False and "csr" should be used, as the some other logic or application needs to make sure that the flash is erased ahead of time. True is only meant for use with RAM chips.
There are two bugs that this also addresses:
Addresses are now masked to flash size or addr_width if no size is set. I'm not 100% happy with this solution, as it might cause issues with non power of 2 flashes (do those exist). However, without this, I would get flash writes to the wishbone address rather than offsets inside the flash. So I'm open to better alternatives. Optimum would be subtracting the base bus address, but I haven't found any clean way of accessing it.I found a way to wire the origin through, so now this can be fixed by wiring through the corresponding addresses (described in the commit message and I will create a PR for LiteX, once this is merged)Let me know if they should be part of separate
commits/PRs.Currently, tests are still to be added.This should fix #25