Litespi cs handling

Documentation/devicetree/bindings/clock/litex,clock.yaml

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+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/litex,clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: LiteX clock control driver
+
+description: |
+  Common clock driver with MMCM unit for dynamic reconfiguration
+  of up to 7 clock outputs with ability to change frequency, duty
+  cycle and phase offset
+
+maintainers:
+  - Karol Gugala <kgugala@antmicro.com>
+  - Mateusz Holenko <mholenko@antmicro.com>
+
+properties:
+  compatible:
+    const: litex,clock
+
+  reg:
+    description: Base address and lengths of the register space
+
+  "#clock-cells":
+    description:
+      Number of cells in a clock specifier;
+      Typically 0 for nodes with a single clock output
+      and 1 for nodes with multiple clock outputs.
+    const: 1
+
+  "#address-cells":
+    description:
+      Number of cells that are needed to form the base address
+      part in the reg property.
+    const: 1
+
+  "#size-cells":
+    description:
+      Used to state how many cells are in each field of a reg property
+    const: 0
+
+  clock-output-names:
+    description:
+      List of strings of clock output signal names indexed
+      by the first cell in the clock specifier.
+    minItems: 1
+    maxItems: 7
+    items:
+      - const: CLKOUT0
+      - const: CLKOUT1
+      - const: CLKOUT2
+      - const: CLKOUT3
+      - const: CLKOUT4
+      - const: CLKOUT5
+      - const: CLKOUT6
+
+  litex,nclkout:
+    description: Number of desired clock outputs
+    $ref: /schemas/types.yaml#/definitions/uint32
+    minimum: 1
+    maximum: 7
+
+  litex,lock-timeout:
+    description: Number of ms to wait for MMCM to assert LOCK signal
+    $ref: /schemas/types.yaml#/definitions/uint32
+    minimum: 1
+
+  litex,drdy-timeout:
+    description: Number of ms to wait for MMCM to assert DRDY signal
+    $ref: /schemas/types.yaml#/definitions/uint32
+    minimum: 1
+
+  litex,sys-clock-freq:
+    description: System clock frequency
+    $ref: /schemas/types.yaml#/definitions/uint32
+
+patternProperties:
+  "^CLKOUT[0-6]$":
+    description:
+      Child node representing configurable clock outputs of MMCM unit
+    type: object
+
+    properties:
+      compatible:
+        const: litex,clock
+
+      reg:
+        description: clock output ID, zero-based numbering
+
+      litex,clock-frequency:
+        description: default frequency in Hz for clock output
+        $ref: /schemas/types.yaml#/definitions/uint32
+        minimum: 1587000
+        maximum: 100000000
+
+      litex,clock-phase:
+        description: default phase offset given in degrees
+        $ref: /schemas/types.yaml#/definitions/uint32
+        minimum: 0
+        maximum: 359
+
+      litex,clock-duty-num:
+        description: default duty cycle numerator value
+        $ref: /schemas/types.yaml#/definitions/uint32
+        minimum: 1
+        maximum: 100
+
+      litex,clock-duty-den:
+        description: default duty cycle denominator value
+        $ref: /schemas/types.yaml#/definitions/uint32
+        minimum: 1
+        maximum: 100
+
+    required:
+      - compatible
+      - "#clock-cells"
+      - clock-output-names
+      - reg
+      - litex,clock-frequency
+      - litex,clock-phase
+      - litex,clock-duty-num
+      - litex,clock-duty-den
+
+required:
+  - compatible
+  - reg
+  - "#clock-cells"
+  - "#address-cells"
+  - "#size-cells"
+  - clock-output-names
+  - litex,nclkout
+  - CLKOUTx
+
+additionalProperties: false
+
+examples:
+  - |
+    clk0: clock-controller@f0003000 {
+            compatible = "litex,clk";
+            reg = <0x0 0xf0003000>, <0x0 0x100>;
+            #clock-cells =        <1>;
+            #address-cells = <1>;
+            #size-cells = <0>;
+            clock-output-names = "CLKOUT0",
+                                 "CLKOUT1",
+                                 "CLKOUT2",
+                                 "CLKOUT3",
+                                 "CLKOUT4",
+                                 "CLKOUT5",
+                                 "CLKOUT6";
+            litex,nclkout = <7>;
+
+            CLKOUT0: CLKOUT0@0 {
+                    compatible = "litex,clk";
+                    #clock-cells = <0>;
+                    clock-output-names = "CLKOUT0";
+                    reg = <0>;
+                    litex,clock-frequency = <50000000>;
+                    litex,clock-phase = <0>;
+                    litex,clock-duty = <50>;
+            };
+
+            CLKOUT1: CLKOUT1@1 {
+                    compatible = "litex,clk";
+                    #clock-cells = <0>;
+                    clock-output-names = "CLKOUT1";
+                    reg = <1>;
+                    litex,clock-frequency = <50000000>;
+                    litex,clock-phase = <90>;
+                    litex,clock-duty = <50>;
+            };
+
+            CLKOUT2: CLKOUT2@2 {
+                    compatible = "litex,clk";
+                    #clock-cells = <0>;
+                    clock-output-names = "CLKOUT2";
+                    reg = <2>;
+                    litex,clock-frequency = <25000000>;
+                    litex,clock-phase = <0>;
+                    litex,clock-duty = <25>;
+            };
+
+            CLKOUT3: CLKOUT3@3 {
+                    compatible = "litex,clk";
+                    #clock-cells = <0>;
+                    clock-output-names = "CLKOUT3";
+                    reg = <3>;
+                    litex,clock-frequency = <12500000>;
+                    litex,clock-phase = <0>;
+                    litex,clock-duty = <75>;
+            };
+
+            CLKOUT4: CLKOUT4@4 {
+                    compatible = "litex,clk";
+                    #clock-cells = <0>;
+                    clock-output-names = "CLKOUT4";
+                    reg = <4>;
+                    litex,clock-frequency = <6250000>;
+                    litex,clock-phase = <0>;
+                    litex,clock-duty = <50>;
+            };
+
+            CLKOUT5: CLKOUT5@5 {
+                    compatible = "litex,clk";
+                    #clock-cells = <0>;
+                    clock-output-names = "CLKOUT5";
+                    reg = <5>;
+                    litex,clock-frequency = <3125000>;
+                    litex,clock-phase = <0>;
+                    litex,clock-duty = <50>;
+            };
+
+            CLKOUT6: CLKOUT6@6 {
+                    compatible = "litex,clk";
+                    #clock-cells = <0>;
+                    clock-output-names = "CLKOUT6";
+                    reg = <6>;
+                    litex,clock-frequency = <1562500>;
+                    litex,clock-phase = <0>;
+                    litex,clock-duty = <5>;
+            };
+    };
+...

Documentation/devicetree/bindings/fpga/litex-fpga.txt

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+LiteX ICAPBitstream fpga manager
+
+Required properties:
+- compatible: should be "litex,fpga-icap"
+- reg: base address of configuration registers with length
+
+Examples:
+
+fpga_man: icap@f0007000 {
+	compatible = "litex,fpga-icap";
+	reg = <0x0 0xf0007000 0x0 0x14>;
+};

Documentation/devicetree/bindings/gpio/litex,gpio.txt

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+LiteX GPIO controller
+
+Required properties:
+- compatible: should be "litex,gpio"
+- reg: base address and length of the register
+- litex,ngpio: number of gpio pins in port
+- litex,direction: direction of gpio port, should be "in" or "out"
+
+Examples:
+
+gpio@f0003000 {
+	compatible = "litex,gpio";
+	reg = <0x0 0xf0003800 0x0 0x1>;
+	litex,ngpio = <4>;
+	litex,direction = "in";
+};
+
+gpio@f0003800 {
+	compatible = "litex,gpio";
+	reg = <0x0 0xf0003800 0x0 0x1>;
+	litex,ngpio = <4>;
+	litex,direction = "out";
+};

Documentation/devicetree/bindings/gpu/litex,litevideo.txt

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+DRM LiteX LiteVideo driver
+
+Required properties:
+- compatible: should be "litex,litevideo"
+- reg: base address of configuration registers with length
+- litevideo,pixel-clock: pixel clock frequency in kHz
+- litevideo,h-active: horizontal active pixels
+- litevideo,h-blanking: total horizontal blanking
+- litevideo,h-sync: horizontal sync width
+- litevideo,h-front-porch: horizontal front porch
+- litevideo,v-active: vertical active pixels
+- litevideo,v-blanking: vertical total blanking
+- litevideo,v-sync: vertical sync width
+- litevideo,v-front-porch: vertical front porch
+- litevideo,dma-offset: dma offset in memory
+- litevideo,dma-length: size of memory used for storing the image
+
+Examples:
+
+litevideo0: gpu@f0009800 {
+	compatible = "litex,litevideo";
+	reg = <0x0 0xf0009800 0x0 0x100>;
+	litevideo,pixel-clock = <148500>;
+	litevideo,h-active = <1920>;
+	litevideo,h-blanking = <280>;
+	litevideo,h-sync = <44>;
+	litevideo,h-front-porch = <148>;
+	litevideo,v-active = <1080>;
+	litevideo,v-blanking = <45>;
+	litevideo,v-sync = <5>;
+	litevideo,v-front-porch = <36>;
+	litevideo,dma-offset = <0x8000000>;
+	litevideo,dma-length = <0x7e9000>;
+};

Documentation/devicetree/bindings/hwmon/litex-hwmon.txt

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+LiteX XADC hwmon controller
+
+Required properties:
+- compatible: should be "litex,hwmon-xadc"
+- reg: base address of configuration registers with length
+
+Examples:
+
+hwmon@f0003000 {
+	compatible = "litex,hwmon-xadc";
+	reg = <0x0 0xf0003000 0x0 0x20>;
+};

Documentation/devicetree/bindings/i2c/i2c-litex.txt

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+LiteX I2C controller
+
+Required properties:
+- compatible: should be "litex,i2c"
+- reg: base address of configuration registers with length
+
+Examples:
+
+i2c@f0003000 {
+	compatible = "litex,i2c";
+	reg = <0x0 0xf0003000 0x0 0x5>;
+};

Documentation/devicetree/bindings/mtd/litex,spiflash.yaml

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+# SPDX-License-Identifier: GPL-2.0
+
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mtd/litex,spiflash.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: LiteX SPI Flash controller
+
+maintainers:
+  - Karol Gugala <kgugala@antmicro.com>
+  - Mateusz Holenko <mholenko@antmicro.com>
+
+description: |
+  LiteX SPI Flash controller is a part of LiteX FPGA SoC builder. It supports
+  multiple CPU architectures, currently including e.g. OpenRISC and RISC-V.
+
+allOf:
+  - $ref: "/schemas/spi/spi-controller.yaml#"
+
+properties:
+  compatible:
+    const: litex,spiflash
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+
+patternProperties:
+  "flash@[0-9a-f]+$":
+    type: object
+    properties:
+      compatible:
+        enum:
+          - jedec,spi-nor
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    spiflash: spi@f0005800 {
+            compatible = "litex,spiflash";
+            reg = <0xf0005800 0xc>;
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            flash: flash@0 {
+                    compatible = "jedec,spi-nor";
+                    reg = <0>;
+            };
+    };