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Labwork on Logic Design implementation in Verilog on a Basys3 FPGA Module

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Name		Name	Last commit message	Last commit date
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Lab 1		Lab 1
Lab 2		Lab 2
Lab 3		Lab 3
README.md		README.md

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CSM152A

Coursework on Logic Design implementation in Verilog on a Basys3 FPGA Module

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Labwork on Logic Design implementation in Verilog on a Basys3 FPGA Module

modular verilog uart basys3 modular-design half-adder full-adder fpga-programming 7-segment-display

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