Soft-core RISC-V CPU
- rv32i without privileged stuff and fences for now
- 3 stage pipeline (fetch, decode, execute + memory + writeback)
- TCM using dual-port block SRAM, shared data and instructions
- separate AXI4-Lite master for instruction and data memory (and MMIO)
- CSR, timer
- M extension
- C extension
- interrupts and exceptions
- Digital Design and Computer Architecture, David Harris, Sarah Harris
- Onur Mutlu, Undergraduate Digital Design & Computer Architecture Course Materials
- From Blinker to RISC-V, took many ideas from here, for example word/halfword/byte width load/store handling, focusing on simplicity
- SCR1, the idea of using dual-port block SRAM for TCM for both data and instructions