diff --git a/_sources/modules/instruction_decoder.rst.txt b/_sources/modules/instruction_decoder.rst.txt index 66f31c2..034334d 100644 --- a/_sources/modules/instruction_decoder.rst.txt +++ b/_sources/modules/instruction_decoder.rst.txt @@ -5,7 +5,8 @@ Instruction decoder =================== The instruction decoder is reponsible for mapping a machine instruction together -with the t-state counter to the control lines. The instruction decoder in the +with the t-state counter to the control lines, effectively tying a set of +microinstructions to a given machine instruction. The instruction decoder in the SAM-SMD uses two :code:`SST39SF010` EEPROMS for this mapping. One of the EEPROMS directs 8 parallel control lines, which are lines that can be pulled high or low in any particular combination. The second EEPROM is tied to four :code:`74HC238` @@ -141,26 +142,190 @@ Mapping - :code:`TO` - T-register: Asserts register value onto data bus * - :code:`OCB8` - - CODE008 - - Description for control line 8. + - :code:`X` + - Unused * - :code:`OCB9` - - CODE009 - - Description for control line 9. + - :code:`X` + - Unused * - :code:`OCB10` - - CODE010 - - Description for control line 10. + - :code:`X` + - Unused * - :code:`OCB11` - - CODE011 - - Description for control line 11. + - :code:`X` + - Unused * - :code:`OCB12` - - CODE012 - - Description for control line 12. + - :code:`X` + - Unused * - :code:`OCB13` - - CODE013 - - Description for control line 13. + - :code:`X` + - Unused * - :code:`OCB14` - - CODE014 - - Description for control line 14. + - :code:`X` + - Unused * - :code:`OCB15` - - CODE015 - - Description for control line 15. + - :code:`X` + - Unused + +Machine instructions +-------------------- + +Upon receiving a new machine instruction, a t-state counter is executed that +loops over a number of microinstructions. Below, a table is provided showing +the sequence of microinstructions that are executed per machine instruction +and per t-state. A secondary table provides an explanation what each machine +code instruction (opt code) does. + +.. note:: + Despite that the t-state counter allows for up to 20 microinstructions, + typically far fewer such microinstructions are needed. + +.. list-table:: Microinstructions per t-state and per machine instruction + :header-rows: 1 + + * - Instruction + - State 0 + - State 1 + - State 2 + - State 3 + - State 4 + - State 5 + - State 6 + * - :code:`NOP` + - :code:`CO | MI` + - :code:`RRO | II | CE` + - :code:`RT` + - + - + - + - + * - :code:`JP` + - :code:`CO | MI` + - :code:`RRO | II | CE` + - :code:`CO | MI` + - :code:`RRO | J` + - :code:`RT` + - + - + * - :code:`LDA` + - :code:`CO | MI` + - :code:`RRO | II | CE` + - :code:`CO | MI` + - :code:`RRO | AI | CE` + - :code:`RT` + - + - + * - :code:`LDB` + - :code:`CO | MI` + - :code:`RRO | II | CE` + - :code:`CO | MI` + - :code:`RRO | BI | CE` + - :code:`RT` + - + - + * - :code:`ADD` + - :code:`CO | MI` + - :code:`RRO | II | CE` + - :code:`0` + - :code:`EO | TI | FI` + - :code:`TO | AI` + - :code:`RT` + - + * - :code:`TAB` + - :code:`CO | MI` + - :code:`RRO | II | CE` + - :code:`AO | BI` + - :code:`RT` + - + - + - + * - :code:`TBA` + - :code:`CO | MI` + - :code:`RRO | II | CE` + - :code:`BO | AI` + - :code:`RT` + - + - + - + * - :code:`TAO` + - :code:`CO | MI` + - :code:`RRO | II | CE` + - :code:`AO | OI` + - :code:`RT` + - + - + - + * - :code:`STA` + - :code:`CO | MI` + - :code:`RRO | II | CE` + - :code:`CO | MI` + - :code:`RRO | TI` + - :code:`TO | MI` + - :code:`RI | AO | CE` + - :code:`RT` + * - :code:`LRA` + - :code:`CO | MI` + - :code:`RRO | II | CE` + - :code:`CO | MI` + - :code:`RRO | TI` + - :code:`TO | MI` + - :code:`RO | AI | CE` + - :code:`RT` + * - :code:`STB` + - :code:`CO | MI` + - :code:`RRO | II | CE` + - :code:`CO | MI` + - :code:`RRO | TI` + - :code:`TO | MI` + - :code:`RI | BO | CE` + - :code:`RT` + * - :code:`LRB` + - :code:`CO | MI` + - :code:`RRO | II | CE` + - :code:`CO | MI` + - :code:`RRO | TI` + - :code:`TO | MI` + - :code:`RO | BI | CE` + - :code:`RT` + +.. list-table:: Explanation of every opt code + :header-rows: 1 + + * - Instruction + - Bytes + - Description + * - :code:`NOP` + - 1 + - Do nothing + * - :code:`JP ` + - 2 + - Jump to memory address + * - :code:`LDA ` + - 2 + - Immediate load into register A + * - :code:`LDB ` + - 2 + - Immediate load into register B + * - :code:`ADD` + - 1 + - Add A+B and store in A (will overwrite) + * - :code:`TAB` + - 1 + - Transfer contents of A to B + * - :code:`TBA` + - 1 + - Transfer contents of B to A + * - :code:`TAO` + - 1 + - Transfer contents of A to Output + * - :code:`STA ` + - 2 + - Store A in RAM at address + * - :code:`LRA ` + - 2 + - Load A from RAM + * - :code:`STB ` + - 2 + - Store B in RAM at address + * - :code:`LRB ` + - 2 + - Load B from RAM \ No newline at end of file diff --git a/index.html b/index.html index d84a436..7568f5e 100644 --- a/index.html +++ b/index.html @@ -254,6 +254,7 @@

SAP-SMD documentation
  • Instruction decoder
    • diff --git a/modules/instruction_decoder.html b/modules/instruction_decoder.html index 72899cd..bab1641 100644 --- a/modules/instruction_decoder.html +++ b/modules/instruction_decoder.html @@ -285,7 +285,8 @@

    Instruction decoder#

    The instruction decoder is reponsible for mapping a machine instruction together -with the t-state counter to the control lines. The instruction decoder in the +with the t-state counter to the control lines, effectively tying a set of +microinstructions to a given machine instruction. The instruction decoder in the SAM-SMD uses two SST39SF010 EEPROMS for this mapping. One of the EEPROMS directs 8 parallel control lines, which are lines that can be pulled high or low in any particular combination. The second EEPROM is tied to four 74HC238 @@ -475,36 +476,234 @@

    Mapping#<

    T-register: Asserts register value onto data bus

    OCB8

    -

    CODE008

    -

    Description for control line 8.

    +

    X

    +

    Unused

    OCB9

    -

    CODE009

    -

    Description for control line 9.

    +

    X

    +

    Unused

    OCB10

    -

    CODE010

    -

    Description for control line 10.

    +

    X

    +

    Unused

    OCB11

    -

    CODE011

    -

    Description for control line 11.

    +

    X

    +

    Unused

    OCB12

    -

    CODE012

    -

    Description for control line 12.

    +

    X

    +

    Unused

    OCB13

    -

    CODE013

    -

    Description for control line 13.

    +

    X

    +

    Unused

    OCB14

    -

    CODE014

    -

    Description for control line 14.

    +

    X

    +

    Unused

    OCB15

    -

    CODE015

    -

    Description for control line 15.

    +

    X

    +

    Unused

    + + + + +

    +
    +

    Machine instructions#

    +

    Upon receiving a new machine instruction, a t-state counter is executed that +loops over a number of microinstructions. Below, a table is provided showing +the sequence of microinstructions that are executed per machine instruction +and per t-state. A secondary table provides an explanation what each machine +code instruction (opt code) does.

    +
    +

    Note

    +

    Despite that the t-state counter allows for up to 20 microinstructions, +typically far fewer such microinstructions are needed.

    +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    Table 4 Microinstructions per t-state and per machine instruction#

    Instruction

    State 0

    State 1

    State 2

    State 3

    State 4

    State 5

    State 6

    NOP

    CO | MI

    RRO | II | CE

    RT

    JP

    CO | MI

    RRO | II | CE

    CO | MI

    RRO | J

    RT

    LDA

    CO | MI

    RRO | II | CE

    CO | MI

    RRO | AI | CE

    RT

    LDB

    CO | MI

    RRO | II | CE

    CO | MI

    RRO | BI | CE

    RT

    ADD

    CO | MI

    RRO | II | CE

    0

    EO | TI | FI

    TO | AI

    RT

    TAB

    CO | MI

    RRO | II | CE

    AO | BI

    RT

    TBA

    CO | MI

    RRO | II | CE

    BO | AI

    RT

    TAO

    CO | MI

    RRO | II | CE

    AO | OI

    RT

    STA

    CO | MI

    RRO | II | CE

    CO | MI

    RRO | TI

    TO | MI

    RI | AO | CE

    RT

    LRA

    CO | MI

    RRO | II | CE

    CO | MI

    RRO | TI

    TO | MI

    RO | AI | CE

    RT

    STB

    CO | MI

    RRO | II | CE

    CO | MI

    RRO | TI

    TO | MI

    RI | BO | CE

    RT

    LRB

    CO | MI

    RRO | II | CE

    CO | MI

    RRO | TI

    TO | MI

    RO | BI | CE

    RT

    +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    Table 5 Explanation of every opt code#

    Instruction

    Bytes

    Description

    NOP

    1

    Do nothing

    JP <ADDR>

    2

    Jump to memory address

    LDA <VAL>

    2

    Immediate load into register A

    LDB <VAL>

    2

    Immediate load into register B

    ADD

    1

    Add A+B and store in A (will overwrite)

    TAB

    1

    Transfer contents of A to B

    TBA

    1

    Transfer contents of B to A

    TAO

    1

    Transfer contents of A to Output

    STA <ADDR>

    2

    Store A in RAM at address

    LRA <ADDR>

    2

    Load A from RAM

    STB <ADDR>

    2

    Store B in RAM at address

    LRB <ADDR>

    2

    Load B from RAM
    @@ -551,6 +750,7 @@

    Mapping#<

    diff --git a/searchindex.js b/searchindex.js index 04f2cfc..ff79aa1 100644 --- a/searchindex.js +++ b/searchindex.js @@ -1 +1 @@ -Search.setIndex({"alltitles": {"Contents:": [[0, null]], "Instruction decoder": [[1, null]], "Mapping": [[1, "mapping"]], "Orthogonal Control Lines A": [[1, "id3"]], "Orthogonal Control Lines B": [[1, "id4"]], "Parallel Control Lines": [[1, "id2"]], "SAP-SMD documentation": [[0, null]]}, "docnames": ["index", "modules/instruction_decoder"], "envversion": {"sphinx": 64, "sphinx.domains.c": 3, "sphinx.domains.changeset": 1, "sphinx.domains.citation": 1, "sphinx.domains.cpp": 9, "sphinx.domains.index": 1, "sphinx.domains.javascript": 3, "sphinx.domains.math": 2, "sphinx.domains.python": 4, "sphinx.domains.rst": 2, "sphinx.domains.std": 2}, "filenames": ["index.rst", "modules/instruction_decoder.rst"], "indexentries": {"instruction decoder": [[1, "index-0", false]]}, "objects": {}, "objnames": {}, "objtypes": {}, "terms": {"10": 1, "11": 1, "12": 1, "13": 1, "14": 1, "15": 1, "2": 1, "30": 1, "74hc238": 1, "8": 1, "9": 1, "In": 1, "One": 1, "TO": 1, "The": 1, "abbrevi": 1, "activ": 1, "address": 1, "ai": 1, "alu": 1, "ani": 1, "ao": 1, "ar": 1, "arithmet": 1, "assert": 1, "below": 1, "benefit": 1, "bi": 1, "bo": 1, "bu": 1, "can": 1, "ce": 1, "chip": 1, "clock": 1, "co": 1, "code008": 1, "code009": 1, "code010": 1, "code011": 1, "code012": 1, "code013": 1, "code014": 1, "code015": 1, "combin": 1, "come": 1, "count": 1, "counter": 1, "current": 1, "data": 1, "decod": 0, "descript": 1, "direct": 1, "e": 1, "eeprom": 1, "enabl": 1, "eo": 1, "far": 1, "fi": 1, "flag": 1, "follow": 1, "form": 1, "four": 1, "from": 1, "halt": 1, "here": 1, "high": 1, "hlt": 1, "i": 1, "ii": 1, "instead": 1, "instrucion": 1, "instruct": 0, "intern": 1, "ir": 1, "j": 1, "jump": 1, "limit": 1, "logic": 1, "low": 1, "machin": 1, "map": 0, "mar": 1, "memori": 1, "mi": 1, "micro": 1, "more": 1, "mr": 1, "note": 1, "oca1": 1, "oca10": 1, "oca11": 1, "oca12": 1, "oca13": 1, "oca14": 1, "oca15": 1, "oca2": 1, "oca3": 1, "oca4": 1, "oca5": 1, "oca6": 1, "oca7": 1, "oca8": 1, "oca9": 1, "ocb1": 1, "ocb10": 1, "ocb11": 1, "ocb12": 1, "ocb13": 1, "ocb14": 1, "ocb15": 1, "ocb2": 1, "ocb3": 1, "ocb4": 1, "ocb5": 1, "ocb6": 1, "ocb7": 1, "ocb8": 1, "ocb9": 1, "oi": 1, "one": 1, "onli": 1, "onto": 1, "oper": 1, "other": 1, "out": 1, "output": 1, "particular": 1, "pc": 1, "pcl0": 1, "pcl1": 1, "pcl2": 1, "pcl3": 1, "pcl4": 1, "pcl5": 1, "pcl6": 1, "pcl7": 1, "program": 1, "pull": 1, "ram": 1, "regist": 1, "repons": 1, "reset": 1, "result": 1, "retriev": 1, "ri": 1, "ro": 1, "rom": 1, "rro": 1, "sam": 1, "second": 1, "set": 1, "simultan": 1, "singl": 1, "smd": 1, "sst39sf010": 1, "state": 1, "store": 1, "su": 1, "subtract": 1, "sum": 1, "summat": 1, "t": 1, "tabl": 1, "thi": 1, "thu": 1, "ti": 1, "time": 1, "togeth": 1, "two": 1, "unit": 1, "unus": 1, "us": 1, "valu": 1, "we": 1, "which": 1, "within": 1, "x": 1}, "titles": ["SAP-SMD documentation", "Instruction decoder"], "titleterms": {"A": 1, "b": 1, "content": 0, "control": 1, "decod": 1, "document": 0, "instruct": 1, "line": 1, "map": 1, "orthogon": 1, "parallel": 1, "sap": 0, "smd": 0}}) \ No newline at end of file +Search.setIndex({"alltitles": {"Contents:": [[0, null]], "Explanation of every opt code": [[1, "id6"]], "Instruction decoder": [[1, null]], "Machine instructions": [[1, "machine-instructions"]], "Mapping": [[1, "mapping"]], "Microinstructions per t-state and per machine instruction": [[1, "id5"]], "Orthogonal Control Lines A": [[1, "id3"]], "Orthogonal Control Lines B": [[1, "id4"]], "Parallel Control Lines": [[1, "id2"]], "SAP-SMD documentation": [[0, null]]}, "docnames": ["index", "modules/instruction_decoder"], "envversion": {"sphinx": 64, "sphinx.domains.c": 3, "sphinx.domains.changeset": 1, "sphinx.domains.citation": 1, "sphinx.domains.cpp": 9, "sphinx.domains.index": 1, "sphinx.domains.javascript": 3, "sphinx.domains.math": 2, "sphinx.domains.python": 4, "sphinx.domains.rst": 2, "sphinx.domains.std": 2}, "filenames": ["index.rst", "modules/instruction_decoder.rst"], "indexentries": {"instruction decoder": [[1, "index-0", false]]}, "objects": {}, "objnames": {}, "objtypes": {}, "terms": {"0": 1, "1": 1, "15": 1, "2": 1, "20": 1, "3": 1, "30": 1, "4": 1, "5": 1, "6": 1, "74hc238": 1, "8": 1, "In": 1, "One": 1, "TO": 1, "The": 1, "abbrevi": 1, "activ": 1, "add": 1, "addr": 1, "address": 1, "ai": 1, "allow": 1, "alu": 1, "an": 1, "ani": 1, "ao": 1, "ar": 1, "arithmet": 1, "assert": 1, "below": 1, "benefit": 1, "bi": 1, "bo": 1, "bu": 1, "byte": 1, "can": 1, "ce": 1, "chip": 1, "clock": 1, "co": 1, "combin": 1, "come": 1, "content": 1, "count": 1, "counter": 1, "current": 1, "data": 1, "decod": 0, "descript": 1, "despit": 1, "direct": 1, "do": 1, "doe": 1, "e": 1, "each": 1, "eeprom": 1, "effect": 1, "enabl": 1, "eo": 1, "execut": 1, "far": 1, "fewer": 1, "fi": 1, "flag": 1, "follow": 1, "form": 1, "four": 1, "from": 1, "given": 1, "halt": 1, "here": 1, "high": 1, "hlt": 1, "i": 1, "ii": 1, "immedi": 1, "instead": 1, "instrucion": 1, "instruct": 0, "intern": 1, "ir": 1, "j": 1, "jp": 1, "jump": 1, "lda": 1, "ldb": 1, "limit": 1, "load": 1, "logic": 1, "loop": 1, "low": 1, "lra": 1, "lrb": 1, "machin": 0, "map": 0, "mar": 1, "memori": 1, "mi": 1, "micro": 1, "more": 1, "mr": 1, "need": 1, "new": 1, "nop": 1, "note": 1, "noth": 1, "number": 1, "oca1": 1, "oca10": 1, "oca11": 1, "oca12": 1, "oca13": 1, "oca14": 1, "oca15": 1, "oca2": 1, "oca3": 1, "oca4": 1, "oca5": 1, "oca6": 1, "oca7": 1, "oca8": 1, "oca9": 1, "ocb1": 1, "ocb10": 1, "ocb11": 1, "ocb12": 1, "ocb13": 1, "ocb14": 1, "ocb15": 1, "ocb2": 1, "ocb3": 1, "ocb4": 1, "ocb5": 1, "ocb6": 1, "ocb7": 1, "ocb8": 1, "ocb9": 1, "oi": 1, "one": 1, "onli": 1, "onto": 1, "oper": 1, "other": 1, "out": 1, "output": 1, "over": 1, "overwrit": 1, "particular": 1, "pc": 1, "pcl0": 1, "pcl1": 1, "pcl2": 1, "pcl3": 1, "pcl4": 1, "pcl5": 1, "pcl6": 1, "pcl7": 1, "program": 1, "provid": 1, "pull": 1, "ram": 1, "receiv": 1, "regist": 1, "repons": 1, "reset": 1, "result": 1, "retriev": 1, "ri": 1, "ro": 1, "rom": 1, "rro": 1, "rt": 1, "sam": 1, "second": 1, "secondari": 1, "sequenc": 1, "set": 1, "show": 1, "simultan": 1, "singl": 1, "smd": 1, "sst39sf010": 1, "sta": 1, "stb": 1, "store": 1, "su": 1, "subtract": 1, "sum": 1, "summat": 1, "tab": 1, "tabl": 1, "tao": 1, "tba": 1, "thi": 1, "thu": 1, "ti": 1, "time": 1, "togeth": 1, "transfer": 1, "two": 1, "ty": 1, "typic": 1, "unit": 1, "unus": 1, "up": 1, "upon": 1, "us": 1, "val": 1, "valu": 1, "we": 1, "what": 1, "which": 1, "within": 1, "x": 1}, "titles": ["SAP-SMD documentation", "Instruction decoder"], "titleterms": {"A": 1, "b": 1, "code": 1, "content": 0, "control": 1, "decod": 1, "document": 0, "everi": 1, "explan": 1, "instruct": 1, "line": 1, "machin": 1, "map": 1, "microinstruct": 1, "opt": 1, "orthogon": 1, "parallel": 1, "per": 1, "sap": 0, "smd": 0, "state": 1, "t": 1}}) \ No newline at end of file