diff --git a/build/build-dotnet b/build/build-dotnet index c469d2c91..9dc036507 100755 --- a/build/build-dotnet +++ b/build/build-dotnet @@ -36,7 +36,7 @@ new_func() { generator_check() { new_func "Run generator, verify no diff" - dotnet run -c $configuration -p "$root_dir/src/csharp/Intel/Generator/Generator.csproj" + dotnet run -c $configuration --project "$root_dir/src/csharp/Intel/Generator/Generator.csproj" git diff --exit-code } diff --git a/src/UnitTests/Intel/Decoder/Code.32Only.txt b/src/UnitTests/Intel/Decoder/Code.32Only.txt index a92bfd2c0..61347ffab 100644 --- a/src/UnitTests/Intel/Decoder/Code.32Only.txt +++ b/src/UnitTests/Intel/Decoder/Code.32Only.txt @@ -235,3 +235,7 @@ Cyrix_DEDE Frinear Ccs_hash_16 Ccs_encrypt_16 +Via_undoc_F30FA6F0_16 +Via_undoc_F30FA6F8_16 +Xsha512_16 +Xstore2_16 diff --git a/src/UnitTests/Intel/Decoder/Code.64Only.txt b/src/UnitTests/Intel/Decoder/Code.64Only.txt index c0321b2e8..1eb8e8405 100644 --- a/src/UnitTests/Intel/Decoder/Code.64Only.txt +++ b/src/UnitTests/Intel/Decoder/Code.64Only.txt @@ -716,3 +716,7 @@ MVEX_Vcvtfxpntps2dq_zmm_k1_zmmmt_imm8 MVEX_Undoc_zmm_k1_zmmmt_imm8_512_66_0F3A_W0_D0 MVEX_Undoc_zmm_k1_zmmmt_imm8_512_66_0F3A_W0_D1 MVEX_Vcvtfxpntpd2dq_zmm_k1_zmmmt_imm8 +Via_undoc_F30FA6F0_64 +Via_undoc_F30FA6F8_64 +Xsha512_64 +Xstore2_64 diff --git a/src/UnitTests/Intel/Decoder/DecoderTest16.txt b/src/UnitTests/Intel/Decoder/DecoderTest16.txt index 2de8abf27..987ffad28 100644 --- a/src/UnitTests/Intel/Decoder/DecoderTest16.txt +++ b/src/UnitTests/Intel/Decoder/DecoderTest16.txt @@ -8750,35 +8750,158 @@ C4C1F9 99 D3, VEX_Ktestd_kr_kr, Ktestd, 2, op0=r;k2 op1=r;k3 enc=C4E1F999D3 66 0FA5 CE, Shld_rm32_r32_CL, Shld, 3, op0=r;esi op1=r;ecx op2=r;cl 66 0FA5 18, Shld_rm32_r32_CL, Shld, 3, op0=m;ds;bx;si;1;0;0;UInt32 op1=r;ebx op2=r;cl -F3 0FA6 C0, Montmul_16, Montmul, 0, rep +F3 0FA6 C0, INVALID, INVALID, 0, code=Montmul_16 F2 0FA6 C0, INVALID, INVALID, 0, code=Montmul_16 -F2 F3 0FA6 C0, Montmul_16, Montmul, 0, rep enc=F30FA6C0 -F3 F2 0FA6 C0, INVALID, INVALID, 0, code=Montmul_16 -0FA6 C0, INVALID, INVALID, 0, code=Montmul_16 +F3 0FA6 C0, Montmul_16, Montmul, 0, rep decopt=NoInvalidCheck +F2 0FA6 C0, INVALID, INVALID, 0, code=Montmul_16 decopt=NoInvalidCheck +F2 F3 0FA6 C0, Montmul_16, Montmul, 0, rep enc=F30FA6C0 decopt=NoInvalidCheck +F3 F2 0FA6 C0, INVALID, INVALID, 0, code=Montmul_16 decopt=NoInvalidCheck +0FA6 C0, INVALID, INVALID, 0, code=Montmul_16 decopt=NoInvalidCheck +F3 0FA6 C1, INVALID, INVALID, 0, code=Montmul_16 +F3 0FA6 C2, INVALID, INVALID, 0, code=Montmul_16 +F3 0FA6 C3, INVALID, INVALID, 0, code=Montmul_16 +F3 0FA6 C4, INVALID, INVALID, 0, code=Montmul_16 +F3 0FA6 C5, INVALID, INVALID, 0, code=Montmul_16 +F3 0FA6 C6, INVALID, INVALID, 0, code=Montmul_16 +F3 0FA6 C7, INVALID, INVALID, 0, code=Montmul_16 +F3 0FA6 C1, Montmul_16, Montmul, 0, rep decopt=NoInvalidCheck enc=F30FA6C0 +F3 0FA6 C2, Montmul_16, Montmul, 0, rep decopt=NoInvalidCheck enc=F30FA6C0 +F3 0FA6 C3, Montmul_16, Montmul, 0, rep decopt=NoInvalidCheck enc=F30FA6C0 +F3 0FA6 C4, Montmul_16, Montmul, 0, rep decopt=NoInvalidCheck enc=F30FA6C0 +F3 0FA6 C5, Montmul_16, Montmul, 0, rep decopt=NoInvalidCheck enc=F30FA6C0 +F3 0FA6 C6, Montmul_16, Montmul, 0, rep decopt=NoInvalidCheck enc=F30FA6C0 +F3 0FA6 C7, Montmul_16, Montmul, 0, rep decopt=NoInvalidCheck enc=F30FA6C0 F3 67 0FA6 C0, Montmul_32, Montmul, 0, rep enc=67F30FA6C0 67 F3 0FA6 C0, Montmul_32, Montmul, 0, rep 67 0FA6 C0, INVALID, INVALID, 0, code=Montmul_32 +67 F3 0FA6 C1, Montmul_32, Montmul, 0, rep enc=67F30FA6C0 +67 F3 0FA6 C2, Montmul_32, Montmul, 0, rep enc=67F30FA6C0 +67 F3 0FA6 C3, Montmul_32, Montmul, 0, rep enc=67F30FA6C0 +67 F3 0FA6 C4, Montmul_32, Montmul, 0, rep enc=67F30FA6C0 +67 F3 0FA6 C5, Montmul_32, Montmul, 0, rep enc=67F30FA6C0 +67 F3 0FA6 C6, Montmul_32, Montmul, 0, rep enc=67F30FA6C0 +67 F3 0FA6 C7, Montmul_32, Montmul, 0, rep enc=67F30FA6C0 F3 0FA6 C8, Xsha1_16, Xsha1, 0, rep F2 0FA6 C8, INVALID, INVALID, 0, code=Xsha1_16 F2 F3 0FA6 C8, Xsha1_16, Xsha1, 0, rep enc=F30FA6C8 F3 F2 0FA6 C8, INVALID, INVALID, 0, code=Xsha1_16 0FA6 C8, INVALID, INVALID, 0, code=Xsha1_16 +F3 0FA6 C9, Xsha1_16, Xsha1, 0, rep enc=F30FA6C8 +F3 0FA6 CA, Xsha1_16, Xsha1, 0, rep enc=F30FA6C8 +F3 0FA6 CB, Xsha1_16, Xsha1, 0, rep enc=F30FA6C8 +F3 0FA6 CC, Xsha1_16, Xsha1, 0, rep enc=F30FA6C8 +F3 0FA6 CD, Xsha1_16, Xsha1, 0, rep enc=F30FA6C8 +F3 0FA6 CE, Xsha1_16, Xsha1, 0, rep enc=F30FA6C8 +F3 0FA6 CF, Xsha1_16, Xsha1, 0, rep enc=F30FA6C8 F3 67 0FA6 C8, Xsha1_32, Xsha1, 0, rep enc=67F30FA6C8 67 F3 0FA6 C8, Xsha1_32, Xsha1, 0, rep 67 0FA6 C8, INVALID, INVALID, 0, code=Xsha1_32 +67 F3 0FA6 C9, Xsha1_32, Xsha1, 0, rep enc=67F30FA6C8 +67 F3 0FA6 CA, Xsha1_32, Xsha1, 0, rep enc=67F30FA6C8 +67 F3 0FA6 CB, Xsha1_32, Xsha1, 0, rep enc=67F30FA6C8 +67 F3 0FA6 CC, Xsha1_32, Xsha1, 0, rep enc=67F30FA6C8 +67 F3 0FA6 CD, Xsha1_32, Xsha1, 0, rep enc=67F30FA6C8 +67 F3 0FA6 CE, Xsha1_32, Xsha1, 0, rep enc=67F30FA6C8 +67 F3 0FA6 CF, Xsha1_32, Xsha1, 0, rep enc=67F30FA6C8 F3 0FA6 D0, Xsha256_16, Xsha256, 0, rep F2 0FA6 D0, INVALID, INVALID, 0, code=Xsha256_16 F2 F3 0FA6 D0, Xsha256_16, Xsha256, 0, rep enc=F30FA6D0 F3 F2 0FA6 D0, INVALID, INVALID, 0, code=Xsha256_16 0FA6 D0, INVALID, INVALID, 0, code=Xsha256_16 +F3 0FA6 D1, Xsha256_16, Xsha256, 0, rep enc=F30FA6D0 +F3 0FA6 D2, Xsha256_16, Xsha256, 0, rep enc=F30FA6D0 +F3 0FA6 D3, Xsha256_16, Xsha256, 0, rep enc=F30FA6D0 +F3 0FA6 D4, Xsha256_16, Xsha256, 0, rep enc=F30FA6D0 +F3 0FA6 D5, Xsha256_16, Xsha256, 0, rep enc=F30FA6D0 +F3 0FA6 D6, Xsha256_16, Xsha256, 0, rep enc=F30FA6D0 +F3 0FA6 D7, Xsha256_16, Xsha256, 0, rep enc=F30FA6D0 F3 67 0FA6 D0, Xsha256_32, Xsha256, 0, rep enc=67F30FA6D0 67 F3 0FA6 D0, Xsha256_32, Xsha256, 0, rep 67 0FA6 D0, INVALID, INVALID, 0, code=Xsha256_32 +67 F3 0FA6 D1, Xsha256_32, Xsha256, 0, rep enc=67F30FA6D0 +67 F3 0FA6 D2, Xsha256_32, Xsha256, 0, rep enc=67F30FA6D0 +67 F3 0FA6 D3, Xsha256_32, Xsha256, 0, rep enc=67F30FA6D0 +67 F3 0FA6 D4, Xsha256_32, Xsha256, 0, rep enc=67F30FA6D0 +67 F3 0FA6 D5, Xsha256_32, Xsha256, 0, rep enc=67F30FA6D0 +67 F3 0FA6 D6, Xsha256_32, Xsha256, 0, rep enc=67F30FA6D0 +67 F3 0FA6 D7, Xsha256_32, Xsha256, 0, rep enc=67F30FA6D0 + +F3 0FA6 E0, Xsha512_16, Xsha512, 0, rep +F2 0FA6 E0, INVALID, INVALID, 0, code=Xsha512_16 +F2 F3 0FA6 E0, Xsha512_16, Xsha512, 0, rep enc=F30FA6E0 +F3 F2 0FA6 E0, INVALID, INVALID, 0, code=Xsha512_16 +0FA6 E0, INVALID, INVALID, 0, code=Xsha512_16 +F3 0FA6 E1, Xsha512_16, Xsha512, 0, rep enc=F30FA6E0 +F3 0FA6 E2, Xsha512_16, Xsha512, 0, rep enc=F30FA6E0 +F3 0FA6 E3, Xsha512_16, Xsha512, 0, rep enc=F30FA6E0 +F3 0FA6 E4, Xsha512_16, Xsha512, 0, rep enc=F30FA6E0 +F3 0FA6 E5, Xsha512_16, Xsha512, 0, rep enc=F30FA6E0 +F3 0FA6 E6, Xsha512_16, Xsha512, 0, rep enc=F30FA6E0 +F3 0FA6 E7, Xsha512_16, Xsha512, 0, rep enc=F30FA6E0 + +F3 67 0FA6 E0, Xsha512_32, Xsha512, 0, rep enc=67F30FA6E0 +67 F3 0FA6 E0, Xsha512_32, Xsha512, 0, rep +67 0FA6 E0, INVALID, INVALID, 0, code=Xsha512_32 +67 F3 0FA6 E1, Xsha512_32, Xsha512, 0, rep enc=67F30FA6E0 +67 F3 0FA6 E2, Xsha512_32, Xsha512, 0, rep enc=67F30FA6E0 +67 F3 0FA6 E3, Xsha512_32, Xsha512, 0, rep enc=67F30FA6E0 +67 F3 0FA6 E4, Xsha512_32, Xsha512, 0, rep enc=67F30FA6E0 +67 F3 0FA6 E5, Xsha512_32, Xsha512, 0, rep enc=67F30FA6E0 +67 F3 0FA6 E6, Xsha512_32, Xsha512, 0, rep enc=67F30FA6E0 +67 F3 0FA6 E7, Xsha512_32, Xsha512, 0, rep enc=67F30FA6E0 + +F3 0FA6 F0, Via_undoc_F30FA6F0_16, Undoc, 0, rep +F2 0FA6 F0, INVALID, INVALID, 0, code=Via_undoc_F30FA6F0_16 +F2 F3 0FA6 F0, Via_undoc_F30FA6F0_16, Undoc, 0, rep enc=F30FA6F0 +F3 F2 0FA6 F0, INVALID, INVALID, 0, code=Via_undoc_F30FA6F0_16 +0FA6 F0, INVALID, INVALID, 0, code=Via_undoc_F30FA6F0_16 +F3 0FA6 F1, Via_undoc_F30FA6F0_16, Undoc, 0, rep enc=F30FA6F0 +F3 0FA6 F2, Via_undoc_F30FA6F0_16, Undoc, 0, rep enc=F30FA6F0 +F3 0FA6 F3, Via_undoc_F30FA6F0_16, Undoc, 0, rep enc=F30FA6F0 +F3 0FA6 F4, Via_undoc_F30FA6F0_16, Undoc, 0, rep enc=F30FA6F0 +F3 0FA6 F5, Via_undoc_F30FA6F0_16, Undoc, 0, rep enc=F30FA6F0 +F3 0FA6 F6, Via_undoc_F30FA6F0_16, Undoc, 0, rep enc=F30FA6F0 +F3 0FA6 F7, Via_undoc_F30FA6F0_16, Undoc, 0, rep enc=F30FA6F0 + +F3 67 0FA6 F0, Via_undoc_F30FA6F0_32, Undoc, 0, rep enc=67F30FA6F0 +67 F3 0FA6 F0, Via_undoc_F30FA6F0_32, Undoc, 0, rep +67 0FA6 F0, INVALID, INVALID, 0, code=Via_undoc_F30FA6F0_32 +67 F3 0FA6 F1, Via_undoc_F30FA6F0_32, Undoc, 0, rep enc=67F30FA6F0 +67 F3 0FA6 F2, Via_undoc_F30FA6F0_32, Undoc, 0, rep enc=67F30FA6F0 +67 F3 0FA6 F3, Via_undoc_F30FA6F0_32, Undoc, 0, rep enc=67F30FA6F0 +67 F3 0FA6 F4, Via_undoc_F30FA6F0_32, Undoc, 0, rep enc=67F30FA6F0 +67 F3 0FA6 F5, Via_undoc_F30FA6F0_32, Undoc, 0, rep enc=67F30FA6F0 +67 F3 0FA6 F6, Via_undoc_F30FA6F0_32, Undoc, 0, rep enc=67F30FA6F0 +67 F3 0FA6 F7, Via_undoc_F30FA6F0_32, Undoc, 0, rep enc=67F30FA6F0 + +F3 0FA6 F8, Via_undoc_F30FA6F8_16, Undoc, 0, rep +F2 0FA6 F8, INVALID, INVALID, 0, code=Via_undoc_F30FA6F8_16 +F2 F3 0FA6 F8, Via_undoc_F30FA6F8_16, Undoc, 0, rep enc=F30FA6F8 +F3 F2 0FA6 F8, INVALID, INVALID, 0, code=Via_undoc_F30FA6F8_16 +0FA6 F8, INVALID, INVALID, 0, code=Via_undoc_F30FA6F8_16 +F3 0FA6 F9, Via_undoc_F30FA6F8_16, Undoc, 0, rep enc=F30FA6F8 +F3 0FA6 FA, Via_undoc_F30FA6F8_16, Undoc, 0, rep enc=F30FA6F8 +F3 0FA6 FB, Via_undoc_F30FA6F8_16, Undoc, 0, rep enc=F30FA6F8 +F3 0FA6 FC, Via_undoc_F30FA6F8_16, Undoc, 0, rep enc=F30FA6F8 +F3 0FA6 FD, Via_undoc_F30FA6F8_16, Undoc, 0, rep enc=F30FA6F8 +F3 0FA6 FE, Via_undoc_F30FA6F8_16, Undoc, 0, rep enc=F30FA6F8 +F3 0FA6 FF, Via_undoc_F30FA6F8_16, Undoc, 0, rep enc=F30FA6F8 + +F3 67 0FA6 F8, Via_undoc_F30FA6F8_32, Undoc, 0, rep enc=67F30FA6F8 +67 F3 0FA6 F8, Via_undoc_F30FA6F8_32, Undoc, 0, rep +67 0FA6 F8, INVALID, INVALID, 0, code=Via_undoc_F30FA6F8_32 +67 F3 0FA6 F9, Via_undoc_F30FA6F8_32, Undoc, 0, rep enc=67F30FA6F8 +67 F3 0FA6 FA, Via_undoc_F30FA6F8_32, Undoc, 0, rep enc=67F30FA6F8 +67 F3 0FA6 FB, Via_undoc_F30FA6F8_32, Undoc, 0, rep enc=67F30FA6F8 +67 F3 0FA6 FC, Via_undoc_F30FA6F8_32, Undoc, 0, rep enc=67F30FA6F8 +67 F3 0FA6 FD, Via_undoc_F30FA6F8_32, Undoc, 0, rep enc=67F30FA6F8 +67 F3 0FA6 FE, Via_undoc_F30FA6F8_32, Undoc, 0, rep enc=67F30FA6F8 +67 F3 0FA6 FF, Via_undoc_F30FA6F8_32, Undoc, 0, rep enc=67F30FA6F8 0FA6 CE, Xbts_r16_rm16, Xbts, 2, op0=r;cx op1=r;si decopt=Xbts 0FA6 CE, Xbts_r16_rm16, Xbts, 2, op0=r;cx op1=r;si decopt=Xbts decopt=Cmpxchg486A @@ -8804,60 +8927,197 @@ F2 0FA7 C0, Xstore_16, Xstore, 0, repne F2 F3 0FA7 C0, Xstore_16, Xstore, 0, rep enc=F30FA7C0 F3 F2 0FA7 C0, Xstore_16, Xstore, 0, repne enc=F20FA7C0 0FA7 C0, Xstore_16, Xstore, 0, +F3 0FA7 C1, Xstore_16, Xstore, 0, rep enc=F30FA7C0 +F3 0FA7 C2, Xstore_16, Xstore, 0, rep enc=F30FA7C0 +F3 0FA7 C3, Xstore_16, Xstore, 0, rep enc=F30FA7C0 +F3 0FA7 C4, Xstore_16, Xstore, 0, rep enc=F30FA7C0 +F3 0FA7 C5, Xstore_16, Xstore, 0, rep enc=F30FA7C0 +F3 0FA7 C6, Xstore_16, Xstore, 0, rep enc=F30FA7C0 +F3 0FA7 C7, Xstore_16, Xstore, 0, rep enc=F30FA7C0 +F2 0FA7 C1, Xstore_16, Xstore, 0, repne enc=F20FA7C0 +F2 0FA7 C2, Xstore_16, Xstore, 0, repne enc=F20FA7C0 +F2 0FA7 C3, Xstore_16, Xstore, 0, repne enc=F20FA7C0 +F2 0FA7 C4, Xstore_16, Xstore, 0, repne enc=F20FA7C0 +F2 0FA7 C5, Xstore_16, Xstore, 0, repne enc=F20FA7C0 +F2 0FA7 C6, Xstore_16, Xstore, 0, repne enc=F20FA7C0 +F2 0FA7 C7, Xstore_16, Xstore, 0, repne enc=F20FA7C0 F3 67 0FA7 C0, Xstore_32, Xstore, 0, rep enc=67F30FA7C0 67 F3 0FA7 C0, Xstore_32, Xstore, 0, rep 67 0FA7 C0, Xstore_32, Xstore, 0, +67 F3 0FA7 C1, Xstore_32, Xstore, 0, rep enc=67F30FA7C0 +67 F3 0FA7 C2, Xstore_32, Xstore, 0, rep enc=67F30FA7C0 +67 F3 0FA7 C3, Xstore_32, Xstore, 0, rep enc=67F30FA7C0 +67 F3 0FA7 C4, Xstore_32, Xstore, 0, rep enc=67F30FA7C0 +67 F3 0FA7 C5, Xstore_32, Xstore, 0, rep enc=67F30FA7C0 +67 F3 0FA7 C6, Xstore_32, Xstore, 0, rep enc=67F30FA7C0 +67 F3 0FA7 C7, Xstore_32, Xstore, 0, rep enc=67F30FA7C0 +67 F2 0FA7 C0, Xstore_32, Xstore, 0, repne enc=67F20FA7C0 +67 F2 0FA7 C1, Xstore_32, Xstore, 0, repne enc=67F20FA7C0 +67 F2 0FA7 C2, Xstore_32, Xstore, 0, repne enc=67F20FA7C0 +67 F2 0FA7 C3, Xstore_32, Xstore, 0, repne enc=67F20FA7C0 +67 F2 0FA7 C4, Xstore_32, Xstore, 0, repne enc=67F20FA7C0 +67 F2 0FA7 C5, Xstore_32, Xstore, 0, repne enc=67F20FA7C0 +67 F2 0FA7 C6, Xstore_32, Xstore, 0, repne enc=67F20FA7C0 +67 F2 0FA7 C7, Xstore_32, Xstore, 0, repne enc=67F20FA7C0 + +F3 0FA7 F8, Xstore2_16, Xstore2, 0, rep +F2 0FA7 F8, INVALID, INVALID, 0, code=Xstore2_16 +F2 F3 0FA7 F8, Xstore2_16, Xstore2, 0, rep enc=F30FA7F8 +F3 F2 0FA7 F8, INVALID, INVALID, 0, code=Xstore2_16 +0FA7 F8, INVALID, INVALID, 0, code=Xstore2_16 +F3 0FA7 F9, Xstore2_16, Xstore2, 0, rep enc=F30FA7F8 +F3 0FA7 FA, Xstore2_16, Xstore2, 0, rep enc=F30FA7F8 +F3 0FA7 FB, Xstore2_16, Xstore2, 0, rep enc=F30FA7F8 +F3 0FA7 FC, Xstore2_16, Xstore2, 0, rep enc=F30FA7F8 +F3 0FA7 FD, Xstore2_16, Xstore2, 0, rep enc=F30FA7F8 +F3 0FA7 FE, Xstore2_16, Xstore2, 0, rep enc=F30FA7F8 +F3 0FA7 FF, Xstore2_16, Xstore2, 0, rep enc=F30FA7F8 +F2 0FA7 F9, INVALID, INVALID, 0, code=Xstore2_16 +F2 0FA7 FA, INVALID, INVALID, 0, code=Xstore2_16 +F2 0FA7 FB, INVALID, INVALID, 0, code=Xstore2_16 +F2 0FA7 FC, INVALID, INVALID, 0, code=Xstore2_16 +F2 0FA7 FD, INVALID, INVALID, 0, code=Xstore2_16 +F2 0FA7 FE, INVALID, INVALID, 0, code=Xstore2_16 +F2 0FA7 FF, INVALID, INVALID, 0, code=Xstore2_16 + +F3 67 0FA7 F8, Xstore2_32, Xstore2, 0, rep enc=67F30FA7F8 +67 F3 0FA7 F8, Xstore2_32, Xstore2, 0, rep +67 0FA7 F8, INVALID, INVALID, 0, code=Xstore2_32 +67 F3 0FA7 F9, Xstore2_32, Xstore2, 0, rep enc=67F30FA7F8 +67 F3 0FA7 FA, Xstore2_32, Xstore2, 0, rep enc=67F30FA7F8 +67 F3 0FA7 FB, Xstore2_32, Xstore2, 0, rep enc=67F30FA7F8 +67 F3 0FA7 FC, Xstore2_32, Xstore2, 0, rep enc=67F30FA7F8 +67 F3 0FA7 FD, Xstore2_32, Xstore2, 0, rep enc=67F30FA7F8 +67 F3 0FA7 FE, Xstore2_32, Xstore2, 0, rep enc=67F30FA7F8 +67 F3 0FA7 FF, Xstore2_32, Xstore2, 0, rep enc=67F30FA7F8 +67 F2 0FA7 F9, INVALID, INVALID, 0, code=Xstore2_32 +67 F2 0FA7 FA, INVALID, INVALID, 0, code=Xstore2_32 +67 F2 0FA7 FB, INVALID, INVALID, 0, code=Xstore2_32 +67 F2 0FA7 FC, INVALID, INVALID, 0, code=Xstore2_32 +67 F2 0FA7 FD, INVALID, INVALID, 0, code=Xstore2_32 +67 F2 0FA7 FE, INVALID, INVALID, 0, code=Xstore2_32 +67 F2 0FA7 FF, INVALID, INVALID, 0, code=Xstore2_32 F3 0FA7 C8, Xcryptecb_16, Xcryptecb, 0, rep F2 0FA7 C8, INVALID, INVALID, 0, code=Xcryptecb_16 F2 F3 0FA7 C8, Xcryptecb_16, Xcryptecb, 0, rep enc=F30FA7C8 F3 F2 0FA7 C8, INVALID, INVALID, 0, code=Xcryptecb_16 0FA7 C8, INVALID, INVALID, 0, code=Xcryptecb_16 +F3 0FA7 C9, Xcryptecb_16, Xcryptecb, 0, rep enc=F30FA7C8 +F3 0FA7 CA, Xcryptecb_16, Xcryptecb, 0, rep enc=F30FA7C8 +F3 0FA7 CB, Xcryptecb_16, Xcryptecb, 0, rep enc=F30FA7C8 +F3 0FA7 CC, Xcryptecb_16, Xcryptecb, 0, rep enc=F30FA7C8 +F3 0FA7 CD, Xcryptecb_16, Xcryptecb, 0, rep enc=F30FA7C8 +F3 0FA7 CE, Xcryptecb_16, Xcryptecb, 0, rep enc=F30FA7C8 +F3 0FA7 CF, Xcryptecb_16, Xcryptecb, 0, rep enc=F30FA7C8 F3 67 0FA7 C8, Xcryptecb_32, Xcryptecb, 0, rep enc=67F30FA7C8 67 F3 0FA7 C8, Xcryptecb_32, Xcryptecb, 0, rep 67 0FA7 C8, INVALID, INVALID, 0, code=Xcryptecb_32 +67 F3 0FA7 C9, Xcryptecb_32, Xcryptecb, 0, rep enc=67F30FA7C8 +67 F3 0FA7 CA, Xcryptecb_32, Xcryptecb, 0, rep enc=67F30FA7C8 +67 F3 0FA7 CB, Xcryptecb_32, Xcryptecb, 0, rep enc=67F30FA7C8 +67 F3 0FA7 CC, Xcryptecb_32, Xcryptecb, 0, rep enc=67F30FA7C8 +67 F3 0FA7 CD, Xcryptecb_32, Xcryptecb, 0, rep enc=67F30FA7C8 +67 F3 0FA7 CE, Xcryptecb_32, Xcryptecb, 0, rep enc=67F30FA7C8 +67 F3 0FA7 CF, Xcryptecb_32, Xcryptecb, 0, rep enc=67F30FA7C8 F3 0FA7 D0, Xcryptcbc_16, Xcryptcbc, 0, rep F2 0FA7 D0, INVALID, INVALID, 0, code=Xcryptcbc_16 F2 F3 0FA7 D0, Xcryptcbc_16, Xcryptcbc, 0, rep enc=F30FA7D0 F3 F2 0FA7 D0, INVALID, INVALID, 0, code=Xcryptcbc_16 0FA7 D0, INVALID, INVALID, 0, code=Xcryptcbc_16 +F3 0FA7 D1, Xcryptcbc_16, Xcryptcbc, 0, rep enc=F30FA7D0 +F3 0FA7 D2, Xcryptcbc_16, Xcryptcbc, 0, rep enc=F30FA7D0 +F3 0FA7 D3, Xcryptcbc_16, Xcryptcbc, 0, rep enc=F30FA7D0 +F3 0FA7 D4, Xcryptcbc_16, Xcryptcbc, 0, rep enc=F30FA7D0 +F3 0FA7 D5, Xcryptcbc_16, Xcryptcbc, 0, rep enc=F30FA7D0 +F3 0FA7 D6, Xcryptcbc_16, Xcryptcbc, 0, rep enc=F30FA7D0 +F3 0FA7 D7, Xcryptcbc_16, Xcryptcbc, 0, rep enc=F30FA7D0 F3 67 0FA7 D0, Xcryptcbc_32, Xcryptcbc, 0, rep enc=67F30FA7D0 67 F3 0FA7 D0, Xcryptcbc_32, Xcryptcbc, 0, rep 67 0FA7 D0, INVALID, INVALID, 0, code=Xcryptcbc_32 +67 F3 0FA7 D1, Xcryptcbc_32, Xcryptcbc, 0, rep enc=67F30FA7D0 +67 F3 0FA7 D2, Xcryptcbc_32, Xcryptcbc, 0, rep enc=67F30FA7D0 +67 F3 0FA7 D3, Xcryptcbc_32, Xcryptcbc, 0, rep enc=67F30FA7D0 +67 F3 0FA7 D4, Xcryptcbc_32, Xcryptcbc, 0, rep enc=67F30FA7D0 +67 F3 0FA7 D5, Xcryptcbc_32, Xcryptcbc, 0, rep enc=67F30FA7D0 +67 F3 0FA7 D6, Xcryptcbc_32, Xcryptcbc, 0, rep enc=67F30FA7D0 +67 F3 0FA7 D7, Xcryptcbc_32, Xcryptcbc, 0, rep enc=67F30FA7D0 F3 0FA7 D8, Xcryptctr_16, Xcryptctr, 0, rep F2 0FA7 D8, INVALID, INVALID, 0, code=Xcryptctr_16 F2 F3 0FA7 D8, Xcryptctr_16, Xcryptctr, 0, rep enc=F30FA7D8 F3 F2 0FA7 D8, INVALID, INVALID, 0, code=Xcryptctr_16 0FA7 D8, INVALID, INVALID, 0, code=Xcryptctr_16 +F3 0FA7 D9, Xcryptctr_16, Xcryptctr, 0, rep enc=F30FA7D8 +F3 0FA7 DA, Xcryptctr_16, Xcryptctr, 0, rep enc=F30FA7D8 +F3 0FA7 DB, Xcryptctr_16, Xcryptctr, 0, rep enc=F30FA7D8 +F3 0FA7 DC, Xcryptctr_16, Xcryptctr, 0, rep enc=F30FA7D8 +F3 0FA7 DD, Xcryptctr_16, Xcryptctr, 0, rep enc=F30FA7D8 +F3 0FA7 DE, Xcryptctr_16, Xcryptctr, 0, rep enc=F30FA7D8 +F3 0FA7 DF, Xcryptctr_16, Xcryptctr, 0, rep enc=F30FA7D8 F3 67 0FA7 D8, Xcryptctr_32, Xcryptctr, 0, rep enc=67F30FA7D8 67 F3 0FA7 D8, Xcryptctr_32, Xcryptctr, 0, rep 67 0FA7 D8, INVALID, INVALID, 0, code=Xcryptctr_32 +67 F3 0FA7 D9, Xcryptctr_32, Xcryptctr, 0, rep enc=67F30FA7D8 +67 F3 0FA7 DA, Xcryptctr_32, Xcryptctr, 0, rep enc=67F30FA7D8 +67 F3 0FA7 DB, Xcryptctr_32, Xcryptctr, 0, rep enc=67F30FA7D8 +67 F3 0FA7 DC, Xcryptctr_32, Xcryptctr, 0, rep enc=67F30FA7D8 +67 F3 0FA7 DD, Xcryptctr_32, Xcryptctr, 0, rep enc=67F30FA7D8 +67 F3 0FA7 DE, Xcryptctr_32, Xcryptctr, 0, rep enc=67F30FA7D8 +67 F3 0FA7 DF, Xcryptctr_32, Xcryptctr, 0, rep enc=67F30FA7D8 F3 0FA7 E0, Xcryptcfb_16, Xcryptcfb, 0, rep F2 0FA7 E0, INVALID, INVALID, 0, code=Xcryptcfb_16 F2 F3 0FA7 E0, Xcryptcfb_16, Xcryptcfb, 0, rep enc=F30FA7E0 F3 F2 0FA7 E0, INVALID, INVALID, 0, code=Xcryptcfb_16 0FA7 E0, INVALID, INVALID, 0, code=Xcryptcfb_16 +F3 0FA7 E1, Xcryptcfb_16, Xcryptcfb, 0, rep enc=F30FA7E0 +F3 0FA7 E2, Xcryptcfb_16, Xcryptcfb, 0, rep enc=F30FA7E0 +F3 0FA7 E3, Xcryptcfb_16, Xcryptcfb, 0, rep enc=F30FA7E0 +F3 0FA7 E4, Xcryptcfb_16, Xcryptcfb, 0, rep enc=F30FA7E0 +F3 0FA7 E5, Xcryptcfb_16, Xcryptcfb, 0, rep enc=F30FA7E0 +F3 0FA7 E6, Xcryptcfb_16, Xcryptcfb, 0, rep enc=F30FA7E0 +F3 0FA7 E7, Xcryptcfb_16, Xcryptcfb, 0, rep enc=F30FA7E0 F3 67 0FA7 E0, Xcryptcfb_32, Xcryptcfb, 0, rep enc=67F30FA7E0 67 F3 0FA7 E0, Xcryptcfb_32, Xcryptcfb, 0, rep 67 0FA7 E0, INVALID, INVALID, 0, code=Xcryptcfb_32 +67 F3 0FA7 E1, Xcryptcfb_32, Xcryptcfb, 0, rep enc=67F30FA7E0 +67 F3 0FA7 E2, Xcryptcfb_32, Xcryptcfb, 0, rep enc=67F30FA7E0 +67 F3 0FA7 E3, Xcryptcfb_32, Xcryptcfb, 0, rep enc=67F30FA7E0 +67 F3 0FA7 E4, Xcryptcfb_32, Xcryptcfb, 0, rep enc=67F30FA7E0 +67 F3 0FA7 E5, Xcryptcfb_32, Xcryptcfb, 0, rep enc=67F30FA7E0 +67 F3 0FA7 E6, Xcryptcfb_32, Xcryptcfb, 0, rep enc=67F30FA7E0 +67 F3 0FA7 E7, Xcryptcfb_32, Xcryptcfb, 0, rep enc=67F30FA7E0 F3 0FA7 E8, Xcryptofb_16, Xcryptofb, 0, rep F2 0FA7 E8, INVALID, INVALID, 0, code=Xcryptofb_16 F2 F3 0FA7 E8, Xcryptofb_16, Xcryptofb, 0, rep enc=F30FA7E8 F3 F2 0FA7 E8, INVALID, INVALID, 0, code=Xcryptofb_16 0FA7 E8, INVALID, INVALID, 0, code=Xcryptofb_16 +F3 0FA7 E9, Xcryptofb_16, Xcryptofb, 0, rep enc=F30FA7E8 +F3 0FA7 EA, Xcryptofb_16, Xcryptofb, 0, rep enc=F30FA7E8 +F3 0FA7 EB, Xcryptofb_16, Xcryptofb, 0, rep enc=F30FA7E8 +F3 0FA7 EC, Xcryptofb_16, Xcryptofb, 0, rep enc=F30FA7E8 +F3 0FA7 ED, Xcryptofb_16, Xcryptofb, 0, rep enc=F30FA7E8 +F3 0FA7 EE, Xcryptofb_16, Xcryptofb, 0, rep enc=F30FA7E8 +F3 0FA7 EF, Xcryptofb_16, Xcryptofb, 0, rep enc=F30FA7E8 F3 67 0FA7 E8, Xcryptofb_32, Xcryptofb, 0, rep enc=67F30FA7E8 67 F3 0FA7 E8, Xcryptofb_32, Xcryptofb, 0, rep 67 0FA7 E8, INVALID, INVALID, 0, code=Xcryptofb_32 +67 F3 0FA7 E9, Xcryptofb_32, Xcryptofb, 0, rep enc=67F30FA7E8 +67 F3 0FA7 EA, Xcryptofb_32, Xcryptofb, 0, rep enc=67F30FA7E8 +67 F3 0FA7 EB, Xcryptofb_32, Xcryptofb, 0, rep enc=67F30FA7E8 +67 F3 0FA7 EC, Xcryptofb_32, Xcryptofb, 0, rep enc=67F30FA7E8 +67 F3 0FA7 ED, Xcryptofb_32, Xcryptofb, 0, rep enc=67F30FA7E8 +67 F3 0FA7 EE, Xcryptofb_32, Xcryptofb, 0, rep enc=67F30FA7E8 +67 F3 0FA7 EF, Xcryptofb_32, Xcryptofb, 0, rep enc=67F30FA7E8 0FA7 CE, Cmpxchg486_rm16_r16, Cmpxchg, 2, op0=r;si op1=r;cx decopt=Cmpxchg486A 0FA7 18, Cmpxchg486_rm16_r16, Cmpxchg, 2, op0=m;ds;bx;si;1;0;0;UInt16 op1=r;bx decopt=Cmpxchg486A @@ -21750,20 +22010,48 @@ F2 0FA6 E8, INVALID, INVALID, 0, code=Ccs_hash_16 F2 F3 0FA6 E8, Ccs_hash_16, Ccs_hash, 0, rep enc=F30FA6E8 F3 F2 0FA6 E8, INVALID, INVALID, 0, code=Ccs_hash_16 0FA6 E8, INVALID, INVALID, 0, code=Ccs_hash_16 +F3 0FA6 E9, Ccs_hash_16, Ccs_hash, 0, rep enc=F30FA6E8 +F3 0FA6 EA, Ccs_hash_16, Ccs_hash, 0, rep enc=F30FA6E8 +F3 0FA6 EB, Ccs_hash_16, Ccs_hash, 0, rep enc=F30FA6E8 +F3 0FA6 EC, Ccs_hash_16, Ccs_hash, 0, rep enc=F30FA6E8 +F3 0FA6 ED, Ccs_hash_16, Ccs_hash, 0, rep enc=F30FA6E8 +F3 0FA6 EE, Ccs_hash_16, Ccs_hash, 0, rep enc=F30FA6E8 +F3 0FA6 EF, Ccs_hash_16, Ccs_hash, 0, rep enc=F30FA6E8 F3 67 0FA6 E8, Ccs_hash_32, Ccs_hash, 0, rep enc=67F30FA6E8 67 F3 0FA6 E8, Ccs_hash_32, Ccs_hash, 0, rep 67 0FA6 E8, INVALID, INVALID, 0, code=Ccs_hash_32 +67 F3 0FA6 E9, Ccs_hash_32, Ccs_hash, 0, rep enc=67F30FA6E8 +67 F3 0FA6 EA, Ccs_hash_32, Ccs_hash, 0, rep enc=67F30FA6E8 +67 F3 0FA6 EB, Ccs_hash_32, Ccs_hash, 0, rep enc=67F30FA6E8 +67 F3 0FA6 EC, Ccs_hash_32, Ccs_hash, 0, rep enc=67F30FA6E8 +67 F3 0FA6 ED, Ccs_hash_32, Ccs_hash, 0, rep enc=67F30FA6E8 +67 F3 0FA6 EE, Ccs_hash_32, Ccs_hash, 0, rep enc=67F30FA6E8 +67 F3 0FA6 EF, Ccs_hash_32, Ccs_hash, 0, rep enc=67F30FA6E8 F3 0FA7 F0, Ccs_encrypt_16, Ccs_encrypt, 0, rep F2 0FA7 F0, INVALID, INVALID, 0, code=Ccs_encrypt_16 F2 F3 0FA7 F0, Ccs_encrypt_16, Ccs_encrypt, 0, rep enc=F30FA7F0 F3 F2 0FA7 F0, INVALID, INVALID, 0, code=Ccs_encrypt_16 0FA7 F0, INVALID, INVALID, 0, code=Ccs_encrypt_16 +F3 0FA7 F1, Ccs_encrypt_16, Ccs_encrypt, 0, rep enc=F30FA7F0 +F3 0FA7 F2, Ccs_encrypt_16, Ccs_encrypt, 0, rep enc=F30FA7F0 +F3 0FA7 F3, Ccs_encrypt_16, Ccs_encrypt, 0, rep enc=F30FA7F0 +F3 0FA7 F4, Ccs_encrypt_16, Ccs_encrypt, 0, rep enc=F30FA7F0 +F3 0FA7 F5, Ccs_encrypt_16, Ccs_encrypt, 0, rep enc=F30FA7F0 +F3 0FA7 F6, Ccs_encrypt_16, Ccs_encrypt, 0, rep enc=F30FA7F0 +F3 0FA7 F7, Ccs_encrypt_16, Ccs_encrypt, 0, rep enc=F30FA7F0 F3 67 0FA7 F0, Ccs_encrypt_32, Ccs_encrypt, 0, rep enc=67F30FA7F0 67 F3 0FA7 F0, Ccs_encrypt_32, Ccs_encrypt, 0, rep 67 0FA7 F0, INVALID, INVALID, 0, code=Ccs_encrypt_32 +67 F3 0FA7 F1, Ccs_encrypt_32, Ccs_encrypt, 0, rep enc=67F30FA7F0 +67 F3 0FA7 F2, Ccs_encrypt_32, Ccs_encrypt, 0, rep enc=67F30FA7F0 +67 F3 0FA7 F3, Ccs_encrypt_32, Ccs_encrypt, 0, rep enc=67F30FA7F0 +67 F3 0FA7 F4, Ccs_encrypt_32, Ccs_encrypt, 0, rep enc=67F30FA7F0 +67 F3 0FA7 F5, Ccs_encrypt_32, Ccs_encrypt, 0, rep enc=67F30FA7F0 +67 F3 0FA7 F6, Ccs_encrypt_32, Ccs_encrypt, 0, rep enc=67F30FA7F0 +67 F3 0FA7 F7, Ccs_encrypt_32, Ccs_encrypt, 0, rep enc=67F30FA7F0 62 F54C0B 58 50 01, EVEX_Vaddph_xmm_k1z_xmm_xmmm128b16, Vaddph, 3, op0=r;xmm2 op1=r;xmm6 op2=m;ds;bx;si;1;16;1;Packed128_Float16 k3 co=0;0;0;0;6;1 62 F54C9D 58 50 01, EVEX_Vaddph_xmm_k1z_xmm_xmmm128b16, Vaddph, 3, op0=r;xmm2 op1=r;xmm6 op2=m;ds;bx;si;1;2;1;Broadcast128_Float16 bcst k5 zmsk co=0;0;0;0;6;1 diff --git a/src/UnitTests/Intel/Decoder/DecoderTest32.txt b/src/UnitTests/Intel/Decoder/DecoderTest32.txt index d76d77a52..1033c1c42 100644 --- a/src/UnitTests/Intel/Decoder/DecoderTest32.txt +++ b/src/UnitTests/Intel/Decoder/DecoderTest32.txt @@ -8751,35 +8751,158 @@ C4C1F9 99 D3, VEX_Ktestd_kr_kr, Ktestd, 2, op0=r;k2 op1=r;k3 enc=C4E1F999D3 0FA5 CE, Shld_rm32_r32_CL, Shld, 3, op0=r;esi op1=r;ecx op2=r;cl 0FA5 18, Shld_rm32_r32_CL, Shld, 3, op0=m;ds;eax;;1;0;0;UInt32 op1=r;ebx op2=r;cl -F3 67 0FA6 C0, Montmul_16, Montmul, 0, rep enc=67F30FA6C0 -67 F3 0FA6 C0, Montmul_16, Montmul, 0, rep -67 0FA6 C0, INVALID, INVALID, 0, code=Montmul_16 +F3 67 0FA6 C0, INVALID, INVALID, 0, code=Montmul_16 +67 F3 0FA6 C0, INVALID, INVALID, 0, code=Montmul_16 +F3 67 0FA6 C0, Montmul_16, Montmul, 0, rep enc=67F30FA6C0 decopt=NoInvalidCheck +67 F3 0FA6 C0, Montmul_16, Montmul, 0, rep decopt=NoInvalidCheck +67 0FA6 C0, INVALID, INVALID, 0, code=Montmul_16 decopt=NoInvalidCheck +67 F3 0FA6 C1, INVALID, INVALID, 0, code=Montmul_16 +67 F3 0FA6 C2, INVALID, INVALID, 0, code=Montmul_16 +67 F3 0FA6 C3, INVALID, INVALID, 0, code=Montmul_16 +67 F3 0FA6 C4, INVALID, INVALID, 0, code=Montmul_16 +67 F3 0FA6 C5, INVALID, INVALID, 0, code=Montmul_16 +67 F3 0FA6 C6, INVALID, INVALID, 0, code=Montmul_16 +67 F3 0FA6 C7, INVALID, INVALID, 0, code=Montmul_16 +67 F3 0FA6 C1, Montmul_16, Montmul, 0, rep decopt=NoInvalidCheck enc=67F30FA6C0 +67 F3 0FA6 C2, Montmul_16, Montmul, 0, rep decopt=NoInvalidCheck enc=67F30FA6C0 +67 F3 0FA6 C3, Montmul_16, Montmul, 0, rep decopt=NoInvalidCheck enc=67F30FA6C0 +67 F3 0FA6 C4, Montmul_16, Montmul, 0, rep decopt=NoInvalidCheck enc=67F30FA6C0 +67 F3 0FA6 C5, Montmul_16, Montmul, 0, rep decopt=NoInvalidCheck enc=67F30FA6C0 +67 F3 0FA6 C6, Montmul_16, Montmul, 0, rep decopt=NoInvalidCheck enc=67F30FA6C0 +67 F3 0FA6 C7, Montmul_16, Montmul, 0, rep decopt=NoInvalidCheck enc=67F30FA6C0 F3 0FA6 C0, Montmul_32, Montmul, 0, rep F2 0FA6 C0, INVALID, INVALID, 0, code=Montmul_32 F2 F3 0FA6 C0, Montmul_32, Montmul, 0, rep enc=F30FA6C0 F3 F2 0FA6 C0, INVALID, INVALID, 0, code=Montmul_32 0FA6 C0, INVALID, INVALID, 0, code=Montmul_32 +F3 0FA6 C1, Montmul_32, Montmul, 0, rep enc=F30FA6C0 +F3 0FA6 C2, Montmul_32, Montmul, 0, rep enc=F30FA6C0 +F3 0FA6 C3, Montmul_32, Montmul, 0, rep enc=F30FA6C0 +F3 0FA6 C4, Montmul_32, Montmul, 0, rep enc=F30FA6C0 +F3 0FA6 C5, Montmul_32, Montmul, 0, rep enc=F30FA6C0 +F3 0FA6 C6, Montmul_32, Montmul, 0, rep enc=F30FA6C0 +F3 0FA6 C7, Montmul_32, Montmul, 0, rep enc=F30FA6C0 F3 67 0FA6 C8, Xsha1_16, Xsha1, 0, rep enc=67F30FA6C8 67 F3 0FA6 C8, Xsha1_16, Xsha1, 0, rep 67 0FA6 C8, INVALID, INVALID, 0, code=Xsha1_16 +67 F3 0FA6 C9, Xsha1_16, Xsha1, 0, rep enc=67F30FA6C8 +67 F3 0FA6 CA, Xsha1_16, Xsha1, 0, rep enc=67F30FA6C8 +67 F3 0FA6 CB, Xsha1_16, Xsha1, 0, rep enc=67F30FA6C8 +67 F3 0FA6 CC, Xsha1_16, Xsha1, 0, rep enc=67F30FA6C8 +67 F3 0FA6 CD, Xsha1_16, Xsha1, 0, rep enc=67F30FA6C8 +67 F3 0FA6 CE, Xsha1_16, Xsha1, 0, rep enc=67F30FA6C8 +67 F3 0FA6 CF, Xsha1_16, Xsha1, 0, rep enc=67F30FA6C8 F3 0FA6 C8, Xsha1_32, Xsha1, 0, rep F2 0FA6 C8, INVALID, INVALID, 0, code=Xsha1_32 F2 F3 0FA6 C8, Xsha1_32, Xsha1, 0, rep enc=F30FA6C8 F3 F2 0FA6 C8, INVALID, INVALID, 0, code=Xsha1_32 0FA6 C8, INVALID, INVALID, 0, code=Xsha1_32 +F3 0FA6 C9, Xsha1_32, Xsha1, 0, rep enc=F30FA6C8 +F3 0FA6 CA, Xsha1_32, Xsha1, 0, rep enc=F30FA6C8 +F3 0FA6 CB, Xsha1_32, Xsha1, 0, rep enc=F30FA6C8 +F3 0FA6 CC, Xsha1_32, Xsha1, 0, rep enc=F30FA6C8 +F3 0FA6 CD, Xsha1_32, Xsha1, 0, rep enc=F30FA6C8 +F3 0FA6 CE, Xsha1_32, Xsha1, 0, rep enc=F30FA6C8 +F3 0FA6 CF, Xsha1_32, Xsha1, 0, rep enc=F30FA6C8 F3 67 0FA6 D0, Xsha256_16, Xsha256, 0, rep enc=67F30FA6D0 67 F3 0FA6 D0, Xsha256_16, Xsha256, 0, rep 67 0FA6 D0, INVALID, INVALID, 0, code=Xsha256_16 +67 F3 0FA6 D1, Xsha256_16, Xsha256, 0, rep enc=67F30FA6D0 +67 F3 0FA6 D2, Xsha256_16, Xsha256, 0, rep enc=67F30FA6D0 +67 F3 0FA6 D3, Xsha256_16, Xsha256, 0, rep enc=67F30FA6D0 +67 F3 0FA6 D4, Xsha256_16, Xsha256, 0, rep enc=67F30FA6D0 +67 F3 0FA6 D5, Xsha256_16, Xsha256, 0, rep enc=67F30FA6D0 +67 F3 0FA6 D6, Xsha256_16, Xsha256, 0, rep enc=67F30FA6D0 +67 F3 0FA6 D7, Xsha256_16, Xsha256, 0, rep enc=67F30FA6D0 F3 0FA6 D0, Xsha256_32, Xsha256, 0, rep F2 0FA6 D0, INVALID, INVALID, 0, code=Xsha256_32 F2 F3 0FA6 D0, Xsha256_32, Xsha256, 0, rep enc=F30FA6D0 F3 F2 0FA6 D0, INVALID, INVALID, 0, code=Xsha256_32 0FA6 D0, INVALID, INVALID, 0, code=Xsha256_32 +F3 0FA6 D1, Xsha256_32, Xsha256, 0, rep enc=F30FA6D0 +F3 0FA6 D2, Xsha256_32, Xsha256, 0, rep enc=F30FA6D0 +F3 0FA6 D3, Xsha256_32, Xsha256, 0, rep enc=F30FA6D0 +F3 0FA6 D4, Xsha256_32, Xsha256, 0, rep enc=F30FA6D0 +F3 0FA6 D5, Xsha256_32, Xsha256, 0, rep enc=F30FA6D0 +F3 0FA6 D6, Xsha256_32, Xsha256, 0, rep enc=F30FA6D0 +F3 0FA6 D7, Xsha256_32, Xsha256, 0, rep enc=F30FA6D0 + +F3 67 0FA6 E0, Xsha512_16, Xsha512, 0, rep enc=67F30FA6E0 +67 F3 0FA6 E0, Xsha512_16, Xsha512, 0, rep +67 0FA6 E0, INVALID, INVALID, 0, code=Xsha512_16 +67 F3 0FA6 E1, Xsha512_16, Xsha512, 0, rep enc=67F30FA6E0 +67 F3 0FA6 E2, Xsha512_16, Xsha512, 0, rep enc=67F30FA6E0 +67 F3 0FA6 E3, Xsha512_16, Xsha512, 0, rep enc=67F30FA6E0 +67 F3 0FA6 E4, Xsha512_16, Xsha512, 0, rep enc=67F30FA6E0 +67 F3 0FA6 E5, Xsha512_16, Xsha512, 0, rep enc=67F30FA6E0 +67 F3 0FA6 E6, Xsha512_16, Xsha512, 0, rep enc=67F30FA6E0 +67 F3 0FA6 E7, Xsha512_16, Xsha512, 0, rep enc=67F30FA6E0 + +F3 0FA6 E0, Xsha512_32, Xsha512, 0, rep +F2 0FA6 E0, INVALID, INVALID, 0, code=Xsha512_32 +F2 F3 0FA6 E0, Xsha512_32, Xsha512, 0, rep enc=F30FA6E0 +F3 F2 0FA6 E0, INVALID, INVALID, 0, code=Xsha512_32 +0FA6 E0, INVALID, INVALID, 0, code=Xsha512_32 +F3 0FA6 E1, Xsha512_32, Xsha512, 0, rep enc=F30FA6E0 +F3 0FA6 E2, Xsha512_32, Xsha512, 0, rep enc=F30FA6E0 +F3 0FA6 E3, Xsha512_32, Xsha512, 0, rep enc=F30FA6E0 +F3 0FA6 E4, Xsha512_32, Xsha512, 0, rep enc=F30FA6E0 +F3 0FA6 E5, Xsha512_32, Xsha512, 0, rep enc=F30FA6E0 +F3 0FA6 E6, Xsha512_32, Xsha512, 0, rep enc=F30FA6E0 +F3 0FA6 E7, Xsha512_32, Xsha512, 0, rep enc=F30FA6E0 + +F3 67 0FA6 F0, Via_undoc_F30FA6F0_16, Undoc, 0, rep enc=67F30FA6F0 +67 F3 0FA6 F0, Via_undoc_F30FA6F0_16, Undoc, 0, rep +67 0FA6 F0, INVALID, INVALID, 0, code=Via_undoc_F30FA6F0_16 +67 F3 0FA6 F1, Via_undoc_F30FA6F0_16, Undoc, 0, rep enc=67F30FA6F0 +67 F3 0FA6 F2, Via_undoc_F30FA6F0_16, Undoc, 0, rep enc=67F30FA6F0 +67 F3 0FA6 F3, Via_undoc_F30FA6F0_16, Undoc, 0, rep enc=67F30FA6F0 +67 F3 0FA6 F4, Via_undoc_F30FA6F0_16, Undoc, 0, rep enc=67F30FA6F0 +67 F3 0FA6 F5, Via_undoc_F30FA6F0_16, Undoc, 0, rep enc=67F30FA6F0 +67 F3 0FA6 F6, Via_undoc_F30FA6F0_16, Undoc, 0, rep enc=67F30FA6F0 +67 F3 0FA6 F7, Via_undoc_F30FA6F0_16, Undoc, 0, rep enc=67F30FA6F0 + +F3 0FA6 F0, Via_undoc_F30FA6F0_32, Undoc, 0, rep +F2 0FA6 F0, INVALID, INVALID, 0, code=Via_undoc_F30FA6F0_32 +F2 F3 0FA6 F0, Via_undoc_F30FA6F0_32, Undoc, 0, rep enc=F30FA6F0 +F3 F2 0FA6 F0, INVALID, INVALID, 0, code=Via_undoc_F30FA6F0_32 +0FA6 F0, INVALID, INVALID, 0, code=Via_undoc_F30FA6F0_32 +F3 0FA6 F1, Via_undoc_F30FA6F0_32, Undoc, 0, rep enc=F30FA6F0 +F3 0FA6 F2, Via_undoc_F30FA6F0_32, Undoc, 0, rep enc=F30FA6F0 +F3 0FA6 F3, Via_undoc_F30FA6F0_32, Undoc, 0, rep enc=F30FA6F0 +F3 0FA6 F4, Via_undoc_F30FA6F0_32, Undoc, 0, rep enc=F30FA6F0 +F3 0FA6 F5, Via_undoc_F30FA6F0_32, Undoc, 0, rep enc=F30FA6F0 +F3 0FA6 F6, Via_undoc_F30FA6F0_32, Undoc, 0, rep enc=F30FA6F0 +F3 0FA6 F7, Via_undoc_F30FA6F0_32, Undoc, 0, rep enc=F30FA6F0 + +F3 67 0FA6 F8, Via_undoc_F30FA6F8_16, Undoc, 0, rep enc=67F30FA6F8 +67 F3 0FA6 F8, Via_undoc_F30FA6F8_16, Undoc, 0, rep +67 0FA6 F8, INVALID, INVALID, 0, code=Via_undoc_F30FA6F8_16 +67 F3 0FA6 F9, Via_undoc_F30FA6F8_16, Undoc, 0, rep enc=67F30FA6F8 +67 F3 0FA6 FA, Via_undoc_F30FA6F8_16, Undoc, 0, rep enc=67F30FA6F8 +67 F3 0FA6 FB, Via_undoc_F30FA6F8_16, Undoc, 0, rep enc=67F30FA6F8 +67 F3 0FA6 FC, Via_undoc_F30FA6F8_16, Undoc, 0, rep enc=67F30FA6F8 +67 F3 0FA6 FD, Via_undoc_F30FA6F8_16, Undoc, 0, rep enc=67F30FA6F8 +67 F3 0FA6 FE, Via_undoc_F30FA6F8_16, Undoc, 0, rep enc=67F30FA6F8 +67 F3 0FA6 FF, Via_undoc_F30FA6F8_16, Undoc, 0, rep enc=67F30FA6F8 + +F3 0FA6 F8, Via_undoc_F30FA6F8_32, Undoc, 0, rep +F2 0FA6 F8, INVALID, INVALID, 0, code=Via_undoc_F30FA6F8_32 +F2 F3 0FA6 F8, Via_undoc_F30FA6F8_32, Undoc, 0, rep enc=F30FA6F8 +F3 F2 0FA6 F8, INVALID, INVALID, 0, code=Via_undoc_F30FA6F8_32 +0FA6 F8, INVALID, INVALID, 0, code=Via_undoc_F30FA6F8_32 +F3 0FA6 F9, Via_undoc_F30FA6F8_32, Undoc, 0, rep enc=F30FA6F8 +F3 0FA6 FA, Via_undoc_F30FA6F8_32, Undoc, 0, rep enc=F30FA6F8 +F3 0FA6 FB, Via_undoc_F30FA6F8_32, Undoc, 0, rep enc=F30FA6F8 +F3 0FA6 FC, Via_undoc_F30FA6F8_32, Undoc, 0, rep enc=F30FA6F8 +F3 0FA6 FD, Via_undoc_F30FA6F8_32, Undoc, 0, rep enc=F30FA6F8 +F3 0FA6 FE, Via_undoc_F30FA6F8_32, Undoc, 0, rep enc=F30FA6F8 +F3 0FA6 FF, Via_undoc_F30FA6F8_32, Undoc, 0, rep enc=F30FA6F8 66 0FA6 CE, Xbts_r16_rm16, Xbts, 2, op0=r;cx op1=r;si decopt=Xbts 66 0FA6 CE, Xbts_r16_rm16, Xbts, 2, op0=r;cx op1=r;si decopt=Xbts decopt=Cmpxchg486A @@ -8803,62 +8926,200 @@ F3 F2 0FA6 D0, INVALID, INVALID, 0, code=Xsha256_32 F3 67 0FA7 C0, Xstore_16, Xstore, 0, rep enc=67F30FA7C0 67 F3 0FA7 C0, Xstore_16, Xstore, 0, rep 67 0FA7 C0, Xstore_16, Xstore, 0, +67 F3 0FA7 C1, Xstore_16, Xstore, 0, rep enc=67F30FA7C0 +67 F3 0FA7 C2, Xstore_16, Xstore, 0, rep enc=67F30FA7C0 +67 F3 0FA7 C3, Xstore_16, Xstore, 0, rep enc=67F30FA7C0 +67 F3 0FA7 C4, Xstore_16, Xstore, 0, rep enc=67F30FA7C0 +67 F3 0FA7 C5, Xstore_16, Xstore, 0, rep enc=67F30FA7C0 +67 F3 0FA7 C6, Xstore_16, Xstore, 0, rep enc=67F30FA7C0 +67 F3 0FA7 C7, Xstore_16, Xstore, 0, rep enc=67F30FA7C0 +67 F2 0FA7 C0, Xstore_16, Xstore, 0, repne enc=67F20FA7C0 +67 F2 0FA7 C1, Xstore_16, Xstore, 0, repne enc=67F20FA7C0 +67 F2 0FA7 C2, Xstore_16, Xstore, 0, repne enc=67F20FA7C0 +67 F2 0FA7 C3, Xstore_16, Xstore, 0, repne enc=67F20FA7C0 +67 F2 0FA7 C4, Xstore_16, Xstore, 0, repne enc=67F20FA7C0 +67 F2 0FA7 C5, Xstore_16, Xstore, 0, repne enc=67F20FA7C0 +67 F2 0FA7 C6, Xstore_16, Xstore, 0, repne enc=67F20FA7C0 +67 F2 0FA7 C7, Xstore_16, Xstore, 0, repne enc=67F20FA7C0 F3 0FA7 C0, Xstore_32, Xstore, 0, rep F2 0FA7 C0, Xstore_32, Xstore, 0, repne F2 F3 0FA7 C0, Xstore_32, Xstore, 0, rep enc=F30FA7C0 F3 F2 0FA7 C0, Xstore_32, Xstore, 0, repne enc=F20FA7C0 0FA7 C0, Xstore_32, Xstore, 0, +F3 0FA7 C1, Xstore_32, Xstore, 0, rep enc=F30FA7C0 +F3 0FA7 C2, Xstore_32, Xstore, 0, rep enc=F30FA7C0 +F3 0FA7 C3, Xstore_32, Xstore, 0, rep enc=F30FA7C0 +F3 0FA7 C4, Xstore_32, Xstore, 0, rep enc=F30FA7C0 +F3 0FA7 C5, Xstore_32, Xstore, 0, rep enc=F30FA7C0 +F3 0FA7 C6, Xstore_32, Xstore, 0, rep enc=F30FA7C0 +F3 0FA7 C7, Xstore_32, Xstore, 0, rep enc=F30FA7C0 +F2 0FA7 C1, Xstore_32, Xstore, 0, repne enc=F20FA7C0 +F2 0FA7 C2, Xstore_32, Xstore, 0, repne enc=F20FA7C0 +F2 0FA7 C3, Xstore_32, Xstore, 0, repne enc=F20FA7C0 +F2 0FA7 C4, Xstore_32, Xstore, 0, repne enc=F20FA7C0 +F2 0FA7 C5, Xstore_32, Xstore, 0, repne enc=F20FA7C0 +F2 0FA7 C6, Xstore_32, Xstore, 0, repne enc=F20FA7C0 +F2 0FA7 C7, Xstore_32, Xstore, 0, repne enc=F20FA7C0 + +F3 67 0FA7 F8, Xstore2_16, Xstore2, 0, rep enc=67F30FA7F8 +67 F3 0FA7 F8, Xstore2_16, Xstore2, 0, rep +67 0FA7 F8, INVALID, INVALID, 0, code=Xstore2_16 +67 F3 0FA7 F9, Xstore2_16, Xstore2, 0, rep enc=67F30FA7F8 +67 F3 0FA7 FA, Xstore2_16, Xstore2, 0, rep enc=67F30FA7F8 +67 F3 0FA7 FB, Xstore2_16, Xstore2, 0, rep enc=67F30FA7F8 +67 F3 0FA7 FC, Xstore2_16, Xstore2, 0, rep enc=67F30FA7F8 +67 F3 0FA7 FD, Xstore2_16, Xstore2, 0, rep enc=67F30FA7F8 +67 F3 0FA7 FE, Xstore2_16, Xstore2, 0, rep enc=67F30FA7F8 +67 F3 0FA7 FF, Xstore2_16, Xstore2, 0, rep enc=67F30FA7F8 +67 F2 0FA7 F8, INVALID, INVALID, 0, code=Xstore2_16 +67 F2 0FA7 F9, INVALID, INVALID, 0, code=Xstore2_16 +67 F2 0FA7 FA, INVALID, INVALID, 0, code=Xstore2_16 +67 F2 0FA7 FB, INVALID, INVALID, 0, code=Xstore2_16 +67 F2 0FA7 FC, INVALID, INVALID, 0, code=Xstore2_16 +67 F2 0FA7 FD, INVALID, INVALID, 0, code=Xstore2_16 +67 F2 0FA7 FE, INVALID, INVALID, 0, code=Xstore2_16 +67 F2 0FA7 FF, INVALID, INVALID, 0, code=Xstore2_16 + +F3 0FA7 F8, Xstore2_32, Xstore2, 0, rep +F2 0FA7 F8, INVALID, INVALID, 0, code=Xstore2_32 +F2 F3 0FA7 F8, Xstore2_32, Xstore2, 0, rep enc=F30FA7F8 +F3 F2 0FA7 F8, INVALID, INVALID, 0, code=Xstore2_32 +0FA7 F8, INVALID, INVALID, 0, code=Xstore2_32 +F3 0FA7 F9, Xstore2_32, Xstore2, 0, rep enc=F30FA7F8 +F3 0FA7 FA, Xstore2_32, Xstore2, 0, rep enc=F30FA7F8 +F3 0FA7 FB, Xstore2_32, Xstore2, 0, rep enc=F30FA7F8 +F3 0FA7 FC, Xstore2_32, Xstore2, 0, rep enc=F30FA7F8 +F3 0FA7 FD, Xstore2_32, Xstore2, 0, rep enc=F30FA7F8 +F3 0FA7 FE, Xstore2_32, Xstore2, 0, rep enc=F30FA7F8 +F3 0FA7 FF, Xstore2_32, Xstore2, 0, rep enc=F30FA7F8 +F2 0FA7 F9, INVALID, INVALID, 0, code=Xstore2_32 +F2 0FA7 FA, INVALID, INVALID, 0, code=Xstore2_32 +F2 0FA7 FB, INVALID, INVALID, 0, code=Xstore2_32 +F2 0FA7 FC, INVALID, INVALID, 0, code=Xstore2_32 +F2 0FA7 FD, INVALID, INVALID, 0, code=Xstore2_32 +F2 0FA7 FE, INVALID, INVALID, 0, code=Xstore2_32 +F2 0FA7 FF, INVALID, INVALID, 0, code=Xstore2_32 F3 67 0FA7 C8, Xcryptecb_16, Xcryptecb, 0, rep enc=67F30FA7C8 67 F3 0FA7 C8, Xcryptecb_16, Xcryptecb, 0, rep 67 0FA7 C8, INVALID, INVALID, 0, code=Xcryptecb_16 +67 F3 0FA7 C9, Xcryptecb_16, Xcryptecb, 0, rep enc=67F30FA7C8 +67 F3 0FA7 CA, Xcryptecb_16, Xcryptecb, 0, rep enc=67F30FA7C8 +67 F3 0FA7 CB, Xcryptecb_16, Xcryptecb, 0, rep enc=67F30FA7C8 +67 F3 0FA7 CC, Xcryptecb_16, Xcryptecb, 0, rep enc=67F30FA7C8 +67 F3 0FA7 CD, Xcryptecb_16, Xcryptecb, 0, rep enc=67F30FA7C8 +67 F3 0FA7 CE, Xcryptecb_16, Xcryptecb, 0, rep enc=67F30FA7C8 +67 F3 0FA7 CF, Xcryptecb_16, Xcryptecb, 0, rep enc=67F30FA7C8 F3 0FA7 C8, Xcryptecb_32, Xcryptecb, 0, rep F2 0FA7 C8, INVALID, INVALID, 0, code=Xcryptecb_32 F2 F3 0FA7 C8, Xcryptecb_32, Xcryptecb, 0, rep enc=F30FA7C8 F3 F2 0FA7 C8, INVALID, INVALID, 0, code=Xcryptecb_32 0FA7 C8, INVALID, INVALID, 0, code=Xcryptecb_32 +F3 0FA7 C9, Xcryptecb_32, Xcryptecb, 0, rep enc=F30FA7C8 +F3 0FA7 CA, Xcryptecb_32, Xcryptecb, 0, rep enc=F30FA7C8 +F3 0FA7 CB, Xcryptecb_32, Xcryptecb, 0, rep enc=F30FA7C8 +F3 0FA7 CC, Xcryptecb_32, Xcryptecb, 0, rep enc=F30FA7C8 +F3 0FA7 CD, Xcryptecb_32, Xcryptecb, 0, rep enc=F30FA7C8 +F3 0FA7 CE, Xcryptecb_32, Xcryptecb, 0, rep enc=F30FA7C8 +F3 0FA7 CF, Xcryptecb_32, Xcryptecb, 0, rep enc=F30FA7C8 F3 67 0FA7 D0, Xcryptcbc_16, Xcryptcbc, 0, rep enc=67F30FA7D0 67 F3 0FA7 D0, Xcryptcbc_16, Xcryptcbc, 0, rep 67 0FA7 D0, INVALID, INVALID, 0, code=Xcryptcbc_16 +67 F3 0FA7 D1, Xcryptcbc_16, Xcryptcbc, 0, rep enc=67F30FA7D0 +67 F3 0FA7 D2, Xcryptcbc_16, Xcryptcbc, 0, rep enc=67F30FA7D0 +67 F3 0FA7 D3, Xcryptcbc_16, Xcryptcbc, 0, rep enc=67F30FA7D0 +67 F3 0FA7 D4, Xcryptcbc_16, Xcryptcbc, 0, rep enc=67F30FA7D0 +67 F3 0FA7 D5, Xcryptcbc_16, Xcryptcbc, 0, rep enc=67F30FA7D0 +67 F3 0FA7 D6, Xcryptcbc_16, Xcryptcbc, 0, rep enc=67F30FA7D0 +67 F3 0FA7 D7, Xcryptcbc_16, Xcryptcbc, 0, rep enc=67F30FA7D0 F3 0FA7 D0, Xcryptcbc_32, Xcryptcbc, 0, rep F2 0FA7 D0, INVALID, INVALID, 0, code=Xcryptcbc_32 F2 F3 0FA7 D0, Xcryptcbc_32, Xcryptcbc, 0, rep enc=F30FA7D0 F3 F2 0FA7 D0, INVALID, INVALID, 0, code=Xcryptcbc_32 0FA7 D0, INVALID, INVALID, 0, code=Xcryptcbc_32 +F3 0FA7 D1, Xcryptcbc_32, Xcryptcbc, 0, rep enc=F30FA7D0 +F3 0FA7 D2, Xcryptcbc_32, Xcryptcbc, 0, rep enc=F30FA7D0 +F3 0FA7 D3, Xcryptcbc_32, Xcryptcbc, 0, rep enc=F30FA7D0 +F3 0FA7 D4, Xcryptcbc_32, Xcryptcbc, 0, rep enc=F30FA7D0 +F3 0FA7 D5, Xcryptcbc_32, Xcryptcbc, 0, rep enc=F30FA7D0 +F3 0FA7 D6, Xcryptcbc_32, Xcryptcbc, 0, rep enc=F30FA7D0 +F3 0FA7 D7, Xcryptcbc_32, Xcryptcbc, 0, rep enc=F30FA7D0 F3 67 0FA7 D8, Xcryptctr_16, Xcryptctr, 0, rep enc=67F30FA7D8 67 F3 0FA7 D8, Xcryptctr_16, Xcryptctr, 0, rep 67 0FA7 D8, INVALID, INVALID, 0, code=Xcryptctr_16 +67 F3 0FA7 D9, Xcryptctr_16, Xcryptctr, 0, rep enc=67F30FA7D8 +67 F3 0FA7 DA, Xcryptctr_16, Xcryptctr, 0, rep enc=67F30FA7D8 +67 F3 0FA7 DB, Xcryptctr_16, Xcryptctr, 0, rep enc=67F30FA7D8 +67 F3 0FA7 DC, Xcryptctr_16, Xcryptctr, 0, rep enc=67F30FA7D8 +67 F3 0FA7 DD, Xcryptctr_16, Xcryptctr, 0, rep enc=67F30FA7D8 +67 F3 0FA7 DE, Xcryptctr_16, Xcryptctr, 0, rep enc=67F30FA7D8 +67 F3 0FA7 DF, Xcryptctr_16, Xcryptctr, 0, rep enc=67F30FA7D8 F3 0FA7 D8, Xcryptctr_32, Xcryptctr, 0, rep F2 0FA7 D8, INVALID, INVALID, 0, code=Xcryptctr_32 F2 F3 0FA7 D8, Xcryptctr_32, Xcryptctr, 0, rep enc=F30FA7D8 F3 F2 0FA7 D8, INVALID, INVALID, 0, code=Xcryptctr_32 0FA7 D8, INVALID, INVALID, 0, code=Xcryptctr_32 +F3 0FA7 D9, Xcryptctr_32, Xcryptctr, 0, rep enc=F30FA7D8 +F3 0FA7 DA, Xcryptctr_32, Xcryptctr, 0, rep enc=F30FA7D8 +F3 0FA7 DB, Xcryptctr_32, Xcryptctr, 0, rep enc=F30FA7D8 +F3 0FA7 DC, Xcryptctr_32, Xcryptctr, 0, rep enc=F30FA7D8 +F3 0FA7 DD, Xcryptctr_32, Xcryptctr, 0, rep enc=F30FA7D8 +F3 0FA7 DE, Xcryptctr_32, Xcryptctr, 0, rep enc=F30FA7D8 +F3 0FA7 DF, Xcryptctr_32, Xcryptctr, 0, rep enc=F30FA7D8 F3 67 0FA7 E0, Xcryptcfb_16, Xcryptcfb, 0, rep enc=67F30FA7E0 67 F3 0FA7 E0, Xcryptcfb_16, Xcryptcfb, 0, rep 67 0FA7 E0, INVALID, INVALID, 0, code=Xcryptcfb_16 +67 F3 0FA7 E1, Xcryptcfb_16, Xcryptcfb, 0, rep enc=67F30FA7E0 +67 F3 0FA7 E2, Xcryptcfb_16, Xcryptcfb, 0, rep enc=67F30FA7E0 +67 F3 0FA7 E3, Xcryptcfb_16, Xcryptcfb, 0, rep enc=67F30FA7E0 +67 F3 0FA7 E4, Xcryptcfb_16, Xcryptcfb, 0, rep enc=67F30FA7E0 +67 F3 0FA7 E5, Xcryptcfb_16, Xcryptcfb, 0, rep enc=67F30FA7E0 +67 F3 0FA7 E6, Xcryptcfb_16, Xcryptcfb, 0, rep enc=67F30FA7E0 +67 F3 0FA7 E7, Xcryptcfb_16, Xcryptcfb, 0, rep enc=67F30FA7E0 F3 0FA7 E0, Xcryptcfb_32, Xcryptcfb, 0, rep F2 0FA7 E0, INVALID, INVALID, 0, code=Xcryptcfb_32 F2 F3 0FA7 E0, Xcryptcfb_32, Xcryptcfb, 0, rep enc=F30FA7E0 F3 F2 0FA7 E0, INVALID, INVALID, 0, code=Xcryptcfb_32 0FA7 E0, INVALID, INVALID, 0, code=Xcryptcfb_32 +F3 0FA7 E1, Xcryptcfb_32, Xcryptcfb, 0, rep enc=F30FA7E0 +F3 0FA7 E2, Xcryptcfb_32, Xcryptcfb, 0, rep enc=F30FA7E0 +F3 0FA7 E3, Xcryptcfb_32, Xcryptcfb, 0, rep enc=F30FA7E0 +F3 0FA7 E4, Xcryptcfb_32, Xcryptcfb, 0, rep enc=F30FA7E0 +F3 0FA7 E5, Xcryptcfb_32, Xcryptcfb, 0, rep enc=F30FA7E0 +F3 0FA7 E6, Xcryptcfb_32, Xcryptcfb, 0, rep enc=F30FA7E0 +F3 0FA7 E7, Xcryptcfb_32, Xcryptcfb, 0, rep enc=F30FA7E0 F3 67 0FA7 E8, Xcryptofb_16, Xcryptofb, 0, rep enc=67F30FA7E8 67 F3 0FA7 E8, Xcryptofb_16, Xcryptofb, 0, rep 67 0FA7 E8, INVALID, INVALID, 0, code=Xcryptofb_16 +67 F3 0FA7 E9, Xcryptofb_16, Xcryptofb, 0, rep enc=67F30FA7E8 +67 F3 0FA7 EA, Xcryptofb_16, Xcryptofb, 0, rep enc=67F30FA7E8 +67 F3 0FA7 EB, Xcryptofb_16, Xcryptofb, 0, rep enc=67F30FA7E8 +67 F3 0FA7 EC, Xcryptofb_16, Xcryptofb, 0, rep enc=67F30FA7E8 +67 F3 0FA7 ED, Xcryptofb_16, Xcryptofb, 0, rep enc=67F30FA7E8 +67 F3 0FA7 EE, Xcryptofb_16, Xcryptofb, 0, rep enc=67F30FA7E8 +67 F3 0FA7 EF, Xcryptofb_16, Xcryptofb, 0, rep enc=67F30FA7E8 F3 0FA7 E8, Xcryptofb_32, Xcryptofb, 0, rep F2 0FA7 E8, INVALID, INVALID, 0, code=Xcryptofb_32 F2 F3 0FA7 E8, Xcryptofb_32, Xcryptofb, 0, rep enc=F30FA7E8 F3 F2 0FA7 E8, INVALID, INVALID, 0, code=Xcryptofb_32 0FA7 E8, INVALID, INVALID, 0, code=Xcryptofb_32 +F3 0FA7 E9, Xcryptofb_32, Xcryptofb, 0, rep enc=F30FA7E8 +F3 0FA7 EA, Xcryptofb_32, Xcryptofb, 0, rep enc=F30FA7E8 +F3 0FA7 EB, Xcryptofb_32, Xcryptofb, 0, rep enc=F30FA7E8 +F3 0FA7 EC, Xcryptofb_32, Xcryptofb, 0, rep enc=F30FA7E8 +F3 0FA7 ED, Xcryptofb_32, Xcryptofb, 0, rep enc=F30FA7E8 +F3 0FA7 EE, Xcryptofb_32, Xcryptofb, 0, rep enc=F30FA7E8 +F3 0FA7 EF, Xcryptofb_32, Xcryptofb, 0, rep enc=F30FA7E8 66 0FA7 CE, Cmpxchg486_rm16_r16, Cmpxchg, 2, op0=r;si op1=r;cx decopt=Cmpxchg486A 66 0FA7 18, Cmpxchg486_rm16_r16, Cmpxchg, 2, op0=m;ds;eax;;1;0;0;UInt16 op1=r;bx decopt=Cmpxchg486A @@ -21749,22 +22010,50 @@ C4C24D 53 10, VEX_Vpdpwssds_ymm_ymm_ymmm256, Vpdpwssds, 3, op0=r;ymm2 op1=r;ymm6 F3 67 0FA6 E8, Ccs_hash_16, Ccs_hash, 0, rep enc=67F30FA6E8 67 F3 0FA6 E8, Ccs_hash_16, Ccs_hash, 0, rep 67 0FA6 E8, INVALID, INVALID, 0, code=Ccs_hash_16 +67 F3 0FA6 E9, Ccs_hash_16, Ccs_hash, 0, rep enc=67F30FA6E8 +67 F3 0FA6 EA, Ccs_hash_16, Ccs_hash, 0, rep enc=67F30FA6E8 +67 F3 0FA6 EB, Ccs_hash_16, Ccs_hash, 0, rep enc=67F30FA6E8 +67 F3 0FA6 EC, Ccs_hash_16, Ccs_hash, 0, rep enc=67F30FA6E8 +67 F3 0FA6 ED, Ccs_hash_16, Ccs_hash, 0, rep enc=67F30FA6E8 +67 F3 0FA6 EE, Ccs_hash_16, Ccs_hash, 0, rep enc=67F30FA6E8 +67 F3 0FA6 EF, Ccs_hash_16, Ccs_hash, 0, rep enc=67F30FA6E8 F3 0FA6 E8, Ccs_hash_32, Ccs_hash, 0, rep F2 0FA6 E8, INVALID, INVALID, 0, code=Ccs_hash_32 F2 F3 0FA6 E8, Ccs_hash_32, Ccs_hash, 0, rep enc=F30FA6E8 F3 F2 0FA6 E8, INVALID, INVALID, 0, code=Ccs_hash_32 0FA6 E8, INVALID, INVALID, 0, code=Ccs_hash_32 +F3 0FA6 E9, Ccs_hash_32, Ccs_hash, 0, rep enc=F30FA6E8 +F3 0FA6 EA, Ccs_hash_32, Ccs_hash, 0, rep enc=F30FA6E8 +F3 0FA6 EB, Ccs_hash_32, Ccs_hash, 0, rep enc=F30FA6E8 +F3 0FA6 EC, Ccs_hash_32, Ccs_hash, 0, rep enc=F30FA6E8 +F3 0FA6 ED, Ccs_hash_32, Ccs_hash, 0, rep enc=F30FA6E8 +F3 0FA6 EE, Ccs_hash_32, Ccs_hash, 0, rep enc=F30FA6E8 +F3 0FA6 EF, Ccs_hash_32, Ccs_hash, 0, rep enc=F30FA6E8 F3 67 0FA7 F0, Ccs_encrypt_16, Ccs_encrypt, 0, rep enc=67F30FA7F0 67 F3 0FA7 F0, Ccs_encrypt_16, Ccs_encrypt, 0, rep 67 0FA7 F0, INVALID, INVALID, 0, code=Ccs_encrypt_16 +67 F3 0FA7 F1, Ccs_encrypt_16, Ccs_encrypt, 0, rep enc=67F30FA7F0 +67 F3 0FA7 F2, Ccs_encrypt_16, Ccs_encrypt, 0, rep enc=67F30FA7F0 +67 F3 0FA7 F3, Ccs_encrypt_16, Ccs_encrypt, 0, rep enc=67F30FA7F0 +67 F3 0FA7 F4, Ccs_encrypt_16, Ccs_encrypt, 0, rep enc=67F30FA7F0 +67 F3 0FA7 F5, Ccs_encrypt_16, Ccs_encrypt, 0, rep enc=67F30FA7F0 +67 F3 0FA7 F6, Ccs_encrypt_16, Ccs_encrypt, 0, rep enc=67F30FA7F0 +67 F3 0FA7 F7, Ccs_encrypt_16, Ccs_encrypt, 0, rep enc=67F30FA7F0 F3 0FA7 F0, Ccs_encrypt_32, Ccs_encrypt, 0, rep F2 0FA7 F0, INVALID, INVALID, 0, code=Ccs_encrypt_32 F2 F3 0FA7 F0, Ccs_encrypt_32, Ccs_encrypt, 0, rep enc=F30FA7F0 F3 F2 0FA7 F0, INVALID, INVALID, 0, code=Ccs_encrypt_32 0FA7 F0, INVALID, INVALID, 0, code=Ccs_encrypt_32 +F3 0FA7 F1, Ccs_encrypt_32, Ccs_encrypt, 0, rep enc=F30FA7F0 +F3 0FA7 F2, Ccs_encrypt_32, Ccs_encrypt, 0, rep enc=F30FA7F0 +F3 0FA7 F3, Ccs_encrypt_32, Ccs_encrypt, 0, rep enc=F30FA7F0 +F3 0FA7 F4, Ccs_encrypt_32, Ccs_encrypt, 0, rep enc=F30FA7F0 +F3 0FA7 F5, Ccs_encrypt_32, Ccs_encrypt, 0, rep enc=F30FA7F0 +F3 0FA7 F6, Ccs_encrypt_32, Ccs_encrypt, 0, rep enc=F30FA7F0 +F3 0FA7 F7, Ccs_encrypt_32, Ccs_encrypt, 0, rep enc=F30FA7F0 62 F54C0B 58 50 01, EVEX_Vaddph_xmm_k1z_xmm_xmmm128b16, Vaddph, 3, op0=r;xmm2 op1=r;xmm6 op2=m;ds;eax;;1;16;1;Packed128_Float16 k3 co=0;0;0;0;6;1 62 F54C9D 58 50 01, EVEX_Vaddph_xmm_k1z_xmm_xmmm128b16, Vaddph, 3, op0=r;xmm2 op1=r;xmm6 op2=m;ds;eax;;1;2;1;Broadcast128_Float16 bcst k5 zmsk co=0;0;0;0;6;1 diff --git a/src/UnitTests/Intel/Decoder/DecoderTest64.txt b/src/UnitTests/Intel/Decoder/DecoderTest64.txt index 918b363da..d77748096 100644 --- a/src/UnitTests/Intel/Decoder/DecoderTest64.txt +++ b/src/UnitTests/Intel/Decoder/DecoderTest64.txt @@ -14445,15 +14445,38 @@ F3 67 0FA6 C0, Montmul_32, Montmul, 0, rep enc=67F30FA6C0 67 0FA6 C0, INVALID, INVALID, 0, code=Montmul_32 decopt=Xbts no_opt_disable_test 67 0FA6 C0, INVALID, INVALID, 0, code=Montmul_32 decopt=Cmpxchg486A no_opt_disable_test 67 F3 4F 0FA6 C0, Montmul_32, Montmul, 0, rep enc=67F30FA6C0 - -F3 0FA6 C0, Montmul_64, Montmul, 0, rep +67 F3 0FA6 C1, Montmul_32, Montmul, 0, rep enc=67F30FA6C0 +67 F3 0FA6 C2, Montmul_32, Montmul, 0, rep enc=67F30FA6C0 +67 F3 0FA6 C3, Montmul_32, Montmul, 0, rep enc=67F30FA6C0 +67 F3 0FA6 C4, Montmul_32, Montmul, 0, rep enc=67F30FA6C0 +67 F3 0FA6 C5, Montmul_32, Montmul, 0, rep enc=67F30FA6C0 +67 F3 0FA6 C6, Montmul_32, Montmul, 0, rep enc=67F30FA6C0 +67 F3 0FA6 C7, Montmul_32, Montmul, 0, rep enc=67F30FA6C0 + +F3 0FA6 C0, INVALID, INVALID, 0, code=Montmul_64 F2 0FA6 C0, INVALID, INVALID, 0, code=Montmul_64 -F2 F3 0FA6 C0, Montmul_64, Montmul, 0, rep enc=F30FA6C0 -F3 F2 0FA6 C0, INVALID, INVALID, 0, code=Montmul_64 -0FA6 C0, INVALID, INVALID, 0, code=Montmul_64 -0FA6 C0, INVALID, INVALID, 0, code=Montmul_64 decopt=Xbts no_opt_disable_test -0FA6 C0, INVALID, INVALID, 0, code=Montmul_64 decopt=Cmpxchg486A no_opt_disable_test -F3 4F 0FA6 C0, Montmul_64, Montmul, 0, rep enc=F30FA6C0 +F3 0FA6 C0, Montmul_64, Montmul, 0, rep decopt=NoInvalidCheck +F2 0FA6 C0, INVALID, INVALID, 0, code=Montmul_64 decopt=NoInvalidCheck +F2 F3 0FA6 C0, Montmul_64, Montmul, 0, rep enc=F30FA6C0 decopt=NoInvalidCheck +F3 F2 0FA6 C0, INVALID, INVALID, 0, code=Montmul_64 decopt=NoInvalidCheck +0FA6 C0, INVALID, INVALID, 0, code=Montmul_64 decopt=NoInvalidCheck +0FA6 C0, INVALID, INVALID, 0, code=Montmul_64 decopt=Xbts no_opt_disable_test decopt=NoInvalidCheck +0FA6 C0, INVALID, INVALID, 0, code=Montmul_64 decopt=Cmpxchg486A no_opt_disable_test decopt=NoInvalidCheck +F3 4F 0FA6 C0, Montmul_64, Montmul, 0, rep enc=F30FA6C0 decopt=NoInvalidCheck +F3 0FA6 C1, INVALID, INVALID, 0, code=Montmul_64 +F3 0FA6 C2, INVALID, INVALID, 0, code=Montmul_64 +F3 0FA6 C3, INVALID, INVALID, 0, code=Montmul_64 +F3 0FA6 C4, INVALID, INVALID, 0, code=Montmul_64 +F3 0FA6 C5, INVALID, INVALID, 0, code=Montmul_64 +F3 0FA6 C6, INVALID, INVALID, 0, code=Montmul_64 +F3 0FA6 C7, INVALID, INVALID, 0, code=Montmul_64 +F3 0FA6 C1, Montmul_64, Montmul, 0, rep decopt=NoInvalidCheck enc=F30FA6C0 +F3 0FA6 C2, Montmul_64, Montmul, 0, rep decopt=NoInvalidCheck enc=F30FA6C0 +F3 0FA6 C3, Montmul_64, Montmul, 0, rep decopt=NoInvalidCheck enc=F30FA6C0 +F3 0FA6 C4, Montmul_64, Montmul, 0, rep decopt=NoInvalidCheck enc=F30FA6C0 +F3 0FA6 C5, Montmul_64, Montmul, 0, rep decopt=NoInvalidCheck enc=F30FA6C0 +F3 0FA6 C6, Montmul_64, Montmul, 0, rep decopt=NoInvalidCheck enc=F30FA6C0 +F3 0FA6 C7, Montmul_64, Montmul, 0, rep decopt=NoInvalidCheck enc=F30FA6C0 F3 67 0FA6 C8, Xsha1_32, Xsha1, 0, rep enc=67F30FA6C8 67 F3 0FA6 C8, Xsha1_32, Xsha1, 0, rep @@ -14461,6 +14484,13 @@ F3 67 0FA6 C8, Xsha1_32, Xsha1, 0, rep enc=67F30FA6C8 67 0FA6 C8, INVALID, INVALID, 0, code=Xsha1_32 decopt=Xbts no_opt_disable_test 67 0FA6 C8, INVALID, INVALID, 0, code=Xsha1_32 decopt=Cmpxchg486A no_opt_disable_test 67 F3 4F 0FA6 C8, Xsha1_32, Xsha1, 0, rep enc=67F30FA6C8 +67 F3 0FA6 C9, Xsha1_32, Xsha1, 0, rep enc=67F30FA6C8 +67 F3 0FA6 CA, Xsha1_32, Xsha1, 0, rep enc=67F30FA6C8 +67 F3 0FA6 CB, Xsha1_32, Xsha1, 0, rep enc=67F30FA6C8 +67 F3 0FA6 CC, Xsha1_32, Xsha1, 0, rep enc=67F30FA6C8 +67 F3 0FA6 CD, Xsha1_32, Xsha1, 0, rep enc=67F30FA6C8 +67 F3 0FA6 CE, Xsha1_32, Xsha1, 0, rep enc=67F30FA6C8 +67 F3 0FA6 CF, Xsha1_32, Xsha1, 0, rep enc=67F30FA6C8 F3 0FA6 C8, Xsha1_64, Xsha1, 0, rep F2 0FA6 C8, INVALID, INVALID, 0, code=Xsha1_64 @@ -14470,6 +14500,13 @@ F3 F2 0FA6 C8, INVALID, INVALID, 0, code=Xsha1_64 0FA6 C8, INVALID, INVALID, 0, code=Xsha1_64 decopt=Xbts no_opt_disable_test 0FA6 C8, INVALID, INVALID, 0, code=Xsha1_64 decopt=Cmpxchg486A no_opt_disable_test F3 4F 0FA6 C8, Xsha1_64, Xsha1, 0, rep enc=F30FA6C8 +F3 0FA6 C9, Xsha1_64, Xsha1, 0, rep enc=F30FA6C8 +F3 0FA6 CA, Xsha1_64, Xsha1, 0, rep enc=F30FA6C8 +F3 0FA6 CB, Xsha1_64, Xsha1, 0, rep enc=F30FA6C8 +F3 0FA6 CC, Xsha1_64, Xsha1, 0, rep enc=F30FA6C8 +F3 0FA6 CD, Xsha1_64, Xsha1, 0, rep enc=F30FA6C8 +F3 0FA6 CE, Xsha1_64, Xsha1, 0, rep enc=F30FA6C8 +F3 0FA6 CF, Xsha1_64, Xsha1, 0, rep enc=F30FA6C8 F3 67 0FA6 D0, Xsha256_32, Xsha256, 0, rep enc=67F30FA6D0 67 F3 0FA6 D0, Xsha256_32, Xsha256, 0, rep @@ -14477,6 +14514,13 @@ F3 67 0FA6 D0, Xsha256_32, Xsha256, 0, rep enc=67F30FA6D0 67 0FA6 D0, INVALID, INVALID, 0, code=Xsha256_32 decopt=Xbts no_opt_disable_test 67 0FA6 D0, INVALID, INVALID, 0, code=Xsha256_32 decopt=Cmpxchg486A no_opt_disable_test 67 F3 4F 0FA6 D0, Xsha256_32, Xsha256, 0, rep enc=67F30FA6D0 +67 F3 0FA6 D1, Xsha256_32, Xsha256, 0, rep enc=67F30FA6D0 +67 F3 0FA6 D2, Xsha256_32, Xsha256, 0, rep enc=67F30FA6D0 +67 F3 0FA6 D3, Xsha256_32, Xsha256, 0, rep enc=67F30FA6D0 +67 F3 0FA6 D4, Xsha256_32, Xsha256, 0, rep enc=67F30FA6D0 +67 F3 0FA6 D5, Xsha256_32, Xsha256, 0, rep enc=67F30FA6D0 +67 F3 0FA6 D6, Xsha256_32, Xsha256, 0, rep enc=67F30FA6D0 +67 F3 0FA6 D7, Xsha256_32, Xsha256, 0, rep enc=67F30FA6D0 F3 0FA6 D0, Xsha256_64, Xsha256, 0, rep F2 0FA6 D0, INVALID, INVALID, 0, code=Xsha256_64 @@ -14486,11 +14530,123 @@ F3 F2 0FA6 D0, INVALID, INVALID, 0, code=Xsha256_64 0FA6 D0, INVALID, INVALID, 0, code=Xsha256_64 decopt=Xbts no_opt_disable_test 0FA6 D0, INVALID, INVALID, 0, code=Xsha256_64 decopt=Cmpxchg486A no_opt_disable_test F3 4F 0FA6 D0, Xsha256_64, Xsha256, 0, rep enc=F30FA6D0 +F3 0FA6 D1, Xsha256_64, Xsha256, 0, rep enc=F30FA6D0 +F3 0FA6 D2, Xsha256_64, Xsha256, 0, rep enc=F30FA6D0 +F3 0FA6 D3, Xsha256_64, Xsha256, 0, rep enc=F30FA6D0 +F3 0FA6 D4, Xsha256_64, Xsha256, 0, rep enc=F30FA6D0 +F3 0FA6 D5, Xsha256_64, Xsha256, 0, rep enc=F30FA6D0 +F3 0FA6 D6, Xsha256_64, Xsha256, 0, rep enc=F30FA6D0 +F3 0FA6 D7, Xsha256_64, Xsha256, 0, rep enc=F30FA6D0 + +F3 67 0FA6 E0, Xsha512_32, Xsha512, 0, rep enc=67F30FA6E0 +67 F3 0FA6 E0, Xsha512_32, Xsha512, 0, rep +67 0FA6 E0, INVALID, INVALID, 0, code=Xsha512_32 +67 0FA6 E0, INVALID, INVALID, 0, code=Xsha512_32 decopt=Xbts no_opt_disable_test +67 0FA6 E0, INVALID, INVALID, 0, code=Xsha512_32 decopt=Cmpxchg486A no_opt_disable_test +67 F3 4F 0FA6 E0, Xsha512_32, Xsha512, 0, rep enc=67F30FA6E0 +67 F3 0FA6 E1, Xsha512_32, Xsha512, 0, rep enc=67F30FA6E0 +67 F3 0FA6 E2, Xsha512_32, Xsha512, 0, rep enc=67F30FA6E0 +67 F3 0FA6 E3, Xsha512_32, Xsha512, 0, rep enc=67F30FA6E0 +67 F3 0FA6 E4, Xsha512_32, Xsha512, 0, rep enc=67F30FA6E0 +67 F3 0FA6 E5, Xsha512_32, Xsha512, 0, rep enc=67F30FA6E0 +67 F3 0FA6 E6, Xsha512_32, Xsha512, 0, rep enc=67F30FA6E0 +67 F3 0FA6 E7, Xsha512_32, Xsha512, 0, rep enc=67F30FA6E0 + +F3 0FA6 E0, Xsha512_64, Xsha512, 0, rep +F2 0FA6 E0, INVALID, INVALID, 0, code=Xsha512_64 +F2 F3 0FA6 E0, Xsha512_64, Xsha512, 0, rep enc=F30FA6E0 +F3 F2 0FA6 E0, INVALID, INVALID, 0, code=Xsha512_64 +0FA6 E0, INVALID, INVALID, 0, code=Xsha512_64 +0FA6 E0, INVALID, INVALID, 0, code=Xsha512_64 decopt=Xbts no_opt_disable_test +0FA6 E0, INVALID, INVALID, 0, code=Xsha512_64 decopt=Cmpxchg486A no_opt_disable_test +F3 4F 0FA6 E0, Xsha512_64, Xsha512, 0, rep enc=F30FA6E0 +F3 0FA6 E1, Xsha512_64, Xsha512, 0, rep enc=F30FA6E0 +F3 0FA6 E2, Xsha512_64, Xsha512, 0, rep enc=F30FA6E0 +F3 0FA6 E3, Xsha512_64, Xsha512, 0, rep enc=F30FA6E0 +F3 0FA6 E4, Xsha512_64, Xsha512, 0, rep enc=F30FA6E0 +F3 0FA6 E5, Xsha512_64, Xsha512, 0, rep enc=F30FA6E0 +F3 0FA6 E6, Xsha512_64, Xsha512, 0, rep enc=F30FA6E0 +F3 0FA6 E7, Xsha512_64, Xsha512, 0, rep enc=F30FA6E0 + +F3 67 0FA6 F0, Via_undoc_F30FA6F0_32, Undoc, 0, rep enc=67F30FA6F0 +67 F3 0FA6 F0, Via_undoc_F30FA6F0_32, Undoc, 0, rep +67 0FA6 F0, INVALID, INVALID, 0, code=Via_undoc_F30FA6F0_32 +67 0FA6 F0, INVALID, INVALID, 0, code=Via_undoc_F30FA6F0_32 decopt=Xbts no_opt_disable_test +67 0FA6 F0, INVALID, INVALID, 0, code=Via_undoc_F30FA6F0_32 decopt=Cmpxchg486A no_opt_disable_test +67 F3 4F 0FA6 F0, Via_undoc_F30FA6F0_32, Undoc, 0, rep enc=67F30FA6F0 +67 F3 0FA6 F1, Via_undoc_F30FA6F0_32, Undoc, 0, rep enc=67F30FA6F0 +67 F3 0FA6 F2, Via_undoc_F30FA6F0_32, Undoc, 0, rep enc=67F30FA6F0 +67 F3 0FA6 F3, Via_undoc_F30FA6F0_32, Undoc, 0, rep enc=67F30FA6F0 +67 F3 0FA6 F4, Via_undoc_F30FA6F0_32, Undoc, 0, rep enc=67F30FA6F0 +67 F3 0FA6 F5, Via_undoc_F30FA6F0_32, Undoc, 0, rep enc=67F30FA6F0 +67 F3 0FA6 F6, Via_undoc_F30FA6F0_32, Undoc, 0, rep enc=67F30FA6F0 +67 F3 0FA6 F7, Via_undoc_F30FA6F0_32, Undoc, 0, rep enc=67F30FA6F0 + +F3 0FA6 F0, Via_undoc_F30FA6F0_64, Undoc, 0, rep +F2 0FA6 F0, INVALID, INVALID, 0, code=Via_undoc_F30FA6F0_64 +F2 F3 0FA6 F0, Via_undoc_F30FA6F0_64, Undoc, 0, rep enc=F30FA6F0 +F3 F2 0FA6 F0, INVALID, INVALID, 0, code=Via_undoc_F30FA6F0_64 +0FA6 F0, INVALID, INVALID, 0, code=Via_undoc_F30FA6F0_64 +0FA6 F0, INVALID, INVALID, 0, code=Via_undoc_F30FA6F0_64 decopt=Xbts no_opt_disable_test +0FA6 F0, INVALID, INVALID, 0, code=Via_undoc_F30FA6F0_64 decopt=Cmpxchg486A no_opt_disable_test +F3 4F 0FA6 F0, Via_undoc_F30FA6F0_64, Undoc, 0, rep enc=F30FA6F0 +F3 0FA6 F1, Via_undoc_F30FA6F0_64, Undoc, 0, rep enc=F30FA6F0 +F3 0FA6 F2, Via_undoc_F30FA6F0_64, Undoc, 0, rep enc=F30FA6F0 +F3 0FA6 F3, Via_undoc_F30FA6F0_64, Undoc, 0, rep enc=F30FA6F0 +F3 0FA6 F4, Via_undoc_F30FA6F0_64, Undoc, 0, rep enc=F30FA6F0 +F3 0FA6 F5, Via_undoc_F30FA6F0_64, Undoc, 0, rep enc=F30FA6F0 +F3 0FA6 F6, Via_undoc_F30FA6F0_64, Undoc, 0, rep enc=F30FA6F0 +F3 0FA6 F7, Via_undoc_F30FA6F0_64, Undoc, 0, rep enc=F30FA6F0 + +F3 67 0FA6 F8, Via_undoc_F30FA6F8_32, Undoc, 0, rep enc=67F30FA6F8 +67 F3 0FA6 F8, Via_undoc_F30FA6F8_32, Undoc, 0, rep +67 0FA6 F8, INVALID, INVALID, 0, code=Via_undoc_F30FA6F8_32 +67 0FA6 F8, INVALID, INVALID, 0, code=Via_undoc_F30FA6F8_32 decopt=Xbts no_opt_disable_test +67 0FA6 F8, INVALID, INVALID, 0, code=Via_undoc_F30FA6F8_32 decopt=Cmpxchg486A no_opt_disable_test +67 F3 4F 0FA6 F8, Via_undoc_F30FA6F8_32, Undoc, 0, rep enc=67F30FA6F8 +67 F3 0FA6 F9, Via_undoc_F30FA6F8_32, Undoc, 0, rep enc=67F30FA6F8 +67 F3 0FA6 FA, Via_undoc_F30FA6F8_32, Undoc, 0, rep enc=67F30FA6F8 +67 F3 0FA6 FB, Via_undoc_F30FA6F8_32, Undoc, 0, rep enc=67F30FA6F8 +67 F3 0FA6 FC, Via_undoc_F30FA6F8_32, Undoc, 0, rep enc=67F30FA6F8 +67 F3 0FA6 FD, Via_undoc_F30FA6F8_32, Undoc, 0, rep enc=67F30FA6F8 +67 F3 0FA6 FE, Via_undoc_F30FA6F8_32, Undoc, 0, rep enc=67F30FA6F8 +67 F3 0FA6 FF, Via_undoc_F30FA6F8_32, Undoc, 0, rep enc=67F30FA6F8 + +F3 0FA6 F8, Via_undoc_F30FA6F8_64, Undoc, 0, rep +F2 0FA6 F8, INVALID, INVALID, 0, code=Via_undoc_F30FA6F8_64 +F2 F3 0FA6 F8, Via_undoc_F30FA6F8_64, Undoc, 0, rep enc=F30FA6F8 +F3 F2 0FA6 F8, INVALID, INVALID, 0, code=Via_undoc_F30FA6F8_64 +0FA6 F8, INVALID, INVALID, 0, code=Via_undoc_F30FA6F8_64 +0FA6 F8, INVALID, INVALID, 0, code=Via_undoc_F30FA6F8_64 decopt=Xbts no_opt_disable_test +0FA6 F8, INVALID, INVALID, 0, code=Via_undoc_F30FA6F8_64 decopt=Cmpxchg486A no_opt_disable_test +F3 4F 0FA6 F8, Via_undoc_F30FA6F8_64, Undoc, 0, rep enc=F30FA6F8 +F3 0FA6 F9, Via_undoc_F30FA6F8_64, Undoc, 0, rep enc=F30FA6F8 +F3 0FA6 FA, Via_undoc_F30FA6F8_64, Undoc, 0, rep enc=F30FA6F8 +F3 0FA6 FB, Via_undoc_F30FA6F8_64, Undoc, 0, rep enc=F30FA6F8 +F3 0FA6 FC, Via_undoc_F30FA6F8_64, Undoc, 0, rep enc=F30FA6F8 +F3 0FA6 FD, Via_undoc_F30FA6F8_64, Undoc, 0, rep enc=F30FA6F8 +F3 0FA6 FE, Via_undoc_F30FA6F8_64, Undoc, 0, rep enc=F30FA6F8 +F3 0FA6 FF, Via_undoc_F30FA6F8_64, Undoc, 0, rep enc=F30FA6F8 F3 67 0FA7 C0, Xstore_32, Xstore, 0, rep enc=67F30FA7C0 67 F3 0FA7 C0, Xstore_32, Xstore, 0, rep 67 0FA7 C0, Xstore_32, Xstore, 0, 67 F3 4F 0FA7 C0, Xstore_32, Xstore, 0, rep enc=67F30FA7C0 +67 F3 0FA7 C1, Xstore_32, Xstore, 0, rep enc=67F30FA7C0 +67 F3 0FA7 C2, Xstore_32, Xstore, 0, rep enc=67F30FA7C0 +67 F3 0FA7 C3, Xstore_32, Xstore, 0, rep enc=67F30FA7C0 +67 F3 0FA7 C4, Xstore_32, Xstore, 0, rep enc=67F30FA7C0 +67 F3 0FA7 C5, Xstore_32, Xstore, 0, rep enc=67F30FA7C0 +67 F3 0FA7 C6, Xstore_32, Xstore, 0, rep enc=67F30FA7C0 +67 F3 0FA7 C7, Xstore_32, Xstore, 0, rep enc=67F30FA7C0 +67 F2 0FA7 C0, Xstore_32, Xstore, 0, repne enc=67F20FA7C0 +67 F2 0FA7 C1, Xstore_32, Xstore, 0, repne enc=67F20FA7C0 +67 F2 0FA7 C2, Xstore_32, Xstore, 0, repne enc=67F20FA7C0 +67 F2 0FA7 C3, Xstore_32, Xstore, 0, repne enc=67F20FA7C0 +67 F2 0FA7 C4, Xstore_32, Xstore, 0, repne enc=67F20FA7C0 +67 F2 0FA7 C5, Xstore_32, Xstore, 0, repne enc=67F20FA7C0 +67 F2 0FA7 C6, Xstore_32, Xstore, 0, repne enc=67F20FA7C0 +67 F2 0FA7 C7, Xstore_32, Xstore, 0, repne enc=67F20FA7C0 F3 0FA7 C0, Xstore_64, Xstore, 0, rep F2 0FA7 C0, Xstore_64, Xstore, 0, repne @@ -14498,11 +14654,73 @@ F2 F3 0FA7 C0, Xstore_64, Xstore, 0, rep enc=F30FA7C0 F3 F2 0FA7 C0, Xstore_64, Xstore, 0, repne enc=F20FA7C0 0FA7 C0, Xstore_64, Xstore, 0, F3 4F 0FA7 C0, Xstore_64, Xstore, 0, rep enc=F30FA7C0 +F3 0FA7 C1, Xstore_64, Xstore, 0, rep enc=F30FA7C0 +F3 0FA7 C2, Xstore_64, Xstore, 0, rep enc=F30FA7C0 +F3 0FA7 C3, Xstore_64, Xstore, 0, rep enc=F30FA7C0 +F3 0FA7 C4, Xstore_64, Xstore, 0, rep enc=F30FA7C0 +F3 0FA7 C5, Xstore_64, Xstore, 0, rep enc=F30FA7C0 +F3 0FA7 C6, Xstore_64, Xstore, 0, rep enc=F30FA7C0 +F3 0FA7 C7, Xstore_64, Xstore, 0, rep enc=F30FA7C0 +F2 0FA7 C1, Xstore_64, Xstore, 0, repne enc=F20FA7C0 +F2 0FA7 C2, Xstore_64, Xstore, 0, repne enc=F20FA7C0 +F2 0FA7 C3, Xstore_64, Xstore, 0, repne enc=F20FA7C0 +F2 0FA7 C4, Xstore_64, Xstore, 0, repne enc=F20FA7C0 +F2 0FA7 C5, Xstore_64, Xstore, 0, repne enc=F20FA7C0 +F2 0FA7 C6, Xstore_64, Xstore, 0, repne enc=F20FA7C0 +F2 0FA7 C7, Xstore_64, Xstore, 0, repne enc=F20FA7C0 + +F3 67 0FA7 F8, Xstore2_32, Xstore2, 0, rep enc=67F30FA7F8 +67 F3 0FA7 F8, Xstore2_32, Xstore2, 0, rep +67 0FA7 F8, INVALID, INVALID, 0, code=Xstore2_32 +67 F3 4F 0FA7 F8, Xstore2_32, Xstore2, 0, rep enc=67F30FA7F8 +67 F3 0FA7 F9, Xstore2_32, Xstore2, 0, rep enc=67F30FA7F8 +67 F3 0FA7 FA, Xstore2_32, Xstore2, 0, rep enc=67F30FA7F8 +67 F3 0FA7 FB, Xstore2_32, Xstore2, 0, rep enc=67F30FA7F8 +67 F3 0FA7 FC, Xstore2_32, Xstore2, 0, rep enc=67F30FA7F8 +67 F3 0FA7 FD, Xstore2_32, Xstore2, 0, rep enc=67F30FA7F8 +67 F3 0FA7 FE, Xstore2_32, Xstore2, 0, rep enc=67F30FA7F8 +67 F3 0FA7 FF, Xstore2_32, Xstore2, 0, rep enc=67F30FA7F8 +67 F2 0FA7 F8, INVALID, INVALID, 0, code=Xstore2_32 +67 F2 0FA7 F9, INVALID, INVALID, 0, code=Xstore2_32 +67 F2 0FA7 FA, INVALID, INVALID, 0, code=Xstore2_32 +67 F2 0FA7 FB, INVALID, INVALID, 0, code=Xstore2_32 +67 F2 0FA7 FC, INVALID, INVALID, 0, code=Xstore2_32 +67 F2 0FA7 FD, INVALID, INVALID, 0, code=Xstore2_32 +67 F2 0FA7 FE, INVALID, INVALID, 0, code=Xstore2_32 +67 F2 0FA7 FF, INVALID, INVALID, 0, code=Xstore2_32 + +F3 0FA7 F8, Xstore2_64, Xstore2, 0, rep +F2 0FA7 F8, INVALID, INVALID, 0, code=Xstore2_64 +F2 F3 0FA7 F8, Xstore2_64, Xstore2, 0, rep enc=F30FA7F8 +F3 F2 0FA7 F8, INVALID, INVALID, 0, code=Xstore2_64 +0FA7 F8, INVALID, INVALID, 0, code=Xstore2_64 +F3 4F 0FA7 F8, Xstore2_64, Xstore2, 0, rep enc=F30FA7F8 +F3 0FA7 F9, Xstore2_64, Xstore2, 0, rep enc=F30FA7F8 +F3 0FA7 FA, Xstore2_64, Xstore2, 0, rep enc=F30FA7F8 +F3 0FA7 FB, Xstore2_64, Xstore2, 0, rep enc=F30FA7F8 +F3 0FA7 FC, Xstore2_64, Xstore2, 0, rep enc=F30FA7F8 +F3 0FA7 FD, Xstore2_64, Xstore2, 0, rep enc=F30FA7F8 +F3 0FA7 FE, Xstore2_64, Xstore2, 0, rep enc=F30FA7F8 +F3 0FA7 FF, Xstore2_64, Xstore2, 0, rep enc=F30FA7F8 +F2 0FA7 F9, INVALID, INVALID, 0, code=Xstore2_64 +F2 0FA7 FA, INVALID, INVALID, 0, code=Xstore2_64 +F2 0FA7 FB, INVALID, INVALID, 0, code=Xstore2_64 +F2 0FA7 FC, INVALID, INVALID, 0, code=Xstore2_64 +F2 0FA7 FD, INVALID, INVALID, 0, code=Xstore2_64 +F2 0FA7 FE, INVALID, INVALID, 0, code=Xstore2_64 +F2 0FA7 FF, INVALID, INVALID, 0, code=Xstore2_64 F3 67 0FA7 C8, Xcryptecb_32, Xcryptecb, 0, rep enc=67F30FA7C8 67 F3 0FA7 C8, Xcryptecb_32, Xcryptecb, 0, rep 67 0FA7 C8, INVALID, INVALID, 0, code=Xcryptecb_32 67 F3 4F 0FA7 C8, Xcryptecb_32, Xcryptecb, 0, rep enc=67F30FA7C8 +67 F3 0FA7 C9, Xcryptecb_32, Xcryptecb, 0, rep enc=67F30FA7C8 +67 F3 0FA7 CA, Xcryptecb_32, Xcryptecb, 0, rep enc=67F30FA7C8 +67 F3 0FA7 CB, Xcryptecb_32, Xcryptecb, 0, rep enc=67F30FA7C8 +67 F3 0FA7 CC, Xcryptecb_32, Xcryptecb, 0, rep enc=67F30FA7C8 +67 F3 0FA7 CD, Xcryptecb_32, Xcryptecb, 0, rep enc=67F30FA7C8 +67 F3 0FA7 CE, Xcryptecb_32, Xcryptecb, 0, rep enc=67F30FA7C8 +67 F3 0FA7 CF, Xcryptecb_32, Xcryptecb, 0, rep enc=67F30FA7C8 F3 0FA7 C8, Xcryptecb_64, Xcryptecb, 0, rep F2 0FA7 C8, INVALID, INVALID, 0, code=Xcryptecb_64 @@ -14510,11 +14728,25 @@ F2 F3 0FA7 C8, Xcryptecb_64, Xcryptecb, 0, rep enc=F30FA7C8 F3 F2 0FA7 C8, INVALID, INVALID, 0, code=Xcryptecb_64 0FA7 C8, INVALID, INVALID, 0, code=Xcryptecb_64 F3 4F 0FA7 C8, Xcryptecb_64, Xcryptecb, 0, rep enc=F30FA7C8 +F3 0FA7 C9, Xcryptecb_64, Xcryptecb, 0, rep enc=F30FA7C8 +F3 0FA7 CA, Xcryptecb_64, Xcryptecb, 0, rep enc=F30FA7C8 +F3 0FA7 CB, Xcryptecb_64, Xcryptecb, 0, rep enc=F30FA7C8 +F3 0FA7 CC, Xcryptecb_64, Xcryptecb, 0, rep enc=F30FA7C8 +F3 0FA7 CD, Xcryptecb_64, Xcryptecb, 0, rep enc=F30FA7C8 +F3 0FA7 CE, Xcryptecb_64, Xcryptecb, 0, rep enc=F30FA7C8 +F3 0FA7 CF, Xcryptecb_64, Xcryptecb, 0, rep enc=F30FA7C8 F3 67 0FA7 D0, Xcryptcbc_32, Xcryptcbc, 0, rep enc=67F30FA7D0 67 F3 0FA7 D0, Xcryptcbc_32, Xcryptcbc, 0, rep 67 0FA7 D0, INVALID, INVALID, 0, code=Xcryptcbc_32 67 F3 4F 0FA7 D0, Xcryptcbc_32, Xcryptcbc, 0, rep enc=67F30FA7D0 +67 F3 0FA7 D1, Xcryptcbc_32, Xcryptcbc, 0, rep enc=67F30FA7D0 +67 F3 0FA7 D2, Xcryptcbc_32, Xcryptcbc, 0, rep enc=67F30FA7D0 +67 F3 0FA7 D3, Xcryptcbc_32, Xcryptcbc, 0, rep enc=67F30FA7D0 +67 F3 0FA7 D4, Xcryptcbc_32, Xcryptcbc, 0, rep enc=67F30FA7D0 +67 F3 0FA7 D5, Xcryptcbc_32, Xcryptcbc, 0, rep enc=67F30FA7D0 +67 F3 0FA7 D6, Xcryptcbc_32, Xcryptcbc, 0, rep enc=67F30FA7D0 +67 F3 0FA7 D7, Xcryptcbc_32, Xcryptcbc, 0, rep enc=67F30FA7D0 F3 0FA7 D0, Xcryptcbc_64, Xcryptcbc, 0, rep F2 0FA7 D0, INVALID, INVALID, 0, code=Xcryptcbc_64 @@ -14522,11 +14754,25 @@ F2 F3 0FA7 D0, Xcryptcbc_64, Xcryptcbc, 0, rep enc=F30FA7D0 F3 F2 0FA7 D0, INVALID, INVALID, 0, code=Xcryptcbc_64 0FA7 D0, INVALID, INVALID, 0, code=Xcryptcbc_64 F3 4F 0FA7 D0, Xcryptcbc_64, Xcryptcbc, 0, rep enc=F30FA7D0 +F3 0FA7 D1, Xcryptcbc_64, Xcryptcbc, 0, rep enc=F30FA7D0 +F3 0FA7 D2, Xcryptcbc_64, Xcryptcbc, 0, rep enc=F30FA7D0 +F3 0FA7 D3, Xcryptcbc_64, Xcryptcbc, 0, rep enc=F30FA7D0 +F3 0FA7 D4, Xcryptcbc_64, Xcryptcbc, 0, rep enc=F30FA7D0 +F3 0FA7 D5, Xcryptcbc_64, Xcryptcbc, 0, rep enc=F30FA7D0 +F3 0FA7 D6, Xcryptcbc_64, Xcryptcbc, 0, rep enc=F30FA7D0 +F3 0FA7 D7, Xcryptcbc_64, Xcryptcbc, 0, rep enc=F30FA7D0 F3 67 0FA7 D8, Xcryptctr_32, Xcryptctr, 0, rep enc=67F30FA7D8 67 F3 0FA7 D8, Xcryptctr_32, Xcryptctr, 0, rep 67 0FA7 D8, INVALID, INVALID, 0, code=Xcryptctr_32 67 F3 4F 0FA7 D8, Xcryptctr_32, Xcryptctr, 0, rep enc=67F30FA7D8 +67 F3 0FA7 D9, Xcryptctr_32, Xcryptctr, 0, rep enc=67F30FA7D8 +67 F3 0FA7 DA, Xcryptctr_32, Xcryptctr, 0, rep enc=67F30FA7D8 +67 F3 0FA7 DB, Xcryptctr_32, Xcryptctr, 0, rep enc=67F30FA7D8 +67 F3 0FA7 DC, Xcryptctr_32, Xcryptctr, 0, rep enc=67F30FA7D8 +67 F3 0FA7 DD, Xcryptctr_32, Xcryptctr, 0, rep enc=67F30FA7D8 +67 F3 0FA7 DE, Xcryptctr_32, Xcryptctr, 0, rep enc=67F30FA7D8 +67 F3 0FA7 DF, Xcryptctr_32, Xcryptctr, 0, rep enc=67F30FA7D8 F3 0FA7 D8, Xcryptctr_64, Xcryptctr, 0, rep F2 0FA7 D8, INVALID, INVALID, 0, code=Xcryptctr_64 @@ -14534,11 +14780,25 @@ F2 F3 0FA7 D8, Xcryptctr_64, Xcryptctr, 0, rep enc=F30FA7D8 F3 F2 0FA7 D8, INVALID, INVALID, 0, code=Xcryptctr_64 0FA7 D8, INVALID, INVALID, 0, code=Xcryptctr_64 F3 4F 0FA7 D8, Xcryptctr_64, Xcryptctr, 0, rep enc=F30FA7D8 +F3 0FA7 D9, Xcryptctr_64, Xcryptctr, 0, rep enc=F30FA7D8 +F3 0FA7 DA, Xcryptctr_64, Xcryptctr, 0, rep enc=F30FA7D8 +F3 0FA7 DB, Xcryptctr_64, Xcryptctr, 0, rep enc=F30FA7D8 +F3 0FA7 DC, Xcryptctr_64, Xcryptctr, 0, rep enc=F30FA7D8 +F3 0FA7 DD, Xcryptctr_64, Xcryptctr, 0, rep enc=F30FA7D8 +F3 0FA7 DE, Xcryptctr_64, Xcryptctr, 0, rep enc=F30FA7D8 +F3 0FA7 DF, Xcryptctr_64, Xcryptctr, 0, rep enc=F30FA7D8 F3 67 0FA7 E0, Xcryptcfb_32, Xcryptcfb, 0, rep enc=67F30FA7E0 67 F3 0FA7 E0, Xcryptcfb_32, Xcryptcfb, 0, rep 67 0FA7 E0, INVALID, INVALID, 0, code=Xcryptcfb_32 67 F3 4F 0FA7 E0, Xcryptcfb_32, Xcryptcfb, 0, rep enc=67F30FA7E0 +67 F3 0FA7 E1, Xcryptcfb_32, Xcryptcfb, 0, rep enc=67F30FA7E0 +67 F3 0FA7 E2, Xcryptcfb_32, Xcryptcfb, 0, rep enc=67F30FA7E0 +67 F3 0FA7 E3, Xcryptcfb_32, Xcryptcfb, 0, rep enc=67F30FA7E0 +67 F3 0FA7 E4, Xcryptcfb_32, Xcryptcfb, 0, rep enc=67F30FA7E0 +67 F3 0FA7 E5, Xcryptcfb_32, Xcryptcfb, 0, rep enc=67F30FA7E0 +67 F3 0FA7 E6, Xcryptcfb_32, Xcryptcfb, 0, rep enc=67F30FA7E0 +67 F3 0FA7 E7, Xcryptcfb_32, Xcryptcfb, 0, rep enc=67F30FA7E0 F3 0FA7 E0, Xcryptcfb_64, Xcryptcfb, 0, rep F2 0FA7 E0, INVALID, INVALID, 0, code=Xcryptcfb_64 @@ -14546,11 +14806,25 @@ F2 F3 0FA7 E0, Xcryptcfb_64, Xcryptcfb, 0, rep enc=F30FA7E0 F3 F2 0FA7 E0, INVALID, INVALID, 0, code=Xcryptcfb_64 0FA7 E0, INVALID, INVALID, 0, code=Xcryptcfb_64 F3 4F 0FA7 E0, Xcryptcfb_64, Xcryptcfb, 0, rep enc=F30FA7E0 +F3 0FA7 E1, Xcryptcfb_64, Xcryptcfb, 0, rep enc=F30FA7E0 +F3 0FA7 E2, Xcryptcfb_64, Xcryptcfb, 0, rep enc=F30FA7E0 +F3 0FA7 E3, Xcryptcfb_64, Xcryptcfb, 0, rep enc=F30FA7E0 +F3 0FA7 E4, Xcryptcfb_64, Xcryptcfb, 0, rep enc=F30FA7E0 +F3 0FA7 E5, Xcryptcfb_64, Xcryptcfb, 0, rep enc=F30FA7E0 +F3 0FA7 E6, Xcryptcfb_64, Xcryptcfb, 0, rep enc=F30FA7E0 +F3 0FA7 E7, Xcryptcfb_64, Xcryptcfb, 0, rep enc=F30FA7E0 F3 67 0FA7 E8, Xcryptofb_32, Xcryptofb, 0, rep enc=67F30FA7E8 67 F3 0FA7 E8, Xcryptofb_32, Xcryptofb, 0, rep 67 0FA7 E8, INVALID, INVALID, 0, code=Xcryptofb_32 67 F3 4F 0FA7 E8, Xcryptofb_32, Xcryptofb, 0, rep enc=67F30FA7E8 +67 F3 0FA7 E9, Xcryptofb_32, Xcryptofb, 0, rep enc=67F30FA7E8 +67 F3 0FA7 EA, Xcryptofb_32, Xcryptofb, 0, rep enc=67F30FA7E8 +67 F3 0FA7 EB, Xcryptofb_32, Xcryptofb, 0, rep enc=67F30FA7E8 +67 F3 0FA7 EC, Xcryptofb_32, Xcryptofb, 0, rep enc=67F30FA7E8 +67 F3 0FA7 ED, Xcryptofb_32, Xcryptofb, 0, rep enc=67F30FA7E8 +67 F3 0FA7 EE, Xcryptofb_32, Xcryptofb, 0, rep enc=67F30FA7E8 +67 F3 0FA7 EF, Xcryptofb_32, Xcryptofb, 0, rep enc=67F30FA7E8 F3 0FA7 E8, Xcryptofb_64, Xcryptofb, 0, rep F2 0FA7 E8, INVALID, INVALID, 0, code=Xcryptofb_64 @@ -14558,6 +14832,13 @@ F2 F3 0FA7 E8, Xcryptofb_64, Xcryptofb, 0, rep enc=F30FA7E8 F3 F2 0FA7 E8, INVALID, INVALID, 0, code=Xcryptofb_64 0FA7 E8, INVALID, INVALID, 0, code=Xcryptofb_64 F3 4F 0FA7 E8, Xcryptofb_64, Xcryptofb, 0, rep enc=F30FA7E8 +F3 0FA7 E9, Xcryptofb_64, Xcryptofb, 0, rep enc=F30FA7E8 +F3 0FA7 EA, Xcryptofb_64, Xcryptofb, 0, rep enc=F30FA7E8 +F3 0FA7 EB, Xcryptofb_64, Xcryptofb, 0, rep enc=F30FA7E8 +F3 0FA7 EC, Xcryptofb_64, Xcryptofb, 0, rep enc=F30FA7E8 +F3 0FA7 ED, Xcryptofb_64, Xcryptofb, 0, rep enc=F30FA7E8 +F3 0FA7 EE, Xcryptofb_64, Xcryptofb, 0, rep enc=F30FA7E8 +F3 0FA7 EF, Xcryptofb_64, Xcryptofb, 0, rep enc=F30FA7E8 66 0FA8, Pushw_GS, Push, 1, op0=r;gs 66 47 0FA8, Pushw_GS, Push, 1, op0=r;gs enc=660FA8 @@ -32544,6 +32825,13 @@ F3 67 0FA6 E8, Ccs_hash_32, Ccs_hash, 0, rep enc=67F30FA6E8 67 0FA6 E8, INVALID, INVALID, 0, code=Ccs_hash_32 decopt=Xbts no_opt_disable_test 67 0FA6 E8, INVALID, INVALID, 0, code=Ccs_hash_32 decopt=Cmpxchg486A no_opt_disable_test 67 F3 4F 0FA6 E8, Ccs_hash_32, Ccs_hash, 0, rep enc=67F30FA6E8 +67 F3 0FA6 E9, Ccs_hash_32, Ccs_hash, 0, rep enc=67F30FA6E8 +67 F3 0FA6 EA, Ccs_hash_32, Ccs_hash, 0, rep enc=67F30FA6E8 +67 F3 0FA6 EB, Ccs_hash_32, Ccs_hash, 0, rep enc=67F30FA6E8 +67 F3 0FA6 EC, Ccs_hash_32, Ccs_hash, 0, rep enc=67F30FA6E8 +67 F3 0FA6 ED, Ccs_hash_32, Ccs_hash, 0, rep enc=67F30FA6E8 +67 F3 0FA6 EE, Ccs_hash_32, Ccs_hash, 0, rep enc=67F30FA6E8 +67 F3 0FA6 EF, Ccs_hash_32, Ccs_hash, 0, rep enc=67F30FA6E8 F3 0FA6 E8, Ccs_hash_64, Ccs_hash, 0, rep F2 0FA6 E8, INVALID, INVALID, 0, code=Ccs_hash_64 @@ -32553,6 +32841,13 @@ F3 F2 0FA6 E8, INVALID, INVALID, 0, code=Ccs_hash_64 0FA6 E8, INVALID, INVALID, 0, code=Ccs_hash_64 decopt=Xbts no_opt_disable_test 0FA6 E8, INVALID, INVALID, 0, code=Ccs_hash_64 decopt=Cmpxchg486A no_opt_disable_test F3 4F 0FA6 E8, Ccs_hash_64, Ccs_hash, 0, rep enc=F30FA6E8 +F3 0FA6 E9, Ccs_hash_64, Ccs_hash, 0, rep enc=F30FA6E8 +F3 0FA6 EA, Ccs_hash_64, Ccs_hash, 0, rep enc=F30FA6E8 +F3 0FA6 EB, Ccs_hash_64, Ccs_hash, 0, rep enc=F30FA6E8 +F3 0FA6 EC, Ccs_hash_64, Ccs_hash, 0, rep enc=F30FA6E8 +F3 0FA6 ED, Ccs_hash_64, Ccs_hash, 0, rep enc=F30FA6E8 +F3 0FA6 EE, Ccs_hash_64, Ccs_hash, 0, rep enc=F30FA6E8 +F3 0FA6 EF, Ccs_hash_64, Ccs_hash, 0, rep enc=F30FA6E8 F3 67 0FA7 F0, Ccs_encrypt_32, Ccs_encrypt, 0, rep enc=67F30FA7F0 67 F3 0FA7 F0, Ccs_encrypt_32, Ccs_encrypt, 0, rep @@ -32560,6 +32855,13 @@ F3 67 0FA7 F0, Ccs_encrypt_32, Ccs_encrypt, 0, rep enc=67F30FA7F0 67 0FA7 F0, INVALID, INVALID, 0, code=Ccs_encrypt_32 decopt=Xbts no_opt_disable_test 67 0FA7 F0, INVALID, INVALID, 0, code=Ccs_encrypt_32 decopt=Cmpxchg486A no_opt_disable_test 67 F3 4F 0FA7 F0, Ccs_encrypt_32, Ccs_encrypt, 0, rep enc=67F30FA7F0 +67 F3 0FA7 F1, Ccs_encrypt_32, Ccs_encrypt, 0, rep enc=67F30FA7F0 +67 F3 0FA7 F2, Ccs_encrypt_32, Ccs_encrypt, 0, rep enc=67F30FA7F0 +67 F3 0FA7 F3, Ccs_encrypt_32, Ccs_encrypt, 0, rep enc=67F30FA7F0 +67 F3 0FA7 F4, Ccs_encrypt_32, Ccs_encrypt, 0, rep enc=67F30FA7F0 +67 F3 0FA7 F5, Ccs_encrypt_32, Ccs_encrypt, 0, rep enc=67F30FA7F0 +67 F3 0FA7 F6, Ccs_encrypt_32, Ccs_encrypt, 0, rep enc=67F30FA7F0 +67 F3 0FA7 F7, Ccs_encrypt_32, Ccs_encrypt, 0, rep enc=67F30FA7F0 F3 0FA7 F0, Ccs_encrypt_64, Ccs_encrypt, 0, rep F2 0FA7 F0, INVALID, INVALID, 0, code=Ccs_encrypt_64 @@ -32569,6 +32871,13 @@ F3 F2 0FA7 F0, INVALID, INVALID, 0, code=Ccs_encrypt_64 0FA7 F0, INVALID, INVALID, 0, code=Ccs_encrypt_64 decopt=Xbts no_opt_disable_test 0FA7 F0, INVALID, INVALID, 0, code=Ccs_encrypt_64 decopt=Cmpxchg486A no_opt_disable_test F3 4F 0FA7 F0, Ccs_encrypt_64, Ccs_encrypt, 0, rep enc=F30FA7F0 +F3 0FA7 F1, Ccs_encrypt_64, Ccs_encrypt, 0, rep enc=F30FA7F0 +F3 0FA7 F2, Ccs_encrypt_64, Ccs_encrypt, 0, rep enc=F30FA7F0 +F3 0FA7 F3, Ccs_encrypt_64, Ccs_encrypt, 0, rep enc=F30FA7F0 +F3 0FA7 F4, Ccs_encrypt_64, Ccs_encrypt, 0, rep enc=F30FA7F0 +F3 0FA7 F5, Ccs_encrypt_64, Ccs_encrypt, 0, rep enc=F30FA7F0 +F3 0FA7 F6, Ccs_encrypt_64, Ccs_encrypt, 0, rep enc=F30FA7F0 +F3 0FA7 F7, Ccs_encrypt_64, Ccs_encrypt, 0, rep enc=F30FA7F0 66 F2 0F00 F1, Lkgs_rm16, Lkgs, 1, op0=r;cx F2 66 0F00 F1, Lkgs_rm16, Lkgs, 1, op0=r;cx enc=66F20F00F1 diff --git a/src/UnitTests/Intel/Encoder/OpCodeInfos.txt b/src/UnitTests/Intel/Encoder/OpCodeInfos.txt index b0a15e18c..0dc83744e 100644 --- a/src/UnitTests/Intel/Encoder/OpCodeInfos.txt +++ b/src/UnitTests/Intel/Encoder/OpCodeInfos.txt @@ -4821,3 +4821,15 @@ MVEX_Vcvtfxpntps2dq_zmm_k1_zmmmt_imm8, Vcvtfxpntps2dq, Unknown, Unknown, MVEX, 6 MVEX_Undoc_zmm_k1_zmmmt_imm8_512_66_0F3A_W0_D0, Undoc, Unknown, Unknown, MVEX, 66, 0F3A, D0, MVEX.512.66.0F3A.W0 D0 /r ib, UNDOC zmm1 {k1}| zmm2/mt| imm8, dec-opt=KNC 64 cpl0 cpl1 cpl2 cpl3 L512 W0 op=zmm_reg;zmm_or_mem;imm8 save-restore tt=N1 mvex=Float32;None;0xFF;0xFF er sae k intel64 amd64 lm outside-smm in-smm outside-sgx in-sgx1 in-sgx2 outside-vmx-op in-vmx-root-op in-vmx-non-root-op outside-seam in-seam eh MVEX_Undoc_zmm_k1_zmmmt_imm8_512_66_0F3A_W0_D1, Undoc, Unknown, Unknown, MVEX, 66, 0F3A, D1, MVEX.512.66.0F3A.W0 D1 /r ib, UNDOC zmm1 {k1}| zmm2/mt| imm8, dec-opt=KNC 64 cpl0 cpl1 cpl2 cpl3 L512 W0 op=zmm_reg;zmm_or_mem;imm8 save-restore tt=N1 mvex=Float32;None;0xFF;0xFF er sae k intel64 amd64 lm outside-smm in-smm outside-sgx in-sgx1 in-sgx2 outside-vmx-op in-vmx-root-op in-vmx-non-root-op outside-seam in-seam eh MVEX_Vcvtfxpntpd2dq_zmm_k1_zmmmt_imm8, Vcvtfxpntpd2dq, Unknown, Unknown, MVEX, F2, 0F3A, E6, MVEX.512.F2.0F3A.W1 E6 /r ib, VCVTFXPNTPD2DQ zmm1 {k1}| Sf64(zmm2/mt)| imm8, dec-opt=KNC 64 cpl0 cpl1 cpl2 cpl3 L512 W1 op=zmm_reg;zmm_or_mem;imm8 tt=N1 mvex=Float64;Sf64;0x7;0xFF er sae k intel64 amd64 lm outside-smm in-smm outside-sgx in-sgx1 in-sgx2 outside-vmx-op in-vmx-root-op in-vmx-non-root-op outside-seam in-seam eh er-imm +Via_undoc_F30FA6F0_16, Undoc, Unknown, Unknown, legacy, F3, 0F, A6F0, a16 F3 0F A6 F0, UNDOC, 16 32 cpl0 cpl1 cpl2 cpl3 a16 save-restore intel16 intel32 amd16 amd32 rm pm v86 cm outside-smm in-smm outside-sgx in-sgx1 in-sgx2 outside-vmx-op in-vmx-root-op in-vmx-non-root-op outside-seam in-seam +Via_undoc_F30FA6F0_32, Undoc, Unknown, Unknown, legacy, F3, 0F, A6F0, a32 F3 0F A6 F0, UNDOC, 16 32 64 cpl0 cpl1 cpl2 cpl3 a32 save-restore intel16 intel32 intel64 amd16 amd32 amd64 rm pm v86 cm lm outside-smm in-smm outside-sgx in-sgx1 in-sgx2 outside-vmx-op in-vmx-root-op in-vmx-non-root-op outside-seam in-seam +Via_undoc_F30FA6F0_64, Undoc, Unknown, Unknown, legacy, F3, 0F, A6F0, a64 F3 0F A6 F0, UNDOC, 64 cpl0 cpl1 cpl2 cpl3 a64 save-restore intel64 amd64 lm outside-smm in-smm outside-sgx in-sgx1 in-sgx2 outside-vmx-op in-vmx-root-op in-vmx-non-root-op outside-seam in-seam +Via_undoc_F30FA6F8_16, Undoc, Unknown, Unknown, legacy, F3, 0F, A6F8, a16 F3 0F A6 F8, UNDOC, 16 32 cpl0 cpl1 cpl2 cpl3 a16 save-restore intel16 intel32 amd16 amd32 rm pm v86 cm outside-smm in-smm outside-sgx in-sgx1 in-sgx2 outside-vmx-op in-vmx-root-op in-vmx-non-root-op outside-seam in-seam +Via_undoc_F30FA6F8_32, Undoc, Unknown, Unknown, legacy, F3, 0F, A6F8, a32 F3 0F A6 F8, UNDOC, 16 32 64 cpl0 cpl1 cpl2 cpl3 a32 save-restore intel16 intel32 intel64 amd16 amd32 amd64 rm pm v86 cm lm outside-smm in-smm outside-sgx in-sgx1 in-sgx2 outside-vmx-op in-vmx-root-op in-vmx-non-root-op outside-seam in-seam +Via_undoc_F30FA6F8_64, Undoc, Unknown, Unknown, legacy, F3, 0F, A6F8, a64 F3 0F A6 F8, UNDOC, 64 cpl0 cpl1 cpl2 cpl3 a64 save-restore intel64 amd64 lm outside-smm in-smm outside-sgx in-sgx1 in-sgx2 outside-vmx-op in-vmx-root-op in-vmx-non-root-op outside-seam in-seam +Xsha512_16, Xsha512, Unknown, Unknown, legacy, F3, 0F, A6E0, a16 F3 0F A6 E0, XSHA512, 16 32 cpl0 cpl1 cpl2 cpl3 a16 intel16 intel32 amd16 amd32 rm pm v86 cm outside-smm in-smm outside-sgx in-sgx1 in-sgx2 outside-vmx-op in-vmx-root-op in-vmx-non-root-op outside-seam in-seam +Xsha512_32, Xsha512, Unknown, Unknown, legacy, F3, 0F, A6E0, a32 F3 0F A6 E0, XSHA512, 16 32 64 cpl0 cpl1 cpl2 cpl3 a32 intel16 intel32 intel64 amd16 amd32 amd64 rm pm v86 cm lm outside-smm in-smm outside-sgx in-sgx1 in-sgx2 outside-vmx-op in-vmx-root-op in-vmx-non-root-op outside-seam in-seam +Xsha512_64, Xsha512, Unknown, Unknown, legacy, F3, 0F, A6E0, a64 F3 0F A6 E0, XSHA512, 64 cpl0 cpl1 cpl2 cpl3 a64 intel64 amd64 lm outside-smm in-smm outside-sgx in-sgx1 in-sgx2 outside-vmx-op in-vmx-root-op in-vmx-non-root-op outside-seam in-seam +Xstore2_16, Xstore2, Unknown, Unknown, legacy, F3, 0F, A7F8, a16 F3 0F A7 F8, XSTORE2, 16 32 cpl0 cpl1 cpl2 cpl3 a16 intel16 intel32 amd16 amd32 rm pm v86 cm outside-smm in-smm outside-sgx in-sgx1 in-sgx2 outside-vmx-op in-vmx-root-op in-vmx-non-root-op outside-seam in-seam +Xstore2_32, Xstore2, Unknown, Unknown, legacy, F3, 0F, A7F8, a32 F3 0F A7 F8, XSTORE2, 16 32 64 cpl0 cpl1 cpl2 cpl3 a32 intel16 intel32 intel64 amd16 amd32 amd64 rm pm v86 cm lm outside-smm in-smm outside-sgx in-sgx1 in-sgx2 outside-vmx-op in-vmx-root-op in-vmx-non-root-op outside-seam in-seam +Xstore2_64, Xstore2, Unknown, Unknown, legacy, F3, 0F, A7F8, a64 F3 0F A7 F8, XSTORE2, 64 cpl0 cpl1 cpl2 cpl3 a64 intel64 amd64 lm outside-smm in-smm outside-sgx in-sgx1 in-sgx2 outside-vmx-op in-vmx-root-op in-vmx-non-root-op outside-seam in-seam diff --git a/src/UnitTests/Intel/Formatter/Fast/Test16_Default.txt b/src/UnitTests/Intel/Formatter/Fast/Test16_Default.txt index f3757f58f..2731c1ea6 100644 --- a/src/UnitTests/Intel/Formatter/Fast/Test16_Default.txt +++ b/src/UnitTests/Intel/Formatter/Fast/Test16_Default.txt @@ -518,3 +518,11 @@ pvalidate serialize xsusldtrk xresldtrk +rep undoc +rep undoc +rep undoc +rep undoc +rep xsha512 +rep xsha512 +rep xstore2 +rep xstore2 diff --git a/src/UnitTests/Intel/Formatter/Fast/Test16_Inverted.txt b/src/UnitTests/Intel/Formatter/Fast/Test16_Inverted.txt index cc2c765f9..193dc44d6 100644 --- a/src/UnitTests/Intel/Formatter/Fast/Test16_Inverted.txt +++ b/src/UnitTests/Intel/Formatter/Fast/Test16_Inverted.txt @@ -518,3 +518,11 @@ pvalidate serialize xsusldtrk xresldtrk +rep undoc +rep undoc +rep undoc +rep undoc +rep xsha512 +rep xsha512 +rep xstore2 +rep xstore2 diff --git a/src/UnitTests/Intel/Formatter/Fast/Test32_Default.txt b/src/UnitTests/Intel/Formatter/Fast/Test32_Default.txt index 2efb7dbf8..1aaf4ac9b 100644 --- a/src/UnitTests/Intel/Formatter/Fast/Test32_Default.txt +++ b/src/UnitTests/Intel/Formatter/Fast/Test32_Default.txt @@ -729,3 +729,11 @@ rep ccs_hash rep ccs_hash rep ccs_encrypt rep ccs_encrypt +rep undoc +rep undoc +rep undoc +rep undoc +rep xsha512 +rep xsha512 +rep xstore2 +rep xstore2 diff --git a/src/UnitTests/Intel/Formatter/Fast/Test32_Inverted.txt b/src/UnitTests/Intel/Formatter/Fast/Test32_Inverted.txt index f4659c222..9ca15ff01 100644 --- a/src/UnitTests/Intel/Formatter/Fast/Test32_Inverted.txt +++ b/src/UnitTests/Intel/Formatter/Fast/Test32_Inverted.txt @@ -729,3 +729,11 @@ rep ccs_hash rep ccs_hash rep ccs_encrypt rep ccs_encrypt +rep undoc +rep undoc +rep undoc +rep undoc +rep xsha512 +rep xsha512 +rep xstore2 +rep xstore2 diff --git a/src/UnitTests/Intel/Formatter/Fast/Test64_Default.txt b/src/UnitTests/Intel/Formatter/Fast/Test64_Default.txt index 9f253c248..d35e00855 100644 --- a/src/UnitTests/Intel/Formatter/Fast/Test64_Default.txt +++ b/src/UnitTests/Intel/Formatter/Fast/Test64_Default.txt @@ -13005,3 +13005,11 @@ vpsubrsetbd zmm2,k6,zmm19{bbbb} vpsubrsetbd zmm2,k6,zmm27{cccc} vpsubrsetbd zmm2,k6,zmm3{dddd} vpsubrsetbd zmm2,k6,zmm3 +rep undoc +rep undoc +rep undoc +rep undoc +rep xsha512 +rep xsha512 +rep xstore2 +rep xstore2 diff --git a/src/UnitTests/Intel/Formatter/Fast/Test64_Inverted.txt b/src/UnitTests/Intel/Formatter/Fast/Test64_Inverted.txt index 6032b042a..0fd130c0c 100644 --- a/src/UnitTests/Intel/Formatter/Fast/Test64_Inverted.txt +++ b/src/UnitTests/Intel/Formatter/Fast/Test64_Inverted.txt @@ -13005,3 +13005,11 @@ vpsubrsetbd zmm2, k6, zmm19{bbbb} vpsubrsetbd zmm2, k6, zmm27{cccc} vpsubrsetbd zmm2, k6, zmm3{dddd} vpsubrsetbd zmm2, k6, zmm3 +rep undoc +rep undoc +rep undoc +rep undoc +rep xsha512 +rep xsha512 +rep xstore2 +rep xstore2 diff --git a/src/UnitTests/Intel/Formatter/Gas/OptionsResult.txt b/src/UnitTests/Intel/Formatter/Gas/OptionsResult.txt index 3306a0e07..cb5fdbc6f 100644 --- a/src/UnitTests/Intel/Formatter/Gas/OptionsResult.txt +++ b/src/UnitTests/Intel/Formatter/Gas/OptionsResult.txt @@ -2068,6 +2068,10 @@ rep xcryptcfb rep xcryptofb rep ccs_hash rep ccs_encrypt +rep undoc +rep undoc +rep xsha512 +rep xstore2 repne insb %dx,(%rdi) repne insw %dx,(%rdi) @@ -2128,6 +2132,10 @@ rep xcryptcfb rep xcryptofb rep ccs_hash rep ccs_encrypt +rep undoc +rep undoc +rep xsha512 +rep xstore2 repne insb %dx,(%edi) repne insw %dx,(%edi) @@ -2183,6 +2191,10 @@ rep xcryptcfb rep xcryptofb rep ccs_hash rep ccs_encrypt +rep undoc +rep undoc +rep xsha512 +rep xstore2 repne insb %dx,(%di) repne insw %dx,(%di) @@ -2243,6 +2255,10 @@ rep xcryptcfb rep xcryptofb rep ccs_hash rep ccs_encrypt +rep undoc +rep undoc +rep xsha512 +rep xstore2 repne insb %dx,(%rdi) repne insw %dx,(%rdi) @@ -2303,6 +2319,10 @@ rep xcryptcfb rep xcryptofb rep ccs_hash rep ccs_encrypt +rep undoc +rep undoc +rep xsha512 +rep xstore2 repne insb %dx,(%edi) repne insw %dx,(%edi) @@ -2358,6 +2378,10 @@ rep xcryptcfb rep xcryptofb rep ccs_hash rep ccs_encrypt +rep undoc +rep undoc +rep xsha512 +rep xstore2 repne insb %dx,(%di) repne insw %dx,(%di) @@ -2418,6 +2442,10 @@ rep xcryptcfb rep xcryptofb rep ccs_hash rep ccs_encrypt +rep undoc +rep undoc +rep xsha512 +rep xstore2 repne insb %dx,(%rdi) repne insw %dx,(%rdi) @@ -2478,6 +2506,10 @@ rep xcryptcfb rep xcryptofb rep ccs_hash rep ccs_encrypt +rep undoc +rep undoc +rep xsha512 +rep xstore2 repne insb %dx,(%edi) repne insw %dx,(%edi) @@ -2533,6 +2565,10 @@ rep xcryptcfb rep xcryptofb rep ccs_hash rep ccs_encrypt +rep undoc +rep undoc +rep xsha512 +rep xstore2 repne insb %dx,(%di) repne insw %dx,(%di) @@ -2593,6 +2629,10 @@ rep xcryptcfb rep xcryptofb rep ccs_hash rep ccs_encrypt +rep undoc +rep undoc +rep xsha512 +rep xstore2 repnz insb %dx,(%rdi) repnz insw %dx,(%rdi) @@ -2653,6 +2693,10 @@ rep xcryptcfb rep xcryptofb rep ccs_hash rep ccs_encrypt +rep undoc +rep undoc +rep xsha512 +rep xstore2 repnz insb %dx,(%edi) repnz insw %dx,(%edi) @@ -2708,6 +2752,10 @@ rep xcryptcfb rep xcryptofb rep ccs_hash rep ccs_encrypt +rep undoc +rep undoc +rep xsha512 +rep xstore2 repnz insb %dx,(%di) repnz insw %dx,(%di) diff --git a/src/UnitTests/Intel/Formatter/Gas/Test16_ForceSuffix.txt b/src/UnitTests/Intel/Formatter/Gas/Test16_ForceSuffix.txt index 7754ec4f4..68e14c03d 100644 --- a/src/UnitTests/Intel/Formatter/Gas/Test16_ForceSuffix.txt +++ b/src/UnitTests/Intel/Formatter/Gas/Test16_ForceSuffix.txt @@ -518,3 +518,11 @@ addr32 pvalidate serialize xsusldtrk xresldtrk +rep undoc +addr32 rep undoc +rep undoc +addr32 rep undoc +rep xsha512 +addr32 rep xsha512 +rep xstore2 +addr32 rep xstore2 diff --git a/src/UnitTests/Intel/Formatter/Gas/Test16_NoSuffix.txt b/src/UnitTests/Intel/Formatter/Gas/Test16_NoSuffix.txt index 0e82f48d7..6a15f6ea0 100644 --- a/src/UnitTests/Intel/Formatter/Gas/Test16_NoSuffix.txt +++ b/src/UnitTests/Intel/Formatter/Gas/Test16_NoSuffix.txt @@ -518,3 +518,11 @@ addr32 pvalidate serialize xsusldtrk xresldtrk +rep undoc +addr32 rep undoc +rep undoc +addr32 rep undoc +rep xsha512 +addr32 rep xsha512 +rep xstore2 +addr32 rep xstore2 diff --git a/src/UnitTests/Intel/Formatter/Gas/Test32_ForceSuffix.txt b/src/UnitTests/Intel/Formatter/Gas/Test32_ForceSuffix.txt index b114a472d..11bd19a61 100644 --- a/src/UnitTests/Intel/Formatter/Gas/Test32_ForceSuffix.txt +++ b/src/UnitTests/Intel/Formatter/Gas/Test32_ForceSuffix.txt @@ -729,3 +729,11 @@ rep ccs_hash addr16 rep ccs_hash rep ccs_encrypt addr16 rep ccs_encrypt +addr16 rep undoc +rep undoc +addr16 rep undoc +rep undoc +addr16 rep xsha512 +rep xsha512 +addr16 rep xstore2 +rep xstore2 diff --git a/src/UnitTests/Intel/Formatter/Gas/Test32_NoSuffix.txt b/src/UnitTests/Intel/Formatter/Gas/Test32_NoSuffix.txt index dc0078c80..345d72149 100644 --- a/src/UnitTests/Intel/Formatter/Gas/Test32_NoSuffix.txt +++ b/src/UnitTests/Intel/Formatter/Gas/Test32_NoSuffix.txt @@ -729,3 +729,11 @@ rep ccs_hash addr16 rep ccs_hash rep ccs_encrypt addr16 rep ccs_encrypt +addr16 rep undoc +rep undoc +addr16 rep undoc +rep undoc +addr16 rep xsha512 +rep xsha512 +addr16 rep xstore2 +rep xstore2 diff --git a/src/UnitTests/Intel/Formatter/Gas/Test64_ForceSuffix.txt b/src/UnitTests/Intel/Formatter/Gas/Test64_ForceSuffix.txt index 4c7828245..24253acd9 100644 --- a/src/UnitTests/Intel/Formatter/Gas/Test64_ForceSuffix.txt +++ b/src/UnitTests/Intel/Formatter/Gas/Test64_ForceSuffix.txt @@ -13005,3 +13005,11 @@ vpsubrsetbd zmm19{bbbb}, k6, zmm2 vpsubrsetbd zmm27{cccc}, k6, zmm2 vpsubrsetbd zmm3{dddd}, k6, zmm2 vpsubrsetbd zmm3, k6, zmm2 +addr32 rep undoc +rep undoc +addr32 rep undoc +rep undoc +addr32 rep xsha512 +rep xsha512 +addr32 rep xstore2 +rep xstore2 diff --git a/src/UnitTests/Intel/Formatter/Gas/Test64_NoSuffix.txt b/src/UnitTests/Intel/Formatter/Gas/Test64_NoSuffix.txt index e050f6cc2..956dec243 100644 --- a/src/UnitTests/Intel/Formatter/Gas/Test64_NoSuffix.txt +++ b/src/UnitTests/Intel/Formatter/Gas/Test64_NoSuffix.txt @@ -13005,3 +13005,11 @@ vpsubrsetbd %zmm19{bbbb},%k6,%zmm2 vpsubrsetbd %zmm27{cccc},%k6,%zmm2 vpsubrsetbd %zmm3{dddd},%k6,%zmm2 vpsubrsetbd %zmm3,%k6,%zmm2 +addr32 rep undoc +rep undoc +addr32 rep undoc +rep undoc +addr32 rep xsha512 +rep xsha512 +addr32 rep xstore2 +rep xstore2 diff --git a/src/UnitTests/Intel/Formatter/InstructionInfos16.txt b/src/UnitTests/Intel/Formatter/InstructionInfos16.txt index 75b9ae1f4..fdccdaee3 100644 --- a/src/UnitTests/Intel/Formatter/InstructionInfos16.txt +++ b/src/UnitTests/Intel/Formatter/InstructionInfos16.txt @@ -518,3 +518,11 @@ F2 0F 01 FF, Pvalidatew 0F 01 E8, Serialize F2 0F 01 E8, Xsusldtrk F2 0F 01 E9, Xresldtrk +F3 0FA6 F0, Via_undoc_F30FA6F0_16 +67 F3 0FA6 F0, Via_undoc_F30FA6F0_32 +F3 0FA6 F8, Via_undoc_F30FA6F8_16 +67 F3 0FA6 F8, Via_undoc_F30FA6F8_32 +F3 0FA6 E0, Xsha512_16 +67 F3 0FA6 E0, Xsha512_32 +F3 0FA7 F8, Xstore2_16 +67 F3 0FA7 F8, Xstore2_32 diff --git a/src/UnitTests/Intel/Formatter/InstructionInfos32.txt b/src/UnitTests/Intel/Formatter/InstructionInfos32.txt index ba5d7b29d..bb6c497f2 100644 --- a/src/UnitTests/Intel/Formatter/InstructionInfos32.txt +++ b/src/UnitTests/Intel/Formatter/InstructionInfos32.txt @@ -644,7 +644,7 @@ F2 0F38F8 18, Enqcmd_r32_m512 64 67 0F01 FC, Clzerow 64 67 F3 0FAE F5, Umonitor_r16 F3 0FA6 C0, Montmul_32 -67 F3 0FA6 C0, Montmul_16 +67 F3 0FA6 C0, Montmul_16, NoInvalidCheck F3 0FA6 C8, Xsha1_32 67 F3 0FA6 C8, Xsha1_16 F3 0FA6 D0, Xsha256_32 @@ -729,3 +729,11 @@ F3 0FA6 E8, Ccs_hash_32 67 F3 0FA6 E8, Ccs_hash_16 F3 0FA7 F0, Ccs_encrypt_32 67 F3 0FA7 F0, Ccs_encrypt_16 +67 F3 0FA6 F0, Via_undoc_F30FA6F0_16 +F3 0FA6 F0, Via_undoc_F30FA6F0_32 +67 F3 0FA6 F8, Via_undoc_F30FA6F8_16 +F3 0FA6 F8, Via_undoc_F30FA6F8_32 +67 F3 0FA6 E0, Xsha512_16 +F3 0FA6 E0, Xsha512_32 +67 F3 0FA7 F8, Xstore2_16 +F3 0FA7 F8, Xstore2_32 diff --git a/src/UnitTests/Intel/Formatter/InstructionInfos64.txt b/src/UnitTests/Intel/Formatter/InstructionInfos64.txt index e2a6e6f01..c217e5684 100644 --- a/src/UnitTests/Intel/Formatter/InstructionInfos64.txt +++ b/src/UnitTests/Intel/Formatter/InstructionInfos64.txt @@ -8260,7 +8260,7 @@ C4E3CD CF 10 A5, VEX_Vgf2p8affineinvqb_ymm_ymm_ymmm256_imm8 64 0F01 FC, Clzeroq 64 67 F3 0FAE F5, Umonitor_r32 64 F3 0FAE F5, Umonitor_r64 -F3 0FA6 C0, Montmul_64 +F3 0FA6 C0, Montmul_64, NoInvalidCheck 67 F3 0FA6 C0, Montmul_32 F3 0FA6 C8, Xsha1_64 67 F3 0FA6 C8, Xsha1_32 @@ -13005,3 +13005,11 @@ C4E379 3E D3 A5, VEX_KNC_Kextract_kr_r64_imm8, KNC 62 924968 6F D3, MVEX_Vpsubrsetbd_zmm_k1_kr_zmmmt, KNC 62 F24978 6F D3, MVEX_Vpsubrsetbd_zmm_k1_kr_zmmmt, KNC 62 F24988 6F D3, MVEX_Vpsubrsetbd_zmm_k1_kr_zmmmt, KNC +67 F3 0FA6 F0, Via_undoc_F30FA6F0_32 +F3 0FA6 F0, Via_undoc_F30FA6F0_64 +67 F3 0FA6 F8, Via_undoc_F30FA6F8_32 +F3 0FA6 F8, Via_undoc_F30FA6F8_64 +67 F3 0FA6 E0, Xsha512_32 +F3 0FA6 E0, Xsha512_64 +67 F3 0FA7 F8, Xstore2_32 +F3 0FA7 F8, Xstore2_64 diff --git a/src/UnitTests/Intel/Formatter/Intel/OptionsResult.txt b/src/UnitTests/Intel/Formatter/Intel/OptionsResult.txt index 2e577be4d..572ddabe2 100644 --- a/src/UnitTests/Intel/Formatter/Intel/OptionsResult.txt +++ b/src/UnitTests/Intel/Formatter/Intel/OptionsResult.txt @@ -2068,6 +2068,10 @@ rep xcryptcfb rep xcryptofb rep ccs_hash rep ccs_encrypt +rep undoc +rep undoc +rep xsha512 +rep xstore2 repne insb [rdi],dx repne insw [rdi],dx @@ -2128,6 +2132,10 @@ rep xcryptcfb rep xcryptofb rep ccs_hash rep ccs_encrypt +rep undoc +rep undoc +rep xsha512 +rep xstore2 repne insb [edi],dx repne insw [edi],dx @@ -2183,6 +2191,10 @@ rep xcryptcfb rep xcryptofb rep ccs_hash rep ccs_encrypt +rep undoc +rep undoc +rep xsha512 +rep xstore2 repne insb [di],dx repne insw [di],dx @@ -2243,6 +2255,10 @@ rep xcryptcfb rep xcryptofb rep ccs_hash rep ccs_encrypt +rep undoc +rep undoc +rep xsha512 +rep xstore2 repne insb [rdi],dx repne insw [rdi],dx @@ -2303,6 +2319,10 @@ rep xcryptcfb rep xcryptofb rep ccs_hash rep ccs_encrypt +rep undoc +rep undoc +rep xsha512 +rep xstore2 repne insb [edi],dx repne insw [edi],dx @@ -2358,6 +2378,10 @@ rep xcryptcfb rep xcryptofb rep ccs_hash rep ccs_encrypt +rep undoc +rep undoc +rep xsha512 +rep xstore2 repne insb [di],dx repne insw [di],dx @@ -2418,6 +2442,10 @@ rep xcryptcfb rep xcryptofb rep ccs_hash rep ccs_encrypt +rep undoc +rep undoc +rep xsha512 +rep xstore2 repne insb [rdi],dx repne insw [rdi],dx @@ -2478,6 +2506,10 @@ rep xcryptcfb rep xcryptofb rep ccs_hash rep ccs_encrypt +rep undoc +rep undoc +rep xsha512 +rep xstore2 repne insb [edi],dx repne insw [edi],dx @@ -2533,6 +2565,10 @@ rep xcryptcfb rep xcryptofb rep ccs_hash rep ccs_encrypt +rep undoc +rep undoc +rep xsha512 +rep xstore2 repne insb [di],dx repne insw [di],dx @@ -2593,6 +2629,10 @@ rep xcryptcfb rep xcryptofb rep ccs_hash rep ccs_encrypt +rep undoc +rep undoc +rep xsha512 +rep xstore2 repnz insb [rdi],dx repnz insw [rdi],dx @@ -2653,6 +2693,10 @@ rep xcryptcfb rep xcryptofb rep ccs_hash rep ccs_encrypt +rep undoc +rep undoc +rep xsha512 +rep xstore2 repnz insb [edi],dx repnz insw [edi],dx @@ -2708,6 +2752,10 @@ rep xcryptcfb rep xcryptofb rep ccs_hash rep ccs_encrypt +rep undoc +rep undoc +rep xsha512 +rep xstore2 repnz insb [di],dx repnz insw [di],dx diff --git a/src/UnitTests/Intel/Formatter/Intel/Test16_MemAlways.txt b/src/UnitTests/Intel/Formatter/Intel/Test16_MemAlways.txt index 09bbebf9b..19209a15e 100644 --- a/src/UnitTests/Intel/Formatter/Intel/Test16_MemAlways.txt +++ b/src/UnitTests/Intel/Formatter/Intel/Test16_MemAlways.txt @@ -518,3 +518,11 @@ pvalidate eax serialize xsusldtrk xresldtrk +rep undoc +addr32 rep undoc +rep undoc +addr32 rep undoc +rep xsha512 +addr32 rep xsha512 +rep xstore2 +addr32 rep xstore2 diff --git a/src/UnitTests/Intel/Formatter/Intel/Test16_MemDefault.txt b/src/UnitTests/Intel/Formatter/Intel/Test16_MemDefault.txt index 1bc92e751..0111c754f 100644 --- a/src/UnitTests/Intel/Formatter/Intel/Test16_MemDefault.txt +++ b/src/UnitTests/Intel/Formatter/Intel/Test16_MemDefault.txt @@ -518,3 +518,11 @@ pvalidate eax serialize xsusldtrk xresldtrk +rep undoc +addr32 rep undoc +rep undoc +addr32 rep undoc +rep xsha512 +addr32 rep xsha512 +rep xstore2 +addr32 rep xstore2 diff --git a/src/UnitTests/Intel/Formatter/Intel/Test16_MemMinimum.txt b/src/UnitTests/Intel/Formatter/Intel/Test16_MemMinimum.txt index 697caa234..876f0dcbd 100644 --- a/src/UnitTests/Intel/Formatter/Intel/Test16_MemMinimum.txt +++ b/src/UnitTests/Intel/Formatter/Intel/Test16_MemMinimum.txt @@ -518,3 +518,11 @@ pvalidate eax serialize xsusldtrk xresldtrk +rep undoc +addr32 rep undoc +rep undoc +addr32 rep undoc +rep xsha512 +addr32 rep xsha512 +rep xstore2 +addr32 rep xstore2 diff --git a/src/UnitTests/Intel/Formatter/Intel/Test32_MemAlways.txt b/src/UnitTests/Intel/Formatter/Intel/Test32_MemAlways.txt index 0785795e2..c9bea73d0 100644 --- a/src/UnitTests/Intel/Formatter/Intel/Test32_MemAlways.txt +++ b/src/UnitTests/Intel/Formatter/Intel/Test32_MemAlways.txt @@ -729,3 +729,11 @@ rep ccs_hash addr16 rep ccs_hash rep ccs_encrypt addr16 rep ccs_encrypt +addr16 rep undoc +rep undoc +addr16 rep undoc +rep undoc +addr16 rep xsha512 +rep xsha512 +addr16 rep xstore2 +rep xstore2 diff --git a/src/UnitTests/Intel/Formatter/Intel/Test32_MemDefault.txt b/src/UnitTests/Intel/Formatter/Intel/Test32_MemDefault.txt index 1b01f0b4f..92a5562cc 100644 --- a/src/UnitTests/Intel/Formatter/Intel/Test32_MemDefault.txt +++ b/src/UnitTests/Intel/Formatter/Intel/Test32_MemDefault.txt @@ -729,3 +729,11 @@ rep ccs_hash addr16 rep ccs_hash rep ccs_encrypt addr16 rep ccs_encrypt +addr16 rep undoc +rep undoc +addr16 rep undoc +rep undoc +addr16 rep xsha512 +rep xsha512 +addr16 rep xstore2 +rep xstore2 diff --git a/src/UnitTests/Intel/Formatter/Intel/Test32_MemMinimum.txt b/src/UnitTests/Intel/Formatter/Intel/Test32_MemMinimum.txt index 010e3a5a9..0c32898dc 100644 --- a/src/UnitTests/Intel/Formatter/Intel/Test32_MemMinimum.txt +++ b/src/UnitTests/Intel/Formatter/Intel/Test32_MemMinimum.txt @@ -729,3 +729,11 @@ rep ccs_hash addr16 rep ccs_hash rep ccs_encrypt addr16 rep ccs_encrypt +addr16 rep undoc +rep undoc +addr16 rep undoc +rep undoc +addr16 rep xsha512 +rep xsha512 +addr16 rep xstore2 +rep xstore2 diff --git a/src/UnitTests/Intel/Formatter/Intel/Test64_MemAlways.txt b/src/UnitTests/Intel/Formatter/Intel/Test64_MemAlways.txt index cd16c7e8b..cb08cdc96 100644 --- a/src/UnitTests/Intel/Formatter/Intel/Test64_MemAlways.txt +++ b/src/UnitTests/Intel/Formatter/Intel/Test64_MemAlways.txt @@ -13005,3 +13005,11 @@ vpsubrsetbd zmm2, k6, zmm19{bbbb} vpsubrsetbd zmm2, k6, zmm27{cccc} vpsubrsetbd zmm2, k6, zmm3{dddd} vpsubrsetbd zmm2, k6, zmm3 +addr32 rep undoc +rep undoc +addr32 rep undoc +rep undoc +addr32 rep xsha512 +rep xsha512 +addr32 rep xstore2 +rep xstore2 diff --git a/src/UnitTests/Intel/Formatter/Intel/Test64_MemDefault.txt b/src/UnitTests/Intel/Formatter/Intel/Test64_MemDefault.txt index 698235fc4..d5ba80d0b 100644 --- a/src/UnitTests/Intel/Formatter/Intel/Test64_MemDefault.txt +++ b/src/UnitTests/Intel/Formatter/Intel/Test64_MemDefault.txt @@ -13005,3 +13005,11 @@ vpsubrsetbd zmm2,k6,zmm19{bbbb} vpsubrsetbd zmm2,k6,zmm27{cccc} vpsubrsetbd zmm2,k6,zmm3{dddd} vpsubrsetbd zmm2,k6,zmm3 +addr32 rep undoc +rep undoc +addr32 rep undoc +rep undoc +addr32 rep xsha512 +rep xsha512 +addr32 rep xstore2 +rep xstore2 diff --git a/src/UnitTests/Intel/Formatter/Intel/Test64_MemMinimum.txt b/src/UnitTests/Intel/Formatter/Intel/Test64_MemMinimum.txt index 78e0ed723..3f6db4086 100644 --- a/src/UnitTests/Intel/Formatter/Intel/Test64_MemMinimum.txt +++ b/src/UnitTests/Intel/Formatter/Intel/Test64_MemMinimum.txt @@ -13005,3 +13005,11 @@ vpsubrsetbd zmm2, k6, zmm19{bbbb} vpsubrsetbd zmm2, k6, zmm27{cccc} vpsubrsetbd zmm2, k6, zmm3{dddd} vpsubrsetbd zmm2, k6, zmm3 +addr32 rep undoc +rep undoc +addr32 rep undoc +rep undoc +addr32 rep xsha512 +rep xsha512 +addr32 rep xstore2 +rep xstore2 diff --git a/src/UnitTests/Intel/Formatter/Masm/OptionsResult.txt b/src/UnitTests/Intel/Formatter/Masm/OptionsResult.txt index abe47e8fa..37c9e1358 100644 --- a/src/UnitTests/Intel/Formatter/Masm/OptionsResult.txt +++ b/src/UnitTests/Intel/Formatter/Masm/OptionsResult.txt @@ -2068,6 +2068,10 @@ rep xcryptcfb rep xcryptofb rep ccs_hash rep ccs_encrypt +rep undoc +rep undoc +rep xsha512 +rep xstore2 repne insb repne insw @@ -2128,6 +2132,10 @@ rep xcryptcfb rep xcryptofb rep ccs_hash rep ccs_encrypt +rep undoc +rep undoc +rep xsha512 +rep xstore2 repne insb repne insw @@ -2183,6 +2191,10 @@ rep xcryptcfb rep xcryptofb rep ccs_hash rep ccs_encrypt +rep undoc +rep undoc +rep xsha512 +rep xstore2 repne insb repne insw @@ -2243,6 +2255,10 @@ rep xcryptcfb rep xcryptofb rep ccs_hash rep ccs_encrypt +rep undoc +rep undoc +rep xsha512 +rep xstore2 repne insb repne insw @@ -2303,6 +2319,10 @@ rep xcryptcfb rep xcryptofb rep ccs_hash rep ccs_encrypt +rep undoc +rep undoc +rep xsha512 +rep xstore2 repne insb repne insw @@ -2358,6 +2378,10 @@ rep xcryptcfb rep xcryptofb rep ccs_hash rep ccs_encrypt +rep undoc +rep undoc +rep xsha512 +rep xstore2 repne insb repne insw @@ -2418,6 +2442,10 @@ rep xcryptcfb rep xcryptofb rep ccs_hash rep ccs_encrypt +rep undoc +rep undoc +rep xsha512 +rep xstore2 repne insb repne insw @@ -2478,6 +2506,10 @@ rep xcryptcfb rep xcryptofb rep ccs_hash rep ccs_encrypt +rep undoc +rep undoc +rep xsha512 +rep xstore2 repne insb repne insw @@ -2533,6 +2565,10 @@ rep xcryptcfb rep xcryptofb rep ccs_hash rep ccs_encrypt +rep undoc +rep undoc +rep xsha512 +rep xstore2 repne insb repne insw @@ -2593,6 +2629,10 @@ rep xcryptcfb rep xcryptofb rep ccs_hash rep ccs_encrypt +rep undoc +rep undoc +rep xsha512 +rep xstore2 repnz insb repnz insw @@ -2653,6 +2693,10 @@ rep xcryptcfb rep xcryptofb rep ccs_hash rep ccs_encrypt +rep undoc +rep undoc +rep xsha512 +rep xstore2 repnz insb repnz insw @@ -2708,6 +2752,10 @@ rep xcryptcfb rep xcryptofb rep ccs_hash rep ccs_encrypt +rep undoc +rep undoc +rep xsha512 +rep xstore2 repnz insb repnz insw diff --git a/src/UnitTests/Intel/Formatter/Masm/Test16_MemAlways.txt b/src/UnitTests/Intel/Formatter/Masm/Test16_MemAlways.txt index 3b61bab15..9bcd76589 100644 --- a/src/UnitTests/Intel/Formatter/Masm/Test16_MemAlways.txt +++ b/src/UnitTests/Intel/Formatter/Masm/Test16_MemAlways.txt @@ -518,3 +518,11 @@ pvalidate serialize xsusldtrk xresldtrk +rep undoc +rep undoc +rep undoc +rep undoc +rep xsha512 +rep xsha512 +rep xstore2 +rep xstore2 diff --git a/src/UnitTests/Intel/Formatter/Masm/Test16_MemDefault.txt b/src/UnitTests/Intel/Formatter/Masm/Test16_MemDefault.txt index e6be4ea72..bca1bba77 100644 --- a/src/UnitTests/Intel/Formatter/Masm/Test16_MemDefault.txt +++ b/src/UnitTests/Intel/Formatter/Masm/Test16_MemDefault.txt @@ -518,3 +518,11 @@ pvalidate serialize xsusldtrk xresldtrk +rep undoc +rep undoc +rep undoc +rep undoc +rep xsha512 +rep xsha512 +rep xstore2 +rep xstore2 diff --git a/src/UnitTests/Intel/Formatter/Masm/Test16_MemMinimum.txt b/src/UnitTests/Intel/Formatter/Masm/Test16_MemMinimum.txt index f95a176e3..0e91714d5 100644 --- a/src/UnitTests/Intel/Formatter/Masm/Test16_MemMinimum.txt +++ b/src/UnitTests/Intel/Formatter/Masm/Test16_MemMinimum.txt @@ -518,3 +518,11 @@ pvalidate serialize xsusldtrk xresldtrk +rep undoc +rep undoc +rep undoc +rep undoc +rep xsha512 +rep xsha512 +rep xstore2 +rep xstore2 diff --git a/src/UnitTests/Intel/Formatter/Masm/Test32_MemAlways.txt b/src/UnitTests/Intel/Formatter/Masm/Test32_MemAlways.txt index 3a1582f40..622fec7e4 100644 --- a/src/UnitTests/Intel/Formatter/Masm/Test32_MemAlways.txt +++ b/src/UnitTests/Intel/Formatter/Masm/Test32_MemAlways.txt @@ -729,3 +729,11 @@ rep ccs_hash rep ccs_hash rep ccs_encrypt rep ccs_encrypt +rep undoc +rep undoc +rep undoc +rep undoc +rep xsha512 +rep xsha512 +rep xstore2 +rep xstore2 diff --git a/src/UnitTests/Intel/Formatter/Masm/Test32_MemDefault.txt b/src/UnitTests/Intel/Formatter/Masm/Test32_MemDefault.txt index dddfe2609..48025ba9e 100644 --- a/src/UnitTests/Intel/Formatter/Masm/Test32_MemDefault.txt +++ b/src/UnitTests/Intel/Formatter/Masm/Test32_MemDefault.txt @@ -729,3 +729,11 @@ rep ccs_hash rep ccs_hash rep ccs_encrypt rep ccs_encrypt +rep undoc +rep undoc +rep undoc +rep undoc +rep xsha512 +rep xsha512 +rep xstore2 +rep xstore2 diff --git a/src/UnitTests/Intel/Formatter/Masm/Test32_MemMinimum.txt b/src/UnitTests/Intel/Formatter/Masm/Test32_MemMinimum.txt index c733eebb3..e52113b17 100644 --- a/src/UnitTests/Intel/Formatter/Masm/Test32_MemMinimum.txt +++ b/src/UnitTests/Intel/Formatter/Masm/Test32_MemMinimum.txt @@ -729,3 +729,11 @@ rep ccs_hash rep ccs_hash rep ccs_encrypt rep ccs_encrypt +rep undoc +rep undoc +rep undoc +rep undoc +rep xsha512 +rep xsha512 +rep xstore2 +rep xstore2 diff --git a/src/UnitTests/Intel/Formatter/Masm/Test64_MemAlways.txt b/src/UnitTests/Intel/Formatter/Masm/Test64_MemAlways.txt index cdb1c1408..093fdf105 100644 --- a/src/UnitTests/Intel/Formatter/Masm/Test64_MemAlways.txt +++ b/src/UnitTests/Intel/Formatter/Masm/Test64_MemAlways.txt @@ -13005,3 +13005,11 @@ vpsubrsetbd zmm2, k6, zmm19{bbbb} vpsubrsetbd zmm2, k6, zmm27{cccc} vpsubrsetbd zmm2, k6, zmm3{dddd} vpsubrsetbd zmm2, k6, zmm3 +rep undoc +rep undoc +rep undoc +rep undoc +rep xsha512 +rep xsha512 +rep xstore2 +rep xstore2 diff --git a/src/UnitTests/Intel/Formatter/Masm/Test64_MemDefault.txt b/src/UnitTests/Intel/Formatter/Masm/Test64_MemDefault.txt index b3ef5840d..f6393ad25 100644 --- a/src/UnitTests/Intel/Formatter/Masm/Test64_MemDefault.txt +++ b/src/UnitTests/Intel/Formatter/Masm/Test64_MemDefault.txt @@ -13005,3 +13005,11 @@ vpsubrsetbd zmm2,k6,zmm19{bbbb} vpsubrsetbd zmm2,k6,zmm27{cccc} vpsubrsetbd zmm2,k6,zmm3{dddd} vpsubrsetbd zmm2,k6,zmm3 +rep undoc +rep undoc +rep undoc +rep undoc +rep xsha512 +rep xsha512 +rep xstore2 +rep xstore2 diff --git a/src/UnitTests/Intel/Formatter/Masm/Test64_MemMinimum.txt b/src/UnitTests/Intel/Formatter/Masm/Test64_MemMinimum.txt index 42d407a81..e25d6ffe1 100644 --- a/src/UnitTests/Intel/Formatter/Masm/Test64_MemMinimum.txt +++ b/src/UnitTests/Intel/Formatter/Masm/Test64_MemMinimum.txt @@ -13005,3 +13005,11 @@ vpsubrsetbd zmm2, k6, zmm19{bbbb} vpsubrsetbd zmm2, k6, zmm27{cccc} vpsubrsetbd zmm2, k6, zmm3{dddd} vpsubrsetbd zmm2, k6, zmm3 +rep undoc +rep undoc +rep undoc +rep undoc +rep xsha512 +rep xsha512 +rep xstore2 +rep xstore2 diff --git a/src/UnitTests/Intel/Formatter/Nasm/OptionsResult.txt b/src/UnitTests/Intel/Formatter/Nasm/OptionsResult.txt index 4c9786a35..fd3b4a789 100644 --- a/src/UnitTests/Intel/Formatter/Nasm/OptionsResult.txt +++ b/src/UnitTests/Intel/Formatter/Nasm/OptionsResult.txt @@ -2068,6 +2068,10 @@ rep xcryptcfb rep xcryptofb rep ccs_hash rep ccs_encrypt +rep undoc +rep undoc +rep xsha512 +rep xstore2 repne insb repne insw @@ -2128,6 +2132,10 @@ rep xcryptcfb rep xcryptofb rep ccs_hash rep ccs_encrypt +rep undoc +rep undoc +rep xsha512 +rep xstore2 repne insb repne insw @@ -2183,6 +2191,10 @@ rep xcryptcfb rep xcryptofb rep ccs_hash rep ccs_encrypt +rep undoc +rep undoc +rep xsha512 +rep xstore2 repne insb repne insw @@ -2243,6 +2255,10 @@ rep xcryptcfb rep xcryptofb rep ccs_hash rep ccs_encrypt +rep undoc +rep undoc +rep xsha512 +rep xstore2 repne insb repne insw @@ -2303,6 +2319,10 @@ rep xcryptcfb rep xcryptofb rep ccs_hash rep ccs_encrypt +rep undoc +rep undoc +rep xsha512 +rep xstore2 repne insb repne insw @@ -2358,6 +2378,10 @@ rep xcryptcfb rep xcryptofb rep ccs_hash rep ccs_encrypt +rep undoc +rep undoc +rep xsha512 +rep xstore2 repne insb repne insw @@ -2418,6 +2442,10 @@ rep xcryptcfb rep xcryptofb rep ccs_hash rep ccs_encrypt +rep undoc +rep undoc +rep xsha512 +rep xstore2 repne insb repne insw @@ -2478,6 +2506,10 @@ rep xcryptcfb rep xcryptofb rep ccs_hash rep ccs_encrypt +rep undoc +rep undoc +rep xsha512 +rep xstore2 repne insb repne insw @@ -2533,6 +2565,10 @@ rep xcryptcfb rep xcryptofb rep ccs_hash rep ccs_encrypt +rep undoc +rep undoc +rep xsha512 +rep xstore2 repne insb repne insw @@ -2593,6 +2629,10 @@ rep xcryptcfb rep xcryptofb rep ccs_hash rep ccs_encrypt +rep undoc +rep undoc +rep xsha512 +rep xstore2 repnz insb repnz insw @@ -2653,6 +2693,10 @@ rep xcryptcfb rep xcryptofb rep ccs_hash rep ccs_encrypt +rep undoc +rep undoc +rep xsha512 +rep xstore2 repnz insb repnz insw @@ -2708,6 +2752,10 @@ rep xcryptcfb rep xcryptofb rep ccs_hash rep ccs_encrypt +rep undoc +rep undoc +rep xsha512 +rep xstore2 repnz insb repnz insw diff --git a/src/UnitTests/Intel/Formatter/Nasm/Test16_MemAlways.txt b/src/UnitTests/Intel/Formatter/Nasm/Test16_MemAlways.txt index 15b649d1f..378f079aa 100644 --- a/src/UnitTests/Intel/Formatter/Nasm/Test16_MemAlways.txt +++ b/src/UnitTests/Intel/Formatter/Nasm/Test16_MemAlways.txt @@ -518,3 +518,11 @@ a32 pvalidate serialize xsusldtrk xresldtrk +rep undoc +a32 rep undoc +rep undoc +a32 rep undoc +rep xsha512 +a32 rep xsha512 +rep xstore2 +a32 rep xstore2 diff --git a/src/UnitTests/Intel/Formatter/Nasm/Test16_MemDefault.txt b/src/UnitTests/Intel/Formatter/Nasm/Test16_MemDefault.txt index 7bb3b4a45..afd335205 100644 --- a/src/UnitTests/Intel/Formatter/Nasm/Test16_MemDefault.txt +++ b/src/UnitTests/Intel/Formatter/Nasm/Test16_MemDefault.txt @@ -518,3 +518,11 @@ a32 pvalidate serialize xsusldtrk xresldtrk +rep undoc +a32 rep undoc +rep undoc +a32 rep undoc +rep xsha512 +a32 rep xsha512 +rep xstore2 +a32 rep xstore2 diff --git a/src/UnitTests/Intel/Formatter/Nasm/Test16_MemMinimum.txt b/src/UnitTests/Intel/Formatter/Nasm/Test16_MemMinimum.txt index cb1554e86..af8f44ebd 100644 --- a/src/UnitTests/Intel/Formatter/Nasm/Test16_MemMinimum.txt +++ b/src/UnitTests/Intel/Formatter/Nasm/Test16_MemMinimum.txt @@ -518,3 +518,11 @@ a32 pvalidate serialize xsusldtrk xresldtrk +rep undoc +a32 rep undoc +rep undoc +a32 rep undoc +rep xsha512 +a32 rep xsha512 +rep xstore2 +a32 rep xstore2 diff --git a/src/UnitTests/Intel/Formatter/Nasm/Test32_MemAlways.txt b/src/UnitTests/Intel/Formatter/Nasm/Test32_MemAlways.txt index dd6f66a23..ab01c1e84 100644 --- a/src/UnitTests/Intel/Formatter/Nasm/Test32_MemAlways.txt +++ b/src/UnitTests/Intel/Formatter/Nasm/Test32_MemAlways.txt @@ -729,3 +729,11 @@ rep ccs_hash a16 rep ccs_hash rep ccs_encrypt a16 rep ccs_encrypt +a16 rep undoc +rep undoc +a16 rep undoc +rep undoc +a16 rep xsha512 +rep xsha512 +a16 rep xstore2 +rep xstore2 diff --git a/src/UnitTests/Intel/Formatter/Nasm/Test32_MemDefault.txt b/src/UnitTests/Intel/Formatter/Nasm/Test32_MemDefault.txt index 83ac73c84..4125d8961 100644 --- a/src/UnitTests/Intel/Formatter/Nasm/Test32_MemDefault.txt +++ b/src/UnitTests/Intel/Formatter/Nasm/Test32_MemDefault.txt @@ -729,3 +729,11 @@ rep ccs_hash a16 rep ccs_hash rep ccs_encrypt a16 rep ccs_encrypt +a16 rep undoc +rep undoc +a16 rep undoc +rep undoc +a16 rep xsha512 +rep xsha512 +a16 rep xstore2 +rep xstore2 diff --git a/src/UnitTests/Intel/Formatter/Nasm/Test32_MemMinimum.txt b/src/UnitTests/Intel/Formatter/Nasm/Test32_MemMinimum.txt index d29706c02..82e969991 100644 --- a/src/UnitTests/Intel/Formatter/Nasm/Test32_MemMinimum.txt +++ b/src/UnitTests/Intel/Formatter/Nasm/Test32_MemMinimum.txt @@ -729,3 +729,11 @@ rep ccs_hash a16 rep ccs_hash rep ccs_encrypt a16 rep ccs_encrypt +a16 rep undoc +rep undoc +a16 rep undoc +rep undoc +a16 rep xsha512 +rep xsha512 +a16 rep xstore2 +rep xstore2 diff --git a/src/UnitTests/Intel/Formatter/Nasm/Test64_MemAlways.txt b/src/UnitTests/Intel/Formatter/Nasm/Test64_MemAlways.txt index af831324f..6a3883944 100644 --- a/src/UnitTests/Intel/Formatter/Nasm/Test64_MemAlways.txt +++ b/src/UnitTests/Intel/Formatter/Nasm/Test64_MemAlways.txt @@ -13005,3 +13005,11 @@ vpsubrsetbd zmm2, k6, zmm19{bbbb} vpsubrsetbd zmm2, k6, zmm27{cccc} vpsubrsetbd zmm2, k6, zmm3{dddd} vpsubrsetbd zmm2, k6, zmm3 +a32 rep undoc +rep undoc +a32 rep undoc +rep undoc +a32 rep xsha512 +rep xsha512 +a32 rep xstore2 +rep xstore2 diff --git a/src/UnitTests/Intel/Formatter/Nasm/Test64_MemDefault.txt b/src/UnitTests/Intel/Formatter/Nasm/Test64_MemDefault.txt index 02c8294aa..3a300bb79 100644 --- a/src/UnitTests/Intel/Formatter/Nasm/Test64_MemDefault.txt +++ b/src/UnitTests/Intel/Formatter/Nasm/Test64_MemDefault.txt @@ -13005,3 +13005,11 @@ vpsubrsetbd zmm2,k6,zmm19{bbbb} vpsubrsetbd zmm2,k6,zmm27{cccc} vpsubrsetbd zmm2,k6,zmm3{dddd} vpsubrsetbd zmm2,k6,zmm3 +a32 rep undoc +rep undoc +a32 rep undoc +rep undoc +a32 rep xsha512 +rep xsha512 +a32 rep xstore2 +rep xstore2 diff --git a/src/UnitTests/Intel/Formatter/Nasm/Test64_MemMinimum.txt b/src/UnitTests/Intel/Formatter/Nasm/Test64_MemMinimum.txt index e7b66c3a5..ec371c5b9 100644 --- a/src/UnitTests/Intel/Formatter/Nasm/Test64_MemMinimum.txt +++ b/src/UnitTests/Intel/Formatter/Nasm/Test64_MemMinimum.txt @@ -13005,3 +13005,11 @@ vpsubrsetbd zmm2, k6, zmm19{bbbb} vpsubrsetbd zmm2, k6, zmm27{cccc} vpsubrsetbd zmm2, k6, zmm3{dddd} vpsubrsetbd zmm2, k6, zmm3 +a32 rep undoc +rep undoc +a32 rep undoc +rep undoc +a32 rep xsha512 +rep xsha512 +a32 rep xstore2 +rep xstore2 diff --git a/src/UnitTests/Intel/Formatter/Options.txt b/src/UnitTests/Intel/Formatter/Options.txt index 9eaaa299c..c3967b97c 100644 --- a/src/UnitTests/Intel/Formatter/Options.txt +++ b/src/UnitTests/Intel/Formatter/Options.txt @@ -2057,7 +2057,7 @@ 64, F3 66 AF, Scasw_AX_m16, ShowUselessPrefixes=false 64, F3 AF, Scasd_EAX_m32, ShowUselessPrefixes=false 64, F3 48 AF, Scasq_RAX_m64, ShowUselessPrefixes=false -64, F3 0FA6 C0, Montmul_64, ShowUselessPrefixes=false +64, F3 0FA6 C0, Montmul_64, ShowUselessPrefixes=false DecoderOptions=NoInvalidCheck 64, F3 0FA6 C8, Xsha1_64, ShowUselessPrefixes=false 64, F3 0FA6 D0, Xsha256_64, ShowUselessPrefixes=false 64, F3 0FA7 C0, Xstore_64, ShowUselessPrefixes=false @@ -2068,6 +2068,10 @@ 64, F3 0FA7 E8, Xcryptofb_64, ShowUselessPrefixes=false 64, F3 0FA6 E8, Ccs_hash_64, ShowUselessPrefixes=false 64, F3 0FA7 F0, Ccs_encrypt_64, ShowUselessPrefixes=false +64, F3 0FA6 F0, Via_undoc_F30FA6F0_64, ShowUselessPrefixes=false +64, F3 0FA6 F8, Via_undoc_F30FA6F8_64, ShowUselessPrefixes=false +64, F3 0FA6 E0, Xsha512_64, ShowUselessPrefixes=false +64, F3 0FA7 F8, Xstore2_64, ShowUselessPrefixes=false 64, F2 6C, Insb_m8_DX, ShowUselessPrefixes=false 64, F2 66 6D, Insw_m16_DX, ShowUselessPrefixes=false @@ -2128,6 +2132,10 @@ 32, F3 0FA7 E8, Xcryptofb_32, ShowUselessPrefixes=false 32, F3 0FA6 E8, Ccs_hash_32, ShowUselessPrefixes=false 32, F3 0FA7 F0, Ccs_encrypt_32, ShowUselessPrefixes=false +32, F3 0FA6 F0, Via_undoc_F30FA6F0_32, ShowUselessPrefixes=false +32, F3 0FA6 F8, Via_undoc_F30FA6F8_32, ShowUselessPrefixes=false +32, F3 0FA6 E0, Xsha512_32, ShowUselessPrefixes=false +32, F3 0FA7 F8, Xstore2_32, ShowUselessPrefixes=false 32, F2 6C, Insb_m8_DX, ShowUselessPrefixes=false 32, F2 66 6D, Insw_m16_DX, ShowUselessPrefixes=false @@ -2172,7 +2180,7 @@ 16, F3 AE, Scasb_AL_m8, ShowUselessPrefixes=false 16, F3 AF, Scasw_AX_m16, ShowUselessPrefixes=false 16, F3 66 AF, Scasd_EAX_m32, ShowUselessPrefixes=false -16, F3 0FA6 C0, Montmul_16, ShowUselessPrefixes=false +16, F3 0FA6 C0, Montmul_16, ShowUselessPrefixes=false DecoderOptions=NoInvalidCheck 16, F3 0FA6 C8, Xsha1_16, ShowUselessPrefixes=false 16, F3 0FA6 D0, Xsha256_16, ShowUselessPrefixes=false 16, F3 0FA7 C0, Xstore_16, ShowUselessPrefixes=false @@ -2183,6 +2191,10 @@ 16, F3 0FA7 E8, Xcryptofb_16, ShowUselessPrefixes=false 16, F3 0FA6 E8, Ccs_hash_16, ShowUselessPrefixes=false 16, F3 0FA7 F0, Ccs_encrypt_16, ShowUselessPrefixes=false +16, F3 0FA6 F0, Via_undoc_F30FA6F0_16, ShowUselessPrefixes=false +16, F3 0FA6 F8, Via_undoc_F30FA6F8_16, ShowUselessPrefixes=false +16, F3 0FA6 E0, Xsha512_16, ShowUselessPrefixes=false +16, F3 0FA7 F8, Xstore2_16, ShowUselessPrefixes=false 16, F2 6C, Insb_m8_DX, ShowUselessPrefixes=false 16, F2 6D, Insw_m16_DX, ShowUselessPrefixes=false @@ -2232,7 +2244,7 @@ 64, F3 66 AF, Scasw_AX_m16, ShowUselessPrefixes=true 64, F3 AF, Scasd_EAX_m32, ShowUselessPrefixes=true 64, F3 48 AF, Scasq_RAX_m64, ShowUselessPrefixes=true -64, F3 0FA6 C0, Montmul_64, ShowUselessPrefixes=true +64, F3 0FA6 C0, Montmul_64, ShowUselessPrefixes=true DecoderOptions=NoInvalidCheck 64, F3 0FA6 C8, Xsha1_64, ShowUselessPrefixes=true 64, F3 0FA6 D0, Xsha256_64, ShowUselessPrefixes=true 64, F3 0FA7 C0, Xstore_64, ShowUselessPrefixes=true @@ -2243,6 +2255,10 @@ 64, F3 0FA7 E8, Xcryptofb_64, ShowUselessPrefixes=true 64, F3 0FA6 E8, Ccs_hash_64, ShowUselessPrefixes=true 64, F3 0FA7 F0, Ccs_encrypt_64, ShowUselessPrefixes=true +64, F3 0FA6 F0, Via_undoc_F30FA6F0_64, ShowUselessPrefixes=true +64, F3 0FA6 F8, Via_undoc_F30FA6F8_64, ShowUselessPrefixes=true +64, F3 0FA6 E0, Xsha512_64, ShowUselessPrefixes=true +64, F3 0FA7 F8, Xstore2_64, ShowUselessPrefixes=true 64, F2 6C, Insb_m8_DX, ShowUselessPrefixes=true 64, F2 66 6D, Insw_m16_DX, ShowUselessPrefixes=true @@ -2303,6 +2319,10 @@ 32, F3 0FA7 E8, Xcryptofb_32, ShowUselessPrefixes=true 32, F3 0FA6 E8, Ccs_hash_32, ShowUselessPrefixes=true 32, F3 0FA7 F0, Ccs_encrypt_32, ShowUselessPrefixes=true +32, F3 0FA6 F0, Via_undoc_F30FA6F0_32, ShowUselessPrefixes=true +32, F3 0FA6 F8, Via_undoc_F30FA6F8_32, ShowUselessPrefixes=true +32, F3 0FA6 E0, Xsha512_32, ShowUselessPrefixes=true +32, F3 0FA7 F8, Xstore2_32, ShowUselessPrefixes=true 32, F2 6C, Insb_m8_DX, ShowUselessPrefixes=true 32, F2 66 6D, Insw_m16_DX, ShowUselessPrefixes=true @@ -2347,7 +2367,7 @@ 16, F3 AE, Scasb_AL_m8, ShowUselessPrefixes=true 16, F3 AF, Scasw_AX_m16, ShowUselessPrefixes=true 16, F3 66 AF, Scasd_EAX_m32, ShowUselessPrefixes=true -16, F3 0FA6 C0, Montmul_16, ShowUselessPrefixes=true +16, F3 0FA6 C0, Montmul_16, ShowUselessPrefixes=true DecoderOptions=NoInvalidCheck 16, F3 0FA6 C8, Xsha1_16, ShowUselessPrefixes=true 16, F3 0FA6 D0, Xsha256_16, ShowUselessPrefixes=true 16, F3 0FA7 C0, Xstore_16, ShowUselessPrefixes=true @@ -2358,6 +2378,10 @@ 16, F3 0FA7 E8, Xcryptofb_16, ShowUselessPrefixes=true 16, F3 0FA6 E8, Ccs_hash_16, ShowUselessPrefixes=true 16, F3 0FA7 F0, Ccs_encrypt_16, ShowUselessPrefixes=true +16, F3 0FA6 F0, Via_undoc_F30FA6F0_16, ShowUselessPrefixes=true +16, F3 0FA6 F8, Via_undoc_F30FA6F8_16, ShowUselessPrefixes=true +16, F3 0FA6 E0, Xsha512_16, ShowUselessPrefixes=true +16, F3 0FA7 F8, Xstore2_16, ShowUselessPrefixes=true 16, F2 6C, Insb_m8_DX, ShowUselessPrefixes=true 16, F2 6D, Insw_m16_DX, ShowUselessPrefixes=true @@ -2407,7 +2431,7 @@ 64, F3 66 AF, Scasw_AX_m16, CC_e=e 64, F3 AF, Scasd_EAX_m32, CC_e=e 64, F3 48 AF, Scasq_RAX_m64, CC_e=e -64, F3 0FA6 C0, Montmul_64, CC_e=e +64, F3 0FA6 C0, Montmul_64, CC_e=e DecoderOptions=NoInvalidCheck 64, F3 0FA6 C8, Xsha1_64, CC_e=e 64, F3 0FA6 D0, Xsha256_64, CC_e=e 64, F3 0FA7 C0, Xstore_64, CC_e=e @@ -2418,6 +2442,10 @@ 64, F3 0FA7 E8, Xcryptofb_64, CC_e=e 64, F3 0FA6 E8, Ccs_hash_64, CC_e=e 64, F3 0FA7 F0, Ccs_encrypt_64, CC_e=e +64, F3 0FA6 F0, Via_undoc_F30FA6F0_64, CC_e=e +64, F3 0FA6 F8, Via_undoc_F30FA6F8_64, CC_e=e +64, F3 0FA6 E0, Xsha512_64, CC_e=e +64, F3 0FA7 F8, Xstore2_64, CC_e=e 64, F2 6C, Insb_m8_DX, CC_ne=ne 64, F2 66 6D, Insw_m16_DX, CC_ne=ne @@ -2478,6 +2506,10 @@ 32, F3 0FA7 E8, Xcryptofb_32, CC_e=e 32, F3 0FA6 E8, Ccs_hash_32, CC_e=e 32, F3 0FA7 F0, Ccs_encrypt_32, CC_e=e +32, F3 0FA6 F0, Via_undoc_F30FA6F0_32, CC_e=e +32, F3 0FA6 F8, Via_undoc_F30FA6F8_32, CC_e=e +32, F3 0FA6 E0, Xsha512_32, CC_e=e +32, F3 0FA7 F8, Xstore2_32, CC_e=e 32, F2 6C, Insb_m8_DX, CC_ne=ne 32, F2 66 6D, Insw_m16_DX, CC_ne=ne @@ -2522,7 +2554,7 @@ 16, F3 AE, Scasb_AL_m8, CC_e=e 16, F3 AF, Scasw_AX_m16, CC_e=e 16, F3 66 AF, Scasd_EAX_m32, CC_e=e -16, F3 0FA6 C0, Montmul_16, CC_e=e +16, F3 0FA6 C0, Montmul_16, CC_e=e DecoderOptions=NoInvalidCheck 16, F3 0FA6 C8, Xsha1_16, CC_e=e 16, F3 0FA6 D0, Xsha256_16, CC_e=e 16, F3 0FA7 C0, Xstore_16, CC_e=e @@ -2533,6 +2565,10 @@ 16, F3 0FA7 E8, Xcryptofb_16, CC_e=e 16, F3 0FA6 E8, Ccs_hash_16, CC_e=e 16, F3 0FA7 F0, Ccs_encrypt_16, CC_e=e +16, F3 0FA6 F0, Via_undoc_F30FA6F0_16, CC_e=e +16, F3 0FA6 F8, Via_undoc_F30FA6F8_16, CC_e=e +16, F3 0FA6 E0, Xsha512_16, CC_e=e +16, F3 0FA7 F8, Xstore2_16, CC_e=e 16, F2 6C, Insb_m8_DX, CC_ne=ne 16, F2 6D, Insw_m16_DX, CC_ne=ne @@ -2582,7 +2618,7 @@ 64, F3 66 AF, Scasw_AX_m16, CC_e=z 64, F3 AF, Scasd_EAX_m32, CC_e=z 64, F3 48 AF, Scasq_RAX_m64, CC_e=z -64, F3 0FA6 C0, Montmul_64, CC_e=z +64, F3 0FA6 C0, Montmul_64, CC_e=z DecoderOptions=NoInvalidCheck 64, F3 0FA6 C8, Xsha1_64, CC_e=z 64, F3 0FA6 D0, Xsha256_64, CC_e=z 64, F3 0FA7 C0, Xstore_64, CC_e=z @@ -2593,6 +2629,10 @@ 64, F3 0FA7 E8, Xcryptofb_64, CC_e=z 64, F3 0FA6 E8, Ccs_hash_64, CC_e=z 64, F3 0FA7 F0, Ccs_encrypt_64, CC_e=z +64, F3 0FA6 F0, Via_undoc_F30FA6F0_64, CC_e=z +64, F3 0FA6 F8, Via_undoc_F30FA6F8_64, CC_e=z +64, F3 0FA6 E0, Xsha512_64, CC_e=z +64, F3 0FA7 F8, Xstore2_64, CC_e=z 64, F2 6C, Insb_m8_DX, CC_ne=nz 64, F2 66 6D, Insw_m16_DX, CC_ne=nz @@ -2653,6 +2693,10 @@ 32, F3 0FA7 E8, Xcryptofb_32, CC_e=z 32, F3 0FA6 E8, Ccs_hash_32, CC_e=z 32, F3 0FA7 F0, Ccs_encrypt_32, CC_e=z +32, F3 0FA6 F0, Via_undoc_F30FA6F0_32, CC_e=z +32, F3 0FA6 F8, Via_undoc_F30FA6F8_32, CC_e=z +32, F3 0FA6 E0, Xsha512_32, CC_e=z +32, F3 0FA7 F8, Xstore2_32, CC_e=z 32, F2 6C, Insb_m8_DX, CC_ne=nz 32, F2 66 6D, Insw_m16_DX, CC_ne=nz @@ -2697,7 +2741,7 @@ 16, F3 AE, Scasb_AL_m8, CC_e=z 16, F3 AF, Scasw_AX_m16, CC_e=z 16, F3 66 AF, Scasd_EAX_m32, CC_e=z -16, F3 0FA6 C0, Montmul_16, CC_e=z +16, F3 0FA6 C0, Montmul_16, CC_e=z DecoderOptions=NoInvalidCheck 16, F3 0FA6 C8, Xsha1_16, CC_e=z 16, F3 0FA6 D0, Xsha256_16, CC_e=z 16, F3 0FA7 C0, Xstore_16, CC_e=z @@ -2708,6 +2752,10 @@ 16, F3 0FA7 E8, Xcryptofb_16, CC_e=z 16, F3 0FA6 E8, Ccs_hash_16, CC_e=z 16, F3 0FA7 F0, Ccs_encrypt_16, CC_e=z +16, F3 0FA6 F0, Via_undoc_F30FA6F0_16, CC_e=z +16, F3 0FA6 F8, Via_undoc_F30FA6F8_16, CC_e=z +16, F3 0FA6 E0, Xsha512_16, CC_e=z +16, F3 0FA7 F8, Xstore2_16, CC_e=z 16, F2 6C, Insb_m8_DX, CC_ne=nz 16, F2 6D, Insw_m16_DX, CC_ne=nz diff --git a/src/UnitTests/Intel/InstructionInfo/InstructionInfoTest_16.txt b/src/UnitTests/Intel/InstructionInfo/InstructionInfoTest_16.txt index d7bb80724..b8c8d8a6e 100644 --- a/src/UnitTests/Intel/InstructionInfo/InstructionInfoTest_16.txt +++ b/src/UnitTests/Intel/InstructionInfo/InstructionInfoTest_16.txt @@ -592,7 +592,7 @@ F2 0F38F8 18, Enqcmd_r16_m512, Legacy, ENQCMD, fw=z fc=acops op0=r op1=r r=bx r= # fs clzero 64 67 0F01 FC, Clzerod, Legacy, CLZERO, r=eax;fs # rep montmul -F3 0FA6 C0, Montmul_16, Legacy, PADLOCK_PMM, crm=es:si;Unknown cr=es;si cw=edx r=ecx cr=eax cw=eax;ecx +F3 0FA6 C0, Montmul_16, Legacy, PADLOCK_PMM, crm=es:si;Unknown cr=es;si cw=edx r=ecx cr=eax cw=eax;ecx decopt=NoInvalidCheck # rep montmul 67 F3 0FA6 C0, Montmul_32, Legacy, PADLOCK_PMM, crm=es:esi;Unknown cr=es;esi cw=edx r=ecx cr=eax cw=eax;ecx # rep xsha1 @@ -693,3 +693,19 @@ F3 0FA6 E8, Ccs_hash_16, Legacy, PADLOCK_GMI, crm=es:di;Unknown cwm=es:di;Unknow F3 0FA7 F0, Ccs_encrypt_16, Legacy, PADLOCK_GMI, crm=es:dx;Unknown crm=es:bx;Unknown crm=es:si;Unknown cwm=es:di;Unknown cr=es cr=dx;bx;si;di cw=si;di rcw=cx cr=ax # rep ccs_encrypt 67 F3 0FA7 F0, Ccs_encrypt_32, Legacy, PADLOCK_GMI, crm=es:edx;Unknown crm=es:ebx;Unknown crm=es:esi;Unknown cwm=es:edi;Unknown cr=es cr=edx;ebx;esi;edi cw=esi;edi rcw=ecx cr=eax +# rep undoc +F3 0FA6 F0, Via_undoc_F30FA6F0_16, Legacy, PADLOCK_UNDOC, save-restore +# rep undoc +67 F3 0FA6 F0, Via_undoc_F30FA6F0_32, Legacy, PADLOCK_UNDOC, save-restore +# rep undoc +F3 0FA6 F8, Via_undoc_F30FA6F8_16, Legacy, PADLOCK_UNDOC, save-restore +# rep undoc +67 F3 0FA6 F8, Via_undoc_F30FA6F8_32, Legacy, PADLOCK_UNDOC, save-restore +# rep xsha512 +F3 0FA6 E0, Xsha512_16, Legacy, PADLOCK_PHE, crm=es:di;Unknown cwm=es:di;Unknown crm=es:si;Unknown cr=es cr=si;di cw=si rcw=cx +# rep xsha512 +67 F3 0FA6 E0, Xsha512_32, Legacy, PADLOCK_PHE, crm=es:edi;Unknown cwm=es:edi;Unknown crm=es:esi;Unknown cr=es cr=esi;edi cw=esi rcw=ecx +# rep xstore2 +F3 0FA7 F8, Xstore2_16, Legacy, PADLOCK_RNG, cwm=es:di;Unknown cr=es cr=di cw=di cr=edx cw=eax rcw=cx +# rep xstore2 +67 F3 0FA7 F8, Xstore2_32, Legacy, PADLOCK_RNG, cwm=es:edi;Unknown cr=es cr=edi cw=edi cr=edx cw=eax rcw=ecx diff --git a/src/UnitTests/Intel/InstructionInfo/InstructionInfoTest_32.txt b/src/UnitTests/Intel/InstructionInfo/InstructionInfoTest_32.txt index 4f2ca4c20..cf6c2794c 100644 --- a/src/UnitTests/Intel/InstructionInfo/InstructionInfoTest_32.txt +++ b/src/UnitTests/Intel/InstructionInfo/InstructionInfoTest_32.txt @@ -1586,7 +1586,7 @@ C5ED FB CA, VEX_Vpsubq_ymm_ymm_ymmm256, VEX, AVX2, op0=w op1=n op2=n w=vmm1 # fs clzero 64 0F01 FC, Clzerod, Legacy, CLZERO, r=eax;fs # rep montmul -67 F3 0FA6 C0, Montmul_16, Legacy, PADLOCK_PMM, crm=es:si;Unknown cr=es;si cw=edx r=ecx cr=eax cw=eax;ecx +67 F3 0FA6 C0, Montmul_16, Legacy, PADLOCK_PMM, crm=es:si;Unknown cr=es;si cw=edx r=ecx cr=eax cw=eax;ecx decopt=NoInvalidCheck # rep montmul F3 0FA6 C0, Montmul_32, Legacy, PADLOCK_PMM, crm=es:esi;Unknown cr=es;esi cw=edx r=ecx cr=eax cw=eax;ecx # rep xsha1 @@ -1929,3 +1929,19 @@ F3 0FA7 F0, Ccs_encrypt_32, Legacy, PADLOCK_GMI, crm=es:edx;Unknown crm=es:ebx;U 0F0E, Rdudbg, Legacy, UDBG, priv r=eax;ecx w=edx;ebx decopt=Udbg # wrudbg 0F0F, Wrudbg, Legacy, UDBG, priv r=eax;ecx;edx cr=ebx cw=edx;ebx decopt=Udbg +# rep undoc +67 F3 0FA6 F0, Via_undoc_F30FA6F0_16, Legacy, PADLOCK_UNDOC, save-restore +# rep undoc +F3 0FA6 F0, Via_undoc_F30FA6F0_32, Legacy, PADLOCK_UNDOC, save-restore +# rep undoc +67 F3 0FA6 F8, Via_undoc_F30FA6F8_16, Legacy, PADLOCK_UNDOC, save-restore +# rep undoc +F3 0FA6 F8, Via_undoc_F30FA6F8_32, Legacy, PADLOCK_UNDOC, save-restore +# rep xsha512 +67 F3 0FA6 E0, Xsha512_16, Legacy, PADLOCK_PHE, crm=es:di;Unknown cwm=es:di;Unknown crm=es:si;Unknown cr=es cr=si;di cw=si rcw=cx +# rep xsha512 +F3 0FA6 E0, Xsha512_32, Legacy, PADLOCK_PHE, crm=es:edi;Unknown cwm=es:edi;Unknown crm=es:esi;Unknown cr=es cr=esi;edi cw=esi rcw=ecx +# rep xstore2 +67 F3 0FA7 F8, Xstore2_16, Legacy, PADLOCK_RNG, cwm=es:di;Unknown cr=es cr=di cw=di cr=edx cw=eax rcw=cx +# rep xstore2 +F3 0FA7 F8, Xstore2_32, Legacy, PADLOCK_RNG, cwm=es:edi;Unknown cr=es cr=edi cw=edi cr=edx cw=eax rcw=ecx diff --git a/src/UnitTests/Intel/InstructionInfo/InstructionInfoTest_64.txt b/src/UnitTests/Intel/InstructionInfo/InstructionInfoTest_64.txt index 12ef549ea..ea22c9c6d 100644 --- a/src/UnitTests/Intel/InstructionInfo/InstructionInfoTest_64.txt +++ b/src/UnitTests/Intel/InstructionInfo/InstructionInfoTest_64.txt @@ -19024,7 +19024,7 @@ C5ED FB CA, VEX_Vpsubq_ymm_ymm_ymmm256, VEX, AVX2, op0=w op1=n op2=n w=vmm1 # fs clzero 64 0F01 FC, Clzeroq, Legacy, CLZERO, r=rax;fs # rep montmul -F3 0FA6 C0, Montmul_64, Legacy, PADLOCK_PMM, crm=es:rsi;Unknown cr=rsi cw=rdx r=rcx cr=eax cw=rax;rcx +F3 0FA6 C0, Montmul_64, Legacy, PADLOCK_PMM, crm=es:rsi;Unknown cr=rsi cw=rdx r=rcx cr=eax cw=rax;rcx decopt=NoInvalidCheck # rep montmul 67 F3 0FA6 C0, Montmul_32, Legacy, PADLOCK_PMM, crm=es:esi;Unknown cr=esi cw=rdx r=ecx cr=eax cw=rax;rcx # rep xsha1 @@ -21985,3 +21985,19 @@ C4C379 3E D3 5A, VEX_KNC_Kextract_kr_r64_imm8, VEX, KNC, op0=w op1=r op2=r w=k2 62 F3FB08 E6 D3 5A, MVEX_Vcvtfxpntpd2dq_zmm_k1_zmmmt_imm8, MVEX, KNC, op0=w op1=r op2=r w=vmm2 r=zmm3 decopt=KNC # vcvtfxpntpd2dq zmm10{k3},zmm3{cdab},0A5h 62 73FB1B E6 D3 A5, MVEX_Vcvtfxpntpd2dq_zmm_k1_zmmmt_imm8, MVEX, KNC, op0=rcw op1=r op2=r rcw=vmm10 r=zmm3 r=k3 decopt=KNC +# rep undoc +67 F3 0FA6 F0, Via_undoc_F30FA6F0_32, Legacy, PADLOCK_UNDOC, save-restore +# rep undoc +F3 0FA6 F0, Via_undoc_F30FA6F0_64, Legacy, PADLOCK_UNDOC, save-restore +# rep undoc +67 F3 0FA6 F8, Via_undoc_F30FA6F8_32, Legacy, PADLOCK_UNDOC, save-restore +# rep undoc +F3 0FA6 F8, Via_undoc_F30FA6F8_64, Legacy, PADLOCK_UNDOC, save-restore +# rep xsha512 +67 F3 0FA6 E0, Xsha512_32, Legacy, PADLOCK_PHE, crm=es:edi;Unknown cwm=es:edi;Unknown crm=es:esi;Unknown cr=esi;edi cw=rsi r=ecx cw=rcx +# rep xsha512 +F3 0FA6 E0, Xsha512_64, Legacy, PADLOCK_PHE, crm=es:rdi;Unknown cwm=es:rdi;Unknown crm=es:rsi;Unknown cr=rsi;rdi cw=rsi rcw=rcx +# rep xstore2 +67 F3 0FA7 F8, Xstore2_32, Legacy, PADLOCK_RNG, cwm=es:edi;Unknown cr=edi cw=rdi cr=edx cw=rax r=ecx cw=rcx +# rep xstore2 +F3 0FA7 F8, Xstore2_64, Legacy, PADLOCK_RNG, cwm=es:rdi;Unknown cr=rdi cw=rdi cr=edx cw=rax rcw=rcx diff --git a/src/csharp/Intel/Generator/Assembler/AssemblerSyntaxGenerator.cs b/src/csharp/Intel/Generator/Assembler/AssemblerSyntaxGenerator.cs index 1cb20baef..83a4c01c9 100644 --- a/src/csharp/Intel/Generator/Assembler/AssemblerSyntaxGenerator.cs +++ b/src/csharp/Intel/Generator/Assembler/AssemblerSyntaxGenerator.cs @@ -1834,6 +1834,13 @@ protected List GetDecoderOptions(int bitness, InstructionDef def) { if (def.DecoderOption.Value != 0) list.Add(decoderOptions[def.DecoderOption.RawName]); + switch ((Code)def.Code.Value) { + // Must use 32-bit addressing + case Code.Montmul_16: + case Code.Montmul_64: + list.Add(decoderOptions[nameof(DecoderOptions.NoInvalidCheck)]); + break; + } switch (bitness) { case 16: if ((def.Flags2 & InstructionDefFlags2.IntelDecoder16) == 0 && (def.Flags2 & InstructionDefFlags2.AmdDecoder16) != 0) diff --git a/src/csharp/Intel/Generator/Decoder/DecoderTableSerializer.cs b/src/csharp/Intel/Generator/Decoder/DecoderTableSerializer.cs index ea7f78dba..50756b8d4 100644 --- a/src/csharp/Intel/Generator/Decoder/DecoderTableSerializer.cs +++ b/src/csharp/Intel/Generator/Decoder/DecoderTableSerializer.cs @@ -349,6 +349,7 @@ int CountInvalid(object?[] handlers, int index) { { opCodeHandlerKind[nameof(LegacyOpCodeHandlerKind.Simple2Iw)], (1, 3) }, { opCodeHandlerKind[nameof(LegacyOpCodeHandlerKind.Simple3)], (1, 3) }, { opCodeHandlerKind[nameof(LegacyOpCodeHandlerKind.Simple5)], (1, 3) }, + { opCodeHandlerKind[nameof(LegacyOpCodeHandlerKind.Simple5_a32)], (1, 3) }, { opCodeHandlerKind[nameof(LegacyOpCodeHandlerKind.Simple5_ModRM_as)], (1, 3) }, { opCodeHandlerKind[nameof(LegacyOpCodeHandlerKind.Sw_Ev)], (1, 3) }, { opCodeHandlerKind[nameof(LegacyOpCodeHandlerKind.Xv_Yv)], (1, 3) }, diff --git a/src/csharp/Intel/Generator/Decoder/DecoderTable_Legacy.cs b/src/csharp/Intel/Generator/Decoder/DecoderTable_Legacy.cs index 02a47e969..87efa33b8 100644 --- a/src/csharp/Intel/Generator/Decoder/DecoderTable_Legacy.cs +++ b/src/csharp/Intel/Generator/Decoder/DecoderTable_Legacy.cs @@ -181,6 +181,7 @@ public static (string name, object?[] handlers)[] CreateHandlers(GenTypes genTyp var Simple3 = kind[nameof(LegacyOpCodeHandlerKind.Simple3)]; var Simple4 = kind[nameof(LegacyOpCodeHandlerKind.Simple4)]; var Simple5 = kind[nameof(LegacyOpCodeHandlerKind.Simple5)]; + var Simple5_a32 = kind[nameof(LegacyOpCodeHandlerKind.Simple5_a32)]; var Simple5_ModRM_as = kind[nameof(LegacyOpCodeHandlerKind.Simple5_ModRM_as)]; var SimpleReg = kind[nameof(LegacyOpCodeHandlerKind.SimpleReg)]; var ST_STi = kind[nameof(LegacyOpCodeHandlerKind.ST_STi)]; @@ -1521,254 +1522,157 @@ public static (string name, object?[] handlers)[] CreateHandlers(GenTypes genTyp invalid, }), - ("handlers_Grp_0FA6_lo", + ("handlers_Grp_0FA6", new object[8] { + new object[] { RM, + new object[] { MandatoryPrefix4, + invalid, + invalid, + new object[] { Simple5_a32, code[nameof(Code.Montmul_16)], code[nameof(Code.Montmul_32)], code[nameof(Code.Montmul_64)] }, + invalid, + 0x00, + }, + invalid, + }, + new object[] { RM, + new object[] { MandatoryPrefix4, + invalid, + invalid, + new object[] { Simple5, code[nameof(Code.Xsha1_16)], code[nameof(Code.Xsha1_32)], code[nameof(Code.Xsha1_64)] }, + invalid, + 0x00, + }, + invalid, + }, + new object[] { RM, + new object[] { MandatoryPrefix4, + invalid, + invalid, + new object[] { Simple5, code[nameof(Code.Xsha256_16)], code[nameof(Code.Xsha256_32)], code[nameof(Code.Xsha256_64)] }, + invalid, + 0x00, + }, + invalid, + }, invalid, - invalid, - invalid, - invalid, - invalid, - invalid, - invalid, - invalid, - }), - - ("handlers_Grp_0FA6_hi", - new object?[0x40] { - // C0 - new object[] { MandatoryPrefix4, - invalid_NoModRM, - invalid_NoModRM, - new object[] { Simple5, code[nameof(Code.Montmul_16)], code[nameof(Code.Montmul_32)], code[nameof(Code.Montmul_64)] }, - invalid_NoModRM, - 0x00, + new object[] { RM, + new object[] { MandatoryPrefix4, + invalid, + invalid, + new object[] { Simple5, code[nameof(Code.Xsha512_16)], code[nameof(Code.Xsha512_32)], code[nameof(Code.Xsha512_64)] }, + invalid, + 0x00, + }, + invalid, }, - null, - null, - null, - null, - null, - null, - null, - - // C8 - new object[] { MandatoryPrefix4, - invalid_NoModRM, - invalid_NoModRM, - new object[] { Simple5, code[nameof(Code.Xsha1_16)], code[nameof(Code.Xsha1_32)], code[nameof(Code.Xsha1_64)] }, - invalid_NoModRM, - 0x00, + new object[] { RM, + new object[] { MandatoryPrefix4, + invalid, + invalid, + new object[] { Simple5, code[nameof(Code.Ccs_hash_16)], code[nameof(Code.Ccs_hash_32)], code[nameof(Code.Ccs_hash_64)] }, + invalid, + 0x00, + }, + invalid, }, - null, - null, - null, - null, - null, - null, - null, - - // D0 - new object[] { MandatoryPrefix4, - invalid_NoModRM, - invalid_NoModRM, - new object[] { Simple5, code[nameof(Code.Xsha256_16)], code[nameof(Code.Xsha256_32)], code[nameof(Code.Xsha256_64)] }, - invalid_NoModRM, - 0x00, + new object[] { RM, + new object[] { MandatoryPrefix4, + invalid, + invalid, + new object[] { Simple5, code[nameof(Code.Via_undoc_F30FA6F0_16)], code[nameof(Code.Via_undoc_F30FA6F0_32)], code[nameof(Code.Via_undoc_F30FA6F0_64)] }, + invalid, + 0x00, + }, + invalid, }, - null, - null, - null, - null, - null, - null, - null, - - // D8 - null, - null, - null, - null, - null, - null, - null, - null, - - // E0 - null, - null, - null, - null, - null, - null, - null, - null, - - // E8 - new object[] { MandatoryPrefix4, - invalid_NoModRM, - invalid_NoModRM, - new object[] { Simple5, code[nameof(Code.Ccs_hash_16)], code[nameof(Code.Ccs_hash_32)], code[nameof(Code.Ccs_hash_64)] }, - invalid_NoModRM, - 0x00, + new object[] { RM, + new object[] { MandatoryPrefix4, + invalid, + invalid, + new object[] { Simple5, code[nameof(Code.Via_undoc_F30FA6F8_16)], code[nameof(Code.Via_undoc_F30FA6F8_32)], code[nameof(Code.Via_undoc_F30FA6F8_64)] }, + invalid, + 0x00, + }, + invalid, }, - null, - null, - null, - null, - null, - null, - null, - - // F0 - null, - null, - null, - null, - null, - null, - null, - null, - - // F8 - null, - null, - null, - null, - null, - null, - null, - null, }), - ("handlers_Grp_0FA7_lo", + ("handlers_Grp_0FA7", new object[8] { - invalid, - invalid, - invalid, - invalid, - invalid, - invalid, - invalid, - invalid, - }), - - ("handlers_Grp_0FA7_hi", - new object?[0x40] { - // C0 - new object[] { Simple5, code[nameof(Code.Xstore_16)], code[nameof(Code.Xstore_32)], code[nameof(Code.Xstore_64)] }, - null, - null, - null, - null, - null, - null, - null, - - // C8 - new object[] { MandatoryPrefix4, - invalid_NoModRM, - invalid_NoModRM, - new object[] { Simple5, code[nameof(Code.Xcryptecb_16)], code[nameof(Code.Xcryptecb_32)], code[nameof(Code.Xcryptecb_64)] }, - invalid_NoModRM, - 0x00, + new object[] { RM, + new object[] { Simple5, code[nameof(Code.Xstore_16)], code[nameof(Code.Xstore_32)], code[nameof(Code.Xstore_64)] }, + invalid, }, - null, - null, - null, - null, - null, - null, - null, - - // D0 - new object[] { MandatoryPrefix4, - invalid_NoModRM, - invalid_NoModRM, - new object[] { Simple5, code[nameof(Code.Xcryptcbc_16)], code[nameof(Code.Xcryptcbc_32)], code[nameof(Code.Xcryptcbc_64)] }, - invalid_NoModRM, - 0x00, + new object[] { RM, + new object[] { MandatoryPrefix4, + invalid, + invalid, + new object[] { Simple5, code[nameof(Code.Xcryptecb_16)], code[nameof(Code.Xcryptecb_32)], code[nameof(Code.Xcryptecb_64)] }, + invalid, + 0x00, + }, + invalid, }, - null, - null, - null, - null, - null, - null, - null, - - // D8 - new object[] { MandatoryPrefix4, - invalid_NoModRM, - invalid_NoModRM, - new object[] { Simple5, code[nameof(Code.Xcryptctr_16)], code[nameof(Code.Xcryptctr_32)], code[nameof(Code.Xcryptctr_64)] }, - invalid_NoModRM, - 0x00, + new object[] { RM, + new object[] { MandatoryPrefix4, + invalid, + invalid, + new object[] { Simple5, code[nameof(Code.Xcryptcbc_16)], code[nameof(Code.Xcryptcbc_32)], code[nameof(Code.Xcryptcbc_64)] }, + invalid, + 0x00, + }, + invalid, }, - null, - null, - null, - null, - null, - null, - null, - - // E0 - new object[] { MandatoryPrefix4, - invalid_NoModRM, - invalid_NoModRM, - new object[] { Simple5, code[nameof(Code.Xcryptcfb_16)], code[nameof(Code.Xcryptcfb_32)], code[nameof(Code.Xcryptcfb_64)] }, - invalid_NoModRM, - 0x00, + new object[] { RM, + new object[] { MandatoryPrefix4, + invalid, + invalid, + new object[] { Simple5, code[nameof(Code.Xcryptctr_16)], code[nameof(Code.Xcryptctr_32)], code[nameof(Code.Xcryptctr_64)] }, + invalid, + 0x00, + }, + invalid, }, - null, - null, - null, - null, - null, - null, - null, - - // E8 - new object[] { MandatoryPrefix4, - invalid_NoModRM, - invalid_NoModRM, - new object[] { Simple5, code[nameof(Code.Xcryptofb_16)], code[nameof(Code.Xcryptofb_32)], code[nameof(Code.Xcryptofb_64)] }, - invalid_NoModRM, - 0x00, + new object[] { RM, + new object[] { MandatoryPrefix4, + invalid, + invalid, + new object[] { Simple5, code[nameof(Code.Xcryptcfb_16)], code[nameof(Code.Xcryptcfb_32)], code[nameof(Code.Xcryptcfb_64)] }, + invalid, + 0x00, + }, + invalid, }, - null, - null, - null, - null, - null, - null, - null, - - // F0 - new object[] { MandatoryPrefix4, - invalid_NoModRM, - invalid_NoModRM, - new object[] { Simple5, code[nameof(Code.Ccs_encrypt_16)], code[nameof(Code.Ccs_encrypt_32)], code[nameof(Code.Ccs_encrypt_64)] }, - invalid_NoModRM, - 0x00, + new object[] { RM, + new object[] { MandatoryPrefix4, + invalid, + invalid, + new object[] { Simple5, code[nameof(Code.Xcryptofb_16)], code[nameof(Code.Xcryptofb_32)], code[nameof(Code.Xcryptofb_64)] }, + invalid, + 0x00, + }, + invalid, + }, + new object[] { RM, + new object[] { MandatoryPrefix4, + invalid, + invalid, + new object[] { Simple5, code[nameof(Code.Ccs_encrypt_16)], code[nameof(Code.Ccs_encrypt_32)], code[nameof(Code.Ccs_encrypt_64)] }, + invalid, + 0x00, + }, + invalid, + }, + new object[] { RM, + new object[] { MandatoryPrefix4, + invalid, + invalid, + new object[] { Simple5, code[nameof(Code.Xstore2_16)], code[nameof(Code.Xstore2_32)], code[nameof(Code.Xstore2_64)] }, + invalid, + 0x00, + }, + invalid, }, - null, - null, - null, - null, - null, - null, - null, - - // F8 - null, - null, - null, - null, - null, - null, - null, - null, }), ("handlers_Grp_0FBA", @@ -4641,19 +4545,19 @@ public static (string name, object?[] handlers)[] CreateHandlers(GenTypes genTyp new object[] { Ev_Gv_CL, code[nameof(Code.Shld_rm16_r16_CL)], code[nameof(Code.Shld_rm32_r32_CL)], code[nameof(Code.Shld_rm64_r64_CL)] }, new object[] { Bitness, new object[] { Options5, - new object[] { Group8x64, "handlers_Grp_0FA6_lo", "handlers_Grp_0FA6_hi" }, + new object[] { Group, "handlers_Grp_0FA6" }, new object[] { Gv_Ev_3b, code[nameof(Code.Xbts_r16_rm16)], code[nameof(Code.Xbts_r32_rm32)] }, options[nameof(DecoderOptions.Xbts)], new object[] { Eb_Gb_1, code[nameof(Code.Cmpxchg486_rm8_r8)] }, options[nameof(DecoderOptions.Cmpxchg486A)] }, - new object[] { Group8x64, "handlers_Grp_0FA6_lo", "handlers_Grp_0FA6_hi" }, + new object[] { Group, "handlers_Grp_0FA6" }, }, new object[] { Bitness, new object[] { Options5, - new object[] { Group8x64, "handlers_Grp_0FA7_lo", "handlers_Grp_0FA7_hi" }, + new object[] { Group, "handlers_Grp_0FA7" }, new object[] { Ev_Gv_3b, code[nameof(Code.Ibts_rm16_r16)], code[nameof(Code.Ibts_rm32_r32)] }, options[nameof(DecoderOptions.Xbts)], new object[] { Ev_Gv_3b, code[nameof(Code.Cmpxchg486_rm16_r16)], code[nameof(Code.Cmpxchg486_rm32_r32)] }, options[nameof(DecoderOptions.Cmpxchg486A)] }, - new object[] { Group8x64, "handlers_Grp_0FA7_lo", "handlers_Grp_0FA7_hi" }, + new object[] { Group, "handlers_Grp_0FA7" }, }, // A8 diff --git a/src/csharp/Intel/Generator/Enums/Code.cs b/src/csharp/Intel/Generator/Enums/Code.cs index c03ed8c91..cc258a46e 100644 --- a/src/csharp/Intel/Generator/Enums/Code.cs +++ b/src/csharp/Intel/Generator/Enums/Code.cs @@ -4829,6 +4829,18 @@ enum Code { MVEX_Undoc_zmm_k1_zmmmt_imm8_512_66_0F3A_W0_D0, MVEX_Undoc_zmm_k1_zmmmt_imm8_512_66_0F3A_W0_D1, MVEX_Vcvtfxpntpd2dq_zmm_k1_zmmmt_imm8, + Via_undoc_F30FA6F0_16, + Via_undoc_F30FA6F0_32, + Via_undoc_F30FA6F0_64, + Via_undoc_F30FA6F8_16, + Via_undoc_F30FA6F8_32, + Via_undoc_F30FA6F8_64, + Xsha512_16, + Xsha512_32, + Xsha512_64, + Xstore2_16, + Xstore2_32, + Xstore2_64, } [TypeGen(TypeGenOrders.CreatedInstructions)] diff --git a/src/csharp/Intel/Generator/Enums/Decoder/LegacyOpCodeHandlerKind.cs b/src/csharp/Intel/Generator/Enums/Decoder/LegacyOpCodeHandlerKind.cs index d389ddc50..bb3a3513b 100644 --- a/src/csharp/Intel/Generator/Enums/Decoder/LegacyOpCodeHandlerKind.cs +++ b/src/csharp/Intel/Generator/Enums/Decoder/LegacyOpCodeHandlerKind.cs @@ -218,5 +218,6 @@ enum LegacyOpCodeHandlerKind : byte { PrefixF2, PrefixF3, PrefixREX, + Simple5_a32, } } diff --git a/src/csharp/Intel/Generator/Enums/InstructionInfo/CpuidFeature.cs b/src/csharp/Intel/Generator/Enums/InstructionInfo/CpuidFeature.cs index e1a7ca0b3..44039b891 100644 --- a/src/csharp/Intel/Generator/Enums/InstructionInfo/CpuidFeature.cs +++ b/src/csharp/Intel/Generator/Enums/InstructionInfo/CpuidFeature.cs @@ -326,5 +326,7 @@ enum CpuidFeature { UDBG, [Comment("Intel Knights Corner")] KNC, + [Comment("Undocumented instruction")] + PADLOCK_UNDOC, } } diff --git a/src/csharp/Intel/Generator/Enums/Mnemonic.cs b/src/csharp/Intel/Generator/Enums/Mnemonic.cs index 5f89d1e87..da9391bc5 100644 --- a/src/csharp/Intel/Generator/Enums/Mnemonic.cs +++ b/src/csharp/Intel/Generator/Enums/Mnemonic.cs @@ -1838,5 +1838,7 @@ enum Mnemonic { Vscatterpf0hintdps, Vsubrpd, Vsubrps, + Xsha512, + Xstore2, } } diff --git a/src/csharp/Intel/Generator/Tables/InstructionDef.cs b/src/csharp/Intel/Generator/Tables/InstructionDef.cs index 0dbf1932c..e8b5dfe0b 100644 --- a/src/csharp/Intel/Generator/Tables/InstructionDef.cs +++ b/src/csharp/Intel/Generator/Tables/InstructionDef.cs @@ -386,6 +386,10 @@ enum InstructionDefFlags3 : uint { /// Code assembler ignores it when generating memory operand methods /// AsmIgnoreMemory = 0x02000000, + /// + /// Address size must be 32 or #UD + /// + RequiresAddressSize32 = 0x04000000,//TODO: Add to OpCodeInfo } enum VmxMode { diff --git a/src/csharp/Intel/Generator/Tables/InstructionDefs.txt b/src/csharp/Intel/Generator/Tables/InstructionDefs.txt index 6361fe741..b55d645cf 100644 --- a/src/csharp/Intel/Generator/Tables/InstructionDefs.txt +++ b/src/csharp/Intel/Generator/Tables/InstructionDefs.txt @@ -15806,7 +15806,8 @@ END INSTRUCTION: a16 F3 0F A6 C0 | MONTMUL | PADLOCK_PMM implied: cr=[es:si=Unknown] rcw=ecx cr=eax cw=eax;edx code-suffix: 16 - flags: 16 32 + # Requires 32-bit addressing (Zhaoxin KX-6580 CPU, tested by @tremalrik) + flags: 16 32 a32-req gas: asz intel: asz nasm: asz @@ -15816,6 +15817,8 @@ END INSTRUCTION: a32 F3 0F A6 C0 | MONTMUL | PADLOCK_PMM implied: cr=[es:esi=Unknown] rcw=ecx cr=eax cw=eax;edx code-suffix: 32 + # Requires 32-bit addressing (Zhaoxin KX-6580 CPU, tested by @tremalrik) + flags: a32-req gas: asz intel: asz nasm: asz @@ -15825,7 +15828,8 @@ END INSTRUCTION: a64 F3 0F A6 C0 | MONTMUL | PADLOCK_PMM implied: cr=[es:rsi=Unknown] rcw=rcx cr=eax cw=eax;edx code-suffix: 64 - flags: 64 + # Requires 32-bit addressing (Zhaoxin KX-6580 CPU, tested by @tremalrik) + flags: 64 a32-req gas: asz intel: asz nasm: asz @@ -15889,6 +15893,37 @@ INSTRUCTION: a64 F3 0F A6 D0 | XSHA256 | PADLOCK_PHE nasm: asz END +# Code: Xsha512_16 +INSTRUCTION: a16 F3 0F A6 E0 | XSHA512 | PADLOCK_PHE + # https://github.com/openssl/openssl/blob/27aca04e13ca8a9bead49de7bc380110ecb7064e/engines/asm/e_padlock-x86.pl#L597 + # rAX isn't used like in XSHA256 + implied: cr=[es:si=Unknown] crcw=[es:di=Unknown] cw=si rcw=cx + code-suffix: 16 + flags: 16 32 + gas: asz + intel: asz + nasm: asz +END + +# Code: Xsha512_32 +INSTRUCTION: a32 F3 0F A6 E0 | XSHA512 | PADLOCK_PHE + implied: cr=[es:esi=Unknown] crcw=[es:edi=Unknown] cw=esi rcw=ecx + code-suffix: 32 + gas: asz + intel: asz + nasm: asz +END + +# Code: Xsha512_64 +INSTRUCTION: a64 F3 0F A6 E0 | XSHA512 | PADLOCK_PHE + implied: cr=[es:rsi=Unknown] crcw=[es:rdi=Unknown] cw=rsi rcw=rcx + code-suffix: 64 + flags: 64 + gas: asz + intel: asz + nasm: asz +END + # Code: Xbts_r16_rm16 INSTRUCTION: o16 0F A6 /r | XBTS r16, r/m16 | INTEL386_A0_ONLY ops: rw=reg r=rm | UInt16 @@ -16080,6 +16115,36 @@ INSTRUCTION: a64 F3 0F A7 E8 | XCRYPTOFB | PADLOCK_ACE nasm: asz END +# Code: Xstore2_16 +INSTRUCTION: a16 F3 0F A7 F8 | XSTORE2 | PADLOCK_RNG + # Seems to be an alias of XSTORE but doesn't accept F2 prefix (Zhaoxin KX-6580 CPU, tested by @tremalrik) + implied: xstore=2 + code-suffix: 16 + flags: 16 32 + gas: asz + intel: asz + nasm: asz +END + +# Code: Xstore2_32 +INSTRUCTION: a32 F3 0F A7 F8 | XSTORE2 | PADLOCK_RNG + implied: xstore=4 + code-suffix: 32 + gas: asz + intel: asz + nasm: asz +END + +# Code: Xstore2_64 +INSTRUCTION: a64 F3 0F A7 F8 | XSTORE2 | PADLOCK_RNG + implied: xstore=8 + code-suffix: 64 + flags: 64 + gas: asz + intel: asz + nasm: asz +END + # Code: Ibts_rm16_r16 INSTRUCTION: o16 0F A7 /r | IBTS r/m16, r16 | INTEL386_A0_ONLY ops: rw=rm r=reg | UInt16 @@ -29861,6 +29926,68 @@ INSTRUCTION: a64 F3 0F A6 E8 | CCS_HASH | PADLOCK_GMI nasm: asz END +# Code: Via_undoc_F30FA6F0_16 +INSTRUCTION: a16 F3 0F A6 F0 | UNDOC | PADLOCK_UNDOC + # Undocumented instruction (Zhaoxin KX-6580 CPU, tested by @tremalrik) + code-mnemonic: via_undoc + code-suffix: F30FA6F0_16 + flags: 16 32 save-restore asm-ig + gas: asz + intel: asz + nasm: asz +END + +# Code: Via_undoc_F30FA6F0_32 +INSTRUCTION: a32 F3 0F A6 F0 | UNDOC | PADLOCK_UNDOC + code-mnemonic: via_undoc + code-suffix: F30FA6F0_32 + flags: save-restore asm-ig + gas: asz + intel: asz + nasm: asz +END + +# Code: Via_undoc_F30FA6F0_64 +INSTRUCTION: a64 F3 0F A6 F0 | UNDOC | PADLOCK_UNDOC + code-mnemonic: via_undoc + code-suffix: F30FA6F0_64 + flags: 64 save-restore asm-ig + gas: asz + intel: asz + nasm: asz +END + +# Code: Via_undoc_F30FA6F8_16 +INSTRUCTION: a16 F3 0F A6 F8 | UNDOC | PADLOCK_UNDOC + # Undocumented instruction (Zhaoxin KX-6580 CPU, tested by @tremalrik) + code-mnemonic: via_undoc + code-suffix: F30FA6F8_16 + flags: 16 32 save-restore asm-ig + gas: asz + intel: asz + nasm: asz +END + +# Code: Via_undoc_F30FA6F8_32 +INSTRUCTION: a32 F3 0F A6 F8 | UNDOC | PADLOCK_UNDOC + code-mnemonic: via_undoc + code-suffix: F30FA6F8_32 + flags: save-restore asm-ig + gas: asz + intel: asz + nasm: asz +END + +# Code: Via_undoc_F30FA6F8_64 +INSTRUCTION: a64 F3 0F A6 F8 | UNDOC | PADLOCK_UNDOC + code-mnemonic: via_undoc + code-suffix: F30FA6F8_64 + flags: 64 save-restore asm-ig + gas: asz + intel: asz + nasm: asz +END + # Code: Ccs_encrypt_16 INSTRUCTION: a16 F3 0F A7 F0 | CCS_ENCRYPT | PADLOCK_GMI # https://github.com/ZXOpenSource/OpenSSL-ZX-GMI/blob/master/GMI%20User%20Manual%20V1.0.pdf diff --git a/src/csharp/Intel/Generator/Tables/InstructionDefsReader.cs b/src/csharp/Intel/Generator/Tables/InstructionDefsReader.cs index d7b322040..7733d0fda 100644 --- a/src/csharp/Intel/Generator/Tables/InstructionDefsReader.cs +++ b/src/csharp/Intel/Generator/Tables/InstructionDefsReader.cs @@ -634,6 +634,7 @@ bool TryParse(ref int lineIndex, [NotNullWhen(true)] out InstructionDef? def, ou case "tile-stride-index": state.Flags3 |= InstructionDefFlags3.TileStrideIndex; break; case "unique-dest-reg-num": state.Flags3 |= InstructionDefFlags3.RequiresUniqueDestRegNum; break; case "is-string-op": state.Flags3 |= InstructionDefFlags3.IsStringOp; break; + case "a32-req": state.Flags3 |= InstructionDefFlags3.RequiresAddressSize32; break; case "vmx": if (state.VmxMode != VmxMode.None) { diff --git a/src/csharp/Intel/Iced.UnitTests/Intel/AssemblerTests/AssemblerTests16.g.cs b/src/csharp/Intel/Iced.UnitTests/Intel/AssemblerTests/AssemblerTests16.g.cs index a806891e2..f11869023 100644 --- a/src/csharp/Intel/Iced.UnitTests/Intel/AssemblerTests/AssemblerTests16.g.cs +++ b/src/csharp/Intel/Iced.UnitTests/Intel/AssemblerTests/AssemblerTests16.g.cs @@ -6251,7 +6251,7 @@ public void monitorx() { public void montmul() { { // skip (Bitness == 64) not supported by this Assembler bitness } /* else */ { // skip (Bitness >= 32) not supported by this Assembler bitness - } /* else */ TestAssembler(c => c.montmul(), Instruction.Create(Code.Montmul_16), TestInstrFlags.RemoveRepRepnePrefixes); + } /* else */ TestAssembler(c => c.montmul(), Instruction.Create(Code.Montmul_16), TestInstrFlags.RemoveRepRepnePrefixes, decoderOptions: DecoderOptions.NoInvalidCheck); } [Fact] @@ -46939,6 +46939,13 @@ public void xsha256() { } /* else */ TestAssembler(c => c.xsha256(), Instruction.Create(Code.Xsha256_16), TestInstrFlags.RemoveRepRepnePrefixes); } + [Fact] + public void xsha512() { + { // skip (Bitness == 64) not supported by this Assembler bitness + } /* else */ { // skip (Bitness >= 32) not supported by this Assembler bitness + } /* else */ TestAssembler(c => c.xsha512(), Instruction.Create(Code.Xsha512_16), TestInstrFlags.RemoveRepRepnePrefixes); + } + [Fact] public void xstore() { { // skip (Bitness == 64) not supported by this Assembler bitness @@ -46946,6 +46953,13 @@ public void xstore() { } /* else */ TestAssembler(c => c.xstore(), Instruction.Create(Code.Xstore_16), TestInstrFlags.RemoveRepRepnePrefixes); } + [Fact] + public void xstore2() { + { // skip (Bitness == 64) not supported by this Assembler bitness + } /* else */ { // skip (Bitness >= 32) not supported by this Assembler bitness + } /* else */ TestAssembler(c => c.xstore2(), Instruction.Create(Code.Xstore2_16), TestInstrFlags.RemoveRepRepnePrefixes); + } + [Fact] public void xsusldtrk() { TestAssembler(c => c.xsusldtrk(), Instruction.Create(Code.Xsusldtrk)); diff --git a/src/csharp/Intel/Iced.UnitTests/Intel/AssemblerTests/AssemblerTests32.g.cs b/src/csharp/Intel/Iced.UnitTests/Intel/AssemblerTests/AssemblerTests32.g.cs index a63d45f78..ad7925546 100644 --- a/src/csharp/Intel/Iced.UnitTests/Intel/AssemblerTests/AssemblerTests32.g.cs +++ b/src/csharp/Intel/Iced.UnitTests/Intel/AssemblerTests/AssemblerTests32.g.cs @@ -47142,6 +47142,14 @@ public void xsha256() { } /* else skip !(Bitness >= 32) not supported by this Assembler bitness */ } + [Fact] + public void xsha512() { + { // skip (Bitness == 64) not supported by this Assembler bitness + } /* else */ { /* if (Bitness >= 32) */ + TestAssembler(c => c.xsha512(), Instruction.Create(Code.Xsha512_32), TestInstrFlags.RemoveRepRepnePrefixes); + } /* else skip !(Bitness >= 32) not supported by this Assembler bitness */ + } + [Fact] public void xstore() { { // skip (Bitness == 64) not supported by this Assembler bitness @@ -47150,6 +47158,14 @@ public void xstore() { } /* else skip !(Bitness >= 32) not supported by this Assembler bitness */ } + [Fact] + public void xstore2() { + { // skip (Bitness == 64) not supported by this Assembler bitness + } /* else */ { /* if (Bitness >= 32) */ + TestAssembler(c => c.xstore2(), Instruction.Create(Code.Xstore2_32), TestInstrFlags.RemoveRepRepnePrefixes); + } /* else skip !(Bitness >= 32) not supported by this Assembler bitness */ + } + [Fact] public void xsusldtrk() { TestAssembler(c => c.xsusldtrk(), Instruction.Create(Code.Xsusldtrk)); diff --git a/src/csharp/Intel/Iced.UnitTests/Intel/AssemblerTests/AssemblerTests64.g.cs b/src/csharp/Intel/Iced.UnitTests/Intel/AssemblerTests/AssemblerTests64.g.cs index 38afa6a09..0881d81e4 100644 --- a/src/csharp/Intel/Iced.UnitTests/Intel/AssemblerTests/AssemblerTests64.g.cs +++ b/src/csharp/Intel/Iced.UnitTests/Intel/AssemblerTests/AssemblerTests64.g.cs @@ -7077,7 +7077,7 @@ public void monitorx() { [Fact] public void montmul() { { /* if (Bitness == 64) */ - TestAssembler(c => c.montmul(), Instruction.Create(Code.Montmul_64), TestInstrFlags.RemoveRepRepnePrefixes); + TestAssembler(c => c.montmul(), Instruction.Create(Code.Montmul_64), TestInstrFlags.RemoveRepRepnePrefixes, decoderOptions: DecoderOptions.NoInvalidCheck); } /* else skip !(Bitness == 64) not supported by this Assembler bitness */ } @@ -49107,6 +49107,13 @@ public void xsha256() { } /* else skip !(Bitness == 64) not supported by this Assembler bitness */ } + [Fact] + public void xsha512() { + { /* if (Bitness == 64) */ + TestAssembler(c => c.xsha512(), Instruction.Create(Code.Xsha512_64), TestInstrFlags.RemoveRepRepnePrefixes); + } /* else skip !(Bitness == 64) not supported by this Assembler bitness */ + } + [Fact] public void xstore() { { /* if (Bitness == 64) */ @@ -49114,6 +49121,13 @@ public void xstore() { } /* else skip !(Bitness == 64) not supported by this Assembler bitness */ } + [Fact] + public void xstore2() { + { /* if (Bitness == 64) */ + TestAssembler(c => c.xstore2(), Instruction.Create(Code.Xstore2_64), TestInstrFlags.RemoveRepRepnePrefixes); + } /* else skip !(Bitness == 64) not supported by this Assembler bitness */ + } + [Fact] public void xsusldtrk() { TestAssembler(c => c.xsusldtrk(), Instruction.Create(Code.Xsusldtrk)); diff --git a/src/csharp/Intel/Iced.UnitTests/Intel/EncoderTests/DecEncTests.cs b/src/csharp/Intel/Iced.UnitTests/Intel/EncoderTests/DecEncTests.cs index a3063ea56..7fd6de992 100644 --- a/src/csharp/Intel/Iced.UnitTests/Intel/EncoderTests/DecEncTests.cs +++ b/src/csharp/Intel/Iced.UnitTests/Intel/EncoderTests/DecEncTests.cs @@ -2036,6 +2036,11 @@ void Verify_that_test_cases_test_enough_bits() { if (CodeUtils.IsIgnored(codeNames[i])) continue; var code = (Code)i; + switch (code) { + case Code.Montmul_16: + case Code.Montmul_64: + continue; + } var opCode = code.ToOpCode(); if (!opCode.IsInstruction || opCode.Code == Code.Popw_CS) continue; diff --git a/src/csharp/Intel/Iced.UnitTests/Intel/ToEnumConverter.Code.cs b/src/csharp/Intel/Iced.UnitTests/Intel/ToEnumConverter.Code.cs index b192031b1..314f90674 100644 --- a/src/csharp/Intel/Iced.UnitTests/Intel/ToEnumConverter.Code.cs +++ b/src/csharp/Intel/Iced.UnitTests/Intel/ToEnumConverter.Code.cs @@ -15,7 +15,7 @@ static partial class ToEnumConverter { static readonly Dictionary codeDict = // GENERATOR-BEGIN: CodeHash // ⚠️This was generated by GENERATOR!🦹‍♂️ - new Dictionary(4818, StringComparer.Ordinal) { + new Dictionary(4830, StringComparer.Ordinal) { { "INVALID", Code.INVALID }, { "DeclareByte", Code.DeclareByte }, { "DeclareWord", Code.DeclareWord }, @@ -4834,6 +4834,18 @@ static partial class ToEnumConverter { { "MVEX_Undoc_zmm_k1_zmmmt_imm8_512_66_0F3A_W0_D0", Code.MVEX_Undoc_zmm_k1_zmmmt_imm8_512_66_0F3A_W0_D0 }, { "MVEX_Undoc_zmm_k1_zmmmt_imm8_512_66_0F3A_W0_D1", Code.MVEX_Undoc_zmm_k1_zmmmt_imm8_512_66_0F3A_W0_D1 }, { "MVEX_Vcvtfxpntpd2dq_zmm_k1_zmmmt_imm8", Code.MVEX_Vcvtfxpntpd2dq_zmm_k1_zmmmt_imm8 }, + { "Via_undoc_F30FA6F0_16", Code.Via_undoc_F30FA6F0_16 }, + { "Via_undoc_F30FA6F0_32", Code.Via_undoc_F30FA6F0_32 }, + { "Via_undoc_F30FA6F0_64", Code.Via_undoc_F30FA6F0_64 }, + { "Via_undoc_F30FA6F8_16", Code.Via_undoc_F30FA6F8_16 }, + { "Via_undoc_F30FA6F8_32", Code.Via_undoc_F30FA6F8_32 }, + { "Via_undoc_F30FA6F8_64", Code.Via_undoc_F30FA6F8_64 }, + { "Xsha512_16", Code.Xsha512_16 }, + { "Xsha512_32", Code.Xsha512_32 }, + { "Xsha512_64", Code.Xsha512_64 }, + { "Xstore2_16", Code.Xstore2_16 }, + { "Xstore2_32", Code.Xstore2_32 }, + { "Xstore2_64", Code.Xstore2_64 }, }; // GENERATOR-END: CodeHash } diff --git a/src/csharp/Intel/Iced.UnitTests/Intel/ToEnumConverter.CpuidFeature.cs b/src/csharp/Intel/Iced.UnitTests/Intel/ToEnumConverter.CpuidFeature.cs index 39113a26d..e93a6081e 100644 --- a/src/csharp/Intel/Iced.UnitTests/Intel/ToEnumConverter.CpuidFeature.cs +++ b/src/csharp/Intel/Iced.UnitTests/Intel/ToEnumConverter.CpuidFeature.cs @@ -14,7 +14,7 @@ static partial class ToEnumConverter { static readonly Dictionary cpuidFeatureDict = // GENERATOR-BEGIN: CpuidFeatureHash // ⚠️This was generated by GENERATOR!🦹‍♂️ - new Dictionary(161, StringComparer.Ordinal) { + new Dictionary(162, StringComparer.Ordinal) { { "INTEL8086", CpuidFeature.INTEL8086 }, { "INTEL8086_ONLY", CpuidFeature.INTEL8086_ONLY }, { "INTEL186", CpuidFeature.INTEL186 }, @@ -176,6 +176,7 @@ static partial class ToEnumConverter { { "AVX512_FP16", CpuidFeature.AVX512_FP16 }, { "UDBG", CpuidFeature.UDBG }, { "KNC", CpuidFeature.KNC }, + { "PADLOCK_UNDOC", CpuidFeature.PADLOCK_UNDOC }, }; // GENERATOR-END: CpuidFeatureHash } diff --git a/src/csharp/Intel/Iced.UnitTests/Intel/ToEnumConverter.Mnemonic.cs b/src/csharp/Intel/Iced.UnitTests/Intel/ToEnumConverter.Mnemonic.cs index 555ab0d2b..4915e78a2 100644 --- a/src/csharp/Intel/Iced.UnitTests/Intel/ToEnumConverter.Mnemonic.cs +++ b/src/csharp/Intel/Iced.UnitTests/Intel/ToEnumConverter.Mnemonic.cs @@ -13,7 +13,7 @@ static partial class ToEnumConverter { static readonly Dictionary mnemonicDict = // GENERATOR-BEGIN: MnemonicHash // ⚠️This was generated by GENERATOR!🦹‍♂️ - new Dictionary(1834, StringComparer.Ordinal) { + new Dictionary(1836, StringComparer.Ordinal) { { "INVALID", Mnemonic.INVALID }, { "Aaa", Mnemonic.Aaa }, { "Aad", Mnemonic.Aad }, @@ -1848,6 +1848,8 @@ static partial class ToEnumConverter { { "Vscatterpf0hintdps", Mnemonic.Vscatterpf0hintdps }, { "Vsubrpd", Mnemonic.Vsubrpd }, { "Vsubrps", Mnemonic.Vsubrps }, + { "Xsha512", Mnemonic.Xsha512 }, + { "Xstore2", Mnemonic.Xstore2 }, }; // GENERATOR-END: MnemonicHash } diff --git a/src/csharp/Intel/Iced/Intel/Assembler/Assembler.g.cs b/src/csharp/Intel/Iced/Intel/Assembler/Assembler.g.cs index 90f8d3b65..0a56e2fb8 100644 --- a/src/csharp/Intel/Iced/Intel/Assembler/Assembler.g.cs +++ b/src/csharp/Intel/Iced/Intel/Assembler/Assembler.g.cs @@ -137138,6 +137138,39 @@ public void xsha256() { AddInstruction(Instruction.Create(code)); } + /// xsha512 instruction.
+ ///
+ /// XSHA512
+ ///
+ /// a64 F3 0F A6 E0
+ ///
+ /// PADLOCK_PHE
+ ///
+ /// 64-bit
+ ///
+ /// XSHA512
+ ///
+ /// a32 F3 0F A6 E0
+ ///
+ /// PADLOCK_PHE
+ ///
+ /// 16/32/64-bit
+ ///
+ /// XSHA512
+ ///
+ /// a16 F3 0F A6 E0
+ ///
+ /// PADLOCK_PHE
+ ///
+ /// 16/32-bit + public void xsha512() { + Code code; + if (Bitness == 64) { + code = Code.Xsha512_64; + } else code = Bitness >= 32 ? Code.Xsha512_32 : Code.Xsha512_16; + AddInstruction(Instruction.Create(code)); + } + /// xstore instruction.
///
/// XSTORE
@@ -137171,6 +137204,39 @@ public void xstore() { AddInstruction(Instruction.Create(code)); } + /// xstore2 instruction.
+ ///
+ /// XSTORE2
+ ///
+ /// a64 F3 0F A7 F8
+ ///
+ /// PADLOCK_RNG
+ ///
+ /// 64-bit
+ ///
+ /// XSTORE2
+ ///
+ /// a32 F3 0F A7 F8
+ ///
+ /// PADLOCK_RNG
+ ///
+ /// 16/32/64-bit
+ ///
+ /// XSTORE2
+ ///
+ /// a16 F3 0F A7 F8
+ ///
+ /// PADLOCK_RNG
+ ///
+ /// 16/32-bit + public void xstore2() { + Code code; + if (Bitness == 64) { + code = Code.Xstore2_64; + } else code = Bitness >= 32 ? Code.Xstore2_32 : Code.Xstore2_16; + AddInstruction(Instruction.Create(code)); + } + /// xsusldtrk instruction.
///
/// XSUSLDTRK
diff --git a/src/csharp/Intel/Iced/Intel/Code.g.cs b/src/csharp/Intel/Iced/Intel/Code.g.cs index d13539fda..98d65b1f7 100644 --- a/src/csharp/Intel/Iced/Intel/Code.g.cs +++ b/src/csharp/Intel/Iced/Intel/Code.g.cs @@ -38522,5 +38522,101 @@ public enum Code { ///
/// 64-bit MVEX_Vcvtfxpntpd2dq_zmm_k1_zmmmt_imm8 = 4817, + /// UNDOC
+ ///
+ /// a16 F3 0F A6 F0
+ ///
+ /// PADLOCK_UNDOC
+ ///
+ /// 16/32-bit + Via_undoc_F30FA6F0_16 = 4818, + /// UNDOC
+ ///
+ /// a32 F3 0F A6 F0
+ ///
+ /// PADLOCK_UNDOC
+ ///
+ /// 16/32/64-bit + Via_undoc_F30FA6F0_32 = 4819, + /// UNDOC
+ ///
+ /// a64 F3 0F A6 F0
+ ///
+ /// PADLOCK_UNDOC
+ ///
+ /// 64-bit + Via_undoc_F30FA6F0_64 = 4820, + /// UNDOC
+ ///
+ /// a16 F3 0F A6 F8
+ ///
+ /// PADLOCK_UNDOC
+ ///
+ /// 16/32-bit + Via_undoc_F30FA6F8_16 = 4821, + /// UNDOC
+ ///
+ /// a32 F3 0F A6 F8
+ ///
+ /// PADLOCK_UNDOC
+ ///
+ /// 16/32/64-bit + Via_undoc_F30FA6F8_32 = 4822, + /// UNDOC
+ ///
+ /// a64 F3 0F A6 F8
+ ///
+ /// PADLOCK_UNDOC
+ ///
+ /// 64-bit + Via_undoc_F30FA6F8_64 = 4823, + /// XSHA512
+ ///
+ /// a16 F3 0F A6 E0
+ ///
+ /// PADLOCK_PHE
+ ///
+ /// 16/32-bit + Xsha512_16 = 4824, + /// XSHA512
+ ///
+ /// a32 F3 0F A6 E0
+ ///
+ /// PADLOCK_PHE
+ ///
+ /// 16/32/64-bit + Xsha512_32 = 4825, + /// XSHA512
+ ///
+ /// a64 F3 0F A6 E0
+ ///
+ /// PADLOCK_PHE
+ ///
+ /// 64-bit + Xsha512_64 = 4826, + /// XSTORE2
+ ///
+ /// a16 F3 0F A7 F8
+ ///
+ /// PADLOCK_RNG
+ ///
+ /// 16/32-bit + Xstore2_16 = 4827, + /// XSTORE2
+ ///
+ /// a32 F3 0F A7 F8
+ ///
+ /// PADLOCK_RNG
+ ///
+ /// 16/32/64-bit + Xstore2_32 = 4828, + /// XSTORE2
+ ///
+ /// a64 F3 0F A7 F8
+ ///
+ /// PADLOCK_RNG
+ ///
+ /// 64-bit + Xstore2_64 = 4829, } } diff --git a/src/csharp/Intel/Iced/Intel/CpuidFeature.g.cs b/src/csharp/Intel/Iced/Intel/CpuidFeature.g.cs index 226f99e1a..c270aeb50 100644 --- a/src/csharp/Intel/Iced/Intel/CpuidFeature.g.cs +++ b/src/csharp/Intel/Iced/Intel/CpuidFeature.g.cs @@ -331,6 +331,8 @@ public enum CpuidFeature { UDBG = 159, /// Intel Knights Corner KNC = 160, + /// Undocumented instruction + PADLOCK_UNDOC = 161, } } #endif diff --git a/src/csharp/Intel/Iced/Intel/DecoderInternal/LegacyOpCodeHandlerKind.g.cs b/src/csharp/Intel/Iced/Intel/DecoderInternal/LegacyOpCodeHandlerKind.g.cs index debc74144..6fe2ce841 100644 --- a/src/csharp/Intel/Iced/Intel/DecoderInternal/LegacyOpCodeHandlerKind.g.cs +++ b/src/csharp/Intel/Iced/Intel/DecoderInternal/LegacyOpCodeHandlerKind.g.cs @@ -222,6 +222,7 @@ enum LegacyOpCodeHandlerKind : byte { PrefixF2, PrefixF3, PrefixREX, + Simple5_a32, } } #endif diff --git a/src/csharp/Intel/Iced/Intel/DecoderInternal/LegacyOpCodeHandlerReader.cs b/src/csharp/Intel/Iced/Intel/DecoderInternal/LegacyOpCodeHandlerReader.cs index c71597136..3b7579145 100644 --- a/src/csharp/Intel/Iced/Intel/DecoderInternal/LegacyOpCodeHandlerReader.cs +++ b/src/csharp/Intel/Iced/Intel/DecoderInternal/LegacyOpCodeHandlerReader.cs @@ -808,6 +808,11 @@ public override int ReadHandlers(ref TableDeserializer deserializer, OpCodeHandl elem = new OpCodeHandler_Simple5(code, code + 1, code + 2); return 1; + case LegacyOpCodeHandlerKind.Simple5_a32: + code = deserializer.ReadCode(); + elem = new OpCodeHandler_Simple5_a32(code, code + 1, code + 2); + return 1; + case LegacyOpCodeHandlerKind.Simple5_ModRM_as: code = deserializer.ReadCode(); elem = new OpCodeHandler_Simple5_ModRM_as(code, code + 1, code + 2); diff --git a/src/csharp/Intel/Iced/Intel/DecoderInternal/OpCodeHandlersTables_Legacy.g.cs b/src/csharp/Intel/Iced/Intel/DecoderInternal/OpCodeHandlersTables_Legacy.g.cs index f84029774..156350e22 100644 --- a/src/csharp/Intel/Iced/Intel/DecoderInternal/OpCodeHandlersTables_Legacy.g.cs +++ b/src/csharp/Intel/Iced/Intel/DecoderInternal/OpCodeHandlersTables_Legacy.g.cs @@ -1966,176 +1966,174 @@ static byte[] GetSerializedTables() => 0x07,// 7 0x02,// Invalid - // handlers_Grp_0FA6_lo + // handlers_Grp_0FA6 0x01,// ArrayReference 0x08,// 0x8 // 0 = 0x00 - 0x05,// Dup - 0x08,// 8 + 0x09,// RM + 0x12,// MandatoryPrefix4 + 0x02,// Invalid + 0x02,// Invalid + 0xD6,// Simple5_a32 + 0xA6, 0x0F,// Montmul_16 + 0x02,// Invalid + 0x00,// 0x0 0x02,// Invalid - // handlers_Grp_0FA6_hi - 0x01,// ArrayReference - 0x40,// 0x40 - // 0 = 0x00 - 0x12,// MandatoryPrefix4 - 0x03,// Invalid_NoModRM - 0x03,// Invalid_NoModRM - 0xAB,// Simple5 - 0xA6, 0x0F,// Montmul_16 - 0x03,// Invalid_NoModRM - 0x00,// 0x0 - // 1 = 0x01 - 0x05,// Dup - 0x07,// 7 - 0x06,// Null + 0x09,// RM + 0x12,// MandatoryPrefix4 + 0x02,// Invalid + 0x02,// Invalid + 0xAB,// Simple5 + 0xA9, 0x0F,// Xsha1_16 + 0x02,// Invalid + 0x00,// 0x0 + 0x02,// Invalid - // 8 = 0x08 - 0x12,// MandatoryPrefix4 - 0x03,// Invalid_NoModRM - 0x03,// Invalid_NoModRM - 0xAB,// Simple5 - 0xA9, 0x0F,// Xsha1_16 - 0x03,// Invalid_NoModRM - 0x00,// 0x0 + // 2 = 0x02 + 0x09,// RM + 0x12,// MandatoryPrefix4 + 0x02,// Invalid + 0x02,// Invalid + 0xAB,// Simple5 + 0xAC, 0x0F,// Xsha256_16 + 0x02,// Invalid + 0x00,// 0x0 + 0x02,// Invalid - // 9 = 0x09 - 0x05,// Dup - 0x07,// 7 - 0x06,// Null + // 3 = 0x03 + 0x02,// Invalid - // 16 = 0x10 - 0x12,// MandatoryPrefix4 - 0x03,// Invalid_NoModRM - 0x03,// Invalid_NoModRM - 0xAB,// Simple5 - 0xAC, 0x0F,// Xsha256_16 - 0x03,// Invalid_NoModRM - 0x00,// 0x0 + // 4 = 0x04 + 0x09,// RM + 0x12,// MandatoryPrefix4 + 0x02,// Invalid + 0x02,// Invalid + 0xAB,// Simple5 + 0xD8, 0x25,// Xsha512_16 + 0x02,// Invalid + 0x00,// 0x0 + 0x02,// Invalid - // 17 = 0x11 - 0x05,// Dup - 0x17,// 23 - 0x06,// Null + // 5 = 0x05 + 0x09,// RM + 0x12,// MandatoryPrefix4 + 0x02,// Invalid + 0x02,// Invalid + 0xAB,// Simple5 + 0xD8, 0x21,// Ccs_hash_16 + 0x02,// Invalid + 0x00,// 0x0 + 0x02,// Invalid - // 40 = 0x28 - 0x12,// MandatoryPrefix4 - 0x03,// Invalid_NoModRM - 0x03,// Invalid_NoModRM - 0xAB,// Simple5 - 0xD8, 0x21,// Ccs_hash_16 - 0x03,// Invalid_NoModRM - 0x00,// 0x0 + // 6 = 0x06 + 0x09,// RM + 0x12,// MandatoryPrefix4 + 0x02,// Invalid + 0x02,// Invalid + 0xAB,// Simple5 + 0xD2, 0x25,// Via_undoc_F30FA6F0_16 + 0x02,// Invalid + 0x00,// 0x0 + 0x02,// Invalid - // 41 = 0x29 - 0x05,// Dup - 0x17,// 23 - 0x06,// Null + // 7 = 0x07 + 0x09,// RM + 0x12,// MandatoryPrefix4 + 0x02,// Invalid + 0x02,// Invalid + 0xAB,// Simple5 + 0xD5, 0x25,// Via_undoc_F30FA6F8_16 + 0x02,// Invalid + 0x00,// 0x0 + 0x02,// Invalid - // handlers_Grp_0FA7_lo + // handlers_Grp_0FA7 0x01,// ArrayReference 0x08,// 0x8 // 0 = 0x00 - 0x05,// Dup - 0x08,// 8 + 0x09,// RM + 0xAB,// Simple5 + 0xB1, 0x0F,// Xstore_16 0x02,// Invalid - // handlers_Grp_0FA7_hi - 0x01,// ArrayReference - 0x40,// 0x40 - // 0 = 0x00 - 0xAB,// Simple5 - 0xB1, 0x0F,// Xstore_16 - // 1 = 0x01 - 0x05,// Dup - 0x07,// 7 - 0x06,// Null - - // 8 = 0x08 - 0x12,// MandatoryPrefix4 - 0x03,// Invalid_NoModRM - 0x03,// Invalid_NoModRM - 0xAB,// Simple5 - 0xB4, 0x0F,// Xcryptecb_16 - 0x03,// Invalid_NoModRM - 0x00,// 0x0 - - // 9 = 0x09 - 0x05,// Dup - 0x07,// 7 - 0x06,// Null - - // 16 = 0x10 - 0x12,// MandatoryPrefix4 - 0x03,// Invalid_NoModRM - 0x03,// Invalid_NoModRM - 0xAB,// Simple5 - 0xB7, 0x0F,// Xcryptcbc_16 - 0x03,// Invalid_NoModRM - 0x00,// 0x0 - - // 17 = 0x11 - 0x05,// Dup - 0x07,// 7 - 0x06,// Null - - // 24 = 0x18 - 0x12,// MandatoryPrefix4 - 0x03,// Invalid_NoModRM - 0x03,// Invalid_NoModRM - 0xAB,// Simple5 - 0xBA, 0x0F,// Xcryptctr_16 - 0x03,// Invalid_NoModRM - 0x00,// 0x0 - - // 25 = 0x19 - 0x05,// Dup - 0x07,// 7 - 0x06,// Null + 0x09,// RM + 0x12,// MandatoryPrefix4 + 0x02,// Invalid + 0x02,// Invalid + 0xAB,// Simple5 + 0xB4, 0x0F,// Xcryptecb_16 + 0x02,// Invalid + 0x00,// 0x0 + 0x02,// Invalid - // 32 = 0x20 - 0x12,// MandatoryPrefix4 - 0x03,// Invalid_NoModRM - 0x03,// Invalid_NoModRM - 0xAB,// Simple5 - 0xBD, 0x0F,// Xcryptcfb_16 - 0x03,// Invalid_NoModRM - 0x00,// 0x0 + // 2 = 0x02 + 0x09,// RM + 0x12,// MandatoryPrefix4 + 0x02,// Invalid + 0x02,// Invalid + 0xAB,// Simple5 + 0xB7, 0x0F,// Xcryptcbc_16 + 0x02,// Invalid + 0x00,// 0x0 + 0x02,// Invalid - // 33 = 0x21 - 0x05,// Dup - 0x07,// 7 - 0x06,// Null + // 3 = 0x03 + 0x09,// RM + 0x12,// MandatoryPrefix4 + 0x02,// Invalid + 0x02,// Invalid + 0xAB,// Simple5 + 0xBA, 0x0F,// Xcryptctr_16 + 0x02,// Invalid + 0x00,// 0x0 + 0x02,// Invalid - // 40 = 0x28 - 0x12,// MandatoryPrefix4 - 0x03,// Invalid_NoModRM - 0x03,// Invalid_NoModRM - 0xAB,// Simple5 - 0xC0, 0x0F,// Xcryptofb_16 - 0x03,// Invalid_NoModRM - 0x00,// 0x0 + // 4 = 0x04 + 0x09,// RM + 0x12,// MandatoryPrefix4 + 0x02,// Invalid + 0x02,// Invalid + 0xAB,// Simple5 + 0xBD, 0x0F,// Xcryptcfb_16 + 0x02,// Invalid + 0x00,// 0x0 + 0x02,// Invalid - // 41 = 0x29 - 0x05,// Dup - 0x07,// 7 - 0x06,// Null + // 5 = 0x05 + 0x09,// RM + 0x12,// MandatoryPrefix4 + 0x02,// Invalid + 0x02,// Invalid + 0xAB,// Simple5 + 0xC0, 0x0F,// Xcryptofb_16 + 0x02,// Invalid + 0x00,// 0x0 + 0x02,// Invalid - // 48 = 0x30 - 0x12,// MandatoryPrefix4 - 0x03,// Invalid_NoModRM - 0x03,// Invalid_NoModRM - 0xAB,// Simple5 - 0xDB, 0x21,// Ccs_encrypt_16 - 0x03,// Invalid_NoModRM - 0x00,// 0x0 + // 6 = 0x06 + 0x09,// RM + 0x12,// MandatoryPrefix4 + 0x02,// Invalid + 0x02,// Invalid + 0xAB,// Simple5 + 0xDB, 0x21,// Ccs_encrypt_16 + 0x02,// Invalid + 0x00,// 0x0 + 0x02,// Invalid - // 49 = 0x31 - 0x05,// Dup - 0x0F,// 15 - 0x06,// Null + // 7 = 0x07 + 0x09,// RM + 0x12,// MandatoryPrefix4 + 0x02,// Invalid + 0x02,// Invalid + 0xAB,// Simple5 + 0xDB, 0x25,// Xstore2_16 + 0x02,// Invalid + 0x00,// 0x0 + 0x02,// Invalid // handlers_Grp_0FBA 0x01,// ArrayReference @@ -2870,10 +2868,10 @@ static byte[] GetSerializedTables() => 0x00,// HandlerReference 0x09,// RM 0x07,// HandlerReference - 0x37,// 0x37 = reservedNop_0F0D + 0x35,// 0x35 = reservedNop_0F0D 0x0E,// Group 0x08,// ArrayReference - 0x40,// 0x40 = handlers_Grp_0F0D_mem + 0x3E,// 0x3E = handlers_Grp_0F0D_mem // handlers_Grp_0F18_mem 0x01,// ArrayReference @@ -2898,19 +2896,19 @@ static byte[] GetSerializedTables() => 0x05,// Dup 0x04,// 4 0x07,// HandlerReference - 0x38,// 0x38 = reservedNop_0F18 + 0x36,// 0x36 = reservedNop_0F18 // grp0F18 0x00,// HandlerReference 0x9E,// Reservednop 0x07,// HandlerReference - 0x38,// 0x38 = reservedNop_0F18 + 0x36,// 0x36 = reservedNop_0F18 0x09,// RM 0x07,// HandlerReference - 0x38,// 0x38 = reservedNop_0F18 + 0x36,// 0x36 = reservedNop_0F18 0x0E,// Group 0x08,// ArrayReference - 0x42,// 0x42 = handlers_Grp_0F18_mem + 0x40,// 0x40 = handlers_Grp_0F18_mem // handlers_Grp_0F1C_mem 0x01,// ArrayReference @@ -2920,30 +2918,30 @@ static byte[] GetSerializedTables() => 0x6E,// M_1 0x9B, 0x08,// Cldemote_m8 0x07,// HandlerReference - 0x3C,// 0x3C = reservedNop_0F1C + 0x3A,// 0x3A = reservedNop_0F1C 0x07,// HandlerReference - 0x3C,// 0x3C = reservedNop_0F1C + 0x3A,// 0x3A = reservedNop_0F1C 0x07,// HandlerReference - 0x3C,// 0x3C = reservedNop_0F1C + 0x3A,// 0x3A = reservedNop_0F1C 0x00,// 0x0 // 1 = 0x01 0x05,// Dup 0x07,// 7 0x07,// HandlerReference - 0x3C,// 0x3C = reservedNop_0F1C + 0x3A,// 0x3A = reservedNop_0F1C // grp0F1C 0x00,// HandlerReference 0x9E,// Reservednop 0x07,// HandlerReference - 0x3C,// 0x3C = reservedNop_0F1C + 0x3A,// 0x3A = reservedNop_0F1C 0x09,// RM 0x07,// HandlerReference - 0x3C,// 0x3C = reservedNop_0F1C + 0x3A,// 0x3A = reservedNop_0F1C 0x0E,// Group 0x08,// ArrayReference - 0x44,// 0x44 = handlers_Grp_0F1C_mem + 0x42,// 0x42 = handlers_Grp_0F1C_mem // handlers_Grp_0F1E_reg_lo 0x01,// ArrayReference @@ -2952,23 +2950,23 @@ static byte[] GetSerializedTables() => 0x05,// Dup 0x08,// 8 0x07,// HandlerReference - 0x3E,// 0x3E = reservedNop_0F1E + 0x3C,// 0x3C = reservedNop_0F1E // grp0F1E_1 0x00,// HandlerReference 0x11,// MandatoryPrefix 0x07,// HandlerReference - 0x3E,// 0x3E = reservedNop_0F1E + 0x3C,// 0x3C = reservedNop_0F1E 0x07,// HandlerReference - 0x3E,// 0x3E = reservedNop_0F1E + 0x3C,// 0x3C = reservedNop_0F1E 0x09,// RM 0x44,// Ev_REXW 0x9C, 0x08,// Rdsspd_r32 0x01,// 0x1 0x07,// HandlerReference - 0x3E,// 0x3E = reservedNop_0F1E + 0x3C,// 0x3C = reservedNop_0F1E 0x07,// HandlerReference - 0x3E,// 0x3E = reservedNop_0F1E + 0x3C,// 0x3C = reservedNop_0F1E // handlers_Grp_0F1E_reg_hi 0x01,// ArrayReference @@ -2982,7 +2980,7 @@ static byte[] GetSerializedTables() => 0x05,// Dup 0x08,// 8 0x07,// HandlerReference - 0x47,// 0x47 = grp0F1E_1 + 0x45,// 0x45 = grp0F1E_1 // 16 = 0x10 0x05,// Dup @@ -2992,24 +2990,24 @@ static byte[] GetSerializedTables() => // 58 = 0x3A 0x11,// MandatoryPrefix 0x07,// HandlerReference - 0x3E,// 0x3E = reservedNop_0F1E + 0x3C,// 0x3C = reservedNop_0F1E 0x07,// HandlerReference - 0x3E,// 0x3E = reservedNop_0F1E + 0x3C,// 0x3C = reservedNop_0F1E 0xA5,// Simple_ModRM 0x9E, 0x08,// Endbr64 0x07,// HandlerReference - 0x3E,// 0x3E = reservedNop_0F1E + 0x3C,// 0x3C = reservedNop_0F1E // 59 = 0x3B 0x11,// MandatoryPrefix 0x07,// HandlerReference - 0x3E,// 0x3E = reservedNop_0F1E + 0x3C,// 0x3C = reservedNop_0F1E 0x07,// HandlerReference - 0x3E,// 0x3E = reservedNop_0F1E + 0x3C,// 0x3C = reservedNop_0F1E 0xA5,// Simple_ModRM 0x9F, 0x08,// Endbr32 0x07,// HandlerReference - 0x3E,// 0x3E = reservedNop_0F1E + 0x3C,// 0x3C = reservedNop_0F1E // 60 = 0x3C 0x05,// Dup @@ -3020,15 +3018,15 @@ static byte[] GetSerializedTables() => 0x00,// HandlerReference 0x9E,// Reservednop 0x07,// HandlerReference - 0x3E,// 0x3E = reservedNop_0F1E + 0x3C,// 0x3C = reservedNop_0F1E 0x09,// RM 0x0F,// Group8x64 0x08,// ArrayReference - 0x46,// 0x46 = handlers_Grp_0F1E_reg_lo + 0x44,// 0x44 = handlers_Grp_0F1E_reg_lo 0x08,// ArrayReference - 0x48,// 0x48 = handlers_Grp_0F1E_reg_hi + 0x46,// 0x46 = handlers_Grp_0F1E_reg_hi 0x07,// HandlerReference - 0x3E,// 0x3E = reservedNop_0F1E + 0x3C,// 0x3C = reservedNop_0F1E // handlers_Grp_0F1F 0x01,// ArrayReference @@ -3041,16 +3039,16 @@ static byte[] GetSerializedTables() => 0x05,// Dup 0x07,// 7 0x07,// HandlerReference - 0x3F,// 0x3F = reservedNop_0F1F + 0x3D,// 0x3D = reservedNop_0F1F // grp0F1F 0x00,// HandlerReference 0x9E,// Reservednop 0x07,// HandlerReference - 0x3F,// 0x3F = reservedNop_0F1F + 0x3D,// 0x3D = reservedNop_0F1F 0x0E,// Group 0x08,// ArrayReference - 0x4A,// 0x4A = handlers_Grp_0F1F + 0x48,// 0x48 = handlers_Grp_0F1F // handlers_Grp_660F78 0x01,// ArrayReference @@ -3654,7 +3652,7 @@ static byte[] GetSerializedTables() => 0x02,// Invalid 0x0E,// Group 0x08,// ArrayReference - 0x4D,// 0x4D = handlers_Grp_F30F38D8 + 0x4B,// 0x4B = handlers_Grp_F30F38D8 0x02,// Invalid // 217 = 0xD9 @@ -4082,9 +4080,9 @@ static byte[] GetSerializedTables() => // 240 = 0xF0 0x0F,// Group8x64 0x08,// ArrayReference - 0x4E,// 0x4E = handlers_Grp_0F3AF0_lo + 0x4C,// 0x4C = handlers_Grp_0F3AF0_lo 0x08,// ArrayReference - 0x4F,// 0x4F = handlers_Grp_0F3AF0_hi + 0x4D,// 0x4D = handlers_Grp_0F3AF0_hi // 241 = 0xF1 0x05,// Dup @@ -4179,9 +4177,9 @@ static byte[] GetSerializedTables() => // 13 = 0x0D 0x9E,// Reservednop 0x07,// HandlerReference - 0x37,// 0x37 = reservedNop_0F0D + 0x35,// 0x35 = reservedNop_0F0D 0x07,// HandlerReference - 0x41,// 0x41 = grp0F0D + 0x3F,// 0x3F = grp0F0D // 14 = 0x0E 0x0A,// Options3 @@ -4336,23 +4334,23 @@ static byte[] GetSerializedTables() => // 24 = 0x18 0x07,// HandlerReference - 0x43,// 0x43 = grp0F18 + 0x41,// 0x41 = grp0F18 // 25 = 0x19 0x07,// HandlerReference - 0x39,// 0x39 = reservedNop_0F19 + 0x37,// 0x37 = reservedNop_0F19 // 26 = 0x1A 0x9E,// Reservednop 0x07,// HandlerReference - 0x3A,// 0x3A = reservedNop_0F1A + 0x38,// 0x38 = reservedNop_0F1A 0x0C,// Options_DontReadModRM 0x07,// HandlerReference - 0x3A,// 0x3A = reservedNop_0F1A + 0x38,// 0x38 = reservedNop_0F1A 0x11,// MandatoryPrefix 0x09,// RM 0x07,// HandlerReference - 0x3A,// 0x3A = reservedNop_0F1A + 0x38,// 0x38 = reservedNop_0F1A 0x1F,// B_MIB 0x8D, 0x08,// Bndldx_bnd_mib 0x1D,// B_BM @@ -4368,21 +4366,21 @@ static byte[] GetSerializedTables() => // 27 = 0x1B 0x9E,// Reservednop 0x07,// HandlerReference - 0x3B,// 0x3B = reservedNop_0F1B + 0x39,// 0x39 = reservedNop_0F1B 0x0C,// Options_DontReadModRM 0x07,// HandlerReference - 0x3B,// 0x3B = reservedNop_0F1B + 0x39,// 0x39 = reservedNop_0F1B 0x11,// MandatoryPrefix 0x09,// RM 0x07,// HandlerReference - 0x3B,// 0x3B = reservedNop_0F1B + 0x39,// 0x39 = reservedNop_0F1B 0x76,// MIB_B 0x94, 0x08,// Bndstx_mib_bnd 0x20,// BM_B 0x95, 0x08,// Bndmov_bndm64_bnd 0x09,// RM 0x07,// HandlerReference - 0x3B,// 0x3B = reservedNop_0F1B + 0x39,// 0x39 = reservedNop_0F1B 0x1E,// B_Ev 0x97, 0x08,// Bndmk_bnd_m32 0x00,// false @@ -4393,19 +4391,19 @@ static byte[] GetSerializedTables() => // 28 = 0x1C 0x07,// HandlerReference - 0x45,// 0x45 = grp0F1C + 0x43,// 0x43 = grp0F1C // 29 = 0x1D 0x07,// HandlerReference - 0x3D,// 0x3D = reservedNop_0F1D + 0x3B,// 0x3B = reservedNop_0F1D // 30 = 0x1E 0x07,// HandlerReference - 0x49,// 0x49 = grp0F1E + 0x47,// 0x47 = grp0F1E // 31 = 0x1F 0x07,// HandlerReference - 0x4B,// 0x4B = grp0F1F + 0x49,// 0x49 = grp0F1F // 32 = 0x20 0x8D,// R_C_3a @@ -4583,7 +4581,7 @@ static byte[] GetSerializedTables() => 0xC8,// Options1632_1 0x0D,// AnotherTable 0x08,// ArrayReference - 0x50,// 0x50 = Handlers_0F38 + 0x4E,// 0x4E = Handlers_0F38 0xA4,// Simple 0x90, 0x21,// Smint 0x80, 0x80, 0x40,// Cyrix @@ -4599,7 +4597,7 @@ static byte[] GetSerializedTables() => 0xC9,// Options1632_2 0x0D,// AnotherTable 0x08,// ArrayReference - 0x51,// 0x51 = Handlers_0F3A + 0x4F,// 0x4F = Handlers_0F3A 0xA4,// Simple 0x92, 0x21,// Rdm 0x80, 0x80, 0x80, 0x02,// Cyrix_DMI @@ -5080,17 +5078,17 @@ static byte[] GetSerializedTables() => // 113 = 0x71 0x0E,// Group 0x08,// ArrayReference - 0x32,// 0x32 = handlers_Grp_0F71 + 0x30,// 0x30 = handlers_Grp_0F71 // 114 = 0x72 0x0E,// Group 0x08,// ArrayReference - 0x33,// 0x33 = handlers_Grp_0F72 + 0x31,// 0x31 = handlers_Grp_0F72 // 115 = 0x73 0x0E,// Group 0x08,// ArrayReference - 0x34,// 0x34 = handlers_Grp_0F73 + 0x32,// 0x32 = handlers_Grp_0F73 // 116 = 0x74 0x11,// MandatoryPrefix @@ -5134,7 +5132,7 @@ static byte[] GetSerializedTables() => 0xCA, 0x0D,// Vmread_rm32_r32 0x0E,// Group 0x08,// ArrayReference - 0x4C,// 0x4C = handlers_Grp_660F78 + 0x4A,// 0x4A = handlers_Grp_660F78 0x02,// Invalid 0xB6,// VRIbIb 0xDB, 0x0D,// Insertq_xmm_xmm_imm8_imm8 @@ -5389,42 +5387,34 @@ static byte[] GetSerializedTables() => // 166 = 0xA6 0x00,// Bitness 0x0B,// Options5 - 0x0F,// Group8x64 - 0x08,// ArrayReference - 0x28,// 0x28 = handlers_Grp_0FA6_lo + 0x0E,// Group 0x08,// ArrayReference - 0x29,// 0x29 = handlers_Grp_0FA6_hi + 0x28,// 0x28 = handlers_Grp_0FA6 0x51,// Gv_Ev_3b 0xAF, 0x0F,// Xbts_r16_rm16 0x10,// Xbts 0x2B,// Eb_Gb_1 0xC5, 0x0F,// Cmpxchg486_rm8_r8 0x20,// Cmpxchg486A - 0x0F,// Group8x64 - 0x08,// ArrayReference - 0x28,// 0x28 = handlers_Grp_0FA6_lo + 0x0E,// Group 0x08,// ArrayReference - 0x29,// 0x29 = handlers_Grp_0FA6_hi + 0x28,// 0x28 = handlers_Grp_0FA6 // 167 = 0xA7 0x00,// Bitness 0x0B,// Options5 - 0x0F,// Group8x64 - 0x08,// ArrayReference - 0x2A,// 0x2A = handlers_Grp_0FA7_lo + 0x0E,// Group 0x08,// ArrayReference - 0x2B,// 0x2B = handlers_Grp_0FA7_hi + 0x29,// 0x29 = handlers_Grp_0FA7 0x38,// Ev_Gv_3b 0xC3, 0x0F,// Ibts_rm16_r16 0x10,// Xbts 0x38,// Ev_Gv_3b 0xC6, 0x0F,// Cmpxchg486_rm16_r16 0x20,// Cmpxchg486A - 0x0F,// Group8x64 - 0x08,// ArrayReference - 0x2A,// 0x2A = handlers_Grp_0FA7_lo + 0x0E,// Group 0x08,// ArrayReference - 0x2B,// 0x2B = handlers_Grp_0FA7_hi + 0x29,// 0x29 = handlers_Grp_0FA7 // 168 = 0xA8 0x88,// PushOpSizeReg_4a @@ -5456,9 +5446,9 @@ static byte[] GetSerializedTables() => // 174 = 0xAE 0x0F,// Group8x64 0x08,// ArrayReference - 0x35,// 0x35 = handlers_Grp_0FAE_lo + 0x33,// 0x33 = handlers_Grp_0FAE_lo 0x08,// ArrayReference - 0x36,// 0x36 = handlers_Grp_0FAE_hi + 0x34,// 0x34 = handlers_Grp_0FAE_hi // 175 = 0xAF 0x50,// Gv_Ev_3a @@ -5527,7 +5517,7 @@ static byte[] GetSerializedTables() => // 186 = 0xBA 0x0E,// Group 0x08,// ArrayReference - 0x2C,// 0x2C = handlers_Grp_0FBA + 0x2A,// 0x2A = handlers_Grp_0FBA // 187 = 0xBB 0x39,// Ev_Gv_4 @@ -5635,7 +5625,7 @@ static byte[] GetSerializedTables() => // 199 = 0xC7 0x0E,// Group 0x08,// ArrayReference - 0x2D,// 0x2D = handlers_Grp_0FC7 + 0x2B,// 0x2B = handlers_Grp_0FC7 // 200 = 0xC8 0xAD,// SimpleReg @@ -6190,7 +6180,7 @@ static byte[] GetSerializedTables() => // 15 = 0x0F 0x0D,// AnotherTable 0x08,// ArrayReference - 0x52,// 0x52 = Handlers_0F + 0x50,// 0x50 = Handlers_0F // 16 = 0x10 0x2C,// Eb_Gb_2 @@ -7071,16 +7061,16 @@ static byte[] GetSerializedTables() => // 198 = 0xC6 0x0F,// Group8x64 0x08,// ArrayReference - 0x2E,// 0x2E = handlers_Grp_C6_lo + 0x2C,// 0x2C = handlers_Grp_C6_lo 0x08,// ArrayReference - 0x2F,// 0x2F = handlers_Grp_C6_hi + 0x2D,// 0x2D = handlers_Grp_C6_hi // 199 = 0xC7 0x0F,// Group8x64 0x08,// ArrayReference - 0x30,// 0x30 = handlers_Grp_C7_lo + 0x2E,// 0x2E = handlers_Grp_C7_lo 0x08,// ArrayReference - 0x31,// 0x31 = handlers_Grp_C7_hi + 0x2F,// 0x2F = handlers_Grp_C7_hi // 200 = 0xC8 0x68,// Iw_Ib @@ -7371,8 +7361,8 @@ static byte[] GetSerializedTables() => 0x08,// ArrayReference 0x1E,// 0x1E = handlers_Grp_FF }; - const int MaxIdNames = 84; - const uint Handlers_MAP0Index = 83; + const int MaxIdNames = 82; + const uint Handlers_MAP0Index = 81; } } #endif diff --git a/src/csharp/Intel/Iced/Intel/DecoderInternal/OpCodeHandlers_Legacy.cs b/src/csharp/Intel/Iced/Intel/DecoderInternal/OpCodeHandlers_Legacy.cs index 8911c8a0d..85c6728bf 100644 --- a/src/csharp/Intel/Iced/Intel/DecoderInternal/OpCodeHandlers_Legacy.cs +++ b/src/csharp/Intel/Iced/Intel/DecoderInternal/OpCodeHandlers_Legacy.cs @@ -2259,6 +2259,31 @@ public override void Decode(Decoder decoder, ref Instruction instruction) { } } + sealed class OpCodeHandler_Simple5_a32 : OpCodeHandler { + readonly Code code16; + readonly Code code32; + readonly Code code64; + + public OpCodeHandler_Simple5_a32(Code code16, Code code32, Code code64) { + this.code16 = code16; + this.code32 = code32; + this.code64 = code64; + } + + public override void Decode(Decoder decoder, ref Instruction instruction) { + ref var state = ref decoder.state; + Debug.Assert(state.Encoding == EncodingKind.Legacy); + if (state.addressSize != OpSize.Size32 && decoder.invalidCheckMask != 0) + decoder.SetInvalidInstruction(); + if (state.addressSize == OpSize.Size64) + instruction.Code = code64; + else if (state.addressSize == OpSize.Size32) + instruction.Code = code32; + else + instruction.Code = code16; + } + } + sealed class OpCodeHandler_Simple5_ModRM_as : OpCodeHandlerModRM { readonly Code code16; readonly Code code32; diff --git a/src/csharp/Intel/Iced/Intel/EncoderInternal/EncoderData.g.cs b/src/csharp/Intel/Iced/Intel/EncoderInternal/EncoderData.g.cs index e60ba42f5..cccfef049 100644 --- a/src/csharp/Intel/Iced/Intel/EncoderInternal/EncoderData.g.cs +++ b/src/csharp/Intel/Iced/Intel/EncoderInternal/EncoderData.g.cs @@ -13,7 +13,7 @@ static class EncoderData { internal static readonly uint[] EncFlags3 = GetEncFlags3(); static uint[] GetEncFlags1() => - new uint[4818] { + new uint[4830] { 0x00000000,// INVALID 0x00000000,// DeclareByte 0x00000000,// DeclareWord @@ -4832,10 +4832,22 @@ static uint[] GetEncFlags1() => 0x00000836,// MVEX_Undoc_zmm_k1_zmmmt_imm8_512_66_0F3A_W0_D0 0x00000836,// MVEX_Undoc_zmm_k1_zmmmt_imm8_512_66_0F3A_W0_D1 0x00000836,// MVEX_Vcvtfxpntpd2dq_zmm_k1_zmmmt_imm8 + 0x00000000,// Via_undoc_F30FA6F0_16 + 0x00000000,// Via_undoc_F30FA6F0_32 + 0x00000000,// Via_undoc_F30FA6F0_64 + 0x00000000,// Via_undoc_F30FA6F8_16 + 0x00000000,// Via_undoc_F30FA6F8_32 + 0x00000000,// Via_undoc_F30FA6F8_64 + 0x00000000,// Xsha512_16 + 0x00000000,// Xsha512_32 + 0x00000000,// Xsha512_64 + 0x00000000,// Xstore2_16 + 0x00000000,// Xstore2_32 + 0x00000000,// Xstore2_64 }; static uint[] GetEncFlags2() => - new uint[4818] { + new uint[4830] { 0x00000000,// INVALID 0x00000000,// DeclareByte 0x00000000,// DeclareWord @@ -9654,10 +9666,22 @@ static uint[] GetEncFlags2() => 0x461600D0,// MVEX_Undoc_zmm_k1_zmmmt_imm8_512_66_0F3A_W0_D0 0x461600D1,// MVEX_Undoc_zmm_k1_zmmmt_imm8_512_66_0F3A_W0_D1 0x467600E6,// MVEX_Vcvtfxpntpd2dq_zmm_k1_zmmmt_imm8 + 0x4023A6F0,// Via_undoc_F30FA6F0_16 + 0x4023A6F0,// Via_undoc_F30FA6F0_32 + 0x4023A6F0,// Via_undoc_F30FA6F0_64 + 0x4023A6F8,// Via_undoc_F30FA6F8_16 + 0x4023A6F8,// Via_undoc_F30FA6F8_32 + 0x4023A6F8,// Via_undoc_F30FA6F8_64 + 0x4023A6E0,// Xsha512_16 + 0x4023A6E0,// Xsha512_32 + 0x4023A6E0,// Xsha512_64 + 0x4023A7F8,// Xstore2_16 + 0x4023A7F8,// Xstore2_32 + 0x4023A7F8,// Xstore2_64 }; static uint[] GetEncFlags3() => - new uint[4818] { + new uint[4830] { 0x00030000,// INVALID 0x00030000,// DeclareByte 0x00030000,// DeclareWord @@ -14476,6 +14500,18 @@ static uint[] GetEncFlags3() => 0x38020005,// MVEX_Undoc_zmm_k1_zmmmt_imm8_512_66_0F3A_W0_D0 0x38020005,// MVEX_Undoc_zmm_k1_zmmmt_imm8_512_66_0F3A_W0_D1 0x38020005,// MVEX_Vcvtfxpntpd2dq_zmm_k1_zmmmt_imm8 + 0x00010020,// Via_undoc_F30FA6F0_16 + 0x00030040,// Via_undoc_F30FA6F0_32 + 0x00020060,// Via_undoc_F30FA6F0_64 + 0x00010020,// Via_undoc_F30FA6F8_16 + 0x00030040,// Via_undoc_F30FA6F8_32 + 0x00020060,// Via_undoc_F30FA6F8_64 + 0x00010020,// Xsha512_16 + 0x00030040,// Xsha512_32 + 0x00020060,// Xsha512_64 + 0x00010020,// Xstore2_16 + 0x00030040,// Xstore2_32 + 0x00020060,// Xstore2_64 }; } } diff --git a/src/csharp/Intel/Iced/Intel/EncoderInternal/OpCodeInfoData.g.cs b/src/csharp/Intel/Iced/Intel/EncoderInternal/OpCodeInfoData.g.cs index d5172c35f..b26164307 100644 --- a/src/csharp/Intel/Iced/Intel/EncoderInternal/OpCodeInfoData.g.cs +++ b/src/csharp/Intel/Iced/Intel/EncoderInternal/OpCodeInfoData.g.cs @@ -12,7 +12,7 @@ static class OpCodeInfoData { internal static readonly uint[] OpcFlags2 = GetOpcFlags2(); static uint[] GetOpcFlags1() => - new uint[4818] { + new uint[4830] { 0x00000000,// INVALID 0x00000000,// DeclareByte 0x00000000,// DeclareWord @@ -4831,10 +4831,22 @@ static uint[] GetOpcFlags1() => 0x02210000,// MVEX_Undoc_zmm_k1_zmmmt_imm8_512_66_0F3A_W0_D0 0x02210000,// MVEX_Undoc_zmm_k1_zmmmt_imm8_512_66_0F3A_W0_D1 0x02200000,// MVEX_Vcvtfxpntpd2dq_zmm_k1_zmmmt_imm8 + 0x00010000,// Via_undoc_F30FA6F0_16 + 0x00010000,// Via_undoc_F30FA6F0_32 + 0x00010000,// Via_undoc_F30FA6F0_64 + 0x00010000,// Via_undoc_F30FA6F8_16 + 0x00010000,// Via_undoc_F30FA6F8_32 + 0x00010000,// Via_undoc_F30FA6F8_64 + 0x00000000,// Xsha512_16 + 0x00000000,// Xsha512_32 + 0x00000000,// Xsha512_64 + 0x00000000,// Xstore2_16 + 0x00000000,// Xstore2_32 + 0x00000000,// Xstore2_64 }; static uint[] GetOpcFlags2() => - new uint[4818] { + new uint[4830] { 0x1E003FFF,// INVALID 0x1E003FFF,// DeclareByte 0x1E003FFF,// DeclareWord @@ -9653,6 +9665,18 @@ static uint[] GetOpcFlags2() => 0x14003FF0,// MVEX_Undoc_zmm_k1_zmmmt_imm8_512_66_0F3A_W0_D0 0x14003FF0,// MVEX_Undoc_zmm_k1_zmmmt_imm8_512_66_0F3A_W0_D1 0x14003FF0,// MVEX_Vcvtfxpntpd2dq_zmm_k1_zmmmt_imm8 + 0x0A003FFF,// Via_undoc_F30FA6F0_16 + 0x1E003FFF,// Via_undoc_F30FA6F0_32 + 0x14003FF0,// Via_undoc_F30FA6F0_64 + 0x0A003FFF,// Via_undoc_F30FA6F8_16 + 0x1E003FFF,// Via_undoc_F30FA6F8_32 + 0x14003FF0,// Via_undoc_F30FA6F8_64 + 0x0A003FFF,// Xsha512_16 + 0x1E003FFF,// Xsha512_32 + 0x14003FF0,// Xsha512_64 + 0x0A003FFF,// Xstore2_16 + 0x1E003FFF,// Xstore2_32 + 0x14003FF0,// Xstore2_64 }; } } diff --git a/src/csharp/Intel/Iced/Intel/FastFormatterInternal/FmtData.g.cs b/src/csharp/Intel/Iced/Intel/FastFormatterInternal/FmtData.g.cs index 1a9314281..0eb8c14d4 100644 --- a/src/csharp/Intel/Iced/Intel/FastFormatterInternal/FmtData.g.cs +++ b/src/csharp/Intel/Iced/Intel/FastFormatterInternal/FmtData.g.cs @@ -16580,6 +16580,45 @@ static byte[] GetSerializedData() => // MVEX_Vcvtfxpntpd2dq_zmm_k1_zmmmt_imm8 0x00,// No flags set 0x96, 0x0D,// 1686 = "vcvtfxpntpd2dq" + + // Via_undoc_F30FA6F0_16 + 0x00,// No flags set + 0x00,// 0 = "undoc" + + // Via_undoc_F30FA6F0_32 + 0x02,// SameAsPrev + + // Via_undoc_F30FA6F0_64 + 0x02,// SameAsPrev + + // Via_undoc_F30FA6F8_16 + 0x02,// SameAsPrev + + // Via_undoc_F30FA6F8_32 + 0x02,// SameAsPrev + + // Via_undoc_F30FA6F8_64 + 0x02,// SameAsPrev + + // Xsha512_16 + 0x00,// No flags set + 0x97, 0x0D,// 1687 = "xsha512" + + // Xsha512_32 + 0x02,// SameAsPrev + + // Xsha512_64 + 0x02,// SameAsPrev + + // Xstore2_16 + 0x00,// No flags set + 0x98, 0x0D,// 1688 = "xstore2" + + // Xstore2_32 + 0x02,// SameAsPrev + + // Xstore2_64 + 0x02,// SameAsPrev }; } } diff --git a/src/csharp/Intel/Iced/Intel/FormatterInternal/FormatterStringsTable.g.cs b/src/csharp/Intel/Iced/Intel/FormatterInternal/FormatterStringsTable.g.cs index 600fb3097..f0b806c29 100644 --- a/src/csharp/Intel/Iced/Intel/FormatterInternal/FormatterStringsTable.g.cs +++ b/src/csharp/Intel/Iced/Intel/FormatterInternal/FormatterStringsTable.g.cs @@ -9,7 +9,7 @@ namespace Iced.Intel.FormatterInternal { static partial class FormatterStringsTable { const int MaxStringLength = 18; - const int StringsCount = 1687; + const int StringsCount = 1689; #if HAS_SPAN static System.ReadOnlySpan GetSerializedStrings() => #else @@ -1703,6 +1703,8 @@ static byte[] GetSerializedStrings() => 0x0E, 0x76, 0x63, 0x76, 0x74, 0x66, 0x78, 0x70, 0x6E, 0x74, 0x64, 0x71, 0x32, 0x70, 0x73,// vcvtfxpntdq2ps 0x0E, 0x76, 0x63, 0x76, 0x74, 0x66, 0x78, 0x70, 0x6E, 0x74, 0x70, 0x73, 0x32, 0x64, 0x71,// vcvtfxpntps2dq 0x0E, 0x76, 0x63, 0x76, 0x74, 0x66, 0x78, 0x70, 0x6E, 0x74, 0x70, 0x64, 0x32, 0x64, 0x71,// vcvtfxpntpd2dq + 0x07, 0x78, 0x73, 0x68, 0x61, 0x35, 0x31, 0x32,// xsha512 + 0x07, 0x78, 0x73, 0x74, 0x6F, 0x72, 0x65, 0x32,// xstore2 }; } } diff --git a/src/csharp/Intel/Iced/Intel/FormatterInternal/FormatterUtils.All.cs b/src/csharp/Intel/Iced/Intel/FormatterInternal/FormatterUtils.All.cs index 47924e0db..c66043bf4 100644 --- a/src/csharp/Intel/Iced/Intel/FormatterInternal/FormatterUtils.All.cs +++ b/src/csharp/Intel/Iced/Intel/FormatterInternal/FormatterUtils.All.cs @@ -147,6 +147,18 @@ static bool IsRepRepeRepneInstruction(Code code) { case Code.Ccs_encrypt_16: case Code.Ccs_encrypt_32: case Code.Ccs_encrypt_64: + case Code.Via_undoc_F30FA6F0_16: + case Code.Via_undoc_F30FA6F0_32: + case Code.Via_undoc_F30FA6F0_64: + case Code.Via_undoc_F30FA6F8_16: + case Code.Via_undoc_F30FA6F8_32: + case Code.Via_undoc_F30FA6F8_64: + case Code.Xsha512_16: + case Code.Xsha512_32: + case Code.Xsha512_64: + case Code.Xstore2_16: + case Code.Xstore2_32: + case Code.Xstore2_64: return true; default: diff --git a/src/csharp/Intel/Iced/Intel/GasFormatterInternal/InstrInfos.g.cs b/src/csharp/Intel/Iced/Intel/GasFormatterInternal/InstrInfos.g.cs index 836804f7e..0a67e888d 100644 --- a/src/csharp/Intel/Iced/Intel/GasFormatterInternal/InstrInfos.g.cs +++ b/src/csharp/Intel/Iced/Intel/GasFormatterInternal/InstrInfos.g.cs @@ -20133,6 +20133,66 @@ static byte[] GetSerializedInstrInfos() => 0x0B,// er_2 0x96, 0x0D,// 1686 = "vcvtfxpntpd2dq" 0x00,// 0x0 + + // Via_undoc_F30FA6F0_16 + 0x07,// asz + 0x00,// 0 = "undoc" + 0x10,// 0x10 + + // Via_undoc_F30FA6F0_32 + 0x07,// asz + 0x00,// 0 = "undoc" + 0x20,// 0x20 + + // Via_undoc_F30FA6F0_64 + 0x07,// asz + 0x00,// 0 = "undoc" + 0x40,// 0x40 + + // Via_undoc_F30FA6F8_16 + 0x07,// asz + 0x00,// 0 = "undoc" + 0x10,// 0x10 + + // Via_undoc_F30FA6F8_32 + 0x07,// asz + 0x00,// 0 = "undoc" + 0x20,// 0x20 + + // Via_undoc_F30FA6F8_64 + 0x07,// asz + 0x00,// 0 = "undoc" + 0x40,// 0x40 + + // Xsha512_16 + 0x07,// asz + 0x97, 0x0D,// 1687 = "xsha512" + 0x10,// 0x10 + + // Xsha512_32 + 0x07,// asz + 0x97, 0x0D,// 1687 = "xsha512" + 0x20,// 0x20 + + // Xsha512_64 + 0x07,// asz + 0x97, 0x0D,// 1687 = "xsha512" + 0x40,// 0x40 + + // Xstore2_16 + 0x07,// asz + 0x98, 0x0D,// 1688 = "xstore2" + 0x10,// 0x10 + + // Xstore2_32 + 0x07,// asz + 0x98, 0x0D,// 1688 = "xstore2" + 0x20,// 0x20 + + // Xstore2_64 + 0x07,// asz + 0x98, 0x0D,// 1688 = "xstore2" + 0x40,// 0x40 }; } } diff --git a/src/csharp/Intel/Iced/Intel/IcedConstants.g.cs b/src/csharp/Intel/Iced/Intel/IcedConstants.g.cs index fa5f62abd..d9a2a647e 100644 --- a/src/csharp/Intel/Iced/Intel/IcedConstants.g.cs +++ b/src/csharp/Intel/Iced/Intel/IcedConstants.g.cs @@ -17,7 +17,7 @@ static partial class IcedConstants { internal const Register YMM_last = Register.YMM31; internal const Register ZMM_last = Register.ZMM31; internal const Register TMM_last = Register.TMM7; - internal const int MaxCpuidFeatureInternalValues = 182; + internal const int MaxCpuidFeatureInternalValues = 183; internal const MemorySize FirstBroadcastMemorySize = MemorySize.Broadcast32_Float16; internal const uint MvexStart = 4611; internal const uint MvexLength = 207; @@ -33,10 +33,10 @@ static partial class IcedConstants { internal const int CC_ne_EnumCount = 2; internal const int CC_np_EnumCount = 2; internal const int CC_p_EnumCount = 2; - internal const int CodeEnumCount = 4818; + internal const int CodeEnumCount = 4830; internal const int CodeSizeEnumCount = 4; internal const int ConditionCodeEnumCount = 17; - internal const int CpuidFeatureEnumCount = 161; + internal const int CpuidFeatureEnumCount = 162; internal const int DecoderErrorEnumCount = 3; internal const int DecoratorKindEnumCount = 6; internal const int EncodingKindEnumCount = 6; @@ -46,7 +46,7 @@ static partial class IcedConstants { internal const int MandatoryPrefixEnumCount = 5; internal const int MemorySizeEnumCount = 160; internal const int MemorySizeOptionsEnumCount = 4; - internal const int MnemonicEnumCount = 1834; + internal const int MnemonicEnumCount = 1836; internal const int MvexConvFnEnumCount = 13; internal const int MvexEHBitEnumCount = 3; internal const int MvexRegMemConvEnumCount = 17; diff --git a/src/csharp/Intel/Iced/Intel/InstructionInfoFactory.cs b/src/csharp/Intel/Iced/Intel/InstructionInfoFactory.cs index 386a8738f..7d4deda24 100644 --- a/src/csharp/Intel/Iced/Intel/InstructionInfoFactory.cs +++ b/src/csharp/Intel/Iced/Intel/InstructionInfoFactory.cs @@ -1685,6 +1685,51 @@ void AddImpliedAccesses(ImpliedAccess impliedAccess, in Instruction instruction, case ImpliedAccess.t_memdisplm64: CommandMemDispl(flags, -64); break; + case ImpliedAccess.t_CRmem_CRmem_CWmem_CRsi_CRdi_CRes_CWsi_RCWcx: + if ((flags & Flags.NoMemoryUsage) == 0) { + AddMemory(Register.ES, Register.SI, Register.None, 1, 0x0, MemorySize.Unknown, OpAccess.CondRead, CodeSize.Code16, 0); + AddMemory(Register.ES, Register.DI, Register.None, 1, 0x0, MemorySize.Unknown, OpAccess.CondRead, CodeSize.Code16, 0); + AddMemory(Register.ES, Register.DI, Register.None, 1, 0x0, MemorySize.Unknown, OpAccess.CondWrite, CodeSize.Code16, 0); + } + if ((flags & Flags.NoRegisterUsage) == 0) { + AddRegister(flags, Register.SI, OpAccess.CondRead); + AddRegister(flags, Register.DI, OpAccess.CondRead); + if ((flags & Flags.Is64Bit) == 0) + AddRegister(flags, Register.ES, OpAccess.CondRead); + AddRegister(flags, Register.SI, OpAccess.CondWrite); + AddRegister(flags, Register.CX, OpAccess.ReadCondWrite); + } + break; + case ImpliedAccess.t_CRmem_CRmem_CWmem_CResi_CRedi_CRes_CWesi_RCWecx: + if ((flags & Flags.NoMemoryUsage) == 0) { + AddMemory(Register.ES, Register.ESI, Register.None, 1, 0x0, MemorySize.Unknown, OpAccess.CondRead, CodeSize.Code32, 0); + AddMemory(Register.ES, Register.EDI, Register.None, 1, 0x0, MemorySize.Unknown, OpAccess.CondRead, CodeSize.Code32, 0); + AddMemory(Register.ES, Register.EDI, Register.None, 1, 0x0, MemorySize.Unknown, OpAccess.CondWrite, CodeSize.Code32, 0); + } + if ((flags & Flags.NoRegisterUsage) == 0) { + AddRegister(flags, Register.ESI, OpAccess.CondRead); + AddRegister(flags, Register.EDI, OpAccess.CondRead); + if ((flags & Flags.Is64Bit) == 0) + AddRegister(flags, Register.ES, OpAccess.CondRead); + AddRegister(flags, Register.ESI, OpAccess.CondWrite); + AddRegister(flags, Register.ECX, OpAccess.ReadCondWrite); + } + break; + case ImpliedAccess.t_CRmem_CRmem_CWmem_CRrsi_CRrdi_CRes_CWrsi_RCWrcx: + if ((flags & Flags.NoMemoryUsage) == 0) { + AddMemory(Register.ES, Register.RSI, Register.None, 1, 0x0, MemorySize.Unknown, OpAccess.CondRead, CodeSize.Code64, 0); + AddMemory(Register.ES, Register.RDI, Register.None, 1, 0x0, MemorySize.Unknown, OpAccess.CondRead, CodeSize.Code64, 0); + AddMemory(Register.ES, Register.RDI, Register.None, 1, 0x0, MemorySize.Unknown, OpAccess.CondWrite, CodeSize.Code64, 0); + } + if ((flags & Flags.NoRegisterUsage) == 0) { + AddRegister(flags, Register.RSI, OpAccess.CondRead); + AddRegister(flags, Register.RDI, OpAccess.CondRead); + if ((flags & Flags.Is64Bit) == 0) + AddRegister(flags, Register.ES, OpAccess.CondRead); + AddRegister(flags, Register.RSI, OpAccess.CondWrite); + AddRegister(flags, Register.RCX, OpAccess.ReadCondWrite); + } + break; // GENERATOR-END: ImpliedAccessHandler default: diff --git a/src/csharp/Intel/Iced/Intel/InstructionInfoInternal/CpuidFeatureInternal.g.cs b/src/csharp/Intel/Iced/Intel/InstructionInfoInternal/CpuidFeatureInternal.g.cs index 5226e49cd..32b078adf 100644 --- a/src/csharp/Intel/Iced/Intel/InstructionInfoInternal/CpuidFeatureInternal.g.cs +++ b/src/csharp/Intel/Iced/Intel/InstructionInfoInternal/CpuidFeatureInternal.g.cs @@ -190,6 +190,7 @@ enum CpuidFeatureInternal { AVX512VL_and_AVX512_FP16, UDBG, KNC, + PADLOCK_UNDOC, } } #endif diff --git a/src/csharp/Intel/Iced/Intel/InstructionInfoInternal/CpuidFeatureInternalData.g.cs b/src/csharp/Intel/Iced/Intel/InstructionInfoInternal/CpuidFeatureInternalData.g.cs index a7774a092..b361e8210 100644 --- a/src/csharp/Intel/Iced/Intel/InstructionInfoInternal/CpuidFeatureInternalData.g.cs +++ b/src/csharp/Intel/Iced/Intel/InstructionInfoInternal/CpuidFeatureInternalData.g.cs @@ -221,6 +221,7 @@ static byte[] GetGetCpuidFeaturesData() => 0x21, 0x9E,// AVX512VL_and_AVX512_FP16 0x9F,// UDBG 0xA0,// KNC + 0xA1,// PADLOCK_UNDOC }; } } diff --git a/src/csharp/Intel/Iced/Intel/InstructionInfoInternal/InfoHandlerFlags.cs b/src/csharp/Intel/Iced/Intel/InstructionInfoInternal/InfoHandlerFlags.cs index 3f0bf7bda..3e33cbe91 100644 --- a/src/csharp/Intel/Iced/Intel/InstructionInfoInternal/InfoHandlerFlags.cs +++ b/src/csharp/Intel/Iced/Intel/InstructionInfoInternal/InfoHandlerFlags.cs @@ -333,6 +333,9 @@ enum ImpliedAccess { t_Reax_Recx_Wedx_Webx, t_Reax_Recx_Redx_CRebx_CWedx_CWebx, t_memdisplm64, + t_CRmem_CRmem_CWmem_CRsi_CRdi_CRes_CWsi_RCWcx, + t_CRmem_CRmem_CWmem_CResi_CRedi_CRes_CWesi_RCWecx, + t_CRmem_CRmem_CWmem_CRrsi_CRrdi_CRes_CWrsi_RCWrcx, } // GENERATOR-END: ImpliedAccess diff --git a/src/csharp/Intel/Iced/Intel/InstructionInfoInternal/InstrInfoTable.g.cs b/src/csharp/Intel/Iced/Intel/InstructionInfoInternal/InstrInfoTable.g.cs index b470ddb84..5cac1c559 100644 --- a/src/csharp/Intel/Iced/Intel/InstructionInfoInternal/InstrInfoTable.g.cs +++ b/src/csharp/Intel/Iced/Intel/InstructionInfoInternal/InstrInfoTable.g.cs @@ -8,7 +8,7 @@ #if INSTR_INFO namespace Iced.Intel.InstructionInfoInternal { static class InstrInfoTable { - internal static readonly uint[] Data = new uint[9636] { + internal static readonly uint[] Data = new uint[9660] { 0x00000000, 0x00900000,// INVALID 0x00000000, 0x00900000,// DeclareByte 0x00000000, 0x00900000,// DeclareWord @@ -4827,6 +4827,18 @@ static class InstrInfoTable { 0x00000000, 0xB5020005,// MVEX_Undoc_zmm_k1_zmmmt_imm8_512_66_0F3A_W0_D0 0x00000000, 0xB5020005,// MVEX_Undoc_zmm_k1_zmmmt_imm8_512_66_0F3A_W0_D1 0x000000B8, 0xB5000005,// MVEX_Vcvtfxpntpd2dq_zmm_k1_zmmmt_imm8 + 0x00000000, 0xB6020000,// Via_undoc_F30FA6F0_16 + 0x00000000, 0xB6020000,// Via_undoc_F30FA6F0_32 + 0x00000000, 0xB6020000,// Via_undoc_F30FA6F0_64 + 0x00000000, 0xB6020000,// Via_undoc_F30FA6F8_16 + 0x00000000, 0xB6020000,// Via_undoc_F30FA6F8_32 + 0x00000000, 0xB6020000,// Via_undoc_F30FA6F8_64 + 0x0C200000, 0x5F000000,// Xsha512_16 + 0x0C300000, 0x5F000000,// Xsha512_32 + 0x0C400000, 0x5F000000,// Xsha512_64 + 0x08000000, 0x61000000,// Xstore2_16 + 0x08100000, 0x61000000,// Xstore2_32 + 0x08200000, 0x61000000,// Xstore2_64 }; } } diff --git a/src/csharp/Intel/Iced/Intel/InstructionMemorySizes.g.cs b/src/csharp/Intel/Iced/Intel/InstructionMemorySizes.g.cs index 8c42a7169..12e49f1d1 100644 --- a/src/csharp/Intel/Iced/Intel/InstructionMemorySizes.g.cs +++ b/src/csharp/Intel/Iced/Intel/InstructionMemorySizes.g.cs @@ -4830,6 +4830,18 @@ static class InstructionMemorySizes { 0,// MVEX_Undoc_zmm_k1_zmmmt_imm8_512_66_0F3A_W0_D0 0,// MVEX_Undoc_zmm_k1_zmmmt_imm8_512_66_0F3A_W0_D1 0,// MVEX_Vcvtfxpntpd2dq_zmm_k1_zmmmt_imm8 + 0,// Via_undoc_F30FA6F0_16 + 0,// Via_undoc_F30FA6F0_32 + 0,// Via_undoc_F30FA6F0_64 + 0,// Via_undoc_F30FA6F8_16 + 0,// Via_undoc_F30FA6F8_32 + 0,// Via_undoc_F30FA6F8_64 + 0,// Xsha512_16 + 0,// Xsha512_32 + 0,// Xsha512_64 + 0,// Xstore2_16 + 0,// Xstore2_32 + 0,// Xstore2_64 }; #if HAS_SPAN @@ -9655,6 +9667,18 @@ static class InstructionMemorySizes { 0,// MVEX_Undoc_zmm_k1_zmmmt_imm8_512_66_0F3A_W0_D0 0,// MVEX_Undoc_zmm_k1_zmmmt_imm8_512_66_0F3A_W0_D1 0,// MVEX_Vcvtfxpntpd2dq_zmm_k1_zmmmt_imm8 + 0,// Via_undoc_F30FA6F0_16 + 0,// Via_undoc_F30FA6F0_32 + 0,// Via_undoc_F30FA6F0_64 + 0,// Via_undoc_F30FA6F8_16 + 0,// Via_undoc_F30FA6F8_32 + 0,// Via_undoc_F30FA6F8_64 + 0,// Xsha512_16 + 0,// Xsha512_32 + 0,// Xsha512_64 + 0,// Xstore2_16 + 0,// Xstore2_32 + 0,// Xstore2_64 }; } } diff --git a/src/csharp/Intel/Iced/Intel/InstructionOpCounts.g.cs b/src/csharp/Intel/Iced/Intel/InstructionOpCounts.g.cs index 72f1f50c8..12bbe9898 100644 --- a/src/csharp/Intel/Iced/Intel/InstructionOpCounts.g.cs +++ b/src/csharp/Intel/Iced/Intel/InstructionOpCounts.g.cs @@ -4830,6 +4830,18 @@ static class InstructionOpCounts { 3,// MVEX_Undoc_zmm_k1_zmmmt_imm8_512_66_0F3A_W0_D0 3,// MVEX_Undoc_zmm_k1_zmmmt_imm8_512_66_0F3A_W0_D1 3,// MVEX_Vcvtfxpntpd2dq_zmm_k1_zmmmt_imm8 + 0,// Via_undoc_F30FA6F0_16 + 0,// Via_undoc_F30FA6F0_32 + 0,// Via_undoc_F30FA6F0_64 + 0,// Via_undoc_F30FA6F8_16 + 0,// Via_undoc_F30FA6F8_32 + 0,// Via_undoc_F30FA6F8_64 + 0,// Xsha512_16 + 0,// Xsha512_32 + 0,// Xsha512_64 + 0,// Xstore2_16 + 0,// Xstore2_32 + 0,// Xstore2_64 }; } } diff --git a/src/csharp/Intel/Iced/Intel/IntelFormatterInternal/InstrInfos.g.cs b/src/csharp/Intel/Iced/Intel/IntelFormatterInternal/InstrInfos.g.cs index 14b2f205a..cd90a98ec 100644 --- a/src/csharp/Intel/Iced/Intel/IntelFormatterInternal/InstrInfos.g.cs +++ b/src/csharp/Intel/Iced/Intel/IntelFormatterInternal/InstrInfos.g.cs @@ -17975,6 +17975,66 @@ static byte[] GetSerializedInstrInfos() => // MVEX_Vcvtfxpntpd2dq_zmm_k1_zmmmt_imm8 0x01,// Normal_1 0x96, 0x0D,// 1686 = "vcvtfxpntpd2dq" + + // Via_undoc_F30FA6F0_16 + 0x03,// asz + 0x00,// 0 = "undoc" + 0x10,// 0x10 + + // Via_undoc_F30FA6F0_32 + 0x03,// asz + 0x00,// 0 = "undoc" + 0x20,// 0x20 + + // Via_undoc_F30FA6F0_64 + 0x03,// asz + 0x00,// 0 = "undoc" + 0x40,// 0x40 + + // Via_undoc_F30FA6F8_16 + 0x03,// asz + 0x00,// 0 = "undoc" + 0x10,// 0x10 + + // Via_undoc_F30FA6F8_32 + 0x03,// asz + 0x00,// 0 = "undoc" + 0x20,// 0x20 + + // Via_undoc_F30FA6F8_64 + 0x03,// asz + 0x00,// 0 = "undoc" + 0x40,// 0x40 + + // Xsha512_16 + 0x03,// asz + 0x97, 0x0D,// 1687 = "xsha512" + 0x10,// 0x10 + + // Xsha512_32 + 0x03,// asz + 0x97, 0x0D,// 1687 = "xsha512" + 0x20,// 0x20 + + // Xsha512_64 + 0x03,// asz + 0x97, 0x0D,// 1687 = "xsha512" + 0x40,// 0x40 + + // Xstore2_16 + 0x03,// asz + 0x98, 0x0D,// 1688 = "xstore2" + 0x10,// 0x10 + + // Xstore2_32 + 0x03,// asz + 0x98, 0x0D,// 1688 = "xstore2" + 0x20,// 0x20 + + // Xstore2_64 + 0x03,// asz + 0x98, 0x0D,// 1688 = "xstore2" + 0x40,// 0x40 }; } } diff --git a/src/csharp/Intel/Iced/Intel/MasmFormatterInternal/InstrInfos.g.cs b/src/csharp/Intel/Iced/Intel/MasmFormatterInternal/InstrInfos.g.cs index 018e8c028..df2c49cb9 100644 --- a/src/csharp/Intel/Iced/Intel/MasmFormatterInternal/InstrInfos.g.cs +++ b/src/csharp/Intel/Iced/Intel/MasmFormatterInternal/InstrInfos.g.cs @@ -18100,6 +18100,45 @@ static byte[] GetSerializedInstrInfos() => // MVEX_Vcvtfxpntpd2dq_zmm_k1_zmmmt_imm8 0x01,// Normal_1 0x96, 0x0D,// 1686 = "vcvtfxpntpd2dq" + + // Via_undoc_F30FA6F0_16 + 0x01,// Normal_1 + 0x00,// 0 = "undoc" + + // Via_undoc_F30FA6F0_32 + 0x00,// Previous + + // Via_undoc_F30FA6F0_64 + 0x00,// Previous + + // Via_undoc_F30FA6F8_16 + 0x00,// Previous + + // Via_undoc_F30FA6F8_32 + 0x00,// Previous + + // Via_undoc_F30FA6F8_64 + 0x00,// Previous + + // Xsha512_16 + 0x01,// Normal_1 + 0x97, 0x0D,// 1687 = "xsha512" + + // Xsha512_32 + 0x00,// Previous + + // Xsha512_64 + 0x00,// Previous + + // Xstore2_16 + 0x01,// Normal_1 + 0x98, 0x0D,// 1688 = "xstore2" + + // Xstore2_32 + 0x00,// Previous + + // Xstore2_64 + 0x00,// Previous }; } } diff --git a/src/csharp/Intel/Iced/Intel/Mnemonic.g.cs b/src/csharp/Intel/Iced/Intel/Mnemonic.g.cs index e6c608787..fa04afac5 100644 --- a/src/csharp/Intel/Iced/Intel/Mnemonic.g.cs +++ b/src/csharp/Intel/Iced/Intel/Mnemonic.g.cs @@ -1843,6 +1843,8 @@ public enum Mnemonic { Vscatterpf0hintdps = 1831, Vsubrpd = 1832, Vsubrps = 1833, + Xsha512 = 1834, + Xstore2 = 1835, } #pragma warning restore CS1591 // Missing XML comment for publicly visible type or member } diff --git a/src/csharp/Intel/Iced/Intel/MnemonicUtilsData.g.cs b/src/csharp/Intel/Iced/Intel/MnemonicUtilsData.g.cs index bc217f56a..ac7007e92 100644 --- a/src/csharp/Intel/Iced/Intel/MnemonicUtilsData.g.cs +++ b/src/csharp/Intel/Iced/Intel/MnemonicUtilsData.g.cs @@ -4826,6 +4826,18 @@ static class MnemonicUtilsData { (ushort)Mnemonic.Undoc,// MVEX_Undoc_zmm_k1_zmmmt_imm8_512_66_0F3A_W0_D0 (ushort)Mnemonic.Undoc,// MVEX_Undoc_zmm_k1_zmmmt_imm8_512_66_0F3A_W0_D1 (ushort)Mnemonic.Vcvtfxpntpd2dq,// MVEX_Vcvtfxpntpd2dq_zmm_k1_zmmmt_imm8 + (ushort)Mnemonic.Undoc,// Via_undoc_F30FA6F0_16 + (ushort)Mnemonic.Undoc,// Via_undoc_F30FA6F0_32 + (ushort)Mnemonic.Undoc,// Via_undoc_F30FA6F0_64 + (ushort)Mnemonic.Undoc,// Via_undoc_F30FA6F8_16 + (ushort)Mnemonic.Undoc,// Via_undoc_F30FA6F8_32 + (ushort)Mnemonic.Undoc,// Via_undoc_F30FA6F8_64 + (ushort)Mnemonic.Xsha512,// Xsha512_16 + (ushort)Mnemonic.Xsha512,// Xsha512_32 + (ushort)Mnemonic.Xsha512,// Xsha512_64 + (ushort)Mnemonic.Xstore2,// Xstore2_16 + (ushort)Mnemonic.Xstore2,// Xstore2_32 + (ushort)Mnemonic.Xstore2,// Xstore2_64 }; } } diff --git a/src/csharp/Intel/Iced/Intel/NasmFormatterInternal/InstrInfos.g.cs b/src/csharp/Intel/Iced/Intel/NasmFormatterInternal/InstrInfos.g.cs index 9cf06afe4..d2bbf4d74 100644 --- a/src/csharp/Intel/Iced/Intel/NasmFormatterInternal/InstrInfos.g.cs +++ b/src/csharp/Intel/Iced/Intel/NasmFormatterInternal/InstrInfos.g.cs @@ -18721,6 +18721,66 @@ static byte[] GetSerializedInstrInfos() => 0x0C,// er_2 0x96, 0x0D,// 1686 = "vcvtfxpntpd2dq" 0x03,// 0x3 + + // Via_undoc_F30FA6F0_16 + 0x04,// asz + 0x00,// 0 = "undoc" + 0x10,// 0x10 + + // Via_undoc_F30FA6F0_32 + 0x04,// asz + 0x00,// 0 = "undoc" + 0x20,// 0x20 + + // Via_undoc_F30FA6F0_64 + 0x04,// asz + 0x00,// 0 = "undoc" + 0x40,// 0x40 + + // Via_undoc_F30FA6F8_16 + 0x04,// asz + 0x00,// 0 = "undoc" + 0x10,// 0x10 + + // Via_undoc_F30FA6F8_32 + 0x04,// asz + 0x00,// 0 = "undoc" + 0x20,// 0x20 + + // Via_undoc_F30FA6F8_64 + 0x04,// asz + 0x00,// 0 = "undoc" + 0x40,// 0x40 + + // Xsha512_16 + 0x04,// asz + 0x97, 0x0D,// 1687 = "xsha512" + 0x10,// 0x10 + + // Xsha512_32 + 0x04,// asz + 0x97, 0x0D,// 1687 = "xsha512" + 0x20,// 0x20 + + // Xsha512_64 + 0x04,// asz + 0x97, 0x0D,// 1687 = "xsha512" + 0x40,// 0x40 + + // Xstore2_16 + 0x04,// asz + 0x98, 0x0D,// 1688 = "xstore2" + 0x10,// 0x10 + + // Xstore2_32 + 0x04,// asz + 0x98, 0x0D,// 1688 = "xstore2" + 0x20,// 0x20 + + // Xstore2_64 + 0x04,// asz + 0x98, 0x0D,// 1688 = "xstore2" + 0x40,// 0x40 }; } } diff --git a/src/csharp/Intel/IcedFuzzer/IcedFuzzer.Core/Instr.cs b/src/csharp/Intel/IcedFuzzer/IcedFuzzer.Core/Instr.cs index f7302fd20..2fd7ad349 100644 --- a/src/csharp/Intel/IcedFuzzer/IcedFuzzer.Core/Instr.cs +++ b/src/csharp/Intel/IcedFuzzer/IcedFuzzer.Core/Instr.cs @@ -114,6 +114,7 @@ enum FuzzerInstructionFlags : uint { ReservedNop = 0x00200000, DefaultOperandSize64 = 0x00400000, RequiresUniqueDestRegNum = 0x00800000, + RequiresAddressSize32 = 0x01000000, } [DebuggerDisplay("Mem={" + nameof(IsModrmMemory) + "} {" + nameof(MandatoryPrefix) + "} L{" + nameof(L) + ",d} W{" + nameof(W) + ",d} {" + nameof(Code) + "}")] @@ -144,6 +145,7 @@ public sealed class FuzzerInstruction { public bool IsReservedNop => (Flags & FuzzerInstructionFlags.ReservedNop) != 0; public bool DefaultOperandSize64 => (Flags & FuzzerInstructionFlags.DefaultOperandSize64) != 0; public bool RequiresUniqueDestRegNum => (Flags & FuzzerInstructionFlags.RequiresUniqueDestRegNum) != 0; + public bool RequiresAddressSize32 => (Flags & FuzzerInstructionFlags.RequiresAddressSize32) != 0; public readonly Code Code; internal FuzzerInstructionFlags Flags; @@ -227,6 +229,11 @@ public sealed class FuzzerInstruction { case Code.Nopq: flags |= FuzzerInstructionFlags.IsNop; break; + case Code.Montmul_16: + case Code.Montmul_32: + case Code.Montmul_64: + flags |= FuzzerInstructionFlags.RequiresAddressSize32; + break; } Code = code; diff --git a/src/csharp/Intel/IcedFuzzer/IcedFuzzer.Core/InstrGen.cs b/src/csharp/Intel/IcedFuzzer/IcedFuzzer.Core/InstrGen.cs index d21b135be..3e460ff1e 100644 --- a/src/csharp/Intel/IcedFuzzer/IcedFuzzer.Core/InstrGen.cs +++ b/src/csharp/Intel/IcedFuzzer/IcedFuzzer.Core/InstrGen.cs @@ -1143,6 +1143,8 @@ static void UpdateInstructionFlags(int bitness, ref LegacyInfo info) { } if (instr.AddressSize != 0 && instr.AddressSize != bitness) fflags |= FuzzerInstructionFlags.DontUsePrefix67; + if (instr.RequiresAddressSize32 && instr.AddressSize == 32) + fflags |= FuzzerInstructionFlags.DontUsePrefix67; } info.SetInstructionFlags(prefix, fflags); if ((fflags & FuzzerInstructionFlags.DontUsePrefixREXW) == 0) { @@ -1529,6 +1531,26 @@ Code.Seta_rm8 or Code.Sets_rm8 or Code.Setns_rm8 or Code.Setp_rm8 or Code.Setnp_ _ => false, }; + static bool IgnoresModRmLow3Bits(Code code) => + code switch { + Code.Montmul_16 or Code.Montmul_32 or Code.Montmul_64 or + Code.Xsha1_16 or Code.Xsha1_32 or Code.Xsha1_64 or + Code.Xsha256_16 or Code.Xsha256_32 or Code.Xsha256_64 or + Code.Xsha512_16 or Code.Xsha512_32 or Code.Xsha512_64 or + Code.Xstore_16 or Code.Xstore_32 or Code.Xstore_64 or + Code.Xcryptecb_16 or Code.Xcryptecb_32 or Code.Xcryptecb_64 or + Code.Xcryptcbc_16 or Code.Xcryptcbc_32 or Code.Xcryptcbc_64 or + Code.Xcryptctr_16 or Code.Xcryptctr_32 or Code.Xcryptctr_64 or + Code.Xcryptcfb_16 or Code.Xcryptcfb_32 or Code.Xcryptcfb_64 or + Code.Xcryptofb_16 or Code.Xcryptofb_32 or Code.Xcryptofb_64 or + Code.Xstore2_16 or Code.Xstore2_32 or Code.Xstore2_64 or + Code.Ccs_hash_16 or Code.Ccs_hash_32 or Code.Ccs_hash_64 or + Code.Via_undoc_F30FA6F0_16 or Code.Via_undoc_F30FA6F0_32 or Code.Via_undoc_F30FA6F0_64 or + Code.Via_undoc_F30FA6F8_16 or Code.Via_undoc_F30FA6F8_32 or Code.Via_undoc_F30FA6F8_64 or + Code.Ccs_encrypt_16 or Code.Ccs_encrypt_32 or Code.Ccs_encrypt_64 => true, + _ => false, + }; + static IEnumerable<(bool hasModrm, FuzzerInstruction)> GetInstructions(int bitness, OpCodeInfo[] opCodes) { // Split up instructions with a reg/mem (modrm) operand into two instructions, // one with reg only ops and the other one with reg+mem ops, eg. `add r16,rm16` @@ -1540,6 +1562,14 @@ Code.Seta_rm8 or Code.Sets_rm8 or Code.Setns_rm8 or Code.Setp_rm8 or Code.Setnp_ yield return info; } } + else if (IgnoresModRmLow3Bits(opCode.Code)) { + for (int i = 0; i < 8; i++) { + Assert.True((opCode.OpCode & 7) == 0); + var realOpCode = OpCode.CreateFromUInt32(opCode.OpCode + (uint)i, opCode.OpCodeLength); + foreach (var info in GetInstructions(bitness, opCode, opCode.MandatoryPrefix, opCode.GroupIndex, realOpCode)) + yield return info; + } + } else { foreach (var info in GetInstructions(bitness, opCode, opCode.MandatoryPrefix, opCode.GroupIndex)) yield return info; @@ -1547,13 +1577,13 @@ Code.Seta_rm8 or Code.Sets_rm8 or Code.Setns_rm8 or Code.Setp_rm8 or Code.Setnp_ } } - static IEnumerable<(bool hasModrm, FuzzerInstruction)> GetInstructions(int bitness, OpCodeInfo opCode, MandatoryPrefix mandatoryPrefix, int groupIndex) { + static IEnumerable<(bool hasModrm, FuzzerInstruction)> GetInstructions(int bitness, OpCodeInfo opCode, MandatoryPrefix mandatoryPrefix, int groupIndex, OpCode? realOpCode = null) { var (hasModrm, kind) = HasModRmWithRegAndMemOps(opCode); foreach (var (w, l) in GetLW(bitness, opCode)) { if (kind == ModrmMemoryKind.Mem || kind == ModrmMemoryKind.RegOrMem) - yield return (hasModrm, FuzzerInstruction.CreateValid(opCode.Code, isModrmMemory: true, w, l, mandatoryPrefix, groupIndex)); + yield return (hasModrm, FuzzerInstruction.CreateValid(opCode.Code, isModrmMemory: true, w, l, mandatoryPrefix, groupIndex, realOpCode)); if (kind == ModrmMemoryKind.Other || kind == ModrmMemoryKind.RegOrMem) - yield return (hasModrm, FuzzerInstruction.CreateValid(opCode.Code, isModrmMemory: false, w, l, mandatoryPrefix, groupIndex)); + yield return (hasModrm, FuzzerInstruction.CreateValid(opCode.Code, isModrmMemory: false, w, l, mandatoryPrefix, groupIndex, realOpCode)); } } diff --git a/src/csharp/Intel/IcedFuzzer/IcedFuzzer.Core/OpCodeInfoProvider.cs b/src/csharp/Intel/IcedFuzzer/IcedFuzzer.Core/OpCodeInfoProvider.cs index 7d093aba2..3ea6c5b0a 100644 --- a/src/csharp/Intel/IcedFuzzer/IcedFuzzer.Core/OpCodeInfoProvider.cs +++ b/src/csharp/Intel/IcedFuzzer/IcedFuzzer.Core/OpCodeInfoProvider.cs @@ -80,6 +80,16 @@ public static OpCodeInfo[] GetOpCodeInfos(OpCodeInfoOptions options) { if (!options.Filter.ShouldInclude(code)) continue; + switch (code) { + case Code.Montmul_16: + case Code.Montmul_32: + case Code.Montmul_64: + // Address size must be 32 + if (opCode.AddressSize != 32) + continue; + break; + } + switch (opCode.Encoding) { case EncodingKind.Legacy: break; diff --git a/src/csharp/Intel/IcedFuzzer/IcedFuzzer/Program.cs b/src/csharp/Intel/IcedFuzzer/IcedFuzzer/Program.cs index 18d4775ef..310e2b365 100644 --- a/src/csharp/Intel/IcedFuzzer/IcedFuzzer/Program.cs +++ b/src/csharp/Intel/IcedFuzzer/IcedFuzzer/Program.cs @@ -367,6 +367,7 @@ static Options ParseOptions(string[] args) { options.OpCodeInfoOptions.Filter.ExcludeCpuid.Add(CpuidFeature.PADLOCK_PMM); options.OpCodeInfoOptions.Filter.ExcludeCpuid.Add(CpuidFeature.PADLOCK_RNG); options.OpCodeInfoOptions.Filter.ExcludeCpuid.Add(CpuidFeature.PADLOCK_GMI); + options.OpCodeInfoOptions.Filter.ExcludeCpuid.Add(CpuidFeature.PADLOCK_UNDOC); break; case "--no-unused-tables": diff --git a/src/rust/iced-x86-js/src/code.rs b/src/rust/iced-x86-js/src/code.rs index 89c7139f7..5d68b7dd0 100644 --- a/src/rust/iced-x86-js/src/code.rs +++ b/src/rust/iced-x86-js/src/code.rs @@ -4829,6 +4829,18 @@ pub enum Code { MVEX_Undoc_zmm_k1_zmmmt_imm8_512_66_0F3A_W0_D0 = 4815, MVEX_Undoc_zmm_k1_zmmmt_imm8_512_66_0F3A_W0_D1 = 4816, MVEX_Vcvtfxpntpd2dq_zmm_k1_zmmmt_imm8 = 4817, + Via_undoc_F30FA6F0_16 = 4818, + Via_undoc_F30FA6F0_32 = 4819, + Via_undoc_F30FA6F0_64 = 4820, + Via_undoc_F30FA6F8_16 = 4821, + Via_undoc_F30FA6F8_32 = 4822, + Via_undoc_F30FA6F8_64 = 4823, + Xsha512_16 = 4824, + Xsha512_32 = 4825, + Xsha512_64 = 4826, + Xstore2_16 = 4827, + Xstore2_32 = 4828, + Xstore2_64 = 4829, } // GENERATOR-END: Enum diff --git a/src/rust/iced-x86-js/src/cpuid_feature.rs b/src/rust/iced-x86-js/src/cpuid_feature.rs index 25e252fd2..4e63dd8e8 100644 --- a/src/rust/iced-x86-js/src/cpuid_feature.rs +++ b/src/rust/iced-x86-js/src/cpuid_feature.rs @@ -338,5 +338,7 @@ pub enum CpuidFeature { UDBG = 159, /// Intel Knights Corner KNC = 160, + /// Undocumented instruction + PADLOCK_UNDOC = 161, } // GENERATOR-END: Enum diff --git a/src/rust/iced-x86-js/src/mnemonic.rs b/src/rust/iced-x86-js/src/mnemonic.rs index 439be7f7b..87bd2cedc 100644 --- a/src/rust/iced-x86-js/src/mnemonic.rs +++ b/src/rust/iced-x86-js/src/mnemonic.rs @@ -1845,6 +1845,8 @@ pub enum Mnemonic { Vscatterpf0hintdps = 1831, Vsubrpd = 1832, Vsubrps = 1833, + Xsha512 = 1834, + Xstore2 = 1835, } // GENERATOR-END: Enum diff --git a/src/rust/iced-x86-py/src/iced_x86/Code.py b/src/rust/iced-x86-py/src/iced_x86/Code.py index ac1c61e5e..62e75c54e 100644 --- a/src/rust/iced-x86-py/src/iced_x86/Code.py +++ b/src/rust/iced-x86-py/src/iced_x86/Code.py @@ -48167,3 +48167,123 @@ ``64-bit`` """ +VIA_UNDOC_F30FA6F0_16: Code = 4818 # type: ignore +""" +``UNDOC`` + +``a16 F3 0F A6 F0`` + +``PADLOCK_UNDOC`` + +``16/32-bit`` +""" +VIA_UNDOC_F30FA6F0_32: Code = 4819 # type: ignore +""" +``UNDOC`` + +``a32 F3 0F A6 F0`` + +``PADLOCK_UNDOC`` + +``16/32/64-bit`` +""" +VIA_UNDOC_F30FA6F0_64: Code = 4820 # type: ignore +""" +``UNDOC`` + +``a64 F3 0F A6 F0`` + +``PADLOCK_UNDOC`` + +``64-bit`` +""" +VIA_UNDOC_F30FA6F8_16: Code = 4821 # type: ignore +""" +``UNDOC`` + +``a16 F3 0F A6 F8`` + +``PADLOCK_UNDOC`` + +``16/32-bit`` +""" +VIA_UNDOC_F30FA6F8_32: Code = 4822 # type: ignore +""" +``UNDOC`` + +``a32 F3 0F A6 F8`` + +``PADLOCK_UNDOC`` + +``16/32/64-bit`` +""" +VIA_UNDOC_F30FA6F8_64: Code = 4823 # type: ignore +""" +``UNDOC`` + +``a64 F3 0F A6 F8`` + +``PADLOCK_UNDOC`` + +``64-bit`` +""" +XSHA512_16: Code = 4824 # type: ignore +""" +``XSHA512`` + +``a16 F3 0F A6 E0`` + +``PADLOCK_PHE`` + +``16/32-bit`` +""" +XSHA512_32: Code = 4825 # type: ignore +""" +``XSHA512`` + +``a32 F3 0F A6 E0`` + +``PADLOCK_PHE`` + +``16/32/64-bit`` +""" +XSHA512_64: Code = 4826 # type: ignore +""" +``XSHA512`` + +``a64 F3 0F A6 E0`` + +``PADLOCK_PHE`` + +``64-bit`` +""" +XSTORE2_16: Code = 4827 # type: ignore +""" +``XSTORE2`` + +``a16 F3 0F A7 F8`` + +``PADLOCK_RNG`` + +``16/32-bit`` +""" +XSTORE2_32: Code = 4828 # type: ignore +""" +``XSTORE2`` + +``a32 F3 0F A7 F8`` + +``PADLOCK_RNG`` + +``16/32/64-bit`` +""" +XSTORE2_64: Code = 4829 # type: ignore +""" +``XSTORE2`` + +``a64 F3 0F A7 F8`` + +``PADLOCK_RNG`` + +``64-bit`` +""" diff --git a/src/rust/iced-x86-py/src/iced_x86/CpuidFeature.py b/src/rust/iced-x86-py/src/iced_x86/CpuidFeature.py index 7da372415..43a9c23f2 100644 --- a/src/rust/iced-x86-py/src/iced_x86/CpuidFeature.py +++ b/src/rust/iced-x86-py/src/iced_x86/CpuidFeature.py @@ -661,3 +661,7 @@ """ Intel Knights Corner """ +PADLOCK_UNDOC: CpuidFeature = 161 # type: ignore +""" +Undocumented instruction +""" diff --git a/src/rust/iced-x86-py/src/iced_x86/Mnemonic.py b/src/rust/iced-x86-py/src/iced_x86/Mnemonic.py index 3c9961209..112aeef8a 100644 --- a/src/rust/iced-x86-py/src/iced_x86/Mnemonic.py +++ b/src/rust/iced-x86-py/src/iced_x86/Mnemonic.py @@ -7353,3 +7353,11 @@ """ """ +XSHA512: Mnemonic = 1834 # type: ignore +""" + +""" +XSTORE2: Mnemonic = 1835 # type: ignore +""" + +""" diff --git a/src/rust/iced-x86/src/code.rs b/src/rust/iced-x86/src/code.rs index 73dea7903..85283a0c6 100644 --- a/src/rust/iced-x86/src/code.rs +++ b/src/rust/iced-x86/src/code.rs @@ -38534,9 +38534,105 @@ pub enum Code { /// /// `64-bit` MVEX_Vcvtfxpntpd2dq_zmm_k1_zmmmt_imm8 = 4817, + /// `UNDOC` + /// + /// `a16 F3 0F A6 F0` + /// + /// `PADLOCK_UNDOC` + /// + /// `16/32-bit` + Via_undoc_F30FA6F0_16 = 4818, + /// `UNDOC` + /// + /// `a32 F3 0F A6 F0` + /// + /// `PADLOCK_UNDOC` + /// + /// `16/32/64-bit` + Via_undoc_F30FA6F0_32 = 4819, + /// `UNDOC` + /// + /// `a64 F3 0F A6 F0` + /// + /// `PADLOCK_UNDOC` + /// + /// `64-bit` + Via_undoc_F30FA6F0_64 = 4820, + /// `UNDOC` + /// + /// `a16 F3 0F A6 F8` + /// + /// `PADLOCK_UNDOC` + /// + /// `16/32-bit` + Via_undoc_F30FA6F8_16 = 4821, + /// `UNDOC` + /// + /// `a32 F3 0F A6 F8` + /// + /// `PADLOCK_UNDOC` + /// + /// `16/32/64-bit` + Via_undoc_F30FA6F8_32 = 4822, + /// `UNDOC` + /// + /// `a64 F3 0F A6 F8` + /// + /// `PADLOCK_UNDOC` + /// + /// `64-bit` + Via_undoc_F30FA6F8_64 = 4823, + /// `XSHA512` + /// + /// `a16 F3 0F A6 E0` + /// + /// `PADLOCK_PHE` + /// + /// `16/32-bit` + Xsha512_16 = 4824, + /// `XSHA512` + /// + /// `a32 F3 0F A6 E0` + /// + /// `PADLOCK_PHE` + /// + /// `16/32/64-bit` + Xsha512_32 = 4825, + /// `XSHA512` + /// + /// `a64 F3 0F A6 E0` + /// + /// `PADLOCK_PHE` + /// + /// `64-bit` + Xsha512_64 = 4826, + /// `XSTORE2` + /// + /// `a16 F3 0F A7 F8` + /// + /// `PADLOCK_RNG` + /// + /// `16/32-bit` + Xstore2_16 = 4827, + /// `XSTORE2` + /// + /// `a32 F3 0F A7 F8` + /// + /// `PADLOCK_RNG` + /// + /// `16/32/64-bit` + Xstore2_32 = 4828, + /// `XSTORE2` + /// + /// `a64 F3 0F A7 F8` + /// + /// `PADLOCK_RNG` + /// + /// `64-bit` + Xstore2_64 = 4829, } #[rustfmt::skip] -static GEN_DEBUG_CODE: [&str; 4818] = [ +static GEN_DEBUG_CODE: [&str; 4830] = [ "INVALID", "DeclareByte", "DeclareWord", @@ -43355,6 +43451,18 @@ static GEN_DEBUG_CODE: [&str; 4818] = [ "MVEX_Undoc_zmm_k1_zmmmt_imm8_512_66_0F3A_W0_D0", "MVEX_Undoc_zmm_k1_zmmmt_imm8_512_66_0F3A_W0_D1", "MVEX_Vcvtfxpntpd2dq_zmm_k1_zmmmt_imm8", + "Via_undoc_F30FA6F0_16", + "Via_undoc_F30FA6F0_32", + "Via_undoc_F30FA6F0_64", + "Via_undoc_F30FA6F8_16", + "Via_undoc_F30FA6F8_32", + "Via_undoc_F30FA6F8_64", + "Xsha512_16", + "Xsha512_32", + "Xsha512_64", + "Xstore2_16", + "Xstore2_32", + "Xstore2_64", ]; impl fmt::Debug for Code { #[inline] diff --git a/src/rust/iced-x86/src/code_asm/asm_traits.rs b/src/rust/iced-x86/src/code_asm/asm_traits.rs index 3a60f1cdc..9da1f873c 100644 --- a/src/rust/iced-x86/src/code_asm/asm_traits.rs +++ b/src/rust/iced-x86/src/code_asm/asm_traits.rs @@ -11054,11 +11054,21 @@ pub trait CodeAsmXsha256 { fn xsha256(&mut self) -> Result<(), IcedError>; } +#[rustfmt::skip] +pub trait CodeAsmXsha512 { + fn xsha512(&mut self) -> Result<(), IcedError>; +} + #[rustfmt::skip] pub trait CodeAsmXstore { fn xstore(&mut self) -> Result<(), IcedError>; } +#[rustfmt::skip] +pub trait CodeAsmXstore2 { + fn xstore2(&mut self) -> Result<(), IcedError>; +} + #[rustfmt::skip] pub trait CodeAsmXsusldtrk { fn xsusldtrk(&mut self) -> Result<(), IcedError>; diff --git a/src/rust/iced-x86/src/code_asm/fn_asm_impl.rs b/src/rust/iced-x86/src/code_asm/fn_asm_impl.rs index be0470f83..60d9ba511 100644 --- a/src/rust/iced-x86/src/code_asm/fn_asm_impl.rs +++ b/src/rust/iced-x86/src/code_asm/fn_asm_impl.rs @@ -75946,6 +75946,20 @@ impl CodeAsmXsha256 for CodeAssembler { } } +#[rustfmt::skip] +impl CodeAsmXsha512 for CodeAssembler { + fn xsha512(&mut self) -> Result<(), IcedError> { + let code = if self.bitness() == 64 { + Code::Xsha512_64 + } else if self.bitness() >= 32 { + Code::Xsha512_32 + } else { + Code::Xsha512_16 + }; + self.add_instr(Instruction::with(code)) + } +} + #[rustfmt::skip] impl CodeAsmXstore for CodeAssembler { fn xstore(&mut self) -> Result<(), IcedError> { @@ -75960,6 +75974,20 @@ impl CodeAsmXstore for CodeAssembler { } } +#[rustfmt::skip] +impl CodeAsmXstore2 for CodeAssembler { + fn xstore2(&mut self) -> Result<(), IcedError> { + let code = if self.bitness() == 64 { + Code::Xstore2_64 + } else if self.bitness() >= 32 { + Code::Xstore2_32 + } else { + Code::Xstore2_16 + }; + self.add_instr(Instruction::with(code)) + } +} + #[rustfmt::skip] impl CodeAsmXsusldtrk for CodeAssembler { #[inline] diff --git a/src/rust/iced-x86/src/code_asm/fn_asm_pub.rs b/src/rust/iced-x86/src/code_asm/fn_asm_pub.rs index dee22f4d2..a8be43d4e 100644 --- a/src/rust/iced-x86/src/code_asm/fn_asm_pub.rs +++ b/src/rust/iced-x86/src/code_asm/fn_asm_pub.rs @@ -51718,6 +51718,25 @@ impl CodeAssembler { ::xsha256(self) } + /// `XSHA512` instruction + /// + /// Instruction | Opcode | CPUID + /// ------------|--------|------ + /// `XSHA512` | `a16 F3 0F A6 E0` | `PADLOCK_PHE` + /// `XSHA512` | `a32 F3 0F A6 E0` | `PADLOCK_PHE` + /// `XSHA512` | `a64 F3 0F A6 E0` | `PADLOCK_PHE` + /// + /// # Errors + /// + /// Fails if an operand is invalid (basic checks only) + #[inline] + pub fn xsha512(&mut self) -> Result<(), IcedError> + where + Self: CodeAsmXsha512, + { + ::xsha512(self) + } + /// `XSTORE` instruction /// /// Instruction | Opcode | CPUID @@ -51737,6 +51756,25 @@ impl CodeAssembler { ::xstore(self) } + /// `XSTORE2` instruction + /// + /// Instruction | Opcode | CPUID + /// ------------|--------|------ + /// `XSTORE2` | `a16 F3 0F A7 F8` | `PADLOCK_RNG` + /// `XSTORE2` | `a32 F3 0F A7 F8` | `PADLOCK_RNG` + /// `XSTORE2` | `a64 F3 0F A7 F8` | `PADLOCK_RNG` + /// + /// # Errors + /// + /// Fails if an operand is invalid (basic checks only) + #[inline] + pub fn xstore2(&mut self) -> Result<(), IcedError> + where + Self: CodeAsmXstore2, + { + ::xstore2(self) + } + /// `XSUSLDTRK` instruction /// /// Instruction | Opcode | CPUID diff --git a/src/rust/iced-x86/src/code_asm/tests/instr16.rs b/src/rust/iced-x86/src/code_asm/tests/instr16.rs index 934f57b28..7d042f59d 100644 --- a/src/rust/iced-x86/src/code_asm/tests/instr16.rs +++ b/src/rust/iced-x86/src/code_asm/tests/instr16.rs @@ -12429,7 +12429,7 @@ fn montmul() { // Montmul_16 test_instr(16, |a| a.montmul().unwrap(), Instruction::with(Code::Montmul_16), - TestInstrFlags::REMOVE_REP_REPNE_PREFIXES, DecoderOptions::NONE); + TestInstrFlags::REMOVE_REP_REPNE_PREFIXES, DecoderOptions::NO_INVALID_CHECK); } } @@ -94201,6 +94201,21 @@ fn xsha256() { } } +#[test] +#[rustfmt::skip] +fn xsha512() { + /* if self.bitness() == 64 */ { + // skip `if self.bitness() == 64` since it's not supported by the current test bitness + } /* else if self.bitness() >= 32 */ { + // skip `if self.bitness() >= 32` since it's not supported by the current test bitness + } /* else */ { + // Xsha512_16 + test_instr(16, |a| a.xsha512().unwrap(), + Instruction::with(Code::Xsha512_16), + TestInstrFlags::REMOVE_REP_REPNE_PREFIXES, DecoderOptions::NONE); + } +} + #[test] #[rustfmt::skip] fn xstore() { @@ -94216,6 +94231,21 @@ fn xstore() { } } +#[test] +#[rustfmt::skip] +fn xstore2() { + /* if self.bitness() == 64 */ { + // skip `if self.bitness() == 64` since it's not supported by the current test bitness + } /* else if self.bitness() >= 32 */ { + // skip `if self.bitness() >= 32` since it's not supported by the current test bitness + } /* else */ { + // Xstore2_16 + test_instr(16, |a| a.xstore2().unwrap(), + Instruction::with(Code::Xstore2_16), + TestInstrFlags::REMOVE_REP_REPNE_PREFIXES, DecoderOptions::NONE); + } +} + #[test] #[rustfmt::skip] fn xsusldtrk() { diff --git a/src/rust/iced-x86/src/code_asm/tests/instr32.rs b/src/rust/iced-x86/src/code_asm/tests/instr32.rs index 05232451f..9ffd28812 100644 --- a/src/rust/iced-x86/src/code_asm/tests/instr32.rs +++ b/src/rust/iced-x86/src/code_asm/tests/instr32.rs @@ -94207,6 +94207,21 @@ fn xsha256() { } } +#[test] +#[rustfmt::skip] +fn xsha512() { + /* if self.bitness() == 64 */ { + // skip `if self.bitness() == 64` since it's not supported by the current test bitness + } /* else if self.bitness() >= 32 */ { + // Xsha512_32 + test_instr(32, |a| a.xsha512().unwrap(), + Instruction::with(Code::Xsha512_32), + TestInstrFlags::REMOVE_REP_REPNE_PREFIXES, DecoderOptions::NONE); + } /* else */ { + // skip `if !(self.bitness() >= 32)` since it's not supported by the current test bitness + } +} + #[test] #[rustfmt::skip] fn xstore() { @@ -94222,6 +94237,21 @@ fn xstore() { } } +#[test] +#[rustfmt::skip] +fn xstore2() { + /* if self.bitness() == 64 */ { + // skip `if self.bitness() == 64` since it's not supported by the current test bitness + } /* else if self.bitness() >= 32 */ { + // Xstore2_32 + test_instr(32, |a| a.xstore2().unwrap(), + Instruction::with(Code::Xstore2_32), + TestInstrFlags::REMOVE_REP_REPNE_PREFIXES, DecoderOptions::NONE); + } /* else */ { + // skip `if !(self.bitness() >= 32)` since it's not supported by the current test bitness + } +} + #[test] #[rustfmt::skip] fn xsusldtrk() { diff --git a/src/rust/iced-x86/src/code_asm/tests/instr64.rs b/src/rust/iced-x86/src/code_asm/tests/instr64.rs index a2fa361d2..d10cc2860 100644 --- a/src/rust/iced-x86/src/code_asm/tests/instr64.rs +++ b/src/rust/iced-x86/src/code_asm/tests/instr64.rs @@ -13891,7 +13891,7 @@ fn montmul() { // Montmul_64 test_instr(64, |a| a.montmul().unwrap(), Instruction::with(Code::Montmul_64), - TestInstrFlags::REMOVE_REP_REPNE_PREFIXES, DecoderOptions::NONE); + TestInstrFlags::REMOVE_REP_REPNE_PREFIXES, DecoderOptions::NO_INVALID_CHECK); } /* else */ { // skip `if !(self.bitness() == 64)` since it's not supported by the current test bitness } @@ -98827,6 +98827,19 @@ fn xsha256() { } } +#[test] +#[rustfmt::skip] +fn xsha512() { + /* if self.bitness() == 64 */ { + // Xsha512_64 + test_instr(64, |a| a.xsha512().unwrap(), + Instruction::with(Code::Xsha512_64), + TestInstrFlags::REMOVE_REP_REPNE_PREFIXES, DecoderOptions::NONE); + } /* else */ { + // skip `if !(self.bitness() == 64)` since it's not supported by the current test bitness + } +} + #[test] #[rustfmt::skip] fn xstore() { @@ -98840,6 +98853,19 @@ fn xstore() { } } +#[test] +#[rustfmt::skip] +fn xstore2() { + /* if self.bitness() == 64 */ { + // Xstore2_64 + test_instr(64, |a| a.xstore2().unwrap(), + Instruction::with(Code::Xstore2_64), + TestInstrFlags::REMOVE_REP_REPNE_PREFIXES, DecoderOptions::NONE); + } /* else */ { + // skip `if !(self.bitness() == 64)` since it's not supported by the current test bitness + } +} + #[test] #[rustfmt::skip] fn xsusldtrk() { diff --git a/src/rust/iced-x86/src/decoder/handlers/legacy.rs b/src/rust/iced-x86/src/decoder/handlers/legacy.rs index 604be5c7c..ca79b0ade 100644 --- a/src/rust/iced-x86/src/decoder/handlers/legacy.rs +++ b/src/rust/iced-x86/src/decoder/handlers/legacy.rs @@ -2365,6 +2365,29 @@ impl OpCodeHandler_Simple5 { } } +#[allow(non_camel_case_types)] +#[repr(C)] +pub(in crate::decoder) struct OpCodeHandler_Simple5_a32 { + has_modrm: bool, + code: [Code; 3], +} + +impl OpCodeHandler_Simple5_a32 { + #[inline] + pub(in crate::decoder) fn new(code16: Code, code32: Code, code64: Code) -> (OpCodeHandlerDecodeFn, Self) { + (OpCodeHandler_Simple5_a32::decode, Self { has_modrm: false, code: [code16, code32, code64] }) + } + + fn decode(self_ptr: *const OpCodeHandler, decoder: &mut Decoder<'_>, instruction: &mut Instruction) { + let this = unsafe { &*(self_ptr as *const Self) }; + debug_assert_eq!(decoder.state.encoding(), EncodingKind::Legacy as u32); + if decoder.state.address_size != OpSize::Size32 && decoder.invalid_check_mask != 0 { + decoder.set_invalid_instruction(); + } + instruction.set_code(this.code[decoder.state.address_size as usize]); + } +} + #[allow(non_camel_case_types)] #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_Simple5_ModRM_as { diff --git a/src/rust/iced-x86/src/decoder/table_de/data_legacy.rs b/src/rust/iced-x86/src/decoder/table_de/data_legacy.rs index 5b98c3066..f7ab8312c 100644 --- a/src/rust/iced-x86/src/decoder/table_de/data_legacy.rs +++ b/src/rust/iced-x86/src/decoder/table_de/data_legacy.rs @@ -1957,176 +1957,174 @@ pub(super) static TBL_DATA: &[u8] = &[ 0x07,// 7 0x02,// Invalid - // handlers_Grp_0FA6_lo + // handlers_Grp_0FA6 0x01,// ArrayReference 0x08,// 0x8 // 0 = 0x00 - 0x05,// Dup - 0x08,// 8 + 0x09,// RM + 0x12,// MandatoryPrefix4 + 0x02,// Invalid + 0x02,// Invalid + 0xD6,// Simple5_a32 + 0xA6, 0x0F,// Montmul_16 + 0x02,// Invalid + 0x00,// 0x0 0x02,// Invalid - // handlers_Grp_0FA6_hi - 0x01,// ArrayReference - 0x40,// 0x40 - // 0 = 0x00 - 0x12,// MandatoryPrefix4 - 0x03,// Invalid_NoModRM - 0x03,// Invalid_NoModRM - 0xAB,// Simple5 - 0xA6, 0x0F,// Montmul_16 - 0x03,// Invalid_NoModRM - 0x00,// 0x0 - // 1 = 0x01 - 0x05,// Dup - 0x07,// 7 - 0x06,// Null + 0x09,// RM + 0x12,// MandatoryPrefix4 + 0x02,// Invalid + 0x02,// Invalid + 0xAB,// Simple5 + 0xA9, 0x0F,// Xsha1_16 + 0x02,// Invalid + 0x00,// 0x0 + 0x02,// Invalid - // 8 = 0x08 - 0x12,// MandatoryPrefix4 - 0x03,// Invalid_NoModRM - 0x03,// Invalid_NoModRM - 0xAB,// Simple5 - 0xA9, 0x0F,// Xsha1_16 - 0x03,// Invalid_NoModRM - 0x00,// 0x0 + // 2 = 0x02 + 0x09,// RM + 0x12,// MandatoryPrefix4 + 0x02,// Invalid + 0x02,// Invalid + 0xAB,// Simple5 + 0xAC, 0x0F,// Xsha256_16 + 0x02,// Invalid + 0x00,// 0x0 + 0x02,// Invalid - // 9 = 0x09 - 0x05,// Dup - 0x07,// 7 - 0x06,// Null + // 3 = 0x03 + 0x02,// Invalid - // 16 = 0x10 - 0x12,// MandatoryPrefix4 - 0x03,// Invalid_NoModRM - 0x03,// Invalid_NoModRM - 0xAB,// Simple5 - 0xAC, 0x0F,// Xsha256_16 - 0x03,// Invalid_NoModRM - 0x00,// 0x0 + // 4 = 0x04 + 0x09,// RM + 0x12,// MandatoryPrefix4 + 0x02,// Invalid + 0x02,// Invalid + 0xAB,// Simple5 + 0xD8, 0x25,// Xsha512_16 + 0x02,// Invalid + 0x00,// 0x0 + 0x02,// Invalid - // 17 = 0x11 - 0x05,// Dup - 0x17,// 23 - 0x06,// Null + // 5 = 0x05 + 0x09,// RM + 0x12,// MandatoryPrefix4 + 0x02,// Invalid + 0x02,// Invalid + 0xAB,// Simple5 + 0xD8, 0x21,// Ccs_hash_16 + 0x02,// Invalid + 0x00,// 0x0 + 0x02,// Invalid - // 40 = 0x28 - 0x12,// MandatoryPrefix4 - 0x03,// Invalid_NoModRM - 0x03,// Invalid_NoModRM - 0xAB,// Simple5 - 0xD8, 0x21,// Ccs_hash_16 - 0x03,// Invalid_NoModRM - 0x00,// 0x0 + // 6 = 0x06 + 0x09,// RM + 0x12,// MandatoryPrefix4 + 0x02,// Invalid + 0x02,// Invalid + 0xAB,// Simple5 + 0xD2, 0x25,// Via_undoc_F30FA6F0_16 + 0x02,// Invalid + 0x00,// 0x0 + 0x02,// Invalid - // 41 = 0x29 - 0x05,// Dup - 0x17,// 23 - 0x06,// Null + // 7 = 0x07 + 0x09,// RM + 0x12,// MandatoryPrefix4 + 0x02,// Invalid + 0x02,// Invalid + 0xAB,// Simple5 + 0xD5, 0x25,// Via_undoc_F30FA6F8_16 + 0x02,// Invalid + 0x00,// 0x0 + 0x02,// Invalid - // handlers_Grp_0FA7_lo + // handlers_Grp_0FA7 0x01,// ArrayReference 0x08,// 0x8 // 0 = 0x00 - 0x05,// Dup - 0x08,// 8 + 0x09,// RM + 0xAB,// Simple5 + 0xB1, 0x0F,// Xstore_16 0x02,// Invalid - // handlers_Grp_0FA7_hi - 0x01,// ArrayReference - 0x40,// 0x40 - // 0 = 0x00 - 0xAB,// Simple5 - 0xB1, 0x0F,// Xstore_16 - // 1 = 0x01 - 0x05,// Dup - 0x07,// 7 - 0x06,// Null - - // 8 = 0x08 - 0x12,// MandatoryPrefix4 - 0x03,// Invalid_NoModRM - 0x03,// Invalid_NoModRM - 0xAB,// Simple5 - 0xB4, 0x0F,// Xcryptecb_16 - 0x03,// Invalid_NoModRM - 0x00,// 0x0 - - // 9 = 0x09 - 0x05,// Dup - 0x07,// 7 - 0x06,// Null - - // 16 = 0x10 - 0x12,// MandatoryPrefix4 - 0x03,// Invalid_NoModRM - 0x03,// Invalid_NoModRM - 0xAB,// Simple5 - 0xB7, 0x0F,// Xcryptcbc_16 - 0x03,// Invalid_NoModRM - 0x00,// 0x0 - - // 17 = 0x11 - 0x05,// Dup - 0x07,// 7 - 0x06,// Null - - // 24 = 0x18 - 0x12,// MandatoryPrefix4 - 0x03,// Invalid_NoModRM - 0x03,// Invalid_NoModRM - 0xAB,// Simple5 - 0xBA, 0x0F,// Xcryptctr_16 - 0x03,// Invalid_NoModRM - 0x00,// 0x0 - - // 25 = 0x19 - 0x05,// Dup - 0x07,// 7 - 0x06,// Null + 0x09,// RM + 0x12,// MandatoryPrefix4 + 0x02,// Invalid + 0x02,// Invalid + 0xAB,// Simple5 + 0xB4, 0x0F,// Xcryptecb_16 + 0x02,// Invalid + 0x00,// 0x0 + 0x02,// Invalid - // 32 = 0x20 - 0x12,// MandatoryPrefix4 - 0x03,// Invalid_NoModRM - 0x03,// Invalid_NoModRM - 0xAB,// Simple5 - 0xBD, 0x0F,// Xcryptcfb_16 - 0x03,// Invalid_NoModRM - 0x00,// 0x0 + // 2 = 0x02 + 0x09,// RM + 0x12,// MandatoryPrefix4 + 0x02,// Invalid + 0x02,// Invalid + 0xAB,// Simple5 + 0xB7, 0x0F,// Xcryptcbc_16 + 0x02,// Invalid + 0x00,// 0x0 + 0x02,// Invalid - // 33 = 0x21 - 0x05,// Dup - 0x07,// 7 - 0x06,// Null + // 3 = 0x03 + 0x09,// RM + 0x12,// MandatoryPrefix4 + 0x02,// Invalid + 0x02,// Invalid + 0xAB,// Simple5 + 0xBA, 0x0F,// Xcryptctr_16 + 0x02,// Invalid + 0x00,// 0x0 + 0x02,// Invalid - // 40 = 0x28 - 0x12,// MandatoryPrefix4 - 0x03,// Invalid_NoModRM - 0x03,// Invalid_NoModRM - 0xAB,// Simple5 - 0xC0, 0x0F,// Xcryptofb_16 - 0x03,// Invalid_NoModRM - 0x00,// 0x0 + // 4 = 0x04 + 0x09,// RM + 0x12,// MandatoryPrefix4 + 0x02,// Invalid + 0x02,// Invalid + 0xAB,// Simple5 + 0xBD, 0x0F,// Xcryptcfb_16 + 0x02,// Invalid + 0x00,// 0x0 + 0x02,// Invalid - // 41 = 0x29 - 0x05,// Dup - 0x07,// 7 - 0x06,// Null + // 5 = 0x05 + 0x09,// RM + 0x12,// MandatoryPrefix4 + 0x02,// Invalid + 0x02,// Invalid + 0xAB,// Simple5 + 0xC0, 0x0F,// Xcryptofb_16 + 0x02,// Invalid + 0x00,// 0x0 + 0x02,// Invalid - // 48 = 0x30 - 0x12,// MandatoryPrefix4 - 0x03,// Invalid_NoModRM - 0x03,// Invalid_NoModRM - 0xAB,// Simple5 - 0xDB, 0x21,// Ccs_encrypt_16 - 0x03,// Invalid_NoModRM - 0x00,// 0x0 + // 6 = 0x06 + 0x09,// RM + 0x12,// MandatoryPrefix4 + 0x02,// Invalid + 0x02,// Invalid + 0xAB,// Simple5 + 0xDB, 0x21,// Ccs_encrypt_16 + 0x02,// Invalid + 0x00,// 0x0 + 0x02,// Invalid - // 49 = 0x31 - 0x05,// Dup - 0x0F,// 15 - 0x06,// Null + // 7 = 0x07 + 0x09,// RM + 0x12,// MandatoryPrefix4 + 0x02,// Invalid + 0x02,// Invalid + 0xAB,// Simple5 + 0xDB, 0x25,// Xstore2_16 + 0x02,// Invalid + 0x00,// 0x0 + 0x02,// Invalid // handlers_Grp_0FBA 0x01,// ArrayReference @@ -2861,10 +2859,10 @@ pub(super) static TBL_DATA: &[u8] = &[ 0x00,// HandlerReference 0x09,// RM 0x07,// HandlerReference - 0x37,// 0x37 = reservedNop_0F0D + 0x35,// 0x35 = reservedNop_0F0D 0x0E,// Group 0x08,// ArrayReference - 0x40,// 0x40 = handlers_Grp_0F0D_mem + 0x3E,// 0x3E = handlers_Grp_0F0D_mem // handlers_Grp_0F18_mem 0x01,// ArrayReference @@ -2889,19 +2887,19 @@ pub(super) static TBL_DATA: &[u8] = &[ 0x05,// Dup 0x04,// 4 0x07,// HandlerReference - 0x38,// 0x38 = reservedNop_0F18 + 0x36,// 0x36 = reservedNop_0F18 // grp0F18 0x00,// HandlerReference 0x9E,// Reservednop 0x07,// HandlerReference - 0x38,// 0x38 = reservedNop_0F18 + 0x36,// 0x36 = reservedNop_0F18 0x09,// RM 0x07,// HandlerReference - 0x38,// 0x38 = reservedNop_0F18 + 0x36,// 0x36 = reservedNop_0F18 0x0E,// Group 0x08,// ArrayReference - 0x42,// 0x42 = handlers_Grp_0F18_mem + 0x40,// 0x40 = handlers_Grp_0F18_mem // handlers_Grp_0F1C_mem 0x01,// ArrayReference @@ -2911,30 +2909,30 @@ pub(super) static TBL_DATA: &[u8] = &[ 0x6E,// M_1 0x9B, 0x08,// Cldemote_m8 0x07,// HandlerReference - 0x3C,// 0x3C = reservedNop_0F1C + 0x3A,// 0x3A = reservedNop_0F1C 0x07,// HandlerReference - 0x3C,// 0x3C = reservedNop_0F1C + 0x3A,// 0x3A = reservedNop_0F1C 0x07,// HandlerReference - 0x3C,// 0x3C = reservedNop_0F1C + 0x3A,// 0x3A = reservedNop_0F1C 0x00,// 0x0 // 1 = 0x01 0x05,// Dup 0x07,// 7 0x07,// HandlerReference - 0x3C,// 0x3C = reservedNop_0F1C + 0x3A,// 0x3A = reservedNop_0F1C // grp0F1C 0x00,// HandlerReference 0x9E,// Reservednop 0x07,// HandlerReference - 0x3C,// 0x3C = reservedNop_0F1C + 0x3A,// 0x3A = reservedNop_0F1C 0x09,// RM 0x07,// HandlerReference - 0x3C,// 0x3C = reservedNop_0F1C + 0x3A,// 0x3A = reservedNop_0F1C 0x0E,// Group 0x08,// ArrayReference - 0x44,// 0x44 = handlers_Grp_0F1C_mem + 0x42,// 0x42 = handlers_Grp_0F1C_mem // handlers_Grp_0F1E_reg_lo 0x01,// ArrayReference @@ -2943,23 +2941,23 @@ pub(super) static TBL_DATA: &[u8] = &[ 0x05,// Dup 0x08,// 8 0x07,// HandlerReference - 0x3E,// 0x3E = reservedNop_0F1E + 0x3C,// 0x3C = reservedNop_0F1E // grp0F1E_1 0x00,// HandlerReference 0x11,// MandatoryPrefix 0x07,// HandlerReference - 0x3E,// 0x3E = reservedNop_0F1E + 0x3C,// 0x3C = reservedNop_0F1E 0x07,// HandlerReference - 0x3E,// 0x3E = reservedNop_0F1E + 0x3C,// 0x3C = reservedNop_0F1E 0x09,// RM 0x44,// Ev_REXW 0x9C, 0x08,// Rdsspd_r32 0x01,// 0x1 0x07,// HandlerReference - 0x3E,// 0x3E = reservedNop_0F1E + 0x3C,// 0x3C = reservedNop_0F1E 0x07,// HandlerReference - 0x3E,// 0x3E = reservedNop_0F1E + 0x3C,// 0x3C = reservedNop_0F1E // handlers_Grp_0F1E_reg_hi 0x01,// ArrayReference @@ -2973,7 +2971,7 @@ pub(super) static TBL_DATA: &[u8] = &[ 0x05,// Dup 0x08,// 8 0x07,// HandlerReference - 0x47,// 0x47 = grp0F1E_1 + 0x45,// 0x45 = grp0F1E_1 // 16 = 0x10 0x05,// Dup @@ -2983,24 +2981,24 @@ pub(super) static TBL_DATA: &[u8] = &[ // 58 = 0x3A 0x11,// MandatoryPrefix 0x07,// HandlerReference - 0x3E,// 0x3E = reservedNop_0F1E + 0x3C,// 0x3C = reservedNop_0F1E 0x07,// HandlerReference - 0x3E,// 0x3E = reservedNop_0F1E + 0x3C,// 0x3C = reservedNop_0F1E 0xA5,// Simple_ModRM 0x9E, 0x08,// Endbr64 0x07,// HandlerReference - 0x3E,// 0x3E = reservedNop_0F1E + 0x3C,// 0x3C = reservedNop_0F1E // 59 = 0x3B 0x11,// MandatoryPrefix 0x07,// HandlerReference - 0x3E,// 0x3E = reservedNop_0F1E + 0x3C,// 0x3C = reservedNop_0F1E 0x07,// HandlerReference - 0x3E,// 0x3E = reservedNop_0F1E + 0x3C,// 0x3C = reservedNop_0F1E 0xA5,// Simple_ModRM 0x9F, 0x08,// Endbr32 0x07,// HandlerReference - 0x3E,// 0x3E = reservedNop_0F1E + 0x3C,// 0x3C = reservedNop_0F1E // 60 = 0x3C 0x05,// Dup @@ -3011,15 +3009,15 @@ pub(super) static TBL_DATA: &[u8] = &[ 0x00,// HandlerReference 0x9E,// Reservednop 0x07,// HandlerReference - 0x3E,// 0x3E = reservedNop_0F1E + 0x3C,// 0x3C = reservedNop_0F1E 0x09,// RM 0x0F,// Group8x64 0x08,// ArrayReference - 0x46,// 0x46 = handlers_Grp_0F1E_reg_lo + 0x44,// 0x44 = handlers_Grp_0F1E_reg_lo 0x08,// ArrayReference - 0x48,// 0x48 = handlers_Grp_0F1E_reg_hi + 0x46,// 0x46 = handlers_Grp_0F1E_reg_hi 0x07,// HandlerReference - 0x3E,// 0x3E = reservedNop_0F1E + 0x3C,// 0x3C = reservedNop_0F1E // handlers_Grp_0F1F 0x01,// ArrayReference @@ -3032,16 +3030,16 @@ pub(super) static TBL_DATA: &[u8] = &[ 0x05,// Dup 0x07,// 7 0x07,// HandlerReference - 0x3F,// 0x3F = reservedNop_0F1F + 0x3D,// 0x3D = reservedNop_0F1F // grp0F1F 0x00,// HandlerReference 0x9E,// Reservednop 0x07,// HandlerReference - 0x3F,// 0x3F = reservedNop_0F1F + 0x3D,// 0x3D = reservedNop_0F1F 0x0E,// Group 0x08,// ArrayReference - 0x4A,// 0x4A = handlers_Grp_0F1F + 0x48,// 0x48 = handlers_Grp_0F1F // handlers_Grp_660F78 0x01,// ArrayReference @@ -3645,7 +3643,7 @@ pub(super) static TBL_DATA: &[u8] = &[ 0x02,// Invalid 0x0E,// Group 0x08,// ArrayReference - 0x4D,// 0x4D = handlers_Grp_F30F38D8 + 0x4B,// 0x4B = handlers_Grp_F30F38D8 0x02,// Invalid // 217 = 0xD9 @@ -4073,9 +4071,9 @@ pub(super) static TBL_DATA: &[u8] = &[ // 240 = 0xF0 0x0F,// Group8x64 0x08,// ArrayReference - 0x4E,// 0x4E = handlers_Grp_0F3AF0_lo + 0x4C,// 0x4C = handlers_Grp_0F3AF0_lo 0x08,// ArrayReference - 0x4F,// 0x4F = handlers_Grp_0F3AF0_hi + 0x4D,// 0x4D = handlers_Grp_0F3AF0_hi // 241 = 0xF1 0x05,// Dup @@ -4170,9 +4168,9 @@ pub(super) static TBL_DATA: &[u8] = &[ // 13 = 0x0D 0x9E,// Reservednop 0x07,// HandlerReference - 0x37,// 0x37 = reservedNop_0F0D + 0x35,// 0x35 = reservedNop_0F0D 0x07,// HandlerReference - 0x41,// 0x41 = grp0F0D + 0x3F,// 0x3F = grp0F0D // 14 = 0x0E 0x0A,// Options3 @@ -4327,23 +4325,23 @@ pub(super) static TBL_DATA: &[u8] = &[ // 24 = 0x18 0x07,// HandlerReference - 0x43,// 0x43 = grp0F18 + 0x41,// 0x41 = grp0F18 // 25 = 0x19 0x07,// HandlerReference - 0x39,// 0x39 = reservedNop_0F19 + 0x37,// 0x37 = reservedNop_0F19 // 26 = 0x1A 0x9E,// Reservednop 0x07,// HandlerReference - 0x3A,// 0x3A = reservedNop_0F1A + 0x38,// 0x38 = reservedNop_0F1A 0x0C,// Options_DontReadModRM 0x07,// HandlerReference - 0x3A,// 0x3A = reservedNop_0F1A + 0x38,// 0x38 = reservedNop_0F1A 0x11,// MandatoryPrefix 0x09,// RM 0x07,// HandlerReference - 0x3A,// 0x3A = reservedNop_0F1A + 0x38,// 0x38 = reservedNop_0F1A 0x1F,// B_MIB 0x8D, 0x08,// Bndldx_bnd_mib 0x1D,// B_BM @@ -4359,21 +4357,21 @@ pub(super) static TBL_DATA: &[u8] = &[ // 27 = 0x1B 0x9E,// Reservednop 0x07,// HandlerReference - 0x3B,// 0x3B = reservedNop_0F1B + 0x39,// 0x39 = reservedNop_0F1B 0x0C,// Options_DontReadModRM 0x07,// HandlerReference - 0x3B,// 0x3B = reservedNop_0F1B + 0x39,// 0x39 = reservedNop_0F1B 0x11,// MandatoryPrefix 0x09,// RM 0x07,// HandlerReference - 0x3B,// 0x3B = reservedNop_0F1B + 0x39,// 0x39 = reservedNop_0F1B 0x76,// MIB_B 0x94, 0x08,// Bndstx_mib_bnd 0x20,// BM_B 0x95, 0x08,// Bndmov_bndm64_bnd 0x09,// RM 0x07,// HandlerReference - 0x3B,// 0x3B = reservedNop_0F1B + 0x39,// 0x39 = reservedNop_0F1B 0x1E,// B_Ev 0x97, 0x08,// Bndmk_bnd_m32 0x00,// false @@ -4384,19 +4382,19 @@ pub(super) static TBL_DATA: &[u8] = &[ // 28 = 0x1C 0x07,// HandlerReference - 0x45,// 0x45 = grp0F1C + 0x43,// 0x43 = grp0F1C // 29 = 0x1D 0x07,// HandlerReference - 0x3D,// 0x3D = reservedNop_0F1D + 0x3B,// 0x3B = reservedNop_0F1D // 30 = 0x1E 0x07,// HandlerReference - 0x49,// 0x49 = grp0F1E + 0x47,// 0x47 = grp0F1E // 31 = 0x1F 0x07,// HandlerReference - 0x4B,// 0x4B = grp0F1F + 0x49,// 0x49 = grp0F1F // 32 = 0x20 0x8D,// R_C_3a @@ -4574,7 +4572,7 @@ pub(super) static TBL_DATA: &[u8] = &[ 0xC8,// Options1632_1 0x0D,// AnotherTable 0x08,// ArrayReference - 0x50,// 0x50 = Handlers_0F38 + 0x4E,// 0x4E = Handlers_0F38 0xA4,// Simple 0x90, 0x21,// Smint 0x80, 0x80, 0x40,// Cyrix @@ -4590,7 +4588,7 @@ pub(super) static TBL_DATA: &[u8] = &[ 0xC9,// Options1632_2 0x0D,// AnotherTable 0x08,// ArrayReference - 0x51,// 0x51 = Handlers_0F3A + 0x4F,// 0x4F = Handlers_0F3A 0xA4,// Simple 0x92, 0x21,// Rdm 0x80, 0x80, 0x80, 0x02,// Cyrix_DMI @@ -5071,17 +5069,17 @@ pub(super) static TBL_DATA: &[u8] = &[ // 113 = 0x71 0x0E,// Group 0x08,// ArrayReference - 0x32,// 0x32 = handlers_Grp_0F71 + 0x30,// 0x30 = handlers_Grp_0F71 // 114 = 0x72 0x0E,// Group 0x08,// ArrayReference - 0x33,// 0x33 = handlers_Grp_0F72 + 0x31,// 0x31 = handlers_Grp_0F72 // 115 = 0x73 0x0E,// Group 0x08,// ArrayReference - 0x34,// 0x34 = handlers_Grp_0F73 + 0x32,// 0x32 = handlers_Grp_0F73 // 116 = 0x74 0x11,// MandatoryPrefix @@ -5125,7 +5123,7 @@ pub(super) static TBL_DATA: &[u8] = &[ 0xCA, 0x0D,// Vmread_rm32_r32 0x0E,// Group 0x08,// ArrayReference - 0x4C,// 0x4C = handlers_Grp_660F78 + 0x4A,// 0x4A = handlers_Grp_660F78 0x02,// Invalid 0xB6,// VRIbIb 0xDB, 0x0D,// Insertq_xmm_xmm_imm8_imm8 @@ -5380,42 +5378,34 @@ pub(super) static TBL_DATA: &[u8] = &[ // 166 = 0xA6 0x00,// Bitness 0x0B,// Options5 - 0x0F,// Group8x64 - 0x08,// ArrayReference - 0x28,// 0x28 = handlers_Grp_0FA6_lo + 0x0E,// Group 0x08,// ArrayReference - 0x29,// 0x29 = handlers_Grp_0FA6_hi + 0x28,// 0x28 = handlers_Grp_0FA6 0x51,// Gv_Ev_3b 0xAF, 0x0F,// Xbts_r16_rm16 0x10,// Xbts 0x2B,// Eb_Gb_1 0xC5, 0x0F,// Cmpxchg486_rm8_r8 0x20,// Cmpxchg486A - 0x0F,// Group8x64 - 0x08,// ArrayReference - 0x28,// 0x28 = handlers_Grp_0FA6_lo + 0x0E,// Group 0x08,// ArrayReference - 0x29,// 0x29 = handlers_Grp_0FA6_hi + 0x28,// 0x28 = handlers_Grp_0FA6 // 167 = 0xA7 0x00,// Bitness 0x0B,// Options5 - 0x0F,// Group8x64 - 0x08,// ArrayReference - 0x2A,// 0x2A = handlers_Grp_0FA7_lo + 0x0E,// Group 0x08,// ArrayReference - 0x2B,// 0x2B = handlers_Grp_0FA7_hi + 0x29,// 0x29 = handlers_Grp_0FA7 0x38,// Ev_Gv_3b 0xC3, 0x0F,// Ibts_rm16_r16 0x10,// Xbts 0x38,// Ev_Gv_3b 0xC6, 0x0F,// Cmpxchg486_rm16_r16 0x20,// Cmpxchg486A - 0x0F,// Group8x64 - 0x08,// ArrayReference - 0x2A,// 0x2A = handlers_Grp_0FA7_lo + 0x0E,// Group 0x08,// ArrayReference - 0x2B,// 0x2B = handlers_Grp_0FA7_hi + 0x29,// 0x29 = handlers_Grp_0FA7 // 168 = 0xA8 0x88,// PushOpSizeReg_4a @@ -5447,9 +5437,9 @@ pub(super) static TBL_DATA: &[u8] = &[ // 174 = 0xAE 0x0F,// Group8x64 0x08,// ArrayReference - 0x35,// 0x35 = handlers_Grp_0FAE_lo + 0x33,// 0x33 = handlers_Grp_0FAE_lo 0x08,// ArrayReference - 0x36,// 0x36 = handlers_Grp_0FAE_hi + 0x34,// 0x34 = handlers_Grp_0FAE_hi // 175 = 0xAF 0x50,// Gv_Ev_3a @@ -5518,7 +5508,7 @@ pub(super) static TBL_DATA: &[u8] = &[ // 186 = 0xBA 0x0E,// Group 0x08,// ArrayReference - 0x2C,// 0x2C = handlers_Grp_0FBA + 0x2A,// 0x2A = handlers_Grp_0FBA // 187 = 0xBB 0x39,// Ev_Gv_4 @@ -5626,7 +5616,7 @@ pub(super) static TBL_DATA: &[u8] = &[ // 199 = 0xC7 0x0E,// Group 0x08,// ArrayReference - 0x2D,// 0x2D = handlers_Grp_0FC7 + 0x2B,// 0x2B = handlers_Grp_0FC7 // 200 = 0xC8 0xAD,// SimpleReg @@ -6181,7 +6171,7 @@ pub(super) static TBL_DATA: &[u8] = &[ // 15 = 0x0F 0x0D,// AnotherTable 0x08,// ArrayReference - 0x52,// 0x52 = Handlers_0F + 0x50,// 0x50 = Handlers_0F // 16 = 0x10 0x2C,// Eb_Gb_2 @@ -7062,16 +7052,16 @@ pub(super) static TBL_DATA: &[u8] = &[ // 198 = 0xC6 0x0F,// Group8x64 0x08,// ArrayReference - 0x2E,// 0x2E = handlers_Grp_C6_lo + 0x2C,// 0x2C = handlers_Grp_C6_lo 0x08,// ArrayReference - 0x2F,// 0x2F = handlers_Grp_C6_hi + 0x2D,// 0x2D = handlers_Grp_C6_hi // 199 = 0xC7 0x0F,// Group8x64 0x08,// ArrayReference - 0x30,// 0x30 = handlers_Grp_C7_lo + 0x2E,// 0x2E = handlers_Grp_C7_lo 0x08,// ArrayReference - 0x31,// 0x31 = handlers_Grp_C7_hi + 0x2F,// 0x2F = handlers_Grp_C7_hi // 200 = 0xC8 0x68,// Iw_Ib @@ -7362,6 +7352,6 @@ pub(super) static TBL_DATA: &[u8] = &[ 0x08,// ArrayReference 0x1E,// 0x1E = handlers_Grp_FF ]; -pub(super) const MAX_ID_NAMES: usize = 84; +pub(super) const MAX_ID_NAMES: usize = 82; #[allow(dead_code)] -pub(super) const HANDLERS_MAP0_INDEX: usize = 83; +pub(super) const HANDLERS_MAP0_INDEX: usize = 81; diff --git a/src/rust/iced-x86/src/decoder/table_de/enums.rs b/src/rust/iced-x86/src/decoder/table_de/enums.rs index c2b581896..3d951f3e0 100644 --- a/src/rust/iced-x86/src/decoder/table_de/enums.rs +++ b/src/rust/iced-x86/src/decoder/table_de/enums.rs @@ -252,9 +252,10 @@ pub(crate) enum LegacyOpCodeHandlerKind { PrefixF2, PrefixF3, PrefixREX, + Simple5_a32, } #[rustfmt::skip] -static GEN_DEBUG_LEGACY_OP_CODE_HANDLER_KIND: [&str; 214] = [ +static GEN_DEBUG_LEGACY_OP_CODE_HANDLER_KIND: [&str; 215] = [ "Bitness", "Bitness_DontReadModRM", "Invalid", @@ -469,6 +470,7 @@ static GEN_DEBUG_LEGACY_OP_CODE_HANDLER_KIND: [&str; 214] = [ "PrefixF2", "PrefixF3", "PrefixREX", + "Simple5_a32", ]; impl fmt::Debug for LegacyOpCodeHandlerKind { #[inline] diff --git a/src/rust/iced-x86/src/decoder/table_de/legacy_reader.rs b/src/rust/iced-x86/src/decoder/table_de/legacy_reader.rs index c4a2d3875..6828173f4 100644 --- a/src/rust/iced-x86/src/decoder/table_de/legacy_reader.rs +++ b/src/rust/iced-x86/src/decoder/table_de/legacy_reader.rs @@ -753,6 +753,11 @@ pub(super) fn read_handlers(deserializer: &mut TableDeserializer<'_>, result: &m box_opcode_handler(OpCodeHandler_Simple5::new(code1, code2, code3)) } + LegacyOpCodeHandlerKind::Simple5_a32 => { + let (code1, code2, code3) = deserializer.read_code3(); + box_opcode_handler(OpCodeHandler_Simple5_a32::new(code1, code2, code3)) + } + LegacyOpCodeHandlerKind::Simple5_ModRM_as => { let (code1, code2, code3) = deserializer.read_code3(); box_opcode_handler(OpCodeHandler_Simple5_ModRM_as::new(code1, code2, code3)) diff --git a/src/rust/iced-x86/src/encoder/encoder_data.rs b/src/rust/iced-x86/src/encoder/encoder_data.rs index 2ef8242db..d5270eede 100644 --- a/src/rust/iced-x86/src/encoder/encoder_data.rs +++ b/src/rust/iced-x86/src/encoder/encoder_data.rs @@ -4,7 +4,7 @@ // ⚠️This file was generated by GENERATOR!🦹‍♂️ #[rustfmt::skip] -pub(super) static ENC_FLAGS1: [u32; 4818] = [ +pub(super) static ENC_FLAGS1: [u32; 4830] = [ 0x0000_0000,// INVALID 0x0000_0000,// DeclareByte 0x0000_0000,// DeclareWord @@ -4823,9 +4823,21 @@ pub(super) static ENC_FLAGS1: [u32; 4818] = [ 0x0000_0836,// MVEX_Undoc_zmm_k1_zmmmt_imm8_512_66_0F3A_W0_D0 0x0000_0836,// MVEX_Undoc_zmm_k1_zmmmt_imm8_512_66_0F3A_W0_D1 0x0000_0836,// MVEX_Vcvtfxpntpd2dq_zmm_k1_zmmmt_imm8 + 0x0000_0000,// Via_undoc_F30FA6F0_16 + 0x0000_0000,// Via_undoc_F30FA6F0_32 + 0x0000_0000,// Via_undoc_F30FA6F0_64 + 0x0000_0000,// Via_undoc_F30FA6F8_16 + 0x0000_0000,// Via_undoc_F30FA6F8_32 + 0x0000_0000,// Via_undoc_F30FA6F8_64 + 0x0000_0000,// Xsha512_16 + 0x0000_0000,// Xsha512_32 + 0x0000_0000,// Xsha512_64 + 0x0000_0000,// Xstore2_16 + 0x0000_0000,// Xstore2_32 + 0x0000_0000,// Xstore2_64 ]; #[rustfmt::skip] -pub(super) static ENC_FLAGS2: [u32; 4818] = [ +pub(super) static ENC_FLAGS2: [u32; 4830] = [ 0x0000_0000,// INVALID 0x0000_0000,// DeclareByte 0x0000_0000,// DeclareWord @@ -9644,9 +9656,21 @@ pub(super) static ENC_FLAGS2: [u32; 4818] = [ 0x4616_00D0,// MVEX_Undoc_zmm_k1_zmmmt_imm8_512_66_0F3A_W0_D0 0x4616_00D1,// MVEX_Undoc_zmm_k1_zmmmt_imm8_512_66_0F3A_W0_D1 0x4676_00E6,// MVEX_Vcvtfxpntpd2dq_zmm_k1_zmmmt_imm8 + 0x4023_A6F0,// Via_undoc_F30FA6F0_16 + 0x4023_A6F0,// Via_undoc_F30FA6F0_32 + 0x4023_A6F0,// Via_undoc_F30FA6F0_64 + 0x4023_A6F8,// Via_undoc_F30FA6F8_16 + 0x4023_A6F8,// Via_undoc_F30FA6F8_32 + 0x4023_A6F8,// Via_undoc_F30FA6F8_64 + 0x4023_A6E0,// Xsha512_16 + 0x4023_A6E0,// Xsha512_32 + 0x4023_A6E0,// Xsha512_64 + 0x4023_A7F8,// Xstore2_16 + 0x4023_A7F8,// Xstore2_32 + 0x4023_A7F8,// Xstore2_64 ]; #[rustfmt::skip] -pub(super) static ENC_FLAGS3: [u32; 4818] = [ +pub(super) static ENC_FLAGS3: [u32; 4830] = [ 0x0003_0000,// INVALID 0x0003_0000,// DeclareByte 0x0003_0000,// DeclareWord @@ -14465,4 +14489,16 @@ pub(super) static ENC_FLAGS3: [u32; 4818] = [ 0x3802_0005,// MVEX_Undoc_zmm_k1_zmmmt_imm8_512_66_0F3A_W0_D0 0x3802_0005,// MVEX_Undoc_zmm_k1_zmmmt_imm8_512_66_0F3A_W0_D1 0x3802_0005,// MVEX_Vcvtfxpntpd2dq_zmm_k1_zmmmt_imm8 + 0x0001_0020,// Via_undoc_F30FA6F0_16 + 0x0003_0040,// Via_undoc_F30FA6F0_32 + 0x0002_0060,// Via_undoc_F30FA6F0_64 + 0x0001_0020,// Via_undoc_F30FA6F8_16 + 0x0003_0040,// Via_undoc_F30FA6F8_32 + 0x0002_0060,// Via_undoc_F30FA6F8_64 + 0x0001_0020,// Xsha512_16 + 0x0003_0040,// Xsha512_32 + 0x0002_0060,// Xsha512_64 + 0x0001_0020,// Xstore2_16 + 0x0003_0040,// Xstore2_32 + 0x0002_0060,// Xstore2_64 ]; diff --git a/src/rust/iced-x86/src/encoder/mnemonic_str_tbl.rs b/src/rust/iced-x86/src/encoder/mnemonic_str_tbl.rs index 2df2e1fd5..56e8275be 100644 --- a/src/rust/iced-x86/src/encoder/mnemonic_str_tbl.rs +++ b/src/rust/iced-x86/src/encoder/mnemonic_str_tbl.rs @@ -4,7 +4,7 @@ // ⚠️This file was generated by GENERATOR!🦹‍♂️ #[rustfmt::skip] -pub(super) static TO_MNEMONIC_STR: [&str; 1834] = [ +pub(super) static TO_MNEMONIC_STR: [&str; 1836] = [ "invalid", "aaa", "aad", @@ -1839,4 +1839,6 @@ pub(super) static TO_MNEMONIC_STR: [&str; 1834] = [ "vscatterpf0hintdps", "vsubrpd", "vsubrps", + "xsha512", + "xstore2", ]; diff --git a/src/rust/iced-x86/src/encoder/op_code_data.rs b/src/rust/iced-x86/src/encoder/op_code_data.rs index 58474572f..2c92668b4 100644 --- a/src/rust/iced-x86/src/encoder/op_code_data.rs +++ b/src/rust/iced-x86/src/encoder/op_code_data.rs @@ -4,7 +4,7 @@ // ⚠️This file was generated by GENERATOR!🦹‍♂️ #[rustfmt::skip] -pub(super) static OPC_FLAGS1: [u32; 4818] = [ +pub(super) static OPC_FLAGS1: [u32; 4830] = [ 0x0000_0000,// INVALID 0x0000_0000,// DeclareByte 0x0000_0000,// DeclareWord @@ -4823,9 +4823,21 @@ pub(super) static OPC_FLAGS1: [u32; 4818] = [ 0x0221_0000,// MVEX_Undoc_zmm_k1_zmmmt_imm8_512_66_0F3A_W0_D0 0x0221_0000,// MVEX_Undoc_zmm_k1_zmmmt_imm8_512_66_0F3A_W0_D1 0x0220_0000,// MVEX_Vcvtfxpntpd2dq_zmm_k1_zmmmt_imm8 + 0x0001_0000,// Via_undoc_F30FA6F0_16 + 0x0001_0000,// Via_undoc_F30FA6F0_32 + 0x0001_0000,// Via_undoc_F30FA6F0_64 + 0x0001_0000,// Via_undoc_F30FA6F8_16 + 0x0001_0000,// Via_undoc_F30FA6F8_32 + 0x0001_0000,// Via_undoc_F30FA6F8_64 + 0x0000_0000,// Xsha512_16 + 0x0000_0000,// Xsha512_32 + 0x0000_0000,// Xsha512_64 + 0x0000_0000,// Xstore2_16 + 0x0000_0000,// Xstore2_32 + 0x0000_0000,// Xstore2_64 ]; #[rustfmt::skip] -pub(super) static OPC_FLAGS2: [u32; 4818] = [ +pub(super) static OPC_FLAGS2: [u32; 4830] = [ 0x1E00_3FFF,// INVALID 0x1E00_3FFF,// DeclareByte 0x1E00_3FFF,// DeclareWord @@ -9644,4 +9656,16 @@ pub(super) static OPC_FLAGS2: [u32; 4818] = [ 0x1400_3FF0,// MVEX_Undoc_zmm_k1_zmmmt_imm8_512_66_0F3A_W0_D0 0x1400_3FF0,// MVEX_Undoc_zmm_k1_zmmmt_imm8_512_66_0F3A_W0_D1 0x1400_3FF0,// MVEX_Vcvtfxpntpd2dq_zmm_k1_zmmmt_imm8 + 0x0A00_3FFF,// Via_undoc_F30FA6F0_16 + 0x1E00_3FFF,// Via_undoc_F30FA6F0_32 + 0x1400_3FF0,// Via_undoc_F30FA6F0_64 + 0x0A00_3FFF,// Via_undoc_F30FA6F8_16 + 0x1E00_3FFF,// Via_undoc_F30FA6F8_32 + 0x1400_3FF0,// Via_undoc_F30FA6F8_64 + 0x0A00_3FFF,// Xsha512_16 + 0x1E00_3FFF,// Xsha512_32 + 0x1400_3FF0,// Xsha512_64 + 0x0A00_3FFF,// Xstore2_16 + 0x1E00_3FFF,// Xstore2_32 + 0x1400_3FF0,// Xstore2_64 ]; diff --git a/src/rust/iced-x86/src/encoder/tests/dec_enc.rs b/src/rust/iced-x86/src/encoder/tests/dec_enc.rs index 8b959a56e..152558a58 100644 --- a/src/rust/iced-x86/src/encoder/tests/dec_enc.rs +++ b/src/rust/iced-x86/src/encoder/tests/dec_enc.rs @@ -209,7 +209,7 @@ fn reg_size(reg: Register) -> u32 { } else if Register::RAX <= reg && reg <= Register::R15 || reg == Register::RIP { 8 } else { - panic!() + unreachable!() } } @@ -249,7 +249,7 @@ fn reg_number(reg: Register) -> u32 { } else if Register::TR0 <= reg && reg <= Register::TR7 { reg as u32 - Register::TR0 as u32 } else { - panic!() + unreachable!() } } @@ -382,7 +382,7 @@ fn test_wig_instructions_ignore_w() { } else if encoding == EncodingKind::Legacy || encoding == EncodingKind::D3NOW { continue; } else { - panic!(); + unreachable!(); } } } @@ -490,7 +490,7 @@ fn test_lig_instructions_ignore_l() { } else if encoding == EncodingKind::Legacy || encoding == EncodingKind::D3NOW || encoding == EncodingKind::MVEX { continue; } else { - panic!(); + unreachable!(); } } } @@ -866,7 +866,7 @@ fn verify_invalid_vvvv() { assert_ne!(decoder.last_error(), DecoderError::None); } } else { - panic!(); + unreachable!(); } } } @@ -877,7 +877,7 @@ fn get_vvvvv_info(op_code: &OpCodeInfo) -> (bool, bool, u8) { let mut vvvv_mask = match op_code.encoding() { EncodingKind::EVEX | EncodingKind::MVEX => 0x1F, EncodingKind::VEX | EncodingKind::XOP => 0xF, - EncodingKind::Legacy | EncodingKind::D3NOW => panic!(), + EncodingKind::Legacy | EncodingKind::D3NOW => unreachable!(), }; for &op_kind in op_code.op_kinds() { match op_kind { @@ -1089,7 +1089,7 @@ fn verify_gpr_rrxb_bits() { } } } else { - panic!(); + unreachable!(); } } } @@ -1298,7 +1298,7 @@ fn verify_k_reg_rrxb_bits() { } } } else { - panic!(); + unreachable!(); } } } @@ -1359,7 +1359,7 @@ fn verify_vsib_with_invalid_index_register_evex() { } } } else { - panic!(); + unreachable!(); } } } @@ -1479,7 +1479,7 @@ fn verify_vsib_with_invalid_index_mask_dest_register_vex() { } } } else { - panic!(); + unreachable!(); } } } @@ -1625,7 +1625,7 @@ fn verify_that_test_cases_test_enough_bits() { 16 => &mut tested_infos_16, 32 => &mut tested_infos_32, 64 => &mut tested_infos_64, - _ => panic!(), + _ => unreachable!(), }; let op_code = info.code().op_code(); @@ -1719,27 +1719,27 @@ fn verify_that_test_cases_test_enough_bits() { OpCodeTableKind::Normal => {} OpCodeTableKind::T0F => { if bytes[i] != 0x0F { - panic!(); + unreachable!(); } i += 1; } OpCodeTableKind::T0F38 => { if bytes[i] != 0x0F { - panic!(); + unreachable!(); } i += 1; if bytes[i] != 0x38 { - panic!(); + unreachable!(); } i += 1; } OpCodeTableKind::T0F3A => { if bytes[i] != 0x0F { - panic!(); + unreachable!(); } i += 1; if bytes[i] != 0x3A { - panic!(); + unreachable!(); } i += 1; } @@ -1816,7 +1816,7 @@ fn verify_that_test_cases_test_enough_bits() { } } } else { - panic!(); + unreachable!(); } } @@ -1956,13 +1956,16 @@ fn verify_that_test_cases_test_enough_bits() { 16 => &tested_infos_16, 32 => &tested_infos_32, 64 => &tested_infos_64, - _ => panic!(), + _ => unreachable!(), }; for code in Code::values() { if is_ignored_code(code_names[code as usize]) { continue; } + if matches!(code, Code::Montmul_16 | Code::Montmul_64) { + continue; + } let op_code = code.op_code(); if !op_code.is_instruction() || op_code.code() == Code::Popw_CS { continue; @@ -1987,7 +1990,7 @@ fn verify_that_test_cases_test_enough_bits() { continue; } } - _ => panic!(), + _ => unreachable!(), } let tested = &tested_infos[code as usize]; @@ -2014,7 +2017,7 @@ fn verify_that_test_cases_test_enough_bits() { match op_code.encoding() { EncodingKind::VEX | EncodingKind::XOP => all_l_bits = 3, // 1 bit = 2 values EncodingKind::EVEX => all_l_bits = 0xF, // 2 bits = 4 values - EncodingKind::Legacy | EncodingKind::D3NOW | EncodingKind::MVEX => panic!(), + EncodingKind::Legacy | EncodingKind::D3NOW | EncodingKind::MVEX => unreachable!(), } if tested.l_bits != all_l_bits { get_vec(bitness, &mut lig_16, &mut lig_32, &mut lig_64).push(code); @@ -2672,7 +2675,7 @@ fn verify_that_test_cases_test_enough_bits() { match bitness { 16 => l16, 32 => l32, - _ => panic!(), + _ => unreachable!(), } } @@ -2681,7 +2684,7 @@ fn verify_that_test_cases_test_enough_bits() { 16 => l16, 32 => l32, 64 => l64, - _ => panic!(), + _ => unreachable!(), } } } @@ -2873,7 +2876,7 @@ fn verify_invalid_table_encoding() { } } else if op_code.encoding() == EncodingKind::Legacy || op_code.encoding() == EncodingKind::D3NOW { } else { - panic!(); + unreachable!(); } } } @@ -2919,7 +2922,7 @@ fn verify_invalid_pp_field() { } } else if op_code.encoding() == EncodingKind::Legacy || op_code.encoding() == EncodingKind::D3NOW { } else { - panic!(); + unreachable!(); } } } @@ -2953,35 +2956,35 @@ fn verify_regonly_or_regmemonly_mod_bits() { OpCodeTableKind::Normal => {} OpCodeTableKind::T0F => { if bytes[m_index] != 0x0F { - panic!(); + unreachable!(); } m_index += 1; } OpCodeTableKind::T0F38 => { if bytes[m_index] != 0x0F { - panic!(); + unreachable!(); } m_index += 1; if bytes[m_index] != 0x38 { - panic!(); + unreachable!(); } m_index += 1; } OpCodeTableKind::T0F3A => { if bytes[m_index] != 0x0F { - panic!(); + unreachable!(); } m_index += 1; if bytes[m_index] != 0x3A { - panic!(); + unreachable!(); } m_index += 1; } - _ => panic!(), + _ => unreachable!(), } m_index + 1 } else { - panic!(); + unreachable!(); }; if bytes[m_index] >= 0xC0 { diff --git a/src/rust/iced-x86/src/enums.rs b/src/rust/iced-x86/src/enums.rs index 044d8ed5f..825d1ddad 100644 --- a/src/rust/iced-x86/src/enums.rs +++ b/src/rust/iced-x86/src/enums.rs @@ -2660,10 +2660,12 @@ pub enum CpuidFeature { UDBG = 159, /// Intel Knights Corner KNC = 160, + /// Undocumented instruction + PADLOCK_UNDOC = 161, } #[cfg(feature = "instr_info")] #[rustfmt::skip] -static GEN_DEBUG_CPUID_FEATURE: [&str; 161] = [ +static GEN_DEBUG_CPUID_FEATURE: [&str; 162] = [ "INTEL8086", "INTEL8086_ONLY", "INTEL186", @@ -2825,6 +2827,7 @@ static GEN_DEBUG_CPUID_FEATURE: [&str; 161] = [ "AVX512_FP16", "UDBG", "KNC", + "PADLOCK_UNDOC", ]; #[cfg(feature = "instr_info")] impl fmt::Debug for CpuidFeature { diff --git a/src/rust/iced-x86/src/formatter/fast/fmt_data.rs b/src/rust/iced-x86/src/formatter/fast/fmt_data.rs index 0d63635ea..eb094d138 100644 --- a/src/rust/iced-x86/src/formatter/fast/fmt_data.rs +++ b/src/rust/iced-x86/src/formatter/fast/fmt_data.rs @@ -16571,4 +16571,43 @@ pub(super) static FORMATTER_TBL_DATA: &[u8] = &[ // MVEX_Vcvtfxpntpd2dq_zmm_k1_zmmmt_imm8 0x00,// No flags set 0x96, 0x0D,// 1686 = "vcvtfxpntpd2dq" + + // Via_undoc_F30FA6F0_16 + 0x00,// No flags set + 0x00,// 0 = "undoc" + + // Via_undoc_F30FA6F0_32 + 0x02,// SameAsPrev + + // Via_undoc_F30FA6F0_64 + 0x02,// SameAsPrev + + // Via_undoc_F30FA6F8_16 + 0x02,// SameAsPrev + + // Via_undoc_F30FA6F8_32 + 0x02,// SameAsPrev + + // Via_undoc_F30FA6F8_64 + 0x02,// SameAsPrev + + // Xsha512_16 + 0x00,// No flags set + 0x97, 0x0D,// 1687 = "xsha512" + + // Xsha512_32 + 0x02,// SameAsPrev + + // Xsha512_64 + 0x02,// SameAsPrev + + // Xstore2_16 + 0x00,// No flags set + 0x98, 0x0D,// 1688 = "xstore2" + + // Xstore2_32 + 0x02,// SameAsPrev + + // Xstore2_64 + 0x02,// SameAsPrev ]; diff --git a/src/rust/iced-x86/src/formatter/fmt_utils_all.rs b/src/rust/iced-x86/src/formatter/fmt_utils_all.rs index ea7fcde57..960348c0a 100644 --- a/src/rust/iced-x86/src/formatter/fmt_utils_all.rs +++ b/src/rust/iced-x86/src/formatter/fmt_utils_all.rs @@ -67,6 +67,18 @@ pub(super) fn is_rep_repe_repne_instruction(code: Code) -> bool { | Code::Ccs_encrypt_16 | Code::Ccs_encrypt_32 | Code::Ccs_encrypt_64 + | Code::Via_undoc_F30FA6F0_16 + | Code::Via_undoc_F30FA6F0_32 + | Code::Via_undoc_F30FA6F0_64 + | Code::Via_undoc_F30FA6F8_16 + | Code::Via_undoc_F30FA6F8_32 + | Code::Via_undoc_F30FA6F8_64 + | Code::Xsha512_16 + | Code::Xsha512_32 + | Code::Xsha512_64 + | Code::Xstore2_16 + | Code::Xstore2_32 + | Code::Xstore2_64 ) } diff --git a/src/rust/iced-x86/src/formatter/gas/fmt_data.rs b/src/rust/iced-x86/src/formatter/gas/fmt_data.rs index f36613911..37a48d0d0 100644 --- a/src/rust/iced-x86/src/formatter/gas/fmt_data.rs +++ b/src/rust/iced-x86/src/formatter/gas/fmt_data.rs @@ -20124,4 +20124,64 @@ pub(super) static FORMATTER_TBL_DATA: &[u8] = &[ 0x0B,// er_2 0x96, 0x0D,// 1686 = "vcvtfxpntpd2dq" 0x00,// 0x0 + + // Via_undoc_F30FA6F0_16 + 0x07,// asz + 0x00,// 0 = "undoc" + 0x10,// 0x10 + + // Via_undoc_F30FA6F0_32 + 0x07,// asz + 0x00,// 0 = "undoc" + 0x20,// 0x20 + + // Via_undoc_F30FA6F0_64 + 0x07,// asz + 0x00,// 0 = "undoc" + 0x40,// 0x40 + + // Via_undoc_F30FA6F8_16 + 0x07,// asz + 0x00,// 0 = "undoc" + 0x10,// 0x10 + + // Via_undoc_F30FA6F8_32 + 0x07,// asz + 0x00,// 0 = "undoc" + 0x20,// 0x20 + + // Via_undoc_F30FA6F8_64 + 0x07,// asz + 0x00,// 0 = "undoc" + 0x40,// 0x40 + + // Xsha512_16 + 0x07,// asz + 0x97, 0x0D,// 1687 = "xsha512" + 0x10,// 0x10 + + // Xsha512_32 + 0x07,// asz + 0x97, 0x0D,// 1687 = "xsha512" + 0x20,// 0x20 + + // Xsha512_64 + 0x07,// asz + 0x97, 0x0D,// 1687 = "xsha512" + 0x40,// 0x40 + + // Xstore2_16 + 0x07,// asz + 0x98, 0x0D,// 1688 = "xstore2" + 0x10,// 0x10 + + // Xstore2_32 + 0x07,// asz + 0x98, 0x0D,// 1688 = "xstore2" + 0x20,// 0x20 + + // Xstore2_64 + 0x07,// asz + 0x98, 0x0D,// 1688 = "xstore2" + 0x40,// 0x40 ]; diff --git a/src/rust/iced-x86/src/formatter/intel/fmt_data.rs b/src/rust/iced-x86/src/formatter/intel/fmt_data.rs index de43d78b3..0e70b8dc1 100644 --- a/src/rust/iced-x86/src/formatter/intel/fmt_data.rs +++ b/src/rust/iced-x86/src/formatter/intel/fmt_data.rs @@ -17966,4 +17966,64 @@ pub(super) static FORMATTER_TBL_DATA: &[u8] = &[ // MVEX_Vcvtfxpntpd2dq_zmm_k1_zmmmt_imm8 0x01,// Normal_1 0x96, 0x0D,// 1686 = "vcvtfxpntpd2dq" + + // Via_undoc_F30FA6F0_16 + 0x03,// asz + 0x00,// 0 = "undoc" + 0x10,// 0x10 + + // Via_undoc_F30FA6F0_32 + 0x03,// asz + 0x00,// 0 = "undoc" + 0x20,// 0x20 + + // Via_undoc_F30FA6F0_64 + 0x03,// asz + 0x00,// 0 = "undoc" + 0x40,// 0x40 + + // Via_undoc_F30FA6F8_16 + 0x03,// asz + 0x00,// 0 = "undoc" + 0x10,// 0x10 + + // Via_undoc_F30FA6F8_32 + 0x03,// asz + 0x00,// 0 = "undoc" + 0x20,// 0x20 + + // Via_undoc_F30FA6F8_64 + 0x03,// asz + 0x00,// 0 = "undoc" + 0x40,// 0x40 + + // Xsha512_16 + 0x03,// asz + 0x97, 0x0D,// 1687 = "xsha512" + 0x10,// 0x10 + + // Xsha512_32 + 0x03,// asz + 0x97, 0x0D,// 1687 = "xsha512" + 0x20,// 0x20 + + // Xsha512_64 + 0x03,// asz + 0x97, 0x0D,// 1687 = "xsha512" + 0x40,// 0x40 + + // Xstore2_16 + 0x03,// asz + 0x98, 0x0D,// 1688 = "xstore2" + 0x10,// 0x10 + + // Xstore2_32 + 0x03,// asz + 0x98, 0x0D,// 1688 = "xstore2" + 0x20,// 0x20 + + // Xstore2_64 + 0x03,// asz + 0x98, 0x0D,// 1688 = "xstore2" + 0x40,// 0x40 ]; diff --git a/src/rust/iced-x86/src/formatter/masm/fmt_data.rs b/src/rust/iced-x86/src/formatter/masm/fmt_data.rs index 079c1269b..bdec9636e 100644 --- a/src/rust/iced-x86/src/formatter/masm/fmt_data.rs +++ b/src/rust/iced-x86/src/formatter/masm/fmt_data.rs @@ -18091,4 +18091,43 @@ pub(super) static FORMATTER_TBL_DATA: &[u8] = &[ // MVEX_Vcvtfxpntpd2dq_zmm_k1_zmmmt_imm8 0x01,// Normal_1 0x96, 0x0D,// 1686 = "vcvtfxpntpd2dq" + + // Via_undoc_F30FA6F0_16 + 0x01,// Normal_1 + 0x00,// 0 = "undoc" + + // Via_undoc_F30FA6F0_32 + 0x00,// Previous + + // Via_undoc_F30FA6F0_64 + 0x00,// Previous + + // Via_undoc_F30FA6F8_16 + 0x00,// Previous + + // Via_undoc_F30FA6F8_32 + 0x00,// Previous + + // Via_undoc_F30FA6F8_64 + 0x00,// Previous + + // Xsha512_16 + 0x01,// Normal_1 + 0x97, 0x0D,// 1687 = "xsha512" + + // Xsha512_32 + 0x00,// Previous + + // Xsha512_64 + 0x00,// Previous + + // Xstore2_16 + 0x01,// Normal_1 + 0x98, 0x0D,// 1688 = "xstore2" + + // Xstore2_32 + 0x00,// Previous + + // Xstore2_64 + 0x00,// Previous ]; diff --git a/src/rust/iced-x86/src/formatter/nasm/fmt_data.rs b/src/rust/iced-x86/src/formatter/nasm/fmt_data.rs index 3bca445cc..3e5aa0e35 100644 --- a/src/rust/iced-x86/src/formatter/nasm/fmt_data.rs +++ b/src/rust/iced-x86/src/formatter/nasm/fmt_data.rs @@ -18712,4 +18712,64 @@ pub(super) static FORMATTER_TBL_DATA: &[u8] = &[ 0x0C,// er_2 0x96, 0x0D,// 1686 = "vcvtfxpntpd2dq" 0x03,// 0x3 + + // Via_undoc_F30FA6F0_16 + 0x04,// asz + 0x00,// 0 = "undoc" + 0x10,// 0x10 + + // Via_undoc_F30FA6F0_32 + 0x04,// asz + 0x00,// 0 = "undoc" + 0x20,// 0x20 + + // Via_undoc_F30FA6F0_64 + 0x04,// asz + 0x00,// 0 = "undoc" + 0x40,// 0x40 + + // Via_undoc_F30FA6F8_16 + 0x04,// asz + 0x00,// 0 = "undoc" + 0x10,// 0x10 + + // Via_undoc_F30FA6F8_32 + 0x04,// asz + 0x00,// 0 = "undoc" + 0x20,// 0x20 + + // Via_undoc_F30FA6F8_64 + 0x04,// asz + 0x00,// 0 = "undoc" + 0x40,// 0x40 + + // Xsha512_16 + 0x04,// asz + 0x97, 0x0D,// 1687 = "xsha512" + 0x10,// 0x10 + + // Xsha512_32 + 0x04,// asz + 0x97, 0x0D,// 1687 = "xsha512" + 0x20,// 0x20 + + // Xsha512_64 + 0x04,// asz + 0x97, 0x0D,// 1687 = "xsha512" + 0x40,// 0x40 + + // Xstore2_16 + 0x04,// asz + 0x98, 0x0D,// 1688 = "xstore2" + 0x10,// 0x10 + + // Xstore2_32 + 0x04,// asz + 0x98, 0x0D,// 1688 = "xstore2" + 0x20,// 0x20 + + // Xstore2_64 + 0x04,// asz + 0x98, 0x0D,// 1688 = "xstore2" + 0x40,// 0x40 ]; diff --git a/src/rust/iced-x86/src/formatter/strings_data.rs b/src/rust/iced-x86/src/formatter/strings_data.rs index 516ac1ed3..099b4ff8f 100644 --- a/src/rust/iced-x86/src/formatter/strings_data.rs +++ b/src/rust/iced-x86/src/formatter/strings_data.rs @@ -3,15 +3,15 @@ // ⚠️This file was generated by GENERATOR!🦹‍♂️ -pub(super) const STRINGS_COUNT: usize = 1687; +pub(super) const STRINGS_COUNT: usize = 1689; #[allow(dead_code)] pub(super) const MAX_STRING_LEN: usize = 18; #[allow(dead_code)] pub(super) const VALID_STRING_LENGTH: usize = 20; -pub(super) const PADDING_SIZE: usize = 6; +pub(super) const PADDING_SIZE: usize = 13; #[rustfmt::skip] -pub(super) static STRINGS_TBL_DATA: [u8; 14048] = [ +pub(super) static STRINGS_TBL_DATA: [u8; 14071] = [ 0x05, 0x75, 0x6E, 0x64, 0x6F, 0x63,// undoc 0x03, 0x6D, 0x6F, 0x76,// mov 0x03, 0x6E, 0x6F, 0x70,// nop @@ -1699,6 +1699,8 @@ pub(super) static STRINGS_TBL_DATA: [u8; 14048] = [ 0x0E, 0x76, 0x63, 0x76, 0x74, 0x66, 0x78, 0x70, 0x6E, 0x74, 0x64, 0x71, 0x32, 0x70, 0x73,// vcvtfxpntdq2ps 0x0E, 0x76, 0x63, 0x76, 0x74, 0x66, 0x78, 0x70, 0x6E, 0x74, 0x70, 0x73, 0x32, 0x64, 0x71,// vcvtfxpntps2dq 0x0E, 0x76, 0x63, 0x76, 0x74, 0x66, 0x78, 0x70, 0x6E, 0x74, 0x70, 0x64, 0x32, 0x64, 0x71,// vcvtfxpntpd2dq + 0x07, 0x78, 0x73, 0x68, 0x61, 0x35, 0x31, 0x32,// xsha512 + 0x07, 0x78, 0x73, 0x74, 0x6F, 0x72, 0x65, 0x32,// xstore2 // Padding so it's possible to read FastStringMnemonic::SIZE bytes from the last value - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ]; diff --git a/src/rust/iced-x86/src/iced_constants.rs b/src/rust/iced-x86/src/iced_constants.rs index 2c4c005c9..f0035f195 100644 --- a/src/rust/iced-x86/src/iced_constants.rs +++ b/src/rust/iced-x86/src/iced_constants.rs @@ -18,7 +18,7 @@ impl IcedConstants { pub(crate) const YMM_LAST: Register = Register::YMM31; pub(crate) const ZMM_LAST: Register = Register::ZMM31; pub(crate) const TMM_LAST: Register = Register::TMM7; - pub(crate) const MAX_CPUID_FEATURE_INTERNAL_VALUES: usize = 182; + pub(crate) const MAX_CPUID_FEATURE_INTERNAL_VALUES: usize = 183; pub(crate) const FIRST_BROADCAST_MEMORY_SIZE: MemorySize = MemorySize::Broadcast32_Float16; pub(crate) const MVEX_START: u32 = 4611; pub(crate) const MVEX_LENGTH: u32 = 207; @@ -34,10 +34,10 @@ impl IcedConstants { pub(crate) const CC_NE_ENUM_COUNT: usize = 2; pub(crate) const CC_NP_ENUM_COUNT: usize = 2; pub(crate) const CC_P_ENUM_COUNT: usize = 2; - pub(crate) const CODE_ENUM_COUNT: usize = 4818; + pub(crate) const CODE_ENUM_COUNT: usize = 4830; pub(crate) const CODE_SIZE_ENUM_COUNT: usize = 4; pub(crate) const CONDITION_CODE_ENUM_COUNT: usize = 17; - pub(crate) const CPUID_FEATURE_ENUM_COUNT: usize = 161; + pub(crate) const CPUID_FEATURE_ENUM_COUNT: usize = 162; pub(crate) const DECODER_ERROR_ENUM_COUNT: usize = 3; pub(crate) const DECORATOR_KIND_ENUM_COUNT: usize = 6; pub(crate) const ENCODING_KIND_ENUM_COUNT: usize = 6; @@ -47,7 +47,7 @@ impl IcedConstants { pub(crate) const MANDATORY_PREFIX_ENUM_COUNT: usize = 5; pub(crate) const MEMORY_SIZE_ENUM_COUNT: usize = 160; pub(crate) const MEMORY_SIZE_OPTIONS_ENUM_COUNT: usize = 4; - pub(crate) const MNEMONIC_ENUM_COUNT: usize = 1834; + pub(crate) const MNEMONIC_ENUM_COUNT: usize = 1836; pub(crate) const MVEX_CONV_FN_ENUM_COUNT: usize = 13; pub(crate) const MVEX_EHBIT_ENUM_COUNT: usize = 3; pub(crate) const MVEX_REG_MEM_CONV_ENUM_COUNT: usize = 17; diff --git a/src/rust/iced-x86/src/info/cpuid_table.rs b/src/rust/iced-x86/src/info/cpuid_table.rs index ec9dabd79..2fee7029f 100644 --- a/src/rust/iced-x86/src/info/cpuid_table.rs +++ b/src/rust/iced-x86/src/info/cpuid_table.rs @@ -6,7 +6,7 @@ use crate::CpuidFeature; #[rustfmt::skip] -pub(crate) static CPUID: [&[CpuidFeature]; 182] = [ +pub(crate) static CPUID: [&[CpuidFeature]; 183] = [ &[CpuidFeature::INTEL8086],// INTEL8086 &[CpuidFeature::INTEL8086_ONLY],// INTEL8086_ONLY &[CpuidFeature::INTEL186],// INTEL186 @@ -189,4 +189,5 @@ pub(crate) static CPUID: [&[CpuidFeature]; 182] = [ &[CpuidFeature::AVX512VL, CpuidFeature::AVX512_FP16],// AVX512VL_and_AVX512_FP16 &[CpuidFeature::UDBG],// UDBG &[CpuidFeature::KNC],// KNC + &[CpuidFeature::PADLOCK_UNDOC],// PADLOCK_UNDOC ]; diff --git a/src/rust/iced-x86/src/info/enums.rs b/src/rust/iced-x86/src/info/enums.rs index 1286c3a22..8fb591135 100644 --- a/src/rust/iced-x86/src/info/enums.rs +++ b/src/rust/iced-x86/src/info/enums.rs @@ -486,10 +486,13 @@ pub(crate) enum ImpliedAccess { t_Reax_Recx_Wedx_Webx, t_Reax_Recx_Redx_CRebx_CWedx_CWebx, t_memdisplm64, + t_CRmem_CRmem_CWmem_CRsi_CRdi_CRes_CWsi_RCWcx, + t_CRmem_CRmem_CWmem_CResi_CRedi_CRes_CWesi_RCWecx, + t_CRmem_CRmem_CWmem_CRrsi_CRrdi_CRes_CWrsi_RCWrcx, } #[cfg(feature = "instr_info")] #[rustfmt::skip] -static GEN_DEBUG_IMPLIED_ACCESS: [&str; 194] = [ +static GEN_DEBUG_IMPLIED_ACCESS: [&str; 197] = [ "None", "Shift_Ib_MASK1FMOD9", "Shift_Ib_MASK1FMOD11", @@ -684,6 +687,9 @@ static GEN_DEBUG_IMPLIED_ACCESS: [&str; 194] = [ "t_Reax_Recx_Wedx_Webx", "t_Reax_Recx_Redx_CRebx_CWedx_CWebx", "t_memdisplm64", + "t_CRmem_CRmem_CWmem_CRsi_CRdi_CRes_CWsi_RCWcx", + "t_CRmem_CRmem_CWmem_CResi_CRedi_CRes_CWesi_RCWecx", + "t_CRmem_CRmem_CWmem_CRrsi_CRrdi_CRes_CWrsi_RCWrcx", ]; #[cfg(feature = "instr_info")] impl fmt::Debug for ImpliedAccess { @@ -1078,10 +1084,11 @@ pub(crate) enum CpuidFeatureInternal { AVX512VL_and_AVX512_FP16, UDBG, KNC, + PADLOCK_UNDOC, } #[cfg(feature = "instr_info")] #[rustfmt::skip] -static GEN_DEBUG_CPUID_FEATURE_INTERNAL: [&str; 182] = [ +static GEN_DEBUG_CPUID_FEATURE_INTERNAL: [&str; 183] = [ "INTEL8086", "INTEL8086_ONLY", "INTEL186", @@ -1264,6 +1271,7 @@ static GEN_DEBUG_CPUID_FEATURE_INTERNAL: [&str; 182] = [ "AVX512VL_and_AVX512_FP16", "UDBG", "KNC", + "PADLOCK_UNDOC", ]; #[cfg(feature = "instr_info")] impl fmt::Debug for CpuidFeatureInternal { diff --git a/src/rust/iced-x86/src/info/factory.rs b/src/rust/iced-x86/src/info/factory.rs index 9b3ba0e9a..e2a165d4a 100644 --- a/src/rust/iced-x86/src/info/factory.rs +++ b/src/rust/iced-x86/src/info/factory.rs @@ -1871,6 +1871,54 @@ impl InstructionInfoFactory { ImpliedAccess::t_memdisplm64 => { Self::command_mem_displ(info, flags, -64); } + ImpliedAccess::t_CRmem_CRmem_CWmem_CRsi_CRdi_CRes_CWsi_RCWcx => { + if (flags & Flags::NO_MEMORY_USAGE) == 0 { + Self::add_memory(info, Register::ES, Register::SI, Register::None, 1, 0x0, MemorySize::Unknown, OpAccess::CondRead, CodeSize::Code16, 0); + Self::add_memory(info, Register::ES, Register::DI, Register::None, 1, 0x0, MemorySize::Unknown, OpAccess::CondRead, CodeSize::Code16, 0); + Self::add_memory(info, Register::ES, Register::DI, Register::None, 1, 0x0, MemorySize::Unknown, OpAccess::CondWrite, CodeSize::Code16, 0); + } + if (flags & Flags::NO_REGISTER_USAGE) == 0 { + Self::add_register(flags, info, Register::SI, OpAccess::CondRead); + Self::add_register(flags, info, Register::DI, OpAccess::CondRead); + if (flags & Flags::IS_64BIT) == 0 { + Self::add_register(flags, info, Register::ES, OpAccess::CondRead); + } + Self::add_register(flags, info, Register::SI, OpAccess::CondWrite); + Self::add_register(flags, info, Register::CX, OpAccess::ReadCondWrite); + } + } + ImpliedAccess::t_CRmem_CRmem_CWmem_CResi_CRedi_CRes_CWesi_RCWecx => { + if (flags & Flags::NO_MEMORY_USAGE) == 0 { + Self::add_memory(info, Register::ES, Register::ESI, Register::None, 1, 0x0, MemorySize::Unknown, OpAccess::CondRead, CodeSize::Code32, 0); + Self::add_memory(info, Register::ES, Register::EDI, Register::None, 1, 0x0, MemorySize::Unknown, OpAccess::CondRead, CodeSize::Code32, 0); + Self::add_memory(info, Register::ES, Register::EDI, Register::None, 1, 0x0, MemorySize::Unknown, OpAccess::CondWrite, CodeSize::Code32, 0); + } + if (flags & Flags::NO_REGISTER_USAGE) == 0 { + Self::add_register(flags, info, Register::ESI, OpAccess::CondRead); + Self::add_register(flags, info, Register::EDI, OpAccess::CondRead); + if (flags & Flags::IS_64BIT) == 0 { + Self::add_register(flags, info, Register::ES, OpAccess::CondRead); + } + Self::add_register(flags, info, Register::ESI, OpAccess::CondWrite); + Self::add_register(flags, info, Register::ECX, OpAccess::ReadCondWrite); + } + } + ImpliedAccess::t_CRmem_CRmem_CWmem_CRrsi_CRrdi_CRes_CWrsi_RCWrcx => { + if (flags & Flags::NO_MEMORY_USAGE) == 0 { + Self::add_memory(info, Register::ES, Register::RSI, Register::None, 1, 0x0, MemorySize::Unknown, OpAccess::CondRead, CodeSize::Code64, 0); + Self::add_memory(info, Register::ES, Register::RDI, Register::None, 1, 0x0, MemorySize::Unknown, OpAccess::CondRead, CodeSize::Code64, 0); + Self::add_memory(info, Register::ES, Register::RDI, Register::None, 1, 0x0, MemorySize::Unknown, OpAccess::CondWrite, CodeSize::Code64, 0); + } + if (flags & Flags::NO_REGISTER_USAGE) == 0 { + Self::add_register(flags, info, Register::RSI, OpAccess::CondRead); + Self::add_register(flags, info, Register::RDI, OpAccess::CondRead); + if (flags & Flags::IS_64BIT) == 0 { + Self::add_register(flags, info, Register::ES, OpAccess::CondRead); + } + Self::add_register(flags, info, Register::RSI, OpAccess::CondWrite); + Self::add_register(flags, info, Register::RCX, OpAccess::ReadCondWrite); + } + } // GENERATOR-END: ImpliedAccessHandler } } diff --git a/src/rust/iced-x86/src/info/info_table.rs b/src/rust/iced-x86/src/info/info_table.rs index 34d85657c..467c5e011 100644 --- a/src/rust/iced-x86/src/info/info_table.rs +++ b/src/rust/iced-x86/src/info/info_table.rs @@ -4,7 +4,7 @@ // ⚠️This file was generated by GENERATOR!🦹‍♂️ #[rustfmt::skip] -pub(crate) static TABLE: [(u32, u32); 4818] = [ +pub(crate) static TABLE: [(u32, u32); 4830] = [ (0x0000_0000, 0x0090_0000),// INVALID (0x0000_0000, 0x0090_0000),// DeclareByte (0x0000_0000, 0x0090_0000),// DeclareWord @@ -4823,4 +4823,16 @@ pub(crate) static TABLE: [(u32, u32); 4818] = [ (0x0000_0000, 0xB502_0005),// MVEX_Undoc_zmm_k1_zmmmt_imm8_512_66_0F3A_W0_D0 (0x0000_0000, 0xB502_0005),// MVEX_Undoc_zmm_k1_zmmmt_imm8_512_66_0F3A_W0_D1 (0x0000_00B8, 0xB500_0005),// MVEX_Vcvtfxpntpd2dq_zmm_k1_zmmmt_imm8 + (0x0000_0000, 0xB602_0000),// Via_undoc_F30FA6F0_16 + (0x0000_0000, 0xB602_0000),// Via_undoc_F30FA6F0_32 + (0x0000_0000, 0xB602_0000),// Via_undoc_F30FA6F0_64 + (0x0000_0000, 0xB602_0000),// Via_undoc_F30FA6F8_16 + (0x0000_0000, 0xB602_0000),// Via_undoc_F30FA6F8_32 + (0x0000_0000, 0xB602_0000),// Via_undoc_F30FA6F8_64 + (0x0C20_0000, 0x5F00_0000),// Xsha512_16 + (0x0C30_0000, 0x5F00_0000),// Xsha512_32 + (0x0C40_0000, 0x5F00_0000),// Xsha512_64 + (0x0800_0000, 0x6100_0000),// Xstore2_16 + (0x0810_0000, 0x6100_0000),// Xstore2_32 + (0x0820_0000, 0x6100_0000),// Xstore2_64 ]; diff --git a/src/rust/iced-x86/src/info/tests/mod.rs b/src/rust/iced-x86/src/info/tests/mod.rs index f9c4dcab0..0cdffeb59 100644 --- a/src/rust/iced-x86/src/info/tests/mod.rs +++ b/src/rust/iced-x86/src/info/tests/mod.rs @@ -231,7 +231,7 @@ fn test_info_core(tc: &InstrInfoTestCase, factory: &mut InstructionInfoFactory) } assert_eq!(instr.code().encoding(), tc.encoding); - #[cfg(feature = "encoder")] + #[cfg(all(feature = "encoder", feature = "op_code_info"))] { assert_eq!(tc.encoding, tc.code.op_code().encoding()); } diff --git a/src/rust/iced-x86/src/instruction_memory_sizes.rs b/src/rust/iced-x86/src/instruction_memory_sizes.rs index 0ddd37a81..38a59a34a 100644 --- a/src/rust/iced-x86/src/instruction_memory_sizes.rs +++ b/src/rust/iced-x86/src/instruction_memory_sizes.rs @@ -4826,6 +4826,18 @@ pub(super) static SIZES_NORMAL: [MemorySize; IcedConstants::CODE_ENUM_COUNT] = [ MemorySize::Unknown,// MVEX_Undoc_zmm_k1_zmmmt_imm8_512_66_0F3A_W0_D0 MemorySize::Unknown,// MVEX_Undoc_zmm_k1_zmmmt_imm8_512_66_0F3A_W0_D1 MemorySize::Unknown,// MVEX_Vcvtfxpntpd2dq_zmm_k1_zmmmt_imm8 + MemorySize::Unknown,// Via_undoc_F30FA6F0_16 + MemorySize::Unknown,// Via_undoc_F30FA6F0_32 + MemorySize::Unknown,// Via_undoc_F30FA6F0_64 + MemorySize::Unknown,// Via_undoc_F30FA6F8_16 + MemorySize::Unknown,// Via_undoc_F30FA6F8_32 + MemorySize::Unknown,// Via_undoc_F30FA6F8_64 + MemorySize::Unknown,// Xsha512_16 + MemorySize::Unknown,// Xsha512_32 + MemorySize::Unknown,// Xsha512_64 + MemorySize::Unknown,// Xstore2_16 + MemorySize::Unknown,// Xstore2_32 + MemorySize::Unknown,// Xstore2_64 ]; #[rustfmt::skip] @@ -9648,4 +9660,16 @@ pub(super) static SIZES_BCST: [MemorySize; IcedConstants::CODE_ENUM_COUNT] = [ MemorySize::Unknown,// MVEX_Undoc_zmm_k1_zmmmt_imm8_512_66_0F3A_W0_D0 MemorySize::Unknown,// MVEX_Undoc_zmm_k1_zmmmt_imm8_512_66_0F3A_W0_D1 MemorySize::Unknown,// MVEX_Vcvtfxpntpd2dq_zmm_k1_zmmmt_imm8 + MemorySize::Unknown,// Via_undoc_F30FA6F0_16 + MemorySize::Unknown,// Via_undoc_F30FA6F0_32 + MemorySize::Unknown,// Via_undoc_F30FA6F0_64 + MemorySize::Unknown,// Via_undoc_F30FA6F8_16 + MemorySize::Unknown,// Via_undoc_F30FA6F8_32 + MemorySize::Unknown,// Via_undoc_F30FA6F8_64 + MemorySize::Unknown,// Xsha512_16 + MemorySize::Unknown,// Xsha512_32 + MemorySize::Unknown,// Xsha512_64 + MemorySize::Unknown,// Xstore2_16 + MemorySize::Unknown,// Xstore2_32 + MemorySize::Unknown,// Xstore2_64 ]; diff --git a/src/rust/iced-x86/src/instruction_op_counts.rs b/src/rust/iced-x86/src/instruction_op_counts.rs index b4bc979d2..03f2db95f 100644 --- a/src/rust/iced-x86/src/instruction_op_counts.rs +++ b/src/rust/iced-x86/src/instruction_op_counts.rs @@ -4825,4 +4825,16 @@ pub(super) static OP_COUNT: [u8; IcedConstants::CODE_ENUM_COUNT] = [ 3,// MVEX_Undoc_zmm_k1_zmmmt_imm8_512_66_0F3A_W0_D0 3,// MVEX_Undoc_zmm_k1_zmmmt_imm8_512_66_0F3A_W0_D1 3,// MVEX_Vcvtfxpntpd2dq_zmm_k1_zmmmt_imm8 + 0,// Via_undoc_F30FA6F0_16 + 0,// Via_undoc_F30FA6F0_32 + 0,// Via_undoc_F30FA6F0_64 + 0,// Via_undoc_F30FA6F8_16 + 0,// Via_undoc_F30FA6F8_32 + 0,// Via_undoc_F30FA6F8_64 + 0,// Xsha512_16 + 0,// Xsha512_32 + 0,// Xsha512_64 + 0,// Xstore2_16 + 0,// Xstore2_32 + 0,// Xstore2_64 ]; diff --git a/src/rust/iced-x86/src/mnemonic.rs b/src/rust/iced-x86/src/mnemonic.rs index a49ae01ae..700817bce 100644 --- a/src/rust/iced-x86/src/mnemonic.rs +++ b/src/rust/iced-x86/src/mnemonic.rs @@ -1849,9 +1849,11 @@ pub enum Mnemonic { Vscatterpf0hintdps = 1831, Vsubrpd = 1832, Vsubrps = 1833, + Xsha512 = 1834, + Xstore2 = 1835, } #[rustfmt::skip] -static GEN_DEBUG_MNEMONIC: [&str; 1834] = [ +static GEN_DEBUG_MNEMONIC: [&str; 1836] = [ "INVALID", "Aaa", "Aad", @@ -3686,6 +3688,8 @@ static GEN_DEBUG_MNEMONIC: [&str; 1834] = [ "Vscatterpf0hintdps", "Vsubrpd", "Vsubrps", + "Xsha512", + "Xstore2", ]; impl fmt::Debug for Mnemonic { #[inline] diff --git a/src/rust/iced-x86/src/mnemonics.rs b/src/rust/iced-x86/src/mnemonics.rs index ac5c05472..1eb42c253 100644 --- a/src/rust/iced-x86/src/mnemonics.rs +++ b/src/rust/iced-x86/src/mnemonics.rs @@ -4826,4 +4826,16 @@ pub(super) static TO_MNEMONIC: [Mnemonic; IcedConstants::CODE_ENUM_COUNT] = [ Mnemonic::Undoc,// MVEX_Undoc_zmm_k1_zmmmt_imm8_512_66_0F3A_W0_D0 Mnemonic::Undoc,// MVEX_Undoc_zmm_k1_zmmmt_imm8_512_66_0F3A_W0_D1 Mnemonic::Vcvtfxpntpd2dq,// MVEX_Vcvtfxpntpd2dq_zmm_k1_zmmmt_imm8 + Mnemonic::Undoc,// Via_undoc_F30FA6F0_16 + Mnemonic::Undoc,// Via_undoc_F30FA6F0_32 + Mnemonic::Undoc,// Via_undoc_F30FA6F0_64 + Mnemonic::Undoc,// Via_undoc_F30FA6F8_16 + Mnemonic::Undoc,// Via_undoc_F30FA6F8_32 + Mnemonic::Undoc,// Via_undoc_F30FA6F8_64 + Mnemonic::Xsha512,// Xsha512_16 + Mnemonic::Xsha512,// Xsha512_32 + Mnemonic::Xsha512,// Xsha512_64 + Mnemonic::Xstore2,// Xstore2_16 + Mnemonic::Xstore2,// Xstore2_32 + Mnemonic::Xstore2,// Xstore2_64 ]; diff --git a/src/rust/iced-x86/src/test_utils/from_str_conv/code_table.rs b/src/rust/iced-x86/src/test_utils/from_str_conv/code_table.rs index 84828ffd9..5bebcafa4 100644 --- a/src/rust/iced-x86/src/test_utils/from_str_conv/code_table.rs +++ b/src/rust/iced-x86/src/test_utils/from_str_conv/code_table.rs @@ -9,7 +9,7 @@ lazy_static! { pub(super) static ref TO_CODE_HASH: HashMap<&'static str, Code> = { // GENERATOR-BEGIN: CodeHash // ⚠️This was generated by GENERATOR!🦹‍♂️ - let mut h = HashMap::with_capacity(4818); + let mut h = HashMap::with_capacity(4830); let _ = h.insert("INVALID", Code::INVALID); let _ = h.insert("DeclareByte", Code::DeclareByte); let _ = h.insert("DeclareWord", Code::DeclareWord); @@ -4828,6 +4828,18 @@ lazy_static! { let _ = h.insert("MVEX_Undoc_zmm_k1_zmmmt_imm8_512_66_0F3A_W0_D0", Code::MVEX_Undoc_zmm_k1_zmmmt_imm8_512_66_0F3A_W0_D0); let _ = h.insert("MVEX_Undoc_zmm_k1_zmmmt_imm8_512_66_0F3A_W0_D1", Code::MVEX_Undoc_zmm_k1_zmmmt_imm8_512_66_0F3A_W0_D1); let _ = h.insert("MVEX_Vcvtfxpntpd2dq_zmm_k1_zmmmt_imm8", Code::MVEX_Vcvtfxpntpd2dq_zmm_k1_zmmmt_imm8); + let _ = h.insert("Via_undoc_F30FA6F0_16", Code::Via_undoc_F30FA6F0_16); + let _ = h.insert("Via_undoc_F30FA6F0_32", Code::Via_undoc_F30FA6F0_32); + let _ = h.insert("Via_undoc_F30FA6F0_64", Code::Via_undoc_F30FA6F0_64); + let _ = h.insert("Via_undoc_F30FA6F8_16", Code::Via_undoc_F30FA6F8_16); + let _ = h.insert("Via_undoc_F30FA6F8_32", Code::Via_undoc_F30FA6F8_32); + let _ = h.insert("Via_undoc_F30FA6F8_64", Code::Via_undoc_F30FA6F8_64); + let _ = h.insert("Xsha512_16", Code::Xsha512_16); + let _ = h.insert("Xsha512_32", Code::Xsha512_32); + let _ = h.insert("Xsha512_64", Code::Xsha512_64); + let _ = h.insert("Xstore2_16", Code::Xstore2_16); + let _ = h.insert("Xstore2_32", Code::Xstore2_32); + let _ = h.insert("Xstore2_64", Code::Xstore2_64); // GENERATOR-END: CodeHash h }; diff --git a/src/rust/iced-x86/src/test_utils/from_str_conv/cpuid_feature_table.rs b/src/rust/iced-x86/src/test_utils/from_str_conv/cpuid_feature_table.rs index 13fb891f0..3a820981c 100644 --- a/src/rust/iced-x86/src/test_utils/from_str_conv/cpuid_feature_table.rs +++ b/src/rust/iced-x86/src/test_utils/from_str_conv/cpuid_feature_table.rs @@ -9,7 +9,7 @@ lazy_static! { pub(super) static ref TO_CPUID_FEATURE_HASH: HashMap<&'static str, CpuidFeature> = { // GENERATOR-BEGIN: CpuidFeatureHash // ⚠️This was generated by GENERATOR!🦹‍♂️ - let mut h = HashMap::with_capacity(161); + let mut h = HashMap::with_capacity(162); let _ = h.insert("INTEL8086", CpuidFeature::INTEL8086); let _ = h.insert("INTEL8086_ONLY", CpuidFeature::INTEL8086_ONLY); let _ = h.insert("INTEL186", CpuidFeature::INTEL186); @@ -171,6 +171,7 @@ lazy_static! { let _ = h.insert("AVX512_FP16", CpuidFeature::AVX512_FP16); let _ = h.insert("UDBG", CpuidFeature::UDBG); let _ = h.insert("KNC", CpuidFeature::KNC); + let _ = h.insert("PADLOCK_UNDOC", CpuidFeature::PADLOCK_UNDOC); // GENERATOR-END: CpuidFeatureHash h }; diff --git a/src/rust/iced-x86/src/test_utils/from_str_conv/mnemonic_table.rs b/src/rust/iced-x86/src/test_utils/from_str_conv/mnemonic_table.rs index a1ad9519c..28017b100 100644 --- a/src/rust/iced-x86/src/test_utils/from_str_conv/mnemonic_table.rs +++ b/src/rust/iced-x86/src/test_utils/from_str_conv/mnemonic_table.rs @@ -9,7 +9,7 @@ lazy_static! { pub(super) static ref TO_MNEMONIC_HASH: HashMap<&'static str, Mnemonic> = { // GENERATOR-BEGIN: MnemonicHash // ⚠️This was generated by GENERATOR!🦹‍♂️ - let mut h = HashMap::with_capacity(1834); + let mut h = HashMap::with_capacity(1836); let _ = h.insert("INVALID", Mnemonic::INVALID); let _ = h.insert("Aaa", Mnemonic::Aaa); let _ = h.insert("Aad", Mnemonic::Aad); @@ -1844,6 +1844,8 @@ lazy_static! { let _ = h.insert("Vscatterpf0hintdps", Mnemonic::Vscatterpf0hintdps); let _ = h.insert("Vsubrpd", Mnemonic::Vsubrpd); let _ = h.insert("Vsubrps", Mnemonic::Vsubrps); + let _ = h.insert("Xsha512", Mnemonic::Xsha512); + let _ = h.insert("Xstore2", Mnemonic::Xstore2); // GENERATOR-END: MnemonicHash h };