diff --git a/esp32p4/device.x b/esp32p4/device.x index 770868f421..5002f73592 100644 --- a/esp32p4/device.x +++ b/esp32p4/device.x @@ -22,6 +22,10 @@ PROVIDE(I2S1 = DefaultHandler); PROVIDE(I2S2 = DefaultHandler); PROVIDE(UHCI0 = DefaultHandler); PROVIDE(UART0 = DefaultHandler); +PROVIDE(UART1 = DefaultHandler); +PROVIDE(UART2 = DefaultHandler); +PROVIDE(UART3 = DefaultHandler); +PROVIDE(UART4 = DefaultHandler); PROVIDE(PWM0 = DefaultHandler); PROVIDE(PWM1 = DefaultHandler); PROVIDE(TWAI0 = DefaultHandler); @@ -40,6 +44,18 @@ PROVIDE(LEDC = DefaultHandler); PROVIDE(SYSTIMER_TARGET0 = DefaultHandler); PROVIDE(SYSTIMER_TARGET1 = DefaultHandler); PROVIDE(SYSTIMER_TARGET2 = DefaultHandler); +PROVIDE(AHB_PDMA_IN_CH0 = DefaultHandler); +PROVIDE(AHB_PDMA_IN_CH1 = DefaultHandler); +PROVIDE(AHB_PDMA_IN_CH2 = DefaultHandler); +PROVIDE(AHB_PDMA_OUT_CH0 = DefaultHandler); +PROVIDE(AHB_PDMA_OUT_CH1 = DefaultHandler); +PROVIDE(AHB_PDMA_OUT_CH2 = DefaultHandler); +PROVIDE(AXI_PDMA_IN_CH0 = DefaultHandler); +PROVIDE(AXI_PDMA_IN_CH1 = DefaultHandler); +PROVIDE(AXI_PDMA_IN_CH2 = DefaultHandler); +PROVIDE(AXI_PDMA_OUT_CH0 = DefaultHandler); +PROVIDE(AXI_PDMA_OUT_CH1 = DefaultHandler); +PROVIDE(AXI_PDMA_OUT_CH2 = DefaultHandler); PROVIDE(RSA = DefaultHandler); PROVIDE(AES = DefaultHandler); PROVIDE(SHA = DefaultHandler); diff --git a/esp32p4/src/ahb_dma.rs b/esp32p4/src/ahb_dma.rs new file mode 100644 index 0000000000..7b525cbef3 --- /dev/null +++ b/esp32p4/src/ahb_dma.rs @@ -0,0 +1,1788 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + in_int_raw_ch: (), + _reserved1: [u8; 0x04], + in_int_st_ch: (), + _reserved2: [u8; 0x04], + in_int_ena_ch: (), + _reserved3: [u8; 0x04], + in_int_clr_ch: (), + _reserved4: [u8; 0x24], + out_int_raw_ch: (), + _reserved5: [u8; 0x04], + out_int_st_ch: (), + _reserved6: [u8; 0x04], + out_int_ena_ch: (), + _reserved7: [u8; 0x04], + out_int_clr_ch: (), + _reserved8: [u8; 0x24], + ahb_test: AHB_TEST, + misc_conf: MISC_CONF, + date: DATE, + _reserved11: [u8; 0x04], + in_conf0_ch: (), + _reserved12: [u8; 0x04], + in_conf1_ch: (), + _reserved13: [u8; 0x04], + infifo_status_ch: (), + _reserved14: [u8; 0x04], + in_pop_ch: (), + _reserved15: [u8; 0x04], + in_link_ch: (), + _reserved16: [u8; 0x04], + in_state_ch: (), + _reserved17: [u8; 0x04], + in_suc_eof_des_addr_ch: (), + _reserved18: [u8; 0x04], + in_err_eof_des_addr_ch: (), + _reserved19: [u8; 0x04], + in_dscr_ch: (), + _reserved20: [u8; 0x04], + in_dscr_bf0_ch: (), + _reserved21: [u8; 0x04], + in_dscr_bf1_ch: (), + _reserved22: [u8; 0x04], + in_pri_ch: (), + _reserved23: [u8; 0x04], + in_peri_sel_ch: (), + _reserved24: [u8; 0x30], + out_conf0_ch0: OUT_CONF0_CH0, + out_conf1_ch: (), + _reserved26: [u8; 0x04], + outfifo_status_ch: (), + _reserved27: [u8; 0x04], + out_push_ch: (), + _reserved28: [u8; 0x04], + out_link_ch: (), + _reserved29: [u8; 0x04], + out_state_ch: (), + _reserved30: [u8; 0x04], + out_eof_des_addr_ch: (), + _reserved31: [u8; 0x04], + out_eof_bfr_des_addr_ch: (), + _reserved32: [u8; 0x04], + out_dscr_ch: (), + _reserved33: [u8; 0x04], + out_dscr_bf0_ch: (), + _reserved34: [u8; 0x04], + out_dscr_bf1_ch: (), + _reserved35: [u8; 0x04], + out_pri_ch: (), + _reserved36: [u8; 0x04], + out_peri_sel_ch: (), + _reserved37: [u8; 0x90], + out_conf0_ch: (), + _reserved38: [u8; 0x012c], + out_crc_init_data_ch: (), + _reserved39: [u8; 0x04], + tx_crc_width_ch: (), + _reserved40: [u8; 0x04], + out_crc_clear_ch: (), + _reserved41: [u8; 0x04], + out_crc_final_result_ch: (), + _reserved42: [u8; 0x04], + tx_crc_en_wr_data_ch: (), + _reserved43: [u8; 0x04], + tx_crc_en_addr_ch: (), + _reserved44: [u8; 0x04], + tx_crc_data_en_wr_data_ch: (), + _reserved45: [u8; 0x04], + tx_crc_data_en_addr_ch: (), + _reserved46: [u8; 0x04], + tx_ch_arb_weigh_ch: (), + _reserved47: [u8; 0x04], + tx_arb_weigh_opt_dir_ch: (), + _reserved48: [u8; 0x54], + in_crc_init_data_ch: (), + _reserved49: [u8; 0x04], + rx_crc_width_ch: (), + _reserved50: [u8; 0x04], + in_crc_clear_ch: (), + _reserved51: [u8; 0x04], + in_crc_final_result_ch: (), + _reserved52: [u8; 0x04], + rx_crc_en_wr_data_ch: (), + _reserved53: [u8; 0x04], + rx_crc_en_addr_ch: (), + _reserved54: [u8; 0x04], + rx_crc_data_en_wr_data_ch: (), + _reserved55: [u8; 0x04], + rx_crc_data_en_addr_ch: (), + _reserved56: [u8; 0x04], + rx_ch_arb_weigh_ch: (), + _reserved57: [u8; 0x04], + rx_arb_weigh_opt_dir_ch: (), + _reserved58: [u8; 0x54], + in_link_addr_ch: [IN_LINK_ADDR_CH; 3], + out_link_addr_ch: [OUT_LINK_ADDR_CH; 3], + intr_mem_start_addr: INTR_MEM_START_ADDR, + intr_mem_end_addr: INTR_MEM_END_ADDR, + arb_timeout_tx: ARB_TIMEOUT_TX, + arb_timeout_rx: ARB_TIMEOUT_RX, + weight_en_tx: WEIGHT_EN_TX, + weight_en_rx: WEIGHT_EN_RX, +} +impl RegisterBlock { + #[doc = "0x00..0x0c - Raw status interrupt of channel 0"] + #[inline(always)] + pub const fn in_int_raw_ch(&self, n: usize) -> &IN_INT_RAW_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { &*(self as *const Self).cast::().add(0).add(16 * n).cast() } + } + #[doc = "Iterator for array of:"] + #[doc = "0x00..0x0c - Raw status interrupt of channel 0"] + #[inline(always)] + pub fn in_int_raw_ch_iter(&self) -> impl Iterator { + (0..3).map(|n| unsafe { &*(self as *const Self).cast::().add(0).add(16 * n).cast() }) + } + #[doc = "0x04..0x10 - Masked interrupt of channel 0"] + #[inline(always)] + pub const fn in_int_st_ch(&self, n: usize) -> &IN_INT_ST_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { &*(self as *const Self).cast::().add(4).add(16 * n).cast() } + } + #[doc = "Iterator for array of:"] + #[doc = "0x04..0x10 - Masked interrupt of channel 0"] + #[inline(always)] + pub fn in_int_st_ch_iter(&self) -> impl Iterator { + (0..3).map(|n| unsafe { &*(self as *const Self).cast::().add(4).add(16 * n).cast() }) + } + #[doc = "0x08..0x14 - Interrupt enable bits of channel 0"] + #[inline(always)] + pub const fn in_int_ena_ch(&self, n: usize) -> &IN_INT_ENA_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { &*(self as *const Self).cast::().add(8).add(16 * n).cast() } + } + #[doc = "Iterator for array of:"] + #[doc = "0x08..0x14 - Interrupt enable bits of channel 0"] + #[inline(always)] + pub fn in_int_ena_ch_iter(&self) -> impl Iterator { + (0..3).map(|n| unsafe { &*(self as *const Self).cast::().add(8).add(16 * n).cast() }) + } + #[doc = "0x0c..0x18 - Interrupt clear bits of channel 0"] + #[inline(always)] + pub const fn in_int_clr_ch(&self, n: usize) -> &IN_INT_CLR_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(12) + .add(16 * n) + .cast() + } + } + #[doc = "Iterator for array of:"] + #[doc = "0x0c..0x18 - Interrupt clear bits of channel 0"] + #[inline(always)] + pub fn in_int_clr_ch_iter(&self) -> impl Iterator { + (0..3).map(|n| unsafe { + &*(self as *const Self) + .cast::() + .add(12) + .add(16 * n) + .cast() + }) + } + #[doc = "0x30..0x3c - Raw status interrupt of channel 0"] + #[inline(always)] + pub const fn out_int_raw_ch(&self, n: usize) -> &OUT_INT_RAW_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(48) + .add(16 * n) + .cast() + } + } + #[doc = "Iterator for array of:"] + #[doc = "0x30..0x3c - Raw status interrupt of channel 0"] + #[inline(always)] + pub fn out_int_raw_ch_iter(&self) -> impl Iterator { + (0..3).map(|n| unsafe { + &*(self as *const Self) + .cast::() + .add(48) + .add(16 * n) + .cast() + }) + } + #[doc = "0x34..0x40 - Masked interrupt of channel 0"] + #[inline(always)] + pub const fn out_int_st_ch(&self, n: usize) -> &OUT_INT_ST_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(52) + .add(16 * n) + .cast() + } + } + #[doc = "Iterator for array of:"] + #[doc = "0x34..0x40 - Masked interrupt of channel 0"] + #[inline(always)] + pub fn out_int_st_ch_iter(&self) -> impl Iterator { + (0..3).map(|n| unsafe { + &*(self as *const Self) + .cast::() + .add(52) + .add(16 * n) + .cast() + }) + } + #[doc = "0x38..0x44 - Interrupt enable bits of channel 0"] + #[inline(always)] + pub const fn out_int_ena_ch(&self, n: usize) -> &OUT_INT_ENA_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(56) + .add(16 * n) + .cast() + } + } + #[doc = "Iterator for array of:"] + #[doc = "0x38..0x44 - Interrupt enable bits of channel 0"] + #[inline(always)] + pub fn out_int_ena_ch_iter(&self) -> impl Iterator { + (0..3).map(|n| unsafe { + &*(self as *const Self) + .cast::() + .add(56) + .add(16 * n) + .cast() + }) + } + #[doc = "0x3c..0x48 - Interrupt clear bits of channel 0"] + #[inline(always)] + pub const fn out_int_clr_ch(&self, n: usize) -> &OUT_INT_CLR_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(60) + .add(16 * n) + .cast() + } + } + #[doc = "Iterator for array of:"] + #[doc = "0x3c..0x48 - Interrupt clear bits of channel 0"] + #[inline(always)] + pub fn out_int_clr_ch_iter(&self) -> impl Iterator { + (0..3).map(|n| unsafe { + &*(self as *const Self) + .cast::() + .add(60) + .add(16 * n) + .cast() + }) + } + #[doc = "0x60 - reserved"] + #[inline(always)] + pub const fn ahb_test(&self) -> &AHB_TEST { + &self.ahb_test + } + #[doc = "0x64 - MISC register"] + #[inline(always)] + pub const fn misc_conf(&self) -> &MISC_CONF { + &self.misc_conf + } + #[doc = "0x68 - Version control register"] + #[inline(always)] + pub const fn date(&self) -> &DATE { + &self.date + } + #[doc = "0x70..0x7c - Configure 0 register of Rx channel 0"] + #[inline(always)] + pub const fn in_conf0_ch(&self, n: usize) -> &IN_CONF0_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(112) + .add(192 * n) + .cast() + } + } + #[doc = "Iterator for array of:"] + #[doc = "0x70..0x7c - Configure 0 register of Rx channel 0"] + #[inline(always)] + pub fn in_conf0_ch_iter(&self) -> impl Iterator { + (0..3).map(|n| unsafe { + &*(self as *const Self) + .cast::() + .add(112) + .add(192 * n) + .cast() + }) + } + #[doc = "0x74..0x80 - Configure 1 register of Rx channel 0"] + #[inline(always)] + pub const fn in_conf1_ch(&self, n: usize) -> &IN_CONF1_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(116) + .add(192 * n) + .cast() + } + } + #[doc = "Iterator for array of:"] + #[doc = "0x74..0x80 - Configure 1 register of Rx channel 0"] + #[inline(always)] + pub fn in_conf1_ch_iter(&self) -> impl Iterator { + (0..3).map(|n| unsafe { + &*(self as *const Self) + .cast::() + .add(116) + .add(192 * n) + .cast() + }) + } + #[doc = "0x78..0x84 - Receive FIFO status of Rx channel 0"] + #[inline(always)] + pub const fn infifo_status_ch(&self, n: usize) -> &INFIFO_STATUS_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(120) + .add(192 * n) + .cast() + } + } + #[doc = "Iterator for array of:"] + #[doc = "0x78..0x84 - Receive FIFO status of Rx channel 0"] + #[inline(always)] + pub fn infifo_status_ch_iter(&self) -> impl Iterator { + (0..3).map(|n| unsafe { + &*(self as *const Self) + .cast::() + .add(120) + .add(192 * n) + .cast() + }) + } + #[doc = "0x7c..0x88 - Pop control register of Rx channel 0"] + #[inline(always)] + pub const fn in_pop_ch(&self, n: usize) -> &IN_POP_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(124) + .add(192 * n) + .cast() + } + } + #[doc = "Iterator for array of:"] + #[doc = "0x7c..0x88 - Pop control register of Rx channel 0"] + #[inline(always)] + pub fn in_pop_ch_iter(&self) -> impl Iterator { + (0..3).map(|n| unsafe { + &*(self as *const Self) + .cast::() + .add(124) + .add(192 * n) + .cast() + }) + } + #[doc = "0x80..0x8c - Link descriptor configure and control register of Rx channel 0"] + #[inline(always)] + pub const fn in_link_ch(&self, n: usize) -> &IN_LINK_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(128) + .add(192 * n) + .cast() + } + } + #[doc = "Iterator for array of:"] + #[doc = "0x80..0x8c - Link descriptor configure and control register of Rx channel 0"] + #[inline(always)] + pub fn in_link_ch_iter(&self) -> impl Iterator { + (0..3).map(|n| unsafe { + &*(self as *const Self) + .cast::() + .add(128) + .add(192 * n) + .cast() + }) + } + #[doc = "0x84..0x90 - Receive status of Rx channel 0"] + #[inline(always)] + pub const fn in_state_ch(&self, n: usize) -> &IN_STATE_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(132) + .add(192 * n) + .cast() + } + } + #[doc = "Iterator for array of:"] + #[doc = "0x84..0x90 - Receive status of Rx channel 0"] + #[inline(always)] + pub fn in_state_ch_iter(&self) -> impl Iterator { + (0..3).map(|n| unsafe { + &*(self as *const Self) + .cast::() + .add(132) + .add(192 * n) + .cast() + }) + } + #[doc = "0x88..0x94 - Inlink descriptor address when EOF occurs of Rx channel 0"] + #[inline(always)] + pub const fn in_suc_eof_des_addr_ch(&self, n: usize) -> &IN_SUC_EOF_DES_ADDR_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(136) + .add(192 * n) + .cast() + } + } + #[doc = "Iterator for array of:"] + #[doc = "0x88..0x94 - Inlink descriptor address when EOF occurs of Rx channel 0"] + #[inline(always)] + pub fn in_suc_eof_des_addr_ch_iter(&self) -> impl Iterator { + (0..3).map(|n| unsafe { + &*(self as *const Self) + .cast::() + .add(136) + .add(192 * n) + .cast() + }) + } + #[doc = "0x8c..0x98 - Inlink descriptor address when errors occur of Rx channel 0"] + #[inline(always)] + pub const fn in_err_eof_des_addr_ch(&self, n: usize) -> &IN_ERR_EOF_DES_ADDR_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(140) + .add(192 * n) + .cast() + } + } + #[doc = "Iterator for array of:"] + #[doc = "0x8c..0x98 - Inlink descriptor address when errors occur of Rx channel 0"] + #[inline(always)] + pub fn in_err_eof_des_addr_ch_iter(&self) -> impl Iterator { + (0..3).map(|n| unsafe { + &*(self as *const Self) + .cast::() + .add(140) + .add(192 * n) + .cast() + }) + } + #[doc = "0x90..0x9c - Current inlink descriptor address of Rx channel 0"] + #[inline(always)] + pub const fn in_dscr_ch(&self, n: usize) -> &IN_DSCR_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(144) + .add(192 * n) + .cast() + } + } + #[doc = "Iterator for array of:"] + #[doc = "0x90..0x9c - Current inlink descriptor address of Rx channel 0"] + #[inline(always)] + pub fn in_dscr_ch_iter(&self) -> impl Iterator { + (0..3).map(|n| unsafe { + &*(self as *const Self) + .cast::() + .add(144) + .add(192 * n) + .cast() + }) + } + #[doc = "0x94..0xa0 - The last inlink descriptor address of Rx channel 0"] + #[inline(always)] + pub const fn in_dscr_bf0_ch(&self, n: usize) -> &IN_DSCR_BF0_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(148) + .add(192 * n) + .cast() + } + } + #[doc = "Iterator for array of:"] + #[doc = "0x94..0xa0 - The last inlink descriptor address of Rx channel 0"] + #[inline(always)] + pub fn in_dscr_bf0_ch_iter(&self) -> impl Iterator { + (0..3).map(|n| unsafe { + &*(self as *const Self) + .cast::() + .add(148) + .add(192 * n) + .cast() + }) + } + #[doc = "0x98..0xa4 - The second-to-last inlink descriptor address of Rx channel 0"] + #[inline(always)] + pub const fn in_dscr_bf1_ch(&self, n: usize) -> &IN_DSCR_BF1_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(152) + .add(192 * n) + .cast() + } + } + #[doc = "Iterator for array of:"] + #[doc = "0x98..0xa4 - The second-to-last inlink descriptor address of Rx channel 0"] + #[inline(always)] + pub fn in_dscr_bf1_ch_iter(&self) -> impl Iterator { + (0..3).map(|n| unsafe { + &*(self as *const Self) + .cast::() + .add(152) + .add(192 * n) + .cast() + }) + } + #[doc = "0x9c..0xa8 - Priority register of Rx channel 0"] + #[inline(always)] + pub const fn in_pri_ch(&self, n: usize) -> &IN_PRI_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(156) + .add(192 * n) + .cast() + } + } + #[doc = "Iterator for array of:"] + #[doc = "0x9c..0xa8 - Priority register of Rx channel 0"] + #[inline(always)] + pub fn in_pri_ch_iter(&self) -> impl Iterator { + (0..3).map(|n| unsafe { + &*(self as *const Self) + .cast::() + .add(156) + .add(192 * n) + .cast() + }) + } + #[doc = "0xa0..0xac - Peripheral selection of Rx channel 0"] + #[inline(always)] + pub const fn in_peri_sel_ch(&self, n: usize) -> &IN_PERI_SEL_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(160) + .add(192 * n) + .cast() + } + } + #[doc = "Iterator for array of:"] + #[doc = "0xa0..0xac - Peripheral selection of Rx channel 0"] + #[inline(always)] + pub fn in_peri_sel_ch_iter(&self) -> impl Iterator { + (0..3).map(|n| unsafe { + &*(self as *const Self) + .cast::() + .add(160) + .add(192 * n) + .cast() + }) + } + #[doc = "0xd0 - Configure 0 register of Tx channel 0"] + #[inline(always)] + pub const fn out_conf0_ch0(&self) -> &OUT_CONF0_CH0 { + &self.out_conf0_ch0 + } + #[doc = "0xd4..0xe0 - Configure 1 register of Tx channel 0"] + #[inline(always)] + pub const fn out_conf1_ch(&self, n: usize) -> &OUT_CONF1_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(212) + .add(192 * n) + .cast() + } + } + #[doc = "Iterator for array of:"] + #[doc = "0xd4..0xe0 - Configure 1 register of Tx channel 0"] + #[inline(always)] + pub fn out_conf1_ch_iter(&self) -> impl Iterator { + (0..3).map(|n| unsafe { + &*(self as *const Self) + .cast::() + .add(212) + .add(192 * n) + .cast() + }) + } + #[doc = "0xd8..0xe4 - Transmit FIFO status of Tx channel 0"] + #[inline(always)] + pub const fn outfifo_status_ch(&self, n: usize) -> &OUTFIFO_STATUS_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(216) + .add(192 * n) + .cast() + } + } + #[doc = "Iterator for array of:"] + #[doc = "0xd8..0xe4 - Transmit FIFO status of Tx channel 0"] + #[inline(always)] + pub fn outfifo_status_ch_iter(&self) -> impl Iterator { + (0..3).map(|n| unsafe { + &*(self as *const Self) + .cast::() + .add(216) + .add(192 * n) + .cast() + }) + } + #[doc = "0xdc..0xe8 - Push control register of Rx channel 0"] + #[inline(always)] + pub const fn out_push_ch(&self, n: usize) -> &OUT_PUSH_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(220) + .add(192 * n) + .cast() + } + } + #[doc = "Iterator for array of:"] + #[doc = "0xdc..0xe8 - Push control register of Rx channel 0"] + #[inline(always)] + pub fn out_push_ch_iter(&self) -> impl Iterator { + (0..3).map(|n| unsafe { + &*(self as *const Self) + .cast::() + .add(220) + .add(192 * n) + .cast() + }) + } + #[doc = "0xe0..0xec - Link descriptor configure and control register of Tx channel 0"] + #[inline(always)] + pub const fn out_link_ch(&self, n: usize) -> &OUT_LINK_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(224) + .add(192 * n) + .cast() + } + } + #[doc = "Iterator for array of:"] + #[doc = "0xe0..0xec - Link descriptor configure and control register of Tx channel 0"] + #[inline(always)] + pub fn out_link_ch_iter(&self) -> impl Iterator { + (0..3).map(|n| unsafe { + &*(self as *const Self) + .cast::() + .add(224) + .add(192 * n) + .cast() + }) + } + #[doc = "0xe4..0xf0 - Transmit status of Tx channel 0"] + #[inline(always)] + pub const fn out_state_ch(&self, n: usize) -> &OUT_STATE_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(228) + .add(192 * n) + .cast() + } + } + #[doc = "Iterator for array of:"] + #[doc = "0xe4..0xf0 - Transmit status of Tx channel 0"] + #[inline(always)] + pub fn out_state_ch_iter(&self) -> impl Iterator { + (0..3).map(|n| unsafe { + &*(self as *const Self) + .cast::() + .add(228) + .add(192 * n) + .cast() + }) + } + #[doc = "0xe8..0xf4 - Outlink descriptor address when EOF occurs of Tx channel 0"] + #[inline(always)] + pub const fn out_eof_des_addr_ch(&self, n: usize) -> &OUT_EOF_DES_ADDR_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(232) + .add(192 * n) + .cast() + } + } + #[doc = "Iterator for array of:"] + #[doc = "0xe8..0xf4 - Outlink descriptor address when EOF occurs of Tx channel 0"] + #[inline(always)] + pub fn out_eof_des_addr_ch_iter(&self) -> impl Iterator { + (0..3).map(|n| unsafe { + &*(self as *const Self) + .cast::() + .add(232) + .add(192 * n) + .cast() + }) + } + #[doc = "0xec..0xf8 - The last outlink descriptor address when EOF occurs of Tx channel 0"] + #[inline(always)] + pub const fn out_eof_bfr_des_addr_ch(&self, n: usize) -> &OUT_EOF_BFR_DES_ADDR_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(236) + .add(192 * n) + .cast() + } + } + #[doc = "Iterator for array of:"] + #[doc = "0xec..0xf8 - The last outlink descriptor address when EOF occurs of Tx channel 0"] + #[inline(always)] + pub fn out_eof_bfr_des_addr_ch_iter(&self) -> impl Iterator { + (0..3).map(|n| unsafe { + &*(self as *const Self) + .cast::() + .add(236) + .add(192 * n) + .cast() + }) + } + #[doc = "0xf0..0xfc - Current inlink descriptor address of Tx channel 0"] + #[inline(always)] + pub const fn out_dscr_ch(&self, n: usize) -> &OUT_DSCR_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(240) + .add(192 * n) + .cast() + } + } + #[doc = "Iterator for array of:"] + #[doc = "0xf0..0xfc - Current inlink descriptor address of Tx channel 0"] + #[inline(always)] + pub fn out_dscr_ch_iter(&self) -> impl Iterator { + (0..3).map(|n| unsafe { + &*(self as *const Self) + .cast::() + .add(240) + .add(192 * n) + .cast() + }) + } + #[doc = "0xf4..0x100 - The last inlink descriptor address of Tx channel 0"] + #[inline(always)] + pub const fn out_dscr_bf0_ch(&self, n: usize) -> &OUT_DSCR_BF0_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(244) + .add(192 * n) + .cast() + } + } + #[doc = "Iterator for array of:"] + #[doc = "0xf4..0x100 - The last inlink descriptor address of Tx channel 0"] + #[inline(always)] + pub fn out_dscr_bf0_ch_iter(&self) -> impl Iterator { + (0..3).map(|n| unsafe { + &*(self as *const Self) + .cast::() + .add(244) + .add(192 * n) + .cast() + }) + } + #[doc = "0xf8..0x104 - The second-to-last inlink descriptor address of Tx channel 0"] + #[inline(always)] + pub const fn out_dscr_bf1_ch(&self, n: usize) -> &OUT_DSCR_BF1_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(248) + .add(192 * n) + .cast() + } + } + #[doc = "Iterator for array of:"] + #[doc = "0xf8..0x104 - The second-to-last inlink descriptor address of Tx channel 0"] + #[inline(always)] + pub fn out_dscr_bf1_ch_iter(&self) -> impl Iterator { + (0..3).map(|n| unsafe { + &*(self as *const Self) + .cast::() + .add(248) + .add(192 * n) + .cast() + }) + } + #[doc = "0xfc..0x108 - Priority register of Tx channel 0."] + #[inline(always)] + pub const fn out_pri_ch(&self, n: usize) -> &OUT_PRI_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(252) + .add(192 * n) + .cast() + } + } + #[doc = "Iterator for array of:"] + #[doc = "0xfc..0x108 - Priority register of Tx channel 0."] + #[inline(always)] + pub fn out_pri_ch_iter(&self) -> impl Iterator { + (0..3).map(|n| unsafe { + &*(self as *const Self) + .cast::() + .add(252) + .add(192 * n) + .cast() + }) + } + #[doc = "0x100..0x10c - Peripheral selection of Tx channel 0"] + #[inline(always)] + pub const fn out_peri_sel_ch(&self, n: usize) -> &OUT_PERI_SEL_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(256) + .add(192 * n) + .cast() + } + } + #[doc = "Iterator for array of:"] + #[doc = "0x100..0x10c - Peripheral selection of Tx channel 0"] + #[inline(always)] + pub fn out_peri_sel_ch_iter(&self) -> impl Iterator { + (0..3).map(|n| unsafe { + &*(self as *const Self) + .cast::() + .add(256) + .add(192 * n) + .cast() + }) + } + #[doc = "0x190..0x198 - Configure 0 register of Tx channel 1"] + #[inline(always)] + pub const fn out_conf0_ch(&self, n: usize) -> &OUT_CONF0_CH { + #[allow(clippy::no_effect)] + [(); 2][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(400) + .add(192 * n) + .cast() + } + } + #[doc = "Iterator for array of:"] + #[doc = "0x190..0x198 - Configure 0 register of Tx channel 1"] + #[inline(always)] + pub fn out_conf0_ch_iter(&self) -> impl Iterator { + (0..2).map(|n| unsafe { + &*(self as *const Self) + .cast::() + .add(400) + .add(192 * n) + .cast() + }) + } + #[doc = "0x2bc..0x2c8 - This register is used to config ch0 crc initial data(max 32 bit)"] + #[inline(always)] + pub const fn out_crc_init_data_ch(&self, n: usize) -> &OUT_CRC_INIT_DATA_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(700) + .add(40 * n) + .cast() + } + } + #[doc = "Iterator for array of:"] + #[doc = "0x2bc..0x2c8 - This register is used to config ch0 crc initial data(max 32 bit)"] + #[inline(always)] + pub fn out_crc_init_data_ch_iter(&self) -> impl Iterator { + (0..3).map(|n| unsafe { + &*(self as *const Self) + .cast::() + .add(700) + .add(40 * n) + .cast() + }) + } + #[doc = "0x2c0..0x2cc - This register is used to confiig tx ch0 crc result width,2'b00 mean crc_width <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean 24<crc_width<=32"] + #[inline(always)] + pub const fn tx_crc_width_ch(&self, n: usize) -> &TX_CRC_WIDTH_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(704) + .add(40 * n) + .cast() + } + } + #[doc = "Iterator for array of:"] + #[doc = "0x2c0..0x2cc - This register is used to confiig tx ch0 crc result width,2'b00 mean crc_width <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean 24<crc_width<=32"] + #[inline(always)] + pub fn tx_crc_width_ch_iter(&self) -> impl Iterator { + (0..3).map(|n| unsafe { + &*(self as *const Self) + .cast::() + .add(704) + .add(40 * n) + .cast() + }) + } + #[doc = "0x2c4..0x2d0 - This register is used to clear ch0 crc result"] + #[inline(always)] + pub const fn out_crc_clear_ch(&self, n: usize) -> &OUT_CRC_CLEAR_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(708) + .add(40 * n) + .cast() + } + } + #[doc = "Iterator for array of:"] + #[doc = "0x2c4..0x2d0 - This register is used to clear ch0 crc result"] + #[inline(always)] + pub fn out_crc_clear_ch_iter(&self) -> impl Iterator { + (0..3).map(|n| unsafe { + &*(self as *const Self) + .cast::() + .add(708) + .add(40 * n) + .cast() + }) + } + #[doc = "0x2c8..0x2d4 - This register is used to store ch0 crc result"] + #[inline(always)] + pub const fn out_crc_final_result_ch(&self, n: usize) -> &OUT_CRC_FINAL_RESULT_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(712) + .add(40 * n) + .cast() + } + } + #[doc = "Iterator for array of:"] + #[doc = "0x2c8..0x2d4 - This register is used to store ch0 crc result"] + #[inline(always)] + pub fn out_crc_final_result_ch_iter(&self) -> impl Iterator { + (0..3).map(|n| unsafe { + &*(self as *const Self) + .cast::() + .add(712) + .add(40 * n) + .cast() + }) + } + #[doc = "0x2cc..0x2d8 - This resister is used to config ch0 crc en for every bit"] + #[inline(always)] + pub const fn tx_crc_en_wr_data_ch(&self, n: usize) -> &TX_CRC_EN_WR_DATA_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(716) + .add(40 * n) + .cast() + } + } + #[doc = "Iterator for array of:"] + #[doc = "0x2cc..0x2d8 - This resister is used to config ch0 crc en for every bit"] + #[inline(always)] + pub fn tx_crc_en_wr_data_ch_iter(&self) -> impl Iterator { + (0..3).map(|n| unsafe { + &*(self as *const Self) + .cast::() + .add(716) + .add(40 * n) + .cast() + }) + } + #[doc = "0x2d0..0x2dc - This register is used to config ch0 crc en addr"] + #[inline(always)] + pub const fn tx_crc_en_addr_ch(&self, n: usize) -> &TX_CRC_EN_ADDR_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(720) + .add(40 * n) + .cast() + } + } + #[doc = "Iterator for array of:"] + #[doc = "0x2d0..0x2dc - This register is used to config ch0 crc en addr"] + #[inline(always)] + pub fn tx_crc_en_addr_ch_iter(&self) -> impl Iterator { + (0..3).map(|n| unsafe { + &*(self as *const Self) + .cast::() + .add(720) + .add(40 * n) + .cast() + }) + } + #[doc = "0x2d4..0x2e0 - This register is used to config crc data_8bit en"] + #[inline(always)] + pub const fn tx_crc_data_en_wr_data_ch(&self, n: usize) -> &TX_CRC_DATA_EN_WR_DATA_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(724) + .add(40 * n) + .cast() + } + } + #[doc = "Iterator for array of:"] + #[doc = "0x2d4..0x2e0 - This register is used to config crc data_8bit en"] + #[inline(always)] + pub fn tx_crc_data_en_wr_data_ch_iter( + &self, + ) -> impl Iterator { + (0..3).map(|n| unsafe { + &*(self as *const Self) + .cast::() + .add(724) + .add(40 * n) + .cast() + }) + } + #[doc = "0x2d8..0x2e4 - This register is used to config addr of crc data_8bit en"] + #[inline(always)] + pub const fn tx_crc_data_en_addr_ch(&self, n: usize) -> &TX_CRC_DATA_EN_ADDR_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(728) + .add(40 * n) + .cast() + } + } + #[doc = "Iterator for array of:"] + #[doc = "0x2d8..0x2e4 - This register is used to config addr of crc data_8bit en"] + #[inline(always)] + pub fn tx_crc_data_en_addr_ch_iter(&self) -> impl Iterator { + (0..3).map(|n| unsafe { + &*(self as *const Self) + .cast::() + .add(728) + .add(40 * n) + .cast() + }) + } + #[doc = "0x2dc..0x2e8 - This register is used to config ch0 arbiter weigh"] + #[inline(always)] + pub const fn tx_ch_arb_weigh_ch(&self, n: usize) -> &TX_CH_ARB_WEIGH_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(732) + .add(40 * n) + .cast() + } + } + #[doc = "Iterator for array of:"] + #[doc = "0x2dc..0x2e8 - This register is used to config ch0 arbiter weigh"] + #[inline(always)] + pub fn tx_ch_arb_weigh_ch_iter(&self) -> impl Iterator { + (0..3).map(|n| unsafe { + &*(self as *const Self) + .cast::() + .add(732) + .add(40 * n) + .cast() + }) + } + #[doc = "0x2e0..0x2ec - This register is used to config off or on weigh optimization"] + #[inline(always)] + pub const fn tx_arb_weigh_opt_dir_ch(&self, n: usize) -> &TX_ARB_WEIGH_OPT_DIR_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(736) + .add(40 * n) + .cast() + } + } + #[doc = "Iterator for array of:"] + #[doc = "0x2e0..0x2ec - This register is used to config off or on weigh optimization"] + #[inline(always)] + pub fn tx_arb_weigh_opt_dir_ch_iter(&self) -> impl Iterator { + (0..3).map(|n| unsafe { + &*(self as *const Self) + .cast::() + .add(736) + .add(40 * n) + .cast() + }) + } + #[doc = "0x334..0x340 - This register is used to config ch0 crc initial data(max 32 bit)"] + #[inline(always)] + pub const fn in_crc_init_data_ch(&self, n: usize) -> &IN_CRC_INIT_DATA_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(820) + .add(40 * n) + .cast() + } + } + #[doc = "Iterator for array of:"] + #[doc = "0x334..0x340 - This register is used to config ch0 crc initial data(max 32 bit)"] + #[inline(always)] + pub fn in_crc_init_data_ch_iter(&self) -> impl Iterator { + (0..3).map(|n| unsafe { + &*(self as *const Self) + .cast::() + .add(820) + .add(40 * n) + .cast() + }) + } + #[doc = "0x338..0x344 - This register is used to confiig rx ch0 crc result width,2'b00 mean crc_width <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean 24<crc_width<=32"] + #[inline(always)] + pub const fn rx_crc_width_ch(&self, n: usize) -> &RX_CRC_WIDTH_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(824) + .add(40 * n) + .cast() + } + } + #[doc = "Iterator for array of:"] + #[doc = "0x338..0x344 - This register is used to confiig rx ch0 crc result width,2'b00 mean crc_width <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean 24<crc_width<=32"] + #[inline(always)] + pub fn rx_crc_width_ch_iter(&self) -> impl Iterator { + (0..3).map(|n| unsafe { + &*(self as *const Self) + .cast::() + .add(824) + .add(40 * n) + .cast() + }) + } + #[doc = "0x33c..0x348 - This register is used to clear ch0 crc result"] + #[inline(always)] + pub const fn in_crc_clear_ch(&self, n: usize) -> &IN_CRC_CLEAR_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(828) + .add(40 * n) + .cast() + } + } + #[doc = "Iterator for array of:"] + #[doc = "0x33c..0x348 - This register is used to clear ch0 crc result"] + #[inline(always)] + pub fn in_crc_clear_ch_iter(&self) -> impl Iterator { + (0..3).map(|n| unsafe { + &*(self as *const Self) + .cast::() + .add(828) + .add(40 * n) + .cast() + }) + } + #[doc = "0x340..0x34c - This register is used to store ch0 crc result"] + #[inline(always)] + pub const fn in_crc_final_result_ch(&self, n: usize) -> &IN_CRC_FINAL_RESULT_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(832) + .add(40 * n) + .cast() + } + } + #[doc = "Iterator for array of:"] + #[doc = "0x340..0x34c - This register is used to store ch0 crc result"] + #[inline(always)] + pub fn in_crc_final_result_ch_iter(&self) -> impl Iterator { + (0..3).map(|n| unsafe { + &*(self as *const Self) + .cast::() + .add(832) + .add(40 * n) + .cast() + }) + } + #[doc = "0x344..0x350 - This resister is used to config ch0 crc en for every bit"] + #[inline(always)] + pub const fn rx_crc_en_wr_data_ch(&self, n: usize) -> &RX_CRC_EN_WR_DATA_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(836) + .add(40 * n) + .cast() + } + } + #[doc = "Iterator for array of:"] + #[doc = "0x344..0x350 - This resister is used to config ch0 crc en for every bit"] + #[inline(always)] + pub fn rx_crc_en_wr_data_ch_iter(&self) -> impl Iterator { + (0..3).map(|n| unsafe { + &*(self as *const Self) + .cast::() + .add(836) + .add(40 * n) + .cast() + }) + } + #[doc = "0x348..0x354 - This register is used to config ch0 crc en addr"] + #[inline(always)] + pub const fn rx_crc_en_addr_ch(&self, n: usize) -> &RX_CRC_EN_ADDR_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(840) + .add(40 * n) + .cast() + } + } + #[doc = "Iterator for array of:"] + #[doc = "0x348..0x354 - This register is used to config ch0 crc en addr"] + #[inline(always)] + pub fn rx_crc_en_addr_ch_iter(&self) -> impl Iterator { + (0..3).map(|n| unsafe { + &*(self as *const Self) + .cast::() + .add(840) + .add(40 * n) + .cast() + }) + } + #[doc = "0x34c..0x358 - This register is used to config crc data_8bit en"] + #[inline(always)] + pub const fn rx_crc_data_en_wr_data_ch(&self, n: usize) -> &RX_CRC_DATA_EN_WR_DATA_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(844) + .add(40 * n) + .cast() + } + } + #[doc = "Iterator for array of:"] + #[doc = "0x34c..0x358 - This register is used to config crc data_8bit en"] + #[inline(always)] + pub fn rx_crc_data_en_wr_data_ch_iter( + &self, + ) -> impl Iterator { + (0..3).map(|n| unsafe { + &*(self as *const Self) + .cast::() + .add(844) + .add(40 * n) + .cast() + }) + } + #[doc = "0x350..0x35c - This register is used to config addr of crc data_8bit en"] + #[inline(always)] + pub const fn rx_crc_data_en_addr_ch(&self, n: usize) -> &RX_CRC_DATA_EN_ADDR_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(848) + .add(40 * n) + .cast() + } + } + #[doc = "Iterator for array of:"] + #[doc = "0x350..0x35c - This register is used to config addr of crc data_8bit en"] + #[inline(always)] + pub fn rx_crc_data_en_addr_ch_iter(&self) -> impl Iterator { + (0..3).map(|n| unsafe { + &*(self as *const Self) + .cast::() + .add(848) + .add(40 * n) + .cast() + }) + } + #[doc = "0x354..0x360 - This register is used to config ch0 arbiter weigh"] + #[inline(always)] + pub const fn rx_ch_arb_weigh_ch(&self, n: usize) -> &RX_CH_ARB_WEIGH_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(852) + .add(40 * n) + .cast() + } + } + #[doc = "Iterator for array of:"] + #[doc = "0x354..0x360 - This register is used to config ch0 arbiter weigh"] + #[inline(always)] + pub fn rx_ch_arb_weigh_ch_iter(&self) -> impl Iterator { + (0..3).map(|n| unsafe { + &*(self as *const Self) + .cast::() + .add(852) + .add(40 * n) + .cast() + }) + } + #[doc = "0x358..0x364 - This register is used to config off or on weigh optimization"] + #[inline(always)] + pub const fn rx_arb_weigh_opt_dir_ch(&self, n: usize) -> &RX_ARB_WEIGH_OPT_DIR_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(856) + .add(40 * n) + .cast() + } + } + #[doc = "Iterator for array of:"] + #[doc = "0x358..0x364 - This register is used to config off or on weigh optimization"] + #[inline(always)] + pub fn rx_arb_weigh_opt_dir_ch_iter(&self) -> impl Iterator { + (0..3).map(|n| unsafe { + &*(self as *const Self) + .cast::() + .add(856) + .add(40 * n) + .cast() + }) + } + #[doc = "0x3ac..0x3b8 - Link descriptor configure of Rx channel 0"] + #[inline(always)] + pub const fn in_link_addr_ch(&self, n: usize) -> &IN_LINK_ADDR_CH { + &self.in_link_addr_ch[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x3ac..0x3b8 - Link descriptor configure of Rx channel 0"] + #[inline(always)] + pub fn in_link_addr_ch_iter(&self) -> impl Iterator { + self.in_link_addr_ch.iter() + } + #[doc = "0x3b8..0x3c4 - Link descriptor configure of Tx channel 0"] + #[inline(always)] + pub const fn out_link_addr_ch(&self, n: usize) -> &OUT_LINK_ADDR_CH { + &self.out_link_addr_ch[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x3b8..0x3c4 - Link descriptor configure of Tx channel 0"] + #[inline(always)] + pub fn out_link_addr_ch_iter(&self) -> impl Iterator { + self.out_link_addr_ch.iter() + } + #[doc = "0x3c4 - The start address of accessible address space."] + #[inline(always)] + pub const fn intr_mem_start_addr(&self) -> &INTR_MEM_START_ADDR { + &self.intr_mem_start_addr + } + #[doc = "0x3c8 - The end address of accessible address space. The access address beyond this range would lead to descriptor error."] + #[inline(always)] + pub const fn intr_mem_end_addr(&self) -> &INTR_MEM_END_ADDR { + &self.intr_mem_end_addr + } + #[doc = "0x3cc - This retister is used to config arbiter time slice for tx dir"] + #[inline(always)] + pub const fn arb_timeout_tx(&self) -> &ARB_TIMEOUT_TX { + &self.arb_timeout_tx + } + #[doc = "0x3d0 - This retister is used to config arbiter time slice for rx dir"] + #[inline(always)] + pub const fn arb_timeout_rx(&self) -> &ARB_TIMEOUT_RX { + &self.arb_timeout_rx + } + #[doc = "0x3d4 - This register is used to config arbiter weigh function to on or off for tx dir"] + #[inline(always)] + pub const fn weight_en_tx(&self) -> &WEIGHT_EN_TX { + &self.weight_en_tx + } + #[doc = "0x3d8 - This register is used to config arbiter weigh function to on or off for rx dir"] + #[inline(always)] + pub const fn weight_en_rx(&self) -> &WEIGHT_EN_RX { + &self.weight_en_rx + } +} +#[doc = "IN_INT_RAW_CH (rw) register accessor: Raw status interrupt of channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_int_raw_ch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_int_raw_ch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_int_raw_ch`] module"] +pub type IN_INT_RAW_CH = crate::Reg; +#[doc = "Raw status interrupt of channel 0"] +pub mod in_int_raw_ch; +#[doc = "IN_INT_ST_CH (r) register accessor: Masked interrupt of channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_int_st_ch::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_int_st_ch`] module"] +pub type IN_INT_ST_CH = crate::Reg; +#[doc = "Masked interrupt of channel 0"] +pub mod in_int_st_ch; +#[doc = "IN_INT_ENA_CH (rw) register accessor: Interrupt enable bits of channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_int_ena_ch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_int_ena_ch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_int_ena_ch`] module"] +pub type IN_INT_ENA_CH = crate::Reg; +#[doc = "Interrupt enable bits of channel 0"] +pub mod in_int_ena_ch; +#[doc = "IN_INT_CLR_CH (w) register accessor: Interrupt clear bits of channel 0\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_int_clr_ch::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_int_clr_ch`] module"] +pub type IN_INT_CLR_CH = crate::Reg; +#[doc = "Interrupt clear bits of channel 0"] +pub mod in_int_clr_ch; +#[doc = "OUT_INT_RAW_CH (rw) register accessor: Raw status interrupt of channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_int_raw_ch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_int_raw_ch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_int_raw_ch`] module"] +pub type OUT_INT_RAW_CH = crate::Reg; +#[doc = "Raw status interrupt of channel 0"] +pub mod out_int_raw_ch; +#[doc = "OUT_INT_ST_CH (r) register accessor: Masked interrupt of channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_int_st_ch::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_int_st_ch`] module"] +pub type OUT_INT_ST_CH = crate::Reg; +#[doc = "Masked interrupt of channel 0"] +pub mod out_int_st_ch; +#[doc = "OUT_INT_ENA_CH (rw) register accessor: Interrupt enable bits of channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_int_ena_ch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_int_ena_ch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_int_ena_ch`] module"] +pub type OUT_INT_ENA_CH = crate::Reg; +#[doc = "Interrupt enable bits of channel 0"] +pub mod out_int_ena_ch; +#[doc = "OUT_INT_CLR_CH (w) register accessor: Interrupt clear bits of channel 0\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_int_clr_ch::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_int_clr_ch`] module"] +pub type OUT_INT_CLR_CH = crate::Reg; +#[doc = "Interrupt clear bits of channel 0"] +pub mod out_int_clr_ch; +#[doc = "AHB_TEST (rw) register accessor: reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ahb_test::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ahb_test::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ahb_test`] module"] +pub type AHB_TEST = crate::Reg; +#[doc = "reserved"] +pub mod ahb_test; +#[doc = "MISC_CONF (rw) register accessor: MISC register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`misc_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`misc_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@misc_conf`] module"] +pub type MISC_CONF = crate::Reg; +#[doc = "MISC register"] +pub mod misc_conf; +#[doc = "DATE (rw) register accessor: Version control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@date`] module"] +pub type DATE = crate::Reg; +#[doc = "Version control register"] +pub mod date; +#[doc = "IN_CONF0_CH (rw) register accessor: Configure 0 register of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_conf0_ch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_conf0_ch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_conf0_ch`] module"] +pub type IN_CONF0_CH = crate::Reg; +#[doc = "Configure 0 register of Rx channel 0"] +pub mod in_conf0_ch; +#[doc = "IN_CONF1_CH (rw) register accessor: Configure 1 register of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_conf1_ch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_conf1_ch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_conf1_ch`] module"] +pub type IN_CONF1_CH = crate::Reg; +#[doc = "Configure 1 register of Rx channel 0"] +pub mod in_conf1_ch; +#[doc = "INFIFO_STATUS_CH (r) register accessor: Receive FIFO status of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`infifo_status_ch::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@infifo_status_ch`] module"] +pub type INFIFO_STATUS_CH = crate::Reg; +#[doc = "Receive FIFO status of Rx channel 0"] +pub mod infifo_status_ch; +#[doc = "IN_POP_CH (rw) register accessor: Pop control register of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_pop_ch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_pop_ch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_pop_ch`] module"] +pub type IN_POP_CH = crate::Reg; +#[doc = "Pop control register of Rx channel 0"] +pub mod in_pop_ch; +#[doc = "IN_LINK_CH (rw) register accessor: Link descriptor configure and control register of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_link_ch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_link_ch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_link_ch`] module"] +pub type IN_LINK_CH = crate::Reg; +#[doc = "Link descriptor configure and control register of Rx channel 0"] +pub mod in_link_ch; +#[doc = "IN_STATE_CH (r) register accessor: Receive status of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_state_ch::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_state_ch`] module"] +pub type IN_STATE_CH = crate::Reg; +#[doc = "Receive status of Rx channel 0"] +pub mod in_state_ch; +#[doc = "IN_SUC_EOF_DES_ADDR_CH (r) register accessor: Inlink descriptor address when EOF occurs of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_suc_eof_des_addr_ch::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_suc_eof_des_addr_ch`] module"] +pub type IN_SUC_EOF_DES_ADDR_CH = crate::Reg; +#[doc = "Inlink descriptor address when EOF occurs of Rx channel 0"] +pub mod in_suc_eof_des_addr_ch; +#[doc = "IN_ERR_EOF_DES_ADDR_CH (r) register accessor: Inlink descriptor address when errors occur of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_err_eof_des_addr_ch::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_err_eof_des_addr_ch`] module"] +pub type IN_ERR_EOF_DES_ADDR_CH = crate::Reg; +#[doc = "Inlink descriptor address when errors occur of Rx channel 0"] +pub mod in_err_eof_des_addr_ch; +#[doc = "IN_DSCR_CH (r) register accessor: Current inlink descriptor address of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_dscr_ch::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_dscr_ch`] module"] +pub type IN_DSCR_CH = crate::Reg; +#[doc = "Current inlink descriptor address of Rx channel 0"] +pub mod in_dscr_ch; +#[doc = "IN_DSCR_BF0_CH (r) register accessor: The last inlink descriptor address of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_dscr_bf0_ch::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_dscr_bf0_ch`] module"] +pub type IN_DSCR_BF0_CH = crate::Reg; +#[doc = "The last inlink descriptor address of Rx channel 0"] +pub mod in_dscr_bf0_ch; +#[doc = "IN_DSCR_BF1_CH (r) register accessor: The second-to-last inlink descriptor address of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_dscr_bf1_ch::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_dscr_bf1_ch`] module"] +pub type IN_DSCR_BF1_CH = crate::Reg; +#[doc = "The second-to-last inlink descriptor address of Rx channel 0"] +pub mod in_dscr_bf1_ch; +#[doc = "IN_PRI_CH (rw) register accessor: Priority register of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_pri_ch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_pri_ch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_pri_ch`] module"] +pub type IN_PRI_CH = crate::Reg; +#[doc = "Priority register of Rx channel 0"] +pub mod in_pri_ch; +#[doc = "IN_PERI_SEL_CH (rw) register accessor: Peripheral selection of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_peri_sel_ch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_peri_sel_ch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_peri_sel_ch`] module"] +pub type IN_PERI_SEL_CH = crate::Reg; +#[doc = "Peripheral selection of Rx channel 0"] +pub mod in_peri_sel_ch; +#[doc = "OUT_CONF0_CH0 (rw) register accessor: Configure 0 register of Tx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_conf0_ch0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_conf0_ch0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_conf0_ch0`] module"] +pub type OUT_CONF0_CH0 = crate::Reg; +#[doc = "Configure 0 register of Tx channel 0"] +pub mod out_conf0_ch0; +#[doc = "OUT_CONF1_CH (rw) register accessor: Configure 1 register of Tx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_conf1_ch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_conf1_ch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_conf1_ch`] module"] +pub type OUT_CONF1_CH = crate::Reg; +#[doc = "Configure 1 register of Tx channel 0"] +pub mod out_conf1_ch; +#[doc = "OUTFIFO_STATUS_CH (r) register accessor: Transmit FIFO status of Tx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`outfifo_status_ch::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@outfifo_status_ch`] module"] +pub type OUTFIFO_STATUS_CH = crate::Reg; +#[doc = "Transmit FIFO status of Tx channel 0"] +pub mod outfifo_status_ch; +#[doc = "OUT_PUSH_CH (rw) register accessor: Push control register of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_push_ch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_push_ch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_push_ch`] module"] +pub type OUT_PUSH_CH = crate::Reg; +#[doc = "Push control register of Rx channel 0"] +pub mod out_push_ch; +#[doc = "OUT_LINK_CH (rw) register accessor: Link descriptor configure and control register of Tx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_link_ch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_link_ch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_link_ch`] module"] +pub type OUT_LINK_CH = crate::Reg; +#[doc = "Link descriptor configure and control register of Tx channel 0"] +pub mod out_link_ch; +#[doc = "OUT_STATE_CH (r) register accessor: Transmit status of Tx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_state_ch::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_state_ch`] module"] +pub type OUT_STATE_CH = crate::Reg; +#[doc = "Transmit status of Tx channel 0"] +pub mod out_state_ch; +#[doc = "OUT_EOF_DES_ADDR_CH (r) register accessor: Outlink descriptor address when EOF occurs of Tx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_eof_des_addr_ch::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_eof_des_addr_ch`] module"] +pub type OUT_EOF_DES_ADDR_CH = crate::Reg; +#[doc = "Outlink descriptor address when EOF occurs of Tx channel 0"] +pub mod out_eof_des_addr_ch; +#[doc = "OUT_EOF_BFR_DES_ADDR_CH (r) register accessor: The last outlink descriptor address when EOF occurs of Tx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_eof_bfr_des_addr_ch::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_eof_bfr_des_addr_ch`] module"] +pub type OUT_EOF_BFR_DES_ADDR_CH = + crate::Reg; +#[doc = "The last outlink descriptor address when EOF occurs of Tx channel 0"] +pub mod out_eof_bfr_des_addr_ch; +#[doc = "OUT_DSCR_CH (r) register accessor: Current inlink descriptor address of Tx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_dscr_ch::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_dscr_ch`] module"] +pub type OUT_DSCR_CH = crate::Reg; +#[doc = "Current inlink descriptor address of Tx channel 0"] +pub mod out_dscr_ch; +#[doc = "OUT_DSCR_BF0_CH (r) register accessor: The last inlink descriptor address of Tx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_dscr_bf0_ch::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_dscr_bf0_ch`] module"] +pub type OUT_DSCR_BF0_CH = crate::Reg; +#[doc = "The last inlink descriptor address of Tx channel 0"] +pub mod out_dscr_bf0_ch; +#[doc = "OUT_DSCR_BF1_CH (r) register accessor: The second-to-last inlink descriptor address of Tx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_dscr_bf1_ch::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_dscr_bf1_ch`] module"] +pub type OUT_DSCR_BF1_CH = crate::Reg; +#[doc = "The second-to-last inlink descriptor address of Tx channel 0"] +pub mod out_dscr_bf1_ch; +#[doc = "OUT_PRI_CH (rw) register accessor: Priority register of Tx channel 0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_pri_ch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_pri_ch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_pri_ch`] module"] +pub type OUT_PRI_CH = crate::Reg; +#[doc = "Priority register of Tx channel 0."] +pub mod out_pri_ch; +#[doc = "OUT_PERI_SEL_CH (rw) register accessor: Peripheral selection of Tx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_peri_sel_ch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_peri_sel_ch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_peri_sel_ch`] module"] +pub type OUT_PERI_SEL_CH = crate::Reg; +#[doc = "Peripheral selection of Tx channel 0"] +pub mod out_peri_sel_ch; +#[doc = "OUT_CONF0_CH (rw) register accessor: Configure 0 register of Tx channel 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_conf0_ch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_conf0_ch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_conf0_ch`] module"] +pub type OUT_CONF0_CH = crate::Reg; +#[doc = "Configure 0 register of Tx channel 1"] +pub mod out_conf0_ch; +#[doc = "OUT_CRC_INIT_DATA_CH (rw) register accessor: This register is used to config ch0 crc initial data(max 32 bit)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_crc_init_data_ch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_crc_init_data_ch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_crc_init_data_ch`] module"] +pub type OUT_CRC_INIT_DATA_CH = crate::Reg; +#[doc = "This register is used to config ch0 crc initial data(max 32 bit)"] +pub mod out_crc_init_data_ch; +#[doc = "TX_CRC_WIDTH_CH (rw) register accessor: This register is used to confiig tx ch0 crc result width,2'b00 mean crc_width <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean 24<crc_width<=32\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_crc_width_ch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_crc_width_ch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_crc_width_ch`] module"] +pub type TX_CRC_WIDTH_CH = crate::Reg; +#[doc = "This register is used to confiig tx ch0 crc result width,2'b00 mean crc_width <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean 24<crc_width<=32"] +pub mod tx_crc_width_ch; +#[doc = "OUT_CRC_CLEAR_CH (rw) register accessor: This register is used to clear ch0 crc result\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_crc_clear_ch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_crc_clear_ch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_crc_clear_ch`] module"] +pub type OUT_CRC_CLEAR_CH = crate::Reg; +#[doc = "This register is used to clear ch0 crc result"] +pub mod out_crc_clear_ch; +#[doc = "OUT_CRC_FINAL_RESULT_CH (r) register accessor: This register is used to store ch0 crc result\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_crc_final_result_ch::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_crc_final_result_ch`] module"] +pub type OUT_CRC_FINAL_RESULT_CH = + crate::Reg; +#[doc = "This register is used to store ch0 crc result"] +pub mod out_crc_final_result_ch; +#[doc = "TX_CRC_EN_WR_DATA_CH (rw) register accessor: This resister is used to config ch0 crc en for every bit\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_crc_en_wr_data_ch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_crc_en_wr_data_ch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_crc_en_wr_data_ch`] module"] +pub type TX_CRC_EN_WR_DATA_CH = crate::Reg; +#[doc = "This resister is used to config ch0 crc en for every bit"] +pub mod tx_crc_en_wr_data_ch; +#[doc = "TX_CRC_EN_ADDR_CH (rw) register accessor: This register is used to config ch0 crc en addr\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_crc_en_addr_ch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_crc_en_addr_ch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_crc_en_addr_ch`] module"] +pub type TX_CRC_EN_ADDR_CH = crate::Reg; +#[doc = "This register is used to config ch0 crc en addr"] +pub mod tx_crc_en_addr_ch; +#[doc = "TX_CRC_DATA_EN_WR_DATA_CH (rw) register accessor: This register is used to config crc data_8bit en\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_crc_data_en_wr_data_ch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_crc_data_en_wr_data_ch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_crc_data_en_wr_data_ch`] module"] +pub type TX_CRC_DATA_EN_WR_DATA_CH = + crate::Reg; +#[doc = "This register is used to config crc data_8bit en"] +pub mod tx_crc_data_en_wr_data_ch; +#[doc = "TX_CRC_DATA_EN_ADDR_CH (rw) register accessor: This register is used to config addr of crc data_8bit en\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_crc_data_en_addr_ch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_crc_data_en_addr_ch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_crc_data_en_addr_ch`] module"] +pub type TX_CRC_DATA_EN_ADDR_CH = crate::Reg; +#[doc = "This register is used to config addr of crc data_8bit en"] +pub mod tx_crc_data_en_addr_ch; +#[doc = "TX_CH_ARB_WEIGH_CH (rw) register accessor: This register is used to config ch0 arbiter weigh\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_ch_arb_weigh_ch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_ch_arb_weigh_ch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_ch_arb_weigh_ch`] module"] +pub type TX_CH_ARB_WEIGH_CH = crate::Reg; +#[doc = "This register is used to config ch0 arbiter weigh"] +pub mod tx_ch_arb_weigh_ch; +#[doc = "TX_ARB_WEIGH_OPT_DIR_CH (rw) register accessor: This register is used to config off or on weigh optimization\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_arb_weigh_opt_dir_ch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_arb_weigh_opt_dir_ch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_arb_weigh_opt_dir_ch`] module"] +pub type TX_ARB_WEIGH_OPT_DIR_CH = + crate::Reg; +#[doc = "This register is used to config off or on weigh optimization"] +pub mod tx_arb_weigh_opt_dir_ch; +#[doc = "IN_CRC_INIT_DATA_CH (rw) register accessor: This register is used to config ch0 crc initial data(max 32 bit)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_crc_init_data_ch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_crc_init_data_ch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_crc_init_data_ch`] module"] +pub type IN_CRC_INIT_DATA_CH = crate::Reg; +#[doc = "This register is used to config ch0 crc initial data(max 32 bit)"] +pub mod in_crc_init_data_ch; +#[doc = "RX_CRC_WIDTH_CH (rw) register accessor: This register is used to confiig rx ch0 crc result width,2'b00 mean crc_width <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean 24<crc_width<=32\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_crc_width_ch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_crc_width_ch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_crc_width_ch`] module"] +pub type RX_CRC_WIDTH_CH = crate::Reg; +#[doc = "This register is used to confiig rx ch0 crc result width,2'b00 mean crc_width <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean 24<crc_width<=32"] +pub mod rx_crc_width_ch; +#[doc = "IN_CRC_CLEAR_CH (rw) register accessor: This register is used to clear ch0 crc result\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_crc_clear_ch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_crc_clear_ch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_crc_clear_ch`] module"] +pub type IN_CRC_CLEAR_CH = crate::Reg; +#[doc = "This register is used to clear ch0 crc result"] +pub mod in_crc_clear_ch; +#[doc = "IN_CRC_FINAL_RESULT_CH (r) register accessor: This register is used to store ch0 crc result\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_crc_final_result_ch::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_crc_final_result_ch`] module"] +pub type IN_CRC_FINAL_RESULT_CH = crate::Reg; +#[doc = "This register is used to store ch0 crc result"] +pub mod in_crc_final_result_ch; +#[doc = "RX_CRC_EN_WR_DATA_CH (rw) register accessor: This resister is used to config ch0 crc en for every bit\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_crc_en_wr_data_ch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_crc_en_wr_data_ch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_crc_en_wr_data_ch`] module"] +pub type RX_CRC_EN_WR_DATA_CH = crate::Reg; +#[doc = "This resister is used to config ch0 crc en for every bit"] +pub mod rx_crc_en_wr_data_ch; +#[doc = "RX_CRC_EN_ADDR_CH (rw) register accessor: This register is used to config ch0 crc en addr\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_crc_en_addr_ch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_crc_en_addr_ch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_crc_en_addr_ch`] module"] +pub type RX_CRC_EN_ADDR_CH = crate::Reg; +#[doc = "This register is used to config ch0 crc en addr"] +pub mod rx_crc_en_addr_ch; +#[doc = "RX_CRC_DATA_EN_WR_DATA_CH (rw) register accessor: This register is used to config crc data_8bit en\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_crc_data_en_wr_data_ch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_crc_data_en_wr_data_ch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_crc_data_en_wr_data_ch`] module"] +pub type RX_CRC_DATA_EN_WR_DATA_CH = + crate::Reg; +#[doc = "This register is used to config crc data_8bit en"] +pub mod rx_crc_data_en_wr_data_ch; +#[doc = "RX_CRC_DATA_EN_ADDR_CH (rw) register accessor: This register is used to config addr of crc data_8bit en\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_crc_data_en_addr_ch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_crc_data_en_addr_ch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_crc_data_en_addr_ch`] module"] +pub type RX_CRC_DATA_EN_ADDR_CH = crate::Reg; +#[doc = "This register is used to config addr of crc data_8bit en"] +pub mod rx_crc_data_en_addr_ch; +#[doc = "RX_CH_ARB_WEIGH_CH (rw) register accessor: This register is used to config ch0 arbiter weigh\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_ch_arb_weigh_ch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_ch_arb_weigh_ch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_ch_arb_weigh_ch`] module"] +pub type RX_CH_ARB_WEIGH_CH = crate::Reg; +#[doc = "This register is used to config ch0 arbiter weigh"] +pub mod rx_ch_arb_weigh_ch; +#[doc = "RX_ARB_WEIGH_OPT_DIR_CH (rw) register accessor: This register is used to config off or on weigh optimization\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_arb_weigh_opt_dir_ch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_arb_weigh_opt_dir_ch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_arb_weigh_opt_dir_ch`] module"] +pub type RX_ARB_WEIGH_OPT_DIR_CH = + crate::Reg; +#[doc = "This register is used to config off or on weigh optimization"] +pub mod rx_arb_weigh_opt_dir_ch; +#[doc = "IN_LINK_ADDR_CH (rw) register accessor: Link descriptor configure of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_link_addr_ch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_link_addr_ch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_link_addr_ch`] module"] +pub type IN_LINK_ADDR_CH = crate::Reg; +#[doc = "Link descriptor configure of Rx channel 0"] +pub mod in_link_addr_ch; +#[doc = "OUT_LINK_ADDR_CH (rw) register accessor: Link descriptor configure of Tx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_link_addr_ch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_link_addr_ch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_link_addr_ch`] module"] +pub type OUT_LINK_ADDR_CH = crate::Reg; +#[doc = "Link descriptor configure of Tx channel 0"] +pub mod out_link_addr_ch; +#[doc = "INTR_MEM_START_ADDR (rw) register accessor: The start address of accessible address space.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_mem_start_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr_mem_start_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_mem_start_addr`] module"] +pub type INTR_MEM_START_ADDR = crate::Reg; +#[doc = "The start address of accessible address space."] +pub mod intr_mem_start_addr; +#[doc = "INTR_MEM_END_ADDR (rw) register accessor: The end address of accessible address space. The access address beyond this range would lead to descriptor error.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_mem_end_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr_mem_end_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_mem_end_addr`] module"] +pub type INTR_MEM_END_ADDR = crate::Reg; +#[doc = "The end address of accessible address space. The access address beyond this range would lead to descriptor error."] +pub mod intr_mem_end_addr; +#[doc = "ARB_TIMEOUT_TX (rw) register accessor: This retister is used to config arbiter time slice for tx dir\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`arb_timeout_tx::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`arb_timeout_tx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@arb_timeout_tx`] module"] +pub type ARB_TIMEOUT_TX = crate::Reg; +#[doc = "This retister is used to config arbiter time slice for tx dir"] +pub mod arb_timeout_tx; +#[doc = "ARB_TIMEOUT_RX (rw) register accessor: This retister is used to config arbiter time slice for rx dir\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`arb_timeout_rx::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`arb_timeout_rx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@arb_timeout_rx`] module"] +pub type ARB_TIMEOUT_RX = crate::Reg; +#[doc = "This retister is used to config arbiter time slice for rx dir"] +pub mod arb_timeout_rx; +#[doc = "WEIGHT_EN_TX (rw) register accessor: This register is used to config arbiter weigh function to on or off for tx dir\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`weight_en_tx::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`weight_en_tx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@weight_en_tx`] module"] +pub type WEIGHT_EN_TX = crate::Reg; +#[doc = "This register is used to config arbiter weigh function to on or off for tx dir"] +pub mod weight_en_tx; +#[doc = "WEIGHT_EN_RX (rw) register accessor: This register is used to config arbiter weigh function to on or off for rx dir\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`weight_en_rx::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`weight_en_rx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@weight_en_rx`] module"] +pub type WEIGHT_EN_RX = crate::Reg; +#[doc = "This register is used to config arbiter weigh function to on or off for rx dir"] +pub mod weight_en_rx; diff --git a/esp32p4/src/ahb_dma/ahb_test.rs b/esp32p4/src/ahb_dma/ahb_test.rs new file mode 100644 index 0000000000..0d0b7775b0 --- /dev/null +++ b/esp32p4/src/ahb_dma/ahb_test.rs @@ -0,0 +1,85 @@ +#[doc = "Register `AHB_TEST` reader"] +pub type R = crate::R; +#[doc = "Register `AHB_TEST` writer"] +pub type W = crate::W; +#[doc = "Field `AHB_TESTMODE` reader - reserved"] +pub type AHB_TESTMODE_R = crate::FieldReader; +#[doc = "Field `AHB_TESTMODE` writer - reserved"] +pub type AHB_TESTMODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `AHB_TESTADDR` reader - reserved"] +pub type AHB_TESTADDR_R = crate::FieldReader; +#[doc = "Field `AHB_TESTADDR` writer - reserved"] +pub type AHB_TESTADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:2 - reserved"] + #[inline(always)] + pub fn ahb_testmode(&self) -> AHB_TESTMODE_R { + AHB_TESTMODE_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 4:5 - reserved"] + #[inline(always)] + pub fn ahb_testaddr(&self) -> AHB_TESTADDR_R { + AHB_TESTADDR_R::new(((self.bits >> 4) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AHB_TEST") + .field( + "ahb_testmode", + &format_args!("{}", self.ahb_testmode().bits()), + ) + .field( + "ahb_testaddr", + &format_args!("{}", self.ahb_testaddr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:2 - reserved"] + #[inline(always)] + #[must_use] + pub fn ahb_testmode(&mut self) -> AHB_TESTMODE_W { + AHB_TESTMODE_W::new(self, 0) + } + #[doc = "Bits 4:5 - reserved"] + #[inline(always)] + #[must_use] + pub fn ahb_testaddr(&mut self) -> AHB_TESTADDR_W { + AHB_TESTADDR_W::new(self, 4) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ahb_test::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ahb_test::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AHB_TEST_SPEC; +impl crate::RegisterSpec for AHB_TEST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ahb_test::R`](R) reader structure"] +impl crate::Readable for AHB_TEST_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ahb_test::W`](W) writer structure"] +impl crate::Writable for AHB_TEST_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets AHB_TEST to value 0"] +impl crate::Resettable for AHB_TEST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ahb_dma/arb_timeout_rx.rs b/esp32p4/src/ahb_dma/arb_timeout_rx.rs new file mode 100644 index 0000000000..b0be591a99 --- /dev/null +++ b/esp32p4/src/ahb_dma/arb_timeout_rx.rs @@ -0,0 +1,66 @@ +#[doc = "Register `ARB_TIMEOUT_RX` reader"] +pub type R = crate::R; +#[doc = "Register `ARB_TIMEOUT_RX` writer"] +pub type W = crate::W; +#[doc = "Field `ARB_TIMEOUT_RX` reader - This register is used to config arbiter time out value"] +pub type ARB_TIMEOUT_RX_R = crate::FieldReader; +#[doc = "Field `ARB_TIMEOUT_RX` writer - This register is used to config arbiter time out value"] +pub type ARB_TIMEOUT_RX_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - This register is used to config arbiter time out value"] + #[inline(always)] + pub fn arb_timeout_rx(&self) -> ARB_TIMEOUT_RX_R { + ARB_TIMEOUT_RX_R::new((self.bits & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ARB_TIMEOUT_RX") + .field( + "arb_timeout_rx", + &format_args!("{}", self.arb_timeout_rx().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - This register is used to config arbiter time out value"] + #[inline(always)] + #[must_use] + pub fn arb_timeout_rx(&mut self) -> ARB_TIMEOUT_RX_W { + ARB_TIMEOUT_RX_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "This retister is used to config arbiter time slice for rx dir\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`arb_timeout_rx::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`arb_timeout_rx::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ARB_TIMEOUT_RX_SPEC; +impl crate::RegisterSpec for ARB_TIMEOUT_RX_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`arb_timeout_rx::R`](R) reader structure"] +impl crate::Readable for ARB_TIMEOUT_RX_SPEC {} +#[doc = "`write(|w| ..)` method takes [`arb_timeout_rx::W`](W) writer structure"] +impl crate::Writable for ARB_TIMEOUT_RX_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ARB_TIMEOUT_RX to value 0"] +impl crate::Resettable for ARB_TIMEOUT_RX_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ahb_dma/arb_timeout_tx.rs b/esp32p4/src/ahb_dma/arb_timeout_tx.rs new file mode 100644 index 0000000000..c463070478 --- /dev/null +++ b/esp32p4/src/ahb_dma/arb_timeout_tx.rs @@ -0,0 +1,66 @@ +#[doc = "Register `ARB_TIMEOUT_TX` reader"] +pub type R = crate::R; +#[doc = "Register `ARB_TIMEOUT_TX` writer"] +pub type W = crate::W; +#[doc = "Field `ARB_TIMEOUT_TX` reader - This register is used to config arbiter time out value"] +pub type ARB_TIMEOUT_TX_R = crate::FieldReader; +#[doc = "Field `ARB_TIMEOUT_TX` writer - This register is used to config arbiter time out value"] +pub type ARB_TIMEOUT_TX_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - This register is used to config arbiter time out value"] + #[inline(always)] + pub fn arb_timeout_tx(&self) -> ARB_TIMEOUT_TX_R { + ARB_TIMEOUT_TX_R::new((self.bits & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ARB_TIMEOUT_TX") + .field( + "arb_timeout_tx", + &format_args!("{}", self.arb_timeout_tx().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - This register is used to config arbiter time out value"] + #[inline(always)] + #[must_use] + pub fn arb_timeout_tx(&mut self) -> ARB_TIMEOUT_TX_W { + ARB_TIMEOUT_TX_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "This retister is used to config arbiter time slice for tx dir\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`arb_timeout_tx::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`arb_timeout_tx::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ARB_TIMEOUT_TX_SPEC; +impl crate::RegisterSpec for ARB_TIMEOUT_TX_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`arb_timeout_tx::R`](R) reader structure"] +impl crate::Readable for ARB_TIMEOUT_TX_SPEC {} +#[doc = "`write(|w| ..)` method takes [`arb_timeout_tx::W`](W) writer structure"] +impl crate::Writable for ARB_TIMEOUT_TX_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ARB_TIMEOUT_TX to value 0"] +impl crate::Resettable for ARB_TIMEOUT_TX_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ahb_dma/date.rs b/esp32p4/src/ahb_dma/date.rs new file mode 100644 index 0000000000..f49507d763 --- /dev/null +++ b/esp32p4/src/ahb_dma/date.rs @@ -0,0 +1,63 @@ +#[doc = "Register `DATE` reader"] +pub type R = crate::R; +#[doc = "Register `DATE` writer"] +pub type W = crate::W; +#[doc = "Field `DATE` reader - register version."] +pub type DATE_R = crate::FieldReader; +#[doc = "Field `DATE` writer - register version."] +pub type DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - register version."] + #[inline(always)] + pub fn date(&self) -> DATE_R { + DATE_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DATE") + .field("date", &format_args!("{}", self.date().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - register version."] + #[inline(always)] + #[must_use] + pub fn date(&mut self) -> DATE_W { + DATE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Version control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DATE_SPEC; +impl crate::RegisterSpec for DATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`date::R`](R) reader structure"] +impl crate::Readable for DATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`date::W`](W) writer structure"] +impl crate::Writable for DATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DATE to value 0x0230_3140"] +impl crate::Resettable for DATE_SPEC { + const RESET_VALUE: Self::Ux = 0x0230_3140; +} diff --git a/esp32p4/src/ahb_dma/in_conf0_ch.rs b/esp32p4/src/ahb_dma/in_conf0_ch.rs new file mode 100644 index 0000000000..f0fd6169d5 --- /dev/null +++ b/esp32p4/src/ahb_dma/in_conf0_ch.rs @@ -0,0 +1,158 @@ +#[doc = "Register `IN_CONF0_CH%s` reader"] +pub type R = crate::R; +#[doc = "Register `IN_CONF0_CH%s` writer"] +pub type W = crate::W; +#[doc = "Field `IN_RST_CH` reader - This bit is used to reset AHB_DMA channel 0 Rx FSM and Rx FIFO pointer."] +pub type IN_RST_CH_R = crate::BitReader; +#[doc = "Field `IN_RST_CH` writer - This bit is used to reset AHB_DMA channel 0 Rx FSM and Rx FIFO pointer."] +pub type IN_RST_CH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_LOOP_TEST_CH` reader - reserved"] +pub type IN_LOOP_TEST_CH_R = crate::BitReader; +#[doc = "Field `IN_LOOP_TEST_CH` writer - reserved"] +pub type IN_LOOP_TEST_CH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INDSCR_BURST_EN_CH` reader - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM."] +pub type INDSCR_BURST_EN_CH_R = crate::BitReader; +#[doc = "Field `INDSCR_BURST_EN_CH` writer - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM."] +pub type INDSCR_BURST_EN_CH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_DATA_BURST_EN_CH` reader - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM."] +pub type IN_DATA_BURST_EN_CH_R = crate::BitReader; +#[doc = "Field `IN_DATA_BURST_EN_CH` writer - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM."] +pub type IN_DATA_BURST_EN_CH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MEM_TRANS_EN_CH` reader - Set this bit 1 to enable automatic transmitting data from memory to memory via AHB_DMA."] +pub type MEM_TRANS_EN_CH_R = crate::BitReader; +#[doc = "Field `MEM_TRANS_EN_CH` writer - Set this bit 1 to enable automatic transmitting data from memory to memory via AHB_DMA."] +pub type MEM_TRANS_EN_CH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_ETM_EN_CH` reader - Set this bit to 1 to enable etm control mode, dma Rx channel 0 is triggered by etm task."] +pub type IN_ETM_EN_CH_R = crate::BitReader; +#[doc = "Field `IN_ETM_EN_CH` writer - Set this bit to 1 to enable etm control mode, dma Rx channel 0 is triggered by etm task."] +pub type IN_ETM_EN_CH_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - This bit is used to reset AHB_DMA channel 0 Rx FSM and Rx FIFO pointer."] + #[inline(always)] + pub fn in_rst_ch(&self) -> IN_RST_CH_R { + IN_RST_CH_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - reserved"] + #[inline(always)] + pub fn in_loop_test_ch(&self) -> IN_LOOP_TEST_CH_R { + IN_LOOP_TEST_CH_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM."] + #[inline(always)] + pub fn indscr_burst_en_ch(&self) -> INDSCR_BURST_EN_CH_R { + INDSCR_BURST_EN_CH_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM."] + #[inline(always)] + pub fn in_data_burst_en_ch(&self) -> IN_DATA_BURST_EN_CH_R { + IN_DATA_BURST_EN_CH_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Set this bit 1 to enable automatic transmitting data from memory to memory via AHB_DMA."] + #[inline(always)] + pub fn mem_trans_en_ch(&self) -> MEM_TRANS_EN_CH_R { + MEM_TRANS_EN_CH_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Set this bit to 1 to enable etm control mode, dma Rx channel 0 is triggered by etm task."] + #[inline(always)] + pub fn in_etm_en_ch(&self) -> IN_ETM_EN_CH_R { + IN_ETM_EN_CH_R::new(((self.bits >> 5) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_CONF0_CH") + .field("in_rst_ch", &format_args!("{}", self.in_rst_ch().bit())) + .field( + "in_loop_test_ch", + &format_args!("{}", self.in_loop_test_ch().bit()), + ) + .field( + "indscr_burst_en_ch", + &format_args!("{}", self.indscr_burst_en_ch().bit()), + ) + .field( + "in_data_burst_en_ch", + &format_args!("{}", self.in_data_burst_en_ch().bit()), + ) + .field( + "mem_trans_en_ch", + &format_args!("{}", self.mem_trans_en_ch().bit()), + ) + .field( + "in_etm_en_ch", + &format_args!("{}", self.in_etm_en_ch().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - This bit is used to reset AHB_DMA channel 0 Rx FSM and Rx FIFO pointer."] + #[inline(always)] + #[must_use] + pub fn in_rst_ch(&mut self) -> IN_RST_CH_W { + IN_RST_CH_W::new(self, 0) + } + #[doc = "Bit 1 - reserved"] + #[inline(always)] + #[must_use] + pub fn in_loop_test_ch(&mut self) -> IN_LOOP_TEST_CH_W { + IN_LOOP_TEST_CH_W::new(self, 1) + } + #[doc = "Bit 2 - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM."] + #[inline(always)] + #[must_use] + pub fn indscr_burst_en_ch(&mut self) -> INDSCR_BURST_EN_CH_W { + INDSCR_BURST_EN_CH_W::new(self, 2) + } + #[doc = "Bit 3 - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM."] + #[inline(always)] + #[must_use] + pub fn in_data_burst_en_ch(&mut self) -> IN_DATA_BURST_EN_CH_W { + IN_DATA_BURST_EN_CH_W::new(self, 3) + } + #[doc = "Bit 4 - Set this bit 1 to enable automatic transmitting data from memory to memory via AHB_DMA."] + #[inline(always)] + #[must_use] + pub fn mem_trans_en_ch(&mut self) -> MEM_TRANS_EN_CH_W { + MEM_TRANS_EN_CH_W::new(self, 4) + } + #[doc = "Bit 5 - Set this bit to 1 to enable etm control mode, dma Rx channel 0 is triggered by etm task."] + #[inline(always)] + #[must_use] + pub fn in_etm_en_ch(&mut self) -> IN_ETM_EN_CH_W { + IN_ETM_EN_CH_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Configure 0 register of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_conf0_ch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_conf0_ch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_CONF0_CH_SPEC; +impl crate::RegisterSpec for IN_CONF0_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_conf0_ch::R`](R) reader structure"] +impl crate::Readable for IN_CONF0_CH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_conf0_ch::W`](W) writer structure"] +impl crate::Writable for IN_CONF0_CH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_CONF0_CH%s to value 0"] +impl crate::Resettable for IN_CONF0_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ahb_dma/in_conf1_ch.rs b/esp32p4/src/ahb_dma/in_conf1_ch.rs new file mode 100644 index 0000000000..b8ad457fd6 --- /dev/null +++ b/esp32p4/src/ahb_dma/in_conf1_ch.rs @@ -0,0 +1,66 @@ +#[doc = "Register `IN_CONF1_CH%s` reader"] +pub type R = crate::R; +#[doc = "Register `IN_CONF1_CH%s` writer"] +pub type W = crate::W; +#[doc = "Field `IN_CHECK_OWNER_CH` reader - Set this bit to enable checking the owner attribute of the link descriptor."] +pub type IN_CHECK_OWNER_CH_R = crate::BitReader; +#[doc = "Field `IN_CHECK_OWNER_CH` writer - Set this bit to enable checking the owner attribute of the link descriptor."] +pub type IN_CHECK_OWNER_CH_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 12 - Set this bit to enable checking the owner attribute of the link descriptor."] + #[inline(always)] + pub fn in_check_owner_ch(&self) -> IN_CHECK_OWNER_CH_R { + IN_CHECK_OWNER_CH_R::new(((self.bits >> 12) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_CONF1_CH") + .field( + "in_check_owner_ch", + &format_args!("{}", self.in_check_owner_ch().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 12 - Set this bit to enable checking the owner attribute of the link descriptor."] + #[inline(always)] + #[must_use] + pub fn in_check_owner_ch(&mut self) -> IN_CHECK_OWNER_CH_W { + IN_CHECK_OWNER_CH_W::new(self, 12) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Configure 1 register of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_conf1_ch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_conf1_ch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_CONF1_CH_SPEC; +impl crate::RegisterSpec for IN_CONF1_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_conf1_ch::R`](R) reader structure"] +impl crate::Readable for IN_CONF1_CH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_conf1_ch::W`](W) writer structure"] +impl crate::Writable for IN_CONF1_CH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_CONF1_CH%s to value 0"] +impl crate::Resettable for IN_CONF1_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ahb_dma/in_crc_clear_ch.rs b/esp32p4/src/ahb_dma/in_crc_clear_ch.rs new file mode 100644 index 0000000000..b1495d4987 --- /dev/null +++ b/esp32p4/src/ahb_dma/in_crc_clear_ch.rs @@ -0,0 +1,66 @@ +#[doc = "Register `IN_CRC_CLEAR_CH%s` reader"] +pub type R = crate::R; +#[doc = "Register `IN_CRC_CLEAR_CH%s` writer"] +pub type W = crate::W; +#[doc = "Field `IN_CRC_CLEAR_CH` reader - This register is used to clear ch0 of rx crc result"] +pub type IN_CRC_CLEAR_CH_R = crate::BitReader; +#[doc = "Field `IN_CRC_CLEAR_CH` writer - This register is used to clear ch0 of rx crc result"] +pub type IN_CRC_CLEAR_CH_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - This register is used to clear ch0 of rx crc result"] + #[inline(always)] + pub fn in_crc_clear_ch(&self) -> IN_CRC_CLEAR_CH_R { + IN_CRC_CLEAR_CH_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_CRC_CLEAR_CH") + .field( + "in_crc_clear_ch", + &format_args!("{}", self.in_crc_clear_ch().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - This register is used to clear ch0 of rx crc result"] + #[inline(always)] + #[must_use] + pub fn in_crc_clear_ch(&mut self) -> IN_CRC_CLEAR_CH_W { + IN_CRC_CLEAR_CH_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "This register is used to clear ch0 crc result\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_crc_clear_ch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_crc_clear_ch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_CRC_CLEAR_CH_SPEC; +impl crate::RegisterSpec for IN_CRC_CLEAR_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_crc_clear_ch::R`](R) reader structure"] +impl crate::Readable for IN_CRC_CLEAR_CH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_crc_clear_ch::W`](W) writer structure"] +impl crate::Writable for IN_CRC_CLEAR_CH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_CRC_CLEAR_CH%s to value 0"] +impl crate::Resettable for IN_CRC_CLEAR_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ahb_dma/in_crc_final_result_ch.rs b/esp32p4/src/ahb_dma/in_crc_final_result_ch.rs new file mode 100644 index 0000000000..0c882874f2 --- /dev/null +++ b/esp32p4/src/ahb_dma/in_crc_final_result_ch.rs @@ -0,0 +1,39 @@ +#[doc = "Register `IN_CRC_FINAL_RESULT_CH%s` reader"] +pub type R = crate::R; +#[doc = "Field `IN_CRC_FINAL_RESULT_CH` reader - This register is used to store result ch0 of rx"] +pub type IN_CRC_FINAL_RESULT_CH_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - This register is used to store result ch0 of rx"] + #[inline(always)] + pub fn in_crc_final_result_ch(&self) -> IN_CRC_FINAL_RESULT_CH_R { + IN_CRC_FINAL_RESULT_CH_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_CRC_FINAL_RESULT_CH") + .field( + "in_crc_final_result_ch", + &format_args!("{}", self.in_crc_final_result_ch().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "This register is used to store ch0 crc result\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_crc_final_result_ch::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_CRC_FINAL_RESULT_CH_SPEC; +impl crate::RegisterSpec for IN_CRC_FINAL_RESULT_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_crc_final_result_ch::R`](R) reader structure"] +impl crate::Readable for IN_CRC_FINAL_RESULT_CH_SPEC {} +#[doc = "`reset()` method sets IN_CRC_FINAL_RESULT_CH%s to value 0"] +impl crate::Resettable for IN_CRC_FINAL_RESULT_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ahb_dma/in_crc_init_data_ch.rs b/esp32p4/src/ahb_dma/in_crc_init_data_ch.rs new file mode 100644 index 0000000000..4d9e32f0a0 --- /dev/null +++ b/esp32p4/src/ahb_dma/in_crc_init_data_ch.rs @@ -0,0 +1,66 @@ +#[doc = "Register `IN_CRC_INIT_DATA_CH%s` reader"] +pub type R = crate::R; +#[doc = "Register `IN_CRC_INIT_DATA_CH%s` writer"] +pub type W = crate::W; +#[doc = "Field `IN_CRC_INIT_DATA_CH` reader - This register is used to config ch0 of rx crc initial value"] +pub type IN_CRC_INIT_DATA_CH_R = crate::FieldReader; +#[doc = "Field `IN_CRC_INIT_DATA_CH` writer - This register is used to config ch0 of rx crc initial value"] +pub type IN_CRC_INIT_DATA_CH_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - This register is used to config ch0 of rx crc initial value"] + #[inline(always)] + pub fn in_crc_init_data_ch(&self) -> IN_CRC_INIT_DATA_CH_R { + IN_CRC_INIT_DATA_CH_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_CRC_INIT_DATA_CH") + .field( + "in_crc_init_data_ch", + &format_args!("{}", self.in_crc_init_data_ch().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - This register is used to config ch0 of rx crc initial value"] + #[inline(always)] + #[must_use] + pub fn in_crc_init_data_ch(&mut self) -> IN_CRC_INIT_DATA_CH_W { + IN_CRC_INIT_DATA_CH_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "This register is used to config ch0 crc initial data(max 32 bit)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_crc_init_data_ch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_crc_init_data_ch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_CRC_INIT_DATA_CH_SPEC; +impl crate::RegisterSpec for IN_CRC_INIT_DATA_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_crc_init_data_ch::R`](R) reader structure"] +impl crate::Readable for IN_CRC_INIT_DATA_CH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_crc_init_data_ch::W`](W) writer structure"] +impl crate::Writable for IN_CRC_INIT_DATA_CH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_CRC_INIT_DATA_CH%s to value 0xffff_ffff"] +impl crate::Resettable for IN_CRC_INIT_DATA_CH_SPEC { + const RESET_VALUE: Self::Ux = 0xffff_ffff; +} diff --git a/esp32p4/src/ahb_dma/in_dscr_bf0_ch.rs b/esp32p4/src/ahb_dma/in_dscr_bf0_ch.rs new file mode 100644 index 0000000000..b860c84a76 --- /dev/null +++ b/esp32p4/src/ahb_dma/in_dscr_bf0_ch.rs @@ -0,0 +1,39 @@ +#[doc = "Register `IN_DSCR_BF0_CH%s` reader"] +pub type R = crate::R; +#[doc = "Field `INLINK_DSCR_BF0_CH` reader - The address of the last inlink descriptor x-1."] +pub type INLINK_DSCR_BF0_CH_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The address of the last inlink descriptor x-1."] + #[inline(always)] + pub fn inlink_dscr_bf0_ch(&self) -> INLINK_DSCR_BF0_CH_R { + INLINK_DSCR_BF0_CH_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_DSCR_BF0_CH") + .field( + "inlink_dscr_bf0_ch", + &format_args!("{}", self.inlink_dscr_bf0_ch().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "The last inlink descriptor address of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_dscr_bf0_ch::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_DSCR_BF0_CH_SPEC; +impl crate::RegisterSpec for IN_DSCR_BF0_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_dscr_bf0_ch::R`](R) reader structure"] +impl crate::Readable for IN_DSCR_BF0_CH_SPEC {} +#[doc = "`reset()` method sets IN_DSCR_BF0_CH%s to value 0"] +impl crate::Resettable for IN_DSCR_BF0_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ahb_dma/in_dscr_bf1_ch.rs b/esp32p4/src/ahb_dma/in_dscr_bf1_ch.rs new file mode 100644 index 0000000000..1db9eea30b --- /dev/null +++ b/esp32p4/src/ahb_dma/in_dscr_bf1_ch.rs @@ -0,0 +1,39 @@ +#[doc = "Register `IN_DSCR_BF1_CH%s` reader"] +pub type R = crate::R; +#[doc = "Field `INLINK_DSCR_BF1_CH` reader - The address of the second-to-last inlink descriptor x-2."] +pub type INLINK_DSCR_BF1_CH_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The address of the second-to-last inlink descriptor x-2."] + #[inline(always)] + pub fn inlink_dscr_bf1_ch(&self) -> INLINK_DSCR_BF1_CH_R { + INLINK_DSCR_BF1_CH_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_DSCR_BF1_CH") + .field( + "inlink_dscr_bf1_ch", + &format_args!("{}", self.inlink_dscr_bf1_ch().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "The second-to-last inlink descriptor address of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_dscr_bf1_ch::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_DSCR_BF1_CH_SPEC; +impl crate::RegisterSpec for IN_DSCR_BF1_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_dscr_bf1_ch::R`](R) reader structure"] +impl crate::Readable for IN_DSCR_BF1_CH_SPEC {} +#[doc = "`reset()` method sets IN_DSCR_BF1_CH%s to value 0"] +impl crate::Resettable for IN_DSCR_BF1_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ahb_dma/in_dscr_ch.rs b/esp32p4/src/ahb_dma/in_dscr_ch.rs new file mode 100644 index 0000000000..1759668e9f --- /dev/null +++ b/esp32p4/src/ahb_dma/in_dscr_ch.rs @@ -0,0 +1,39 @@ +#[doc = "Register `IN_DSCR_CH%s` reader"] +pub type R = crate::R; +#[doc = "Field `INLINK_DSCR_CH` reader - The address of the current inlink descriptor x."] +pub type INLINK_DSCR_CH_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The address of the current inlink descriptor x."] + #[inline(always)] + pub fn inlink_dscr_ch(&self) -> INLINK_DSCR_CH_R { + INLINK_DSCR_CH_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_DSCR_CH") + .field( + "inlink_dscr_ch", + &format_args!("{}", self.inlink_dscr_ch().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Current inlink descriptor address of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_dscr_ch::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_DSCR_CH_SPEC; +impl crate::RegisterSpec for IN_DSCR_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_dscr_ch::R`](R) reader structure"] +impl crate::Readable for IN_DSCR_CH_SPEC {} +#[doc = "`reset()` method sets IN_DSCR_CH%s to value 0"] +impl crate::Resettable for IN_DSCR_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ahb_dma/in_err_eof_des_addr_ch.rs b/esp32p4/src/ahb_dma/in_err_eof_des_addr_ch.rs new file mode 100644 index 0000000000..aa9a2761b7 --- /dev/null +++ b/esp32p4/src/ahb_dma/in_err_eof_des_addr_ch.rs @@ -0,0 +1,39 @@ +#[doc = "Register `IN_ERR_EOF_DES_ADDR_CH%s` reader"] +pub type R = crate::R; +#[doc = "Field `IN_ERR_EOF_DES_ADDR_CH` reader - This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0."] +pub type IN_ERR_EOF_DES_ADDR_CH_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0."] + #[inline(always)] + pub fn in_err_eof_des_addr_ch(&self) -> IN_ERR_EOF_DES_ADDR_CH_R { + IN_ERR_EOF_DES_ADDR_CH_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_ERR_EOF_DES_ADDR_CH") + .field( + "in_err_eof_des_addr_ch", + &format_args!("{}", self.in_err_eof_des_addr_ch().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Inlink descriptor address when errors occur of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_err_eof_des_addr_ch::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_ERR_EOF_DES_ADDR_CH_SPEC; +impl crate::RegisterSpec for IN_ERR_EOF_DES_ADDR_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_err_eof_des_addr_ch::R`](R) reader structure"] +impl crate::Readable for IN_ERR_EOF_DES_ADDR_CH_SPEC {} +#[doc = "`reset()` method sets IN_ERR_EOF_DES_ADDR_CH%s to value 0"] +impl crate::Resettable for IN_ERR_EOF_DES_ADDR_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ahb_dma/in_int_clr_ch.rs b/esp32p4/src/ahb_dma/in_int_clr_ch.rs new file mode 100644 index 0000000000..e588fc8ab6 --- /dev/null +++ b/esp32p4/src/ahb_dma/in_int_clr_ch.rs @@ -0,0 +1,90 @@ +#[doc = "Register `IN_INT_CLR_CH%s` writer"] +pub type W = crate::W; +#[doc = "Field `IN_DONE_CH_INT_CLR` writer - Set this bit to clear the IN_DONE_CH_INT interrupt."] +pub type IN_DONE_CH_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_SUC_EOF_CH_INT_CLR` writer - Set this bit to clear the IN_SUC_EOF_CH_INT interrupt."] +pub type IN_SUC_EOF_CH_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_ERR_EOF_CH_INT_CLR` writer - Set this bit to clear the IN_ERR_EOF_CH_INT interrupt."] +pub type IN_ERR_EOF_CH_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_DSCR_ERR_CH_INT_CLR` writer - Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt."] +pub type IN_DSCR_ERR_CH_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_DSCR_EMPTY_CH_INT_CLR` writer - Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt."] +pub type IN_DSCR_EMPTY_CH_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_OVF_CH_INT_CLR` writer - Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt."] +pub type INFIFO_OVF_CH_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_UDF_CH_INT_CLR` writer - Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt."] +pub type INFIFO_UDF_CH_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Set this bit to clear the IN_DONE_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_done_ch_int_clr(&mut self) -> IN_DONE_CH_INT_CLR_W { + IN_DONE_CH_INT_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - Set this bit to clear the IN_SUC_EOF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_suc_eof_ch_int_clr(&mut self) -> IN_SUC_EOF_CH_INT_CLR_W { + IN_SUC_EOF_CH_INT_CLR_W::new(self, 1) + } + #[doc = "Bit 2 - Set this bit to clear the IN_ERR_EOF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_err_eof_ch_int_clr(&mut self) -> IN_ERR_EOF_CH_INT_CLR_W { + IN_ERR_EOF_CH_INT_CLR_W::new(self, 2) + } + #[doc = "Bit 3 - Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_dscr_err_ch_int_clr(&mut self) -> IN_DSCR_ERR_CH_INT_CLR_W { + IN_DSCR_ERR_CH_INT_CLR_W::new(self, 3) + } + #[doc = "Bit 4 - Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_dscr_empty_ch_int_clr(&mut self) -> IN_DSCR_EMPTY_CH_INT_CLR_W { + IN_DSCR_EMPTY_CH_INT_CLR_W::new(self, 4) + } + #[doc = "Bit 5 - Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn infifo_ovf_ch_int_clr(&mut self) -> INFIFO_OVF_CH_INT_CLR_W { + INFIFO_OVF_CH_INT_CLR_W::new(self, 5) + } + #[doc = "Bit 6 - Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn infifo_udf_ch_int_clr(&mut self) -> INFIFO_UDF_CH_INT_CLR_W { + INFIFO_UDF_CH_INT_CLR_W::new(self, 6) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Interrupt clear bits of channel 0\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_int_clr_ch::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_INT_CLR_CH_SPEC; +impl crate::RegisterSpec for IN_INT_CLR_CH_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`in_int_clr_ch::W`](W) writer structure"] +impl crate::Writable for IN_INT_CLR_CH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_INT_CLR_CH%s to value 0"] +impl crate::Resettable for IN_INT_CLR_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ahb_dma/in_int_ena_ch.rs b/esp32p4/src/ahb_dma/in_int_ena_ch.rs new file mode 100644 index 0000000000..c25e6e70e7 --- /dev/null +++ b/esp32p4/src/ahb_dma/in_int_ena_ch.rs @@ -0,0 +1,180 @@ +#[doc = "Register `IN_INT_ENA_CH%s` reader"] +pub type R = crate::R; +#[doc = "Register `IN_INT_ENA_CH%s` writer"] +pub type W = crate::W; +#[doc = "Field `IN_DONE_CH_INT_ENA` reader - The interrupt enable bit for the IN_DONE_CH_INT interrupt."] +pub type IN_DONE_CH_INT_ENA_R = crate::BitReader; +#[doc = "Field `IN_DONE_CH_INT_ENA` writer - The interrupt enable bit for the IN_DONE_CH_INT interrupt."] +pub type IN_DONE_CH_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_SUC_EOF_CH_INT_ENA` reader - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."] +pub type IN_SUC_EOF_CH_INT_ENA_R = crate::BitReader; +#[doc = "Field `IN_SUC_EOF_CH_INT_ENA` writer - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."] +pub type IN_SUC_EOF_CH_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_ERR_EOF_CH_INT_ENA` reader - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt."] +pub type IN_ERR_EOF_CH_INT_ENA_R = crate::BitReader; +#[doc = "Field `IN_ERR_EOF_CH_INT_ENA` writer - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt."] +pub type IN_ERR_EOF_CH_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_DSCR_ERR_CH_INT_ENA` reader - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt."] +pub type IN_DSCR_ERR_CH_INT_ENA_R = crate::BitReader; +#[doc = "Field `IN_DSCR_ERR_CH_INT_ENA` writer - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt."] +pub type IN_DSCR_ERR_CH_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_DSCR_EMPTY_CH_INT_ENA` reader - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt."] +pub type IN_DSCR_EMPTY_CH_INT_ENA_R = crate::BitReader; +#[doc = "Field `IN_DSCR_EMPTY_CH_INT_ENA` writer - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt."] +pub type IN_DSCR_EMPTY_CH_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_OVF_CH_INT_ENA` reader - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."] +pub type INFIFO_OVF_CH_INT_ENA_R = crate::BitReader; +#[doc = "Field `INFIFO_OVF_CH_INT_ENA` writer - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."] +pub type INFIFO_OVF_CH_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_UDF_CH_INT_ENA` reader - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."] +pub type INFIFO_UDF_CH_INT_ENA_R = crate::BitReader; +#[doc = "Field `INFIFO_UDF_CH_INT_ENA` writer - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."] +pub type INFIFO_UDF_CH_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The interrupt enable bit for the IN_DONE_CH_INT interrupt."] + #[inline(always)] + pub fn in_done_ch_int_ena(&self) -> IN_DONE_CH_INT_ENA_R { + IN_DONE_CH_INT_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."] + #[inline(always)] + pub fn in_suc_eof_ch_int_ena(&self) -> IN_SUC_EOF_CH_INT_ENA_R { + IN_SUC_EOF_CH_INT_ENA_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt."] + #[inline(always)] + pub fn in_err_eof_ch_int_ena(&self) -> IN_ERR_EOF_CH_INT_ENA_R { + IN_ERR_EOF_CH_INT_ENA_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt."] + #[inline(always)] + pub fn in_dscr_err_ch_int_ena(&self) -> IN_DSCR_ERR_CH_INT_ENA_R { + IN_DSCR_ERR_CH_INT_ENA_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt."] + #[inline(always)] + pub fn in_dscr_empty_ch_int_ena(&self) -> IN_DSCR_EMPTY_CH_INT_ENA_R { + IN_DSCR_EMPTY_CH_INT_ENA_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."] + #[inline(always)] + pub fn infifo_ovf_ch_int_ena(&self) -> INFIFO_OVF_CH_INT_ENA_R { + INFIFO_OVF_CH_INT_ENA_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."] + #[inline(always)] + pub fn infifo_udf_ch_int_ena(&self) -> INFIFO_UDF_CH_INT_ENA_R { + INFIFO_UDF_CH_INT_ENA_R::new(((self.bits >> 6) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_INT_ENA_CH") + .field( + "in_done_ch_int_ena", + &format_args!("{}", self.in_done_ch_int_ena().bit()), + ) + .field( + "in_suc_eof_ch_int_ena", + &format_args!("{}", self.in_suc_eof_ch_int_ena().bit()), + ) + .field( + "in_err_eof_ch_int_ena", + &format_args!("{}", self.in_err_eof_ch_int_ena().bit()), + ) + .field( + "in_dscr_err_ch_int_ena", + &format_args!("{}", self.in_dscr_err_ch_int_ena().bit()), + ) + .field( + "in_dscr_empty_ch_int_ena", + &format_args!("{}", self.in_dscr_empty_ch_int_ena().bit()), + ) + .field( + "infifo_ovf_ch_int_ena", + &format_args!("{}", self.infifo_ovf_ch_int_ena().bit()), + ) + .field( + "infifo_udf_ch_int_ena", + &format_args!("{}", self.infifo_udf_ch_int_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The interrupt enable bit for the IN_DONE_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_done_ch_int_ena(&mut self) -> IN_DONE_CH_INT_ENA_W { + IN_DONE_CH_INT_ENA_W::new(self, 0) + } + #[doc = "Bit 1 - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_suc_eof_ch_int_ena(&mut self) -> IN_SUC_EOF_CH_INT_ENA_W { + IN_SUC_EOF_CH_INT_ENA_W::new(self, 1) + } + #[doc = "Bit 2 - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_err_eof_ch_int_ena(&mut self) -> IN_ERR_EOF_CH_INT_ENA_W { + IN_ERR_EOF_CH_INT_ENA_W::new(self, 2) + } + #[doc = "Bit 3 - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_dscr_err_ch_int_ena(&mut self) -> IN_DSCR_ERR_CH_INT_ENA_W { + IN_DSCR_ERR_CH_INT_ENA_W::new(self, 3) + } + #[doc = "Bit 4 - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_dscr_empty_ch_int_ena(&mut self) -> IN_DSCR_EMPTY_CH_INT_ENA_W { + IN_DSCR_EMPTY_CH_INT_ENA_W::new(self, 4) + } + #[doc = "Bit 5 - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn infifo_ovf_ch_int_ena(&mut self) -> INFIFO_OVF_CH_INT_ENA_W { + INFIFO_OVF_CH_INT_ENA_W::new(self, 5) + } + #[doc = "Bit 6 - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn infifo_udf_ch_int_ena(&mut self) -> INFIFO_UDF_CH_INT_ENA_W { + INFIFO_UDF_CH_INT_ENA_W::new(self, 6) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Interrupt enable bits of channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_int_ena_ch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_int_ena_ch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_INT_ENA_CH_SPEC; +impl crate::RegisterSpec for IN_INT_ENA_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_int_ena_ch::R`](R) reader structure"] +impl crate::Readable for IN_INT_ENA_CH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_int_ena_ch::W`](W) writer structure"] +impl crate::Writable for IN_INT_ENA_CH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_INT_ENA_CH%s to value 0"] +impl crate::Resettable for IN_INT_ENA_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ahb_dma/in_int_raw_ch.rs b/esp32p4/src/ahb_dma/in_int_raw_ch.rs new file mode 100644 index 0000000000..23615ead57 --- /dev/null +++ b/esp32p4/src/ahb_dma/in_int_raw_ch.rs @@ -0,0 +1,180 @@ +#[doc = "Register `IN_INT_RAW_CH%s` reader"] +pub type R = crate::R; +#[doc = "Register `IN_INT_RAW_CH%s` writer"] +pub type W = crate::W; +#[doc = "Field `IN_DONE_CH_INT_RAW` reader - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0."] +pub type IN_DONE_CH_INT_RAW_R = crate::BitReader; +#[doc = "Field `IN_DONE_CH_INT_RAW` writer - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0."] +pub type IN_DONE_CH_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_SUC_EOF_CH_INT_RAW` reader - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0."] +pub type IN_SUC_EOF_CH_INT_RAW_R = crate::BitReader; +#[doc = "Field `IN_SUC_EOF_CH_INT_RAW` writer - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0."] +pub type IN_SUC_EOF_CH_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_ERR_EOF_CH_INT_RAW` reader - The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw interrupt is reserved."] +pub type IN_ERR_EOF_CH_INT_RAW_R = crate::BitReader; +#[doc = "Field `IN_ERR_EOF_CH_INT_RAW` writer - The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw interrupt is reserved."] +pub type IN_ERR_EOF_CH_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_DSCR_ERR_CH_INT_RAW` reader - The raw interrupt bit turns to high level when detecting inlink descriptor error including owner error and the second and third word error of inlink descriptor for Rx channel 0."] +pub type IN_DSCR_ERR_CH_INT_RAW_R = crate::BitReader; +#[doc = "Field `IN_DSCR_ERR_CH_INT_RAW` writer - The raw interrupt bit turns to high level when detecting inlink descriptor error including owner error and the second and third word error of inlink descriptor for Rx channel 0."] +pub type IN_DSCR_ERR_CH_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_DSCR_EMPTY_CH_INT_RAW` reader - The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed but there is no more inlink for Rx channel 0."] +pub type IN_DSCR_EMPTY_CH_INT_RAW_R = crate::BitReader; +#[doc = "Field `IN_DSCR_EMPTY_CH_INT_RAW` writer - The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed but there is no more inlink for Rx channel 0."] +pub type IN_DSCR_EMPTY_CH_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_OVF_CH_INT_RAW` reader - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow."] +pub type INFIFO_OVF_CH_INT_RAW_R = crate::BitReader; +#[doc = "Field `INFIFO_OVF_CH_INT_RAW` writer - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow."] +pub type INFIFO_OVF_CH_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_UDF_CH_INT_RAW` reader - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow."] +pub type INFIFO_UDF_CH_INT_RAW_R = crate::BitReader; +#[doc = "Field `INFIFO_UDF_CH_INT_RAW` writer - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow."] +pub type INFIFO_UDF_CH_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0."] + #[inline(always)] + pub fn in_done_ch_int_raw(&self) -> IN_DONE_CH_INT_RAW_R { + IN_DONE_CH_INT_RAW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0."] + #[inline(always)] + pub fn in_suc_eof_ch_int_raw(&self) -> IN_SUC_EOF_CH_INT_RAW_R { + IN_SUC_EOF_CH_INT_RAW_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw interrupt is reserved."] + #[inline(always)] + pub fn in_err_eof_ch_int_raw(&self) -> IN_ERR_EOF_CH_INT_RAW_R { + IN_ERR_EOF_CH_INT_RAW_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The raw interrupt bit turns to high level when detecting inlink descriptor error including owner error and the second and third word error of inlink descriptor for Rx channel 0."] + #[inline(always)] + pub fn in_dscr_err_ch_int_raw(&self) -> IN_DSCR_ERR_CH_INT_RAW_R { + IN_DSCR_ERR_CH_INT_RAW_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed but there is no more inlink for Rx channel 0."] + #[inline(always)] + pub fn in_dscr_empty_ch_int_raw(&self) -> IN_DSCR_EMPTY_CH_INT_RAW_R { + IN_DSCR_EMPTY_CH_INT_RAW_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow."] + #[inline(always)] + pub fn infifo_ovf_ch_int_raw(&self) -> INFIFO_OVF_CH_INT_RAW_R { + INFIFO_OVF_CH_INT_RAW_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow."] + #[inline(always)] + pub fn infifo_udf_ch_int_raw(&self) -> INFIFO_UDF_CH_INT_RAW_R { + INFIFO_UDF_CH_INT_RAW_R::new(((self.bits >> 6) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_INT_RAW_CH") + .field( + "in_done_ch_int_raw", + &format_args!("{}", self.in_done_ch_int_raw().bit()), + ) + .field( + "in_suc_eof_ch_int_raw", + &format_args!("{}", self.in_suc_eof_ch_int_raw().bit()), + ) + .field( + "in_err_eof_ch_int_raw", + &format_args!("{}", self.in_err_eof_ch_int_raw().bit()), + ) + .field( + "in_dscr_err_ch_int_raw", + &format_args!("{}", self.in_dscr_err_ch_int_raw().bit()), + ) + .field( + "in_dscr_empty_ch_int_raw", + &format_args!("{}", self.in_dscr_empty_ch_int_raw().bit()), + ) + .field( + "infifo_ovf_ch_int_raw", + &format_args!("{}", self.infifo_ovf_ch_int_raw().bit()), + ) + .field( + "infifo_udf_ch_int_raw", + &format_args!("{}", self.infifo_udf_ch_int_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0."] + #[inline(always)] + #[must_use] + pub fn in_done_ch_int_raw(&mut self) -> IN_DONE_CH_INT_RAW_W { + IN_DONE_CH_INT_RAW_W::new(self, 0) + } + #[doc = "Bit 1 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0."] + #[inline(always)] + #[must_use] + pub fn in_suc_eof_ch_int_raw(&mut self) -> IN_SUC_EOF_CH_INT_RAW_W { + IN_SUC_EOF_CH_INT_RAW_W::new(self, 1) + } + #[doc = "Bit 2 - The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw interrupt is reserved."] + #[inline(always)] + #[must_use] + pub fn in_err_eof_ch_int_raw(&mut self) -> IN_ERR_EOF_CH_INT_RAW_W { + IN_ERR_EOF_CH_INT_RAW_W::new(self, 2) + } + #[doc = "Bit 3 - The raw interrupt bit turns to high level when detecting inlink descriptor error including owner error and the second and third word error of inlink descriptor for Rx channel 0."] + #[inline(always)] + #[must_use] + pub fn in_dscr_err_ch_int_raw(&mut self) -> IN_DSCR_ERR_CH_INT_RAW_W { + IN_DSCR_ERR_CH_INT_RAW_W::new(self, 3) + } + #[doc = "Bit 4 - The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed but there is no more inlink for Rx channel 0."] + #[inline(always)] + #[must_use] + pub fn in_dscr_empty_ch_int_raw(&mut self) -> IN_DSCR_EMPTY_CH_INT_RAW_W { + IN_DSCR_EMPTY_CH_INT_RAW_W::new(self, 4) + } + #[doc = "Bit 5 - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow."] + #[inline(always)] + #[must_use] + pub fn infifo_ovf_ch_int_raw(&mut self) -> INFIFO_OVF_CH_INT_RAW_W { + INFIFO_OVF_CH_INT_RAW_W::new(self, 5) + } + #[doc = "Bit 6 - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow."] + #[inline(always)] + #[must_use] + pub fn infifo_udf_ch_int_raw(&mut self) -> INFIFO_UDF_CH_INT_RAW_W { + INFIFO_UDF_CH_INT_RAW_W::new(self, 6) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Raw status interrupt of channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_int_raw_ch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_int_raw_ch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_INT_RAW_CH_SPEC; +impl crate::RegisterSpec for IN_INT_RAW_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_int_raw_ch::R`](R) reader structure"] +impl crate::Readable for IN_INT_RAW_CH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_int_raw_ch::W`](W) writer structure"] +impl crate::Writable for IN_INT_RAW_CH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_INT_RAW_CH%s to value 0"] +impl crate::Resettable for IN_INT_RAW_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ahb_dma/in_int_st_ch.rs b/esp32p4/src/ahb_dma/in_int_st_ch.rs new file mode 100644 index 0000000000..7c69399a31 --- /dev/null +++ b/esp32p4/src/ahb_dma/in_int_st_ch.rs @@ -0,0 +1,105 @@ +#[doc = "Register `IN_INT_ST_CH%s` reader"] +pub type R = crate::R; +#[doc = "Field `IN_DONE_CH_INT_ST` reader - The raw interrupt status bit for the IN_DONE_CH_INT interrupt."] +pub type IN_DONE_CH_INT_ST_R = crate::BitReader; +#[doc = "Field `IN_SUC_EOF_CH_INT_ST` reader - The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt."] +pub type IN_SUC_EOF_CH_INT_ST_R = crate::BitReader; +#[doc = "Field `IN_ERR_EOF_CH_INT_ST` reader - The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt."] +pub type IN_ERR_EOF_CH_INT_ST_R = crate::BitReader; +#[doc = "Field `IN_DSCR_ERR_CH_INT_ST` reader - The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt."] +pub type IN_DSCR_ERR_CH_INT_ST_R = crate::BitReader; +#[doc = "Field `IN_DSCR_EMPTY_CH_INT_ST` reader - The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt."] +pub type IN_DSCR_EMPTY_CH_INT_ST_R = crate::BitReader; +#[doc = "Field `INFIFO_OVF_CH_INT_ST` reader - The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt."] +pub type INFIFO_OVF_CH_INT_ST_R = crate::BitReader; +#[doc = "Field `INFIFO_UDF_CH_INT_ST` reader - The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt."] +pub type INFIFO_UDF_CH_INT_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - The raw interrupt status bit for the IN_DONE_CH_INT interrupt."] + #[inline(always)] + pub fn in_done_ch_int_st(&self) -> IN_DONE_CH_INT_ST_R { + IN_DONE_CH_INT_ST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt."] + #[inline(always)] + pub fn in_suc_eof_ch_int_st(&self) -> IN_SUC_EOF_CH_INT_ST_R { + IN_SUC_EOF_CH_INT_ST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt."] + #[inline(always)] + pub fn in_err_eof_ch_int_st(&self) -> IN_ERR_EOF_CH_INT_ST_R { + IN_ERR_EOF_CH_INT_ST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt."] + #[inline(always)] + pub fn in_dscr_err_ch_int_st(&self) -> IN_DSCR_ERR_CH_INT_ST_R { + IN_DSCR_ERR_CH_INT_ST_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt."] + #[inline(always)] + pub fn in_dscr_empty_ch_int_st(&self) -> IN_DSCR_EMPTY_CH_INT_ST_R { + IN_DSCR_EMPTY_CH_INT_ST_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt."] + #[inline(always)] + pub fn infifo_ovf_ch_int_st(&self) -> INFIFO_OVF_CH_INT_ST_R { + INFIFO_OVF_CH_INT_ST_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt."] + #[inline(always)] + pub fn infifo_udf_ch_int_st(&self) -> INFIFO_UDF_CH_INT_ST_R { + INFIFO_UDF_CH_INT_ST_R::new(((self.bits >> 6) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_INT_ST_CH") + .field( + "in_done_ch_int_st", + &format_args!("{}", self.in_done_ch_int_st().bit()), + ) + .field( + "in_suc_eof_ch_int_st", + &format_args!("{}", self.in_suc_eof_ch_int_st().bit()), + ) + .field( + "in_err_eof_ch_int_st", + &format_args!("{}", self.in_err_eof_ch_int_st().bit()), + ) + .field( + "in_dscr_err_ch_int_st", + &format_args!("{}", self.in_dscr_err_ch_int_st().bit()), + ) + .field( + "in_dscr_empty_ch_int_st", + &format_args!("{}", self.in_dscr_empty_ch_int_st().bit()), + ) + .field( + "infifo_ovf_ch_int_st", + &format_args!("{}", self.infifo_ovf_ch_int_st().bit()), + ) + .field( + "infifo_udf_ch_int_st", + &format_args!("{}", self.infifo_udf_ch_int_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Masked interrupt of channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_int_st_ch::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_INT_ST_CH_SPEC; +impl crate::RegisterSpec for IN_INT_ST_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_int_st_ch::R`](R) reader structure"] +impl crate::Readable for IN_INT_ST_CH_SPEC {} +#[doc = "`reset()` method sets IN_INT_ST_CH%s to value 0"] +impl crate::Resettable for IN_INT_ST_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ahb_dma/in_link_addr_ch.rs b/esp32p4/src/ahb_dma/in_link_addr_ch.rs new file mode 100644 index 0000000000..0aed0703b2 --- /dev/null +++ b/esp32p4/src/ahb_dma/in_link_addr_ch.rs @@ -0,0 +1,66 @@ +#[doc = "Register `IN_LINK_ADDR_CH%s` reader"] +pub type R = crate::R; +#[doc = "Register `IN_LINK_ADDR_CH%s` writer"] +pub type W = crate::W; +#[doc = "Field `INLINK_ADDR_CH` reader - This register stores the 32 least significant bits of the first inlink descriptor's address."] +pub type INLINK_ADDR_CH_R = crate::FieldReader; +#[doc = "Field `INLINK_ADDR_CH` writer - This register stores the 32 least significant bits of the first inlink descriptor's address."] +pub type INLINK_ADDR_CH_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - This register stores the 32 least significant bits of the first inlink descriptor's address."] + #[inline(always)] + pub fn inlink_addr_ch(&self) -> INLINK_ADDR_CH_R { + INLINK_ADDR_CH_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_LINK_ADDR_CH") + .field( + "inlink_addr_ch", + &format_args!("{}", self.inlink_addr_ch().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - This register stores the 32 least significant bits of the first inlink descriptor's address."] + #[inline(always)] + #[must_use] + pub fn inlink_addr_ch(&mut self) -> INLINK_ADDR_CH_W { + INLINK_ADDR_CH_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Link descriptor configure of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_link_addr_ch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_link_addr_ch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_LINK_ADDR_CH_SPEC; +impl crate::RegisterSpec for IN_LINK_ADDR_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_link_addr_ch::R`](R) reader structure"] +impl crate::Readable for IN_LINK_ADDR_CH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_link_addr_ch::W`](W) writer structure"] +impl crate::Writable for IN_LINK_ADDR_CH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_LINK_ADDR_CH%s to value 0"] +impl crate::Resettable for IN_LINK_ADDR_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ahb_dma/in_link_ch.rs b/esp32p4/src/ahb_dma/in_link_ch.rs new file mode 100644 index 0000000000..998cb25902 --- /dev/null +++ b/esp32p4/src/ahb_dma/in_link_ch.rs @@ -0,0 +1,101 @@ +#[doc = "Register `IN_LINK_CH%s` reader"] +pub type R = crate::R; +#[doc = "Register `IN_LINK_CH%s` writer"] +pub type W = crate::W; +#[doc = "Field `INLINK_AUTO_RET_CH` reader - Set this bit to return to current inlink descriptor's address when there are some errors in current receiving data."] +pub type INLINK_AUTO_RET_CH_R = crate::BitReader; +#[doc = "Field `INLINK_AUTO_RET_CH` writer - Set this bit to return to current inlink descriptor's address when there are some errors in current receiving data."] +pub type INLINK_AUTO_RET_CH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INLINK_STOP_CH` writer - Set this bit to stop dealing with the inlink descriptors."] +pub type INLINK_STOP_CH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INLINK_START_CH` writer - Set this bit to start dealing with the inlink descriptors."] +pub type INLINK_START_CH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INLINK_RESTART_CH` writer - Set this bit to mount a new inlink descriptor."] +pub type INLINK_RESTART_CH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INLINK_PARK_CH` reader - 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working."] +pub type INLINK_PARK_CH_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Set this bit to return to current inlink descriptor's address when there are some errors in current receiving data."] + #[inline(always)] + pub fn inlink_auto_ret_ch(&self) -> INLINK_AUTO_RET_CH_R { + INLINK_AUTO_RET_CH_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 4 - 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working."] + #[inline(always)] + pub fn inlink_park_ch(&self) -> INLINK_PARK_CH_R { + INLINK_PARK_CH_R::new(((self.bits >> 4) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_LINK_CH") + .field( + "inlink_auto_ret_ch", + &format_args!("{}", self.inlink_auto_ret_ch().bit()), + ) + .field( + "inlink_park_ch", + &format_args!("{}", self.inlink_park_ch().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Set this bit to return to current inlink descriptor's address when there are some errors in current receiving data."] + #[inline(always)] + #[must_use] + pub fn inlink_auto_ret_ch(&mut self) -> INLINK_AUTO_RET_CH_W { + INLINK_AUTO_RET_CH_W::new(self, 0) + } + #[doc = "Bit 1 - Set this bit to stop dealing with the inlink descriptors."] + #[inline(always)] + #[must_use] + pub fn inlink_stop_ch(&mut self) -> INLINK_STOP_CH_W { + INLINK_STOP_CH_W::new(self, 1) + } + #[doc = "Bit 2 - Set this bit to start dealing with the inlink descriptors."] + #[inline(always)] + #[must_use] + pub fn inlink_start_ch(&mut self) -> INLINK_START_CH_W { + INLINK_START_CH_W::new(self, 2) + } + #[doc = "Bit 3 - Set this bit to mount a new inlink descriptor."] + #[inline(always)] + #[must_use] + pub fn inlink_restart_ch(&mut self) -> INLINK_RESTART_CH_W { + INLINK_RESTART_CH_W::new(self, 3) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Link descriptor configure and control register of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_link_ch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_link_ch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_LINK_CH_SPEC; +impl crate::RegisterSpec for IN_LINK_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_link_ch::R`](R) reader structure"] +impl crate::Readable for IN_LINK_CH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_link_ch::W`](W) writer structure"] +impl crate::Writable for IN_LINK_CH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_LINK_CH%s to value 0x11"] +impl crate::Resettable for IN_LINK_CH_SPEC { + const RESET_VALUE: Self::Ux = 0x11; +} diff --git a/esp32p4/src/ahb_dma/in_peri_sel_ch.rs b/esp32p4/src/ahb_dma/in_peri_sel_ch.rs new file mode 100644 index 0000000000..0747938ba7 --- /dev/null +++ b/esp32p4/src/ahb_dma/in_peri_sel_ch.rs @@ -0,0 +1,66 @@ +#[doc = "Register `IN_PERI_SEL_CH%s` reader"] +pub type R = crate::R; +#[doc = "Register `IN_PERI_SEL_CH%s` writer"] +pub type W = crate::W; +#[doc = "Field `PERI_IN_SEL_CH` reader - This register is used to select peripheral for Rx channel 0. I3C. 1: Dummy. 2: UHCI0. 3: I2S0. 4: I2S1. 5: I2S2. 6: Dummy. 7: Dummy. 8: ADC_DAC. 9: Dummy. 10: RMT,11~15: Dummy"] +pub type PERI_IN_SEL_CH_R = crate::FieldReader; +#[doc = "Field `PERI_IN_SEL_CH` writer - This register is used to select peripheral for Rx channel 0. I3C. 1: Dummy. 2: UHCI0. 3: I2S0. 4: I2S1. 5: I2S2. 6: Dummy. 7: Dummy. 8: ADC_DAC. 9: Dummy. 10: RMT,11~15: Dummy"] +pub type PERI_IN_SEL_CH_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - This register is used to select peripheral for Rx channel 0. I3C. 1: Dummy. 2: UHCI0. 3: I2S0. 4: I2S1. 5: I2S2. 6: Dummy. 7: Dummy. 8: ADC_DAC. 9: Dummy. 10: RMT,11~15: Dummy"] + #[inline(always)] + pub fn peri_in_sel_ch(&self) -> PERI_IN_SEL_CH_R { + PERI_IN_SEL_CH_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_PERI_SEL_CH") + .field( + "peri_in_sel_ch", + &format_args!("{}", self.peri_in_sel_ch().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - This register is used to select peripheral for Rx channel 0. I3C. 1: Dummy. 2: UHCI0. 3: I2S0. 4: I2S1. 5: I2S2. 6: Dummy. 7: Dummy. 8: ADC_DAC. 9: Dummy. 10: RMT,11~15: Dummy"] + #[inline(always)] + #[must_use] + pub fn peri_in_sel_ch(&mut self) -> PERI_IN_SEL_CH_W { + PERI_IN_SEL_CH_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Peripheral selection of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_peri_sel_ch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_peri_sel_ch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_PERI_SEL_CH_SPEC; +impl crate::RegisterSpec for IN_PERI_SEL_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_peri_sel_ch::R`](R) reader structure"] +impl crate::Readable for IN_PERI_SEL_CH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_peri_sel_ch::W`](W) writer structure"] +impl crate::Writable for IN_PERI_SEL_CH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_PERI_SEL_CH%s to value 0x3f"] +impl crate::Resettable for IN_PERI_SEL_CH_SPEC { + const RESET_VALUE: Self::Ux = 0x3f; +} diff --git a/esp32p4/src/ahb_dma/in_pop_ch.rs b/esp32p4/src/ahb_dma/in_pop_ch.rs new file mode 100644 index 0000000000..f530ddd861 --- /dev/null +++ b/esp32p4/src/ahb_dma/in_pop_ch.rs @@ -0,0 +1,66 @@ +#[doc = "Register `IN_POP_CH%s` reader"] +pub type R = crate::R; +#[doc = "Register `IN_POP_CH%s` writer"] +pub type W = crate::W; +#[doc = "Field `INFIFO_RDATA_CH` reader - This register stores the data popping from AHB_DMA FIFO."] +pub type INFIFO_RDATA_CH_R = crate::FieldReader; +#[doc = "Field `INFIFO_POP_CH` writer - Set this bit to pop data from AHB_DMA FIFO."] +pub type INFIFO_POP_CH_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:11 - This register stores the data popping from AHB_DMA FIFO."] + #[inline(always)] + pub fn infifo_rdata_ch(&self) -> INFIFO_RDATA_CH_R { + INFIFO_RDATA_CH_R::new((self.bits & 0x0fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_POP_CH") + .field( + "infifo_rdata_ch", + &format_args!("{}", self.infifo_rdata_ch().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 12 - Set this bit to pop data from AHB_DMA FIFO."] + #[inline(always)] + #[must_use] + pub fn infifo_pop_ch(&mut self) -> INFIFO_POP_CH_W { + INFIFO_POP_CH_W::new(self, 12) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Pop control register of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_pop_ch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_pop_ch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_POP_CH_SPEC; +impl crate::RegisterSpec for IN_POP_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_pop_ch::R`](R) reader structure"] +impl crate::Readable for IN_POP_CH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_pop_ch::W`](W) writer structure"] +impl crate::Writable for IN_POP_CH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_POP_CH%s to value 0x0800"] +impl crate::Resettable for IN_POP_CH_SPEC { + const RESET_VALUE: Self::Ux = 0x0800; +} diff --git a/esp32p4/src/ahb_dma/in_pri_ch.rs b/esp32p4/src/ahb_dma/in_pri_ch.rs new file mode 100644 index 0000000000..6e2fe42d45 --- /dev/null +++ b/esp32p4/src/ahb_dma/in_pri_ch.rs @@ -0,0 +1,63 @@ +#[doc = "Register `IN_PRI_CH%s` reader"] +pub type R = crate::R; +#[doc = "Register `IN_PRI_CH%s` writer"] +pub type W = crate::W; +#[doc = "Field `RX_PRI_CH` reader - The priority of Rx channel 0. The larger of the value the higher of the priority."] +pub type RX_PRI_CH_R = crate::FieldReader; +#[doc = "Field `RX_PRI_CH` writer - The priority of Rx channel 0. The larger of the value the higher of the priority."] +pub type RX_PRI_CH_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - The priority of Rx channel 0. The larger of the value the higher of the priority."] + #[inline(always)] + pub fn rx_pri_ch(&self) -> RX_PRI_CH_R { + RX_PRI_CH_R::new((self.bits & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_PRI_CH") + .field("rx_pri_ch", &format_args!("{}", self.rx_pri_ch().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:3 - The priority of Rx channel 0. The larger of the value the higher of the priority."] + #[inline(always)] + #[must_use] + pub fn rx_pri_ch(&mut self) -> RX_PRI_CH_W { + RX_PRI_CH_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Priority register of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_pri_ch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_pri_ch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_PRI_CH_SPEC; +impl crate::RegisterSpec for IN_PRI_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_pri_ch::R`](R) reader structure"] +impl crate::Readable for IN_PRI_CH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_pri_ch::W`](W) writer structure"] +impl crate::Writable for IN_PRI_CH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_PRI_CH%s to value 0"] +impl crate::Resettable for IN_PRI_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ahb_dma/in_state_ch.rs b/esp32p4/src/ahb_dma/in_state_ch.rs new file mode 100644 index 0000000000..88cde19415 --- /dev/null +++ b/esp32p4/src/ahb_dma/in_state_ch.rs @@ -0,0 +1,61 @@ +#[doc = "Register `IN_STATE_CH%s` reader"] +pub type R = crate::R; +#[doc = "Field `INLINK_DSCR_ADDR_CH` reader - This register stores the current inlink descriptor's address."] +pub type INLINK_DSCR_ADDR_CH_R = crate::FieldReader; +#[doc = "Field `IN_DSCR_STATE_CH` reader - reserved"] +pub type IN_DSCR_STATE_CH_R = crate::FieldReader; +#[doc = "Field `IN_STATE_CH` reader - reserved"] +pub type IN_STATE_CH_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:17 - This register stores the current inlink descriptor's address."] + #[inline(always)] + pub fn inlink_dscr_addr_ch(&self) -> INLINK_DSCR_ADDR_CH_R { + INLINK_DSCR_ADDR_CH_R::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:19 - reserved"] + #[inline(always)] + pub fn in_dscr_state_ch(&self) -> IN_DSCR_STATE_CH_R { + IN_DSCR_STATE_CH_R::new(((self.bits >> 18) & 3) as u8) + } + #[doc = "Bits 20:22 - reserved"] + #[inline(always)] + pub fn in_state_ch(&self) -> IN_STATE_CH_R { + IN_STATE_CH_R::new(((self.bits >> 20) & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_STATE_CH") + .field( + "inlink_dscr_addr_ch", + &format_args!("{}", self.inlink_dscr_addr_ch().bits()), + ) + .field( + "in_dscr_state_ch", + &format_args!("{}", self.in_dscr_state_ch().bits()), + ) + .field( + "in_state_ch", + &format_args!("{}", self.in_state_ch().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Receive status of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_state_ch::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_STATE_CH_SPEC; +impl crate::RegisterSpec for IN_STATE_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_state_ch::R`](R) reader structure"] +impl crate::Readable for IN_STATE_CH_SPEC {} +#[doc = "`reset()` method sets IN_STATE_CH%s to value 0"] +impl crate::Resettable for IN_STATE_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ahb_dma/in_suc_eof_des_addr_ch.rs b/esp32p4/src/ahb_dma/in_suc_eof_des_addr_ch.rs new file mode 100644 index 0000000000..3405d46814 --- /dev/null +++ b/esp32p4/src/ahb_dma/in_suc_eof_des_addr_ch.rs @@ -0,0 +1,39 @@ +#[doc = "Register `IN_SUC_EOF_DES_ADDR_CH%s` reader"] +pub type R = crate::R; +#[doc = "Field `IN_SUC_EOF_DES_ADDR_CH` reader - This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1."] +pub type IN_SUC_EOF_DES_ADDR_CH_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1."] + #[inline(always)] + pub fn in_suc_eof_des_addr_ch(&self) -> IN_SUC_EOF_DES_ADDR_CH_R { + IN_SUC_EOF_DES_ADDR_CH_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_SUC_EOF_DES_ADDR_CH") + .field( + "in_suc_eof_des_addr_ch", + &format_args!("{}", self.in_suc_eof_des_addr_ch().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Inlink descriptor address when EOF occurs of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_suc_eof_des_addr_ch::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_SUC_EOF_DES_ADDR_CH_SPEC; +impl crate::RegisterSpec for IN_SUC_EOF_DES_ADDR_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_suc_eof_des_addr_ch::R`](R) reader structure"] +impl crate::Readable for IN_SUC_EOF_DES_ADDR_CH_SPEC {} +#[doc = "`reset()` method sets IN_SUC_EOF_DES_ADDR_CH%s to value 0"] +impl crate::Resettable for IN_SUC_EOF_DES_ADDR_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ahb_dma/infifo_status_ch.rs b/esp32p4/src/ahb_dma/infifo_status_ch.rs new file mode 100644 index 0000000000..a5988c410e --- /dev/null +++ b/esp32p4/src/ahb_dma/infifo_status_ch.rs @@ -0,0 +1,116 @@ +#[doc = "Register `INFIFO_STATUS_CH%s` reader"] +pub type R = crate::R; +#[doc = "Field `INFIFO_FULL_CH` reader - L1 Rx FIFO full signal for Rx channel 0."] +pub type INFIFO_FULL_CH_R = crate::BitReader; +#[doc = "Field `INFIFO_EMPTY_CH` reader - L1 Rx FIFO empty signal for Rx channel 0."] +pub type INFIFO_EMPTY_CH_R = crate::BitReader; +#[doc = "Field `INFIFO_CNT_CH` reader - The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0."] +pub type INFIFO_CNT_CH_R = crate::FieldReader; +#[doc = "Field `IN_REMAIN_UNDER_1B_CH` reader - reserved"] +pub type IN_REMAIN_UNDER_1B_CH_R = crate::BitReader; +#[doc = "Field `IN_REMAIN_UNDER_2B_CH` reader - reserved"] +pub type IN_REMAIN_UNDER_2B_CH_R = crate::BitReader; +#[doc = "Field `IN_REMAIN_UNDER_3B_CH` reader - reserved"] +pub type IN_REMAIN_UNDER_3B_CH_R = crate::BitReader; +#[doc = "Field `IN_REMAIN_UNDER_4B_CH` reader - reserved"] +pub type IN_REMAIN_UNDER_4B_CH_R = crate::BitReader; +#[doc = "Field `IN_BUF_HUNGRY_CH` reader - reserved"] +pub type IN_BUF_HUNGRY_CH_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - L1 Rx FIFO full signal for Rx channel 0."] + #[inline(always)] + pub fn infifo_full_ch(&self) -> INFIFO_FULL_CH_R { + INFIFO_FULL_CH_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - L1 Rx FIFO empty signal for Rx channel 0."] + #[inline(always)] + pub fn infifo_empty_ch(&self) -> INFIFO_EMPTY_CH_R { + INFIFO_EMPTY_CH_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:7 - The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0."] + #[inline(always)] + pub fn infifo_cnt_ch(&self) -> INFIFO_CNT_CH_R { + INFIFO_CNT_CH_R::new(((self.bits >> 2) & 0x3f) as u8) + } + #[doc = "Bit 23 - reserved"] + #[inline(always)] + pub fn in_remain_under_1b_ch(&self) -> IN_REMAIN_UNDER_1B_CH_R { + IN_REMAIN_UNDER_1B_CH_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - reserved"] + #[inline(always)] + pub fn in_remain_under_2b_ch(&self) -> IN_REMAIN_UNDER_2B_CH_R { + IN_REMAIN_UNDER_2B_CH_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - reserved"] + #[inline(always)] + pub fn in_remain_under_3b_ch(&self) -> IN_REMAIN_UNDER_3B_CH_R { + IN_REMAIN_UNDER_3B_CH_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - reserved"] + #[inline(always)] + pub fn in_remain_under_4b_ch(&self) -> IN_REMAIN_UNDER_4B_CH_R { + IN_REMAIN_UNDER_4B_CH_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - reserved"] + #[inline(always)] + pub fn in_buf_hungry_ch(&self) -> IN_BUF_HUNGRY_CH_R { + IN_BUF_HUNGRY_CH_R::new(((self.bits >> 27) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INFIFO_STATUS_CH") + .field( + "infifo_full_ch", + &format_args!("{}", self.infifo_full_ch().bit()), + ) + .field( + "infifo_empty_ch", + &format_args!("{}", self.infifo_empty_ch().bit()), + ) + .field( + "infifo_cnt_ch", + &format_args!("{}", self.infifo_cnt_ch().bits()), + ) + .field( + "in_remain_under_1b_ch", + &format_args!("{}", self.in_remain_under_1b_ch().bit()), + ) + .field( + "in_remain_under_2b_ch", + &format_args!("{}", self.in_remain_under_2b_ch().bit()), + ) + .field( + "in_remain_under_3b_ch", + &format_args!("{}", self.in_remain_under_3b_ch().bit()), + ) + .field( + "in_remain_under_4b_ch", + &format_args!("{}", self.in_remain_under_4b_ch().bit()), + ) + .field( + "in_buf_hungry_ch", + &format_args!("{}", self.in_buf_hungry_ch().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Receive FIFO status of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`infifo_status_ch::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INFIFO_STATUS_CH_SPEC; +impl crate::RegisterSpec for INFIFO_STATUS_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`infifo_status_ch::R`](R) reader structure"] +impl crate::Readable for INFIFO_STATUS_CH_SPEC {} +#[doc = "`reset()` method sets INFIFO_STATUS_CH%s to value 0x0780_0003"] +impl crate::Resettable for INFIFO_STATUS_CH_SPEC { + const RESET_VALUE: Self::Ux = 0x0780_0003; +} diff --git a/esp32p4/src/ahb_dma/intr_mem_end_addr.rs b/esp32p4/src/ahb_dma/intr_mem_end_addr.rs new file mode 100644 index 0000000000..5787bf2dcf --- /dev/null +++ b/esp32p4/src/ahb_dma/intr_mem_end_addr.rs @@ -0,0 +1,68 @@ +#[doc = "Register `INTR_MEM_END_ADDR` reader"] +pub type R = crate::R; +#[doc = "Register `INTR_MEM_END_ADDR` writer"] +pub type W = crate::W; +#[doc = "Field `ACCESS_INTR_MEM_END_ADDR` reader - The end address of accessible address space. The access address beyond this range would lead to descriptor error."] +pub type ACCESS_INTR_MEM_END_ADDR_R = crate::FieldReader; +#[doc = "Field `ACCESS_INTR_MEM_END_ADDR` writer - The end address of accessible address space. The access address beyond this range would lead to descriptor error."] +pub type ACCESS_INTR_MEM_END_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - The end address of accessible address space. The access address beyond this range would lead to descriptor error."] + #[inline(always)] + pub fn access_intr_mem_end_addr(&self) -> ACCESS_INTR_MEM_END_ADDR_R { + ACCESS_INTR_MEM_END_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INTR_MEM_END_ADDR") + .field( + "access_intr_mem_end_addr", + &format_args!("{}", self.access_intr_mem_end_addr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - The end address of accessible address space. The access address beyond this range would lead to descriptor error."] + #[inline(always)] + #[must_use] + pub fn access_intr_mem_end_addr( + &mut self, + ) -> ACCESS_INTR_MEM_END_ADDR_W { + ACCESS_INTR_MEM_END_ADDR_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The end address of accessible address space. The access address beyond this range would lead to descriptor error.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_mem_end_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr_mem_end_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTR_MEM_END_ADDR_SPEC; +impl crate::RegisterSpec for INTR_MEM_END_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`intr_mem_end_addr::R`](R) reader structure"] +impl crate::Readable for INTR_MEM_END_ADDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`intr_mem_end_addr::W`](W) writer structure"] +impl crate::Writable for INTR_MEM_END_ADDR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTR_MEM_END_ADDR to value 0xffff_ffff"] +impl crate::Resettable for INTR_MEM_END_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0xffff_ffff; +} diff --git a/esp32p4/src/ahb_dma/intr_mem_start_addr.rs b/esp32p4/src/ahb_dma/intr_mem_start_addr.rs new file mode 100644 index 0000000000..0f84f5d0d1 --- /dev/null +++ b/esp32p4/src/ahb_dma/intr_mem_start_addr.rs @@ -0,0 +1,68 @@ +#[doc = "Register `INTR_MEM_START_ADDR` reader"] +pub type R = crate::R; +#[doc = "Register `INTR_MEM_START_ADDR` writer"] +pub type W = crate::W; +#[doc = "Field `ACCESS_INTR_MEM_START_ADDR` reader - The start address of accessible address space."] +pub type ACCESS_INTR_MEM_START_ADDR_R = crate::FieldReader; +#[doc = "Field `ACCESS_INTR_MEM_START_ADDR` writer - The start address of accessible address space."] +pub type ACCESS_INTR_MEM_START_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - The start address of accessible address space."] + #[inline(always)] + pub fn access_intr_mem_start_addr(&self) -> ACCESS_INTR_MEM_START_ADDR_R { + ACCESS_INTR_MEM_START_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INTR_MEM_START_ADDR") + .field( + "access_intr_mem_start_addr", + &format_args!("{}", self.access_intr_mem_start_addr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - The start address of accessible address space."] + #[inline(always)] + #[must_use] + pub fn access_intr_mem_start_addr( + &mut self, + ) -> ACCESS_INTR_MEM_START_ADDR_W { + ACCESS_INTR_MEM_START_ADDR_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The start address of accessible address space.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_mem_start_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr_mem_start_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTR_MEM_START_ADDR_SPEC; +impl crate::RegisterSpec for INTR_MEM_START_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`intr_mem_start_addr::R`](R) reader structure"] +impl crate::Readable for INTR_MEM_START_ADDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`intr_mem_start_addr::W`](W) writer structure"] +impl crate::Writable for INTR_MEM_START_ADDR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTR_MEM_START_ADDR to value 0"] +impl crate::Resettable for INTR_MEM_START_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ahb_dma/misc_conf.rs b/esp32p4/src/ahb_dma/misc_conf.rs new file mode 100644 index 0000000000..cff6ef9ce2 --- /dev/null +++ b/esp32p4/src/ahb_dma/misc_conf.rs @@ -0,0 +1,98 @@ +#[doc = "Register `MISC_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `MISC_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `AHBM_RST_INTER` reader - Set this bit then clear this bit to reset the internal ahb FSM."] +pub type AHBM_RST_INTER_R = crate::BitReader; +#[doc = "Field `AHBM_RST_INTER` writer - Set this bit then clear this bit to reset the internal ahb FSM."] +pub type AHBM_RST_INTER_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ARB_PRI_DIS` reader - Set this bit to disable priority arbitration function."] +pub type ARB_PRI_DIS_R = crate::BitReader; +#[doc = "Field `ARB_PRI_DIS` writer - Set this bit to disable priority arbitration function."] +pub type ARB_PRI_DIS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_EN` reader - 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers."] +pub type CLK_EN_R = crate::BitReader; +#[doc = "Field `CLK_EN` writer - 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers."] +pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Set this bit then clear this bit to reset the internal ahb FSM."] + #[inline(always)] + pub fn ahbm_rst_inter(&self) -> AHBM_RST_INTER_R { + AHBM_RST_INTER_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 2 - Set this bit to disable priority arbitration function."] + #[inline(always)] + pub fn arb_pri_dis(&self) -> ARB_PRI_DIS_R { + ARB_PRI_DIS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers."] + #[inline(always)] + pub fn clk_en(&self) -> CLK_EN_R { + CLK_EN_R::new(((self.bits >> 3) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MISC_CONF") + .field( + "ahbm_rst_inter", + &format_args!("{}", self.ahbm_rst_inter().bit()), + ) + .field("arb_pri_dis", &format_args!("{}", self.arb_pri_dis().bit())) + .field("clk_en", &format_args!("{}", self.clk_en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Set this bit then clear this bit to reset the internal ahb FSM."] + #[inline(always)] + #[must_use] + pub fn ahbm_rst_inter(&mut self) -> AHBM_RST_INTER_W { + AHBM_RST_INTER_W::new(self, 0) + } + #[doc = "Bit 2 - Set this bit to disable priority arbitration function."] + #[inline(always)] + #[must_use] + pub fn arb_pri_dis(&mut self) -> ARB_PRI_DIS_W { + ARB_PRI_DIS_W::new(self, 2) + } + #[doc = "Bit 3 - 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers."] + #[inline(always)] + #[must_use] + pub fn clk_en(&mut self) -> CLK_EN_W { + CLK_EN_W::new(self, 3) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "MISC register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`misc_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`misc_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MISC_CONF_SPEC; +impl crate::RegisterSpec for MISC_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`misc_conf::R`](R) reader structure"] +impl crate::Readable for MISC_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`misc_conf::W`](W) writer structure"] +impl crate::Writable for MISC_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets MISC_CONF to value 0"] +impl crate::Resettable for MISC_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ahb_dma/out_conf0_ch.rs b/esp32p4/src/ahb_dma/out_conf0_ch.rs new file mode 100644 index 0000000000..282c74ad4c --- /dev/null +++ b/esp32p4/src/ahb_dma/out_conf0_ch.rs @@ -0,0 +1,177 @@ +#[doc = "Register `OUT_CONF0_CH%s` reader"] +pub type R = crate::R; +#[doc = "Register `OUT_CONF0_CH%s` writer"] +pub type W = crate::W; +#[doc = "Field `OUT_RST_CH` reader - This bit is used to reset AHB_DMA channel 1 Tx FSM and Tx FIFO pointer."] +pub type OUT_RST_CH_R = crate::BitReader; +#[doc = "Field `OUT_RST_CH` writer - This bit is used to reset AHB_DMA channel 1 Tx FSM and Tx FIFO pointer."] +pub type OUT_RST_CH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_LOOP_TEST_CH` reader - reserved"] +pub type OUT_LOOP_TEST_CH_R = crate::BitReader; +#[doc = "Field `OUT_LOOP_TEST_CH` writer - reserved"] +pub type OUT_LOOP_TEST_CH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_AUTO_WRBACK_CH` reader - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted."] +pub type OUT_AUTO_WRBACK_CH_R = crate::BitReader; +#[doc = "Field `OUT_AUTO_WRBACK_CH` writer - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted."] +pub type OUT_AUTO_WRBACK_CH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_EOF_MODE_CH` reader - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 1 is generated when data need to transmit has been popped from FIFO in AHB_DMA"] +pub type OUT_EOF_MODE_CH_R = crate::BitReader; +#[doc = "Field `OUT_EOF_MODE_CH` writer - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 1 is generated when data need to transmit has been popped from FIFO in AHB_DMA"] +pub type OUT_EOF_MODE_CH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTDSCR_BURST_EN_CH` reader - Set this bit to 1 to enable INCR burst transfer for Tx channel 1 reading link descriptor when accessing internal SRAM."] +pub type OUTDSCR_BURST_EN_CH_R = crate::BitReader; +#[doc = "Field `OUTDSCR_BURST_EN_CH` writer - Set this bit to 1 to enable INCR burst transfer for Tx channel 1 reading link descriptor when accessing internal SRAM."] +pub type OUTDSCR_BURST_EN_CH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_DATA_BURST_EN_CH` reader - Set this bit to 1 to enable INCR burst transfer for Tx channel 1 transmitting data when accessing internal SRAM."] +pub type OUT_DATA_BURST_EN_CH_R = crate::BitReader; +#[doc = "Field `OUT_DATA_BURST_EN_CH` writer - Set this bit to 1 to enable INCR burst transfer for Tx channel 1 transmitting data when accessing internal SRAM."] +pub type OUT_DATA_BURST_EN_CH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_ETM_EN_CH` reader - Set this bit to 1 to enable etm control mode, dma Tx channel 1 is triggered by etm task."] +pub type OUT_ETM_EN_CH_R = crate::BitReader; +#[doc = "Field `OUT_ETM_EN_CH` writer - Set this bit to 1 to enable etm control mode, dma Tx channel 1 is triggered by etm task."] +pub type OUT_ETM_EN_CH_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - This bit is used to reset AHB_DMA channel 1 Tx FSM and Tx FIFO pointer."] + #[inline(always)] + pub fn out_rst_ch(&self) -> OUT_RST_CH_R { + OUT_RST_CH_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - reserved"] + #[inline(always)] + pub fn out_loop_test_ch(&self) -> OUT_LOOP_TEST_CH_R { + OUT_LOOP_TEST_CH_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted."] + #[inline(always)] + pub fn out_auto_wrback_ch(&self) -> OUT_AUTO_WRBACK_CH_R { + OUT_AUTO_WRBACK_CH_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 1 is generated when data need to transmit has been popped from FIFO in AHB_DMA"] + #[inline(always)] + pub fn out_eof_mode_ch(&self) -> OUT_EOF_MODE_CH_R { + OUT_EOF_MODE_CH_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Set this bit to 1 to enable INCR burst transfer for Tx channel 1 reading link descriptor when accessing internal SRAM."] + #[inline(always)] + pub fn outdscr_burst_en_ch(&self) -> OUTDSCR_BURST_EN_CH_R { + OUTDSCR_BURST_EN_CH_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Set this bit to 1 to enable INCR burst transfer for Tx channel 1 transmitting data when accessing internal SRAM."] + #[inline(always)] + pub fn out_data_burst_en_ch(&self) -> OUT_DATA_BURST_EN_CH_R { + OUT_DATA_BURST_EN_CH_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Set this bit to 1 to enable etm control mode, dma Tx channel 1 is triggered by etm task."] + #[inline(always)] + pub fn out_etm_en_ch(&self) -> OUT_ETM_EN_CH_R { + OUT_ETM_EN_CH_R::new(((self.bits >> 6) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_CONF0_CH") + .field("out_rst_ch", &format_args!("{}", self.out_rst_ch().bit())) + .field( + "out_loop_test_ch", + &format_args!("{}", self.out_loop_test_ch().bit()), + ) + .field( + "out_auto_wrback_ch", + &format_args!("{}", self.out_auto_wrback_ch().bit()), + ) + .field( + "out_eof_mode_ch", + &format_args!("{}", self.out_eof_mode_ch().bit()), + ) + .field( + "outdscr_burst_en_ch", + &format_args!("{}", self.outdscr_burst_en_ch().bit()), + ) + .field( + "out_data_burst_en_ch", + &format_args!("{}", self.out_data_burst_en_ch().bit()), + ) + .field( + "out_etm_en_ch", + &format_args!("{}", self.out_etm_en_ch().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - This bit is used to reset AHB_DMA channel 1 Tx FSM and Tx FIFO pointer."] + #[inline(always)] + #[must_use] + pub fn out_rst_ch(&mut self) -> OUT_RST_CH_W { + OUT_RST_CH_W::new(self, 0) + } + #[doc = "Bit 1 - reserved"] + #[inline(always)] + #[must_use] + pub fn out_loop_test_ch(&mut self) -> OUT_LOOP_TEST_CH_W { + OUT_LOOP_TEST_CH_W::new(self, 1) + } + #[doc = "Bit 2 - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted."] + #[inline(always)] + #[must_use] + pub fn out_auto_wrback_ch(&mut self) -> OUT_AUTO_WRBACK_CH_W { + OUT_AUTO_WRBACK_CH_W::new(self, 2) + } + #[doc = "Bit 3 - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 1 is generated when data need to transmit has been popped from FIFO in AHB_DMA"] + #[inline(always)] + #[must_use] + pub fn out_eof_mode_ch(&mut self) -> OUT_EOF_MODE_CH_W { + OUT_EOF_MODE_CH_W::new(self, 3) + } + #[doc = "Bit 4 - Set this bit to 1 to enable INCR burst transfer for Tx channel 1 reading link descriptor when accessing internal SRAM."] + #[inline(always)] + #[must_use] + pub fn outdscr_burst_en_ch(&mut self) -> OUTDSCR_BURST_EN_CH_W { + OUTDSCR_BURST_EN_CH_W::new(self, 4) + } + #[doc = "Bit 5 - Set this bit to 1 to enable INCR burst transfer for Tx channel 1 transmitting data when accessing internal SRAM."] + #[inline(always)] + #[must_use] + pub fn out_data_burst_en_ch(&mut self) -> OUT_DATA_BURST_EN_CH_W { + OUT_DATA_BURST_EN_CH_W::new(self, 5) + } + #[doc = "Bit 6 - Set this bit to 1 to enable etm control mode, dma Tx channel 1 is triggered by etm task."] + #[inline(always)] + #[must_use] + pub fn out_etm_en_ch(&mut self) -> OUT_ETM_EN_CH_W { + OUT_ETM_EN_CH_W::new(self, 6) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Configure 0 register of Tx channel 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_conf0_ch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_conf0_ch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_CONF0_CH_SPEC; +impl crate::RegisterSpec for OUT_CONF0_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_conf0_ch::R`](R) reader structure"] +impl crate::Readable for OUT_CONF0_CH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out_conf0_ch::W`](W) writer structure"] +impl crate::Writable for OUT_CONF0_CH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_CONF0_CH%s to value 0x08"] +impl crate::Resettable for OUT_CONF0_CH_SPEC { + const RESET_VALUE: Self::Ux = 0x08; +} diff --git a/esp32p4/src/ahb_dma/out_conf0_ch0.rs b/esp32p4/src/ahb_dma/out_conf0_ch0.rs new file mode 100644 index 0000000000..2204858d51 --- /dev/null +++ b/esp32p4/src/ahb_dma/out_conf0_ch0.rs @@ -0,0 +1,177 @@ +#[doc = "Register `OUT_CONF0_CH0` reader"] +pub type R = crate::R; +#[doc = "Register `OUT_CONF0_CH0` writer"] +pub type W = crate::W; +#[doc = "Field `OUT_RST_CH0` reader - This bit is used to reset AHB_DMA channel 0 Tx FSM and Tx FIFO pointer."] +pub type OUT_RST_CH0_R = crate::BitReader; +#[doc = "Field `OUT_RST_CH0` writer - This bit is used to reset AHB_DMA channel 0 Tx FSM and Tx FIFO pointer."] +pub type OUT_RST_CH0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_LOOP_TEST_CH0` reader - reserved"] +pub type OUT_LOOP_TEST_CH0_R = crate::BitReader; +#[doc = "Field `OUT_LOOP_TEST_CH0` writer - reserved"] +pub type OUT_LOOP_TEST_CH0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_AUTO_WRBACK_CH0` reader - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted."] +pub type OUT_AUTO_WRBACK_CH0_R = crate::BitReader; +#[doc = "Field `OUT_AUTO_WRBACK_CH0` writer - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted."] +pub type OUT_AUTO_WRBACK_CH0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_EOF_MODE_CH0` reader - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in AHB_DMA"] +pub type OUT_EOF_MODE_CH0_R = crate::BitReader; +#[doc = "Field `OUT_EOF_MODE_CH0` writer - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in AHB_DMA"] +pub type OUT_EOF_MODE_CH0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTDSCR_BURST_EN_CH0` reader - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM."] +pub type OUTDSCR_BURST_EN_CH0_R = crate::BitReader; +#[doc = "Field `OUTDSCR_BURST_EN_CH0` writer - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM."] +pub type OUTDSCR_BURST_EN_CH0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_DATA_BURST_EN_CH0` reader - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM."] +pub type OUT_DATA_BURST_EN_CH0_R = crate::BitReader; +#[doc = "Field `OUT_DATA_BURST_EN_CH0` writer - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM."] +pub type OUT_DATA_BURST_EN_CH0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_ETM_EN_CH0` reader - Set this bit to 1 to enable etm control mode, dma Tx channel 0 is triggered by etm task."] +pub type OUT_ETM_EN_CH0_R = crate::BitReader; +#[doc = "Field `OUT_ETM_EN_CH0` writer - Set this bit to 1 to enable etm control mode, dma Tx channel 0 is triggered by etm task."] +pub type OUT_ETM_EN_CH0_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - This bit is used to reset AHB_DMA channel 0 Tx FSM and Tx FIFO pointer."] + #[inline(always)] + pub fn out_rst_ch0(&self) -> OUT_RST_CH0_R { + OUT_RST_CH0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - reserved"] + #[inline(always)] + pub fn out_loop_test_ch0(&self) -> OUT_LOOP_TEST_CH0_R { + OUT_LOOP_TEST_CH0_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted."] + #[inline(always)] + pub fn out_auto_wrback_ch0(&self) -> OUT_AUTO_WRBACK_CH0_R { + OUT_AUTO_WRBACK_CH0_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in AHB_DMA"] + #[inline(always)] + pub fn out_eof_mode_ch0(&self) -> OUT_EOF_MODE_CH0_R { + OUT_EOF_MODE_CH0_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM."] + #[inline(always)] + pub fn outdscr_burst_en_ch0(&self) -> OUTDSCR_BURST_EN_CH0_R { + OUTDSCR_BURST_EN_CH0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM."] + #[inline(always)] + pub fn out_data_burst_en_ch0(&self) -> OUT_DATA_BURST_EN_CH0_R { + OUT_DATA_BURST_EN_CH0_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Set this bit to 1 to enable etm control mode, dma Tx channel 0 is triggered by etm task."] + #[inline(always)] + pub fn out_etm_en_ch0(&self) -> OUT_ETM_EN_CH0_R { + OUT_ETM_EN_CH0_R::new(((self.bits >> 6) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_CONF0_CH0") + .field("out_rst_ch0", &format_args!("{}", self.out_rst_ch0().bit())) + .field( + "out_loop_test_ch0", + &format_args!("{}", self.out_loop_test_ch0().bit()), + ) + .field( + "out_auto_wrback_ch0", + &format_args!("{}", self.out_auto_wrback_ch0().bit()), + ) + .field( + "out_eof_mode_ch0", + &format_args!("{}", self.out_eof_mode_ch0().bit()), + ) + .field( + "outdscr_burst_en_ch0", + &format_args!("{}", self.outdscr_burst_en_ch0().bit()), + ) + .field( + "out_data_burst_en_ch0", + &format_args!("{}", self.out_data_burst_en_ch0().bit()), + ) + .field( + "out_etm_en_ch0", + &format_args!("{}", self.out_etm_en_ch0().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - This bit is used to reset AHB_DMA channel 0 Tx FSM and Tx FIFO pointer."] + #[inline(always)] + #[must_use] + pub fn out_rst_ch0(&mut self) -> OUT_RST_CH0_W { + OUT_RST_CH0_W::new(self, 0) + } + #[doc = "Bit 1 - reserved"] + #[inline(always)] + #[must_use] + pub fn out_loop_test_ch0(&mut self) -> OUT_LOOP_TEST_CH0_W { + OUT_LOOP_TEST_CH0_W::new(self, 1) + } + #[doc = "Bit 2 - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted."] + #[inline(always)] + #[must_use] + pub fn out_auto_wrback_ch0(&mut self) -> OUT_AUTO_WRBACK_CH0_W { + OUT_AUTO_WRBACK_CH0_W::new(self, 2) + } + #[doc = "Bit 3 - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in AHB_DMA"] + #[inline(always)] + #[must_use] + pub fn out_eof_mode_ch0(&mut self) -> OUT_EOF_MODE_CH0_W { + OUT_EOF_MODE_CH0_W::new(self, 3) + } + #[doc = "Bit 4 - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM."] + #[inline(always)] + #[must_use] + pub fn outdscr_burst_en_ch0(&mut self) -> OUTDSCR_BURST_EN_CH0_W { + OUTDSCR_BURST_EN_CH0_W::new(self, 4) + } + #[doc = "Bit 5 - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM."] + #[inline(always)] + #[must_use] + pub fn out_data_burst_en_ch0(&mut self) -> OUT_DATA_BURST_EN_CH0_W { + OUT_DATA_BURST_EN_CH0_W::new(self, 5) + } + #[doc = "Bit 6 - Set this bit to 1 to enable etm control mode, dma Tx channel 0 is triggered by etm task."] + #[inline(always)] + #[must_use] + pub fn out_etm_en_ch0(&mut self) -> OUT_ETM_EN_CH0_W { + OUT_ETM_EN_CH0_W::new(self, 6) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Configure 0 register of Tx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_conf0_ch0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_conf0_ch0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_CONF0_CH0_SPEC; +impl crate::RegisterSpec for OUT_CONF0_CH0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_conf0_ch0::R`](R) reader structure"] +impl crate::Readable for OUT_CONF0_CH0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out_conf0_ch0::W`](W) writer structure"] +impl crate::Writable for OUT_CONF0_CH0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_CONF0_CH0 to value 0x08"] +impl crate::Resettable for OUT_CONF0_CH0_SPEC { + const RESET_VALUE: Self::Ux = 0x08; +} diff --git a/esp32p4/src/ahb_dma/out_conf1_ch.rs b/esp32p4/src/ahb_dma/out_conf1_ch.rs new file mode 100644 index 0000000000..54e724cf25 --- /dev/null +++ b/esp32p4/src/ahb_dma/out_conf1_ch.rs @@ -0,0 +1,66 @@ +#[doc = "Register `OUT_CONF1_CH%s` reader"] +pub type R = crate::R; +#[doc = "Register `OUT_CONF1_CH%s` writer"] +pub type W = crate::W; +#[doc = "Field `OUT_CHECK_OWNER_CH` reader - Set this bit to enable checking the owner attribute of the link descriptor."] +pub type OUT_CHECK_OWNER_CH_R = crate::BitReader; +#[doc = "Field `OUT_CHECK_OWNER_CH` writer - Set this bit to enable checking the owner attribute of the link descriptor."] +pub type OUT_CHECK_OWNER_CH_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 12 - Set this bit to enable checking the owner attribute of the link descriptor."] + #[inline(always)] + pub fn out_check_owner_ch(&self) -> OUT_CHECK_OWNER_CH_R { + OUT_CHECK_OWNER_CH_R::new(((self.bits >> 12) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_CONF1_CH") + .field( + "out_check_owner_ch", + &format_args!("{}", self.out_check_owner_ch().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 12 - Set this bit to enable checking the owner attribute of the link descriptor."] + #[inline(always)] + #[must_use] + pub fn out_check_owner_ch(&mut self) -> OUT_CHECK_OWNER_CH_W { + OUT_CHECK_OWNER_CH_W::new(self, 12) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Configure 1 register of Tx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_conf1_ch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_conf1_ch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_CONF1_CH_SPEC; +impl crate::RegisterSpec for OUT_CONF1_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_conf1_ch::R`](R) reader structure"] +impl crate::Readable for OUT_CONF1_CH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out_conf1_ch::W`](W) writer structure"] +impl crate::Writable for OUT_CONF1_CH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_CONF1_CH%s to value 0"] +impl crate::Resettable for OUT_CONF1_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ahb_dma/out_crc_clear_ch.rs b/esp32p4/src/ahb_dma/out_crc_clear_ch.rs new file mode 100644 index 0000000000..b4120a9aea --- /dev/null +++ b/esp32p4/src/ahb_dma/out_crc_clear_ch.rs @@ -0,0 +1,66 @@ +#[doc = "Register `OUT_CRC_CLEAR_CH%s` reader"] +pub type R = crate::R; +#[doc = "Register `OUT_CRC_CLEAR_CH%s` writer"] +pub type W = crate::W; +#[doc = "Field `OUT_CRC_CLEAR_CH` reader - This register is used to clear ch0 of tx crc result"] +pub type OUT_CRC_CLEAR_CH_R = crate::BitReader; +#[doc = "Field `OUT_CRC_CLEAR_CH` writer - This register is used to clear ch0 of tx crc result"] +pub type OUT_CRC_CLEAR_CH_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - This register is used to clear ch0 of tx crc result"] + #[inline(always)] + pub fn out_crc_clear_ch(&self) -> OUT_CRC_CLEAR_CH_R { + OUT_CRC_CLEAR_CH_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_CRC_CLEAR_CH") + .field( + "out_crc_clear_ch", + &format_args!("{}", self.out_crc_clear_ch().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - This register is used to clear ch0 of tx crc result"] + #[inline(always)] + #[must_use] + pub fn out_crc_clear_ch(&mut self) -> OUT_CRC_CLEAR_CH_W { + OUT_CRC_CLEAR_CH_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "This register is used to clear ch0 crc result\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_crc_clear_ch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_crc_clear_ch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_CRC_CLEAR_CH_SPEC; +impl crate::RegisterSpec for OUT_CRC_CLEAR_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_crc_clear_ch::R`](R) reader structure"] +impl crate::Readable for OUT_CRC_CLEAR_CH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out_crc_clear_ch::W`](W) writer structure"] +impl crate::Writable for OUT_CRC_CLEAR_CH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_CRC_CLEAR_CH%s to value 0"] +impl crate::Resettable for OUT_CRC_CLEAR_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ahb_dma/out_crc_final_result_ch.rs b/esp32p4/src/ahb_dma/out_crc_final_result_ch.rs new file mode 100644 index 0000000000..6587c37565 --- /dev/null +++ b/esp32p4/src/ahb_dma/out_crc_final_result_ch.rs @@ -0,0 +1,39 @@ +#[doc = "Register `OUT_CRC_FINAL_RESULT_CH%s` reader"] +pub type R = crate::R; +#[doc = "Field `OUT_CRC_FINAL_RESULT_CH` reader - This register is used to store result ch0 of tx"] +pub type OUT_CRC_FINAL_RESULT_CH_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - This register is used to store result ch0 of tx"] + #[inline(always)] + pub fn out_crc_final_result_ch(&self) -> OUT_CRC_FINAL_RESULT_CH_R { + OUT_CRC_FINAL_RESULT_CH_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_CRC_FINAL_RESULT_CH") + .field( + "out_crc_final_result_ch", + &format_args!("{}", self.out_crc_final_result_ch().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "This register is used to store ch0 crc result\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_crc_final_result_ch::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_CRC_FINAL_RESULT_CH_SPEC; +impl crate::RegisterSpec for OUT_CRC_FINAL_RESULT_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_crc_final_result_ch::R`](R) reader structure"] +impl crate::Readable for OUT_CRC_FINAL_RESULT_CH_SPEC {} +#[doc = "`reset()` method sets OUT_CRC_FINAL_RESULT_CH%s to value 0"] +impl crate::Resettable for OUT_CRC_FINAL_RESULT_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ahb_dma/out_crc_init_data_ch.rs b/esp32p4/src/ahb_dma/out_crc_init_data_ch.rs new file mode 100644 index 0000000000..780dd55dd3 --- /dev/null +++ b/esp32p4/src/ahb_dma/out_crc_init_data_ch.rs @@ -0,0 +1,66 @@ +#[doc = "Register `OUT_CRC_INIT_DATA_CH%s` reader"] +pub type R = crate::R; +#[doc = "Register `OUT_CRC_INIT_DATA_CH%s` writer"] +pub type W = crate::W; +#[doc = "Field `OUT_CRC_INIT_DATA_CH` reader - This register is used to config ch0 of tx crc initial value"] +pub type OUT_CRC_INIT_DATA_CH_R = crate::FieldReader; +#[doc = "Field `OUT_CRC_INIT_DATA_CH` writer - This register is used to config ch0 of tx crc initial value"] +pub type OUT_CRC_INIT_DATA_CH_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - This register is used to config ch0 of tx crc initial value"] + #[inline(always)] + pub fn out_crc_init_data_ch(&self) -> OUT_CRC_INIT_DATA_CH_R { + OUT_CRC_INIT_DATA_CH_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_CRC_INIT_DATA_CH") + .field( + "out_crc_init_data_ch", + &format_args!("{}", self.out_crc_init_data_ch().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - This register is used to config ch0 of tx crc initial value"] + #[inline(always)] + #[must_use] + pub fn out_crc_init_data_ch(&mut self) -> OUT_CRC_INIT_DATA_CH_W { + OUT_CRC_INIT_DATA_CH_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "This register is used to config ch0 crc initial data(max 32 bit)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_crc_init_data_ch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_crc_init_data_ch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_CRC_INIT_DATA_CH_SPEC; +impl crate::RegisterSpec for OUT_CRC_INIT_DATA_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_crc_init_data_ch::R`](R) reader structure"] +impl crate::Readable for OUT_CRC_INIT_DATA_CH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out_crc_init_data_ch::W`](W) writer structure"] +impl crate::Writable for OUT_CRC_INIT_DATA_CH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_CRC_INIT_DATA_CH%s to value 0xffff_ffff"] +impl crate::Resettable for OUT_CRC_INIT_DATA_CH_SPEC { + const RESET_VALUE: Self::Ux = 0xffff_ffff; +} diff --git a/esp32p4/src/ahb_dma/out_dscr_bf0_ch.rs b/esp32p4/src/ahb_dma/out_dscr_bf0_ch.rs new file mode 100644 index 0000000000..7b196c7eb2 --- /dev/null +++ b/esp32p4/src/ahb_dma/out_dscr_bf0_ch.rs @@ -0,0 +1,39 @@ +#[doc = "Register `OUT_DSCR_BF0_CH%s` reader"] +pub type R = crate::R; +#[doc = "Field `OUTLINK_DSCR_BF0_CH` reader - The address of the last outlink descriptor y-1."] +pub type OUTLINK_DSCR_BF0_CH_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The address of the last outlink descriptor y-1."] + #[inline(always)] + pub fn outlink_dscr_bf0_ch(&self) -> OUTLINK_DSCR_BF0_CH_R { + OUTLINK_DSCR_BF0_CH_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_DSCR_BF0_CH") + .field( + "outlink_dscr_bf0_ch", + &format_args!("{}", self.outlink_dscr_bf0_ch().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "The last inlink descriptor address of Tx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_dscr_bf0_ch::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_DSCR_BF0_CH_SPEC; +impl crate::RegisterSpec for OUT_DSCR_BF0_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_dscr_bf0_ch::R`](R) reader structure"] +impl crate::Readable for OUT_DSCR_BF0_CH_SPEC {} +#[doc = "`reset()` method sets OUT_DSCR_BF0_CH%s to value 0"] +impl crate::Resettable for OUT_DSCR_BF0_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ahb_dma/out_dscr_bf1_ch.rs b/esp32p4/src/ahb_dma/out_dscr_bf1_ch.rs new file mode 100644 index 0000000000..fbe00febe9 --- /dev/null +++ b/esp32p4/src/ahb_dma/out_dscr_bf1_ch.rs @@ -0,0 +1,39 @@ +#[doc = "Register `OUT_DSCR_BF1_CH%s` reader"] +pub type R = crate::R; +#[doc = "Field `OUTLINK_DSCR_BF1_CH` reader - The address of the second-to-last inlink descriptor x-2."] +pub type OUTLINK_DSCR_BF1_CH_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The address of the second-to-last inlink descriptor x-2."] + #[inline(always)] + pub fn outlink_dscr_bf1_ch(&self) -> OUTLINK_DSCR_BF1_CH_R { + OUTLINK_DSCR_BF1_CH_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_DSCR_BF1_CH") + .field( + "outlink_dscr_bf1_ch", + &format_args!("{}", self.outlink_dscr_bf1_ch().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "The second-to-last inlink descriptor address of Tx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_dscr_bf1_ch::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_DSCR_BF1_CH_SPEC; +impl crate::RegisterSpec for OUT_DSCR_BF1_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_dscr_bf1_ch::R`](R) reader structure"] +impl crate::Readable for OUT_DSCR_BF1_CH_SPEC {} +#[doc = "`reset()` method sets OUT_DSCR_BF1_CH%s to value 0"] +impl crate::Resettable for OUT_DSCR_BF1_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ahb_dma/out_dscr_ch.rs b/esp32p4/src/ahb_dma/out_dscr_ch.rs new file mode 100644 index 0000000000..cdbf8ba57d --- /dev/null +++ b/esp32p4/src/ahb_dma/out_dscr_ch.rs @@ -0,0 +1,39 @@ +#[doc = "Register `OUT_DSCR_CH%s` reader"] +pub type R = crate::R; +#[doc = "Field `OUTLINK_DSCR_CH` reader - The address of the current outlink descriptor y."] +pub type OUTLINK_DSCR_CH_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The address of the current outlink descriptor y."] + #[inline(always)] + pub fn outlink_dscr_ch(&self) -> OUTLINK_DSCR_CH_R { + OUTLINK_DSCR_CH_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_DSCR_CH") + .field( + "outlink_dscr_ch", + &format_args!("{}", self.outlink_dscr_ch().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Current inlink descriptor address of Tx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_dscr_ch::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_DSCR_CH_SPEC; +impl crate::RegisterSpec for OUT_DSCR_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_dscr_ch::R`](R) reader structure"] +impl crate::Readable for OUT_DSCR_CH_SPEC {} +#[doc = "`reset()` method sets OUT_DSCR_CH%s to value 0"] +impl crate::Resettable for OUT_DSCR_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ahb_dma/out_eof_bfr_des_addr_ch.rs b/esp32p4/src/ahb_dma/out_eof_bfr_des_addr_ch.rs new file mode 100644 index 0000000000..1c93b61373 --- /dev/null +++ b/esp32p4/src/ahb_dma/out_eof_bfr_des_addr_ch.rs @@ -0,0 +1,39 @@ +#[doc = "Register `OUT_EOF_BFR_DES_ADDR_CH%s` reader"] +pub type R = crate::R; +#[doc = "Field `OUT_EOF_BFR_DES_ADDR_CH` reader - This register stores the address of the outlink descriptor before the last outlink descriptor."] +pub type OUT_EOF_BFR_DES_ADDR_CH_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - This register stores the address of the outlink descriptor before the last outlink descriptor."] + #[inline(always)] + pub fn out_eof_bfr_des_addr_ch(&self) -> OUT_EOF_BFR_DES_ADDR_CH_R { + OUT_EOF_BFR_DES_ADDR_CH_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_EOF_BFR_DES_ADDR_CH") + .field( + "out_eof_bfr_des_addr_ch", + &format_args!("{}", self.out_eof_bfr_des_addr_ch().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "The last outlink descriptor address when EOF occurs of Tx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_eof_bfr_des_addr_ch::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_EOF_BFR_DES_ADDR_CH_SPEC; +impl crate::RegisterSpec for OUT_EOF_BFR_DES_ADDR_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_eof_bfr_des_addr_ch::R`](R) reader structure"] +impl crate::Readable for OUT_EOF_BFR_DES_ADDR_CH_SPEC {} +#[doc = "`reset()` method sets OUT_EOF_BFR_DES_ADDR_CH%s to value 0"] +impl crate::Resettable for OUT_EOF_BFR_DES_ADDR_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ahb_dma/out_eof_des_addr_ch.rs b/esp32p4/src/ahb_dma/out_eof_des_addr_ch.rs new file mode 100644 index 0000000000..c47e6ef76e --- /dev/null +++ b/esp32p4/src/ahb_dma/out_eof_des_addr_ch.rs @@ -0,0 +1,39 @@ +#[doc = "Register `OUT_EOF_DES_ADDR_CH%s` reader"] +pub type R = crate::R; +#[doc = "Field `OUT_EOF_DES_ADDR_CH` reader - This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1."] +pub type OUT_EOF_DES_ADDR_CH_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1."] + #[inline(always)] + pub fn out_eof_des_addr_ch(&self) -> OUT_EOF_DES_ADDR_CH_R { + OUT_EOF_DES_ADDR_CH_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_EOF_DES_ADDR_CH") + .field( + "out_eof_des_addr_ch", + &format_args!("{}", self.out_eof_des_addr_ch().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Outlink descriptor address when EOF occurs of Tx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_eof_des_addr_ch::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_EOF_DES_ADDR_CH_SPEC; +impl crate::RegisterSpec for OUT_EOF_DES_ADDR_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_eof_des_addr_ch::R`](R) reader structure"] +impl crate::Readable for OUT_EOF_DES_ADDR_CH_SPEC {} +#[doc = "`reset()` method sets OUT_EOF_DES_ADDR_CH%s to value 0"] +impl crate::Resettable for OUT_EOF_DES_ADDR_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ahb_dma/out_int_clr_ch.rs b/esp32p4/src/ahb_dma/out_int_clr_ch.rs new file mode 100644 index 0000000000..134aeb43a9 --- /dev/null +++ b/esp32p4/src/ahb_dma/out_int_clr_ch.rs @@ -0,0 +1,82 @@ +#[doc = "Register `OUT_INT_CLR_CH%s` writer"] +pub type W = crate::W; +#[doc = "Field `OUT_DONE_CH_INT_CLR` writer - Set this bit to clear the OUT_DONE_CH_INT interrupt."] +pub type OUT_DONE_CH_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_EOF_CH_INT_CLR` writer - Set this bit to clear the OUT_EOF_CH_INT interrupt."] +pub type OUT_EOF_CH_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_DSCR_ERR_CH_INT_CLR` writer - Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt."] +pub type OUT_DSCR_ERR_CH_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_TOTAL_EOF_CH_INT_CLR` writer - Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt."] +pub type OUT_TOTAL_EOF_CH_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_OVF_CH_INT_CLR` writer - Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt."] +pub type OUTFIFO_OVF_CH_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_UDF_CH_INT_CLR` writer - Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt."] +pub type OUTFIFO_UDF_CH_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Set this bit to clear the OUT_DONE_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn out_done_ch_int_clr(&mut self) -> OUT_DONE_CH_INT_CLR_W { + OUT_DONE_CH_INT_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - Set this bit to clear the OUT_EOF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn out_eof_ch_int_clr(&mut self) -> OUT_EOF_CH_INT_CLR_W { + OUT_EOF_CH_INT_CLR_W::new(self, 1) + } + #[doc = "Bit 2 - Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn out_dscr_err_ch_int_clr(&mut self) -> OUT_DSCR_ERR_CH_INT_CLR_W { + OUT_DSCR_ERR_CH_INT_CLR_W::new(self, 2) + } + #[doc = "Bit 3 - Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn out_total_eof_ch_int_clr(&mut self) -> OUT_TOTAL_EOF_CH_INT_CLR_W { + OUT_TOTAL_EOF_CH_INT_CLR_W::new(self, 3) + } + #[doc = "Bit 4 - Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn outfifo_ovf_ch_int_clr(&mut self) -> OUTFIFO_OVF_CH_INT_CLR_W { + OUTFIFO_OVF_CH_INT_CLR_W::new(self, 4) + } + #[doc = "Bit 5 - Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn outfifo_udf_ch_int_clr(&mut self) -> OUTFIFO_UDF_CH_INT_CLR_W { + OUTFIFO_UDF_CH_INT_CLR_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Interrupt clear bits of channel 0\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_int_clr_ch::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_INT_CLR_CH_SPEC; +impl crate::RegisterSpec for OUT_INT_CLR_CH_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`out_int_clr_ch::W`](W) writer structure"] +impl crate::Writable for OUT_INT_CLR_CH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_INT_CLR_CH%s to value 0"] +impl crate::Resettable for OUT_INT_CLR_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ahb_dma/out_int_ena_ch.rs b/esp32p4/src/ahb_dma/out_int_ena_ch.rs new file mode 100644 index 0000000000..183f6573de --- /dev/null +++ b/esp32p4/src/ahb_dma/out_int_ena_ch.rs @@ -0,0 +1,161 @@ +#[doc = "Register `OUT_INT_ENA_CH%s` reader"] +pub type R = crate::R; +#[doc = "Register `OUT_INT_ENA_CH%s` writer"] +pub type W = crate::W; +#[doc = "Field `OUT_DONE_CH_INT_ENA` reader - The interrupt enable bit for the OUT_DONE_CH_INT interrupt."] +pub type OUT_DONE_CH_INT_ENA_R = crate::BitReader; +#[doc = "Field `OUT_DONE_CH_INT_ENA` writer - The interrupt enable bit for the OUT_DONE_CH_INT interrupt."] +pub type OUT_DONE_CH_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_EOF_CH_INT_ENA` reader - The interrupt enable bit for the OUT_EOF_CH_INT interrupt."] +pub type OUT_EOF_CH_INT_ENA_R = crate::BitReader; +#[doc = "Field `OUT_EOF_CH_INT_ENA` writer - The interrupt enable bit for the OUT_EOF_CH_INT interrupt."] +pub type OUT_EOF_CH_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_DSCR_ERR_CH_INT_ENA` reader - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt."] +pub type OUT_DSCR_ERR_CH_INT_ENA_R = crate::BitReader; +#[doc = "Field `OUT_DSCR_ERR_CH_INT_ENA` writer - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt."] +pub type OUT_DSCR_ERR_CH_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_TOTAL_EOF_CH_INT_ENA` reader - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt."] +pub type OUT_TOTAL_EOF_CH_INT_ENA_R = crate::BitReader; +#[doc = "Field `OUT_TOTAL_EOF_CH_INT_ENA` writer - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt."] +pub type OUT_TOTAL_EOF_CH_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_OVF_CH_INT_ENA` reader - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] +pub type OUTFIFO_OVF_CH_INT_ENA_R = crate::BitReader; +#[doc = "Field `OUTFIFO_OVF_CH_INT_ENA` writer - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] +pub type OUTFIFO_OVF_CH_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_UDF_CH_INT_ENA` reader - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] +pub type OUTFIFO_UDF_CH_INT_ENA_R = crate::BitReader; +#[doc = "Field `OUTFIFO_UDF_CH_INT_ENA` writer - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] +pub type OUTFIFO_UDF_CH_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The interrupt enable bit for the OUT_DONE_CH_INT interrupt."] + #[inline(always)] + pub fn out_done_ch_int_ena(&self) -> OUT_DONE_CH_INT_ENA_R { + OUT_DONE_CH_INT_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The interrupt enable bit for the OUT_EOF_CH_INT interrupt."] + #[inline(always)] + pub fn out_eof_ch_int_ena(&self) -> OUT_EOF_CH_INT_ENA_R { + OUT_EOF_CH_INT_ENA_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt."] + #[inline(always)] + pub fn out_dscr_err_ch_int_ena(&self) -> OUT_DSCR_ERR_CH_INT_ENA_R { + OUT_DSCR_ERR_CH_INT_ENA_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt."] + #[inline(always)] + pub fn out_total_eof_ch_int_ena(&self) -> OUT_TOTAL_EOF_CH_INT_ENA_R { + OUT_TOTAL_EOF_CH_INT_ENA_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] + #[inline(always)] + pub fn outfifo_ovf_ch_int_ena(&self) -> OUTFIFO_OVF_CH_INT_ENA_R { + OUTFIFO_OVF_CH_INT_ENA_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] + #[inline(always)] + pub fn outfifo_udf_ch_int_ena(&self) -> OUTFIFO_UDF_CH_INT_ENA_R { + OUTFIFO_UDF_CH_INT_ENA_R::new(((self.bits >> 5) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_INT_ENA_CH") + .field( + "out_done_ch_int_ena", + &format_args!("{}", self.out_done_ch_int_ena().bit()), + ) + .field( + "out_eof_ch_int_ena", + &format_args!("{}", self.out_eof_ch_int_ena().bit()), + ) + .field( + "out_dscr_err_ch_int_ena", + &format_args!("{}", self.out_dscr_err_ch_int_ena().bit()), + ) + .field( + "out_total_eof_ch_int_ena", + &format_args!("{}", self.out_total_eof_ch_int_ena().bit()), + ) + .field( + "outfifo_ovf_ch_int_ena", + &format_args!("{}", self.outfifo_ovf_ch_int_ena().bit()), + ) + .field( + "outfifo_udf_ch_int_ena", + &format_args!("{}", self.outfifo_udf_ch_int_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The interrupt enable bit for the OUT_DONE_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn out_done_ch_int_ena(&mut self) -> OUT_DONE_CH_INT_ENA_W { + OUT_DONE_CH_INT_ENA_W::new(self, 0) + } + #[doc = "Bit 1 - The interrupt enable bit for the OUT_EOF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn out_eof_ch_int_ena(&mut self) -> OUT_EOF_CH_INT_ENA_W { + OUT_EOF_CH_INT_ENA_W::new(self, 1) + } + #[doc = "Bit 2 - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn out_dscr_err_ch_int_ena(&mut self) -> OUT_DSCR_ERR_CH_INT_ENA_W { + OUT_DSCR_ERR_CH_INT_ENA_W::new(self, 2) + } + #[doc = "Bit 3 - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn out_total_eof_ch_int_ena(&mut self) -> OUT_TOTAL_EOF_CH_INT_ENA_W { + OUT_TOTAL_EOF_CH_INT_ENA_W::new(self, 3) + } + #[doc = "Bit 4 - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn outfifo_ovf_ch_int_ena(&mut self) -> OUTFIFO_OVF_CH_INT_ENA_W { + OUTFIFO_OVF_CH_INT_ENA_W::new(self, 4) + } + #[doc = "Bit 5 - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn outfifo_udf_ch_int_ena(&mut self) -> OUTFIFO_UDF_CH_INT_ENA_W { + OUTFIFO_UDF_CH_INT_ENA_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Interrupt enable bits of channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_int_ena_ch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_int_ena_ch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_INT_ENA_CH_SPEC; +impl crate::RegisterSpec for OUT_INT_ENA_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_int_ena_ch::R`](R) reader structure"] +impl crate::Readable for OUT_INT_ENA_CH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out_int_ena_ch::W`](W) writer structure"] +impl crate::Writable for OUT_INT_ENA_CH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_INT_ENA_CH%s to value 0"] +impl crate::Resettable for OUT_INT_ENA_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ahb_dma/out_int_raw_ch.rs b/esp32p4/src/ahb_dma/out_int_raw_ch.rs new file mode 100644 index 0000000000..4616f2a755 --- /dev/null +++ b/esp32p4/src/ahb_dma/out_int_raw_ch.rs @@ -0,0 +1,161 @@ +#[doc = "Register `OUT_INT_RAW_CH%s` reader"] +pub type R = crate::R; +#[doc = "Register `OUT_INT_RAW_CH%s` writer"] +pub type W = crate::W; +#[doc = "Field `OUT_DONE_CH_INT_RAW` reader - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0."] +pub type OUT_DONE_CH_INT_RAW_R = crate::BitReader; +#[doc = "Field `OUT_DONE_CH_INT_RAW` writer - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0."] +pub type OUT_DONE_CH_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_EOF_CH_INT_RAW` reader - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0."] +pub type OUT_EOF_CH_INT_RAW_R = crate::BitReader; +#[doc = "Field `OUT_EOF_CH_INT_RAW` writer - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0."] +pub type OUT_EOF_CH_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_DSCR_ERR_CH_INT_RAW` reader - The raw interrupt bit turns to high level when detecting outlink descriptor error including owner error and the second and third word error of outlink descriptor for Tx channel 0."] +pub type OUT_DSCR_ERR_CH_INT_RAW_R = crate::BitReader; +#[doc = "Field `OUT_DSCR_ERR_CH_INT_RAW` writer - The raw interrupt bit turns to high level when detecting outlink descriptor error including owner error and the second and third word error of outlink descriptor for Tx channel 0."] +pub type OUT_DSCR_ERR_CH_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_TOTAL_EOF_CH_INT_RAW` reader - The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0."] +pub type OUT_TOTAL_EOF_CH_INT_RAW_R = crate::BitReader; +#[doc = "Field `OUT_TOTAL_EOF_CH_INT_RAW` writer - The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0."] +pub type OUT_TOTAL_EOF_CH_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_OVF_CH_INT_RAW` reader - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow."] +pub type OUTFIFO_OVF_CH_INT_RAW_R = crate::BitReader; +#[doc = "Field `OUTFIFO_OVF_CH_INT_RAW` writer - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow."] +pub type OUTFIFO_OVF_CH_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_UDF_CH_INT_RAW` reader - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow."] +pub type OUTFIFO_UDF_CH_INT_RAW_R = crate::BitReader; +#[doc = "Field `OUTFIFO_UDF_CH_INT_RAW` writer - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow."] +pub type OUTFIFO_UDF_CH_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0."] + #[inline(always)] + pub fn out_done_ch_int_raw(&self) -> OUT_DONE_CH_INT_RAW_R { + OUT_DONE_CH_INT_RAW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0."] + #[inline(always)] + pub fn out_eof_ch_int_raw(&self) -> OUT_EOF_CH_INT_RAW_R { + OUT_EOF_CH_INT_RAW_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The raw interrupt bit turns to high level when detecting outlink descriptor error including owner error and the second and third word error of outlink descriptor for Tx channel 0."] + #[inline(always)] + pub fn out_dscr_err_ch_int_raw(&self) -> OUT_DSCR_ERR_CH_INT_RAW_R { + OUT_DSCR_ERR_CH_INT_RAW_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0."] + #[inline(always)] + pub fn out_total_eof_ch_int_raw(&self) -> OUT_TOTAL_EOF_CH_INT_RAW_R { + OUT_TOTAL_EOF_CH_INT_RAW_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow."] + #[inline(always)] + pub fn outfifo_ovf_ch_int_raw(&self) -> OUTFIFO_OVF_CH_INT_RAW_R { + OUTFIFO_OVF_CH_INT_RAW_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow."] + #[inline(always)] + pub fn outfifo_udf_ch_int_raw(&self) -> OUTFIFO_UDF_CH_INT_RAW_R { + OUTFIFO_UDF_CH_INT_RAW_R::new(((self.bits >> 5) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_INT_RAW_CH") + .field( + "out_done_ch_int_raw", + &format_args!("{}", self.out_done_ch_int_raw().bit()), + ) + .field( + "out_eof_ch_int_raw", + &format_args!("{}", self.out_eof_ch_int_raw().bit()), + ) + .field( + "out_dscr_err_ch_int_raw", + &format_args!("{}", self.out_dscr_err_ch_int_raw().bit()), + ) + .field( + "out_total_eof_ch_int_raw", + &format_args!("{}", self.out_total_eof_ch_int_raw().bit()), + ) + .field( + "outfifo_ovf_ch_int_raw", + &format_args!("{}", self.outfifo_ovf_ch_int_raw().bit()), + ) + .field( + "outfifo_udf_ch_int_raw", + &format_args!("{}", self.outfifo_udf_ch_int_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0."] + #[inline(always)] + #[must_use] + pub fn out_done_ch_int_raw(&mut self) -> OUT_DONE_CH_INT_RAW_W { + OUT_DONE_CH_INT_RAW_W::new(self, 0) + } + #[doc = "Bit 1 - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0."] + #[inline(always)] + #[must_use] + pub fn out_eof_ch_int_raw(&mut self) -> OUT_EOF_CH_INT_RAW_W { + OUT_EOF_CH_INT_RAW_W::new(self, 1) + } + #[doc = "Bit 2 - The raw interrupt bit turns to high level when detecting outlink descriptor error including owner error and the second and third word error of outlink descriptor for Tx channel 0."] + #[inline(always)] + #[must_use] + pub fn out_dscr_err_ch_int_raw(&mut self) -> OUT_DSCR_ERR_CH_INT_RAW_W { + OUT_DSCR_ERR_CH_INT_RAW_W::new(self, 2) + } + #[doc = "Bit 3 - The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0."] + #[inline(always)] + #[must_use] + pub fn out_total_eof_ch_int_raw(&mut self) -> OUT_TOTAL_EOF_CH_INT_RAW_W { + OUT_TOTAL_EOF_CH_INT_RAW_W::new(self, 3) + } + #[doc = "Bit 4 - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow."] + #[inline(always)] + #[must_use] + pub fn outfifo_ovf_ch_int_raw(&mut self) -> OUTFIFO_OVF_CH_INT_RAW_W { + OUTFIFO_OVF_CH_INT_RAW_W::new(self, 4) + } + #[doc = "Bit 5 - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow."] + #[inline(always)] + #[must_use] + pub fn outfifo_udf_ch_int_raw(&mut self) -> OUTFIFO_UDF_CH_INT_RAW_W { + OUTFIFO_UDF_CH_INT_RAW_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Raw status interrupt of channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_int_raw_ch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_int_raw_ch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_INT_RAW_CH_SPEC; +impl crate::RegisterSpec for OUT_INT_RAW_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_int_raw_ch::R`](R) reader structure"] +impl crate::Readable for OUT_INT_RAW_CH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out_int_raw_ch::W`](W) writer structure"] +impl crate::Writable for OUT_INT_RAW_CH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_INT_RAW_CH%s to value 0"] +impl crate::Resettable for OUT_INT_RAW_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ahb_dma/out_int_st_ch.rs b/esp32p4/src/ahb_dma/out_int_st_ch.rs new file mode 100644 index 0000000000..9cc59561be --- /dev/null +++ b/esp32p4/src/ahb_dma/out_int_st_ch.rs @@ -0,0 +1,94 @@ +#[doc = "Register `OUT_INT_ST_CH%s` reader"] +pub type R = crate::R; +#[doc = "Field `OUT_DONE_CH_INT_ST` reader - The raw interrupt status bit for the OUT_DONE_CH_INT interrupt."] +pub type OUT_DONE_CH_INT_ST_R = crate::BitReader; +#[doc = "Field `OUT_EOF_CH_INT_ST` reader - The raw interrupt status bit for the OUT_EOF_CH_INT interrupt."] +pub type OUT_EOF_CH_INT_ST_R = crate::BitReader; +#[doc = "Field `OUT_DSCR_ERR_CH_INT_ST` reader - The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt."] +pub type OUT_DSCR_ERR_CH_INT_ST_R = crate::BitReader; +#[doc = "Field `OUT_TOTAL_EOF_CH_INT_ST` reader - The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt."] +pub type OUT_TOTAL_EOF_CH_INT_ST_R = crate::BitReader; +#[doc = "Field `OUTFIFO_OVF_CH_INT_ST` reader - The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] +pub type OUTFIFO_OVF_CH_INT_ST_R = crate::BitReader; +#[doc = "Field `OUTFIFO_UDF_CH_INT_ST` reader - The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] +pub type OUTFIFO_UDF_CH_INT_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - The raw interrupt status bit for the OUT_DONE_CH_INT interrupt."] + #[inline(always)] + pub fn out_done_ch_int_st(&self) -> OUT_DONE_CH_INT_ST_R { + OUT_DONE_CH_INT_ST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The raw interrupt status bit for the OUT_EOF_CH_INT interrupt."] + #[inline(always)] + pub fn out_eof_ch_int_st(&self) -> OUT_EOF_CH_INT_ST_R { + OUT_EOF_CH_INT_ST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt."] + #[inline(always)] + pub fn out_dscr_err_ch_int_st(&self) -> OUT_DSCR_ERR_CH_INT_ST_R { + OUT_DSCR_ERR_CH_INT_ST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt."] + #[inline(always)] + pub fn out_total_eof_ch_int_st(&self) -> OUT_TOTAL_EOF_CH_INT_ST_R { + OUT_TOTAL_EOF_CH_INT_ST_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] + #[inline(always)] + pub fn outfifo_ovf_ch_int_st(&self) -> OUTFIFO_OVF_CH_INT_ST_R { + OUTFIFO_OVF_CH_INT_ST_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] + #[inline(always)] + pub fn outfifo_udf_ch_int_st(&self) -> OUTFIFO_UDF_CH_INT_ST_R { + OUTFIFO_UDF_CH_INT_ST_R::new(((self.bits >> 5) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_INT_ST_CH") + .field( + "out_done_ch_int_st", + &format_args!("{}", self.out_done_ch_int_st().bit()), + ) + .field( + "out_eof_ch_int_st", + &format_args!("{}", self.out_eof_ch_int_st().bit()), + ) + .field( + "out_dscr_err_ch_int_st", + &format_args!("{}", self.out_dscr_err_ch_int_st().bit()), + ) + .field( + "out_total_eof_ch_int_st", + &format_args!("{}", self.out_total_eof_ch_int_st().bit()), + ) + .field( + "outfifo_ovf_ch_int_st", + &format_args!("{}", self.outfifo_ovf_ch_int_st().bit()), + ) + .field( + "outfifo_udf_ch_int_st", + &format_args!("{}", self.outfifo_udf_ch_int_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Masked interrupt of channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_int_st_ch::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_INT_ST_CH_SPEC; +impl crate::RegisterSpec for OUT_INT_ST_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_int_st_ch::R`](R) reader structure"] +impl crate::Readable for OUT_INT_ST_CH_SPEC {} +#[doc = "`reset()` method sets OUT_INT_ST_CH%s to value 0"] +impl crate::Resettable for OUT_INT_ST_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ahb_dma/out_link_addr_ch.rs b/esp32p4/src/ahb_dma/out_link_addr_ch.rs new file mode 100644 index 0000000000..6fa6ace560 --- /dev/null +++ b/esp32p4/src/ahb_dma/out_link_addr_ch.rs @@ -0,0 +1,66 @@ +#[doc = "Register `OUT_LINK_ADDR_CH%s` reader"] +pub type R = crate::R; +#[doc = "Register `OUT_LINK_ADDR_CH%s` writer"] +pub type W = crate::W; +#[doc = "Field `OUTLINK_ADDR_CH` reader - This register stores the 32 least significant bits of the first outlink descriptor's address."] +pub type OUTLINK_ADDR_CH_R = crate::FieldReader; +#[doc = "Field `OUTLINK_ADDR_CH` writer - This register stores the 32 least significant bits of the first outlink descriptor's address."] +pub type OUTLINK_ADDR_CH_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - This register stores the 32 least significant bits of the first outlink descriptor's address."] + #[inline(always)] + pub fn outlink_addr_ch(&self) -> OUTLINK_ADDR_CH_R { + OUTLINK_ADDR_CH_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_LINK_ADDR_CH") + .field( + "outlink_addr_ch", + &format_args!("{}", self.outlink_addr_ch().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - This register stores the 32 least significant bits of the first outlink descriptor's address."] + #[inline(always)] + #[must_use] + pub fn outlink_addr_ch(&mut self) -> OUTLINK_ADDR_CH_W { + OUTLINK_ADDR_CH_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Link descriptor configure of Tx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_link_addr_ch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_link_addr_ch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_LINK_ADDR_CH_SPEC; +impl crate::RegisterSpec for OUT_LINK_ADDR_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_link_addr_ch::R`](R) reader structure"] +impl crate::Readable for OUT_LINK_ADDR_CH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out_link_addr_ch::W`](W) writer structure"] +impl crate::Writable for OUT_LINK_ADDR_CH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_LINK_ADDR_CH%s to value 0"] +impl crate::Resettable for OUT_LINK_ADDR_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ahb_dma/out_link_ch.rs b/esp32p4/src/ahb_dma/out_link_ch.rs new file mode 100644 index 0000000000..8fd8fcd7d0 --- /dev/null +++ b/esp32p4/src/ahb_dma/out_link_ch.rs @@ -0,0 +1,82 @@ +#[doc = "Register `OUT_LINK_CH%s` reader"] +pub type R = crate::R; +#[doc = "Register `OUT_LINK_CH%s` writer"] +pub type W = crate::W; +#[doc = "Field `OUTLINK_STOP_CH` writer - Set this bit to stop dealing with the outlink descriptors."] +pub type OUTLINK_STOP_CH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTLINK_START_CH` writer - Set this bit to start dealing with the outlink descriptors."] +pub type OUTLINK_START_CH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTLINK_RESTART_CH` writer - Set this bit to restart a new outlink from the last address."] +pub type OUTLINK_RESTART_CH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTLINK_PARK_CH` reader - 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working."] +pub type OUTLINK_PARK_CH_R = crate::BitReader; +impl R { + #[doc = "Bit 3 - 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working."] + #[inline(always)] + pub fn outlink_park_ch(&self) -> OUTLINK_PARK_CH_R { + OUTLINK_PARK_CH_R::new(((self.bits >> 3) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_LINK_CH") + .field( + "outlink_park_ch", + &format_args!("{}", self.outlink_park_ch().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Set this bit to stop dealing with the outlink descriptors."] + #[inline(always)] + #[must_use] + pub fn outlink_stop_ch(&mut self) -> OUTLINK_STOP_CH_W { + OUTLINK_STOP_CH_W::new(self, 0) + } + #[doc = "Bit 1 - Set this bit to start dealing with the outlink descriptors."] + #[inline(always)] + #[must_use] + pub fn outlink_start_ch(&mut self) -> OUTLINK_START_CH_W { + OUTLINK_START_CH_W::new(self, 1) + } + #[doc = "Bit 2 - Set this bit to restart a new outlink from the last address."] + #[inline(always)] + #[must_use] + pub fn outlink_restart_ch(&mut self) -> OUTLINK_RESTART_CH_W { + OUTLINK_RESTART_CH_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Link descriptor configure and control register of Tx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_link_ch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_link_ch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_LINK_CH_SPEC; +impl crate::RegisterSpec for OUT_LINK_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_link_ch::R`](R) reader structure"] +impl crate::Readable for OUT_LINK_CH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out_link_ch::W`](W) writer structure"] +impl crate::Writable for OUT_LINK_CH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_LINK_CH%s to value 0x08"] +impl crate::Resettable for OUT_LINK_CH_SPEC { + const RESET_VALUE: Self::Ux = 0x08; +} diff --git a/esp32p4/src/ahb_dma/out_peri_sel_ch.rs b/esp32p4/src/ahb_dma/out_peri_sel_ch.rs new file mode 100644 index 0000000000..0f6930918c --- /dev/null +++ b/esp32p4/src/ahb_dma/out_peri_sel_ch.rs @@ -0,0 +1,66 @@ +#[doc = "Register `OUT_PERI_SEL_CH%s` reader"] +pub type R = crate::R; +#[doc = "Register `OUT_PERI_SEL_CH%s` writer"] +pub type W = crate::W; +#[doc = "Field `PERI_OUT_SEL_CH` reader - This register is used to select peripheral for Tx channel 0. I3C. 1: Dummy. 2: UHCI0. 3: I2S0. 4: I2S1. 5: I2S2. 6: Dummy. 7: Dummy. 8: ADC_DAC. 9: Dummy. 10: RMT,11~15: Dummy"] +pub type PERI_OUT_SEL_CH_R = crate::FieldReader; +#[doc = "Field `PERI_OUT_SEL_CH` writer - This register is used to select peripheral for Tx channel 0. I3C. 1: Dummy. 2: UHCI0. 3: I2S0. 4: I2S1. 5: I2S2. 6: Dummy. 7: Dummy. 8: ADC_DAC. 9: Dummy. 10: RMT,11~15: Dummy"] +pub type PERI_OUT_SEL_CH_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - This register is used to select peripheral for Tx channel 0. I3C. 1: Dummy. 2: UHCI0. 3: I2S0. 4: I2S1. 5: I2S2. 6: Dummy. 7: Dummy. 8: ADC_DAC. 9: Dummy. 10: RMT,11~15: Dummy"] + #[inline(always)] + pub fn peri_out_sel_ch(&self) -> PERI_OUT_SEL_CH_R { + PERI_OUT_SEL_CH_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_PERI_SEL_CH") + .field( + "peri_out_sel_ch", + &format_args!("{}", self.peri_out_sel_ch().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - This register is used to select peripheral for Tx channel 0. I3C. 1: Dummy. 2: UHCI0. 3: I2S0. 4: I2S1. 5: I2S2. 6: Dummy. 7: Dummy. 8: ADC_DAC. 9: Dummy. 10: RMT,11~15: Dummy"] + #[inline(always)] + #[must_use] + pub fn peri_out_sel_ch(&mut self) -> PERI_OUT_SEL_CH_W { + PERI_OUT_SEL_CH_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Peripheral selection of Tx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_peri_sel_ch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_peri_sel_ch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_PERI_SEL_CH_SPEC; +impl crate::RegisterSpec for OUT_PERI_SEL_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_peri_sel_ch::R`](R) reader structure"] +impl crate::Readable for OUT_PERI_SEL_CH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out_peri_sel_ch::W`](W) writer structure"] +impl crate::Writable for OUT_PERI_SEL_CH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_PERI_SEL_CH%s to value 0x3f"] +impl crate::Resettable for OUT_PERI_SEL_CH_SPEC { + const RESET_VALUE: Self::Ux = 0x3f; +} diff --git a/esp32p4/src/ahb_dma/out_pri_ch.rs b/esp32p4/src/ahb_dma/out_pri_ch.rs new file mode 100644 index 0000000000..70be4a7371 --- /dev/null +++ b/esp32p4/src/ahb_dma/out_pri_ch.rs @@ -0,0 +1,63 @@ +#[doc = "Register `OUT_PRI_CH%s` reader"] +pub type R = crate::R; +#[doc = "Register `OUT_PRI_CH%s` writer"] +pub type W = crate::W; +#[doc = "Field `TX_PRI_CH` reader - The priority of Tx channel 0. The larger of the value the higher of the priority."] +pub type TX_PRI_CH_R = crate::FieldReader; +#[doc = "Field `TX_PRI_CH` writer - The priority of Tx channel 0. The larger of the value the higher of the priority."] +pub type TX_PRI_CH_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - The priority of Tx channel 0. The larger of the value the higher of the priority."] + #[inline(always)] + pub fn tx_pri_ch(&self) -> TX_PRI_CH_R { + TX_PRI_CH_R::new((self.bits & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_PRI_CH") + .field("tx_pri_ch", &format_args!("{}", self.tx_pri_ch().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:3 - The priority of Tx channel 0. The larger of the value the higher of the priority."] + #[inline(always)] + #[must_use] + pub fn tx_pri_ch(&mut self) -> TX_PRI_CH_W { + TX_PRI_CH_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Priority register of Tx channel 0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_pri_ch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_pri_ch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_PRI_CH_SPEC; +impl crate::RegisterSpec for OUT_PRI_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_pri_ch::R`](R) reader structure"] +impl crate::Readable for OUT_PRI_CH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out_pri_ch::W`](W) writer structure"] +impl crate::Writable for OUT_PRI_CH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_PRI_CH%s to value 0"] +impl crate::Resettable for OUT_PRI_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ahb_dma/out_push_ch.rs b/esp32p4/src/ahb_dma/out_push_ch.rs new file mode 100644 index 0000000000..18563b9096 --- /dev/null +++ b/esp32p4/src/ahb_dma/out_push_ch.rs @@ -0,0 +1,74 @@ +#[doc = "Register `OUT_PUSH_CH%s` reader"] +pub type R = crate::R; +#[doc = "Register `OUT_PUSH_CH%s` writer"] +pub type W = crate::W; +#[doc = "Field `OUTFIFO_WDATA_CH` reader - This register stores the data that need to be pushed into AHB_DMA FIFO."] +pub type OUTFIFO_WDATA_CH_R = crate::FieldReader; +#[doc = "Field `OUTFIFO_WDATA_CH` writer - This register stores the data that need to be pushed into AHB_DMA FIFO."] +pub type OUTFIFO_WDATA_CH_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; +#[doc = "Field `OUTFIFO_PUSH_CH` writer - Set this bit to push data into AHB_DMA FIFO."] +pub type OUTFIFO_PUSH_CH_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:8 - This register stores the data that need to be pushed into AHB_DMA FIFO."] + #[inline(always)] + pub fn outfifo_wdata_ch(&self) -> OUTFIFO_WDATA_CH_R { + OUTFIFO_WDATA_CH_R::new((self.bits & 0x01ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_PUSH_CH") + .field( + "outfifo_wdata_ch", + &format_args!("{}", self.outfifo_wdata_ch().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:8 - This register stores the data that need to be pushed into AHB_DMA FIFO."] + #[inline(always)] + #[must_use] + pub fn outfifo_wdata_ch(&mut self) -> OUTFIFO_WDATA_CH_W { + OUTFIFO_WDATA_CH_W::new(self, 0) + } + #[doc = "Bit 9 - Set this bit to push data into AHB_DMA FIFO."] + #[inline(always)] + #[must_use] + pub fn outfifo_push_ch(&mut self) -> OUTFIFO_PUSH_CH_W { + OUTFIFO_PUSH_CH_W::new(self, 9) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Push control register of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_push_ch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_push_ch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_PUSH_CH_SPEC; +impl crate::RegisterSpec for OUT_PUSH_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_push_ch::R`](R) reader structure"] +impl crate::Readable for OUT_PUSH_CH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out_push_ch::W`](W) writer structure"] +impl crate::Writable for OUT_PUSH_CH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_PUSH_CH%s to value 0"] +impl crate::Resettable for OUT_PUSH_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ahb_dma/out_state_ch.rs b/esp32p4/src/ahb_dma/out_state_ch.rs new file mode 100644 index 0000000000..26078b0fc1 --- /dev/null +++ b/esp32p4/src/ahb_dma/out_state_ch.rs @@ -0,0 +1,61 @@ +#[doc = "Register `OUT_STATE_CH%s` reader"] +pub type R = crate::R; +#[doc = "Field `OUTLINK_DSCR_ADDR_CH` reader - This register stores the current outlink descriptor's address."] +pub type OUTLINK_DSCR_ADDR_CH_R = crate::FieldReader; +#[doc = "Field `OUT_DSCR_STATE_CH` reader - reserved"] +pub type OUT_DSCR_STATE_CH_R = crate::FieldReader; +#[doc = "Field `OUT_STATE_CH` reader - reserved"] +pub type OUT_STATE_CH_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:17 - This register stores the current outlink descriptor's address."] + #[inline(always)] + pub fn outlink_dscr_addr_ch(&self) -> OUTLINK_DSCR_ADDR_CH_R { + OUTLINK_DSCR_ADDR_CH_R::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:19 - reserved"] + #[inline(always)] + pub fn out_dscr_state_ch(&self) -> OUT_DSCR_STATE_CH_R { + OUT_DSCR_STATE_CH_R::new(((self.bits >> 18) & 3) as u8) + } + #[doc = "Bits 20:22 - reserved"] + #[inline(always)] + pub fn out_state_ch(&self) -> OUT_STATE_CH_R { + OUT_STATE_CH_R::new(((self.bits >> 20) & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_STATE_CH") + .field( + "outlink_dscr_addr_ch", + &format_args!("{}", self.outlink_dscr_addr_ch().bits()), + ) + .field( + "out_dscr_state_ch", + &format_args!("{}", self.out_dscr_state_ch().bits()), + ) + .field( + "out_state_ch", + &format_args!("{}", self.out_state_ch().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Transmit status of Tx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_state_ch::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_STATE_CH_SPEC; +impl crate::RegisterSpec for OUT_STATE_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_state_ch::R`](R) reader structure"] +impl crate::Readable for OUT_STATE_CH_SPEC {} +#[doc = "`reset()` method sets OUT_STATE_CH%s to value 0"] +impl crate::Resettable for OUT_STATE_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ahb_dma/outfifo_status_ch.rs b/esp32p4/src/ahb_dma/outfifo_status_ch.rs new file mode 100644 index 0000000000..a1d7900330 --- /dev/null +++ b/esp32p4/src/ahb_dma/outfifo_status_ch.rs @@ -0,0 +1,105 @@ +#[doc = "Register `OUTFIFO_STATUS_CH%s` reader"] +pub type R = crate::R; +#[doc = "Field `OUTFIFO_FULL_CH` reader - L1 Tx FIFO full signal for Tx channel 0."] +pub type OUTFIFO_FULL_CH_R = crate::BitReader; +#[doc = "Field `OUTFIFO_EMPTY_CH` reader - L1 Tx FIFO empty signal for Tx channel 0."] +pub type OUTFIFO_EMPTY_CH_R = crate::BitReader; +#[doc = "Field `OUTFIFO_CNT_CH` reader - The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0."] +pub type OUTFIFO_CNT_CH_R = crate::FieldReader; +#[doc = "Field `OUT_REMAIN_UNDER_1B_CH` reader - reserved"] +pub type OUT_REMAIN_UNDER_1B_CH_R = crate::BitReader; +#[doc = "Field `OUT_REMAIN_UNDER_2B_CH` reader - reserved"] +pub type OUT_REMAIN_UNDER_2B_CH_R = crate::BitReader; +#[doc = "Field `OUT_REMAIN_UNDER_3B_CH` reader - reserved"] +pub type OUT_REMAIN_UNDER_3B_CH_R = crate::BitReader; +#[doc = "Field `OUT_REMAIN_UNDER_4B_CH` reader - reserved"] +pub type OUT_REMAIN_UNDER_4B_CH_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - L1 Tx FIFO full signal for Tx channel 0."] + #[inline(always)] + pub fn outfifo_full_ch(&self) -> OUTFIFO_FULL_CH_R { + OUTFIFO_FULL_CH_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - L1 Tx FIFO empty signal for Tx channel 0."] + #[inline(always)] + pub fn outfifo_empty_ch(&self) -> OUTFIFO_EMPTY_CH_R { + OUTFIFO_EMPTY_CH_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:7 - The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0."] + #[inline(always)] + pub fn outfifo_cnt_ch(&self) -> OUTFIFO_CNT_CH_R { + OUTFIFO_CNT_CH_R::new(((self.bits >> 2) & 0x3f) as u8) + } + #[doc = "Bit 23 - reserved"] + #[inline(always)] + pub fn out_remain_under_1b_ch(&self) -> OUT_REMAIN_UNDER_1B_CH_R { + OUT_REMAIN_UNDER_1B_CH_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - reserved"] + #[inline(always)] + pub fn out_remain_under_2b_ch(&self) -> OUT_REMAIN_UNDER_2B_CH_R { + OUT_REMAIN_UNDER_2B_CH_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - reserved"] + #[inline(always)] + pub fn out_remain_under_3b_ch(&self) -> OUT_REMAIN_UNDER_3B_CH_R { + OUT_REMAIN_UNDER_3B_CH_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - reserved"] + #[inline(always)] + pub fn out_remain_under_4b_ch(&self) -> OUT_REMAIN_UNDER_4B_CH_R { + OUT_REMAIN_UNDER_4B_CH_R::new(((self.bits >> 26) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUTFIFO_STATUS_CH") + .field( + "outfifo_full_ch", + &format_args!("{}", self.outfifo_full_ch().bit()), + ) + .field( + "outfifo_empty_ch", + &format_args!("{}", self.outfifo_empty_ch().bit()), + ) + .field( + "outfifo_cnt_ch", + &format_args!("{}", self.outfifo_cnt_ch().bits()), + ) + .field( + "out_remain_under_1b_ch", + &format_args!("{}", self.out_remain_under_1b_ch().bit()), + ) + .field( + "out_remain_under_2b_ch", + &format_args!("{}", self.out_remain_under_2b_ch().bit()), + ) + .field( + "out_remain_under_3b_ch", + &format_args!("{}", self.out_remain_under_3b_ch().bit()), + ) + .field( + "out_remain_under_4b_ch", + &format_args!("{}", self.out_remain_under_4b_ch().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Transmit FIFO status of Tx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`outfifo_status_ch::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUTFIFO_STATUS_CH_SPEC; +impl crate::RegisterSpec for OUTFIFO_STATUS_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`outfifo_status_ch::R`](R) reader structure"] +impl crate::Readable for OUTFIFO_STATUS_CH_SPEC {} +#[doc = "`reset()` method sets OUTFIFO_STATUS_CH%s to value 0x0780_0002"] +impl crate::Resettable for OUTFIFO_STATUS_CH_SPEC { + const RESET_VALUE: Self::Ux = 0x0780_0002; +} diff --git a/esp32p4/src/ahb_dma/rx_arb_weigh_opt_dir_ch.rs b/esp32p4/src/ahb_dma/rx_arb_weigh_opt_dir_ch.rs new file mode 100644 index 0000000000..4d38112ae6 --- /dev/null +++ b/esp32p4/src/ahb_dma/rx_arb_weigh_opt_dir_ch.rs @@ -0,0 +1,68 @@ +#[doc = "Register `RX_ARB_WEIGH_OPT_DIR_CH%s` reader"] +pub type R = crate::R; +#[doc = "Register `RX_ARB_WEIGH_OPT_DIR_CH%s` writer"] +pub type W = crate::W; +#[doc = "Field `RX_ARB_WEIGH_OPT_DIR_CH` reader - reserved"] +pub type RX_ARB_WEIGH_OPT_DIR_CH_R = crate::BitReader; +#[doc = "Field `RX_ARB_WEIGH_OPT_DIR_CH` writer - reserved"] +pub type RX_ARB_WEIGH_OPT_DIR_CH_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - reserved"] + #[inline(always)] + pub fn rx_arb_weigh_opt_dir_ch(&self) -> RX_ARB_WEIGH_OPT_DIR_CH_R { + RX_ARB_WEIGH_OPT_DIR_CH_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RX_ARB_WEIGH_OPT_DIR_CH") + .field( + "rx_arb_weigh_opt_dir_ch", + &format_args!("{}", self.rx_arb_weigh_opt_dir_ch().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - reserved"] + #[inline(always)] + #[must_use] + pub fn rx_arb_weigh_opt_dir_ch( + &mut self, + ) -> RX_ARB_WEIGH_OPT_DIR_CH_W { + RX_ARB_WEIGH_OPT_DIR_CH_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "This register is used to config off or on weigh optimization\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_arb_weigh_opt_dir_ch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_arb_weigh_opt_dir_ch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RX_ARB_WEIGH_OPT_DIR_CH_SPEC; +impl crate::RegisterSpec for RX_ARB_WEIGH_OPT_DIR_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rx_arb_weigh_opt_dir_ch::R`](R) reader structure"] +impl crate::Readable for RX_ARB_WEIGH_OPT_DIR_CH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rx_arb_weigh_opt_dir_ch::W`](W) writer structure"] +impl crate::Writable for RX_ARB_WEIGH_OPT_DIR_CH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RX_ARB_WEIGH_OPT_DIR_CH%s to value 0"] +impl crate::Resettable for RX_ARB_WEIGH_OPT_DIR_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ahb_dma/rx_ch_arb_weigh_ch.rs b/esp32p4/src/ahb_dma/rx_ch_arb_weigh_ch.rs new file mode 100644 index 0000000000..953d9ab62d --- /dev/null +++ b/esp32p4/src/ahb_dma/rx_ch_arb_weigh_ch.rs @@ -0,0 +1,66 @@ +#[doc = "Register `RX_CH_ARB_WEIGH_CH%s` reader"] +pub type R = crate::R; +#[doc = "Register `RX_CH_ARB_WEIGH_CH%s` writer"] +pub type W = crate::W; +#[doc = "Field `RX_CH_ARB_WEIGH_CH` reader - reserved"] +pub type RX_CH_ARB_WEIGH_CH_R = crate::FieldReader; +#[doc = "Field `RX_CH_ARB_WEIGH_CH` writer - reserved"] +pub type RX_CH_ARB_WEIGH_CH_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - reserved"] + #[inline(always)] + pub fn rx_ch_arb_weigh_ch(&self) -> RX_CH_ARB_WEIGH_CH_R { + RX_CH_ARB_WEIGH_CH_R::new((self.bits & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RX_CH_ARB_WEIGH_CH") + .field( + "rx_ch_arb_weigh_ch", + &format_args!("{}", self.rx_ch_arb_weigh_ch().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:3 - reserved"] + #[inline(always)] + #[must_use] + pub fn rx_ch_arb_weigh_ch(&mut self) -> RX_CH_ARB_WEIGH_CH_W { + RX_CH_ARB_WEIGH_CH_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "This register is used to config ch0 arbiter weigh\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_ch_arb_weigh_ch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_ch_arb_weigh_ch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RX_CH_ARB_WEIGH_CH_SPEC; +impl crate::RegisterSpec for RX_CH_ARB_WEIGH_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rx_ch_arb_weigh_ch::R`](R) reader structure"] +impl crate::Readable for RX_CH_ARB_WEIGH_CH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rx_ch_arb_weigh_ch::W`](W) writer structure"] +impl crate::Writable for RX_CH_ARB_WEIGH_CH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RX_CH_ARB_WEIGH_CH%s to value 0"] +impl crate::Resettable for RX_CH_ARB_WEIGH_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ahb_dma/rx_crc_data_en_addr_ch.rs b/esp32p4/src/ahb_dma/rx_crc_data_en_addr_ch.rs new file mode 100644 index 0000000000..fbd6131eee --- /dev/null +++ b/esp32p4/src/ahb_dma/rx_crc_data_en_addr_ch.rs @@ -0,0 +1,68 @@ +#[doc = "Register `RX_CRC_DATA_EN_ADDR_CH%s` reader"] +pub type R = crate::R; +#[doc = "Register `RX_CRC_DATA_EN_ADDR_CH%s` writer"] +pub type W = crate::W; +#[doc = "Field `RX_CRC_DATA_EN_ADDR_CH` reader - reserved"] +pub type RX_CRC_DATA_EN_ADDR_CH_R = crate::FieldReader; +#[doc = "Field `RX_CRC_DATA_EN_ADDR_CH` writer - reserved"] +pub type RX_CRC_DATA_EN_ADDR_CH_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - reserved"] + #[inline(always)] + pub fn rx_crc_data_en_addr_ch(&self) -> RX_CRC_DATA_EN_ADDR_CH_R { + RX_CRC_DATA_EN_ADDR_CH_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RX_CRC_DATA_EN_ADDR_CH") + .field( + "rx_crc_data_en_addr_ch", + &format_args!("{}", self.rx_crc_data_en_addr_ch().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - reserved"] + #[inline(always)] + #[must_use] + pub fn rx_crc_data_en_addr_ch( + &mut self, + ) -> RX_CRC_DATA_EN_ADDR_CH_W { + RX_CRC_DATA_EN_ADDR_CH_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "This register is used to config addr of crc data_8bit en\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_crc_data_en_addr_ch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_crc_data_en_addr_ch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RX_CRC_DATA_EN_ADDR_CH_SPEC; +impl crate::RegisterSpec for RX_CRC_DATA_EN_ADDR_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rx_crc_data_en_addr_ch::R`](R) reader structure"] +impl crate::Readable for RX_CRC_DATA_EN_ADDR_CH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rx_crc_data_en_addr_ch::W`](W) writer structure"] +impl crate::Writable for RX_CRC_DATA_EN_ADDR_CH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RX_CRC_DATA_EN_ADDR_CH%s to value 0"] +impl crate::Resettable for RX_CRC_DATA_EN_ADDR_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ahb_dma/rx_crc_data_en_wr_data_ch.rs b/esp32p4/src/ahb_dma/rx_crc_data_en_wr_data_ch.rs new file mode 100644 index 0000000000..70762159f8 --- /dev/null +++ b/esp32p4/src/ahb_dma/rx_crc_data_en_wr_data_ch.rs @@ -0,0 +1,68 @@ +#[doc = "Register `RX_CRC_DATA_EN_WR_DATA_CH%s` reader"] +pub type R = crate::R; +#[doc = "Register `RX_CRC_DATA_EN_WR_DATA_CH%s` writer"] +pub type W = crate::W; +#[doc = "Field `RX_CRC_DATA_EN_WR_DATA_CH` reader - reserved"] +pub type RX_CRC_DATA_EN_WR_DATA_CH_R = crate::FieldReader; +#[doc = "Field `RX_CRC_DATA_EN_WR_DATA_CH` writer - reserved"] +pub type RX_CRC_DATA_EN_WR_DATA_CH_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - reserved"] + #[inline(always)] + pub fn rx_crc_data_en_wr_data_ch(&self) -> RX_CRC_DATA_EN_WR_DATA_CH_R { + RX_CRC_DATA_EN_WR_DATA_CH_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RX_CRC_DATA_EN_WR_DATA_CH") + .field( + "rx_crc_data_en_wr_data_ch", + &format_args!("{}", self.rx_crc_data_en_wr_data_ch().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - reserved"] + #[inline(always)] + #[must_use] + pub fn rx_crc_data_en_wr_data_ch( + &mut self, + ) -> RX_CRC_DATA_EN_WR_DATA_CH_W { + RX_CRC_DATA_EN_WR_DATA_CH_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "This register is used to config crc data_8bit en\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_crc_data_en_wr_data_ch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_crc_data_en_wr_data_ch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RX_CRC_DATA_EN_WR_DATA_CH_SPEC; +impl crate::RegisterSpec for RX_CRC_DATA_EN_WR_DATA_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rx_crc_data_en_wr_data_ch::R`](R) reader structure"] +impl crate::Readable for RX_CRC_DATA_EN_WR_DATA_CH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rx_crc_data_en_wr_data_ch::W`](W) writer structure"] +impl crate::Writable for RX_CRC_DATA_EN_WR_DATA_CH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RX_CRC_DATA_EN_WR_DATA_CH%s to value 0"] +impl crate::Resettable for RX_CRC_DATA_EN_WR_DATA_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ahb_dma/rx_crc_en_addr_ch.rs b/esp32p4/src/ahb_dma/rx_crc_en_addr_ch.rs new file mode 100644 index 0000000000..d37b045934 --- /dev/null +++ b/esp32p4/src/ahb_dma/rx_crc_en_addr_ch.rs @@ -0,0 +1,66 @@ +#[doc = "Register `RX_CRC_EN_ADDR_CH%s` reader"] +pub type R = crate::R; +#[doc = "Register `RX_CRC_EN_ADDR_CH%s` writer"] +pub type W = crate::W; +#[doc = "Field `RX_CRC_EN_ADDR_CH` reader - reserved"] +pub type RX_CRC_EN_ADDR_CH_R = crate::FieldReader; +#[doc = "Field `RX_CRC_EN_ADDR_CH` writer - reserved"] +pub type RX_CRC_EN_ADDR_CH_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - reserved"] + #[inline(always)] + pub fn rx_crc_en_addr_ch(&self) -> RX_CRC_EN_ADDR_CH_R { + RX_CRC_EN_ADDR_CH_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RX_CRC_EN_ADDR_CH") + .field( + "rx_crc_en_addr_ch", + &format_args!("{}", self.rx_crc_en_addr_ch().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - reserved"] + #[inline(always)] + #[must_use] + pub fn rx_crc_en_addr_ch(&mut self) -> RX_CRC_EN_ADDR_CH_W { + RX_CRC_EN_ADDR_CH_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "This register is used to config ch0 crc en addr\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_crc_en_addr_ch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_crc_en_addr_ch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RX_CRC_EN_ADDR_CH_SPEC; +impl crate::RegisterSpec for RX_CRC_EN_ADDR_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rx_crc_en_addr_ch::R`](R) reader structure"] +impl crate::Readable for RX_CRC_EN_ADDR_CH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rx_crc_en_addr_ch::W`](W) writer structure"] +impl crate::Writable for RX_CRC_EN_ADDR_CH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RX_CRC_EN_ADDR_CH%s to value 0"] +impl crate::Resettable for RX_CRC_EN_ADDR_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ahb_dma/rx_crc_en_wr_data_ch.rs b/esp32p4/src/ahb_dma/rx_crc_en_wr_data_ch.rs new file mode 100644 index 0000000000..cba96b2e45 --- /dev/null +++ b/esp32p4/src/ahb_dma/rx_crc_en_wr_data_ch.rs @@ -0,0 +1,66 @@ +#[doc = "Register `RX_CRC_EN_WR_DATA_CH%s` reader"] +pub type R = crate::R; +#[doc = "Register `RX_CRC_EN_WR_DATA_CH%s` writer"] +pub type W = crate::W; +#[doc = "Field `RX_CRC_EN_WR_DATA_CH` reader - This register is used to enable rx ch0 crc 32bit on/off"] +pub type RX_CRC_EN_WR_DATA_CH_R = crate::FieldReader; +#[doc = "Field `RX_CRC_EN_WR_DATA_CH` writer - This register is used to enable rx ch0 crc 32bit on/off"] +pub type RX_CRC_EN_WR_DATA_CH_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - This register is used to enable rx ch0 crc 32bit on/off"] + #[inline(always)] + pub fn rx_crc_en_wr_data_ch(&self) -> RX_CRC_EN_WR_DATA_CH_R { + RX_CRC_EN_WR_DATA_CH_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RX_CRC_EN_WR_DATA_CH") + .field( + "rx_crc_en_wr_data_ch", + &format_args!("{}", self.rx_crc_en_wr_data_ch().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - This register is used to enable rx ch0 crc 32bit on/off"] + #[inline(always)] + #[must_use] + pub fn rx_crc_en_wr_data_ch(&mut self) -> RX_CRC_EN_WR_DATA_CH_W { + RX_CRC_EN_WR_DATA_CH_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "This resister is used to config ch0 crc en for every bit\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_crc_en_wr_data_ch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_crc_en_wr_data_ch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RX_CRC_EN_WR_DATA_CH_SPEC; +impl crate::RegisterSpec for RX_CRC_EN_WR_DATA_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rx_crc_en_wr_data_ch::R`](R) reader structure"] +impl crate::Readable for RX_CRC_EN_WR_DATA_CH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rx_crc_en_wr_data_ch::W`](W) writer structure"] +impl crate::Writable for RX_CRC_EN_WR_DATA_CH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RX_CRC_EN_WR_DATA_CH%s to value 0"] +impl crate::Resettable for RX_CRC_EN_WR_DATA_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ahb_dma/rx_crc_width_ch.rs b/esp32p4/src/ahb_dma/rx_crc_width_ch.rs new file mode 100644 index 0000000000..bae11f4183 --- /dev/null +++ b/esp32p4/src/ahb_dma/rx_crc_width_ch.rs @@ -0,0 +1,85 @@ +#[doc = "Register `RX_CRC_WIDTH_CH%s` reader"] +pub type R = crate::R; +#[doc = "Register `RX_CRC_WIDTH_CH%s` writer"] +pub type W = crate::W; +#[doc = "Field `RX_CRC_WIDTH_CH` reader - reserved"] +pub type RX_CRC_WIDTH_CH_R = crate::FieldReader; +#[doc = "Field `RX_CRC_WIDTH_CH` writer - reserved"] +pub type RX_CRC_WIDTH_CH_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `RX_CRC_LAUTCH_FLGA_CH` reader - reserved"] +pub type RX_CRC_LAUTCH_FLGA_CH_R = crate::BitReader; +#[doc = "Field `RX_CRC_LAUTCH_FLGA_CH` writer - reserved"] +pub type RX_CRC_LAUTCH_FLGA_CH_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:1 - reserved"] + #[inline(always)] + pub fn rx_crc_width_ch(&self) -> RX_CRC_WIDTH_CH_R { + RX_CRC_WIDTH_CH_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 2 - reserved"] + #[inline(always)] + pub fn rx_crc_lautch_flga_ch(&self) -> RX_CRC_LAUTCH_FLGA_CH_R { + RX_CRC_LAUTCH_FLGA_CH_R::new(((self.bits >> 2) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RX_CRC_WIDTH_CH") + .field( + "rx_crc_width_ch", + &format_args!("{}", self.rx_crc_width_ch().bits()), + ) + .field( + "rx_crc_lautch_flga_ch", + &format_args!("{}", self.rx_crc_lautch_flga_ch().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - reserved"] + #[inline(always)] + #[must_use] + pub fn rx_crc_width_ch(&mut self) -> RX_CRC_WIDTH_CH_W { + RX_CRC_WIDTH_CH_W::new(self, 0) + } + #[doc = "Bit 2 - reserved"] + #[inline(always)] + #[must_use] + pub fn rx_crc_lautch_flga_ch(&mut self) -> RX_CRC_LAUTCH_FLGA_CH_W { + RX_CRC_LAUTCH_FLGA_CH_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "This register is used to confiig rx ch0 crc result width,2'b00 mean crc_width <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean 24<crc_width<=32\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_crc_width_ch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_crc_width_ch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RX_CRC_WIDTH_CH_SPEC; +impl crate::RegisterSpec for RX_CRC_WIDTH_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rx_crc_width_ch::R`](R) reader structure"] +impl crate::Readable for RX_CRC_WIDTH_CH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rx_crc_width_ch::W`](W) writer structure"] +impl crate::Writable for RX_CRC_WIDTH_CH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RX_CRC_WIDTH_CH%s to value 0"] +impl crate::Resettable for RX_CRC_WIDTH_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ahb_dma/tx_arb_weigh_opt_dir_ch.rs b/esp32p4/src/ahb_dma/tx_arb_weigh_opt_dir_ch.rs new file mode 100644 index 0000000000..7298357e2f --- /dev/null +++ b/esp32p4/src/ahb_dma/tx_arb_weigh_opt_dir_ch.rs @@ -0,0 +1,68 @@ +#[doc = "Register `TX_ARB_WEIGH_OPT_DIR_CH%s` reader"] +pub type R = crate::R; +#[doc = "Register `TX_ARB_WEIGH_OPT_DIR_CH%s` writer"] +pub type W = crate::W; +#[doc = "Field `TX_ARB_WEIGH_OPT_DIR_CH` reader - reserved"] +pub type TX_ARB_WEIGH_OPT_DIR_CH_R = crate::BitReader; +#[doc = "Field `TX_ARB_WEIGH_OPT_DIR_CH` writer - reserved"] +pub type TX_ARB_WEIGH_OPT_DIR_CH_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - reserved"] + #[inline(always)] + pub fn tx_arb_weigh_opt_dir_ch(&self) -> TX_ARB_WEIGH_OPT_DIR_CH_R { + TX_ARB_WEIGH_OPT_DIR_CH_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TX_ARB_WEIGH_OPT_DIR_CH") + .field( + "tx_arb_weigh_opt_dir_ch", + &format_args!("{}", self.tx_arb_weigh_opt_dir_ch().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - reserved"] + #[inline(always)] + #[must_use] + pub fn tx_arb_weigh_opt_dir_ch( + &mut self, + ) -> TX_ARB_WEIGH_OPT_DIR_CH_W { + TX_ARB_WEIGH_OPT_DIR_CH_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "This register is used to config off or on weigh optimization\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_arb_weigh_opt_dir_ch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_arb_weigh_opt_dir_ch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TX_ARB_WEIGH_OPT_DIR_CH_SPEC; +impl crate::RegisterSpec for TX_ARB_WEIGH_OPT_DIR_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`tx_arb_weigh_opt_dir_ch::R`](R) reader structure"] +impl crate::Readable for TX_ARB_WEIGH_OPT_DIR_CH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tx_arb_weigh_opt_dir_ch::W`](W) writer structure"] +impl crate::Writable for TX_ARB_WEIGH_OPT_DIR_CH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TX_ARB_WEIGH_OPT_DIR_CH%s to value 0"] +impl crate::Resettable for TX_ARB_WEIGH_OPT_DIR_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ahb_dma/tx_ch_arb_weigh_ch.rs b/esp32p4/src/ahb_dma/tx_ch_arb_weigh_ch.rs new file mode 100644 index 0000000000..57332b16b0 --- /dev/null +++ b/esp32p4/src/ahb_dma/tx_ch_arb_weigh_ch.rs @@ -0,0 +1,66 @@ +#[doc = "Register `TX_CH_ARB_WEIGH_CH%s` reader"] +pub type R = crate::R; +#[doc = "Register `TX_CH_ARB_WEIGH_CH%s` writer"] +pub type W = crate::W; +#[doc = "Field `TX_CH_ARB_WEIGH_CH` reader - reserved"] +pub type TX_CH_ARB_WEIGH_CH_R = crate::FieldReader; +#[doc = "Field `TX_CH_ARB_WEIGH_CH` writer - reserved"] +pub type TX_CH_ARB_WEIGH_CH_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - reserved"] + #[inline(always)] + pub fn tx_ch_arb_weigh_ch(&self) -> TX_CH_ARB_WEIGH_CH_R { + TX_CH_ARB_WEIGH_CH_R::new((self.bits & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TX_CH_ARB_WEIGH_CH") + .field( + "tx_ch_arb_weigh_ch", + &format_args!("{}", self.tx_ch_arb_weigh_ch().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:3 - reserved"] + #[inline(always)] + #[must_use] + pub fn tx_ch_arb_weigh_ch(&mut self) -> TX_CH_ARB_WEIGH_CH_W { + TX_CH_ARB_WEIGH_CH_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "This register is used to config ch0 arbiter weigh\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_ch_arb_weigh_ch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_ch_arb_weigh_ch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TX_CH_ARB_WEIGH_CH_SPEC; +impl crate::RegisterSpec for TX_CH_ARB_WEIGH_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`tx_ch_arb_weigh_ch::R`](R) reader structure"] +impl crate::Readable for TX_CH_ARB_WEIGH_CH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tx_ch_arb_weigh_ch::W`](W) writer structure"] +impl crate::Writable for TX_CH_ARB_WEIGH_CH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TX_CH_ARB_WEIGH_CH%s to value 0"] +impl crate::Resettable for TX_CH_ARB_WEIGH_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ahb_dma/tx_crc_data_en_addr_ch.rs b/esp32p4/src/ahb_dma/tx_crc_data_en_addr_ch.rs new file mode 100644 index 0000000000..0393763613 --- /dev/null +++ b/esp32p4/src/ahb_dma/tx_crc_data_en_addr_ch.rs @@ -0,0 +1,68 @@ +#[doc = "Register `TX_CRC_DATA_EN_ADDR_CH%s` reader"] +pub type R = crate::R; +#[doc = "Register `TX_CRC_DATA_EN_ADDR_CH%s` writer"] +pub type W = crate::W; +#[doc = "Field `TX_CRC_DATA_EN_ADDR_CH` reader - reserved"] +pub type TX_CRC_DATA_EN_ADDR_CH_R = crate::FieldReader; +#[doc = "Field `TX_CRC_DATA_EN_ADDR_CH` writer - reserved"] +pub type TX_CRC_DATA_EN_ADDR_CH_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - reserved"] + #[inline(always)] + pub fn tx_crc_data_en_addr_ch(&self) -> TX_CRC_DATA_EN_ADDR_CH_R { + TX_CRC_DATA_EN_ADDR_CH_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TX_CRC_DATA_EN_ADDR_CH") + .field( + "tx_crc_data_en_addr_ch", + &format_args!("{}", self.tx_crc_data_en_addr_ch().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - reserved"] + #[inline(always)] + #[must_use] + pub fn tx_crc_data_en_addr_ch( + &mut self, + ) -> TX_CRC_DATA_EN_ADDR_CH_W { + TX_CRC_DATA_EN_ADDR_CH_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "This register is used to config addr of crc data_8bit en\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_crc_data_en_addr_ch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_crc_data_en_addr_ch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TX_CRC_DATA_EN_ADDR_CH_SPEC; +impl crate::RegisterSpec for TX_CRC_DATA_EN_ADDR_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`tx_crc_data_en_addr_ch::R`](R) reader structure"] +impl crate::Readable for TX_CRC_DATA_EN_ADDR_CH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tx_crc_data_en_addr_ch::W`](W) writer structure"] +impl crate::Writable for TX_CRC_DATA_EN_ADDR_CH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TX_CRC_DATA_EN_ADDR_CH%s to value 0"] +impl crate::Resettable for TX_CRC_DATA_EN_ADDR_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ahb_dma/tx_crc_data_en_wr_data_ch.rs b/esp32p4/src/ahb_dma/tx_crc_data_en_wr_data_ch.rs new file mode 100644 index 0000000000..ac3d3111bd --- /dev/null +++ b/esp32p4/src/ahb_dma/tx_crc_data_en_wr_data_ch.rs @@ -0,0 +1,68 @@ +#[doc = "Register `TX_CRC_DATA_EN_WR_DATA_CH%s` reader"] +pub type R = crate::R; +#[doc = "Register `TX_CRC_DATA_EN_WR_DATA_CH%s` writer"] +pub type W = crate::W; +#[doc = "Field `TX_CRC_DATA_EN_WR_DATA_CH` reader - reserved"] +pub type TX_CRC_DATA_EN_WR_DATA_CH_R = crate::FieldReader; +#[doc = "Field `TX_CRC_DATA_EN_WR_DATA_CH` writer - reserved"] +pub type TX_CRC_DATA_EN_WR_DATA_CH_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - reserved"] + #[inline(always)] + pub fn tx_crc_data_en_wr_data_ch(&self) -> TX_CRC_DATA_EN_WR_DATA_CH_R { + TX_CRC_DATA_EN_WR_DATA_CH_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TX_CRC_DATA_EN_WR_DATA_CH") + .field( + "tx_crc_data_en_wr_data_ch", + &format_args!("{}", self.tx_crc_data_en_wr_data_ch().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - reserved"] + #[inline(always)] + #[must_use] + pub fn tx_crc_data_en_wr_data_ch( + &mut self, + ) -> TX_CRC_DATA_EN_WR_DATA_CH_W { + TX_CRC_DATA_EN_WR_DATA_CH_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "This register is used to config crc data_8bit en\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_crc_data_en_wr_data_ch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_crc_data_en_wr_data_ch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TX_CRC_DATA_EN_WR_DATA_CH_SPEC; +impl crate::RegisterSpec for TX_CRC_DATA_EN_WR_DATA_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`tx_crc_data_en_wr_data_ch::R`](R) reader structure"] +impl crate::Readable for TX_CRC_DATA_EN_WR_DATA_CH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tx_crc_data_en_wr_data_ch::W`](W) writer structure"] +impl crate::Writable for TX_CRC_DATA_EN_WR_DATA_CH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TX_CRC_DATA_EN_WR_DATA_CH%s to value 0"] +impl crate::Resettable for TX_CRC_DATA_EN_WR_DATA_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ahb_dma/tx_crc_en_addr_ch.rs b/esp32p4/src/ahb_dma/tx_crc_en_addr_ch.rs new file mode 100644 index 0000000000..8323392846 --- /dev/null +++ b/esp32p4/src/ahb_dma/tx_crc_en_addr_ch.rs @@ -0,0 +1,66 @@ +#[doc = "Register `TX_CRC_EN_ADDR_CH%s` reader"] +pub type R = crate::R; +#[doc = "Register `TX_CRC_EN_ADDR_CH%s` writer"] +pub type W = crate::W; +#[doc = "Field `TX_CRC_EN_ADDR_CH` reader - reserved"] +pub type TX_CRC_EN_ADDR_CH_R = crate::FieldReader; +#[doc = "Field `TX_CRC_EN_ADDR_CH` writer - reserved"] +pub type TX_CRC_EN_ADDR_CH_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - reserved"] + #[inline(always)] + pub fn tx_crc_en_addr_ch(&self) -> TX_CRC_EN_ADDR_CH_R { + TX_CRC_EN_ADDR_CH_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TX_CRC_EN_ADDR_CH") + .field( + "tx_crc_en_addr_ch", + &format_args!("{}", self.tx_crc_en_addr_ch().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - reserved"] + #[inline(always)] + #[must_use] + pub fn tx_crc_en_addr_ch(&mut self) -> TX_CRC_EN_ADDR_CH_W { + TX_CRC_EN_ADDR_CH_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "This register is used to config ch0 crc en addr\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_crc_en_addr_ch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_crc_en_addr_ch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TX_CRC_EN_ADDR_CH_SPEC; +impl crate::RegisterSpec for TX_CRC_EN_ADDR_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`tx_crc_en_addr_ch::R`](R) reader structure"] +impl crate::Readable for TX_CRC_EN_ADDR_CH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tx_crc_en_addr_ch::W`](W) writer structure"] +impl crate::Writable for TX_CRC_EN_ADDR_CH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TX_CRC_EN_ADDR_CH%s to value 0"] +impl crate::Resettable for TX_CRC_EN_ADDR_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ahb_dma/tx_crc_en_wr_data_ch.rs b/esp32p4/src/ahb_dma/tx_crc_en_wr_data_ch.rs new file mode 100644 index 0000000000..d6a469072f --- /dev/null +++ b/esp32p4/src/ahb_dma/tx_crc_en_wr_data_ch.rs @@ -0,0 +1,66 @@ +#[doc = "Register `TX_CRC_EN_WR_DATA_CH%s` reader"] +pub type R = crate::R; +#[doc = "Register `TX_CRC_EN_WR_DATA_CH%s` writer"] +pub type W = crate::W; +#[doc = "Field `TX_CRC_EN_WR_DATA_CH` reader - This register is used to enable tx ch0 crc 32bit on/off"] +pub type TX_CRC_EN_WR_DATA_CH_R = crate::FieldReader; +#[doc = "Field `TX_CRC_EN_WR_DATA_CH` writer - This register is used to enable tx ch0 crc 32bit on/off"] +pub type TX_CRC_EN_WR_DATA_CH_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - This register is used to enable tx ch0 crc 32bit on/off"] + #[inline(always)] + pub fn tx_crc_en_wr_data_ch(&self) -> TX_CRC_EN_WR_DATA_CH_R { + TX_CRC_EN_WR_DATA_CH_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TX_CRC_EN_WR_DATA_CH") + .field( + "tx_crc_en_wr_data_ch", + &format_args!("{}", self.tx_crc_en_wr_data_ch().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - This register is used to enable tx ch0 crc 32bit on/off"] + #[inline(always)] + #[must_use] + pub fn tx_crc_en_wr_data_ch(&mut self) -> TX_CRC_EN_WR_DATA_CH_W { + TX_CRC_EN_WR_DATA_CH_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "This resister is used to config ch0 crc en for every bit\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_crc_en_wr_data_ch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_crc_en_wr_data_ch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TX_CRC_EN_WR_DATA_CH_SPEC; +impl crate::RegisterSpec for TX_CRC_EN_WR_DATA_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`tx_crc_en_wr_data_ch::R`](R) reader structure"] +impl crate::Readable for TX_CRC_EN_WR_DATA_CH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tx_crc_en_wr_data_ch::W`](W) writer structure"] +impl crate::Writable for TX_CRC_EN_WR_DATA_CH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TX_CRC_EN_WR_DATA_CH%s to value 0"] +impl crate::Resettable for TX_CRC_EN_WR_DATA_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ahb_dma/tx_crc_width_ch.rs b/esp32p4/src/ahb_dma/tx_crc_width_ch.rs new file mode 100644 index 0000000000..7b1efff15d --- /dev/null +++ b/esp32p4/src/ahb_dma/tx_crc_width_ch.rs @@ -0,0 +1,85 @@ +#[doc = "Register `TX_CRC_WIDTH_CH%s` reader"] +pub type R = crate::R; +#[doc = "Register `TX_CRC_WIDTH_CH%s` writer"] +pub type W = crate::W; +#[doc = "Field `TX_CRC_WIDTH_CH` reader - reserved"] +pub type TX_CRC_WIDTH_CH_R = crate::FieldReader; +#[doc = "Field `TX_CRC_WIDTH_CH` writer - reserved"] +pub type TX_CRC_WIDTH_CH_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `TX_CRC_LAUTCH_FLGA_CH` reader - reserved"] +pub type TX_CRC_LAUTCH_FLGA_CH_R = crate::BitReader; +#[doc = "Field `TX_CRC_LAUTCH_FLGA_CH` writer - reserved"] +pub type TX_CRC_LAUTCH_FLGA_CH_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:1 - reserved"] + #[inline(always)] + pub fn tx_crc_width_ch(&self) -> TX_CRC_WIDTH_CH_R { + TX_CRC_WIDTH_CH_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 2 - reserved"] + #[inline(always)] + pub fn tx_crc_lautch_flga_ch(&self) -> TX_CRC_LAUTCH_FLGA_CH_R { + TX_CRC_LAUTCH_FLGA_CH_R::new(((self.bits >> 2) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TX_CRC_WIDTH_CH") + .field( + "tx_crc_width_ch", + &format_args!("{}", self.tx_crc_width_ch().bits()), + ) + .field( + "tx_crc_lautch_flga_ch", + &format_args!("{}", self.tx_crc_lautch_flga_ch().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - reserved"] + #[inline(always)] + #[must_use] + pub fn tx_crc_width_ch(&mut self) -> TX_CRC_WIDTH_CH_W { + TX_CRC_WIDTH_CH_W::new(self, 0) + } + #[doc = "Bit 2 - reserved"] + #[inline(always)] + #[must_use] + pub fn tx_crc_lautch_flga_ch(&mut self) -> TX_CRC_LAUTCH_FLGA_CH_W { + TX_CRC_LAUTCH_FLGA_CH_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "This register is used to confiig tx ch0 crc result width,2'b00 mean crc_width <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean 24<crc_width<=32\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_crc_width_ch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_crc_width_ch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TX_CRC_WIDTH_CH_SPEC; +impl crate::RegisterSpec for TX_CRC_WIDTH_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`tx_crc_width_ch::R`](R) reader structure"] +impl crate::Readable for TX_CRC_WIDTH_CH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tx_crc_width_ch::W`](W) writer structure"] +impl crate::Writable for TX_CRC_WIDTH_CH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TX_CRC_WIDTH_CH%s to value 0"] +impl crate::Resettable for TX_CRC_WIDTH_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ahb_dma/weight_en_rx.rs b/esp32p4/src/ahb_dma/weight_en_rx.rs new file mode 100644 index 0000000000..16b171f851 --- /dev/null +++ b/esp32p4/src/ahb_dma/weight_en_rx.rs @@ -0,0 +1,66 @@ +#[doc = "Register `WEIGHT_EN_RX` reader"] +pub type R = crate::R; +#[doc = "Register `WEIGHT_EN_RX` writer"] +pub type W = crate::W; +#[doc = "Field `WEIGHT_EN_RX` reader - This register is used to config arbiter weight function off/on"] +pub type WEIGHT_EN_RX_R = crate::BitReader; +#[doc = "Field `WEIGHT_EN_RX` writer - This register is used to config arbiter weight function off/on"] +pub type WEIGHT_EN_RX_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - This register is used to config arbiter weight function off/on"] + #[inline(always)] + pub fn weight_en_rx(&self) -> WEIGHT_EN_RX_R { + WEIGHT_EN_RX_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("WEIGHT_EN_RX") + .field( + "weight_en_rx", + &format_args!("{}", self.weight_en_rx().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - This register is used to config arbiter weight function off/on"] + #[inline(always)] + #[must_use] + pub fn weight_en_rx(&mut self) -> WEIGHT_EN_RX_W { + WEIGHT_EN_RX_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "This register is used to config arbiter weigh function to on or off for rx dir\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`weight_en_rx::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`weight_en_rx::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WEIGHT_EN_RX_SPEC; +impl crate::RegisterSpec for WEIGHT_EN_RX_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`weight_en_rx::R`](R) reader structure"] +impl crate::Readable for WEIGHT_EN_RX_SPEC {} +#[doc = "`write(|w| ..)` method takes [`weight_en_rx::W`](W) writer structure"] +impl crate::Writable for WEIGHT_EN_RX_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets WEIGHT_EN_RX to value 0"] +impl crate::Resettable for WEIGHT_EN_RX_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ahb_dma/weight_en_tx.rs b/esp32p4/src/ahb_dma/weight_en_tx.rs new file mode 100644 index 0000000000..388f634444 --- /dev/null +++ b/esp32p4/src/ahb_dma/weight_en_tx.rs @@ -0,0 +1,66 @@ +#[doc = "Register `WEIGHT_EN_TX` reader"] +pub type R = crate::R; +#[doc = "Register `WEIGHT_EN_TX` writer"] +pub type W = crate::W; +#[doc = "Field `WEIGHT_EN_TX` reader - This register is used to config arbiter weight function off/on"] +pub type WEIGHT_EN_TX_R = crate::BitReader; +#[doc = "Field `WEIGHT_EN_TX` writer - This register is used to config arbiter weight function off/on"] +pub type WEIGHT_EN_TX_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - This register is used to config arbiter weight function off/on"] + #[inline(always)] + pub fn weight_en_tx(&self) -> WEIGHT_EN_TX_R { + WEIGHT_EN_TX_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("WEIGHT_EN_TX") + .field( + "weight_en_tx", + &format_args!("{}", self.weight_en_tx().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - This register is used to config arbiter weight function off/on"] + #[inline(always)] + #[must_use] + pub fn weight_en_tx(&mut self) -> WEIGHT_EN_TX_W { + WEIGHT_EN_TX_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "This register is used to config arbiter weigh function to on or off for tx dir\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`weight_en_tx::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`weight_en_tx::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WEIGHT_EN_TX_SPEC; +impl crate::RegisterSpec for WEIGHT_EN_TX_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`weight_en_tx::R`](R) reader structure"] +impl crate::Readable for WEIGHT_EN_TX_SPEC {} +#[doc = "`write(|w| ..)` method takes [`weight_en_tx::W`](W) writer structure"] +impl crate::Writable for WEIGHT_EN_TX_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets WEIGHT_EN_TX to value 0"] +impl crate::Resettable for WEIGHT_EN_TX_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt.rs b/esp32p4/src/interrupt.rs index 470c9e0ec5..ae525029cc 100644 --- a/esp32p4/src/interrupt.rs +++ b/esp32p4/src/interrupt.rs @@ -50,6 +50,14 @@ pub enum Interrupt { UHCI0 = 30, #[doc = "31 - UART0"] UART0 = 31, + #[doc = "32 - UART1"] + UART1 = 32, + #[doc = "33 - UART2"] + UART2 = 33, + #[doc = "34 - UART3"] + UART3 = 34, + #[doc = "35 - UART4"] + UART4 = 35, #[doc = "38 - PWM0"] PWM0 = 38, #[doc = "39 - PWM1"] @@ -86,6 +94,30 @@ pub enum Interrupt { SYSTIMER_TARGET1 = 54, #[doc = "55 - SYSTIMER_TARGET2"] SYSTIMER_TARGET2 = 55, + #[doc = "56 - AHB_PDMA_IN_CH0"] + AHB_PDMA_IN_CH0 = 56, + #[doc = "57 - AHB_PDMA_IN_CH1"] + AHB_PDMA_IN_CH1 = 57, + #[doc = "58 - AHB_PDMA_IN_CH2"] + AHB_PDMA_IN_CH2 = 58, + #[doc = "59 - AHB_PDMA_OUT_CH0"] + AHB_PDMA_OUT_CH0 = 59, + #[doc = "60 - AHB_PDMA_OUT_CH1"] + AHB_PDMA_OUT_CH1 = 60, + #[doc = "61 - AHB_PDMA_OUT_CH2"] + AHB_PDMA_OUT_CH2 = 61, + #[doc = "62 - AXI_PDMA_IN_CH0"] + AXI_PDMA_IN_CH0 = 62, + #[doc = "63 - AXI_PDMA_IN_CH1"] + AXI_PDMA_IN_CH1 = 63, + #[doc = "64 - AXI_PDMA_IN_CH2"] + AXI_PDMA_IN_CH2 = 64, + #[doc = "65 - AXI_PDMA_OUT_CH0"] + AXI_PDMA_OUT_CH0 = 65, + #[doc = "66 - AXI_PDMA_OUT_CH1"] + AXI_PDMA_OUT_CH1 = 66, + #[doc = "67 - AXI_PDMA_OUT_CH2"] + AXI_PDMA_OUT_CH2 = 67, #[doc = "68 - RSA"] RSA = 68, #[doc = "69 - AES"] @@ -193,6 +225,10 @@ impl Interrupt { 29 => Ok(Interrupt::I2S2), 30 => Ok(Interrupt::UHCI0), 31 => Ok(Interrupt::UART0), + 32 => Ok(Interrupt::UART1), + 33 => Ok(Interrupt::UART2), + 34 => Ok(Interrupt::UART3), + 35 => Ok(Interrupt::UART4), 38 => Ok(Interrupt::PWM0), 39 => Ok(Interrupt::PWM1), 40 => Ok(Interrupt::TWAI0), @@ -211,6 +247,18 @@ impl Interrupt { 53 => Ok(Interrupt::SYSTIMER_TARGET0), 54 => Ok(Interrupt::SYSTIMER_TARGET1), 55 => Ok(Interrupt::SYSTIMER_TARGET2), + 56 => Ok(Interrupt::AHB_PDMA_IN_CH0), + 57 => Ok(Interrupt::AHB_PDMA_IN_CH1), + 58 => Ok(Interrupt::AHB_PDMA_IN_CH2), + 59 => Ok(Interrupt::AHB_PDMA_OUT_CH0), + 60 => Ok(Interrupt::AHB_PDMA_OUT_CH1), + 61 => Ok(Interrupt::AHB_PDMA_OUT_CH2), + 62 => Ok(Interrupt::AXI_PDMA_IN_CH0), + 63 => Ok(Interrupt::AXI_PDMA_IN_CH1), + 64 => Ok(Interrupt::AXI_PDMA_IN_CH2), + 65 => Ok(Interrupt::AXI_PDMA_OUT_CH0), + 66 => Ok(Interrupt::AXI_PDMA_OUT_CH1), + 67 => Ok(Interrupt::AXI_PDMA_OUT_CH2), 68 => Ok(Interrupt::RSA), 69 => Ok(Interrupt::AES), 70 => Ok(Interrupt::SHA), diff --git a/esp32p4/src/lib.rs b/esp32p4/src/lib.rs index 38ee4b1091..4c5376f038 100644 --- a/esp32p4/src/lib.rs +++ b/esp32p4/src/lib.rs @@ -37,6 +37,10 @@ extern "C" { fn I2S2(); fn UHCI0(); fn UART0(); + fn UART1(); + fn UART2(); + fn UART3(); + fn UART4(); fn PWM0(); fn PWM1(); fn TWAI0(); @@ -55,6 +59,18 @@ extern "C" { fn SYSTIMER_TARGET0(); fn SYSTIMER_TARGET1(); fn SYSTIMER_TARGET2(); + fn AHB_PDMA_IN_CH0(); + fn AHB_PDMA_IN_CH1(); + fn AHB_PDMA_IN_CH2(); + fn AHB_PDMA_OUT_CH0(); + fn AHB_PDMA_OUT_CH1(); + fn AHB_PDMA_OUT_CH2(); + fn AXI_PDMA_IN_CH0(); + fn AXI_PDMA_IN_CH1(); + fn AXI_PDMA_IN_CH2(); + fn AXI_PDMA_OUT_CH0(); + fn AXI_PDMA_OUT_CH1(); + fn AXI_PDMA_OUT_CH2(); fn RSA(); fn AES(); fn SHA(); @@ -142,10 +158,10 @@ pub static __EXTERNAL_INTERRUPTS: [Vector; 128] = [ Vector { _handler: I2S2 }, Vector { _handler: UHCI0 }, Vector { _handler: UART0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, + Vector { _handler: UART1 }, + Vector { _handler: UART2 }, + Vector { _handler: UART3 }, + Vector { _handler: UART4 }, Vector { _reserved: 0 }, Vector { _reserved: 0 }, Vector { _handler: PWM0 }, @@ -172,18 +188,42 @@ pub static __EXTERNAL_INTERRUPTS: [Vector; 128] = [ Vector { _handler: SYSTIMER_TARGET2, }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, + Vector { + _handler: AHB_PDMA_IN_CH0, + }, + Vector { + _handler: AHB_PDMA_IN_CH1, + }, + Vector { + _handler: AHB_PDMA_IN_CH2, + }, + Vector { + _handler: AHB_PDMA_OUT_CH0, + }, + Vector { + _handler: AHB_PDMA_OUT_CH1, + }, + Vector { + _handler: AHB_PDMA_OUT_CH2, + }, + Vector { + _handler: AXI_PDMA_IN_CH0, + }, + Vector { + _handler: AXI_PDMA_IN_CH1, + }, + Vector { + _handler: AXI_PDMA_IN_CH2, + }, + Vector { + _handler: AXI_PDMA_OUT_CH0, + }, + Vector { + _handler: AXI_PDMA_OUT_CH1, + }, + Vector { + _handler: AXI_PDMA_OUT_CH2, + }, Vector { _handler: RSA }, Vector { _handler: AES }, Vector { _handler: SHA }, @@ -382,6 +422,52 @@ impl core::fmt::Debug for AES { } #[doc = "AES (Advanced Encryption Standard) Accelerator"] pub mod aes; +#[doc = "AHB_DMA Peripheral"] +pub struct AHB_DMA { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for AHB_DMA {} +impl AHB_DMA { + #[doc = r"Pointer to the register block"] + pub const PTR: *const ahb_dma::RegisterBlock = 0x5008_5000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const ahb_dma::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for AHB_DMA { + type Target = ahb_dma::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for AHB_DMA { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AHB_DMA").finish() + } +} +#[doc = "AHB_DMA Peripheral"] +pub mod ahb_dma; #[doc = "LP_I2C_ANA_MST Peripheral"] pub struct LP_I2C_ANA_MST { _marker: PhantomData<*const ()>, @@ -4016,6 +4102,190 @@ impl core::fmt::Debug for UART0 { } #[doc = "UART (Universal Asynchronous Receiver-Transmitter) Controller 0"] pub mod uart0; +#[doc = "UART (Universal Asynchronous Receiver-Transmitter) Controller 1"] +pub struct UART1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for UART1 {} +impl UART1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const uart0::RegisterBlock = 0x500c_b000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const uart0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for UART1 { + type Target = uart0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for UART1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("UART1").finish() + } +} +#[doc = "UART (Universal Asynchronous Receiver-Transmitter) Controller 1"] +pub use self::uart0 as uart1; +#[doc = "UART (Universal Asynchronous Receiver-Transmitter) Controller 2"] +pub struct UART2 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for UART2 {} +impl UART2 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const uart0::RegisterBlock = 0x500c_c000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const uart0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for UART2 { + type Target = uart0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for UART2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("UART2").finish() + } +} +#[doc = "UART (Universal Asynchronous Receiver-Transmitter) Controller 2"] +pub use self::uart0 as uart2; +#[doc = "UART (Universal Asynchronous Receiver-Transmitter) Controller 3"] +pub struct UART3 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for UART3 {} +impl UART3 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const uart0::RegisterBlock = 0x500c_d000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const uart0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for UART3 { + type Target = uart0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for UART3 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("UART3").finish() + } +} +#[doc = "UART (Universal Asynchronous Receiver-Transmitter) Controller 3"] +pub use self::uart0 as uart3; +#[doc = "UART (Universal Asynchronous Receiver-Transmitter) Controller 4"] +pub struct UART4 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for UART4 {} +impl UART4 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const uart0::RegisterBlock = 0x500c_e000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const uart0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for UART4 { + type Target = uart0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for UART4 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("UART4").finish() + } +} +#[doc = "UART (Universal Asynchronous Receiver-Transmitter) Controller 4"] +pub use self::uart0 as uart4; #[doc = "Universal Host Controller Interface 0"] pub struct UHCI0 { _marker: PhantomData<*const ()>, @@ -4163,6 +4433,8 @@ pub struct Peripherals { pub ADC: ADC, #[doc = "AES"] pub AES: AES, + #[doc = "AHB_DMA"] + pub AHB_DMA: AHB_DMA, #[doc = "LP_I2C_ANA_MST"] pub LP_I2C_ANA_MST: LP_I2C_ANA_MST, #[doc = "ASSIST_DEBUG"] @@ -4321,6 +4593,14 @@ pub struct Peripherals { pub TWAI2: TWAI2, #[doc = "UART0"] pub UART0: UART0, + #[doc = "UART1"] + pub UART1: UART1, + #[doc = "UART2"] + pub UART2: UART2, + #[doc = "UART3"] + pub UART3: UART3, + #[doc = "UART4"] + pub UART4: UART4, #[doc = "UHCI0"] pub UHCI0: UHCI0, #[doc = "USB_DEVICE"] @@ -4355,6 +4635,9 @@ impl Peripherals { AES: AES { _marker: PhantomData, }, + AHB_DMA: AHB_DMA { + _marker: PhantomData, + }, LP_I2C_ANA_MST: LP_I2C_ANA_MST { _marker: PhantomData, }, @@ -4592,6 +4875,18 @@ impl Peripherals { UART0: UART0 { _marker: PhantomData, }, + UART1: UART1 { + _marker: PhantomData, + }, + UART2: UART2 { + _marker: PhantomData, + }, + UART3: UART3 { + _marker: PhantomData, + }, + UART4: UART4 { + _marker: PhantomData, + }, UHCI0: UHCI0 { _marker: PhantomData, }, diff --git a/esp32p4/svd/esp32p4.base.svd b/esp32p4/svd/esp32p4.base.svd index ef258da6ef..e805dcf66b 100644 --- a/esp32p4/svd/esp32p4.base.svd +++ b/esp32p4/svd/esp32p4.base.svd @@ -4,9 +4,9 @@ ESPRESSIF ESP32-P4 ESP32 P-Series - 1 + 2 32-bit RISC-V MCU - Copyright 2023 Espressif Systems (Shanghai) PTE LTD + Copyright 2024 Espressif Systems (Shanghai) PTE LTD Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -1284,36 +1284,36 @@ - 16 - 0x1 + 4 + 0x4 IV_MEM[%s] The memory that stores initialization vector 0x50 - 0x8 + 0x20 - 16 - 0x1 + 4 + 0x4 H_MEM[%s] The memory that stores GCM hash subkey 0x60 - 0x8 + 0x20 - 16 - 0x1 + 4 + 0x4 J0_MEM[%s] The memory that stores J0 0x70 - 0x8 + 0x20 - 16 - 0x1 + 4 + 0x4 T0_MEM[%s] The memory that stores T0 0x80 - 0x8 + 0x20 DMA_ENABLE @@ -1484,869 +1484,858 @@ - LP_I2C_ANA_MST - LP_I2C_ANA_MST Peripheral - ANA_I2C_MST - 0x50124000 + AHB_DMA + AHB_DMA Peripheral + AHB_DMA + 0x50085000 0x0 - 0x3C + 0x2C4 registers + + AHB_PDMA_IN_CH0 + 56 + + + AHB_PDMA_IN_CH1 + 57 + + + AHB_PDMA_IN_CH2 + 58 + + + AHB_PDMA_OUT_CH0 + 59 + + + AHB_PDMA_OUT_CH1 + 60 + + + AHB_PDMA_OUT_CH2 + 61 + + + AXI_PDMA_IN_CH0 + 62 + + + AXI_PDMA_IN_CH1 + 63 + + + AXI_PDMA_IN_CH2 + 64 + + + AXI_PDMA_OUT_CH0 + 65 + + + AXI_PDMA_OUT_CH1 + 66 + + + AXI_PDMA_OUT_CH2 + 67 + - I2C0_CTRL - need des + 3 + 0x10 + IN_INT_RAW_CH%s + Raw status interrupt of channel 0 0x0 0x20 - I2C0_CTRL - need des + IN_DONE_CH_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. 0 - 25 + 1 read-write - I2C0_BUSY - need des - 25 + IN_SUC_EOF_CH_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0. + 1 1 - read-only - - - - - I2C1_CTRL - need des - 0x4 - 0x20 - - - I2C1_CTRL - need des - 0 - 25 read-write - I2C1_BUSY - need des - 25 + IN_ERR_EOF_CH_INT_RAW + The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw interrupt is reserved. + 2 1 - read-only - - - - - I2C0_CONF - need des - 0x8 - 0x20 - - - I2C0_CONF - need des - 0 - 24 read-write - I2C0_STATUS - need des - 24 - 8 - read-only + IN_DSCR_ERR_CH_INT_RAW + The raw interrupt bit turns to high level when detecting inlink descriptor error including owner error and the second and third word error of inlink descriptor for Rx channel 0. + 3 + 1 + read-write - - - - I2C1_CONF - need des - 0xC - 0x20 - - I2C1_CONF - need des - 0 - 24 + IN_DSCR_EMPTY_CH_INT_RAW + The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed but there is no more inlink for Rx channel 0. + 4 + 1 read-write - I2C1_STATUS - need des - 24 - 8 - read-only + INFIFO_OVF_CH_INT_RAW + This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow. + 5 + 1 + read-write - - - - I2C_BURST_CONF - need des - 0x10 - 0x20 - - I2C_MST_BURST_CTRL - need des - 0 - 32 + INFIFO_UDF_CH_INT_RAW + This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow. + 6 + 1 read-write - I2C_BURST_STATUS - need des - 0x14 + 3 + 0x10 + IN_INT_ST_CH%s + Masked interrupt of channel 0 + 0x4 0x20 - 0x40000000 - I2C_MST_BURST_DONE - need des + IN_DONE_CH_INT_ST + The raw interrupt status bit for the IN_DONE_CH_INT interrupt. 0 1 read-only - I2C_MST0_BURST_ERR_FLAG - need des + IN_SUC_EOF_CH_INT_ST + The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. 1 1 read-only - I2C_MST1_BURST_ERR_FLAG - need des + IN_ERR_EOF_CH_INT_ST + The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. 2 1 read-only - I2C_MST_BURST_TIMEOUT_CNT - need des - 20 - 12 - read-write - - - - - ANA_CONF0 - need des - 0x18 - 0x20 - - - ANA_CONF0 - need des - 0 - 24 - read-write - - - ANA_STATUS0 - need des - 24 - 8 + IN_DSCR_ERR_CH_INT_ST + The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + 3 + 1 read-only - - - - ANA_CONF1 - need des - 0x1C - 0x20 - - - ANA_CONF1 - need des - 0 - 24 - read-write - - ANA_STATUS1 - need des - 24 - 8 + IN_DSCR_EMPTY_CH_INT_ST + The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + 4 + 1 read-only - - - - ANA_CONF2 - need des - 0x20 - 0x20 - - - ANA_CONF2 - need des - 0 - 24 - read-write - - ANA_STATUS2 - need des - 24 - 8 + INFIFO_OVF_CH_INT_ST + The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + 5 + 1 read-only - - - - I2C0_CTRL1 - need des - 0x24 - 0x20 - 0x00000042 - - - I2C0_SCL_PULSE_DUR - need des - 0 - 6 - read-write - - - I2C0_SDA_SIDE_GUARD - need des - 6 - 5 - read-write - - - - - I2C1_CTRL1 - need des - 0x28 - 0x20 - 0x00000042 - - - I2C1_SCL_PULSE_DUR - need des - 0 - 6 - read-write - - I2C1_SDA_SIDE_GUARD - need des + INFIFO_UDF_CH_INT_ST + The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. 6 - 5 - read-write + 1 + read-only - HW_I2C_CTRL - need des - 0x2C + 3 + 0x10 + IN_INT_ENA_CH%s + Interrupt enable bits of channel 0 + 0x8 0x20 - 0x00000042 - HW_I2C_SCL_PULSE_DUR - need des + IN_DONE_CH_INT_ENA + The interrupt enable bit for the IN_DONE_CH_INT interrupt. 0 - 6 + 1 read-write - HW_I2C_SDA_SIDE_GUARD - need des - 6 - 5 + IN_SUC_EOF_CH_INT_ENA + The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 read-write - ARBITER_DIS - need des - 11 + IN_ERR_EOF_CH_INT_ENA + The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + 2 1 read-write - - - - NOUSE - need des - 0x30 - 0x20 - - I2C_MST_NOUSE - need des - 0 - 32 + IN_DSCR_ERR_CH_INT_ENA + The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + 3 + 1 read-write - - - - CLK160M - need des - 0x34 - 0x20 - - CLK_I2C_MST_SEL_160M - need des - 0 + IN_DSCR_EMPTY_CH_INT_ENA + The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + 4 1 read-write - - - - DATE - need des - 0x38 - 0x20 - 0x02201300 - - DATE - need des - 0 - 28 + INFIFO_OVF_CH_INT_ENA + The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + 5 + 1 read-write - I2C_MST_CLK_EN - need des - 28 + INFIFO_UDF_CH_INT_ENA + The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + 6 1 read-write - - - - ASSIST_DEBUG - Debug Assist - ASSIST_DEBUG - 0x3FF06000 - - 0x0 - 0x100 - registers - - - ASSIST_DEBUG - 127 - - - CORE_0_INTR_ENA - core0 monitor enable configuration register - 0x0 + 3 + 0x10 + IN_INT_CLR_CH%s + Interrupt clear bits of channel 0 + 0xC 0x20 - CORE_0_AREA_DRAM0_0_RD_ENA - Core0 dram0 area0 read monitor enable + IN_DONE_CH_INT_CLR + Set this bit to clear the IN_DONE_CH_INT interrupt. 0 1 - read-write + write-only - CORE_0_AREA_DRAM0_0_WR_ENA - Core0 dram0 area0 write monitor enable + IN_SUC_EOF_CH_INT_CLR + Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. 1 1 - read-write + write-only - CORE_0_AREA_DRAM0_1_RD_ENA - Core0 dram0 area1 read monitor enable + IN_ERR_EOF_CH_INT_CLR + Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. 2 1 - read-write + write-only - CORE_0_AREA_DRAM0_1_WR_ENA - Core0 dram0 area1 write monitor enable + IN_DSCR_ERR_CH_INT_CLR + Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. 3 1 - read-write + write-only - CORE_0_AREA_PIF_0_RD_ENA - Core0 PIF area0 read monitor enable + IN_DSCR_EMPTY_CH_INT_CLR + Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. 4 1 - read-write + write-only - CORE_0_AREA_PIF_0_WR_ENA - Core0 PIF area0 write monitor enable + INFIFO_OVF_CH_INT_CLR + Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. 5 1 - read-write + write-only - CORE_0_AREA_PIF_1_RD_ENA - Core0 PIF area1 read monitor enable + INFIFO_UDF_CH_INT_CLR + Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. 6 1 + write-only + + + + + 3 + 0x10 + OUT_INT_RAW_CH%s + Raw status interrupt of channel 0 + 0x30 + 0x20 + + + OUT_DONE_CH_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0. + 0 + 1 read-write - CORE_0_AREA_PIF_1_WR_ENA - Core0 PIF area1 write monitor enable - 7 + OUT_EOF_CH_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. + 1 1 read-write - CORE_0_SP_SPILL_MIN_ENA - Core0 stackpoint underflow monitor enable - 8 + OUT_DSCR_ERR_CH_INT_RAW + The raw interrupt bit turns to high level when detecting outlink descriptor error including owner error and the second and third word error of outlink descriptor for Tx channel 0. + 2 1 read-write - CORE_0_SP_SPILL_MAX_ENA - Core0 stackpoint overflow monitor enable - 9 + OUT_TOTAL_EOF_CH_INT_RAW + The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0. + 3 1 read-write - CORE_0_IRAM0_EXCEPTION_MONITOR_ENA - IBUS busy monitor enable - 10 + OUTFIFO_OVF_CH_INT_RAW + This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow. + 4 1 read-write - CORE_0_DRAM0_EXCEPTION_MONITOR_ENA - DBUS busy monitor enbale - 11 + OUTFIFO_UDF_CH_INT_RAW + This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow. + 5 1 read-write - CORE_0_INTR_RAW - core0 monitor interrupt status register - 0x4 + 3 + 0x10 + OUT_INT_ST_CH%s + Masked interrupt of channel 0 + 0x34 0x20 - CORE_0_AREA_DRAM0_0_RD_RAW - Core0 dram0 area0 read monitor interrupt status + OUT_DONE_CH_INT_ST + The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. 0 1 read-only - CORE_0_AREA_DRAM0_0_WR_RAW - Core0 dram0 area0 write monitor interrupt status + OUT_EOF_CH_INT_ST + The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. 1 1 read-only - CORE_0_AREA_DRAM0_1_RD_RAW - Core0 dram0 area1 read monitor interrupt status + OUT_DSCR_ERR_CH_INT_ST + The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. 2 1 read-only - CORE_0_AREA_DRAM0_1_WR_RAW - Core0 dram0 area1 write monitor interrupt status + OUT_TOTAL_EOF_CH_INT_ST + The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. 3 1 read-only - CORE_0_AREA_PIF_0_RD_RAW - Core0 PIF area0 read monitor interrupt status + OUTFIFO_OVF_CH_INT_ST + The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. 4 1 read-only - CORE_0_AREA_PIF_0_WR_RAW - Core0 PIF area0 write monitor interrupt status + OUTFIFO_UDF_CH_INT_ST + The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. 5 1 read-only + + + + 3 + 0x10 + OUT_INT_ENA_CH%s + Interrupt enable bits of channel 0 + 0x38 + 0x20 + - CORE_0_AREA_PIF_1_RD_RAW - Core0 PIF area1 read monitor interrupt status - 6 + OUT_DONE_CH_INT_ENA + The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + 0 1 - read-only + read-write - CORE_0_AREA_PIF_1_WR_RAW - Core0 PIF area1 write monitor interrupt status - 7 + OUT_EOF_CH_INT_ENA + The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + 1 1 - read-only + read-write - CORE_0_SP_SPILL_MIN_RAW - Core0 stackpoint underflow monitor interrupt status - 8 + OUT_DSCR_ERR_CH_INT_ENA + The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + 2 1 - read-only + read-write - CORE_0_SP_SPILL_MAX_RAW - Core0 stackpoint overflow monitor interrupt status - 9 + OUT_TOTAL_EOF_CH_INT_ENA + The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + 3 1 - read-only + read-write - CORE_0_IRAM0_EXCEPTION_MONITOR_RAW - IBUS busy monitor interrupt status - 10 + OUTFIFO_OVF_CH_INT_ENA + The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 1 - read-only + read-write - CORE_0_DRAM0_EXCEPTION_MONITOR_RAW - DBUS busy monitor initerrupt status - 11 + OUTFIFO_UDF_CH_INT_ENA + The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 1 - read-only + read-write - CORE_0_INTR_RLS - core0 monitor interrupt enable register - 0x8 + 3 + 0x10 + OUT_INT_CLR_CH%s + Interrupt clear bits of channel 0 + 0x3C 0x20 - CORE_0_AREA_DRAM0_0_RD_RLS - Core0 dram0 area0 read monitor interrupt enable + OUT_DONE_CH_INT_CLR + Set this bit to clear the OUT_DONE_CH_INT interrupt. 0 1 - read-write + write-only - CORE_0_AREA_DRAM0_0_WR_RLS - Core0 dram0 area0 write monitor interrupt enable + OUT_EOF_CH_INT_CLR + Set this bit to clear the OUT_EOF_CH_INT interrupt. 1 1 - read-write + write-only - CORE_0_AREA_DRAM0_1_RD_RLS - Core0 dram0 area1 read monitor interrupt enable + OUT_DSCR_ERR_CH_INT_CLR + Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. 2 1 - read-write + write-only - CORE_0_AREA_DRAM0_1_WR_RLS - Core0 dram0 area1 write monitor interrupt enable + OUT_TOTAL_EOF_CH_INT_CLR + Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. 3 1 - read-write + write-only - CORE_0_AREA_PIF_0_RD_RLS - Core0 PIF area0 read monitor interrupt enable + OUTFIFO_OVF_CH_INT_CLR + Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. 4 1 - read-write + write-only - CORE_0_AREA_PIF_0_WR_RLS - Core0 PIF area0 write monitor interrupt enable + OUTFIFO_UDF_CH_INT_CLR + Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. 5 1 - read-write + write-only + + + + AHB_TEST + reserved + 0x60 + 0x20 + - CORE_0_AREA_PIF_1_RD_RLS - Core0 PIF area1 read monitor interrupt enable - 6 - 1 + AHB_TESTMODE + reserved + 0 + 3 read-write - CORE_0_AREA_PIF_1_WR_RLS - Core0 PIF area1 write monitor interrupt enable - 7 - 1 + AHB_TESTADDR + reserved + 4 + 2 read-write + + + + MISC_CONF + MISC register + 0x64 + 0x20 + - CORE_0_SP_SPILL_MIN_RLS - Core0 stackpoint underflow monitor interrupt enable - 8 + AHBM_RST_INTER + Set this bit then clear this bit to reset the internal ahb FSM. + 0 1 read-write - CORE_0_SP_SPILL_MAX_RLS - Core0 stackpoint overflow monitor interrupt enable - 9 + ARB_PRI_DIS + Set this bit to disable priority arbitration function. + 2 1 read-write - CORE_0_IRAM0_EXCEPTION_MONITOR_RLS - IBUS busy monitor interrupt enable - 10 + CLK_EN + 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers. + 3 1 read-write + + + + DATE + Version control register + 0x68 + 0x20 + 0x02303140 + - CORE_0_DRAM0_EXCEPTION_MONITOR_RLS - DBUS busy monitor interrupt enbale - 11 - 1 + DATE + register version. + 0 + 32 read-write - CORE_0_INTR_CLR - core0 monitor interrupt clr register - 0xC + 3 + 0xC0 + IN_CONF0_CH%s + Configure 0 register of Rx channel 0 + 0x70 0x20 - CORE_0_AREA_DRAM0_0_RD_CLR - Core0 dram0 area0 read monitor interrupt clr + IN_RST_CH + This bit is used to reset AHB_DMA channel 0 Rx FSM and Rx FIFO pointer. 0 1 - write-only + read-write - CORE_0_AREA_DRAM0_0_WR_CLR - Core0 dram0 area0 write monitor interrupt clr + IN_LOOP_TEST_CH + reserved 1 1 - write-only + read-write - CORE_0_AREA_DRAM0_1_RD_CLR - Core0 dram0 area1 read monitor interrupt clr + INDSCR_BURST_EN_CH + Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM. 2 1 - write-only + read-write - CORE_0_AREA_DRAM0_1_WR_CLR - Core0 dram0 area1 write monitor interrupt clr + IN_DATA_BURST_EN_CH + Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM. 3 1 - write-only + read-write - CORE_0_AREA_PIF_0_RD_CLR - Core0 PIF area0 read monitor interrupt clr + MEM_TRANS_EN_CH + Set this bit 1 to enable automatic transmitting data from memory to memory via AHB_DMA. 4 1 - write-only + read-write - CORE_0_AREA_PIF_0_WR_CLR - Core0 PIF area0 write monitor interrupt clr + IN_ETM_EN_CH + Set this bit to 1 to enable etm control mode, dma Rx channel 0 is triggered by etm task. 5 1 - write-only + read-write + + + + 3 + 0xC0 + IN_CONF1_CH%s + Configure 1 register of Rx channel 0 + 0x74 + 0x20 + - CORE_0_AREA_PIF_1_RD_CLR - Core0 PIF area1 read monitor interrupt clr - 6 + IN_CHECK_OWNER_CH + Set this bit to enable checking the owner attribute of the link descriptor. + 12 1 - write-only + read-write + + + + 3 + 0xC0 + INFIFO_STATUS_CH%s + Receive FIFO status of Rx channel 0 + 0x78 + 0x20 + 0x07800003 + - CORE_0_AREA_PIF_1_WR_CLR - Core0 PIF area1 write monitor interrupt clr - 7 + INFIFO_FULL_CH + L1 Rx FIFO full signal for Rx channel 0. + 0 1 - write-only + read-only - CORE_0_SP_SPILL_MIN_CLR - Core0 stackpoint underflow monitor interrupt clr - 8 + INFIFO_EMPTY_CH + L1 Rx FIFO empty signal for Rx channel 0. + 1 1 - write-only + read-only - CORE_0_SP_SPILL_MAX_CLR - Core0 stackpoint overflow monitor interrupt clr - 9 + INFIFO_CNT_CH + The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0. + 2 + 6 + read-only + + + IN_REMAIN_UNDER_1B_CH + reserved + 23 1 - write-only + read-only - CORE_0_IRAM0_EXCEPTION_MONITOR_CLR - IBUS busy monitor interrupt clr - 10 + IN_REMAIN_UNDER_2B_CH + reserved + 24 1 - write-only + read-only - CORE_0_DRAM0_EXCEPTION_MONITOR_CLR - DBUS busy monitor interrupt clr - 11 + IN_REMAIN_UNDER_3B_CH + reserved + 25 1 - write-only + read-only - - - - CORE_0_AREA_DRAM0_0_MIN - core0 dram0 region0 addr configuration register - 0x10 - 0x20 - 0xFFFFFFFF - - CORE_0_AREA_DRAM0_0_MIN - Core0 dram0 region0 start addr - 0 - 32 - read-write + IN_REMAIN_UNDER_4B_CH + reserved + 26 + 1 + read-only - - - - CORE_0_AREA_DRAM0_0_MAX - core0 dram0 region0 addr configuration register - 0x14 - 0x20 - - CORE_0_AREA_DRAM0_0_MAX - Core0 dram0 region0 end addr - 0 - 32 - read-write + IN_BUF_HUNGRY_CH + reserved + 27 + 1 + read-only - CORE_0_AREA_DRAM0_1_MIN - core0 dram0 region1 addr configuration register - 0x18 + 3 + 0xC0 + IN_POP_CH%s + Pop control register of Rx channel 0 + 0x7C 0x20 - 0xFFFFFFFF + 0x00000800 - CORE_0_AREA_DRAM0_1_MIN - Core0 dram0 region1 start addr + INFIFO_RDATA_CH + This register stores the data popping from AHB_DMA FIFO. 0 - 32 - read-write + 12 + read-only - - - - CORE_0_AREA_DRAM0_1_MAX - core0 dram0 region1 addr configuration register - 0x1C - 0x20 - - CORE_0_AREA_DRAM0_1_MAX - Core0 dram0 region1 end addr - 0 - 32 - read-write + INFIFO_POP_CH + Set this bit to pop data from AHB_DMA FIFO. + 12 + 1 + write-only - CORE_0_AREA_PIF_0_MIN - core0 PIF region0 addr configuration register - 0x20 + 3 + 0xC0 + IN_LINK_CH%s + Link descriptor configure and control register of Rx channel 0 + 0x80 0x20 - 0xFFFFFFFF + 0x00000011 - CORE_0_AREA_PIF_0_MIN - Core0 PIF region0 start addr + INLINK_AUTO_RET_CH + Set this bit to return to current inlink descriptor's address when there are some errors in current receiving data. 0 - 32 + 1 read-write + + INLINK_STOP_CH + Set this bit to stop dealing with the inlink descriptors. + 1 + 1 + write-only + + + INLINK_START_CH + Set this bit to start dealing with the inlink descriptors. + 2 + 1 + write-only + + + INLINK_RESTART_CH + Set this bit to mount a new inlink descriptor. + 3 + 1 + write-only + + + INLINK_PARK_CH + 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working. + 4 + 1 + read-only + - CORE_0_AREA_PIF_0_MAX - core0 PIF region0 addr configuration register - 0x24 + 3 + 0xC0 + IN_STATE_CH%s + Receive status of Rx channel 0 + 0x84 0x20 - CORE_0_AREA_PIF_0_MAX - Core0 PIF region0 end addr + INLINK_DSCR_ADDR_CH + This register stores the current inlink descriptor's address. 0 - 32 - read-write + 18 + read-only + + + IN_DSCR_STATE_CH + reserved + 18 + 2 + read-only + + + IN_STATE_CH + reserved + 20 + 3 + read-only - CORE_0_AREA_PIF_1_MIN - core0 PIF region1 addr configuration register - 0x28 + 3 + 0xC0 + IN_SUC_EOF_DES_ADDR_CH%s + Inlink descriptor address when EOF occurs of Rx channel 0 + 0x88 0x20 - 0xFFFFFFFF - CORE_0_AREA_PIF_1_MIN - Core0 PIF region1 start addr + IN_SUC_EOF_DES_ADDR_CH + This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. 0 32 - read-write + read-only - CORE_0_AREA_PIF_1_MAX - core0 PIF region1 addr configuration register - 0x2C + 3 + 0xC0 + IN_ERR_EOF_DES_ADDR_CH%s + Inlink descriptor address when errors occur of Rx channel 0 + 0x8C 0x20 - CORE_0_AREA_PIF_1_MAX - Core0 PIF region1 end addr + IN_ERR_EOF_DES_ADDR_CH + This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0. 0 32 - read-write + read-only - CORE_0_AREA_PC - core0 area pc status register - 0x30 + 3 + 0xC0 + IN_DSCR_CH%s + Current inlink descriptor address of Rx channel 0 + 0x90 0x20 - CORE_0_AREA_PC - the stackpointer when first touch region monitor interrupt + INLINK_DSCR_CH + The address of the current inlink descriptor x. 0 32 read-only @@ -2354,14 +2343,16 @@ - CORE_0_AREA_SP - core0 area sp status register - 0x34 + 3 + 0xC0 + IN_DSCR_BF0_CH%s + The last inlink descriptor address of Rx channel 0 + 0x94 0x20 - CORE_0_AREA_SP - the PC when first touch region monitor interrupt + INLINK_DSCR_BF0_CH + The address of the last inlink descriptor x-1. 0 32 read-only @@ -2369,207 +2360,297 @@ - CORE_0_SP_MIN - stack min value - 0x38 + 3 + 0xC0 + IN_DSCR_BF1_CH%s + The second-to-last inlink descriptor address of Rx channel 0 + 0x98 0x20 - CORE_0_SP_MIN - core0 sp region configuration regsiter + INLINK_DSCR_BF1_CH + The address of the second-to-last inlink descriptor x-2. 0 32 - read-write + read-only - CORE_0_SP_MAX - stack max value - 0x3C + 3 + 0xC0 + IN_PRI_CH%s + Priority register of Rx channel 0 + 0x9C 0x20 - 0xFFFFFFFF - CORE_0_SP_MAX - core0 sp pc status register + RX_PRI_CH + The priority of Rx channel 0. The larger of the value the higher of the priority. 0 - 32 + 4 read-write - CORE_0_SP_PC - stack monitor pc status register - 0x40 + 3 + 0xC0 + IN_PERI_SEL_CH%s + Peripheral selection of Rx channel 0 + 0xA0 0x20 + 0x0000003F - CORE_0_SP_PC - This regsiter stores the PC when trigger stack monitor. + PERI_IN_SEL_CH + This register is used to select peripheral for Rx channel 0. I3C. 1: Dummy. 2: UHCI0. 3: I2S0. 4: I2S1. 5: I2S2. 6: Dummy. 7: Dummy. 8: ADC_DAC. 9: Dummy. 10: RMT,11~15: Dummy 0 - 32 - read-only + 6 + read-write - CORE_0_RCD_EN - record enable configuration register - 0x44 + OUT_CONF0_CH0 + Configure 0 register of Tx channel 0 + 0xD0 0x20 + 0x00000008 - CORE_0_RCD_RECORDEN - Set 1 to enable record PC + OUT_RST_CH0 + This bit is used to reset AHB_DMA channel 0 Tx FSM and Tx FIFO pointer. 0 1 read-write - CORE_0_RCD_PDEBUGEN - Set 1 to enable cpu pdebug function, must set this bit can get cpu PC + OUT_LOOP_TEST_CH0 + reserved 1 1 read-write + + OUT_AUTO_WRBACK_CH0 + Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted. + 2 + 1 + read-write + + + OUT_EOF_MODE_CH0 + EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in AHB_DMA + 3 + 1 + read-write + + + OUTDSCR_BURST_EN_CH0 + Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM. + 4 + 1 + read-write + + + OUT_DATA_BURST_EN_CH0 + Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM. + 5 + 1 + read-write + + + OUT_ETM_EN_CH0 + Set this bit to 1 to enable etm control mode, dma Tx channel 0 is triggered by etm task. + 6 + 1 + read-write + - CORE_0_RCD_PDEBUGPC - record status regsiter - 0x48 + 3 + 0xC0 + OUT_CONF1_CH%s + Configure 1 register of Tx channel 0 + 0xD4 0x20 - CORE_0_RCD_PDEBUGPC - recorded PC - 0 - 32 - read-only + OUT_CHECK_OWNER_CH + Set this bit to enable checking the owner attribute of the link descriptor. + 12 + 1 + read-write - CORE_0_RCD_PDEBUGSP - record status regsiter - 0x4C + 3 + 0xC0 + OUTFIFO_STATUS_CH%s + Transmit FIFO status of Tx channel 0 + 0xD8 0x20 + 0x07800002 - CORE_0_RCD_PDEBUGSP - recorded sp + OUTFIFO_FULL_CH + L1 Tx FIFO full signal for Tx channel 0. 0 - 32 + 1 read-only - - - - CORE_0_IRAM0_EXCEPTION_MONITOR_0 - exception monitor status register0 - 0x50 - 0x20 - - CORE_0_IRAM0_RECORDING_ADDR_0 - reg_core_0_iram0_recording_addr_0 - 0 - 24 + OUTFIFO_EMPTY_CH + L1 Tx FIFO empty signal for Tx channel 0. + 1 + 1 read-only - CORE_0_IRAM0_RECORDING_WR_0 - reg_core_0_iram0_recording_wr_0 + OUTFIFO_CNT_CH + The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0. + 2 + 6 + read-only + + + OUT_REMAIN_UNDER_1B_CH + reserved + 23 + 1 + read-only + + + OUT_REMAIN_UNDER_2B_CH + reserved 24 1 read-only - CORE_0_IRAM0_RECORDING_LOADSTORE_0 - reg_core_0_iram0_recording_loadstore_0 + OUT_REMAIN_UNDER_3B_CH + reserved 25 1 read-only + + OUT_REMAIN_UNDER_4B_CH + reserved + 26 + 1 + read-only + - CORE_0_IRAM0_EXCEPTION_MONITOR_1 - exception monitor status register1 - 0x54 + 3 + 0xC0 + OUT_PUSH_CH%s + Push control register of Rx channel 0 + 0xDC 0x20 - CORE_0_IRAM0_RECORDING_ADDR_1 - reg_core_0_iram0_recording_addr_1 + OUTFIFO_WDATA_CH + This register stores the data that need to be pushed into AHB_DMA FIFO. 0 - 24 - read-only - - - CORE_0_IRAM0_RECORDING_WR_1 - reg_core_0_iram0_recording_wr_1 - 24 - 1 - read-only + 9 + read-write - CORE_0_IRAM0_RECORDING_LOADSTORE_1 - reg_core_0_iram0_recording_loadstore_1 - 25 + OUTFIFO_PUSH_CH + Set this bit to push data into AHB_DMA FIFO. + 9 1 - read-only + write-only - CORE_0_DRAM0_EXCEPTION_MONITOR_0 - exception monitor status register2 - 0x58 + 3 + 0xC0 + OUT_LINK_CH%s + Link descriptor configure and control register of Tx channel 0 + 0xE0 0x20 + 0x00000008 - CORE_0_DRAM0_RECORDING_WR_0 - reg_core_0_dram0_recording_wr_0 + OUTLINK_STOP_CH + Set this bit to stop dealing with the outlink descriptors. 0 1 - read-only + write-only - CORE_0_DRAM0_RECORDING_BYTEEN_0 - reg_core_0_dram0_recording_byteen_0 + OUTLINK_START_CH + Set this bit to start dealing with the outlink descriptors. 1 - 16 + 1 + write-only + + + OUTLINK_RESTART_CH + Set this bit to restart a new outlink from the last address. + 2 + 1 + write-only + + + OUTLINK_PARK_CH + 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working. + 3 + 1 read-only - CORE_0_DRAM0_EXCEPTION_MONITOR_1 - exception monitor status register3 - 0x5C + 3 + 0xC0 + OUT_STATE_CH%s + Transmit status of Tx channel 0 + 0xE4 0x20 - CORE_0_DRAM0_RECORDING_ADDR_0 - reg_core_0_dram0_recording_addr_0 + OUTLINK_DSCR_ADDR_CH + This register stores the current outlink descriptor's address. 0 - 24 + 18 + read-only + + + OUT_DSCR_STATE_CH + reserved + 18 + 2 + read-only + + + OUT_STATE_CH + reserved + 20 + 3 read-only - CORE_0_DRAM0_EXCEPTION_MONITOR_2 - exception monitor status register4 - 0x60 + 3 + 0xC0 + OUT_EOF_DES_ADDR_CH%s + Outlink descriptor address when EOF occurs of Tx channel 0 + 0xE8 0x20 - CORE_0_DRAM0_RECORDING_PC_0 - reg_core_0_dram0_recording_pc_0 + OUT_EOF_DES_ADDR_CH + This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1. 0 32 read-only @@ -2577,51 +2658,50 @@ - CORE_0_DRAM0_EXCEPTION_MONITOR_3 - exception monitor status register5 - 0x64 + 3 + 0xC0 + OUT_EOF_BFR_DES_ADDR_CH%s + The last outlink descriptor address when EOF occurs of Tx channel 0 + 0xEC 0x20 - CORE_0_DRAM0_RECORDING_WR_1 - reg_core_0_dram0_recording_wr_1 + OUT_EOF_BFR_DES_ADDR_CH + This register stores the address of the outlink descriptor before the last outlink descriptor. 0 - 1 - read-only - - - CORE_0_DRAM0_RECORDING_BYTEEN_1 - reg_core_0_dram0_recording_byteen_1 - 1 - 16 + 32 read-only - CORE_0_DRAM0_EXCEPTION_MONITOR_4 - exception monitor status register6 - 0x68 + 3 + 0xC0 + OUT_DSCR_CH%s + Current inlink descriptor address of Tx channel 0 + 0xF0 0x20 - CORE_0_DRAM0_RECORDING_ADDR_1 - reg_core_0_dram0_recording_addr_1 + OUTLINK_DSCR_CH + The address of the current outlink descriptor y. 0 - 24 + 32 read-only - CORE_0_DRAM0_EXCEPTION_MONITOR_5 - exception monitor status register7 - 0x6C + 3 + 0xC0 + OUT_DSCR_BF0_CH%s + The last inlink descriptor address of Tx channel 0 + 0xF4 0x20 - CORE_0_DRAM0_RECORDING_PC_1 - reg_core_0_dram0_recording_pc_1 + OUTLINK_DSCR_BF0_CH + The address of the last outlink descriptor y-1. 0 32 read-only @@ -2629,14 +2709,16 @@ - CORE_0_LASTPC_BEFORE_EXCEPTION - cpu status register - 0x70 + 3 + 0xC0 + OUT_DSCR_BF1_CH%s + The second-to-last inlink descriptor address of Tx channel 0 + 0xF8 0x20 - CORE_0_LASTPC_BEFORE_EXC - cpu's lastpc before exception + OUTLINK_DSCR_BF1_CH + The address of the second-to-last inlink descriptor x-2. 0 32 read-only @@ -2644,436 +2726,365 @@ - CORE_0_DEBUG_MODE - cpu status register - 0x74 + 3 + 0xC0 + OUT_PRI_CH%s + Priority register of Tx channel 0. + 0xFC 0x20 - CORE_0_DEBUG_MODE - cpu debug mode status, 1 means cpu enter debug mode. + TX_PRI_CH + The priority of Tx channel 0. The larger of the value the higher of the priority. 0 - 1 - read-only + 4 + read-write + + + + 3 + 0xC0 + OUT_PERI_SEL_CH%s + Peripheral selection of Tx channel 0 + 0x100 + 0x20 + 0x0000003F + - CORE_0_DEBUG_MODULE_ACTIVE - cpu debug_module active status - 1 - 1 - read-only + PERI_OUT_SEL_CH + This register is used to select peripheral for Tx channel 0. I3C. 1: Dummy. 2: UHCI0. 3: I2S0. 4: I2S1. 5: I2S2. 6: Dummy. 7: Dummy. 8: ADC_DAC. 9: Dummy. 10: RMT,11~15: Dummy + 0 + 6 + read-write - CORE_1_INTR_ENA - core1 monitor enable configuration register - 0x80 + 2 + 0xC0 + OUT_CONF0_CH%s + Configure 0 register of Tx channel 1 + 0x190 0x20 + 0x00000008 - CORE_1_AREA_DRAM0_0_RD_ENA - Core1 dram0 area0 read monitor enable + OUT_RST_CH + This bit is used to reset AHB_DMA channel 1 Tx FSM and Tx FIFO pointer. 0 1 read-write - CORE_1_AREA_DRAM0_0_WR_ENA - Core1 dram0 area0 write monitor enable + OUT_LOOP_TEST_CH + reserved 1 1 read-write - CORE_1_AREA_DRAM0_1_RD_ENA - Core1 dram0 area1 read monitor enable + OUT_AUTO_WRBACK_CH + Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted. 2 1 read-write - CORE_1_AREA_DRAM0_1_WR_ENA - Core1 dram0 area1 write monitor enable + OUT_EOF_MODE_CH + EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 1 is generated when data need to transmit has been popped from FIFO in AHB_DMA 3 1 read-write - CORE_1_AREA_PIF_0_RD_ENA - Core1 PIF area0 read monitor enable + OUTDSCR_BURST_EN_CH + Set this bit to 1 to enable INCR burst transfer for Tx channel 1 reading link descriptor when accessing internal SRAM. 4 1 read-write - CORE_1_AREA_PIF_0_WR_ENA - Core1 PIF area0 write monitor enable + OUT_DATA_BURST_EN_CH + Set this bit to 1 to enable INCR burst transfer for Tx channel 1 transmitting data when accessing internal SRAM. 5 1 read-write - CORE_1_AREA_PIF_1_RD_ENA - Core1 PIF area1 read monitor enable + OUT_ETM_EN_CH + Set this bit to 1 to enable etm control mode, dma Tx channel 1 is triggered by etm task. 6 1 read-write + + + + 3 + 0x28 + OUT_CRC_INIT_DATA_CH%s + This register is used to config ch0 crc initial data(max 32 bit) + 0x2BC + 0x20 + 0xFFFFFFFF + - CORE_1_AREA_PIF_1_WR_ENA - Core1 PIF area1 write monitor enable - 7 - 1 - read-write - - - CORE_1_SP_SPILL_MIN_ENA - Core1 stackpoint underflow monitor enable - 8 - 1 + OUT_CRC_INIT_DATA_CH + This register is used to config ch0 of tx crc initial value + 0 + 32 read-write + + + + 3 + 0x28 + TX_CRC_WIDTH_CH%s + This register is used to confiig tx ch0 crc result width,2'b00 mean crc_width <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean 24<crc_width<=32 + 0x2C0 + 0x20 + - CORE_1_SP_SPILL_MAX_ENA - Core1 stackpoint overflow monitor enable - 9 - 1 + TX_CRC_WIDTH_CH + reserved + 0 + 2 read-write - CORE_1_IRAM0_EXCEPTION_MONITOR_ENA - IBUS busy monitor enable - 10 + TX_CRC_LAUTCH_FLGA_CH + reserved + 2 1 read-write + + + + 3 + 0x28 + OUT_CRC_CLEAR_CH%s + This register is used to clear ch0 crc result + 0x2C4 + 0x20 + - CORE_1_DRAM0_EXCEPTION_MONITOR_ENA - DBUS busy monitor enbale - 11 + OUT_CRC_CLEAR_CH + This register is used to clear ch0 of tx crc result + 0 1 read-write - CORE_1_INTR_RAW - core1 monitor interrupt status register - 0x84 + 3 + 0x28 + OUT_CRC_FINAL_RESULT_CH%s + This register is used to store ch0 crc result + 0x2C8 0x20 - CORE_1_AREA_DRAM0_0_RD_RAW - Core1 dram0 area0 read monitor interrupt status + OUT_CRC_FINAL_RESULT_CH + This register is used to store result ch0 of tx 0 - 1 - read-only - - - CORE_1_AREA_DRAM0_0_WR_RAW - Core1 dram0 area0 write monitor interrupt status - 1 - 1 - read-only - - - CORE_1_AREA_DRAM0_1_RD_RAW - Core1 dram0 area1 read monitor interrupt status - 2 - 1 - read-only - - - CORE_1_AREA_DRAM0_1_WR_RAW - Core1 dram0 area1 write monitor interrupt status - 3 - 1 - read-only - - - CORE_1_AREA_PIF_0_RD_RAW - Core1 PIF area0 read monitor interrupt status - 4 - 1 - read-only - - - CORE_1_AREA_PIF_0_WR_RAW - Core1 PIF area0 write monitor interrupt status - 5 - 1 - read-only - - - CORE_1_AREA_PIF_1_RD_RAW - Core1 PIF area1 read monitor interrupt status - 6 - 1 - read-only - - - CORE_1_AREA_PIF_1_WR_RAW - Core1 PIF area1 write monitor interrupt status - 7 - 1 - read-only - - - CORE_1_SP_SPILL_MIN_RAW - Core1 stackpoint underflow monitor interrupt status - 8 - 1 - read-only - - - CORE_1_SP_SPILL_MAX_RAW - Core1 stackpoint overflow monitor interrupt status - 9 - 1 - read-only - - - CORE_1_IRAM0_EXCEPTION_MONITOR_RAW - IBUS busy monitor interrupt status - 10 - 1 - read-only - - - CORE_1_DRAM0_EXCEPTION_MONITOR_RAW - DBUS busy monitor initerrupt status - 11 - 1 + 32 read-only - CORE_1_INTR_RLS - core1 monitor interrupt enable register - 0x88 + 3 + 0x28 + TX_CRC_EN_WR_DATA_CH%s + This resister is used to config ch0 crc en for every bit + 0x2CC 0x20 - CORE_1_AREA_DRAM0_0_RD_RLS - Core1 dram0 area0 read monitor interrupt enable + TX_CRC_EN_WR_DATA_CH + This register is used to enable tx ch0 crc 32bit on/off 0 - 1 - read-write - - - CORE_1_AREA_DRAM0_0_WR_RLS - Core1 dram0 area0 write monitor interrupt enable - 1 - 1 - read-write - - - CORE_1_AREA_DRAM0_1_RD_RLS - Core1 dram0 area1 read monitor interrupt enable - 2 - 1 - read-write - - - CORE_1_AREA_DRAM0_1_WR_RLS - Core1 dram0 area1 write monitor interrupt enable - 3 - 1 - read-write - - - CORE_1_AREA_PIF_0_RD_RLS - Core1 PIF area0 read monitor interrupt enable - 4 - 1 - read-write - - - CORE_1_AREA_PIF_0_WR_RLS - Core1 PIF area0 write monitor interrupt enable - 5 - 1 + 32 read-write + + + + 3 + 0x28 + TX_CRC_EN_ADDR_CH%s + This register is used to config ch0 crc en addr + 0x2D0 + 0x20 + - CORE_1_AREA_PIF_1_RD_RLS - Core1 PIF area1 read monitor interrupt enable - 6 - 1 + TX_CRC_EN_ADDR_CH + reserved + 0 + 32 read-write + + + + 3 + 0x28 + TX_CRC_DATA_EN_WR_DATA_CH%s + This register is used to config crc data_8bit en + 0x2D4 + 0x20 + - CORE_1_AREA_PIF_1_WR_RLS - Core1 PIF area1 write monitor interrupt enable - 7 - 1 + TX_CRC_DATA_EN_WR_DATA_CH + reserved + 0 + 8 read-write + + + + 3 + 0x28 + TX_CRC_DATA_EN_ADDR_CH%s + This register is used to config addr of crc data_8bit en + 0x2D8 + 0x20 + - CORE_1_SP_SPILL_MIN_RLS - Core1 stackpoint underflow monitor interrupt enable - 8 - 1 + TX_CRC_DATA_EN_ADDR_CH + reserved + 0 + 32 read-write + + + + 3 + 0x28 + TX_CH_ARB_WEIGH_CH%s + This register is used to config ch0 arbiter weigh + 0x2DC + 0x20 + - CORE_1_SP_SPILL_MAX_RLS - Core1 stackpoint overflow monitor interrupt enable - 9 - 1 + TX_CH_ARB_WEIGH_CH + reserved + 0 + 4 read-write + + + + 3 + 0x28 + TX_ARB_WEIGH_OPT_DIR_CH%s + This register is used to config off or on weigh optimization + 0x2E0 + 0x20 + - CORE_1_IRAM0_EXCEPTION_MONITOR_RLS - IBUS busy monitor interrupt enable - 10 + TX_ARB_WEIGH_OPT_DIR_CH + reserved + 0 1 read-write + + + + 3 + 0x28 + IN_CRC_INIT_DATA_CH%s + This register is used to config ch0 crc initial data(max 32 bit) + 0x334 + 0x20 + 0xFFFFFFFF + - CORE_1_DRAM0_EXCEPTION_MONITOR_RLS - DBUS busy monitor interrupt enbale - 11 - 1 + IN_CRC_INIT_DATA_CH + This register is used to config ch0 of rx crc initial value + 0 + 32 read-write - CORE_1_INTR_CLR - core1 monitor interrupt clr register - 0x8C + 3 + 0x28 + RX_CRC_WIDTH_CH%s + This register is used to confiig rx ch0 crc result width,2'b00 mean crc_width <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean 24<crc_width<=32 + 0x338 0x20 - CORE_1_AREA_DRAM0_0_RD_CLR - Core1 dram0 area0 read monitor interrupt clr + RX_CRC_WIDTH_CH + reserved 0 - 1 - write-only - - - CORE_1_AREA_DRAM0_0_WR_CLR - Core1 dram0 area0 write monitor interrupt clr - 1 - 1 - write-only + 2 + read-write - CORE_1_AREA_DRAM0_1_RD_CLR - Core1 dram0 area1 read monitor interrupt clr + RX_CRC_LAUTCH_FLGA_CH + reserved 2 1 - write-only - - - CORE_1_AREA_DRAM0_1_WR_CLR - Core1 dram0 area1 write monitor interrupt clr - 3 - 1 - write-only - - - CORE_1_AREA_PIF_0_RD_CLR - Core1 PIF area0 read monitor interrupt clr - 4 - 1 - write-only - - - CORE_1_AREA_PIF_0_WR_CLR - Core1 PIF area0 write monitor interrupt clr - 5 - 1 - write-only - - - CORE_1_AREA_PIF_1_RD_CLR - Core1 PIF area1 read monitor interrupt clr - 6 - 1 - write-only - - - CORE_1_AREA_PIF_1_WR_CLR - Core1 PIF area1 write monitor interrupt clr - 7 - 1 - write-only - - - CORE_1_SP_SPILL_MIN_CLR - Core1 stackpoint underflow monitor interrupt clr - 8 - 1 - write-only - - - CORE_1_SP_SPILL_MAX_CLR - Core1 stackpoint overflow monitor interrupt clr - 9 - 1 - write-only - - - CORE_1_IRAM0_EXCEPTION_MONITOR_CLR - IBUS busy monitor interrupt clr - 10 - 1 - write-only - - - CORE_1_DRAM0_EXCEPTION_MONITOR_CLR - DBUS busy monitor interrupt clr - 11 - 1 - write-only + read-write - CORE_1_AREA_DRAM0_0_MIN - core1 dram0 region0 addr configuration register - 0x90 + 3 + 0x28 + IN_CRC_CLEAR_CH%s + This register is used to clear ch0 crc result + 0x33C 0x20 - 0xFFFFFFFF - CORE_1_AREA_DRAM0_0_MIN - Core1 dram0 region0 start addr + IN_CRC_CLEAR_CH + This register is used to clear ch0 of rx crc result 0 - 32 + 1 read-write - CORE_1_AREA_DRAM0_0_MAX - core1 dram0 region0 addr configuration register - 0x94 + 3 + 0x28 + IN_CRC_FINAL_RESULT_CH%s + This register is used to store ch0 crc result + 0x340 0x20 - CORE_1_AREA_DRAM0_0_MAX - Core1 dram0 region0 end addr + IN_CRC_FINAL_RESULT_CH + This register is used to store result ch0 of rx 0 32 - read-write + read-only - CORE_1_AREA_DRAM0_1_MIN - core1 dram0 region1 addr configuration register - 0x98 + 3 + 0x28 + RX_CRC_EN_WR_DATA_CH%s + This resister is used to config ch0 crc en for every bit + 0x344 0x20 - 0xFFFFFFFF - CORE_1_AREA_DRAM0_1_MIN - Core1 dram0 region1 start addr + RX_CRC_EN_WR_DATA_CH + This register is used to enable rx ch0 crc 32bit on/off 0 32 read-write @@ -3081,14 +3092,16 @@ - CORE_1_AREA_DRAM0_1_MAX - core1 dram0 region1 addr configuration register - 0x9C + 3 + 0x28 + RX_CRC_EN_ADDR_CH%s + This register is used to config ch0 crc en addr + 0x348 0x20 - CORE_1_AREA_DRAM0_1_MAX - Core1 dram0 region1 end addr + RX_CRC_EN_ADDR_CH + reserved 0 32 read-write @@ -3096,30 +3109,33 @@ - CORE_1_AREA_PIF_0_MIN - core1 PIF region0 addr configuration register - 0xA0 + 3 + 0x28 + RX_CRC_DATA_EN_WR_DATA_CH%s + This register is used to config crc data_8bit en + 0x34C 0x20 - 0xFFFFFFFF - CORE_1_AREA_PIF_0_MIN - Core1 PIF region0 start addr + RX_CRC_DATA_EN_WR_DATA_CH + reserved 0 - 32 + 8 read-write - CORE_1_AREA_PIF_0_MAX - core1 PIF region0 addr configuration register - 0xA4 + 3 + 0x28 + RX_CRC_DATA_EN_ADDR_CH%s + This register is used to config addr of crc data_8bit en + 0x350 0x20 - CORE_1_AREA_PIF_0_MAX - Core1 PIF region0 end addr + RX_CRC_DATA_EN_ADDR_CH + reserved 0 32 read-write @@ -3127,75 +3143,82 @@ - CORE_1_AREA_PIF_1_MIN - core1 PIF region1 addr configuration register - 0xA8 + 3 + 0x28 + RX_CH_ARB_WEIGH_CH%s + This register is used to config ch0 arbiter weigh + 0x354 0x20 - 0xFFFFFFFF - CORE_1_AREA_PIF_1_MIN - Core1 PIF region1 start addr + RX_CH_ARB_WEIGH_CH + reserved 0 - 32 + 4 read-write - CORE_1_AREA_PIF_1_MAX - core1 PIF region1 addr configuration register - 0xAC + 3 + 0x28 + RX_ARB_WEIGH_OPT_DIR_CH%s + This register is used to config off or on weigh optimization + 0x358 0x20 - CORE_1_AREA_PIF_1_MAX - Core1 PIF region1 end addr + RX_ARB_WEIGH_OPT_DIR_CH + reserved 0 - 32 + 1 read-write - CORE_1_AREA_PC - core1 area pc status register - 0xB0 + 3 + 0x4 + IN_LINK_ADDR_CH%s + Link descriptor configure of Rx channel 0 + 0x3AC 0x20 - CORE_1_AREA_PC - the stackpointer when first touch region monitor interrupt + INLINK_ADDR_CH + This register stores the 32 least significant bits of the first inlink descriptor's address. 0 32 - read-only + read-write - CORE_1_AREA_SP - core1 area sp status register - 0xB4 + 3 + 0x4 + OUT_LINK_ADDR_CH%s + Link descriptor configure of Tx channel 0 + 0x3B8 0x20 - CORE_1_AREA_SP - the PC when first touch region monitor interrupt + OUTLINK_ADDR_CH + This register stores the 32 least significant bits of the first outlink descriptor's address. 0 32 - read-only + read-write - CORE_1_SP_MIN - stack min value - 0xB8 + INTR_MEM_START_ADDR + The start address of accessible address space. + 0x3C4 0x20 - CORE_1_SP_MIN - core1 sp region configuration regsiter + ACCESS_INTR_MEM_START_ADDR + The start address of accessible address space. 0 32 read-write @@ -3203,15 +3226,15 @@ - CORE_1_SP_MAX - stack max value - 0xBC + INTR_MEM_END_ADDR + The end address of accessible address space. The access address beyond this range would lead to descriptor error. + 0x3C8 0x20 0xFFFFFFFF - CORE_1_SP_MAX - core1 sp pc status register + ACCESS_INTR_MEM_END_ADDR + The end address of accessible address space. The access address beyond this range would lead to descriptor error. 0 32 read-write @@ -3219,95 +3242,94 @@ - CORE_1_SP_PC - stack monitor pc status register - 0xC0 + ARB_TIMEOUT_TX + This retister is used to config arbiter time slice for tx dir + 0x3CC 0x20 - CORE_1_SP_PC - This regsiter stores the PC when trigger stack monitor. + ARB_TIMEOUT_TX + This register is used to config arbiter time out value 0 - 32 - read-only + 16 + read-write - CORE_1_RCD_EN - record enable configuration register - 0xC4 + ARB_TIMEOUT_RX + This retister is used to config arbiter time slice for rx dir + 0x3D0 0x20 - CORE_1_RCD_RECORDEN - Set 1 to enable record PC + ARB_TIMEOUT_RX + This register is used to config arbiter time out value 0 - 1 - read-write - - - CORE_1_RCD_PDEBUGEN - Set 1 to enable cpu pdebug function, must set this bit can get cpu PC - 1 - 1 + 16 read-write - CORE_1_RCD_PDEBUGPC - record status regsiter - 0xC8 + WEIGHT_EN_TX + This register is used to config arbiter weigh function to on or off for tx dir + 0x3D4 0x20 - CORE_1_RCD_PDEBUGPC - recorded PC + WEIGHT_EN_TX + This register is used to config arbiter weight function off/on 0 - 32 - read-only + 1 + read-write - CORE_1_RCD_PDEBUGSP - record status regsiter - 0xCC + WEIGHT_EN_RX + This register is used to config arbiter weigh function to on or off for rx dir + 0x3D8 0x20 - CORE_1_RCD_PDEBUGSP - recorded sp + WEIGHT_EN_RX + This register is used to config arbiter weight function off/on 0 - 32 - read-only + 1 + read-write + + + + LP_I2C_ANA_MST + LP_I2C_ANA_MST Peripheral + ANA_I2C_MST + 0x50124000 + + 0x0 + 0x3C + registers + + - CORE_1_IRAM0_EXCEPTION_MONITOR_0 - exception monitor status register0 - 0xD0 + I2C0_CTRL + need des + 0x0 0x20 - CORE_1_IRAM0_RECORDING_ADDR_0 - reg_core_1_iram0_recording_addr_0 + I2C0_CTRL + need des 0 - 24 - read-only - - - CORE_1_IRAM0_RECORDING_WR_0 - reg_core_1_iram0_recording_wr_0 - 24 - 1 - read-only + 25 + read-write - CORE_1_IRAM0_RECORDING_LOADSTORE_0 - reg_core_1_iram0_recording_loadstore_0 + I2C0_BUSY + need des 25 1 read-only @@ -3315,28 +3337,21 @@ - CORE_1_IRAM0_EXCEPTION_MONITOR_1 - exception monitor status register1 - 0xD4 + I2C1_CTRL + need des + 0x4 0x20 - CORE_1_IRAM0_RECORDING_ADDR_1 - reg_core_1_iram0_recording_addr_1 + I2C1_CTRL + need des 0 - 24 - read-only - - - CORE_1_IRAM0_RECORDING_WR_1 - reg_core_1_iram0_recording_wr_1 - 24 - 1 - read-only + 25 + read-write - CORE_1_IRAM0_RECORDING_LOADSTORE_1 - reg_core_1_iram0_recording_loadstore_1 + I2C1_BUSY + need des 25 1 read-only @@ -3344,186 +3359,267 @@ - CORE_1_DRAM0_EXCEPTION_MONITOR_0 - exception monitor status register2 - 0xD8 + I2C0_CONF + need des + 0x8 0x20 - CORE_1_DRAM0_RECORDING_WR_0 - reg_core_1_dram0_recording_wr_0 + I2C0_CONF + need des 0 - 1 - read-only + 24 + read-write - CORE_1_DRAM0_RECORDING_BYTEEN_0 - reg_core_1_dram0_recording_byteen_0 - 1 - 16 + I2C0_STATUS + need des + 24 + 8 read-only - CORE_1_DRAM0_EXCEPTION_MONITOR_1 - exception monitor status register3 - 0xDC + I2C1_CONF + need des + 0xC 0x20 - CORE_1_DRAM0_RECORDING_ADDR_0 - reg_core_1_dram0_recording_addr_0 + I2C1_CONF + need des 0 24 + read-write + + + I2C1_STATUS + need des + 24 + 8 read-only - CORE_1_DRAM0_EXCEPTION_MONITOR_2 - exception monitor status register4 - 0xE0 + I2C_BURST_CONF + need des + 0x10 0x20 - CORE_1_DRAM0_RECORDING_PC_0 - reg_core_1_dram0_recording_pc_0 + I2C_MST_BURST_CTRL + need des 0 32 - read-only + read-write - CORE_1_DRAM0_EXCEPTION_MONITOR_3 - exception monitor status register5 - 0xE4 + I2C_BURST_STATUS + need des + 0x14 0x20 + 0x40000000 - CORE_1_DRAM0_RECORDING_WR_1 - reg_core_1_dram0_recording_wr_1 + I2C_MST_BURST_DONE + need des 0 1 read-only - CORE_1_DRAM0_RECORDING_BYTEEN_1 - reg_core_1_dram0_recording_byteen_1 + I2C_MST0_BURST_ERR_FLAG + need des 1 - 16 + 1 + read-only + + + I2C_MST1_BURST_ERR_FLAG + need des + 2 + 1 read-only + + I2C_MST_BURST_TIMEOUT_CNT + need des + 20 + 12 + read-write + - CORE_1_DRAM0_EXCEPTION_MONITOR_4 - exception monitor status register6 - 0xE8 + ANA_CONF0 + need des + 0x18 0x20 - CORE_1_DRAM0_RECORDING_ADDR_1 - reg_core_1_dram0_recording_addr_1 + ANA_CONF0 + need des 0 24 + read-write + + + ANA_STATUS0 + need des + 24 + 8 read-only - CORE_1_DRAM0_EXCEPTION_MONITOR_5 - exception monitor status register7 - 0xEC + ANA_CONF1 + need des + 0x1C 0x20 - CORE_1_DRAM0_RECORDING_PC_1 - reg_core_1_dram0_recording_pc_1 + ANA_CONF1 + need des 0 - 32 + 24 + read-write + + + ANA_STATUS1 + need des + 24 + 8 read-only - CORE_1_LASTPC_BEFORE_EXCEPTION - cpu status register - 0xF0 + ANA_CONF2 + need des + 0x20 0x20 - CORE_1_LASTPC_BEFORE_EXC - cpu's lastpc before exception + ANA_CONF2 + need des 0 - 32 + 24 + read-write + + + ANA_STATUS2 + need des + 24 + 8 read-only - CORE_1_DEBUG_MODE - cpu status register - 0xF4 + I2C0_CTRL1 + need des + 0x24 0x20 + 0x00000042 - CORE_1_DEBUG_MODE - cpu debug mode status, 1 means cpu enter debug mode. + I2C0_SCL_PULSE_DUR + need des 0 - 1 - read-only + 6 + read-write - CORE_1_DEBUG_MODULE_ACTIVE - cpu debug_module active status - 1 - 1 - read-only + I2C0_SDA_SIDE_GUARD + need des + 6 + 5 + read-write - CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0 - exception monitor status register6 - 0x100 + I2C1_CTRL1 + need des + 0x28 0x20 + 0x00000042 - CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 - reg_core_x_iram0_dram0_limit_cycle_0 + I2C1_SCL_PULSE_DUR + need des 0 - 20 + 6 + read-write + + + I2C1_SDA_SIDE_GUARD + need des + 6 + 5 read-write - CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1 - exception monitor status register7 - 0x104 + HW_I2C_CTRL + need des + 0x2C 0x20 + 0x00000042 - CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 - reg_core_x_iram0_dram0_limit_cycle_1 + HW_I2C_SCL_PULSE_DUR + need des 0 - 20 + 6 + read-write + + + HW_I2C_SDA_SIDE_GUARD + need des + 6 + 5 + read-write + + + ARBITER_DIS + need des + 11 + 1 read-write - CLOCK_GATE - clock register - 0x108 + NOUSE + need des + 0x30 0x20 - 0x00000001 - CLK_EN - Set 1 force on the clock gate + I2C_MST_NOUSE + need des + 0 + 32 + read-write + + + + + CLK160M + need des + 0x34 + 0x20 + + + CLK_I2C_MST_SEL_160M + need des 0 1 read-write @@ -3532,711 +3628,499 @@ DATE - version register - 0x3FC + need des + 0x38 0x20 - 0x02109130 + 0x02201300 - ASSIST_DEBUG_DATE - version register + DATE + need des 0 28 read-write + + I2C_MST_CLK_EN + need des + 28 + 1 + read-write + - AXI_DMA - AXI_DMA Peripheral - AXI_DMA - 0x5008A000 + ASSIST_DEBUG + Debug Assist + ASSIST_DEBUG + 0x3FF06000 0x0 - 0x2D8 + 0x100 registers + + ASSIST_DEBUG + 127 + - 3 - 0x68 - IN_INT_RAW_CH%s - Raw status interrupt of channel 0 + CORE_0_INTR_ENA + core0 monitor enable configuration register 0x0 0x20 - IN_DONE_CH_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. + CORE_0_AREA_DRAM0_0_RD_ENA + Core0 dram0 area0 read monitor enable 0 1 read-write - IN_SUC_EOF_CH_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0. + CORE_0_AREA_DRAM0_0_WR_ENA + Core0 dram0 area0 write monitor enable 1 1 read-write - IN_ERR_EOF_CH_INT_RAW - The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw interrupt is reserved. + CORE_0_AREA_DRAM0_1_RD_ENA + Core0 dram0 area1 read monitor enable 2 1 read-write - IN_DSCR_ERR_CH_INT_RAW - The raw interrupt bit turns to high level when detecting inlink descriptor error including owner error and the second and third word error of inlink descriptor for Rx channel 0. + CORE_0_AREA_DRAM0_1_WR_ENA + Core0 dram0 area1 write monitor enable 3 1 read-write - IN_DSCR_EMPTY_CH_INT_RAW - The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed but there is no more inlink for Rx channel 0. + CORE_0_AREA_PIF_0_RD_ENA + Core0 PIF area0 read monitor enable 4 1 read-write - INFIFO_L1_OVF_CH_INT_RAW - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow. + CORE_0_AREA_PIF_0_WR_ENA + Core0 PIF area0 write monitor enable 5 1 read-write - INFIFO_L1_UDF_CH_INT_RAW - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow. + CORE_0_AREA_PIF_1_RD_ENA + Core0 PIF area1 read monitor enable 6 1 read-write - INFIFO_L2_OVF_CH_INT_RAW - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow. + CORE_0_AREA_PIF_1_WR_ENA + Core0 PIF area1 write monitor enable 7 1 read-write - INFIFO_L2_UDF_CH_INT_RAW - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow. + CORE_0_SP_SPILL_MIN_ENA + Core0 stackpoint underflow monitor enable 8 1 read-write - INFIFO_L3_OVF_CH_INT_RAW - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow. + CORE_0_SP_SPILL_MAX_ENA + Core0 stackpoint overflow monitor enable 9 1 read-write - INFIFO_L3_UDF_CH_INT_RAW - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow. + CORE_0_IRAM0_EXCEPTION_MONITOR_ENA + IBUS busy monitor enable 10 1 read-write + + CORE_0_DRAM0_EXCEPTION_MONITOR_ENA + DBUS busy monitor enbale + 11 + 1 + read-write + - 3 - 0x68 - IN_INT_ST_CH%s - Masked interrupt of channel 0 + CORE_0_INTR_RAW + core0 monitor interrupt status register 0x4 0x20 - IN_DONE_CH_INT_ST - The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + CORE_0_AREA_DRAM0_0_RD_RAW + Core0 dram0 area0 read monitor interrupt status 0 1 read-only - IN_SUC_EOF_CH_INT_ST - The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + CORE_0_AREA_DRAM0_0_WR_RAW + Core0 dram0 area0 write monitor interrupt status 1 1 read-only - IN_ERR_EOF_CH_INT_ST - The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + CORE_0_AREA_DRAM0_1_RD_RAW + Core0 dram0 area1 read monitor interrupt status 2 1 read-only - IN_DSCR_ERR_CH_INT_ST - The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + CORE_0_AREA_DRAM0_1_WR_RAW + Core0 dram0 area1 write monitor interrupt status 3 1 read-only - IN_DSCR_EMPTY_CH_INT_ST - The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + CORE_0_AREA_PIF_0_RD_RAW + Core0 PIF area0 read monitor interrupt status 4 1 read-only - INFIFO_OVF_CH_INT_ST - The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + CORE_0_AREA_PIF_0_WR_RAW + Core0 PIF area0 write monitor interrupt status 5 1 read-only - INFIFO_UDF_CH_INT_ST - The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + CORE_0_AREA_PIF_1_RD_RAW + Core0 PIF area1 read monitor interrupt status 6 1 read-only - INFIFO_L1_OVF_CH_INT_ST - The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. + CORE_0_AREA_PIF_1_WR_RAW + Core0 PIF area1 write monitor interrupt status 7 1 read-only - INFIFO_L1_UDF_CH_INT_ST - The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. + CORE_0_SP_SPILL_MIN_RAW + Core0 stackpoint underflow monitor interrupt status 8 1 read-only - INFIFO_L3_OVF_CH_INT_ST - The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt. + CORE_0_SP_SPILL_MAX_RAW + Core0 stackpoint overflow monitor interrupt status 9 1 read-only - INFIFO_L3_UDF_CH_INT_ST - The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt. + CORE_0_IRAM0_EXCEPTION_MONITOR_RAW + IBUS busy monitor interrupt status 10 1 read-only + + CORE_0_DRAM0_EXCEPTION_MONITOR_RAW + DBUS busy monitor initerrupt status + 11 + 1 + read-only + - 3 - 0x68 - IN_INT_ENA_CH%s - Interrupt enable bits of channel 0 + CORE_0_INTR_RLS + core0 monitor interrupt enable register 0x8 0x20 - IN_DONE_CH_INT_ENA - The interrupt enable bit for the IN_DONE_CH_INT interrupt. + CORE_0_AREA_DRAM0_0_RD_RLS + Core0 dram0 area0 read monitor interrupt enable 0 1 read-write - IN_SUC_EOF_CH_INT_ENA - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + CORE_0_AREA_DRAM0_0_WR_RLS + Core0 dram0 area0 write monitor interrupt enable 1 1 read-write - IN_ERR_EOF_CH_INT_ENA - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + CORE_0_AREA_DRAM0_1_RD_RLS + Core0 dram0 area1 read monitor interrupt enable 2 1 read-write - IN_DSCR_ERR_CH_INT_ENA - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + CORE_0_AREA_DRAM0_1_WR_RLS + Core0 dram0 area1 write monitor interrupt enable 3 1 read-write - IN_DSCR_EMPTY_CH_INT_ENA - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + CORE_0_AREA_PIF_0_RD_RLS + Core0 PIF area0 read monitor interrupt enable 4 1 read-write - INFIFO_L1_OVF_CH_INT_ENA - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + CORE_0_AREA_PIF_0_WR_RLS + Core0 PIF area0 write monitor interrupt enable 5 1 read-write - INFIFO_L1_UDF_CH_INT_ENA - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + CORE_0_AREA_PIF_1_RD_RLS + Core0 PIF area1 read monitor interrupt enable 6 1 read-write - INFIFO_L2_OVF_CH_INT_ENA - The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. + CORE_0_AREA_PIF_1_WR_RLS + Core0 PIF area1 write monitor interrupt enable 7 1 read-write - INFIFO_L2_UDF_CH_INT_ENA - The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. + CORE_0_SP_SPILL_MIN_RLS + Core0 stackpoint underflow monitor interrupt enable 8 1 read-write - INFIFO_L3_OVF_CH_INT_ENA - The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt. + CORE_0_SP_SPILL_MAX_RLS + Core0 stackpoint overflow monitor interrupt enable 9 1 read-write - INFIFO_L3_UDF_CH_INT_ENA - The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt. + CORE_0_IRAM0_EXCEPTION_MONITOR_RLS + IBUS busy monitor interrupt enable 10 1 read-write + + CORE_0_DRAM0_EXCEPTION_MONITOR_RLS + DBUS busy monitor interrupt enbale + 11 + 1 + read-write + - 3 - 0x68 - IN_INT_CLR_CH%s - Interrupt clear bits of channel 0 + CORE_0_INTR_CLR + core0 monitor interrupt clr register 0xC 0x20 - IN_DONE_CH_INT_CLR - Set this bit to clear the IN_DONE_CH_INT interrupt. + CORE_0_AREA_DRAM0_0_RD_CLR + Core0 dram0 area0 read monitor interrupt clr 0 1 write-only - IN_SUC_EOF_CH_INT_CLR - Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + CORE_0_AREA_DRAM0_0_WR_CLR + Core0 dram0 area0 write monitor interrupt clr 1 1 write-only - IN_ERR_EOF_CH_INT_CLR - Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + CORE_0_AREA_DRAM0_1_RD_CLR + Core0 dram0 area1 read monitor interrupt clr 2 1 write-only - IN_DSCR_ERR_CH_INT_CLR - Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. + CORE_0_AREA_DRAM0_1_WR_CLR + Core0 dram0 area1 write monitor interrupt clr 3 1 write-only - IN_DSCR_EMPTY_CH_INT_CLR - Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + CORE_0_AREA_PIF_0_RD_CLR + Core0 PIF area0 read monitor interrupt clr 4 1 write-only - INFIFO_L1_OVF_CH_INT_CLR - Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + CORE_0_AREA_PIF_0_WR_CLR + Core0 PIF area0 write monitor interrupt clr 5 1 write-only - INFIFO_L1_UDF_CH_INT_CLR - Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + CORE_0_AREA_PIF_1_RD_CLR + Core0 PIF area1 read monitor interrupt clr 6 1 write-only - INFIFO_L2_OVF_CH_INT_CLR - Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. + CORE_0_AREA_PIF_1_WR_CLR + Core0 PIF area1 write monitor interrupt clr 7 1 write-only - INFIFO_L2_UDF_CH_INT_CLR - Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. + CORE_0_SP_SPILL_MIN_CLR + Core0 stackpoint underflow monitor interrupt clr 8 1 write-only - INFIFO_L3_OVF_CH_INT_CLR - Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt. + CORE_0_SP_SPILL_MAX_CLR + Core0 stackpoint overflow monitor interrupt clr 9 1 write-only - INFIFO_L3_UDF_CH_INT_CLR - Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt. + CORE_0_IRAM0_EXCEPTION_MONITOR_CLR + IBUS busy monitor interrupt clr 10 1 write-only + + CORE_0_DRAM0_EXCEPTION_MONITOR_CLR + DBUS busy monitor interrupt clr + 11 + 1 + write-only + - 3 - 0x68 - IN_CONF0_CH%s - Configure 0 register of Rx channel 0 + CORE_0_AREA_DRAM0_0_MIN + core0 dram0 region0 addr configuration register 0x10 0x20 + 0xFFFFFFFF - IN_RST_CH - This bit is used to reset AXI_DMA channel 0 Rx FSM and Rx FIFO pointer. + CORE_0_AREA_DRAM0_0_MIN + Core0 dram0 region0 start addr 0 - 1 - read-write - - - IN_LOOP_TEST_CH - reserved - 1 - 1 - read-write - - - MEM_TRANS_EN_CH - Set this bit 1 to enable automatic transmitting data from memory to memory via AXI_DMA. - 2 - 1 - read-write - - - IN_ETM_EN_CH - Set this bit to 1 to enable etm control mode, dma Rx channel 0 is triggered by etm task. - 3 - 1 - read-write - - - IN_BURST_SIZE_SEL_CH - 3'b000-3'b100:burst length 8byte~128byte - 4 - 3 - read-write - - - IN_CMD_DISABLE_CH - 1:mean disable cmd of this ch0 - 7 - 1 - read-write - - - IN_ECC_AEC_EN_CH - 1: mean access ecc or aes domain,0: mean not - 8 - 1 - read-write - - - INDSCR_BURST_EN_CH - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM. - 9 - 1 + 32 read-write - 3 - 0x68 - IN_CONF1_CH%s - Configure 1 register of Rx channel 0 + CORE_0_AREA_DRAM0_0_MAX + core0 dram0 region0 addr configuration register 0x14 0x20 - IN_CHECK_OWNER_CH - Set this bit to enable checking the owner attribute of the link descriptor. - 12 - 1 + CORE_0_AREA_DRAM0_0_MAX + Core0 dram0 region0 end addr + 0 + 32 read-write - 3 - 0x68 - INFIFO_STATUS_CH%s - Receive FIFO status of Rx channel 0 + CORE_0_AREA_DRAM0_1_MIN + core0 dram0 region1 addr configuration register 0x18 0x20 - 0x00008803 + 0xFFFFFFFF - INFIFO_L3_FULL_CH - L3 Rx FIFO full signal for Rx channel 0. + CORE_0_AREA_DRAM0_1_MIN + Core0 dram0 region1 start addr 0 - 1 - read-only - - - INFIFO_L3_EMPTY_CH - L3 Rx FIFO empty signal for Rx channel 0. - 1 - 1 - read-only - - - INFIFO_L3_CNT_CH - The register stores the byte number of the data in L3 Rx FIFO for Rx channel 0. - 2 - 6 - read-only - - - INFIFO_L3_UDF_CH - L3 Rx FIFO under flow signal for Rx channel 0. - 8 - 1 - read-only - - - INFIFO_L3_OVF_CH - L3 Rx FIFO over flow signal for Rx channel 0. - 9 - 1 - read-only - - - INFIFO_L1_FULL_CH - L1 Rx FIFO full signal for Rx channel 0. - 10 - 1 - read-only - - - INFIFO_L1_EMPTY_CH - L1 Rx FIFO empty signal for Rx channel 0. - 11 - 1 - read-only - - - INFIFO_L1_UDF_CH - L1 Rx FIFO under flow signal for Rx channel 0. - 12 - 1 - read-only - - - INFIFO_L1_OVF_CH - L1 Rx FIFO over flow signal for Rx channel 0. - 13 - 1 - read-only - - - INFIFO_L2_FULL_CH - L2 Rx RAM full signal for Rx channel 0. - 14 - 1 - read-only - - - INFIFO_L2_EMPTY_CH - L2 Rx RAM empty signal for Rx channel 0. - 15 - 1 - read-only - - - INFIFO_L2_UDF_CH - L2 Rx FIFO under flow signal for Rx channel 0. - 16 - 1 - read-only - - - INFIFO_L2_OVF_CH - L2 Rx FIFO over flow signal for Rx channel 0. - 17 - 1 - read-only - - - IN_REMAIN_UNDER_1B_CH - reserved - 23 - 1 - read-only - - - IN_REMAIN_UNDER_2B_CH - reserved - 24 - 1 - read-only - - - IN_REMAIN_UNDER_3B_CH - reserved - 25 - 1 - read-only - - - IN_REMAIN_UNDER_4B_CH - reserved - 26 - 1 - read-only - - - IN_REMAIN_UNDER_5B_CH - reserved - 27 - 1 - read-only - - - IN_REMAIN_UNDER_6B_CH - reserved - 28 - 1 - read-only - - - IN_REMAIN_UNDER_7B_CH - reserved - 29 - 1 - read-only - - - IN_REMAIN_UNDER_8B_CH - reserved - 30 - 1 - read-only - - - IN_BUF_HUNGRY_CH - reserved - 31 - 1 - read-only + 32 + read-write - 3 - 0x68 - IN_POP_CH%s - Pop control register of Rx channel 0 + CORE_0_AREA_DRAM0_1_MAX + core0 dram0 region1 addr configuration register 0x1C 0x20 - 0x00000800 - INFIFO_RDATA_CH - This register stores the data popping from AXI_DMA FIFO. + CORE_0_AREA_DRAM0_1_MAX + Core0 dram0 region1 end addr 0 - 12 - read-only - - - INFIFO_POP_CH - Set this bit to pop data from AXI_DMA FIFO. - 12 - 1 - write-only + 32 + read-write - 3 - 0x68 - IN_LINK1_CH%s - Link descriptor configure and control register of Rx channel 0 + CORE_0_AREA_PIF_0_MIN + core0 PIF region0 addr configuration register 0x20 0x20 - 0x00000011 + 0xFFFFFFFF - INLINK_AUTO_RET_CH - Set this bit to return to current inlink descriptor's address when there are some errors in current receiving data. + CORE_0_AREA_PIF_0_MIN + Core0 PIF region0 start addr 0 - 1 + 32 read-write - - INLINK_STOP_CH - Set this bit to stop dealing with the inlink descriptors. - 1 - 1 - write-only - - - INLINK_START_CH - Set this bit to start dealing with the inlink descriptors. - 2 - 1 - write-only - - - INLINK_RESTART_CH - Set this bit to mount a new inlink descriptor. - 3 - 1 - write-only - - - INLINK_PARK_CH - 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working. - 4 - 1 - read-only - - 3 - 0x68 - IN_LINK2_CH%s - Link descriptor configure and control register of Rx channel 0 + CORE_0_AREA_PIF_0_MAX + core0 PIF region0 addr configuration register 0x24 0x20 - INLINK_ADDR_CH - This register stores the 20 least significant bits of the first inlink descriptor's address. + CORE_0_AREA_PIF_0_MAX + Core0 PIF region0 end addr 0 32 read-write @@ -4244,64 +4128,45 @@ - 3 - 0x68 - IN_STATE_CH%s - Receive status of Rx channel 0 + CORE_0_AREA_PIF_1_MIN + core0 PIF region1 addr configuration register 0x28 0x20 + 0xFFFFFFFF - INLINK_DSCR_ADDR_CH - This register stores the current inlink descriptor's address. + CORE_0_AREA_PIF_1_MIN + Core0 PIF region1 start addr 0 - 18 - read-only - - - IN_DSCR_STATE_CH - reserved - 18 - 2 - read-only - - - IN_STATE_CH - reserved - 20 - 3 - read-only + 32 + read-write - 3 - 0x68 - IN_SUC_EOF_DES_ADDR_CH%s - Inlink descriptor address when EOF occurs of Rx channel 0 + CORE_0_AREA_PIF_1_MAX + core0 PIF region1 addr configuration register 0x2C 0x20 - IN_SUC_EOF_DES_ADDR_CH - This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. + CORE_0_AREA_PIF_1_MAX + Core0 PIF region1 end addr 0 32 - read-only + read-write - 3 - 0x68 - IN_ERR_EOF_DES_ADDR_CH%s - Inlink descriptor address when errors occur of Rx channel 0 + CORE_0_AREA_PC + core0 area pc status register 0x30 0x20 - IN_ERR_EOF_DES_ADDR_CH - This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0. + CORE_0_AREA_PC + the stackpointer when first touch region monitor interrupt 0 32 read-only @@ -4309,16 +4174,14 @@ - 3 - 0x68 - IN_DSCR_CH%s - Current inlink descriptor address of Rx channel 0 + CORE_0_AREA_SP + core0 area sp status register 0x34 0x20 - INLINK_DSCR_CH - The address of the current inlink descriptor x. + CORE_0_AREA_SP + the PC when first touch region monitor interrupt 0 32 read-only @@ -4326,989 +4189,1026 @@ - 3 - 0x68 - IN_DSCR_BF0_CH%s - The last inlink descriptor address of Rx channel 0 + CORE_0_SP_MIN + stack min value 0x38 0x20 - INLINK_DSCR_BF0_CH - The address of the last inlink descriptor x-1. + CORE_0_SP_MIN + core0 sp region configuration regsiter 0 32 - read-only + read-write - 3 - 0x68 - IN_DSCR_BF1_CH%s - The second-to-last inlink descriptor address of Rx channel 0 + CORE_0_SP_MAX + stack max value 0x3C 0x20 + 0xFFFFFFFF - INLINK_DSCR_BF1_CH - The address of the second-to-last inlink descriptor x-2. + CORE_0_SP_MAX + core0 sp pc status register 0 32 - read-only + read-write - 3 - 0x68 - IN_PRI_CH%s - Priority register of Rx channel 0 + CORE_0_SP_PC + stack monitor pc status register 0x40 0x20 - RX_PRI_CH - The priority of Rx channel 0. The larger of the value the higher of the priority. + CORE_0_SP_PC + This regsiter stores the PC when trigger stack monitor. 0 - 4 - read-write - - - RX_CH_ARB_WEIGH_CH - The weight of Rx channel 0 - 4 - 4 - read-write - - - RX_ARB_WEIGH_OPT_DIR_CH - 0: mean not optimazation weight function ,1: mean optimazation - 8 - 1 - read-write + 32 + read-only - 3 - 0x68 - IN_PERI_SEL_CH%s - Peripheral selection of Rx channel 0 + CORE_0_RCD_EN + record enable configuration register 0x44 0x20 - 0x0000003F - PERI_IN_SEL_CH - This register is used to select peripheral for Rx channel 0. 0:lcdcam. 1: gpspi_2. 2: gpspi_3. 3: parl_io. 4: aes. 5: sha. 6~15: Dummy + CORE_0_RCD_RECORDEN + Set 1 to enable record PC 0 - 6 + 1 + read-write + + + CORE_0_RCD_PDEBUGEN + Set 1 to enable cpu pdebug function, must set this bit can get cpu PC + 1 + 1 read-write - 3 - 0x68 - IN_CRC_INIT_DATA_CH%s - This register is used to config ch0 crc initial data(max 32 bit) + CORE_0_RCD_PDEBUGPC + record status regsiter 0x48 0x20 - 0xFFFFFFFF - IN_CRC_INIT_DATA_CH - This register is used to config ch0 of rx crc initial value + CORE_0_RCD_PDEBUGPC + recorded PC 0 32 - read-write + read-only - 3 - 0x68 - RX_CRC_WIDTH_CH%s - This register is used to confiig rx ch0 crc result width,2'b00 mean crc_width <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean 24<crc_width<=32 + CORE_0_RCD_PDEBUGSP + record status regsiter 0x4C 0x20 - RX_CRC_WIDTH_CH - reserved + CORE_0_RCD_PDEBUGSP + recorded sp 0 - 2 - read-write - - - RX_CRC_LAUTCH_FLGA_CH - reserved - 2 - 1 - read-write + 32 + read-only - 3 - 0x68 - IN_CRC_CLEAR_CH%s - This register is used to clear ch0 crc result + CORE_0_IRAM0_EXCEPTION_MONITOR_0 + exception monitor status register0 0x50 0x20 - IN_CRC_CLEAR_CH - This register is used to clear ch0 of rx crc result + CORE_0_IRAM0_RECORDING_ADDR_0 + reg_core_0_iram0_recording_addr_0 0 + 24 + read-only + + + CORE_0_IRAM0_RECORDING_WR_0 + reg_core_0_iram0_recording_wr_0 + 24 1 - read-write + read-only + + + CORE_0_IRAM0_RECORDING_LOADSTORE_0 + reg_core_0_iram0_recording_loadstore_0 + 25 + 1 + read-only - 3 - 0x68 - IN_CRC_FINAL_RESULT_CH%s - This register is used to store ch0 crc result + CORE_0_IRAM0_EXCEPTION_MONITOR_1 + exception monitor status register1 0x54 0x20 - IN_CRC_FINAL_RESULT_CH - This register is used to store result ch0 of rx + CORE_0_IRAM0_RECORDING_ADDR_1 + reg_core_0_iram0_recording_addr_1 0 - 32 + 24 + read-only + + + CORE_0_IRAM0_RECORDING_WR_1 + reg_core_0_iram0_recording_wr_1 + 24 + 1 + read-only + + + CORE_0_IRAM0_RECORDING_LOADSTORE_1 + reg_core_0_iram0_recording_loadstore_1 + 25 + 1 read-only - 3 - 0x68 - RX_CRC_EN_WR_DATA_CH%s - This resister is used to config ch0 crc en for every bit + CORE_0_DRAM0_EXCEPTION_MONITOR_0 + exception monitor status register2 0x58 0x20 - RX_CRC_EN_WR_DATA_CH - This register is used to enable rx ch0 crc 32bit on/off + CORE_0_DRAM0_RECORDING_WR_0 + reg_core_0_dram0_recording_wr_0 0 - 32 - read-write + 1 + read-only + + + CORE_0_DRAM0_RECORDING_BYTEEN_0 + reg_core_0_dram0_recording_byteen_0 + 1 + 16 + read-only - 3 - 0x68 - RX_CRC_EN_ADDR_CH%s - This register is used to config ch0 crc en addr + CORE_0_DRAM0_EXCEPTION_MONITOR_1 + exception monitor status register3 0x5C 0x20 - RX_CRC_EN_ADDR_CH - reserved + CORE_0_DRAM0_RECORDING_ADDR_0 + reg_core_0_dram0_recording_addr_0 0 - 32 - read-write + 24 + read-only - 3 - 0x68 - RX_CRC_DATA_EN_WR_DATA_CH%s - This register is used to config crc data_8bit en + CORE_0_DRAM0_EXCEPTION_MONITOR_2 + exception monitor status register4 0x60 0x20 - RX_CRC_DATA_EN_WR_DATA_CH - reserved + CORE_0_DRAM0_RECORDING_PC_0 + reg_core_0_dram0_recording_pc_0 0 - 16 - read-write + 32 + read-only - 3 - 0x68 - RX_CRC_DATA_EN_ADDR_CH%s - This register is used to config addr of crc data_8bit en + CORE_0_DRAM0_EXCEPTION_MONITOR_3 + exception monitor status register5 0x64 0x20 - RX_CRC_DATA_EN_ADDR_CH - reserved + CORE_0_DRAM0_RECORDING_WR_1 + reg_core_0_dram0_recording_wr_1 0 - 32 - read-write + 1 + read-only + + + CORE_0_DRAM0_RECORDING_BYTEEN_1 + reg_core_0_dram0_recording_byteen_1 + 1 + 16 + read-only - 3 - 0x68 - OUT_INT_RAW_CH%s - Raw status interrupt of channel0 - 0x138 + CORE_0_DRAM0_EXCEPTION_MONITOR_4 + exception monitor status register6 + 0x68 0x20 - OUT_DONE_CH_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel0. + CORE_0_DRAM0_RECORDING_ADDR_1 + reg_core_0_dram0_recording_addr_1 0 - 1 - read-write + 24 + read-only + + + + CORE_0_DRAM0_EXCEPTION_MONITOR_5 + exception monitor status register7 + 0x6C + 0x20 + - OUT_EOF_CH_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel0. + CORE_0_DRAM0_RECORDING_PC_1 + reg_core_0_dram0_recording_pc_1 + 0 + 32 + read-only + + + + + CORE_0_LASTPC_BEFORE_EXCEPTION + cpu status register + 0x70 + 0x20 + + + CORE_0_LASTPC_BEFORE_EXC + cpu's lastpc before exception + 0 + 32 + read-only + + + + + CORE_0_DEBUG_MODE + cpu status register + 0x74 + 0x20 + + + CORE_0_DEBUG_MODE + cpu debug mode status, 1 means cpu enter debug mode. + 0 + 1 + read-only + + + CORE_0_DEBUG_MODULE_ACTIVE + cpu debug_module active status + 1 + 1 + read-only + + + + + CORE_1_INTR_ENA + core1 monitor enable configuration register + 0x80 + 0x20 + + + CORE_1_AREA_DRAM0_0_RD_ENA + Core1 dram0 area0 read monitor enable + 0 + 1 + read-write + + + CORE_1_AREA_DRAM0_0_WR_ENA + Core1 dram0 area0 write monitor enable 1 1 read-write - OUT_DSCR_ERR_CH_INT_RAW - The raw interrupt bit turns to high level when detecting outlink descriptor error including owner error and the second and third word error of outlink descriptor for Tx channel0. + CORE_1_AREA_DRAM0_1_RD_ENA + Core1 dram0 area1 read monitor enable 2 1 read-write - OUT_TOTAL_EOF_CH_INT_RAW - The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel0. + CORE_1_AREA_DRAM0_1_WR_ENA + Core1 dram0 area1 write monitor enable 3 1 read-write - OUTFIFO_L1_OVF_CH_INT_RAW - This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is overflow. + CORE_1_AREA_PIF_0_RD_ENA + Core1 PIF area0 read monitor enable 4 1 read-write - OUTFIFO_L1_UDF_CH_INT_RAW - This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is underflow. + CORE_1_AREA_PIF_0_WR_ENA + Core1 PIF area0 write monitor enable 5 1 read-write - OUTFIFO_L2_OVF_CH_INT_RAW - This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is overflow. + CORE_1_AREA_PIF_1_RD_ENA + Core1 PIF area1 read monitor enable 6 1 read-write - OUTFIFO_L2_UDF_CH_INT_RAW - This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is underflow. + CORE_1_AREA_PIF_1_WR_ENA + Core1 PIF area1 write monitor enable 7 1 read-write - OUTFIFO_L3_OVF_CH_INT_RAW - This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is overflow. + CORE_1_SP_SPILL_MIN_ENA + Core1 stackpoint underflow monitor enable 8 1 read-write - OUTFIFO_L3_UDF_CH_INT_RAW - This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is underflow. + CORE_1_SP_SPILL_MAX_ENA + Core1 stackpoint overflow monitor enable 9 1 read-write + + CORE_1_IRAM0_EXCEPTION_MONITOR_ENA + IBUS busy monitor enable + 10 + 1 + read-write + + + CORE_1_DRAM0_EXCEPTION_MONITOR_ENA + DBUS busy monitor enbale + 11 + 1 + read-write + - 3 - 0x68 - OUT_INT_ST_CH%s - Masked interrupt of channel0 - 0x13C + CORE_1_INTR_RAW + core1 monitor interrupt status register + 0x84 0x20 - OUT_DONE_CH_INT_ST - The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + CORE_1_AREA_DRAM0_0_RD_RAW + Core1 dram0 area0 read monitor interrupt status 0 1 read-only - OUT_EOF_CH_INT_ST - The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + CORE_1_AREA_DRAM0_0_WR_RAW + Core1 dram0 area0 write monitor interrupt status 1 1 read-only - OUT_DSCR_ERR_CH_INT_ST - The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + CORE_1_AREA_DRAM0_1_RD_RAW + Core1 dram0 area1 read monitor interrupt status 2 1 read-only - OUT_TOTAL_EOF_CH_INT_ST - The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + CORE_1_AREA_DRAM0_1_WR_RAW + Core1 dram0 area1 write monitor interrupt status 3 1 read-only - OUTFIFO_OVF_CH_INT_ST - The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + CORE_1_AREA_PIF_0_RD_RAW + Core1 PIF area0 read monitor interrupt status 4 1 read-only - OUTFIFO_UDF_CH_INT_ST - The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + CORE_1_AREA_PIF_0_WR_RAW + Core1 PIF area0 write monitor interrupt status 5 1 read-only - OUTFIFO_L1_OVF_CH_INT_ST - The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. + CORE_1_AREA_PIF_1_RD_RAW + Core1 PIF area1 read monitor interrupt status 6 1 read-only - OUTFIFO_L1_UDF_CH_INT_ST - The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. + CORE_1_AREA_PIF_1_WR_RAW + Core1 PIF area1 write monitor interrupt status 7 1 read-only - OUTFIFO_L3_OVF_CH_INT_ST - The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt. + CORE_1_SP_SPILL_MIN_RAW + Core1 stackpoint underflow monitor interrupt status 8 1 read-only - OUTFIFO_L3_UDF_CH_INT_ST - The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt. + CORE_1_SP_SPILL_MAX_RAW + Core1 stackpoint overflow monitor interrupt status 9 1 read-only + + CORE_1_IRAM0_EXCEPTION_MONITOR_RAW + IBUS busy monitor interrupt status + 10 + 1 + read-only + + + CORE_1_DRAM0_EXCEPTION_MONITOR_RAW + DBUS busy monitor initerrupt status + 11 + 1 + read-only + - 3 - 0x68 - OUT_INT_ENA_CH%s - Interrupt enable bits of channel0 - 0x140 + CORE_1_INTR_RLS + core1 monitor interrupt enable register + 0x88 0x20 - OUT_DONE_CH_INT_ENA - The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + CORE_1_AREA_DRAM0_0_RD_RLS + Core1 dram0 area0 read monitor interrupt enable 0 1 read-write - OUT_EOF_CH_INT_ENA - The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + CORE_1_AREA_DRAM0_0_WR_RLS + Core1 dram0 area0 write monitor interrupt enable 1 1 read-write - OUT_DSCR_ERR_CH_INT_ENA - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + CORE_1_AREA_DRAM0_1_RD_RLS + Core1 dram0 area1 read monitor interrupt enable 2 1 read-write - OUT_TOTAL_EOF_CH_INT_ENA - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + CORE_1_AREA_DRAM0_1_WR_RLS + Core1 dram0 area1 write monitor interrupt enable 3 1 read-write - OUTFIFO_L1_OVF_CH_INT_ENA - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + CORE_1_AREA_PIF_0_RD_RLS + Core1 PIF area0 read monitor interrupt enable 4 1 read-write - OUTFIFO_L1_UDF_CH_INT_ENA - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + CORE_1_AREA_PIF_0_WR_RLS + Core1 PIF area0 write monitor interrupt enable 5 1 read-write - OUTFIFO_L2_OVF_CH_INT_ENA - The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. + CORE_1_AREA_PIF_1_RD_RLS + Core1 PIF area1 read monitor interrupt enable 6 1 read-write - OUTFIFO_L2_UDF_CH_INT_ENA - The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. + CORE_1_AREA_PIF_1_WR_RLS + Core1 PIF area1 write monitor interrupt enable 7 1 read-write - OUTFIFO_L3_OVF_CH_INT_ENA - The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt. + CORE_1_SP_SPILL_MIN_RLS + Core1 stackpoint underflow monitor interrupt enable 8 1 read-write - OUTFIFO_L3_UDF_CH_INT_ENA - The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt. + CORE_1_SP_SPILL_MAX_RLS + Core1 stackpoint overflow monitor interrupt enable 9 1 read-write + + CORE_1_IRAM0_EXCEPTION_MONITOR_RLS + IBUS busy monitor interrupt enable + 10 + 1 + read-write + + + CORE_1_DRAM0_EXCEPTION_MONITOR_RLS + DBUS busy monitor interrupt enbale + 11 + 1 + read-write + - 3 - 0x68 - OUT_INT_CLR_CH%s - Interrupt clear bits of channel0 - 0x144 + CORE_1_INTR_CLR + core1 monitor interrupt clr register + 0x8C 0x20 - OUT_DONE_CH_INT_CLR - Set this bit to clear the OUT_DONE_CH_INT interrupt. + CORE_1_AREA_DRAM0_0_RD_CLR + Core1 dram0 area0 read monitor interrupt clr 0 1 write-only - OUT_EOF_CH_INT_CLR - Set this bit to clear the OUT_EOF_CH_INT interrupt. + CORE_1_AREA_DRAM0_0_WR_CLR + Core1 dram0 area0 write monitor interrupt clr 1 1 write-only - OUT_DSCR_ERR_CH_INT_CLR - Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + CORE_1_AREA_DRAM0_1_RD_CLR + Core1 dram0 area1 read monitor interrupt clr 2 1 write-only - OUT_TOTAL_EOF_CH_INT_CLR - Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + CORE_1_AREA_DRAM0_1_WR_CLR + Core1 dram0 area1 write monitor interrupt clr 3 1 write-only - OUTFIFO_L1_OVF_CH_INT_CLR - Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + CORE_1_AREA_PIF_0_RD_CLR + Core1 PIF area0 read monitor interrupt clr 4 1 write-only - OUTFIFO_L1_UDF_CH_INT_CLR - Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + CORE_1_AREA_PIF_0_WR_CLR + Core1 PIF area0 write monitor interrupt clr 5 1 write-only - OUTFIFO_L2_OVF_CH_INT_CLR - Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. + CORE_1_AREA_PIF_1_RD_CLR + Core1 PIF area1 read monitor interrupt clr 6 1 write-only - OUTFIFO_L2_UDF_CH_INT_CLR - Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. + CORE_1_AREA_PIF_1_WR_CLR + Core1 PIF area1 write monitor interrupt clr 7 1 write-only - OUTFIFO_L3_OVF_CH_INT_CLR - Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt. + CORE_1_SP_SPILL_MIN_CLR + Core1 stackpoint underflow monitor interrupt clr 8 1 write-only - OUTFIFO_L3_UDF_CH_INT_CLR - Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt. + CORE_1_SP_SPILL_MAX_CLR + Core1 stackpoint overflow monitor interrupt clr 9 1 write-only - - - - OUT_CONF0_CH0 - Configure 0 register of Tx channel0 - 0x148 - 0x20 - 0x00000008 - - OUT_RST_CH0 - This bit is used to reset AXI_DMA channel0 Tx FSM and Tx FIFO pointer. - 0 + CORE_1_IRAM0_EXCEPTION_MONITOR_CLR + IBUS busy monitor interrupt clr + 10 1 - read-write + write-only - OUT_LOOP_TEST_CH0 - reserved - 1 + CORE_1_DRAM0_EXCEPTION_MONITOR_CLR + DBUS busy monitor interrupt clr + 11 1 - read-write + write-only + + + + CORE_1_AREA_DRAM0_0_MIN + core1 dram0 region0 addr configuration register + 0x90 + 0x20 + 0xFFFFFFFF + - OUT_AUTO_WRBACK_CH0 - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted. - 2 - 1 + CORE_1_AREA_DRAM0_0_MIN + Core1 dram0 region0 start addr + 0 + 32 read-write + + + + CORE_1_AREA_DRAM0_0_MAX + core1 dram0 region0 addr configuration register + 0x94 + 0x20 + - OUT_EOF_MODE_CH0 - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel0 is generated when data need to transmit has been popped from FIFO in AXI_DMA - 3 - 1 + CORE_1_AREA_DRAM0_0_MAX + Core1 dram0 region0 end addr + 0 + 32 read-write + + + + CORE_1_AREA_DRAM0_1_MIN + core1 dram0 region1 addr configuration register + 0x98 + 0x20 + 0xFFFFFFFF + - OUT_ETM_EN_CH0 - Set this bit to 1 to enable etm control mode, dma Tx channel0 is triggered by etm task. - 4 - 1 + CORE_1_AREA_DRAM0_1_MIN + Core1 dram0 region1 start addr + 0 + 32 read-write + + + + CORE_1_AREA_DRAM0_1_MAX + core1 dram0 region1 addr configuration register + 0x9C + 0x20 + - OUT_BURST_SIZE_SEL_CH0 - 3'b000-3'b100:burst length 8byte~128byte - 5 - 3 + CORE_1_AREA_DRAM0_1_MAX + Core1 dram0 region1 end addr + 0 + 32 read-write + + + + CORE_1_AREA_PIF_0_MIN + core1 PIF region0 addr configuration register + 0xA0 + 0x20 + 0xFFFFFFFF + - OUT_CMD_DISABLE_CH0 - 1:mean disable cmd of this ch0 - 8 - 1 + CORE_1_AREA_PIF_0_MIN + Core1 PIF region0 start addr + 0 + 32 read-write + + + + CORE_1_AREA_PIF_0_MAX + core1 PIF region0 addr configuration register + 0xA4 + 0x20 + - OUT_ECC_AEC_EN_CH0 - 1: mean access ecc or aes domain,0: mean not - 9 - 1 + CORE_1_AREA_PIF_0_MAX + Core1 PIF region0 end addr + 0 + 32 read-write + + + + CORE_1_AREA_PIF_1_MIN + core1 PIF region1 addr configuration register + 0xA8 + 0x20 + 0xFFFFFFFF + - OUTDSCR_BURST_EN_CH0 - Set this bit to 1 to enable INCR burst transfer for Tx channel0 reading link descriptor when accessing internal SRAM. - 10 - 1 + CORE_1_AREA_PIF_1_MIN + Core1 PIF region1 start addr + 0 + 32 read-write - 3 - 0x68 - OUT_CONF1_CH%s - Configure 1 register of Tx channel0 - 0x14C + CORE_1_AREA_PIF_1_MAX + core1 PIF region1 addr configuration register + 0xAC 0x20 - OUT_CHECK_OWNER_CH - Set this bit to enable checking the owner attribute of the link descriptor. - 12 - 1 + CORE_1_AREA_PIF_1_MAX + Core1 PIF region1 end addr + 0 + 32 read-write - 3 - 0x68 - OUTFIFO_STATUS_CH%s - Transmit FIFO status of Tx channel0 - 0x150 + CORE_1_AREA_PC + core1 area pc status register + 0xB0 0x20 - 0x7F808802 - OUTFIFO_L3_FULL_CH - L3 Tx FIFO full signal for Tx channel0. + CORE_1_AREA_PC + the stackpointer when first touch region monitor interrupt 0 - 1 - read-only - - - OUTFIFO_L3_EMPTY_CH - L3 Tx FIFO empty signal for Tx channel0. - 1 - 1 - read-only - - - OUTFIFO_L3_CNT_CH - The register stores the byte number of the data in L3 Tx FIFO for Tx channel0. - 2 - 6 - read-only - - - OUTFIFO_L3_UDF_CH - L3 Tx FIFO under flow signal for Tx channel0. - 8 - 1 - read-only - - - OUTFIFO_L3_OVF_CH - L3 Tx FIFO over flow signal for Tx channel0. - 9 - 1 - read-only - - - OUTFIFO_L1_FULL_CH - L1 Tx FIFO full signal for Tx channel0. - 10 - 1 - read-only - - - OUTFIFO_L1_EMPTY_CH - L1 Tx FIFO empty signal for Tx channel0. - 11 - 1 - read-only - - - OUTFIFO_L1_UDF_CH - L1 Tx FIFO under flow signal for Tx channel0. - 12 - 1 - read-only - - - OUTFIFO_L1_OVF_CH - L1 Tx FIFO over flow signal for Tx channel0. - 13 - 1 - read-only - - - OUTFIFO_L2_FULL_CH - L2 Tx RAM full signal for Tx channel0. - 14 - 1 - read-only - - - OUTFIFO_L2_EMPTY_CH - L2 Tx RAM empty signal for Tx channel0. - 15 - 1 - read-only - - - OUTFIFO_L2_UDF_CH - L2 Tx FIFO under flow signal for Tx channel0. - 16 - 1 - read-only - - - OUTFIFO_L2_OVF_CH - L2 Tx FIFO over flow signal for Tx channel0. - 17 - 1 - read-only - - - OUT_REMAIN_UNDER_1B_CH - reserved - 23 - 1 - read-only - - - OUT_REMAIN_UNDER_2B_CH - reserved - 24 - 1 - read-only - - - OUT_REMAIN_UNDER_3B_CH - reserved - 25 - 1 - read-only - - - OUT_REMAIN_UNDER_4B_CH - reserved - 26 - 1 - read-only - - - OUT_REMAIN_UNDER_5B_CH - reserved - 27 - 1 - read-only - - - OUT_REMAIN_UNDER_6B_CH - reserved - 28 - 1 + 32 read-only + + + + CORE_1_AREA_SP + core1 area sp status register + 0xB4 + 0x20 + - OUT_REMAIN_UNDER_7B_CH - reserved - 29 - 1 + CORE_1_AREA_SP + the PC when first touch region monitor interrupt + 0 + 32 read-only + + + + CORE_1_SP_MIN + stack min value + 0xB8 + 0x20 + - OUT_REMAIN_UNDER_8B_CH - reserved - 30 - 1 - read-only + CORE_1_SP_MIN + core1 sp region configuration regsiter + 0 + 32 + read-write - 3 - 0x68 - OUT_PUSH_CH%s - Push control register of Tx channel0 - 0x154 + CORE_1_SP_MAX + stack max value + 0xBC 0x20 + 0xFFFFFFFF - OUTFIFO_WDATA_CH - This register stores the data that need to be pushed into AXI_DMA FIFO. + CORE_1_SP_MAX + core1 sp pc status register 0 - 9 + 32 read-write + + + + CORE_1_SP_PC + stack monitor pc status register + 0xC0 + 0x20 + - OUTFIFO_PUSH_CH - Set this bit to push data into AXI_DMA FIFO. - 9 - 1 - write-only + CORE_1_SP_PC + This regsiter stores the PC when trigger stack monitor. + 0 + 32 + read-only - 3 - 0x68 - OUT_LINK1_CH%s - Link descriptor configure and control register of Tx channel0 - 0x158 + CORE_1_RCD_EN + record enable configuration register + 0xC4 0x20 - 0x00000008 - OUTLINK_STOP_CH - Set this bit to stop dealing with the outlink descriptors. + CORE_1_RCD_RECORDEN + Set 1 to enable record PC 0 1 - write-only + read-write - OUTLINK_START_CH - Set this bit to start dealing with the outlink descriptors. + CORE_1_RCD_PDEBUGEN + Set 1 to enable cpu pdebug function, must set this bit can get cpu PC 1 1 - write-only - - - OUTLINK_RESTART_CH - Set this bit to restart a new outlink from the last address. - 2 - 1 - write-only + read-write + + + + CORE_1_RCD_PDEBUGPC + record status regsiter + 0xC8 + 0x20 + - OUTLINK_PARK_CH - 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working. - 3 - 1 + CORE_1_RCD_PDEBUGPC + recorded PC + 0 + 32 read-only - 3 - 0x68 - OUT_LINK2_CH%s - Link descriptor configure and control register of Tx channel0 - 0x15C + CORE_1_RCD_PDEBUGSP + record status regsiter + 0xCC 0x20 - OUTLINK_ADDR_CH - This register stores the 32 least significant bits of the first outlink descriptor's address. + CORE_1_RCD_PDEBUGSP + recorded sp 0 32 - read-write + read-only - 3 - 0x68 - OUT_STATE_CH%s - Transmit status of Tx channel0 - 0x160 + CORE_1_IRAM0_EXCEPTION_MONITOR_0 + exception monitor status register0 + 0xD0 0x20 - OUTLINK_DSCR_ADDR_CH - This register stores the current outlink descriptor's address. + CORE_1_IRAM0_RECORDING_ADDR_0 + reg_core_1_iram0_recording_addr_0 0 - 18 + 24 read-only - OUT_DSCR_STATE_CH - reserved - 18 - 2 + CORE_1_IRAM0_RECORDING_WR_0 + reg_core_1_iram0_recording_wr_0 + 24 + 1 read-only - OUT_STATE_CH - reserved - 20 - 3 + CORE_1_IRAM0_RECORDING_LOADSTORE_0 + reg_core_1_iram0_recording_loadstore_0 + 25 + 1 read-only - 3 - 0x68 - OUT_EOF_DES_ADDR_CH%s - Outlink descriptor address when EOF occurs of Tx channel0 - 0x164 + CORE_1_IRAM0_EXCEPTION_MONITOR_1 + exception monitor status register1 + 0xD4 0x20 - OUT_EOF_DES_ADDR_CH - This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1. + CORE_1_IRAM0_RECORDING_ADDR_1 + reg_core_1_iram0_recording_addr_1 0 - 32 + 24 read-only - - - - 3 - 0x68 - OUT_EOF_BFR_DES_ADDR_CH%s - The last outlink descriptor address when EOF occurs of Tx channel0 - 0x168 - 0x20 - - OUT_EOF_BFR_DES_ADDR_CH - This register stores the address of the outlink descriptor before the last outlink descriptor. - 0 - 32 + CORE_1_IRAM0_RECORDING_WR_1 + reg_core_1_iram0_recording_wr_1 + 24 + 1 + read-only + + + CORE_1_IRAM0_RECORDING_LOADSTORE_1 + reg_core_1_iram0_recording_loadstore_1 + 25 + 1 read-only - 3 - 0x68 - OUT_DSCR_CH%s - Current outlink descriptor address of Tx channel0 - 0x16C + CORE_1_DRAM0_EXCEPTION_MONITOR_0 + exception monitor status register2 + 0xD8 0x20 - OUTLINK_DSCR_CH - The address of the current outlink descriptor y. + CORE_1_DRAM0_RECORDING_WR_0 + reg_core_1_dram0_recording_wr_0 0 - 32 + 1 + read-only + + + CORE_1_DRAM0_RECORDING_BYTEEN_0 + reg_core_1_dram0_recording_byteen_0 + 1 + 16 read-only - 3 - 0x68 - OUT_DSCR_BF0_CH%s - The last outlink descriptor address of Tx channel0 - 0x170 + CORE_1_DRAM0_EXCEPTION_MONITOR_1 + exception monitor status register3 + 0xDC 0x20 - OUTLINK_DSCR_BF0_CH - The address of the last outlink descriptor y-1. + CORE_1_DRAM0_RECORDING_ADDR_0 + reg_core_1_dram0_recording_addr_0 0 - 32 + 24 read-only - 3 - 0x68 - OUT_DSCR_BF1_CH%s - The second-to-last outlink descriptor address of Tx channel0 - 0x174 + CORE_1_DRAM0_EXCEPTION_MONITOR_2 + exception monitor status register4 + 0xE0 0x20 - OUTLINK_DSCR_BF1_CH - The address of the second-to-last outlink descriptor x-2. + CORE_1_DRAM0_RECORDING_PC_0 + reg_core_1_dram0_recording_pc_0 0 32 read-only @@ -5316,264 +5216,250 @@ - 3 - 0x68 - OUT_PRI_CH%s - Priority register of Tx channel0. - 0x178 + CORE_1_DRAM0_EXCEPTION_MONITOR_3 + exception monitor status register5 + 0xE4 0x20 - TX_PRI_CH - The priority of Tx channel0. The larger of the value the higher of the priority. + CORE_1_DRAM0_RECORDING_WR_1 + reg_core_1_dram0_recording_wr_1 0 - 4 - read-write - - - TX_CH_ARB_WEIGH_CH - The weight of Tx channel0 - 4 - 4 - read-write + 1 + read-only - TX_ARB_WEIGH_OPT_DIR_CH - 0: mean not optimazation weight function ,1: mean optimazation - 8 - 1 - read-write + CORE_1_DRAM0_RECORDING_BYTEEN_1 + reg_core_1_dram0_recording_byteen_1 + 1 + 16 + read-only - 3 - 0x68 - OUT_PERI_SEL_CH%s - Peripheral selection of Tx channel0 - 0x17C + CORE_1_DRAM0_EXCEPTION_MONITOR_4 + exception monitor status register6 + 0xE8 0x20 - 0x0000003F - PERI_OUT_SEL_CH - This register is used to select peripheral for Tx channel0. 0:lcdcam. 1: gpspi_2. 2: gpspi_3. 3: parl_io. 4: aes. 5: sha. 6~15: Dummy + CORE_1_DRAM0_RECORDING_ADDR_1 + reg_core_1_dram0_recording_addr_1 0 - 6 - read-write + 24 + read-only - 3 - 0x68 - OUT_CRC_INIT_DATA_CH%s - This register is used to config ch0 crc initial data(max 32 bit) - 0x180 + CORE_1_DRAM0_EXCEPTION_MONITOR_5 + exception monitor status register7 + 0xEC 0x20 - 0xFFFFFFFF - OUT_CRC_INIT_DATA_CH - This register is used to config ch0 of tx crc initial value + CORE_1_DRAM0_RECORDING_PC_1 + reg_core_1_dram0_recording_pc_1 0 32 - read-write + read-only - 3 - 0x68 - TX_CRC_WIDTH_CH%s - This register is used to confiig tx ch0 crc result width,2'b00 mean crc_width <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean 24<crc_width<=32 - 0x184 + CORE_1_LASTPC_BEFORE_EXCEPTION + cpu status register + 0xF0 0x20 - TX_CRC_WIDTH_CH - reserved + CORE_1_LASTPC_BEFORE_EXC + cpu's lastpc before exception 0 - 2 - read-write - - - TX_CRC_LAUTCH_FLGA_CH - reserved - 2 - 1 - read-write + 32 + read-only - 3 - 0x68 - OUT_CRC_CLEAR_CH%s - This register is used to clear ch0 crc result - 0x188 + CORE_1_DEBUG_MODE + cpu status register + 0xF4 0x20 - OUT_CRC_CLEAR_CH - This register is used to clear ch0 of tx crc result + CORE_1_DEBUG_MODE + cpu debug mode status, 1 means cpu enter debug mode. 0 1 - read-write + read-only + + + CORE_1_DEBUG_MODULE_ACTIVE + cpu debug_module active status + 1 + 1 + read-only - 3 - 0x68 - OUT_CRC_FINAL_RESULT_CH%s - This register is used to store ch0 crc result - 0x18C + CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0 + exception monitor status register6 + 0x100 0x20 - OUT_CRC_FINAL_RESULT_CH - This register is used to store result ch0 of tx + CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 + reg_core_x_iram0_dram0_limit_cycle_0 0 - 32 - read-only + 20 + read-write - 3 - 0x68 - TX_CRC_EN_WR_DATA_CH%s - This resister is used to config ch0 crc en for every bit - 0x190 + CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1 + exception monitor status register7 + 0x104 0x20 - TX_CRC_EN_WR_DATA_CH - This register is used to enable tx ch0 crc 32bit on/off + CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 + reg_core_x_iram0_dram0_limit_cycle_1 0 - 32 + 20 read-write - 3 - 0x68 - TX_CRC_EN_ADDR_CH%s - This register is used to config ch0 crc en addr - 0x194 + CLOCK_GATE + clock register + 0x108 0x20 + 0x00000001 - TX_CRC_EN_ADDR_CH - reserved + CLK_EN + Set 1 force on the clock gate 0 - 32 + 1 read-write - 3 - 0x68 - TX_CRC_DATA_EN_WR_DATA_CH%s - This register is used to config crc data_8bit en - 0x198 + DATE + version register + 0x3FC 0x20 + 0x02109130 - TX_CRC_DATA_EN_WR_DATA_CH - reserved + ASSIST_DEBUG_DATE + version register 0 - 16 + 28 read-write + + + + AXI_DMA + AXI_DMA Peripheral + AXI_DMA + 0x5008A000 + + 0x0 + 0x2D8 + registers + + 3 0x68 - TX_CRC_DATA_EN_ADDR_CH%s - This register is used to config addr of crc data_8bit en - 0x19C + IN_INT_RAW_CH%s + Raw status interrupt of channel 0 + 0x0 0x20 - TX_CRC_DATA_EN_ADDR_CH - reserved + IN_DONE_CH_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. 0 - 32 - read-write - - - - - OUT_CONF0_CH1 - Configure 0 register of Tx channel1 - 0x1B0 - 0x20 - 0x00000008 - - - OUT_RST_CH1 - This bit is used to reset AXI_DMA channel1 Tx FSM and Tx FIFO pointer. - 0 - 1 + 1 read-write - OUT_LOOP_TEST_CH1 - reserved + IN_SUC_EOF_CH_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0. 1 1 read-write - OUT_AUTO_WRBACK_CH1 - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted. + IN_ERR_EOF_CH_INT_RAW + The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw interrupt is reserved. 2 1 read-write - OUT_EOF_MODE_CH1 - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel1 is generated when data need to transmit has been popped from FIFO in AXI_DMA + IN_DSCR_ERR_CH_INT_RAW + The raw interrupt bit turns to high level when detecting inlink descriptor error including owner error and the second and third word error of inlink descriptor for Rx channel 0. 3 1 read-write - OUT_ETM_EN_CH1 - Set this bit to 1 to enable etm control mode, dma Tx channel1 is triggered by etm task. + IN_DSCR_EMPTY_CH_INT_RAW + The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed but there is no more inlink for Rx channel 0. 4 1 read-write - OUT_BURST_SIZE_SEL_CH1 - 3'b000-3'b100:burst length 8byte~128byte + INFIFO_L1_OVF_CH_INT_RAW + This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow. 5 - 3 + 1 read-write - OUT_CMD_DISABLE_CH1 - 1:mean disable cmd of this ch1 + INFIFO_L1_UDF_CH_INT_RAW + This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow. + 6 + 1 + read-write + + + INFIFO_L2_OVF_CH_INT_RAW + This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow. + 7 + 1 + read-write + + + INFIFO_L2_UDF_CH_INT_RAW + This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow. 8 1 read-write - OUT_ECC_AEC_EN_CH1 - 1: mean access ecc or aes domain,0: mean not + INFIFO_L3_OVF_CH_INT_RAW + This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow. 9 1 read-write - OUTDSCR_BURST_EN_CH1 - Set this bit to 1 to enable INCR burst transfer for Tx channel1 reading link descriptor when accessing internal SRAM. + INFIFO_L3_UDF_CH_INT_RAW + This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow. 10 1 read-write @@ -5581,248 +5467,509 @@ - OUT_CONF0_CH2 - Configure 0 register of Tx channel2 - 0x218 + 3 + 0x68 + IN_INT_ST_CH%s + Masked interrupt of channel 0 + 0x4 0x20 - 0x00000008 - OUT_RST_CH2 - This bit is used to reset AXI_DMA channel2 Tx FSM and Tx FIFO pointer. + IN_DONE_CH_INT_ST + The raw interrupt status bit for the IN_DONE_CH_INT interrupt. 0 1 - read-write + read-only - OUT_LOOP_TEST_CH2 - reserved + IN_SUC_EOF_CH_INT_ST + The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. 1 1 - read-write + read-only - OUT_AUTO_WRBACK_CH2 - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted. + IN_ERR_EOF_CH_INT_ST + The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. 2 1 - read-write + read-only - OUT_EOF_MODE_CH2 - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel2 is generated when data need to transmit has been popped from FIFO in AXI_DMA + IN_DSCR_ERR_CH_INT_ST + The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. 3 1 - read-write + read-only - OUT_ETM_EN_CH2 - Set this bit to 1 to enable etm control mode, dma Tx channel2 is triggered by etm task. + IN_DSCR_EMPTY_CH_INT_ST + The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. 4 1 - read-write + read-only - OUT_BURST_SIZE_SEL_CH2 - 3'b000-3'b100:burst length 8byte~128byte + INFIFO_OVF_CH_INT_ST + The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. 5 - 3 - read-write + 1 + read-only - OUT_CMD_DISABLE_CH2 - 1:mean disable cmd of this ch2 + INFIFO_UDF_CH_INT_ST + The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + 6 + 1 + read-only + + + INFIFO_L1_OVF_CH_INT_ST + The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. + 7 + 1 + read-only + + + INFIFO_L1_UDF_CH_INT_ST + The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. 8 1 - read-write + read-only - OUT_ECC_AEC_EN_CH2 - 1: mean access ecc or aes domain,0: mean not + INFIFO_L3_OVF_CH_INT_ST + The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt. 9 1 - read-write + read-only - OUTDSCR_BURST_EN_CH2 - Set this bit to 1 to enable INCR burst transfer for Tx channel2 reading link descriptor when accessing internal SRAM. + INFIFO_L3_UDF_CH_INT_ST + The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt. 10 1 - read-write + read-only - ARB_TIMEOUT - This retister is used to config arbiter time slice - 0x270 + 3 + 0x68 + IN_INT_ENA_CH%s + Interrupt enable bits of channel 0 + 0x8 0x20 - TX - This register is used to config tx arbiter time out value + IN_DONE_CH_INT_ENA + The interrupt enable bit for the IN_DONE_CH_INT interrupt. 0 - 16 + 1 read-write - RX - This register is used to config rx arbiter time out value - 16 - 16 + IN_SUC_EOF_CH_INT_ENA + The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + read-write + + + IN_ERR_EOF_CH_INT_ENA + The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + read-write + + + IN_DSCR_ERR_CH_INT_ENA + The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + 3 + 1 + read-write + + + IN_DSCR_EMPTY_CH_INT_ENA + The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + 4 + 1 + read-write + + + INFIFO_L1_OVF_CH_INT_ENA + The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + 5 + 1 + read-write + + + INFIFO_L1_UDF_CH_INT_ENA + The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + 6 + 1 + read-write + + + INFIFO_L2_OVF_CH_INT_ENA + The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. + 7 + 1 + read-write + + + INFIFO_L2_UDF_CH_INT_ENA + The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. + 8 + 1 + read-write + + + INFIFO_L3_OVF_CH_INT_ENA + The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt. + 9 + 1 + read-write + + + INFIFO_L3_UDF_CH_INT_ENA + The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt. + 10 + 1 read-write - WEIGHT_EN - This register is used to config arbiter weight function to on or off - 0x274 + 3 + 0x68 + IN_INT_CLR_CH%s + Interrupt clear bits of channel 0 + 0xC 0x20 - TX - This register is used to config tx arbiter weight function off/on + IN_DONE_CH_INT_CLR + Set this bit to clear the IN_DONE_CH_INT interrupt. 0 1 - read-write + write-only - RX - This register is used to config rx arbiter weight function off/on + IN_SUC_EOF_CH_INT_CLR + Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. 1 1 - read-write + write-only + + + IN_ERR_EOF_CH_INT_CLR + Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + write-only + + + IN_DSCR_ERR_CH_INT_CLR + Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. + 3 + 1 + write-only + + + IN_DSCR_EMPTY_CH_INT_CLR + Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + 4 + 1 + write-only + + + INFIFO_L1_OVF_CH_INT_CLR + Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + 5 + 1 + write-only + + + INFIFO_L1_UDF_CH_INT_CLR + Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + 6 + 1 + write-only + + + INFIFO_L2_OVF_CH_INT_CLR + Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. + 7 + 1 + write-only + + + INFIFO_L2_UDF_CH_INT_CLR + Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. + 8 + 1 + write-only + + + INFIFO_L3_OVF_CH_INT_CLR + Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt. + 9 + 1 + write-only + + + INFIFO_L3_UDF_CH_INT_CLR + Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt. + 10 + 1 + write-only - IN_MEM_CONF - Mem power configure register of Rx channel - 0x278 + 3 + 0x68 + IN_CONF0_CH%s + Configure 0 register of Rx channel 0 + 0x10 0x20 - IN_MEM_CLK_FORCE_EN - 1: Force to open the clock and bypass the gate-clock when accessing the RAM in AXI_DMA. 0: A gate-clock will be used when accessing the RAM in AXI_DMA. + IN_RST_CH + This bit is used to reset AXI_DMA channel 0 Rx FSM and Rx FIFO pointer. 0 1 read-write - IN_MEM_FORCE_PU - Force power up ram + IN_LOOP_TEST_CH + reserved 1 1 read-write - IN_MEM_FORCE_PD - Force power down ram + MEM_TRANS_EN_CH + Set this bit 1 to enable automatic transmitting data from memory to memory via AXI_DMA. 2 1 read-write - OUT_MEM_CLK_FORCE_EN - 1: Force to open the clock and bypass the gate-clock when accessing the RAM in AXI_DMA. 0: A gate-clock will be used when accessing the RAM in AXI_DMA. + IN_ETM_EN_CH + Set this bit to 1 to enable etm control mode, dma Rx channel 0 is triggered by etm task. 3 1 read-write - OUT_MEM_FORCE_PU - Force power up ram + IN_BURST_SIZE_SEL_CH + 3'b000-3'b100:burst length 8byte~128byte 4 - 1 + 3 read-write - OUT_MEM_FORCE_PD - Force power down ram - 5 + IN_CMD_DISABLE_CH + 1:mean disable cmd of this ch0 + 7 1 read-write - - - - INTR_MEM_START_ADDR - The start address of accessible address space. - 0x27C - 0x20 - 0x30100000 - - ACCESS_INTR_MEM_START_ADDR - The start address of accessible address space. - 0 - 32 + IN_ECC_AEC_EN_CH + 1: mean access ecc or aes domain,0: mean not + 8 + 1 read-write - - - - INTR_MEM_END_ADDR - The end address of accessible address space. The access address beyond this range would lead to descriptor error. - 0x280 - 0x20 - 0x8FFFFFFF - - ACCESS_INTR_MEM_END_ADDR - The end address of accessible address space. The access address beyond this range would lead to descriptor error. - 0 - 32 + INDSCR_BURST_EN_CH + Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM. + 9 + 1 read-write - EXTR_MEM_START_ADDR - The start address of accessible address space. - 0x284 + 3 + 0x68 + IN_CONF1_CH%s + Configure 1 register of Rx channel 0 + 0x14 0x20 - 0x30100000 - ACCESS_EXTR_MEM_START_ADDR - The start address of accessible address space. - 0 - 32 + IN_CHECK_OWNER_CH + Set this bit to enable checking the owner attribute of the link descriptor. + 12 + 1 read-write - EXTR_MEM_END_ADDR - The end address of accessible address space. The access address beyond this range would lead to descriptor error. - 0x288 + 3 + 0x68 + INFIFO_STATUS_CH%s + Receive FIFO status of Rx channel 0 + 0x18 0x20 - 0x8FFFFFFF + 0x00008803 - ACCESS_EXTR_MEM_END_ADDR - The end address of accessible address space. The access address beyond this range would lead to descriptor error. + INFIFO_L3_FULL_CH + L3 Rx FIFO full signal for Rx channel 0. 0 - 32 - read-write + 1 + read-only - - - - 3 - 0x4 - IN_RESET_AVAIL_CH%s - The rx channel 0 reset valid_flag register. - 0x28C - 0x20 - 0x00000001 - - IN_RESET_AVAIL_CH - rx chan0 reset valid reg. - 0 + INFIFO_L3_EMPTY_CH + L3 Rx FIFO empty signal for Rx channel 0. + 1 + 1 + read-only + + + INFIFO_L3_CNT_CH + The register stores the byte number of the data in L3 Rx FIFO for Rx channel 0. + 2 + 6 + read-only + + + INFIFO_L3_UDF_CH + L3 Rx FIFO under flow signal for Rx channel 0. + 8 + 1 + read-only + + + INFIFO_L3_OVF_CH + L3 Rx FIFO over flow signal for Rx channel 0. + 9 + 1 + read-only + + + INFIFO_L1_FULL_CH + L1 Rx FIFO full signal for Rx channel 0. + 10 + 1 + read-only + + + INFIFO_L1_EMPTY_CH + L1 Rx FIFO empty signal for Rx channel 0. + 11 + 1 + read-only + + + INFIFO_L1_UDF_CH + L1 Rx FIFO under flow signal for Rx channel 0. + 12 + 1 + read-only + + + INFIFO_L1_OVF_CH + L1 Rx FIFO over flow signal for Rx channel 0. + 13 + 1 + read-only + + + INFIFO_L2_FULL_CH + L2 Rx RAM full signal for Rx channel 0. + 14 + 1 + read-only + + + INFIFO_L2_EMPTY_CH + L2 Rx RAM empty signal for Rx channel 0. + 15 + 1 + read-only + + + INFIFO_L2_UDF_CH + L2 Rx FIFO under flow signal for Rx channel 0. + 16 + 1 + read-only + + + INFIFO_L2_OVF_CH + L2 Rx FIFO over flow signal for Rx channel 0. + 17 + 1 + read-only + + + IN_REMAIN_UNDER_1B_CH + reserved + 23 + 1 + read-only + + + IN_REMAIN_UNDER_2B_CH + reserved + 24 + 1 + read-only + + + IN_REMAIN_UNDER_3B_CH + reserved + 25 + 1 + read-only + + + IN_REMAIN_UNDER_4B_CH + reserved + 26 + 1 + read-only + + + IN_REMAIN_UNDER_5B_CH + reserved + 27 + 1 + read-only + + + IN_REMAIN_UNDER_6B_CH + reserved + 28 + 1 + read-only + + + IN_REMAIN_UNDER_7B_CH + reserved + 29 + 1 + read-only + + + IN_REMAIN_UNDER_8B_CH + reserved + 30 + 1 + read-only + + + IN_BUF_HUNGRY_CH + reserved + 31 1 read-only @@ -5830,90 +5977,86 @@ 3 - 0x4 - OUT_RESET_AVAIL_CH%s - The tx channel 0 reset valid_flag register. - 0x298 + 0x68 + IN_POP_CH%s + Pop control register of Rx channel 0 + 0x1C 0x20 - 0x00000001 + 0x00000800 - OUT_RESET_AVAIL_CH - tx chan0 reset valid reg. + INFIFO_RDATA_CH + This register stores the data popping from AXI_DMA FIFO. 0 - 1 + 12 read-only + + INFIFO_POP_CH + Set this bit to pop data from AXI_DMA FIFO. + 12 + 1 + write-only + - MISC_CONF - MISC register - 0x2A8 + 3 + 0x68 + IN_LINK1_CH%s + Link descriptor configure and control register of Rx channel 0 + 0x20 0x20 + 0x00000011 - AXIM_RST_WR_INTER - Set this bit then clear this bit to reset the internal axi_wr FSM. + INLINK_AUTO_RET_CH + Set this bit to return to current inlink descriptor's address when there are some errors in current receiving data. 0 1 read-write - AXIM_RST_RD_INTER - Set this bit then clear this bit to reset the internal axi_rd FSM. + INLINK_STOP_CH + Set this bit to stop dealing with the inlink descriptors. 1 1 - read-write - - - ARB_PRI_DIS - Set this bit to disable priority arbitration function. - 3 - 1 - read-write + write-only - CLK_EN - 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers. - 4 + INLINK_START_CH + Set this bit to start dealing with the inlink descriptors. + 2 1 - read-write + write-only - - - - RDN_RESULT - reserved - 0x2AC - 0x20 - - RDN_ENA - reserved - 0 + INLINK_RESTART_CH + Set this bit to mount a new inlink descriptor. + 3 1 - read-write + write-only - RDN_RESULT - reserved - 1 + INLINK_PARK_CH + 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working. + 4 1 read-only - RDN_ECO_HIGH - reserved - 0x2B0 + 3 + 0x68 + IN_LINK2_CH%s + Link descriptor configure and control register of Rx channel 0 + 0x24 0x20 - 0xFFFFFFFF - RDN_ECO_HIGH - The start address of accessible address space. + INLINK_ADDR_CH + This register stores the 20 least significant bits of the first inlink descriptor's address. 0 32 read-write @@ -5921,197 +6064,182 @@ - RDN_ECO_LOW - reserved - 0x2B4 + 3 + 0x68 + IN_STATE_CH%s + Receive status of Rx channel 0 + 0x28 0x20 - RDN_ECO_LOW - The start address of accessible address space. + INLINK_DSCR_ADDR_CH + This register stores the current inlink descriptor's address. 0 - 32 - read-write + 18 + read-only + + + IN_DSCR_STATE_CH + reserved + 18 + 2 + read-only + + + IN_STATE_CH + reserved + 20 + 3 + read-only - WRESP_CNT - AXI wr responce cnt register. - 0x2B8 + 3 + 0x68 + IN_SUC_EOF_DES_ADDR_CH%s + Inlink descriptor address when EOF occurs of Rx channel 0 + 0x2C 0x20 - WRESP_CNT - axi wr responce cnt reg. + IN_SUC_EOF_DES_ADDR_CH + This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. 0 - 4 + 32 read-only - RRESP_CNT - AXI wr responce cnt register. - 0x2BC + 3 + 0x68 + IN_ERR_EOF_DES_ADDR_CH%s + Inlink descriptor address when errors occur of Rx channel 0 + 0x30 0x20 - RRESP_CNT - axi rd responce cnt reg. + IN_ERR_EOF_DES_ADDR_CH + This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0. 0 - 4 + 32 read-only 3 - 0x4 - INFIFO_STATUS1_CH%s - Receive FIFO status of Rx channel 0 - 0x2C0 + 0x68 + IN_DSCR_CH%s + Current inlink descriptor address of Rx channel 0 + 0x34 0x20 - L1INFIFO_CNT_CH - The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0. + INLINK_DSCR_CH + The address of the current inlink descriptor x. 0 - 6 - read-only - - - L2INFIFO_CNT_CH - The register stores the byte number of the data in L2 Rx FIFO for Rx channel 0. - 6 - 4 + 32 read-only 3 - 0x4 - OUTFIFO_STATUS1_CH%s - Receive FIFO status of Tx channel 0 - 0x2CC + 0x68 + IN_DSCR_BF0_CH%s + The last inlink descriptor address of Rx channel 0 + 0x38 0x20 - L1OUTFIFO_CNT_CH - The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0. + INLINK_DSCR_BF0_CH + The address of the last inlink descriptor x-1. 0 - 6 - read-only - - - L2OUTFIFO_CNT_CH - The register stores the byte number of the data in L2 Tx FIFO for Tx channel 0. - 6 - 4 + 32 read-only - DATE - Version control register - 0x2D8 + 3 + 0x68 + IN_DSCR_BF1_CH%s + The second-to-last inlink descriptor address of Rx channel 0 + 0x3C 0x20 - 0x02303140 - DATE - register version. + INLINK_DSCR_BF1_CH + The address of the second-to-last inlink descriptor x-2. 0 32 - read-write + read-only - - - - BITSCRAMBLER - BITSCRAMBLER Peripheral - BITSCRAMBLER - 0x500A3000 - - 0x0 - 0x40 - registers - - - TX_INST_CFG0 - Control and configuration registers - 0x0 + 3 + 0x68 + IN_PRI_CH%s + Priority register of Rx channel 0 + 0x40 0x20 - TX_INST_IDX - write this bits to specify the one of 8 instruction + RX_PRI_CH + The priority of Rx channel 0. The larger of the value the higher of the priority. 0 - 3 + 4 read-write - TX_INST_POS - write this bits to specify the bit position of 257 bit instruction which in units of 32 bits - 3 + RX_CH_ARB_WEIGH_CH + The weight of Rx channel 0 + 4 4 read-write - - - - TX_INST_CFG1 - Control and configuration registers - 0x4 - 0x20 - 0x00000004 - - TX_INST - write this bits to update instruction which specified by BITSCRAMBLER_TX_INST_CFG0_REG, Read this bits to get instruction which specified by BITSCRAMBLER_TX_INST_CFG0_REG - 0 - 32 + RX_ARB_WEIGH_OPT_DIR_CH + 0: mean not optimazation weight function ,1: mean optimazation + 8 + 1 read-write - RX_INST_CFG0 - Control and configuration registers - 0x8 + 3 + 0x68 + IN_PERI_SEL_CH%s + Peripheral selection of Rx channel 0 + 0x44 0x20 + 0x0000003F - RX_INST_IDX - write this bits to specify the one of 8 instruction + PERI_IN_SEL_CH + This register is used to select peripheral for Rx channel 0. 0:lcdcam. 1: gpspi_2. 2: gpspi_3. 3: parl_io. 4: aes. 5: sha. 6~15: Dummy 0 - 3 - read-write - - - RX_INST_POS - write this bits to specify the bit position of 257 bit instruction which in units of 32 bits - 3 - 4 + 6 read-write - RX_INST_CFG1 - Control and configuration registers - 0xC + 3 + 0x68 + IN_CRC_INIT_DATA_CH%s + This register is used to config ch0 crc initial data(max 32 bit) + 0x48 0x20 - 0x0000000C + 0xFFFFFFFF - RX_INST - write this bits to update instruction which specified by BITSCRAMBLER_RX_INST_CFG0_REG, Read this bits to get instruction which specified by BITSCRAMBLER_RX_INST_CFG0_REG + IN_CRC_INIT_DATA_CH + This register is used to config ch0 of rx crc initial value 0 32 read-write @@ -6119,75 +6247,91 @@ - TX_LUT_CFG0 - Control and configuration registers - 0x10 + 3 + 0x68 + RX_CRC_WIDTH_CH%s + This register is used to confiig rx ch0 crc result width,2'b00 mean crc_width <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean 24<crc_width<=32 + 0x4C 0x20 - TX_LUT_IDX - write this bits to specify the bytes position of LUT RAM based on reg_bitscrambler_tx_lut_mode + RX_CRC_WIDTH_CH + reserved 0 - 11 + 2 read-write - TX_LUT_MODE - write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4 bytes - 11 - 2 + RX_CRC_LAUTCH_FLGA_CH + reserved + 2 + 1 read-write - TX_LUT_CFG1 - Control and configuration registers - 0x14 + 3 + 0x68 + IN_CRC_CLEAR_CH%s + This register is used to clear ch0 crc result + 0x50 0x20 - 0x00000014 - TX_LUT - write this bits to update LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG, Read this bits to get LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG + IN_CRC_CLEAR_CH + This register is used to clear ch0 of rx crc result 0 - 32 + 1 read-write - RX_LUT_CFG0 - Control and configuration registers - 0x18 + 3 + 0x68 + IN_CRC_FINAL_RESULT_CH%s + This register is used to store ch0 crc result + 0x54 0x20 - RX_LUT_IDX - write this bits to specify the bytes position of LUT RAM based on reg_bitscrambler_rx_lut_mode + IN_CRC_FINAL_RESULT_CH + This register is used to store result ch0 of rx 0 - 11 - read-write + 32 + read-only + + + + 3 + 0x68 + RX_CRC_EN_WR_DATA_CH%s + This resister is used to config ch0 crc en for every bit + 0x58 + 0x20 + - RX_LUT_MODE - write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4 bytes - 11 - 2 + RX_CRC_EN_WR_DATA_CH + This register is used to enable rx ch0 crc 32bit on/off + 0 + 32 read-write - RX_LUT_CFG1 - Control and configuration registers - 0x1C + 3 + 0x68 + RX_CRC_EN_ADDR_CH%s + This register is used to config ch0 crc en addr + 0x5C 0x20 - 0x0000001C - RX_LUT - write this bits to update LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG, Read this bits to get LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG + RX_CRC_EN_ADDR_CH + reserved 0 32 read-write @@ -6195,14 +6339,16 @@ - TX_TAILING_BITS - Control and configuration registers - 0x20 + 3 + 0x68 + RX_CRC_DATA_EN_WR_DATA_CH%s + This register is used to config crc data_8bit en + 0x60 0x20 - TX_TAILING_BITS - write this bits to specify the extra data bit length after getting EOF + RX_CRC_DATA_EN_WR_DATA_CH + reserved 0 16 read-write @@ -6210,1383 +6356,1242 @@ - RX_TAILING_BITS - Control and configuration registers - 0x24 + 3 + 0x68 + RX_CRC_DATA_EN_ADDR_CH%s + This register is used to config addr of crc data_8bit en + 0x64 0x20 - RX_TAILING_BITS - write this bits to specify the extra data bit length after getting EOF + RX_CRC_DATA_EN_ADDR_CH + reserved 0 - 16 + 32 read-write - TX_CTRL - Control and configuration registers - 0x28 + 3 + 0x68 + OUT_INT_RAW_CH%s + Raw status interrupt of channel0 + 0x138 0x20 - 0x00000004 - TX_ENA - write this bit to enable the bitscrambler tx + OUT_DONE_CH_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel0. 0 1 read-write - TX_PAUSE - write this bit to pause the bitscrambler tx core + OUT_EOF_CH_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel0. 1 1 read-write - TX_HALT - write this bit to halt the bitscrambler tx core + OUT_DSCR_ERR_CH_INT_RAW + The raw interrupt bit turns to high level when detecting outlink descriptor error including owner error and the second and third word error of outlink descriptor for Tx channel0. 2 1 read-write - TX_EOF_MODE - write this bit to ser the bitscrambler tx core EOF signal generating mode which is combined with reg_bitscrambler_tx_tailing_bits, 0: counter by read dma fifo, 0 counter by write peripheral buffer + OUT_TOTAL_EOF_CH_INT_RAW + The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel0. 3 1 read-write - TX_COND_MODE - write this bit to specify the LOOP instruction condition mode of bitscrambler tx core, 0: use the little than operator to get the condition, 1: use not equal operator to get the condition + OUTFIFO_L1_OVF_CH_INT_RAW + This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is overflow. 4 1 read-write - TX_FETCH_MODE - write this bit to set the bitscrambler tx core fetch instruction mode, 0: prefetch by reset, 1: fetch by instrutions + OUTFIFO_L1_UDF_CH_INT_RAW + This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is underflow. 5 1 read-write - TX_HALT_MODE - write this bit to set the bitscrambler tx core halt mode when tx_halt is set, 0: wait write data back done, , 1: ignore write data back + OUTFIFO_L2_OVF_CH_INT_RAW + This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is overflow. 6 1 read-write - TX_RD_DUMMY - write this bit to set the bitscrambler tx core read data mode when EOF received.0: wait read data, 1: ignore read data + OUTFIFO_L2_UDF_CH_INT_RAW + This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is underflow. 7 1 read-write - TX_FIFO_RST - write this bit to reset the bitscrambler tx fifo + OUTFIFO_L3_OVF_CH_INT_RAW + This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is overflow. 8 1 - write-only + read-write - - - - RX_CTRL - Control and configuration registers - 0x2C + + OUTFIFO_L3_UDF_CH_INT_RAW + This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is underflow. + 9 + 1 + read-write + + + + + 3 + 0x68 + OUT_INT_ST_CH%s + Masked interrupt of channel0 + 0x13C 0x20 - 0x00000004 - RX_ENA - write this bit to enable the bitscrambler rx + OUT_DONE_CH_INT_ST + The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. 0 1 - read-write + read-only - RX_PAUSE - write this bit to pause the bitscrambler rx core + OUT_EOF_CH_INT_ST + The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. 1 1 - read-write + read-only - RX_HALT - write this bit to halt the bitscrambler rx core + OUT_DSCR_ERR_CH_INT_ST + The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. 2 1 - read-write + read-only - RX_EOF_MODE - write this bit to ser the bitscrambler rx core EOF signal generating mode which is combined with reg_bitscrambler_rx_tailing_bits, 0: counter by read peripheral buffer, 0 counter by write dma fifo + OUT_TOTAL_EOF_CH_INT_ST + The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. 3 1 - read-write + read-only - RX_COND_MODE - write this bit to specify the LOOP instruction condition mode of bitscrambler rx core, 0: use the little than operator to get the condition, 1: use not equal operator to get the condition + OUTFIFO_OVF_CH_INT_ST + The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. 4 1 - read-write + read-only - RX_FETCH_MODE - write this bit to set the bitscrambler rx core fetch instruction mode, 0: prefetch by reset, 1: fetch by instrutions + OUTFIFO_UDF_CH_INT_ST + The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. 5 1 - read-write + read-only - RX_HALT_MODE - write this bit to set the bitscrambler rx core halt mode when rx_halt is set, 0: wait write data back done, , 1: ignore write data back + OUTFIFO_L1_OVF_CH_INT_ST + The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. 6 1 - read-write + read-only - RX_RD_DUMMY - write this bit to set the bitscrambler rx core read data mode when EOF received.0: wait read data, 1: ignore read data + OUTFIFO_L1_UDF_CH_INT_ST + The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. 7 1 - read-write + read-only - RX_FIFO_RST - write this bit to reset the bitscrambler rx fifo + OUTFIFO_L3_OVF_CH_INT_ST + The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt. 8 1 - write-only + read-only + + + OUTFIFO_L3_UDF_CH_INT_ST + The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt. + 9 + 1 + read-only - TX_STATE - Status registers - 0x30 + 3 + 0x68 + OUT_INT_ENA_CH%s + Interrupt enable bits of channel0 + 0x140 0x20 - 0x00000001 - TX_IN_IDLE - represents the bitscrambler tx core in halt mode + OUT_DONE_CH_INT_ENA + The interrupt enable bit for the OUT_DONE_CH_INT interrupt. 0 1 - read-only + read-write - TX_IN_RUN - represents the bitscrambler tx core in run mode + OUT_EOF_CH_INT_ENA + The interrupt enable bit for the OUT_EOF_CH_INT interrupt. 1 1 - read-only + read-write - TX_IN_WAIT - represents the bitscrambler tx core in wait mode to wait write back done + OUT_DSCR_ERR_CH_INT_ENA + The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. 2 1 - read-only + read-write - TX_IN_PAUSE - represents the bitscrambler tx core in pause mode + OUT_TOTAL_EOF_CH_INT_ENA + The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. 3 1 - read-only + read-write - TX_FIFO_EMPTY - represents the bitscrambler tx fifo in empty state + OUTFIFO_L1_OVF_CH_INT_ENA + The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. 4 1 - read-only + read-write - TX_EOF_GET_CNT - represents the bytes numbers of bitscrambler tx core when get EOF - 16 - 14 - read-only + OUTFIFO_L1_UDF_CH_INT_ENA + The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-write - TX_EOF_OVERLOAD - represents the some EOFs will be lost for bitscrambler tx core - 30 + OUTFIFO_L2_OVF_CH_INT_ENA + The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. + 6 1 - read-only + read-write - TX_EOF_TRACE_CLR - write this bit to clear reg_bitscrambler_tx_eof_overload and reg_bitscrambler_tx_eof_get_cnt registers - 31 + OUTFIFO_L2_UDF_CH_INT_ENA + The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. + 7 1 - write-only + read-write + + + OUTFIFO_L3_OVF_CH_INT_ENA + The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt. + 8 + 1 + read-write + + + OUTFIFO_L3_UDF_CH_INT_ENA + The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt. + 9 + 1 + read-write - RX_STATE - Status registers - 0x34 + 3 + 0x68 + OUT_INT_CLR_CH%s + Interrupt clear bits of channel0 + 0x144 0x20 - 0x00000001 - RX_IN_IDLE - represents the bitscrambler rx core in halt mode + OUT_DONE_CH_INT_CLR + Set this bit to clear the OUT_DONE_CH_INT interrupt. 0 1 - read-only + write-only - RX_IN_RUN - represents the bitscrambler rx core in run mode + OUT_EOF_CH_INT_CLR + Set this bit to clear the OUT_EOF_CH_INT interrupt. 1 1 - read-only + write-only - RX_IN_WAIT - represents the bitscrambler rx core in wait mode to wait write back done + OUT_DSCR_ERR_CH_INT_CLR + Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. 2 1 - read-only + write-only - RX_IN_PAUSE - represents the bitscrambler rx core in pause mode + OUT_TOTAL_EOF_CH_INT_CLR + Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. 3 1 - read-only + write-only - RX_FIFO_FULL - represents the bitscrambler rx fifo in full state + OUTFIFO_L1_OVF_CH_INT_CLR + Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. 4 1 - read-only - - - RX_EOF_GET_CNT - represents the bytes numbers of bitscrambler rx core when get EOF - 16 - 14 - read-only + write-only - RX_EOF_OVERLOAD - represents the some EOFs will be lost for bitscrambler rx core - 30 + OUTFIFO_L1_UDF_CH_INT_CLR + Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 1 - read-only + write-only - RX_EOF_TRACE_CLR - write this bit to clear reg_bitscrambler_rx_eof_overload and reg_bitscrambler_rx_eof_get_cnt registers - 31 + OUTFIFO_L2_OVF_CH_INT_CLR + Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. + 6 1 write-only - - - - SYS - Control and configuration registers - 0xF8 - 0x20 - - LOOP_MODE - write this bit to set the bitscrambler tx loop back to DMA rx - 0 + OUTFIFO_L2_UDF_CH_INT_CLR + Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. + 7 1 - read-write + write-only - CLK_EN - Reserved - 31 + OUTFIFO_L3_OVF_CH_INT_CLR + Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt. + 8 1 - read-write + write-only - - - - VERSION - Control and configuration registers - 0xFC - 0x20 - 0x02303240 - - BITSCRAMBLER_VER - Reserved - 0 - 28 - read-write + OUTFIFO_L3_UDF_CH_INT_CLR + Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt. + 9 + 1 + write-only - - - - CACHE - CACHE Peripheral - CACHE - 0x3FF10000 - - 0x0 - 0x3F0 - registers - - - CACHE - 83 - - - L1_ICACHE_CTRL - L1 instruction Cache(L1-ICache) control register - 0x0 + OUT_CONF0_CH0 + Configure 0 register of Tx channel0 + 0x148 0x20 + 0x00000008 - L1_ICACHE_SHUT_IBUS0 - The bit is used to disable core0 ibus access L1-ICache, 0: enable, 1: disable + OUT_RST_CH0 + This bit is used to reset AXI_DMA channel0 Tx FSM and Tx FIFO pointer. 0 1 read-write - L1_ICACHE_SHUT_IBUS1 - The bit is used to disable core1 ibus access L1-ICache, 0: enable, 1: disable + OUT_LOOP_TEST_CH0 + reserved 1 1 read-write - L1_ICACHE_SHUT_IBUS2 - Reserved + OUT_AUTO_WRBACK_CH0 + Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted. 2 1 - read-only + read-write - L1_ICACHE_SHUT_IBUS3 - Reserved + OUT_EOF_MODE_CH0 + EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel0 is generated when data need to transmit has been popped from FIFO in AXI_DMA 3 1 - read-only - - - L1_ICACHE_UNDEF_OP - Reserved - 8 - 8 read-write - - - - L1_DCACHE_CTRL - L1 data Cache(L1-DCache) control register - 0x4 - 0x20 - - L1_DCACHE_SHUT_DBUS0 - The bit is used to disable core0 dbus access L1-DCache, 0: enable, 1: disable - 0 + OUT_ETM_EN_CH0 + Set this bit to 1 to enable etm control mode, dma Tx channel0 is triggered by etm task. + 4 1 read-write - L1_DCACHE_SHUT_DBUS1 - The bit is used to disable core1 dbus access L1-DCache, 0: enable, 1: disable - 1 - 1 + OUT_BURST_SIZE_SEL_CH0 + 3'b000-3'b100:burst length 8byte~128byte + 5 + 3 read-write - L1_DCACHE_SHUT_DBUS2 - Reserved - 2 + OUT_CMD_DISABLE_CH0 + 1:mean disable cmd of this ch0 + 8 1 - read-only + read-write - L1_DCACHE_SHUT_DBUS3 - Reserved - 3 + OUT_ECC_AEC_EN_CH0 + 1: mean access ecc or aes domain,0: mean not + 9 1 - read-only + read-write - L1_DCACHE_SHUT_DMA - The bit is used to disable DMA access L1-DCache, 0: enable, 1: disable - 4 + OUTDSCR_BURST_EN_CH0 + Set this bit to 1 to enable INCR burst transfer for Tx channel0 reading link descriptor when accessing internal SRAM. + 10 1 read-write + + + + 3 + 0x68 + OUT_CONF1_CH%s + Configure 1 register of Tx channel0 + 0x14C + 0x20 + - L1_DCACHE_UNDEF_OP - Reserved - 8 - 8 + OUT_CHECK_OWNER_CH + Set this bit to enable checking the owner attribute of the link descriptor. + 12 + 1 read-write - L1_BYPASS_CACHE_CONF - Bypass Cache configure register - 0x8 + 3 + 0x68 + OUTFIFO_STATUS_CH%s + Transmit FIFO status of Tx channel0 + 0x150 0x20 + 0x7F808802 - BYPASS_L1_ICACHE0_EN - The bit is used to enable bypass L1-ICache0. 0: disable bypass, 1: enable bypass. + OUTFIFO_L3_FULL_CH + L3 Tx FIFO full signal for Tx channel0. 0 1 - read-write + read-only - BYPASS_L1_ICACHE1_EN - The bit is used to enable bypass L1-ICache1. 0: disable bypass, 1: enable bypass. + OUTFIFO_L3_EMPTY_CH + L3 Tx FIFO empty signal for Tx channel0. 1 1 - read-write + read-only - BYPASS_L1_ICACHE2_EN - Reserved + OUTFIFO_L3_CNT_CH + The register stores the byte number of the data in L3 Tx FIFO for Tx channel0. 2 - 1 + 6 read-only - BYPASS_L1_ICACHE3_EN - Reserved - 3 + OUTFIFO_L3_UDF_CH + L3 Tx FIFO under flow signal for Tx channel0. + 8 1 read-only - BYPASS_L1_DCACHE_EN - The bit is used to enable bypass L1-DCache. 0: disable bypass, 1: enable bypass. - 4 - 1 - read-write - - - - - L1_CACHE_ATOMIC_CONF - L1 Cache atomic feature configure register - 0xC - 0x20 - 0x00000001 - - - L1_DCACHE_ATOMIC_EN - The bit is used to enable atomic feature on L1-DCache when multiple cores access L1-DCache. 1: disable, 1: enable. - 0 - 1 - read-write - - - - - L1_ICACHE_CACHESIZE_CONF - L1 instruction Cache CacheSize mode configure register - 0x10 - 0x20 - 0x00000040 - - - L1_ICACHE_CACHESIZE_256 - The field is used to configure cachesize of L1-ICache as 256 bytes. This field and all other fields within this register is onehot. - 0 + OUTFIFO_L3_OVF_CH + L3 Tx FIFO over flow signal for Tx channel0. + 9 1 read-only - L1_ICACHE_CACHESIZE_512 - The field is used to configure cachesize of L1-ICache as 512 bytes. This field and all other fields within this register is onehot. - 1 + OUTFIFO_L1_FULL_CH + L1 Tx FIFO full signal for Tx channel0. + 10 1 read-only - L1_ICACHE_CACHESIZE_1K - The field is used to configure cachesize of L1-ICache as 1k bytes. This field and all other fields within this register is onehot. - 2 + OUTFIFO_L1_EMPTY_CH + L1 Tx FIFO empty signal for Tx channel0. + 11 1 read-only - L1_ICACHE_CACHESIZE_2K - The field is used to configure cachesize of L1-ICache as 2k bytes. This field and all other fields within this register is onehot. - 3 + OUTFIFO_L1_UDF_CH + L1 Tx FIFO under flow signal for Tx channel0. + 12 1 read-only - L1_ICACHE_CACHESIZE_4K - The field is used to configure cachesize of L1-ICache as 4k bytes. This field and all other fields within this register is onehot. - 4 + OUTFIFO_L1_OVF_CH + L1 Tx FIFO over flow signal for Tx channel0. + 13 1 read-only - L1_ICACHE_CACHESIZE_8K - The field is used to configure cachesize of L1-ICache as 8k bytes. This field and all other fields within this register is onehot. - 5 + OUTFIFO_L2_FULL_CH + L2 Tx RAM full signal for Tx channel0. + 14 1 read-only - L1_ICACHE_CACHESIZE_16K - The field is used to configure cachesize of L1-ICache as 16k bytes. This field and all other fields within this register is onehot. - 6 + OUTFIFO_L2_EMPTY_CH + L2 Tx RAM empty signal for Tx channel0. + 15 1 read-only - L1_ICACHE_CACHESIZE_32K - The field is used to configure cachesize of L1-ICache as 32k bytes. This field and all other fields within this register is onehot. - 7 + OUTFIFO_L2_UDF_CH + L2 Tx FIFO under flow signal for Tx channel0. + 16 1 read-only - L1_ICACHE_CACHESIZE_64K - The field is used to configure cachesize of L1-ICache as 64k bytes. This field and all other fields within this register is onehot. - 8 + OUTFIFO_L2_OVF_CH + L2 Tx FIFO over flow signal for Tx channel0. + 17 1 read-only - L1_ICACHE_CACHESIZE_128K - The field is used to configure cachesize of L1-ICache as 128k bytes. This field and all other fields within this register is onehot. - 9 + OUT_REMAIN_UNDER_1B_CH + reserved + 23 1 read-only - L1_ICACHE_CACHESIZE_256K - The field is used to configure cachesize of L1-ICache as 256k bytes. This field and all other fields within this register is onehot. - 10 + OUT_REMAIN_UNDER_2B_CH + reserved + 24 1 read-only - L1_ICACHE_CACHESIZE_512K - The field is used to configure cachesize of L1-ICache as 512k bytes. This field and all other fields within this register is onehot. - 11 + OUT_REMAIN_UNDER_3B_CH + reserved + 25 1 read-only - L1_ICACHE_CACHESIZE_1024K - The field is used to configure cachesize of L1-ICache as 1024k bytes. This field and all other fields within this register is onehot. - 12 + OUT_REMAIN_UNDER_4B_CH + reserved + 26 1 read-only - - - - L1_ICACHE_BLOCKSIZE_CONF - L1 instruction Cache BlockSize mode configure register - 0x14 - 0x20 - 0x00000008 - - L1_ICACHE_BLOCKSIZE_8 - The field is used to configureblocksize of L1-ICache as 8 bytes. This field and all other fields within this register is onehot. - 0 + OUT_REMAIN_UNDER_5B_CH + reserved + 27 1 read-only - L1_ICACHE_BLOCKSIZE_16 - The field is used to configureblocksize of L1-ICache as 16 bytes. This field and all other fields within this register is onehot. - 1 + OUT_REMAIN_UNDER_6B_CH + reserved + 28 1 read-only - L1_ICACHE_BLOCKSIZE_32 - The field is used to configureblocksize of L1-ICache as 32 bytes. This field and all other fields within this register is onehot. - 2 + OUT_REMAIN_UNDER_7B_CH + reserved + 29 1 read-only - L1_ICACHE_BLOCKSIZE_64 - The field is used to configureblocksize of L1-ICache as 64 bytes. This field and all other fields within this register is onehot. - 3 + OUT_REMAIN_UNDER_8B_CH + reserved + 30 1 read-only + + + + 3 + 0x68 + OUT_PUSH_CH%s + Push control register of Tx channel0 + 0x154 + 0x20 + - L1_ICACHE_BLOCKSIZE_128 - The field is used to configureblocksize of L1-ICache as 128 bytes. This field and all other fields within this register is onehot. - 4 - 1 - read-only + OUTFIFO_WDATA_CH + This register stores the data that need to be pushed into AXI_DMA FIFO. + 0 + 9 + read-write - L1_ICACHE_BLOCKSIZE_256 - The field is used to configureblocksize of L1-ICache as 256 bytes. This field and all other fields within this register is onehot. - 5 + OUTFIFO_PUSH_CH + Set this bit to push data into AXI_DMA FIFO. + 9 1 - read-only + write-only - L1_DCACHE_CACHESIZE_CONF - L1 data Cache CacheSize mode configure register - 0x18 + 3 + 0x68 + OUT_LINK1_CH%s + Link descriptor configure and control register of Tx channel0 + 0x158 0x20 - 0x00000100 + 0x00000008 - L1_DCACHE_CACHESIZE_256 - The field is used to configure cachesize of L1-DCache as 256 bytes. This field and all other fields within this register is onehot. + OUTLINK_STOP_CH + Set this bit to stop dealing with the outlink descriptors. 0 1 - read-only + write-only - L1_DCACHE_CACHESIZE_512 - The field is used to configure cachesize of L1-DCache as 512 bytes. This field and all other fields within this register is onehot. + OUTLINK_START_CH + Set this bit to start dealing with the outlink descriptors. 1 1 - read-only + write-only - L1_DCACHE_CACHESIZE_1K - The field is used to configure cachesize of L1-DCache as 1k bytes. This field and all other fields within this register is onehot. + OUTLINK_RESTART_CH + Set this bit to restart a new outlink from the last address. 2 1 - read-only + write-only - L1_DCACHE_CACHESIZE_2K - The field is used to configure cachesize of L1-DCache as 2k bytes. This field and all other fields within this register is onehot. + OUTLINK_PARK_CH + 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working. 3 1 read-only + + + + 3 + 0x68 + OUT_LINK2_CH%s + Link descriptor configure and control register of Tx channel0 + 0x15C + 0x20 + - L1_DCACHE_CACHESIZE_4K - The field is used to configure cachesize of L1-DCache as 4k bytes. This field and all other fields within this register is onehot. - 4 - 1 - read-only + OUTLINK_ADDR_CH + This register stores the 32 least significant bits of the first outlink descriptor's address. + 0 + 32 + read-write + + + + 3 + 0x68 + OUT_STATE_CH%s + Transmit status of Tx channel0 + 0x160 + 0x20 + - L1_DCACHE_CACHESIZE_8K - The field is used to configure cachesize of L1-DCache as 8k bytes. This field and all other fields within this register is onehot. - 5 - 1 + OUTLINK_DSCR_ADDR_CH + This register stores the current outlink descriptor's address. + 0 + 18 read-only - L1_DCACHE_CACHESIZE_16K - The field is used to configure cachesize of L1-DCache as 16k bytes. This field and all other fields within this register is onehot. - 6 - 1 + OUT_DSCR_STATE_CH + reserved + 18 + 2 read-only - L1_DCACHE_CACHESIZE_32K - The field is used to configure cachesize of L1-DCache as 32k bytes. This field and all other fields within this register is onehot. - 7 - 1 + OUT_STATE_CH + reserved + 20 + 3 read-only + + + + 3 + 0x68 + OUT_EOF_DES_ADDR_CH%s + Outlink descriptor address when EOF occurs of Tx channel0 + 0x164 + 0x20 + - L1_DCACHE_CACHESIZE_64K - The field is used to configure cachesize of L1-DCache as 64k bytes. This field and all other fields within this register is onehot. - 8 - 1 + OUT_EOF_DES_ADDR_CH + This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1. + 0 + 32 read-only + + + + 3 + 0x68 + OUT_EOF_BFR_DES_ADDR_CH%s + The last outlink descriptor address when EOF occurs of Tx channel0 + 0x168 + 0x20 + - L1_DCACHE_CACHESIZE_128K - The field is used to configure cachesize of L1-DCache as 128k bytes. This field and all other fields within this register is onehot. - 9 - 1 + OUT_EOF_BFR_DES_ADDR_CH + This register stores the address of the outlink descriptor before the last outlink descriptor. + 0 + 32 read-only + + + + 3 + 0x68 + OUT_DSCR_CH%s + Current outlink descriptor address of Tx channel0 + 0x16C + 0x20 + - L1_DCACHE_CACHESIZE_256K - The field is used to configure cachesize of L1-DCache as 256k bytes. This field and all other fields within this register is onehot. - 10 - 1 + OUTLINK_DSCR_CH + The address of the current outlink descriptor y. + 0 + 32 read-only + + + + 3 + 0x68 + OUT_DSCR_BF0_CH%s + The last outlink descriptor address of Tx channel0 + 0x170 + 0x20 + - L1_DCACHE_CACHESIZE_512K - The field is used to configure cachesize of L1-DCache as 512k bytes. This field and all other fields within this register is onehot. - 11 - 1 + OUTLINK_DSCR_BF0_CH + The address of the last outlink descriptor y-1. + 0 + 32 read-only + + + + 3 + 0x68 + OUT_DSCR_BF1_CH%s + The second-to-last outlink descriptor address of Tx channel0 + 0x174 + 0x20 + - L1_DCACHE_CACHESIZE_1024K - The field is used to configure cachesize of L1-DCache as 1024k bytes. This field and all other fields within this register is onehot. - 12 - 1 + OUTLINK_DSCR_BF1_CH + The address of the second-to-last outlink descriptor x-2. + 0 + 32 read-only - L1_DCACHE_BLOCKSIZE_CONF - L1 data Cache BlockSize mode configure register - 0x1C + 3 + 0x68 + OUT_PRI_CH%s + Priority register of Tx channel0. + 0x178 0x20 - 0x00000008 - L1_DCACHE_BLOCKSIZE_8 - The field is used to configureblocksize of L1-DCache as 8 bytes. This field and all other fields within this register is onehot. + TX_PRI_CH + The priority of Tx channel0. The larger of the value the higher of the priority. 0 - 1 - read-only + 4 + read-write - L1_DCACHE_BLOCKSIZE_16 - The field is used to configureblocksize of L1-DCache as 16 bytes. This field and all other fields within this register is onehot. - 1 - 1 - read-only + TX_CH_ARB_WEIGH_CH + The weight of Tx channel0 + 4 + 4 + read-write - L1_DCACHE_BLOCKSIZE_32 - The field is used to configureblocksize of L1-DCache as 32 bytes. This field and all other fields within this register is onehot. - 2 + TX_ARB_WEIGH_OPT_DIR_CH + 0: mean not optimazation weight function ,1: mean optimazation + 8 1 - read-only + read-write + + + + 3 + 0x68 + OUT_PERI_SEL_CH%s + Peripheral selection of Tx channel0 + 0x17C + 0x20 + 0x0000003F + - L1_DCACHE_BLOCKSIZE_64 - The field is used to configureblocksize of L1-DCache as 64 bytes. This field and all other fields within this register is onehot. - 3 - 1 - read-only + PERI_OUT_SEL_CH + This register is used to select peripheral for Tx channel0. 0:lcdcam. 1: gpspi_2. 2: gpspi_3. 3: parl_io. 4: aes. 5: sha. 6~15: Dummy + 0 + 6 + read-write + + + + 3 + 0x68 + OUT_CRC_INIT_DATA_CH%s + This register is used to config ch0 crc initial data(max 32 bit) + 0x180 + 0x20 + 0xFFFFFFFF + - L1_DCACHE_BLOCKSIZE_128 - The field is used to configureblocksize of L1-DCache as 128 bytes. This field and all other fields within this register is onehot. - 4 - 1 - read-only + OUT_CRC_INIT_DATA_CH + This register is used to config ch0 of tx crc initial value + 0 + 32 + read-write + + + + + 3 + 0x68 + TX_CRC_WIDTH_CH%s + This register is used to confiig tx ch0 crc result width,2'b00 mean crc_width <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean 24<crc_width<=32 + 0x184 + 0x20 + + + TX_CRC_WIDTH_CH + reserved + 0 + 2 + read-write - L1_DCACHE_BLOCKSIZE_256 - The field is used to configureblocksize of L1-DCache as 256 bytes. This field and all other fields within this register is onehot. - 5 + TX_CRC_LAUTCH_FLGA_CH + reserved + 2 1 - read-only + read-write - L1_CACHE_WRAP_AROUND_CTRL - Cache wrap around control register - 0x20 + 3 + 0x68 + OUT_CRC_CLEAR_CH%s + This register is used to clear ch0 crc result + 0x188 0x20 - L1_ICACHE0_WRAP - Set this bit as 1 to enable L1-ICache0 wrap around mode. + OUT_CRC_CLEAR_CH + This register is used to clear ch0 of tx crc result 0 1 read-write + + + + 3 + 0x68 + OUT_CRC_FINAL_RESULT_CH%s + This register is used to store ch0 crc result + 0x18C + 0x20 + - L1_ICACHE1_WRAP - Set this bit as 1 to enable L1-ICache1 wrap around mode. - 1 - 1 + OUT_CRC_FINAL_RESULT_CH + This register is used to store result ch0 of tx + 0 + 32 + read-only + + + + + 3 + 0x68 + TX_CRC_EN_WR_DATA_CH%s + This resister is used to config ch0 crc en for every bit + 0x190 + 0x20 + + + TX_CRC_EN_WR_DATA_CH + This register is used to enable tx ch0 crc 32bit on/off + 0 + 32 read-write + + + + 3 + 0x68 + TX_CRC_EN_ADDR_CH%s + This register is used to config ch0 crc en addr + 0x194 + 0x20 + - L1_ICACHE2_WRAP - Reserved - 2 - 1 - read-only + TX_CRC_EN_ADDR_CH + reserved + 0 + 32 + read-write + + + + 3 + 0x68 + TX_CRC_DATA_EN_WR_DATA_CH%s + This register is used to config crc data_8bit en + 0x198 + 0x20 + - L1_ICACHE3_WRAP - Reserved - 3 - 1 - read-only + TX_CRC_DATA_EN_WR_DATA_CH + reserved + 0 + 16 + read-write + + + + 3 + 0x68 + TX_CRC_DATA_EN_ADDR_CH%s + This register is used to config addr of crc data_8bit en + 0x19C + 0x20 + - L1_DCACHE_WRAP - Set this bit as 1 to enable L1-DCache wrap around mode. - 4 - 1 + TX_CRC_DATA_EN_ADDR_CH + reserved + 0 + 32 read-write - L1_CACHE_TAG_MEM_POWER_CTRL - Cache tag memory power control register - 0x24 + OUT_CONF0_CH1 + Configure 0 register of Tx channel1 + 0x1B0 0x20 - 0x00055555 + 0x00000008 - L1_ICACHE0_TAG_MEM_FORCE_ON - The bit is used to close clock gating of L1-ICache0 tag memory. 1: close gating, 0: open clock gating. + OUT_RST_CH1 + This bit is used to reset AXI_DMA channel1 Tx FSM and Tx FIFO pointer. 0 1 read-write - L1_ICACHE0_TAG_MEM_FORCE_PD - The bit is used to power L1-ICache0 tag memory down. 0: follow rtc_lslp, 1: power down + OUT_LOOP_TEST_CH1 + reserved 1 1 read-write - L1_ICACHE0_TAG_MEM_FORCE_PU - The bit is used to power L1-ICache0 tag memory up. 0: follow rtc_lslp, 1: power up + OUT_AUTO_WRBACK_CH1 + Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted. 2 1 read-write - L1_ICACHE1_TAG_MEM_FORCE_ON - The bit is used to close clock gating of L1-ICache1 tag memory. 1: close gating, 0: open clock gating. - 4 + OUT_EOF_MODE_CH1 + EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel1 is generated when data need to transmit has been popped from FIFO in AXI_DMA + 3 1 read-write - L1_ICACHE1_TAG_MEM_FORCE_PD - The bit is used to power L1-ICache1 tag memory down. 0: follow rtc_lslp, 1: power down - 5 + OUT_ETM_EN_CH1 + Set this bit to 1 to enable etm control mode, dma Tx channel1 is triggered by etm task. + 4 1 read-write - L1_ICACHE1_TAG_MEM_FORCE_PU - The bit is used to power L1-ICache1 tag memory up. 0: follow rtc_lslp, 1: power up - 6 - 1 + OUT_BURST_SIZE_SEL_CH1 + 3'b000-3'b100:burst length 8byte~128byte + 5 + 3 read-write - L1_ICACHE2_TAG_MEM_FORCE_ON - Reserved + OUT_CMD_DISABLE_CH1 + 1:mean disable cmd of this ch1 8 1 - read-only + read-write - L1_ICACHE2_TAG_MEM_FORCE_PD - Reserved + OUT_ECC_AEC_EN_CH1 + 1: mean access ecc or aes domain,0: mean not 9 1 - read-only + read-write - L1_ICACHE2_TAG_MEM_FORCE_PU - Reserved + OUTDSCR_BURST_EN_CH1 + Set this bit to 1 to enable INCR burst transfer for Tx channel1 reading link descriptor when accessing internal SRAM. 10 1 - read-only - - - L1_ICACHE3_TAG_MEM_FORCE_ON - Reserved - 12 - 1 - read-only - - - L1_ICACHE3_TAG_MEM_FORCE_PD - Reserved - 13 - 1 - read-only - - - L1_ICACHE3_TAG_MEM_FORCE_PU - Reserved - 14 - 1 - read-only - - - L1_DCACHE_TAG_MEM_FORCE_ON - The bit is used to close clock gating of L1-DCache tag memory. 1: close gating, 0: open clock gating. - 16 - 1 - read-write - - - L1_DCACHE_TAG_MEM_FORCE_PD - The bit is used to power L1-DCache tag memory down. 0: follow rtc_lslp, 1: power down - 17 - 1 - read-write - - - L1_DCACHE_TAG_MEM_FORCE_PU - The bit is used to power L1-DCache tag memory up. 0: follow rtc_lslp, 1: power up - 18 - 1 - read-write + read-write - L1_CACHE_DATA_MEM_POWER_CTRL - Cache data memory power control register - 0x28 + OUT_CONF0_CH2 + Configure 0 register of Tx channel2 + 0x218 0x20 - 0x00055555 + 0x00000008 - L1_ICACHE0_DATA_MEM_FORCE_ON - The bit is used to close clock gating of L1-ICache0 data memory. 1: close gating, 0: open clock gating. + OUT_RST_CH2 + This bit is used to reset AXI_DMA channel2 Tx FSM and Tx FIFO pointer. 0 1 read-write - L1_ICACHE0_DATA_MEM_FORCE_PD - The bit is used to power L1-ICache0 data memory down. 0: follow rtc_lslp, 1: power down + OUT_LOOP_TEST_CH2 + reserved 1 1 read-write - L1_ICACHE0_DATA_MEM_FORCE_PU - The bit is used to power L1-ICache0 data memory up. 0: follow rtc_lslp, 1: power up + OUT_AUTO_WRBACK_CH2 + Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted. 2 1 read-write - L1_ICACHE1_DATA_MEM_FORCE_ON - The bit is used to close clock gating of L1-ICache1 data memory. 1: close gating, 0: open clock gating. - 4 + OUT_EOF_MODE_CH2 + EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel2 is generated when data need to transmit has been popped from FIFO in AXI_DMA + 3 1 read-write - L1_ICACHE1_DATA_MEM_FORCE_PD - The bit is used to power L1-ICache1 data memory down. 0: follow rtc_lslp, 1: power down - 5 + OUT_ETM_EN_CH2 + Set this bit to 1 to enable etm control mode, dma Tx channel2 is triggered by etm task. + 4 1 read-write - L1_ICACHE1_DATA_MEM_FORCE_PU - The bit is used to power L1-ICache1 data memory up. 0: follow rtc_lslp, 1: power up - 6 - 1 + OUT_BURST_SIZE_SEL_CH2 + 3'b000-3'b100:burst length 8byte~128byte + 5 + 3 read-write - L1_ICACHE2_DATA_MEM_FORCE_ON - Reserved + OUT_CMD_DISABLE_CH2 + 1:mean disable cmd of this ch2 8 1 - read-only - - - L1_ICACHE2_DATA_MEM_FORCE_PD - Reserved - 9 - 1 - read-only - - - L1_ICACHE2_DATA_MEM_FORCE_PU - Reserved - 10 - 1 - read-only - - - L1_ICACHE3_DATA_MEM_FORCE_ON - Reserved - 12 - 1 - read-only - - - L1_ICACHE3_DATA_MEM_FORCE_PD - Reserved - 13 - 1 - read-only - - - L1_ICACHE3_DATA_MEM_FORCE_PU - Reserved - 14 - 1 - read-only - - - L1_DCACHE_DATA_MEM_FORCE_ON - The bit is used to close clock gating of L1-DCache data memory. 1: close gating, 0: open clock gating. - 16 - 1 read-write - L1_DCACHE_DATA_MEM_FORCE_PD - The bit is used to power L1-DCache data memory down. 0: follow rtc_lslp, 1: power down - 17 + OUT_ECC_AEC_EN_CH2 + 1: mean access ecc or aes domain,0: mean not + 9 1 read-write - L1_DCACHE_DATA_MEM_FORCE_PU - The bit is used to power L1-DCache data memory up. 0: follow rtc_lslp, 1: power up - 18 + OUTDSCR_BURST_EN_CH2 + Set this bit to 1 to enable INCR burst transfer for Tx channel2 reading link descriptor when accessing internal SRAM. + 10 1 read-write - L1_CACHE_FREEZE_CTRL - Cache Freeze control register - 0x2C + ARB_TIMEOUT + This retister is used to config arbiter time slice + 0x270 0x20 - L1_ICACHE0_FREEZE_EN - The bit is used to enable freeze operation on L1-ICache0. It can be cleared by software. + TX + This register is used to config tx arbiter time out value 0 - 1 - read-write - - - L1_ICACHE0_FREEZE_MODE - The bit is used to configure mode of freeze operation L1-ICache0. 0: a miss-access will not stuck. 1: a miss-access will stuck. - 1 - 1 - read-write - - - L1_ICACHE0_FREEZE_DONE - The bit is used to indicate whether freeze operation on L1-ICache0 is finished or not. 0: not finished. 1: finished. - 2 - 1 - read-only - - - L1_ICACHE1_FREEZE_EN - The bit is used to enable freeze operation on L1-ICache1. It can be cleared by software. - 4 - 1 - read-write - - - L1_ICACHE1_FREEZE_MODE - The bit is used to configure mode of freeze operation L1-ICache1. 0: a miss-access will not stuck. 1: a miss-access will stuck. - 5 - 1 + 16 read-write - L1_ICACHE1_FREEZE_DONE - The bit is used to indicate whether freeze operation on L1-ICache1 is finished or not. 0: not finished. 1: finished. - 6 - 1 - read-only - - - L1_ICACHE2_FREEZE_EN - Reserved - 8 - 1 - read-only - - - L1_ICACHE2_FREEZE_MODE - Reserved - 9 - 1 - read-only - - - L1_ICACHE2_FREEZE_DONE - Reserved - 10 - 1 - read-only - - - L1_ICACHE3_FREEZE_EN - Reserved - 12 - 1 - read-only - - - L1_ICACHE3_FREEZE_MODE - Reserved - 13 - 1 - read-only - - - L1_ICACHE3_FREEZE_DONE - Reserved - 14 - 1 - read-only - - - L1_DCACHE_FREEZE_EN - The bit is used to enable freeze operation on L1-DCache. It can be cleared by software. + RX + This register is used to config rx arbiter time out value 16 - 1 - read-write - - - L1_DCACHE_FREEZE_MODE - The bit is used to configure mode of freeze operation L1-DCache. 0: a miss-access will not stuck. 1: a miss-access will stuck. - 17 - 1 + 16 read-write - - L1_DCACHE_FREEZE_DONE - The bit is used to indicate whether freeze operation on L1-DCache is finished or not. 0: not finished. 1: finished. - 18 - 1 - read-only - - L1_CACHE_DATA_MEM_ACS_CONF - Cache data memory access configure register - 0x30 + WEIGHT_EN + This register is used to config arbiter weight function to on or off + 0x274 0x20 - 0x00033333 - L1_ICACHE0_DATA_MEM_RD_EN - The bit is used to enable config-bus read L1-ICache0 data memoryory. 0: disable, 1: enable. + TX + This register is used to config tx arbiter weight function off/on 0 1 read-write - L1_ICACHE0_DATA_MEM_WR_EN - The bit is used to enable config-bus write L1-ICache0 data memoryory. 0: disable, 1: enable. + RX + This register is used to config rx arbiter weight function off/on 1 1 read-write - - L1_ICACHE1_DATA_MEM_RD_EN - The bit is used to enable config-bus read L1-ICache1 data memoryory. 0: disable, 1: enable. - 4 - 1 - read-write - - - L1_ICACHE1_DATA_MEM_WR_EN - The bit is used to enable config-bus write L1-ICache1 data memoryory. 0: disable, 1: enable. - 5 - 1 - read-write - - - L1_ICACHE2_DATA_MEM_RD_EN - Reserved - 8 - 1 - read-only - - - L1_ICACHE2_DATA_MEM_WR_EN - Reserved - 9 - 1 - read-only - - - L1_ICACHE3_DATA_MEM_RD_EN - Reserved - 12 - 1 - read-only - - - L1_ICACHE3_DATA_MEM_WR_EN - Reserved - 13 - 1 - read-only - - - L1_DCACHE_DATA_MEM_RD_EN - The bit is used to enable config-bus read L1-DCache data memoryory. 0: disable, 1: enable. - 16 - 1 - read-write - - - L1_DCACHE_DATA_MEM_WR_EN - The bit is used to enable config-bus write L1-DCache data memoryory. 0: disable, 1: enable. - 17 - 1 - read-write - - L1_CACHE_TAG_MEM_ACS_CONF - Cache tag memory access configure register - 0x34 + IN_MEM_CONF + Mem power configure register of Rx channel + 0x278 0x20 - 0x00033333 - L1_ICACHE0_TAG_MEM_RD_EN - The bit is used to enable config-bus read L1-ICache0 tag memoryory. 0: disable, 1: enable. + IN_MEM_CLK_FORCE_EN + 1: Force to open the clock and bypass the gate-clock when accessing the RAM in AXI_DMA. 0: A gate-clock will be used when accessing the RAM in AXI_DMA. 0 1 read-write - L1_ICACHE0_TAG_MEM_WR_EN - The bit is used to enable config-bus write L1-ICache0 tag memoryory. 0: disable, 1: enable. + IN_MEM_FORCE_PU + Force power up ram 1 1 read-write - L1_ICACHE1_TAG_MEM_RD_EN - The bit is used to enable config-bus read L1-ICache1 tag memoryory. 0: disable, 1: enable. - 4 + IN_MEM_FORCE_PD + Force power down ram + 2 1 read-write - L1_ICACHE1_TAG_MEM_WR_EN - The bit is used to enable config-bus write L1-ICache1 tag memoryory. 0: disable, 1: enable. - 5 + OUT_MEM_CLK_FORCE_EN + 1: Force to open the clock and bypass the gate-clock when accessing the RAM in AXI_DMA. 0: A gate-clock will be used when accessing the RAM in AXI_DMA. + 3 1 read-write - L1_ICACHE2_TAG_MEM_RD_EN - Reserved - 8 - 1 - read-only - - - L1_ICACHE2_TAG_MEM_WR_EN - Reserved - 9 - 1 - read-only - - - L1_ICACHE3_TAG_MEM_RD_EN - Reserved - 12 - 1 - read-only - - - L1_ICACHE3_TAG_MEM_WR_EN - Reserved - 13 - 1 - read-only - - - L1_DCACHE_TAG_MEM_RD_EN - The bit is used to enable config-bus read L1-DCache tag memoryory. 0: disable, 1: enable. - 16 + OUT_MEM_FORCE_PU + Force power up ram + 4 1 read-write - L1_DCACHE_TAG_MEM_WR_EN - The bit is used to enable config-bus write L1-DCache tag memoryory. 0: disable, 1: enable. - 17 + OUT_MEM_FORCE_PD + Force power down ram + 5 1 read-write - L1_ICACHE0_PRELOCK_CONF - L1 instruction Cache 0 prelock configure register - 0x38 + INTR_MEM_START_ADDR + The start address of accessible address space. + 0x27C 0x20 + 0x30100000 - L1_ICACHE0_PRELOCK_SCT0_EN - The bit is used to enable the first section of prelock function on L1-ICache0. + ACCESS_INTR_MEM_START_ADDR + The start address of accessible address space. 0 - 1 - read-write - - - L1_ICACHE0_PRELOCK_SCT1_EN - The bit is used to enable the second section of prelock function on L1-ICache0. - 1 - 1 - read-write - - - L1_ICACHE0_PRELOCK_RGID - The bit is used to set the gid of l1 icache0 prelock. - 2 - 4 + 32 read-write - L1_ICACHE0_PRELOCK_SCT0_ADDR - L1 instruction Cache 0 prelock section0 address configure register - 0x3C + INTR_MEM_END_ADDR + The end address of accessible address space. The access address beyond this range would lead to descriptor error. + 0x280 0x20 + 0x8FFFFFFF - L1_ICACHE0_PRELOCK_SCT0_ADDR - Those bits are used to configure the start virtual address of the first section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT0_SIZE_REG + ACCESS_INTR_MEM_END_ADDR + The end address of accessible address space. The access address beyond this range would lead to descriptor error. 0 32 read-write @@ -7594,14 +7599,15 @@ - L1_ICACHE0_PRELOCK_SCT1_ADDR - L1 instruction Cache 0 prelock section1 address configure register - 0x40 + EXTR_MEM_START_ADDR + The start address of accessible address space. + 0x284 0x20 + 0x30100000 - L1_ICACHE0_PRELOCK_SCT1_ADDR - Those bits are used to configure the start virtual address of the second section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT1_SIZE_REG + ACCESS_EXTR_MEM_START_ADDR + The start address of accessible address space. 0 32 read-write @@ -7609,312 +7615,323 @@ - L1_ICACHE0_PRELOCK_SCT_SIZE - L1 instruction Cache 0 prelock section size configure register - 0x44 + EXTR_MEM_END_ADDR + The end address of accessible address space. The access address beyond this range would lead to descriptor error. + 0x288 0x20 - 0x3FFF3FFF + 0x8FFFFFFF - L1_ICACHE0_PRELOCK_SCT0_SIZE - Those bits are used to configure the size of the first section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT0_ADDR_REG + ACCESS_EXTR_MEM_END_ADDR + The end address of accessible address space. The access address beyond this range would lead to descriptor error. 0 - 14 - read-write - - - L1_ICACHE0_PRELOCK_SCT1_SIZE - Those bits are used to configure the size of the second section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT1_ADDR_REG - 16 - 14 + 32 read-write - L1_ICACHE1_PRELOCK_CONF - L1 instruction Cache 1 prelock configure register - 0x48 + 3 + 0x4 + IN_RESET_AVAIL_CH%s + The rx channel 0 reset valid_flag register. + 0x28C 0x20 + 0x00000001 - L1_ICACHE1_PRELOCK_SCT0_EN - The bit is used to enable the first section of prelock function on L1-ICache1. + IN_RESET_AVAIL_CH + rx chan0 reset valid reg. 0 1 - read-write - - - L1_ICACHE1_PRELOCK_SCT1_EN - The bit is used to enable the second section of prelock function on L1-ICache1. - 1 - 1 - read-write - - - L1_ICACHE1_PRELOCK_RGID - The bit is used to set the gid of l1 icache1 prelock. - 2 - 4 - read-write + read-only - L1_ICACHE1_PRELOCK_SCT0_ADDR - L1 instruction Cache 1 prelock section0 address configure register - 0x4C + 3 + 0x4 + OUT_RESET_AVAIL_CH%s + The tx channel 0 reset valid_flag register. + 0x298 0x20 + 0x00000001 - L1_ICACHE1_PRELOCK_SCT0_ADDR - Those bits are used to configure the start virtual address of the first section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT0_SIZE_REG + OUT_RESET_AVAIL_CH + tx chan0 reset valid reg. 0 - 32 - read-write + 1 + read-only - L1_ICACHE1_PRELOCK_SCT1_ADDR - L1 instruction Cache 1 prelock section1 address configure register - 0x50 + MISC_CONF + MISC register + 0x2A8 0x20 - L1_ICACHE1_PRELOCK_SCT1_ADDR - Those bits are used to configure the start virtual address of the second section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT1_SIZE_REG + AXIM_RST_WR_INTER + Set this bit then clear this bit to reset the internal axi_wr FSM. 0 - 32 + 1 read-write - - - - L1_ICACHE1_PRELOCK_SCT_SIZE - L1 instruction Cache 1 prelock section size configure register - 0x54 - 0x20 - 0x3FFF3FFF - - L1_ICACHE1_PRELOCK_SCT0_SIZE - Those bits are used to configure the size of the first section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT0_ADDR_REG - 0 - 14 + AXIM_RST_RD_INTER + Set this bit then clear this bit to reset the internal axi_rd FSM. + 1 + 1 read-write - L1_ICACHE1_PRELOCK_SCT1_SIZE - Those bits are used to configure the size of the second section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT1_ADDR_REG - 16 - 14 + ARB_PRI_DIS + Set this bit to disable priority arbitration function. + 3 + 1 + read-write + + + CLK_EN + 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers. + 4 + 1 read-write - L1_ICACHE2_PRELOCK_CONF - L1 instruction Cache 2 prelock configure register - 0x58 + RDN_RESULT + reserved + 0x2AC 0x20 - L1_ICACHE2_PRELOCK_SCT0_EN - The bit is used to enable the first section of prelock function on L1-ICache2. + RDN_ENA + reserved 0 1 - read-only + read-write - L1_ICACHE2_PRELOCK_SCT1_EN - The bit is used to enable the second section of prelock function on L1-ICache2. + RDN_RESULT + reserved 1 1 read-only - - L1_ICACHE2_PRELOCK_RGID - The bit is used to set the gid of l1 icache2 prelock. - 2 - 4 - read-only - - L1_ICACHE2_PRELOCK_SCT0_ADDR - L1 instruction Cache 2 prelock section0 address configure register - 0x5C + RDN_ECO_HIGH + reserved + 0x2B0 0x20 + 0xFFFFFFFF - L1_ICACHE2_PRELOCK_SCT0_ADDR - Those bits are used to configure the start virtual address of the first section of prelock on L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT0_SIZE_REG + RDN_ECO_HIGH + The start address of accessible address space. 0 32 - read-only + read-write - L1_ICACHE2_PRELOCK_SCT1_ADDR - L1 instruction Cache 2 prelock section1 address configure register - 0x60 + RDN_ECO_LOW + reserved + 0x2B4 0x20 - L1_ICACHE2_PRELOCK_SCT1_ADDR - Those bits are used to configure the start virtual address of the second section of prelock on L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT1_SIZE_REG + RDN_ECO_LOW + The start address of accessible address space. 0 32 - read-only + read-write - L1_ICACHE2_PRELOCK_SCT_SIZE - L1 instruction Cache 2 prelock section size configure register - 0x64 + WRESP_CNT + AXI wr responce cnt register. + 0x2B8 0x20 - 0x3FFF3FFF - L1_ICACHE2_PRELOCK_SCT0_SIZE - Those bits are used to configure the size of the first section of prelock on L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT0_ADDR_REG + WRESP_CNT + axi wr responce cnt reg. 0 - 14 - read-only - - - L1_ICACHE2_PRELOCK_SCT1_SIZE - Those bits are used to configure the size of the second section of prelock on L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT1_ADDR_REG - 16 - 14 + 4 read-only - L1_ICACHE3_PRELOCK_CONF - L1 instruction Cache 3 prelock configure register - 0x68 + RRESP_CNT + AXI wr responce cnt register. + 0x2BC 0x20 - L1_ICACHE3_PRELOCK_SCT0_EN - The bit is used to enable the first section of prelock function on L1-ICache3. + RRESP_CNT + axi rd responce cnt reg. 0 - 1 + 4 read-only + + + + 3 + 0x4 + INFIFO_STATUS1_CH%s + Receive FIFO status of Rx channel 0 + 0x2C0 + 0x20 + - L1_ICACHE3_PRELOCK_SCT1_EN - The bit is used to enable the second section of prelock function on L1-ICache3. - 1 - 1 + L1INFIFO_CNT_CH + The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0. + 0 + 6 read-only - L1_ICACHE3_PRELOCK_RGID - The bit is used to set the gid of l1 icache3 prelock. - 2 + L2INFIFO_CNT_CH + The register stores the byte number of the data in L2 Rx FIFO for Rx channel 0. + 6 4 read-only - L1_ICACHE3_PRELOCK_SCT0_ADDR - L1 instruction Cache 3 prelock section0 address configure register - 0x6C + 3 + 0x4 + OUTFIFO_STATUS1_CH%s + Receive FIFO status of Tx channel 0 + 0x2CC 0x20 - L1_ICACHE3_PRELOCK_SCT0_ADDR - Those bits are used to configure the start virtual address of the first section of prelock on L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT0_SIZE_REG + L1OUTFIFO_CNT_CH + The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0. 0 - 32 + 6 + read-only + + + L2OUTFIFO_CNT_CH + The register stores the byte number of the data in L2 Tx FIFO for Tx channel 0. + 6 + 4 read-only - L1_ICACHE3_PRELOCK_SCT1_ADDR - L1 instruction Cache 3 prelock section1 address configure register - 0x70 + DATE + Version control register + 0x2D8 0x20 + 0x02303140 - L1_ICACHE3_PRELOCK_SCT1_ADDR - Those bits are used to configure the start virtual address of the second section of prelock on L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT1_SIZE_REG + DATE + register version. 0 32 - read-only + read-write + + + + BITSCRAMBLER + BITSCRAMBLER Peripheral + BITSCRAMBLER + 0x500A3000 + + 0x0 + 0x40 + registers + + - L1_ICACHE3_PRELOCK_SCT_SIZE - L1 instruction Cache 3 prelock section size configure register - 0x74 + TX_INST_CFG0 + Control and configuration registers + 0x0 0x20 - 0x3FFF3FFF - L1_ICACHE3_PRELOCK_SCT0_SIZE - Those bits are used to configure the size of the first section of prelock on L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT0_ADDR_REG + TX_INST_IDX + write this bits to specify the one of 8 instruction 0 - 14 - read-only + 3 + read-write - L1_ICACHE3_PRELOCK_SCT1_SIZE - Those bits are used to configure the size of the second section of prelock on L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT1_ADDR_REG - 16 - 14 - read-only + TX_INST_POS + write this bits to specify the bit position of 257 bit instruction which in units of 32 bits + 3 + 4 + read-write - L1_DCACHE_PRELOCK_CONF - L1 data Cache prelock configure register - 0x78 + TX_INST_CFG1 + Control and configuration registers + 0x4 0x20 + 0x00000004 - L1_DCACHE_PRELOCK_SCT0_EN - The bit is used to enable the first section of prelock function on L1-DCache. + TX_INST + write this bits to update instruction which specified by BITSCRAMBLER_TX_INST_CFG0_REG, Read this bits to get instruction which specified by BITSCRAMBLER_TX_INST_CFG0_REG 0 - 1 + 32 read-write + + + + RX_INST_CFG0 + Control and configuration registers + 0x8 + 0x20 + - L1_DCACHE_PRELOCK_SCT1_EN - The bit is used to enable the second section of prelock function on L1-DCache. - 1 - 1 + RX_INST_IDX + write this bits to specify the one of 8 instruction + 0 + 3 read-write - L1_DCACHE_PRELOCK_RGID - The bit is used to set the gid of l1 dcache prelock. - 2 + RX_INST_POS + write this bits to specify the bit position of 257 bit instruction which in units of 32 bits + 3 4 read-write - L1_DCACHE_PRELOCK_SCT0_ADDR - L1 data Cache prelock section0 address configure register - 0x7C + RX_INST_CFG1 + Control and configuration registers + 0xC 0x20 + 0x0000000C - L1_DCACHE_PRELOCK_SCT0_ADDR - Those bits are used to configure the start virtual address of the first section of prelock on L1-DCache, which should be used together with L1_DCACHE_PRELOCK_SCT0_SIZE_REG + RX_INST + write this bits to update instruction which specified by BITSCRAMBLER_RX_INST_CFG0_REG, Read this bits to get instruction which specified by BITSCRAMBLER_RX_INST_CFG0_REG 0 32 read-write @@ -7922,119 +7939,105 @@ - L1_DCACHE_PRELOCK_SCT1_ADDR - L1 data Cache prelock section1 address configure register - 0x80 + TX_LUT_CFG0 + Control and configuration registers + 0x10 0x20 - L1_DCACHE_PRELOCK_SCT1_ADDR - Those bits are used to configure the start virtual address of the second section of prelock on L1-DCache, which should be used together with L1_DCACHE_PRELOCK_SCT1_SIZE_REG + TX_LUT_IDX + write this bits to specify the bytes position of LUT RAM based on reg_bitscrambler_tx_lut_mode 0 - 32 + 11 + read-write + + + TX_LUT_MODE + write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4 bytes + 11 + 2 read-write - L1_DCACHE_PRELOCK_SCT_SIZE - L1 data Cache prelock section size configure register - 0x84 + TX_LUT_CFG1 + Control and configuration registers + 0x14 0x20 - 0x3FFF3FFF + 0x00000014 - L1_DCACHE_PRELOCK_SCT0_SIZE - Those bits are used to configure the size of the first section of prelock on L1-DCache, which should be used together with L1_DCACHE_PRELOCK_SCT0_ADDR_REG + TX_LUT + write this bits to update LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG, Read this bits to get LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG 0 - 14 - read-write - - - L1_DCACHE_PRELOCK_SCT1_SIZE - Those bits are used to configure the size of the second section of prelock on L1-DCache, which should be used together with L1_DCACHE_PRELOCK_SCT1_ADDR_REG - 16 - 14 + 32 read-write - LOCK_CTRL - Lock-class (manual lock) operation control register - 0x88 + RX_LUT_CFG0 + Control and configuration registers + 0x18 0x20 - 0x00000004 - LOCK_ENA - The bit is used to enable lock operation. It will be cleared by hardware after lock operation done. Note that (1) this bit and unlock_ena bit are mutually exclusive, that is, those bits can not be set to 1 at the same time. (2) lock operation can be applied on LL1-ICache, L1-DCache and L2-Cache. + RX_LUT_IDX + write this bits to specify the bytes position of LUT RAM based on reg_bitscrambler_rx_lut_mode 0 - 1 - read-write - - - UNLOCK_ENA - The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done. Note that (1) this bit and lock_ena bit are mutually exclusive, that is, those bits can not be set to 1 at the same time. (2) unlock operation can be applied on L1-ICache, L1-DCache and L2-Cache. - 1 - 1 + 11 read-write - LOCK_DONE - The bit is used to indicate whether unlock/lock operation is finished or not. 0: not finished. 1: finished. - 2 - 1 - read-only - - - LOCK_RGID - The bit is used to set the gid of cache lock/unlock. - 3 - 4 + RX_LUT_MODE + write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4 bytes + 11 + 2 read-write - LOCK_MAP - Lock (manual lock) map configure register - 0x8C + RX_LUT_CFG1 + Control and configuration registers + 0x1C 0x20 + 0x0000001C - LOCK_MAP - Those bits are used to indicate which caches in the two-level cache structure will apply this lock/unlock operation. [0]: L1-ICache0, [1]: L1-ICache1, [2]: L1-ICache2, [3]: L1-ICache3, [4]: L1-DCache, [5]: L2-Cache. + RX_LUT + write this bits to update LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG, Read this bits to get LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG 0 - 6 + 32 read-write - LOCK_ADDR - Lock (manual lock) address configure register - 0x90 + TX_TAILING_BITS + Control and configuration registers + 0x20 0x20 - LOCK_ADDR - Those bits are used to configure the start virtual address of the lock/unlock operation, which should be used together with CACHE_LOCK_SIZE_REG + TX_TAILING_BITS + write this bits to specify the extra data bit length after getting EOF 0 - 32 + 16 read-write - LOCK_SIZE - Lock (manual lock) size configure register - 0x94 + RX_TAILING_BITS + Control and configuration registers + 0x24 0x20 - LOCK_SIZE - Those bits are used to configure the size of the lock/unlock operation, which should be used together with CACHE_LOCK_ADDR_REG + RX_TAILING_BITS + write this bits to specify the extra data bit length after getting EOF 0 16 read-write @@ -8042,1821 +8045,1532 @@ - SYNC_CTRL - Sync-class operation control register - 0x98 + TX_CTRL + Control and configuration registers + 0x28 0x20 - 0x00000001 + 0x00000004 - INVALIDATE_ENA - The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done. Note that this bit and the other sync-bits (clean_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those bits can not be set to 1 at the same time. + TX_ENA + write this bit to enable the bitscrambler tx 0 1 read-write - CLEAN_ENA - The bit is used to enable clean operation. It will be cleared by hardware after clean operation done. Note that this bit and the other sync-bits (invalidate_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those bits can not be set to 1 at the same time. + TX_PAUSE + write this bit to pause the bitscrambler tx core 1 1 read-write - WRITEBACK_ENA - The bit is used to enable writeback operation. It will be cleared by hardware after writeback operation done. Note that this bit and the other sync-bits (invalidate_ena, clean_ena, writeback_invalidate_ena) are mutually exclusive, that is, those bits can not be set to 1 at the same time. + TX_HALT + write this bit to halt the bitscrambler tx core 2 1 read-write - WRITEBACK_INVALIDATE_ENA - The bit is used to enable writeback-invalidate operation. It will be cleared by hardware after writeback-invalidate operation done. Note that this bit and the other sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive, that is, those bits can not be set to 1 at the same time. + TX_EOF_MODE + write this bit to ser the bitscrambler tx core EOF signal generating mode which is combined with reg_bitscrambler_tx_tailing_bits, 0: counter by read dma fifo, 0 counter by write peripheral buffer 3 1 read-write - SYNC_DONE - The bit is used to indicate whether sync operation (invalidate, clean, writeback, writeback_invalidate) is finished or not. 0: not finished. 1: finished. + TX_COND_MODE + write this bit to specify the LOOP instruction condition mode of bitscrambler tx core, 0: use the little than operator to get the condition, 1: use not equal operator to get the condition 4 1 - read-only + read-write - SYNC_RGID - The bit is used to set the gid of cache sync operation (invalidate, clean, writeback, writeback_invalidate) + TX_FETCH_MODE + write this bit to set the bitscrambler tx core fetch instruction mode, 0: prefetch by reset, 1: fetch by instrutions 5 - 4 + 1 read-write - - - - SYNC_MAP - Sync map configure register - 0x9C - 0x20 - 0x0000001F - - SYNC_MAP - Those bits are used to indicate which caches in the two-level cache structure will apply the sync operation. [0]: L1-ICache0, [1]: L1-ICache1, [2]: L1-ICache2, [3]: L1-ICache3, [4]: L1-DCache, [5]: L2-Cache. - 0 - 6 + TX_HALT_MODE + write this bit to set the bitscrambler tx core halt mode when tx_halt is set, 0: wait write data back done, , 1: ignore write data back + 6 + 1 read-write - - - - SYNC_ADDR - Sync address configure register - 0xA0 - 0x20 - - SYNC_ADDR - Those bits are used to configure the start virtual address of the sync operation, which should be used together with CACHE_SYNC_SIZE_REG - 0 - 32 + TX_RD_DUMMY + write this bit to set the bitscrambler tx core read data mode when EOF received.0: wait read data, 1: ignore read data + 7 + 1 read-write - - - - SYNC_SIZE - Sync size configure register - 0xA4 - 0x20 - - SYNC_SIZE - Those bits are used to configure the size of the sync operation, which should be used together with CACHE_SYNC_ADDR_REG - 0 - 28 - read-write + TX_FIFO_RST + write this bit to reset the bitscrambler tx fifo + 8 + 1 + write-only - L1_ICACHE0_PRELOAD_CTRL - L1 instruction Cache 0 preload-operation control register - 0xA8 + RX_CTRL + Control and configuration registers + 0x2C 0x20 - 0x00000002 + 0x00000004 - L1_ICACHE0_PRELOAD_ENA - The bit is used to enable preload operation on L1-ICache0. It will be cleared by hardware automatically after preload operation is done. + RX_ENA + write this bit to enable the bitscrambler rx 0 1 read-write - L1_ICACHE0_PRELOAD_DONE - The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished. + RX_PAUSE + write this bit to pause the bitscrambler rx core 1 1 - read-only + read-write - L1_ICACHE0_PRELOAD_ORDER - The bit is used to configure the direction of preload operation. 0: ascending, 1: descending. + RX_HALT + write this bit to halt the bitscrambler rx core 2 1 read-write - L1_ICACHE0_PRELOAD_RGID - The bit is used to set the gid of l1 icache0 preload. + RX_EOF_MODE + write this bit to ser the bitscrambler rx core EOF signal generating mode which is combined with reg_bitscrambler_rx_tailing_bits, 0: counter by read peripheral buffer, 0 counter by write dma fifo 3 - 4 + 1 read-write - - - - L1_ICACHE0_PRELOAD_ADDR - L1 instruction Cache 0 preload address configure register - 0xAC - 0x20 - - L1_ICACHE0_PRELOAD_ADDR - Those bits are used to configure the start virtual address of preload on L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_SIZE_REG - 0 - 32 + RX_COND_MODE + write this bit to specify the LOOP instruction condition mode of bitscrambler rx core, 0: use the little than operator to get the condition, 1: use not equal operator to get the condition + 4 + 1 read-write - - - - L1_ICACHE0_PRELOAD_SIZE - L1 instruction Cache 0 preload size configure register - 0xB0 - 0x20 - - L1_ICACHE0_PRELOAD_SIZE - Those bits are used to configure the size of the first section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_ADDR_REG - 0 - 14 + RX_FETCH_MODE + write this bit to set the bitscrambler rx core fetch instruction mode, 0: prefetch by reset, 1: fetch by instrutions + 5 + 1 read-write - - - - L1_ICACHE1_PRELOAD_CTRL - L1 instruction Cache 1 preload-operation control register - 0xB4 - 0x20 - 0x00000002 - - L1_ICACHE1_PRELOAD_ENA - The bit is used to enable preload operation on L1-ICache1. It will be cleared by hardware automatically after preload operation is done. - 0 + RX_HALT_MODE + write this bit to set the bitscrambler rx core halt mode when rx_halt is set, 0: wait write data back done, , 1: ignore write data back + 6 1 read-write - L1_ICACHE1_PRELOAD_DONE - The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished. - 1 - 1 - read-only - - - L1_ICACHE1_PRELOAD_ORDER - The bit is used to configure the direction of preload operation. 0: ascending, 1: descending. - 2 + RX_RD_DUMMY + write this bit to set the bitscrambler rx core read data mode when EOF received.0: wait read data, 1: ignore read data + 7 1 read-write - L1_ICACHE1_PRELOAD_RGID - The bit is used to set the gid of l1 icache1 preload. - 3 - 4 - read-write - - - - - L1_ICACHE1_PRELOAD_ADDR - L1 instruction Cache 1 preload address configure register - 0xB8 - 0x20 - - - L1_ICACHE1_PRELOAD_ADDR - Those bits are used to configure the start virtual address of preload on L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_SIZE_REG - 0 - 32 - read-write - - - - - L1_ICACHE1_PRELOAD_SIZE - L1 instruction Cache 1 preload size configure register - 0xBC - 0x20 - - - L1_ICACHE1_PRELOAD_SIZE - Those bits are used to configure the size of the first section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_ADDR_REG - 0 - 14 - read-write + RX_FIFO_RST + write this bit to reset the bitscrambler rx fifo + 8 + 1 + write-only - L1_ICACHE2_PRELOAD_CTRL - L1 instruction Cache 2 preload-operation control register - 0xC0 + TX_STATE + Status registers + 0x30 0x20 - 0x00000002 + 0x00000001 - L1_ICACHE2_PRELOAD_ENA - The bit is used to enable preload operation on L1-ICache2. It will be cleared by hardware automatically after preload operation is done. + TX_IN_IDLE + represents the bitscrambler tx core in halt mode 0 1 read-only - L1_ICACHE2_PRELOAD_DONE - The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished. + TX_IN_RUN + represents the bitscrambler tx core in run mode 1 1 read-only - L1_ICACHE2_PRELOAD_ORDER - The bit is used to configure the direction of preload operation. 0: ascending, 1: descending. + TX_IN_WAIT + represents the bitscrambler tx core in wait mode to wait write back done 2 1 read-only - L1_ICACHE2_PRELOAD_RGID - The bit is used to set the gid of l1 icache2 preload. + TX_IN_PAUSE + represents the bitscrambler tx core in pause mode 3 - 4 + 1 read-only - - - - L1_ICACHE2_PRELOAD_ADDR - L1 instruction Cache 2 preload address configure register - 0xC4 - 0x20 - - L1_ICACHE2_PRELOAD_ADDR - Those bits are used to configure the start virtual address of preload on L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_SIZE_REG - 0 - 32 + TX_FIFO_EMPTY + represents the bitscrambler tx fifo in empty state + 4 + 1 read-only - - - - L1_ICACHE2_PRELOAD_SIZE - L1 instruction Cache 2 preload size configure register - 0xC8 - 0x20 - - L1_ICACHE2_PRELOAD_SIZE - Those bits are used to configure the size of the first section of prelock on L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_ADDR_REG - 0 + TX_EOF_GET_CNT + represents the bytes numbers of bitscrambler tx core when get EOF + 16 14 read-only + + TX_EOF_OVERLOAD + represents the some EOFs will be lost for bitscrambler tx core + 30 + 1 + read-only + + + TX_EOF_TRACE_CLR + write this bit to clear reg_bitscrambler_tx_eof_overload and reg_bitscrambler_tx_eof_get_cnt registers + 31 + 1 + write-only + - L1_ICACHE3_PRELOAD_CTRL - L1 instruction Cache 3 preload-operation control register - 0xCC + RX_STATE + Status registers + 0x34 0x20 - 0x00000002 + 0x00000001 - L1_ICACHE3_PRELOAD_ENA - The bit is used to enable preload operation on L1-ICache3. It will be cleared by hardware automatically after preload operation is done. + RX_IN_IDLE + represents the bitscrambler rx core in halt mode 0 1 read-only - L1_ICACHE3_PRELOAD_DONE - The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished. + RX_IN_RUN + represents the bitscrambler rx core in run mode 1 1 read-only - L1_ICACHE3_PRELOAD_ORDER - The bit is used to configure the direction of preload operation. 0: ascending, 1: descending. + RX_IN_WAIT + represents the bitscrambler rx core in wait mode to wait write back done 2 1 read-only - L1_ICACHE3_PRELOAD_RGID - The bit is used to set the gid of l1 icache3 preload. + RX_IN_PAUSE + represents the bitscrambler rx core in pause mode 3 - 4 + 1 read-only - - - - L1_ICACHE3_PRELOAD_ADDR - L1 instruction Cache 3 preload address configure register - 0xD0 - 0x20 - - L1_ICACHE3_PRELOAD_ADDR - Those bits are used to configure the start virtual address of preload on L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_SIZE_REG - 0 - 32 + RX_FIFO_FULL + represents the bitscrambler rx fifo in full state + 4 + 1 read-only - - - - L1_ICACHE3_PRELOAD_SIZE - L1 instruction Cache 3 preload size configure register - 0xD4 - 0x20 - - L1_ICACHE3_PRELOAD_SIZE - Those bits are used to configure the size of the first section of prelock on L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_ADDR_REG - 0 + RX_EOF_GET_CNT + represents the bytes numbers of bitscrambler rx core when get EOF + 16 14 read-only - - - - L1_DCACHE_PRELOAD_CTRL - L1 data Cache preload-operation control register - 0xD8 - 0x20 - 0x00000002 - - - L1_DCACHE_PRELOAD_ENA - The bit is used to enable preload operation on L1-DCache. It will be cleared by hardware automatically after preload operation is done. - 0 - 1 - read-write - - L1_DCACHE_PRELOAD_DONE - The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished. - 1 + RX_EOF_OVERLOAD + represents the some EOFs will be lost for bitscrambler rx core + 30 1 read-only - L1_DCACHE_PRELOAD_ORDER - The bit is used to configure the direction of preload operation. 0: ascending, 1: descending. - 2 + RX_EOF_TRACE_CLR + write this bit to clear reg_bitscrambler_rx_eof_overload and reg_bitscrambler_rx_eof_get_cnt registers + 31 1 - read-write - - - L1_DCACHE_PRELOAD_RGID - The bit is used to set the gid of l1 dcache preload. - 3 - 4 - read-write + write-only - L1_DCACHE_PRELOAD_ADDR - L1 data Cache preload address configure register - 0xDC + SYS + Control and configuration registers + 0xF8 0x20 - L1_DCACHE_PRELOAD_ADDR - Those bits are used to configure the start virtual address of preload on L1-DCache, which should be used together with L1_DCACHE_PRELOAD_SIZE_REG + LOOP_MODE + write this bit to set the bitscrambler tx loop back to DMA rx 0 - 32 + 1 + read-write + + + CLK_EN + Reserved + 31 + 1 read-write - L1_DCACHE_PRELOAD_SIZE - L1 data Cache preload size configure register - 0xE0 + VERSION + Control and configuration registers + 0xFC 0x20 + 0x02303240 - L1_DCACHE_PRELOAD_SIZE - Those bits are used to configure the size of the first section of prelock on L1-DCache, which should be used together with L1_DCACHE_PRELOAD_ADDR_REG + BITSCRAMBLER_VER + Reserved 0 - 14 + 28 read-write + + + + CACHE + CACHE Peripheral + CACHE + 0x3FF10000 + + 0x0 + 0x3F0 + registers + + + CACHE + 83 + + - L1_ICACHE0_AUTOLOAD_CTRL - L1 instruction Cache 0 autoload-operation control register - 0xE4 + L1_ICACHE_CTRL + L1 instruction Cache(L1-ICache) control register + 0x0 0x20 - 0x00000002 - L1_ICACHE0_AUTOLOAD_ENA - The bit is used to enable and disable autoload operation on L1-ICache0. 1: enable, 0: disable. + L1_ICACHE_SHUT_IBUS0 + The bit is used to disable core0 ibus access L1-ICache, 0: enable, 1: disable 0 1 read-write - L1_ICACHE0_AUTOLOAD_DONE - The bit is used to indicate whether autoload operation on L1-ICache0 is finished or not. 0: not finished. 1: finished. + L1_ICACHE_SHUT_IBUS1 + The bit is used to disable core1 ibus access L1-ICache, 0: enable, 1: disable 1 1 - read-only + read-write - L1_ICACHE0_AUTOLOAD_ORDER - The bit is used to configure the direction of autoload operation on L1-ICache0. 0: ascending. 1: descending. + L1_ICACHE_SHUT_IBUS2 + Reserved 2 1 - read-write + read-only - L1_ICACHE0_AUTOLOAD_TRIGGER_MODE - The field is used to configure trigger mode of autoload operation on L1-ICache0. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + L1_ICACHE_SHUT_IBUS3 + Reserved 3 - 2 - read-write - - - L1_ICACHE0_AUTOLOAD_SCT0_ENA - The bit is used to enable the first section for autoload operation on L1-ICache0. - 8 - 1 - read-write - - - L1_ICACHE0_AUTOLOAD_SCT1_ENA - The bit is used to enable the second section for autoload operation on L1-ICache0. - 9 1 - read-write + read-only - L1_ICACHE0_AUTOLOAD_RGID - The bit is used to set the gid of l1 icache0 autoload. - 10 - 4 + L1_ICACHE_UNDEF_OP + Reserved + 8 + 8 read-write - L1_ICACHE0_AUTOLOAD_SCT0_ADDR - L1 instruction Cache 0 autoload section 0 address configure register - 0xE8 + L1_DCACHE_CTRL + L1 data Cache(L1-DCache) control register + 0x4 0x20 - L1_ICACHE0_AUTOLOAD_SCT0_ADDR - Those bits are used to configure the start virtual address of the first section for autoload operation on L1-ICache0. Note that it should be used together with L1_ICACHE0_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. + L1_DCACHE_SHUT_DBUS0 + The bit is used to disable core0 dbus access L1-DCache, 0: enable, 1: disable 0 - 32 + 1 read-write - - - - L1_ICACHE0_AUTOLOAD_SCT0_SIZE - L1 instruction Cache 0 autoload section 0 size configure register - 0xEC - 0x20 - - L1_ICACHE0_AUTOLOAD_SCT0_SIZE - Those bits are used to configure the size of the first section for autoload operation on L1-ICache0. Note that it should be used together with L1_ICACHE0_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. - 0 - 28 + L1_DCACHE_SHUT_DBUS1 + The bit is used to disable core1 dbus access L1-DCache, 0: enable, 1: disable + 1 + 1 read-write - - - - L1_ICACHE0_AUTOLOAD_SCT1_ADDR - L1 instruction Cache 0 autoload section 1 address configure register - 0xF0 - 0x20 - - L1_ICACHE0_AUTOLOAD_SCT1_ADDR - Those bits are used to configure the start virtual address of the second section for autoload operation on L1-ICache0. Note that it should be used together with L1_ICACHE0_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. - 0 - 32 + L1_DCACHE_SHUT_DBUS2 + Reserved + 2 + 1 + read-only + + + L1_DCACHE_SHUT_DBUS3 + Reserved + 3 + 1 + read-only + + + L1_DCACHE_SHUT_DMA + The bit is used to disable DMA access L1-DCache, 0: enable, 1: disable + 4 + 1 read-write - - - - L1_ICACHE0_AUTOLOAD_SCT1_SIZE - L1 instruction Cache 0 autoload section 1 size configure register - 0xF4 - 0x20 - - L1_ICACHE0_AUTOLOAD_SCT1_SIZE - Those bits are used to configure the size of the second section for autoload operation on L1-ICache0. Note that it should be used together with L1_ICACHE0_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA. - 0 - 28 + L1_DCACHE_UNDEF_OP + Reserved + 8 + 8 read-write - L1_ICACHE1_AUTOLOAD_CTRL - L1 instruction Cache 1 autoload-operation control register - 0xF8 + L1_BYPASS_CACHE_CONF + Bypass Cache configure register + 0x8 0x20 - 0x00000002 - L1_ICACHE1_AUTOLOAD_ENA - The bit is used to enable and disable autoload operation on L1-ICache1. 1: enable, 0: disable. + BYPASS_L1_ICACHE0_EN + The bit is used to enable bypass L1-ICache0. 0: disable bypass, 1: enable bypass. 0 1 read-write - L1_ICACHE1_AUTOLOAD_DONE - The bit is used to indicate whether autoload operation on L1-ICache1 is finished or not. 0: not finished. 1: finished. + BYPASS_L1_ICACHE1_EN + The bit is used to enable bypass L1-ICache1. 0: disable bypass, 1: enable bypass. 1 1 - read-only + read-write - L1_ICACHE1_AUTOLOAD_ORDER - The bit is used to configure the direction of autoload operation on L1-ICache1. 0: ascending. 1: descending. + BYPASS_L1_ICACHE2_EN + Reserved 2 1 - read-write + read-only - L1_ICACHE1_AUTOLOAD_TRIGGER_MODE - The field is used to configure trigger mode of autoload operation on L1-ICache1. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + BYPASS_L1_ICACHE3_EN + Reserved 3 - 2 - read-write - - - L1_ICACHE1_AUTOLOAD_SCT0_ENA - The bit is used to enable the first section for autoload operation on L1-ICache1. - 8 1 - read-write + read-only - L1_ICACHE1_AUTOLOAD_SCT1_ENA - The bit is used to enable the second section for autoload operation on L1-ICache1. - 9 + BYPASS_L1_DCACHE_EN + The bit is used to enable bypass L1-DCache. 0: disable bypass, 1: enable bypass. + 4 1 read-write - - L1_ICACHE1_AUTOLOAD_RGID - The bit is used to set the gid of l1 icache1 autoload. - 10 - 4 - read-write - - - - - L1_ICACHE1_AUTOLOAD_SCT0_ADDR - L1 instruction Cache 1 autoload section 0 address configure register - 0xFC - 0x20 - - - L1_ICACHE1_AUTOLOAD_SCT0_ADDR - Those bits are used to configure the start virtual address of the first section for autoload operation on L1-ICache1. Note that it should be used together with L1_ICACHE1_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. - 0 - 32 - read-write - - L1_ICACHE1_AUTOLOAD_SCT0_SIZE - L1 instruction Cache 1 autoload section 0 size configure register - 0x100 + L1_CACHE_ATOMIC_CONF + L1 Cache atomic feature configure register + 0xC 0x20 + 0x00000001 - L1_ICACHE1_AUTOLOAD_SCT0_SIZE - Those bits are used to configure the size of the first section for autoload operation on L1-ICache1. Note that it should be used together with L1_ICACHE1_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. + L1_DCACHE_ATOMIC_EN + The bit is used to enable atomic feature on L1-DCache when multiple cores access L1-DCache. 1: disable, 1: enable. 0 - 28 + 1 read-write - L1_ICACHE1_AUTOLOAD_SCT1_ADDR - L1 instruction Cache 1 autoload section 1 address configure register - 0x104 + L1_ICACHE_CACHESIZE_CONF + L1 instruction Cache CacheSize mode configure register + 0x10 0x20 + 0x00000040 - L1_ICACHE1_AUTOLOAD_SCT1_ADDR - Those bits are used to configure the start virtual address of the second section for autoload operation on L1-ICache1. Note that it should be used together with L1_ICACHE1_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. + L1_ICACHE_CACHESIZE_256 + The field is used to configure cachesize of L1-ICache as 256 bytes. This field and all other fields within this register is onehot. 0 - 32 - read-write + 1 + read-only - - - - L1_ICACHE1_AUTOLOAD_SCT1_SIZE - L1 instruction Cache 1 autoload section 1 size configure register - 0x108 - 0x20 - - L1_ICACHE1_AUTOLOAD_SCT1_SIZE - Those bits are used to configure the size of the second section for autoload operation on L1-ICache1. Note that it should be used together with L1_ICACHE1_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA. - 0 - 28 - read-write + L1_ICACHE_CACHESIZE_512 + The field is used to configure cachesize of L1-ICache as 512 bytes. This field and all other fields within this register is onehot. + 1 + 1 + read-only - - - - L1_ICACHE2_AUTOLOAD_CTRL - L1 instruction Cache 2 autoload-operation control register - 0x10C - 0x20 - 0x00000002 - - L1_ICACHE2_AUTOLOAD_ENA - The bit is used to enable and disable autoload operation on L1-ICache2. 1: enable, 0: disable. - 0 + L1_ICACHE_CACHESIZE_1K + The field is used to configure cachesize of L1-ICache as 1k bytes. This field and all other fields within this register is onehot. + 2 1 read-only - L1_ICACHE2_AUTOLOAD_DONE - The bit is used to indicate whether autoload operation on L1-ICache2 is finished or not. 0: not finished. 1: finished. - 1 + L1_ICACHE_CACHESIZE_2K + The field is used to configure cachesize of L1-ICache as 2k bytes. This field and all other fields within this register is onehot. + 3 1 read-only - L1_ICACHE2_AUTOLOAD_ORDER - The bit is used to configure the direction of autoload operation on L1-ICache2. 0: ascending. 1: descending. - 2 + L1_ICACHE_CACHESIZE_4K + The field is used to configure cachesize of L1-ICache as 4k bytes. This field and all other fields within this register is onehot. + 4 1 read-only - L1_ICACHE2_AUTOLOAD_TRIGGER_MODE - The field is used to configure trigger mode of autoload operation on L1-ICache2. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. - 3 - 2 + L1_ICACHE_CACHESIZE_8K + The field is used to configure cachesize of L1-ICache as 8k bytes. This field and all other fields within this register is onehot. + 5 + 1 read-only - L1_ICACHE2_AUTOLOAD_SCT0_ENA - The bit is used to enable the first section for autoload operation on L1-ICache2. - 8 + L1_ICACHE_CACHESIZE_16K + The field is used to configure cachesize of L1-ICache as 16k bytes. This field and all other fields within this register is onehot. + 6 1 read-only - L1_ICACHE2_AUTOLOAD_SCT1_ENA - The bit is used to enable the second section for autoload operation on L1-ICache2. - 9 + L1_ICACHE_CACHESIZE_32K + The field is used to configure cachesize of L1-ICache as 32k bytes. This field and all other fields within this register is onehot. + 7 1 read-only - L1_ICACHE2_AUTOLOAD_RGID - The bit is used to set the gid of l1 icache2 autoload. - 10 - 4 + L1_ICACHE_CACHESIZE_64K + The field is used to configure cachesize of L1-ICache as 64k bytes. This field and all other fields within this register is onehot. + 8 + 1 read-only - - - - L1_ICACHE2_AUTOLOAD_SCT0_ADDR - L1 instruction Cache 2 autoload section 0 address configure register - 0x110 - 0x20 - - L1_ICACHE2_AUTOLOAD_SCT0_ADDR - Those bits are used to configure the start virtual address of the first section for autoload operation on L1-ICache2. Note that it should be used together with L1_ICACHE2_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. - 0 - 32 + L1_ICACHE_CACHESIZE_128K + The field is used to configure cachesize of L1-ICache as 128k bytes. This field and all other fields within this register is onehot. + 9 + 1 read-only - - - - L1_ICACHE2_AUTOLOAD_SCT0_SIZE - L1 instruction Cache 2 autoload section 0 size configure register - 0x114 - 0x20 - - L1_ICACHE2_AUTOLOAD_SCT0_SIZE - Those bits are used to configure the size of the first section for autoload operation on L1-ICache2. Note that it should be used together with L1_ICACHE2_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. - 0 - 28 + L1_ICACHE_CACHESIZE_256K + The field is used to configure cachesize of L1-ICache as 256k bytes. This field and all other fields within this register is onehot. + 10 + 1 read-only - - - - L1_ICACHE2_AUTOLOAD_SCT1_ADDR - L1 instruction Cache 2 autoload section 1 address configure register - 0x118 - 0x20 - - L1_ICACHE2_AUTOLOAD_SCT1_ADDR - Those bits are used to configure the start virtual address of the second section for autoload operation on L1-ICache2. Note that it should be used together with L1_ICACHE2_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. - 0 - 32 + L1_ICACHE_CACHESIZE_512K + The field is used to configure cachesize of L1-ICache as 512k bytes. This field and all other fields within this register is onehot. + 11 + 1 read-only - - - - L1_ICACHE2_AUTOLOAD_SCT1_SIZE - L1 instruction Cache 2 autoload section 1 size configure register - 0x11C - 0x20 - - L1_ICACHE2_AUTOLOAD_SCT1_SIZE - Those bits are used to configure the size of the second section for autoload operation on L1-ICache2. Note that it should be used together with L1_ICACHE2_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA. - 0 - 28 + L1_ICACHE_CACHESIZE_1024K + The field is used to configure cachesize of L1-ICache as 1024k bytes. This field and all other fields within this register is onehot. + 12 + 1 read-only - L1_ICACHE3_AUTOLOAD_CTRL - L1 instruction Cache 3 autoload-operation control register - 0x120 + L1_ICACHE_BLOCKSIZE_CONF + L1 instruction Cache BlockSize mode configure register + 0x14 0x20 - 0x00000002 + 0x00000008 - L1_ICACHE3_AUTOLOAD_ENA - The bit is used to enable and disable autoload operation on L1-ICache3. 1: enable, 0: disable. + L1_ICACHE_BLOCKSIZE_8 + The field is used to configureblocksize of L1-ICache as 8 bytes. This field and all other fields within this register is onehot. 0 1 read-only - L1_ICACHE3_AUTOLOAD_DONE - The bit is used to indicate whether autoload operation on L1-ICache3 is finished or not. 0: not finished. 1: finished. + L1_ICACHE_BLOCKSIZE_16 + The field is used to configureblocksize of L1-ICache as 16 bytes. This field and all other fields within this register is onehot. 1 1 read-only - L1_ICACHE3_AUTOLOAD_ORDER - The bit is used to configure the direction of autoload operation on L1-ICache3. 0: ascending. 1: descending. + L1_ICACHE_BLOCKSIZE_32 + The field is used to configureblocksize of L1-ICache as 32 bytes. This field and all other fields within this register is onehot. 2 1 read-only - L1_ICACHE3_AUTOLOAD_TRIGGER_MODE - The field is used to configure trigger mode of autoload operation on L1-ICache3. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + L1_ICACHE_BLOCKSIZE_64 + The field is used to configureblocksize of L1-ICache as 64 bytes. This field and all other fields within this register is onehot. 3 - 2 - read-only - - - L1_ICACHE3_AUTOLOAD_SCT0_ENA - The bit is used to enable the first section for autoload operation on L1-ICache3. - 8 1 read-only - L1_ICACHE3_AUTOLOAD_SCT1_ENA - The bit is used to enable the second section for autoload operation on L1-ICache3. - 9 + L1_ICACHE_BLOCKSIZE_128 + The field is used to configureblocksize of L1-ICache as 128 bytes. This field and all other fields within this register is onehot. + 4 1 read-only - L1_ICACHE3_AUTOLOAD_RGID - The bit is used to set the gid of l1 icache3 autoload. - 10 - 4 + L1_ICACHE_BLOCKSIZE_256 + The field is used to configureblocksize of L1-ICache as 256 bytes. This field and all other fields within this register is onehot. + 5 + 1 read-only - L1_ICACHE3_AUTOLOAD_SCT0_ADDR - L1 instruction Cache 3 autoload section 0 address configure register - 0x124 + L1_DCACHE_CACHESIZE_CONF + L1 data Cache CacheSize mode configure register + 0x18 0x20 + 0x00000100 - L1_ICACHE3_AUTOLOAD_SCT0_ADDR - Those bits are used to configure the start virtual address of the first section for autoload operation on L1-ICache3. Note that it should be used together with L1_ICACHE3_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. + L1_DCACHE_CACHESIZE_256 + The field is used to configure cachesize of L1-DCache as 256 bytes. This field and all other fields within this register is onehot. 0 - 32 + 1 read-only - - - - L1_ICACHE3_AUTOLOAD_SCT0_SIZE - L1 instruction Cache 3 autoload section 0 size configure register - 0x128 - 0x20 - - L1_ICACHE3_AUTOLOAD_SCT0_SIZE - Those bits are used to configure the size of the first section for autoload operation on L1-ICache3. Note that it should be used together with L1_ICACHE3_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. - 0 - 28 + L1_DCACHE_CACHESIZE_512 + The field is used to configure cachesize of L1-DCache as 512 bytes. This field and all other fields within this register is onehot. + 1 + 1 read-only - - - - L1_ICACHE3_AUTOLOAD_SCT1_ADDR - L1 instruction Cache 3 autoload section 1 address configure register - 0x12C - 0x20 - - L1_ICACHE3_AUTOLOAD_SCT1_ADDR - Those bits are used to configure the start virtual address of the second section for autoload operation on L1-ICache3. Note that it should be used together with L1_ICACHE3_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. - 0 - 32 + L1_DCACHE_CACHESIZE_1K + The field is used to configure cachesize of L1-DCache as 1k bytes. This field and all other fields within this register is onehot. + 2 + 1 read-only - - - - L1_ICACHE3_AUTOLOAD_SCT1_SIZE - L1 instruction Cache 3 autoload section 1 size configure register - 0x130 - 0x20 - - L1_ICACHE3_AUTOLOAD_SCT1_SIZE - Reserved - 0 - 28 + L1_DCACHE_CACHESIZE_2K + The field is used to configure cachesize of L1-DCache as 2k bytes. This field and all other fields within this register is onehot. + 3 + 1 read-only - - - - L1_DCACHE_AUTOLOAD_CTRL - L1 data Cache autoload-operation control register - 0x134 - 0x20 - 0x00000002 - - L1_DCACHE_AUTOLOAD_ENA - The bit is used to enable and disable autoload operation on L1-DCache. 1: enable, 0: disable. - 0 + L1_DCACHE_CACHESIZE_4K + The field is used to configure cachesize of L1-DCache as 4k bytes. This field and all other fields within this register is onehot. + 4 1 - read-write + read-only - L1_DCACHE_AUTOLOAD_DONE - The bit is used to indicate whether autoload operation on L1-DCache is finished or not. 0: not finished. 1: finished. - 1 + L1_DCACHE_CACHESIZE_8K + The field is used to configure cachesize of L1-DCache as 8k bytes. This field and all other fields within this register is onehot. + 5 1 read-only - L1_DCACHE_AUTOLOAD_ORDER - The bit is used to configure the direction of autoload operation on L1-DCache. 0: ascending. 1: descending. - 2 + L1_DCACHE_CACHESIZE_16K + The field is used to configure cachesize of L1-DCache as 16k bytes. This field and all other fields within this register is onehot. + 6 1 - read-write + read-only - L1_DCACHE_AUTOLOAD_TRIGGER_MODE - The field is used to configure trigger mode of autoload operation on L1-DCache. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. - 3 - 2 - read-write + L1_DCACHE_CACHESIZE_32K + The field is used to configure cachesize of L1-DCache as 32k bytes. This field and all other fields within this register is onehot. + 7 + 1 + read-only - L1_DCACHE_AUTOLOAD_SCT0_ENA - The bit is used to enable the first section for autoload operation on L1-DCache. + L1_DCACHE_CACHESIZE_64K + The field is used to configure cachesize of L1-DCache as 64k bytes. This field and all other fields within this register is onehot. 8 1 - read-write + read-only - L1_DCACHE_AUTOLOAD_SCT1_ENA - The bit is used to enable the second section for autoload operation on L1-DCache. + L1_DCACHE_CACHESIZE_128K + The field is used to configure cachesize of L1-DCache as 128k bytes. This field and all other fields within this register is onehot. 9 1 - read-write + read-only - L1_DCACHE_AUTOLOAD_SCT2_ENA - The bit is used to enable the third section for autoload operation on L1-DCache. + L1_DCACHE_CACHESIZE_256K + The field is used to configure cachesize of L1-DCache as 256k bytes. This field and all other fields within this register is onehot. 10 1 - read-write + read-only - L1_DCACHE_AUTOLOAD_SCT3_ENA - The bit is used to enable the fourth section for autoload operation on L1-DCache. + L1_DCACHE_CACHESIZE_512K + The field is used to configure cachesize of L1-DCache as 512k bytes. This field and all other fields within this register is onehot. 11 1 - read-write + read-only - L1_DCACHE_AUTOLOAD_RGID - The bit is used to set the gid of l1 dcache autoload. + L1_DCACHE_CACHESIZE_1024K + The field is used to configure cachesize of L1-DCache as 1024k bytes. This field and all other fields within this register is onehot. 12 - 4 - read-write + 1 + read-only - L1_DCACHE_AUTOLOAD_SCT0_ADDR - L1 data Cache autoload section 0 address configure register - 0x138 + L1_DCACHE_BLOCKSIZE_CONF + L1 data Cache BlockSize mode configure register + 0x1C 0x20 + 0x00000008 - L1_DCACHE_AUTOLOAD_SCT0_ADDR - Those bits are used to configure the start virtual address of the first section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT0_SIZE and L1_DCACHE_AUTOLOAD_SCT0_ENA. + L1_DCACHE_BLOCKSIZE_8 + The field is used to configureblocksize of L1-DCache as 8 bytes. This field and all other fields within this register is onehot. 0 - 32 - read-write + 1 + read-only - - - - L1_DCACHE_AUTOLOAD_SCT0_SIZE - L1 data Cache autoload section 0 size configure register - 0x13C - 0x20 - - L1_DCACHE_AUTOLOAD_SCT0_SIZE - Those bits are used to configure the size of the first section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT0_ADDR and L1_DCACHE_AUTOLOAD_SCT0_ENA. - 0 - 28 - read-write + L1_DCACHE_BLOCKSIZE_16 + The field is used to configureblocksize of L1-DCache as 16 bytes. This field and all other fields within this register is onehot. + 1 + 1 + read-only - - - - L1_DCACHE_AUTOLOAD_SCT1_ADDR - L1 data Cache autoload section 1 address configure register - 0x140 - 0x20 - - L1_DCACHE_AUTOLOAD_SCT1_ADDR - Those bits are used to configure the start virtual address of the second section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT1_SIZE and L1_DCACHE_AUTOLOAD_SCT1_ENA. - 0 - 32 - read-write + L1_DCACHE_BLOCKSIZE_32 + The field is used to configureblocksize of L1-DCache as 32 bytes. This field and all other fields within this register is onehot. + 2 + 1 + read-only - - - - L1_DCACHE_AUTOLOAD_SCT1_SIZE - L1 data Cache autoload section 1 size configure register - 0x144 - 0x20 - - L1_DCACHE_AUTOLOAD_SCT1_SIZE - Those bits are used to configure the size of the second section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT1_ADDR and L1_DCACHE_AUTOLOAD_SCT1_ENA. - 0 - 28 - read-write + L1_DCACHE_BLOCKSIZE_64 + The field is used to configureblocksize of L1-DCache as 64 bytes. This field and all other fields within this register is onehot. + 3 + 1 + read-only - - - - L1_DCACHE_AUTOLOAD_SCT2_ADDR - L1 data Cache autoload section 2 address configure register - 0x148 - 0x20 - - L1_DCACHE_AUTOLOAD_SCT2_ADDR - Those bits are used to configure the start virtual address of the third section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT2_SIZE and L1_DCACHE_AUTOLOAD_SCT2_ENA. - 0 - 32 - read-write + L1_DCACHE_BLOCKSIZE_128 + The field is used to configureblocksize of L1-DCache as 128 bytes. This field and all other fields within this register is onehot. + 4 + 1 + read-only + + + L1_DCACHE_BLOCKSIZE_256 + The field is used to configureblocksize of L1-DCache as 256 bytes. This field and all other fields within this register is onehot. + 5 + 1 + read-only - L1_DCACHE_AUTOLOAD_SCT2_SIZE - L1 data Cache autoload section 2 size configure register - 0x14C + L1_CACHE_WRAP_AROUND_CTRL + Cache wrap around control register + 0x20 0x20 - L1_DCACHE_AUTOLOAD_SCT2_SIZE - Those bits are used to configure the size of the third section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT2_ADDR and L1_DCACHE_AUTOLOAD_SCT2_ENA. + L1_ICACHE0_WRAP + Set this bit as 1 to enable L1-ICache0 wrap around mode. 0 - 28 + 1 read-write - - - - L1_DCACHE_AUTOLOAD_SCT3_ADDR - L1 data Cache autoload section 1 address configure register - 0x150 - 0x20 - - L1_DCACHE_AUTOLOAD_SCT3_ADDR - Those bits are used to configure the start virtual address of the fourth section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT3_SIZE and L1_DCACHE_AUTOLOAD_SCT3_ENA. - 0 - 32 + L1_ICACHE1_WRAP + Set this bit as 1 to enable L1-ICache1 wrap around mode. + 1 + 1 read-write - - - - L1_DCACHE_AUTOLOAD_SCT3_SIZE - L1 data Cache autoload section 1 size configure register - 0x154 - 0x20 - - L1_DCACHE_AUTOLOAD_SCT3_SIZE - Those bits are used to configure the size of the fourth section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT3_ADDR and L1_DCACHE_AUTOLOAD_SCT3_ENA. - 0 - 28 + L1_ICACHE2_WRAP + Reserved + 2 + 1 + read-only + + + L1_ICACHE3_WRAP + Reserved + 3 + 1 + read-only + + + L1_DCACHE_WRAP + Set this bit as 1 to enable L1-DCache wrap around mode. + 4 + 1 read-write - L1_CACHE_ACS_CNT_INT_ENA - Cache Access Counter Interrupt enable register - 0x158 + L1_CACHE_TAG_MEM_POWER_CTRL + Cache tag memory power control register + 0x24 0x20 + 0x00055555 - L1_IBUS0_OVF_INT_ENA - The bit is used to enable interrupt of one of counters overflow that occurs in L1-ICache0 due to bus0 accesses L1-ICache0. + L1_ICACHE0_TAG_MEM_FORCE_ON + The bit is used to close clock gating of L1-ICache0 tag memory. 1: close gating, 0: open clock gating. 0 1 read-write - L1_IBUS1_OVF_INT_ENA - The bit is used to enable interrupt of one of counters overflow that occurs in L1-ICache1 due to bus1 accesses L1-ICache1. + L1_ICACHE0_TAG_MEM_FORCE_PD + The bit is used to power L1-ICache0 tag memory down. 0: follow rtc_lslp, 1: power down 1 1 read-write - L1_IBUS2_OVF_INT_ENA - Reserved + L1_ICACHE0_TAG_MEM_FORCE_PU + The bit is used to power L1-ICache0 tag memory up. 0: follow rtc_lslp, 1: power up 2 1 - read-only - - - L1_IBUS3_OVF_INT_ENA - Reserved - 3 - 1 - read-only + read-write - L1_DBUS0_OVF_INT_ENA - The bit is used to enable interrupt of one of counters overflow that occurs in L1-DCache due to bus0 accesses L1-DCache. + L1_ICACHE1_TAG_MEM_FORCE_ON + The bit is used to close clock gating of L1-ICache1 tag memory. 1: close gating, 0: open clock gating. 4 1 read-write - L1_DBUS1_OVF_INT_ENA - The bit is used to enable interrupt of one of counters overflow that occurs in L1-DCache due to bus1 accesses L1-DCache. + L1_ICACHE1_TAG_MEM_FORCE_PD + The bit is used to power L1-ICache1 tag memory down. 0: follow rtc_lslp, 1: power down 5 1 read-write - L1_DBUS2_OVF_INT_ENA - Reserved + L1_ICACHE1_TAG_MEM_FORCE_PU + The bit is used to power L1-ICache1 tag memory up. 0: follow rtc_lslp, 1: power up 6 1 - read-only + read-write - L1_DBUS3_OVF_INT_ENA + L1_ICACHE2_TAG_MEM_FORCE_ON Reserved - 7 + 8 1 read-only - - - - L1_CACHE_ACS_CNT_INT_CLR - Cache Access Counter Interrupt clear register - 0x15C - 0x20 - - L1_IBUS0_OVF_INT_CLR - The bit is used to clear counters overflow interrupt and counters in L1-ICache0 due to bus0 accesses L1-ICache0. - 0 + L1_ICACHE2_TAG_MEM_FORCE_PD + Reserved + 9 1 - write-only + read-only - L1_IBUS1_OVF_INT_CLR - The bit is used to clear counters overflow interrupt and counters in L1-ICache1 due to bus1 accesses L1-ICache1. - 1 + L1_ICACHE2_TAG_MEM_FORCE_PU + Reserved + 10 1 - write-only + read-only - L1_IBUS2_OVF_INT_CLR + L1_ICACHE3_TAG_MEM_FORCE_ON Reserved - 2 + 12 1 read-only - L1_IBUS3_OVF_INT_CLR + L1_ICACHE3_TAG_MEM_FORCE_PD Reserved - 3 + 13 1 read-only - L1_DBUS0_OVF_INT_CLR - The bit is used to clear counters overflow interrupt and counters in L1-DCache due to bus0 accesses L1-DCache. - 4 + L1_ICACHE3_TAG_MEM_FORCE_PU + Reserved + 14 1 - write-only + read-only - L1_DBUS1_OVF_INT_CLR - The bit is used to clear counters overflow interrupt and counters in L1-DCache due to bus1 accesses L1-DCache. - 5 + L1_DCACHE_TAG_MEM_FORCE_ON + The bit is used to close clock gating of L1-DCache tag memory. 1: close gating, 0: open clock gating. + 16 1 - write-only + read-write - L1_DBUS2_OVF_INT_CLR - Reserved - 6 + L1_DCACHE_TAG_MEM_FORCE_PD + The bit is used to power L1-DCache tag memory down. 0: follow rtc_lslp, 1: power down + 17 1 - read-only + read-write - L1_DBUS3_OVF_INT_CLR - Reserved - 7 + L1_DCACHE_TAG_MEM_FORCE_PU + The bit is used to power L1-DCache tag memory up. 0: follow rtc_lslp, 1: power up + 18 1 - read-only + read-write - L1_CACHE_ACS_CNT_INT_RAW - Cache Access Counter Interrupt raw register - 0x160 + L1_CACHE_DATA_MEM_POWER_CTRL + Cache data memory power control register + 0x28 0x20 + 0x00055555 - L1_IBUS0_OVF_INT_RAW - The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache0 due to bus0 accesses L1-ICache0. + L1_ICACHE0_DATA_MEM_FORCE_ON + The bit is used to close clock gating of L1-ICache0 data memory. 1: close gating, 0: open clock gating. 0 1 read-write - L1_IBUS1_OVF_INT_RAW - The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache1 due to bus1 accesses L1-ICache1. + L1_ICACHE0_DATA_MEM_FORCE_PD + The bit is used to power L1-ICache0 data memory down. 0: follow rtc_lslp, 1: power down 1 1 read-write - L1_IBUS2_OVF_INT_RAW - The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache2 due to bus2 accesses L1-ICache2. + L1_ICACHE0_DATA_MEM_FORCE_PU + The bit is used to power L1-ICache0 data memory up. 0: follow rtc_lslp, 1: power up 2 1 read-write - L1_IBUS3_OVF_INT_RAW - The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache3 due to bus3 accesses L1-ICache3. - 3 - 1 - read-write - - - L1_DBUS0_OVF_INT_RAW - The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache due to bus0 accesses L1-DCache. + L1_ICACHE1_DATA_MEM_FORCE_ON + The bit is used to close clock gating of L1-ICache1 data memory. 1: close gating, 0: open clock gating. 4 1 read-write - L1_DBUS1_OVF_INT_RAW - The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache due to bus1 accesses L1-DCache. + L1_ICACHE1_DATA_MEM_FORCE_PD + The bit is used to power L1-ICache1 data memory down. 0: follow rtc_lslp, 1: power down 5 1 read-write - L1_DBUS2_OVF_INT_RAW - The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache due to bus2 accesses L1-DCache. + L1_ICACHE1_DATA_MEM_FORCE_PU + The bit is used to power L1-ICache1 data memory up. 0: follow rtc_lslp, 1: power up 6 1 read-write - L1_DBUS3_OVF_INT_RAW - The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache due to bus3 accesses L1-DCache. - 7 + L1_ICACHE2_DATA_MEM_FORCE_ON + Reserved + 8 1 - read-write + read-only - - - - L1_CACHE_ACS_CNT_INT_ST - Cache Access Counter Interrupt status register - 0x164 - 0x20 - - L1_IBUS0_OVF_INT_ST - The bit indicates the interrupt status of one of counters overflow that occurs in L1-ICache0 due to bus0 accesses L1-ICache0. - 0 + L1_ICACHE2_DATA_MEM_FORCE_PD + Reserved + 9 1 read-only - L1_IBUS1_OVF_INT_ST - The bit indicates the interrupt status of one of counters overflow that occurs in L1-ICache1 due to bus1 accesses L1-ICache1. - 1 + L1_ICACHE2_DATA_MEM_FORCE_PU + Reserved + 10 1 read-only - L1_IBUS2_OVF_INT_ST + L1_ICACHE3_DATA_MEM_FORCE_ON Reserved - 2 + 12 1 read-only - L1_IBUS3_OVF_INT_ST + L1_ICACHE3_DATA_MEM_FORCE_PD Reserved - 3 + 13 1 read-only - L1_DBUS0_OVF_INT_ST - The bit indicates the interrupt status of one of counters overflow that occurs in L1-DCache due to bus0 accesses L1-DCache. - 4 + L1_ICACHE3_DATA_MEM_FORCE_PU + Reserved + 14 1 read-only - L1_DBUS1_OVF_INT_ST - The bit indicates the interrupt status of one of counters overflow that occurs in L1-DCache due to bus1 accesses L1-DCache. - 5 + L1_DCACHE_DATA_MEM_FORCE_ON + The bit is used to close clock gating of L1-DCache data memory. 1: close gating, 0: open clock gating. + 16 1 - read-only + read-write - L1_DBUS2_OVF_INT_ST - Reserved - 6 + L1_DCACHE_DATA_MEM_FORCE_PD + The bit is used to power L1-DCache data memory down. 0: follow rtc_lslp, 1: power down + 17 1 - read-only + read-write - L1_DBUS3_OVF_INT_ST - Reserved - 7 + L1_DCACHE_DATA_MEM_FORCE_PU + The bit is used to power L1-DCache data memory up. 0: follow rtc_lslp, 1: power up + 18 1 - read-only + read-write - L1_CACHE_ACS_FAIL_CTRL - Cache Access Fail Configuration register - 0x168 + L1_CACHE_FREEZE_CTRL + Cache Freeze control register + 0x2C 0x20 - L1_ICACHE0_ACS_FAIL_CHECK_MODE - The bit is used to configure l1 icache0 access fail check mode. 0: the access fail is not propagated to the request, 1: the access fail is propagated to the request + L1_ICACHE0_FREEZE_EN + The bit is used to enable freeze operation on L1-ICache0. It can be cleared by software. 0 1 read-write - L1_ICACHE1_ACS_FAIL_CHECK_MODE - The bit is used to configure l1 icache1 access fail check mode. 0: the access fail is not propagated to the request, 1: the access fail is propagated to the request + L1_ICACHE0_FREEZE_MODE + The bit is used to configure mode of freeze operation L1-ICache0. 0: a miss-access will not stuck. 1: a miss-access will stuck. 1 1 read-write - L1_ICACHE2_ACS_FAIL_CHECK_MODE - The bit is used to configure l1 icache2 access fail check mode. 0: the access fail is not propagated to the request, 1: the access fail is propagated to the request + L1_ICACHE0_FREEZE_DONE + The bit is used to indicate whether freeze operation on L1-ICache0 is finished or not. 0: not finished. 1: finished. 2 1 - read-write - - - L1_ICACHE3_ACS_FAIL_CHECK_MODE - The bit is used to configure l1 icache3 access fail check mode. 0: the access fail is not propagated to the request, 1: the access fail is propagated to the request - 3 - 1 - read-write + read-only - L1_DCACHE_ACS_FAIL_CHECK_MODE - The bit is used to configure l1 dcache access fail check mode. 0: the access fail is not propagated to the request, 1: the access fail is propagated to the request + L1_ICACHE1_FREEZE_EN + The bit is used to enable freeze operation on L1-ICache1. It can be cleared by software. 4 1 read-write - - - - L1_CACHE_ACS_FAIL_INT_ENA - Cache Access Fail Interrupt enable register - 0x16C - 0x20 - - L1_ICACHE0_FAIL_INT_ENA - The bit is used to enable interrupt of access fail that occurs in L1-ICache0 due to cpu accesses L1-ICache0. - 0 + L1_ICACHE1_FREEZE_MODE + The bit is used to configure mode of freeze operation L1-ICache1. 0: a miss-access will not stuck. 1: a miss-access will stuck. + 5 1 read-write - L1_ICACHE1_FAIL_INT_ENA - The bit is used to enable interrupt of access fail that occurs in L1-ICache1 due to cpu accesses L1-ICache1. - 1 + L1_ICACHE1_FREEZE_DONE + The bit is used to indicate whether freeze operation on L1-ICache1 is finished or not. 0: not finished. 1: finished. + 6 1 - read-write + read-only - L1_ICACHE2_FAIL_INT_ENA + L1_ICACHE2_FREEZE_EN Reserved - 2 + 8 1 read-only - L1_ICACHE3_FAIL_INT_ENA + L1_ICACHE2_FREEZE_MODE Reserved - 3 + 9 1 read-only - L1_DCACHE_FAIL_INT_ENA - The bit is used to enable interrupt of access fail that occurs in L1-DCache due to cpu accesses L1-DCache. - 4 + L1_ICACHE2_FREEZE_DONE + Reserved + 10 1 - read-write + read-only - - - - L1_CACHE_ACS_FAIL_INT_CLR - L1-Cache Access Fail Interrupt clear register - 0x170 - 0x20 - - L1_ICACHE0_FAIL_INT_CLR - The bit is used to clear interrupt of access fail that occurs in L1-ICache0 due to cpu accesses L1-ICache0. - 0 + L1_ICACHE3_FREEZE_EN + Reserved + 12 1 - write-only + read-only - L1_ICACHE1_FAIL_INT_CLR - The bit is used to clear interrupt of access fail that occurs in L1-ICache1 due to cpu accesses L1-ICache1. - 1 + L1_ICACHE3_FREEZE_MODE + Reserved + 13 1 - write-only + read-only - L1_ICACHE2_FAIL_INT_CLR + L1_ICACHE3_FREEZE_DONE Reserved - 2 + 14 1 read-only - L1_ICACHE3_FAIL_INT_CLR - Reserved - 3 + L1_DCACHE_FREEZE_EN + The bit is used to enable freeze operation on L1-DCache. It can be cleared by software. + 16 1 - read-only + read-write - L1_DCACHE_FAIL_INT_CLR - The bit is used to clear interrupt of access fail that occurs in L1-DCache due to cpu accesses L1-DCache. - 4 + L1_DCACHE_FREEZE_MODE + The bit is used to configure mode of freeze operation L1-DCache. 0: a miss-access will not stuck. 1: a miss-access will stuck. + 17 1 - write-only + read-write + + + L1_DCACHE_FREEZE_DONE + The bit is used to indicate whether freeze operation on L1-DCache is finished or not. 0: not finished. 1: finished. + 18 + 1 + read-only - L1_CACHE_ACS_FAIL_INT_RAW - Cache Access Fail Interrupt raw register - 0x174 + L1_CACHE_DATA_MEM_ACS_CONF + Cache data memory access configure register + 0x30 0x20 + 0x00033333 - L1_ICACHE0_FAIL_INT_RAW - The raw bit of the interrupt of access fail that occurs in L1-ICache0. + L1_ICACHE0_DATA_MEM_RD_EN + The bit is used to enable config-bus read L1-ICache0 data memoryory. 0: disable, 1: enable. 0 1 read-write - L1_ICACHE1_FAIL_INT_RAW - The raw bit of the interrupt of access fail that occurs in L1-ICache1. + L1_ICACHE0_DATA_MEM_WR_EN + The bit is used to enable config-bus write L1-ICache0 data memoryory. 0: disable, 1: enable. 1 1 read-write - L1_ICACHE2_FAIL_INT_RAW - The raw bit of the interrupt of access fail that occurs in L1-ICache2. - 2 + L1_ICACHE1_DATA_MEM_RD_EN + The bit is used to enable config-bus read L1-ICache1 data memoryory. 0: disable, 1: enable. + 4 1 read-write - L1_ICACHE3_FAIL_INT_RAW - The raw bit of the interrupt of access fail that occurs in L1-ICache3. - 3 + L1_ICACHE1_DATA_MEM_WR_EN + The bit is used to enable config-bus write L1-ICache1 data memoryory. 0: disable, 1: enable. + 5 1 read-write - L1_DCACHE_FAIL_INT_RAW - The raw bit of the interrupt of access fail that occurs in L1-DCache. - 4 + L1_ICACHE2_DATA_MEM_RD_EN + Reserved + 8 1 - read-write + read-only - - - - L1_CACHE_ACS_FAIL_INT_ST - Cache Access Fail Interrupt status register - 0x178 - 0x20 - - L1_ICACHE0_FAIL_INT_ST - The bit indicates the interrupt status of access fail that occurs in L1-ICache0 due to cpu accesses L1-ICache. - 0 + L1_ICACHE2_DATA_MEM_WR_EN + Reserved + 9 1 read-only - L1_ICACHE1_FAIL_INT_ST - The bit indicates the interrupt status of access fail that occurs in L1-ICache1 due to cpu accesses L1-ICache. - 1 + L1_ICACHE3_DATA_MEM_RD_EN + Reserved + 12 1 read-only - L1_ICACHE2_FAIL_INT_ST + L1_ICACHE3_DATA_MEM_WR_EN Reserved - 2 + 13 1 read-only - L1_ICACHE3_FAIL_INT_ST - Reserved - 3 + L1_DCACHE_DATA_MEM_RD_EN + The bit is used to enable config-bus read L1-DCache data memoryory. 0: disable, 1: enable. + 16 1 - read-only + read-write - L1_DCACHE_FAIL_INT_ST - The bit indicates the interrupt status of access fail that occurs in L1-DCache due to cpu accesses L1-DCache. - 4 + L1_DCACHE_DATA_MEM_WR_EN + The bit is used to enable config-bus write L1-DCache data memoryory. 0: disable, 1: enable. + 17 1 - read-only + read-write - L1_CACHE_ACS_CNT_CTRL - Cache Access Counter enable and clear register - 0x17C + L1_CACHE_TAG_MEM_ACS_CONF + Cache tag memory access configure register + 0x34 0x20 + 0x00033333 - L1_IBUS0_CNT_ENA - The bit is used to enable ibus0 counter in L1-ICache0. + L1_ICACHE0_TAG_MEM_RD_EN + The bit is used to enable config-bus read L1-ICache0 tag memoryory. 0: disable, 1: enable. 0 1 read-write - L1_IBUS1_CNT_ENA - The bit is used to enable ibus1 counter in L1-ICache1. + L1_ICACHE0_TAG_MEM_WR_EN + The bit is used to enable config-bus write L1-ICache0 tag memoryory. 0: disable, 1: enable. 1 1 read-write - L1_IBUS2_CNT_ENA - Reserved - 2 - 1 - read-only - - - L1_IBUS3_CNT_ENA - Reserved - 3 - 1 - read-only - - - L1_DBUS0_CNT_ENA - The bit is used to enable dbus0 counter in L1-DCache. + L1_ICACHE1_TAG_MEM_RD_EN + The bit is used to enable config-bus read L1-ICache1 tag memoryory. 0: disable, 1: enable. 4 1 read-write - L1_DBUS1_CNT_ENA - The bit is used to enable dbus1 counter in L1-DCache. + L1_ICACHE1_TAG_MEM_WR_EN + The bit is used to enable config-bus write L1-ICache1 tag memoryory. 0: disable, 1: enable. 5 1 read-write - L1_DBUS2_CNT_ENA + L1_ICACHE2_TAG_MEM_RD_EN Reserved - 6 + 8 1 read-only - L1_DBUS3_CNT_ENA + L1_ICACHE2_TAG_MEM_WR_EN Reserved - 7 + 9 1 read-only - L1_IBUS0_CNT_CLR - The bit is used to clear ibus0 counter in L1-ICache0. - 16 - 1 - write-only - - - L1_IBUS1_CNT_CLR - The bit is used to clear ibus1 counter in L1-ICache1. - 17 - 1 - write-only - - - L1_IBUS2_CNT_CLR + L1_ICACHE3_TAG_MEM_RD_EN Reserved - 18 + 12 1 read-only - L1_IBUS3_CNT_CLR + L1_ICACHE3_TAG_MEM_WR_EN Reserved - 19 + 13 1 read-only - L1_DBUS0_CNT_CLR - The bit is used to clear dbus0 counter in L1-DCache. - 20 + L1_DCACHE_TAG_MEM_RD_EN + The bit is used to enable config-bus read L1-DCache tag memoryory. 0: disable, 1: enable. + 16 1 - write-only + read-write - L1_DBUS1_CNT_CLR - The bit is used to clear dbus1 counter in L1-DCache. - 21 + L1_DCACHE_TAG_MEM_WR_EN + The bit is used to enable config-bus write L1-DCache tag memoryory. 0: disable, 1: enable. + 17 1 - write-only + read-write + + + + L1_ICACHE0_PRELOCK_CONF + L1 instruction Cache 0 prelock configure register + 0x38 + 0x20 + - L1_DBUS2_CNT_CLR - Reserved - 22 + L1_ICACHE0_PRELOCK_SCT0_EN + The bit is used to enable the first section of prelock function on L1-ICache0. + 0 1 - read-only + read-write - L1_DBUS3_CNT_CLR - Reserved - 23 + L1_ICACHE0_PRELOCK_SCT1_EN + The bit is used to enable the second section of prelock function on L1-ICache0. + 1 1 - read-only + read-write + + + L1_ICACHE0_PRELOCK_RGID + The bit is used to set the gid of l1 icache0 prelock. + 2 + 4 + read-write - L1_IBUS0_ACS_HIT_CNT - L1-ICache bus0 Hit-Access Counter register - 0x180 + L1_ICACHE0_PRELOCK_SCT0_ADDR + L1 instruction Cache 0 prelock section0 address configure register + 0x3C 0x20 - L1_IBUS0_HIT_CNT - The register records the number of hits when bus0 accesses L1-ICache0. + L1_ICACHE0_PRELOCK_SCT0_ADDR + Those bits are used to configure the start virtual address of the first section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT0_SIZE_REG 0 32 - read-only + read-write - L1_IBUS0_ACS_MISS_CNT - L1-ICache bus0 Miss-Access Counter register - 0x184 + L1_ICACHE0_PRELOCK_SCT1_ADDR + L1 instruction Cache 0 prelock section1 address configure register + 0x40 0x20 - L1_IBUS0_MISS_CNT - The register records the number of missing when bus0 accesses L1-ICache0. + L1_ICACHE0_PRELOCK_SCT1_ADDR + Those bits are used to configure the start virtual address of the second section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT1_SIZE_REG 0 32 - read-only + read-write - L1_IBUS0_ACS_CONFLICT_CNT - L1-ICache bus0 Conflict-Access Counter register - 0x188 + L1_ICACHE0_PRELOCK_SCT_SIZE + L1 instruction Cache 0 prelock section size configure register + 0x44 0x20 + 0x3FFF3FFF - L1_IBUS0_CONFLICT_CNT - The register records the number of access-conflicts when bus0 accesses L1-ICache0. + L1_ICACHE0_PRELOCK_SCT0_SIZE + Those bits are used to configure the size of the first section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT0_ADDR_REG 0 - 32 - read-only + 14 + read-write + + + L1_ICACHE0_PRELOCK_SCT1_SIZE + Those bits are used to configure the size of the second section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT1_ADDR_REG + 16 + 14 + read-write - L1_IBUS0_ACS_NXTLVL_RD_CNT - L1-ICache bus0 Next-Level-Access Counter register - 0x18C + L1_ICACHE1_PRELOCK_CONF + L1 instruction Cache 1 prelock configure register + 0x48 0x20 - L1_IBUS0_NXTLVL_RD_CNT - The register records the number of times that L1-ICache accesses L2-Cache due to bus0 accessing L1-ICache0. + L1_ICACHE1_PRELOCK_SCT0_EN + The bit is used to enable the first section of prelock function on L1-ICache1. 0 - 32 - read-only + 1 + read-write + + + L1_ICACHE1_PRELOCK_SCT1_EN + The bit is used to enable the second section of prelock function on L1-ICache1. + 1 + 1 + read-write + + + L1_ICACHE1_PRELOCK_RGID + The bit is used to set the gid of l1 icache1 prelock. + 2 + 4 + read-write - L1_IBUS1_ACS_HIT_CNT - L1-ICache bus1 Hit-Access Counter register - 0x190 + L1_ICACHE1_PRELOCK_SCT0_ADDR + L1 instruction Cache 1 prelock section0 address configure register + 0x4C 0x20 - L1_IBUS1_HIT_CNT - The register records the number of hits when bus1 accesses L1-ICache1. + L1_ICACHE1_PRELOCK_SCT0_ADDR + Those bits are used to configure the start virtual address of the first section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT0_SIZE_REG 0 32 - read-only + read-write - L1_IBUS1_ACS_MISS_CNT - L1-ICache bus1 Miss-Access Counter register - 0x194 + L1_ICACHE1_PRELOCK_SCT1_ADDR + L1 instruction Cache 1 prelock section1 address configure register + 0x50 0x20 - L1_IBUS1_MISS_CNT - The register records the number of missing when bus1 accesses L1-ICache1. + L1_ICACHE1_PRELOCK_SCT1_ADDR + Those bits are used to configure the start virtual address of the second section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT1_SIZE_REG 0 32 - read-only + read-write - L1_IBUS1_ACS_CONFLICT_CNT - L1-ICache bus1 Conflict-Access Counter register - 0x198 + L1_ICACHE1_PRELOCK_SCT_SIZE + L1 instruction Cache 1 prelock section size configure register + 0x54 0x20 + 0x3FFF3FFF - L1_IBUS1_CONFLICT_CNT - The register records the number of access-conflicts when bus1 accesses L1-ICache1. + L1_ICACHE1_PRELOCK_SCT0_SIZE + Those bits are used to configure the size of the first section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT0_ADDR_REG 0 - 32 - read-only + 14 + read-write + + + L1_ICACHE1_PRELOCK_SCT1_SIZE + Those bits are used to configure the size of the second section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT1_ADDR_REG + 16 + 14 + read-write - L1_IBUS1_ACS_NXTLVL_RD_CNT - L1-ICache bus1 Next-Level-Access Counter register - 0x19C + L1_ICACHE2_PRELOCK_CONF + L1 instruction Cache 2 prelock configure register + 0x58 0x20 - L1_IBUS1_NXTLVL_RD_CNT - The register records the number of times that L1-ICache accesses L2-Cache due to bus1 accessing L1-ICache1. + L1_ICACHE2_PRELOCK_SCT0_EN + The bit is used to enable the first section of prelock function on L1-ICache2. 0 - 32 + 1 + read-only + + + L1_ICACHE2_PRELOCK_SCT1_EN + The bit is used to enable the second section of prelock function on L1-ICache2. + 1 + 1 + read-only + + + L1_ICACHE2_PRELOCK_RGID + The bit is used to set the gid of l1 icache2 prelock. + 2 + 4 read-only - L1_IBUS2_ACS_HIT_CNT - L1-ICache bus2 Hit-Access Counter register - 0x1A0 + L1_ICACHE2_PRELOCK_SCT0_ADDR + L1 instruction Cache 2 prelock section0 address configure register + 0x5C 0x20 - L1_IBUS2_HIT_CNT - The register records the number of hits when bus2 accesses L1-ICache2. + L1_ICACHE2_PRELOCK_SCT0_ADDR + Those bits are used to configure the start virtual address of the first section of prelock on L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT0_SIZE_REG 0 32 read-only @@ -9864,14 +9578,14 @@ - L1_IBUS2_ACS_MISS_CNT - L1-ICache bus2 Miss-Access Counter register - 0x1A4 + L1_ICACHE2_PRELOCK_SCT1_ADDR + L1 instruction Cache 2 prelock section1 address configure register + 0x60 0x20 - L1_IBUS2_MISS_CNT - The register records the number of missing when bus2 accesses L1-ICache2. + L1_ICACHE2_PRELOCK_SCT1_ADDR + Those bits are used to configure the start virtual address of the second section of prelock on L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT1_SIZE_REG 0 32 read-only @@ -9879,44 +9593,66 @@ - L1_IBUS2_ACS_CONFLICT_CNT - L1-ICache bus2 Conflict-Access Counter register - 0x1A8 + L1_ICACHE2_PRELOCK_SCT_SIZE + L1 instruction Cache 2 prelock section size configure register + 0x64 0x20 + 0x3FFF3FFF - L1_IBUS2_CONFLICT_CNT - The register records the number of access-conflicts when bus2 accesses L1-ICache2. + L1_ICACHE2_PRELOCK_SCT0_SIZE + Those bits are used to configure the size of the first section of prelock on L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT0_ADDR_REG 0 - 32 + 14 + read-only + + + L1_ICACHE2_PRELOCK_SCT1_SIZE + Those bits are used to configure the size of the second section of prelock on L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT1_ADDR_REG + 16 + 14 read-only - L1_IBUS2_ACS_NXTLVL_RD_CNT - L1-ICache bus2 Next-Level-Access Counter register - 0x1AC + L1_ICACHE3_PRELOCK_CONF + L1 instruction Cache 3 prelock configure register + 0x68 0x20 - L1_IBUS2_NXTLVL_RD_CNT - The register records the number of times that L1-ICache accesses L2-Cache due to bus2 accessing L1-ICache2. + L1_ICACHE3_PRELOCK_SCT0_EN + The bit is used to enable the first section of prelock function on L1-ICache3. 0 - 32 + 1 + read-only + + + L1_ICACHE3_PRELOCK_SCT1_EN + The bit is used to enable the second section of prelock function on L1-ICache3. + 1 + 1 + read-only + + + L1_ICACHE3_PRELOCK_RGID + The bit is used to set the gid of l1 icache3 prelock. + 2 + 4 read-only - L1_IBUS3_ACS_HIT_CNT - L1-ICache bus3 Hit-Access Counter register - 0x1B0 + L1_ICACHE3_PRELOCK_SCT0_ADDR + L1 instruction Cache 3 prelock section0 address configure register + 0x6C 0x20 - L1_IBUS3_HIT_CNT - The register records the number of hits when bus3 accesses L1-ICache3. + L1_ICACHE3_PRELOCK_SCT0_ADDR + Those bits are used to configure the start virtual address of the first section of prelock on L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT0_SIZE_REG 0 32 read-only @@ -9924,14 +9660,14 @@ - L1_IBUS3_ACS_MISS_CNT - L1-ICache bus3 Miss-Access Counter register - 0x1B4 + L1_ICACHE3_PRELOCK_SCT1_ADDR + L1 instruction Cache 3 prelock section1 address configure register + 0x70 0x20 - L1_IBUS3_MISS_CNT - The register records the number of missing when bus3 accesses L1-ICache3. + L1_ICACHE3_PRELOCK_SCT1_ADDR + Those bits are used to configure the start virtual address of the second section of prelock on L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT1_SIZE_REG 0 32 read-only @@ -9939,366 +9675,469 @@ - L1_IBUS3_ACS_CONFLICT_CNT - L1-ICache bus3 Conflict-Access Counter register - 0x1B8 + L1_ICACHE3_PRELOCK_SCT_SIZE + L1 instruction Cache 3 prelock section size configure register + 0x74 0x20 + 0x3FFF3FFF - L1_IBUS3_CONFLICT_CNT - The register records the number of access-conflicts when bus3 accesses L1-ICache3. + L1_ICACHE3_PRELOCK_SCT0_SIZE + Those bits are used to configure the size of the first section of prelock on L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT0_ADDR_REG 0 - 32 + 14 + read-only + + + L1_ICACHE3_PRELOCK_SCT1_SIZE + Those bits are used to configure the size of the second section of prelock on L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT1_ADDR_REG + 16 + 14 read-only - L1_IBUS3_ACS_NXTLVL_RD_CNT - L1-ICache bus3 Next-Level-Access Counter register - 0x1BC + L1_DCACHE_PRELOCK_CONF + L1 data Cache prelock configure register + 0x78 0x20 - L1_IBUS3_NXTLVL_RD_CNT - The register records the number of times that L1-ICache accesses L2-Cache due to bus3 accessing L1-ICache3. + L1_DCACHE_PRELOCK_SCT0_EN + The bit is used to enable the first section of prelock function on L1-DCache. 0 - 32 - read-only + 1 + read-write + + + L1_DCACHE_PRELOCK_SCT1_EN + The bit is used to enable the second section of prelock function on L1-DCache. + 1 + 1 + read-write + + + L1_DCACHE_PRELOCK_RGID + The bit is used to set the gid of l1 dcache prelock. + 2 + 4 + read-write - L1_DBUS0_ACS_HIT_CNT - L1-DCache bus0 Hit-Access Counter register - 0x1C0 + L1_DCACHE_PRELOCK_SCT0_ADDR + L1 data Cache prelock section0 address configure register + 0x7C 0x20 - L1_DBUS0_HIT_CNT - The register records the number of hits when bus0 accesses L1-DCache. + L1_DCACHE_PRELOCK_SCT0_ADDR + Those bits are used to configure the start virtual address of the first section of prelock on L1-DCache, which should be used together with L1_DCACHE_PRELOCK_SCT0_SIZE_REG 0 32 - read-only + read-write - L1_DBUS0_ACS_MISS_CNT - L1-DCache bus0 Miss-Access Counter register - 0x1C4 + L1_DCACHE_PRELOCK_SCT1_ADDR + L1 data Cache prelock section1 address configure register + 0x80 0x20 - L1_DBUS0_MISS_CNT - The register records the number of missing when bus0 accesses L1-DCache. + L1_DCACHE_PRELOCK_SCT1_ADDR + Those bits are used to configure the start virtual address of the second section of prelock on L1-DCache, which should be used together with L1_DCACHE_PRELOCK_SCT1_SIZE_REG 0 32 - read-only + read-write - L1_DBUS0_ACS_CONFLICT_CNT - L1-DCache bus0 Conflict-Access Counter register - 0x1C8 + L1_DCACHE_PRELOCK_SCT_SIZE + L1 data Cache prelock section size configure register + 0x84 0x20 + 0x3FFF3FFF - L1_DBUS0_CONFLICT_CNT - The register records the number of access-conflicts when bus0 accesses L1-DCache. + L1_DCACHE_PRELOCK_SCT0_SIZE + Those bits are used to configure the size of the first section of prelock on L1-DCache, which should be used together with L1_DCACHE_PRELOCK_SCT0_ADDR_REG 0 - 32 - read-only + 14 + read-write + + + L1_DCACHE_PRELOCK_SCT1_SIZE + Those bits are used to configure the size of the second section of prelock on L1-DCache, which should be used together with L1_DCACHE_PRELOCK_SCT1_ADDR_REG + 16 + 14 + read-write - L1_DBUS0_ACS_NXTLVL_RD_CNT - L1-DCache bus0 Next-Level-Access Counter register - 0x1CC + LOCK_CTRL + Lock-class (manual lock) operation control register + 0x88 0x20 + 0x00000004 - L1_DBUS0_NXTLVL_RD_CNT - The register records the number of times that L1-DCache accesses L2-Cache due to bus0 accessing L1-DCache. + LOCK_ENA + The bit is used to enable lock operation. It will be cleared by hardware after lock operation done. Note that (1) this bit and unlock_ena bit are mutually exclusive, that is, those bits can not be set to 1 at the same time. (2) lock operation can be applied on LL1-ICache, L1-DCache and L2-Cache. 0 - 32 + 1 + read-write + + + UNLOCK_ENA + The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done. Note that (1) this bit and lock_ena bit are mutually exclusive, that is, those bits can not be set to 1 at the same time. (2) unlock operation can be applied on L1-ICache, L1-DCache and L2-Cache. + 1 + 1 + read-write + + + LOCK_DONE + The bit is used to indicate whether unlock/lock operation is finished or not. 0: not finished. 1: finished. + 2 + 1 read-only + + LOCK_RGID + The bit is used to set the gid of cache lock/unlock. + 3 + 4 + read-write + - L1_DBUS0_ACS_NXTLVL_WR_CNT - L1-DCache bus0 WB-Access Counter register - 0x1D0 + LOCK_MAP + Lock (manual lock) map configure register + 0x8C 0x20 - L1_DBUS0_NXTLVL_WR_CNT - The register records the number of write back when bus0 accesses L1-DCache. + LOCK_MAP + Those bits are used to indicate which caches in the two-level cache structure will apply this lock/unlock operation. [0]: L1-ICache0, [1]: L1-ICache1, [2]: L1-ICache2, [3]: L1-ICache3, [4]: L1-DCache, [5]: L2-Cache. 0 - 32 - read-only + 6 + read-write - L1_DBUS1_ACS_HIT_CNT - L1-DCache bus1 Hit-Access Counter register - 0x1D4 + LOCK_ADDR + Lock (manual lock) address configure register + 0x90 0x20 - L1_DBUS1_HIT_CNT - The register records the number of hits when bus1 accesses L1-DCache. + LOCK_ADDR + Those bits are used to configure the start virtual address of the lock/unlock operation, which should be used together with CACHE_LOCK_SIZE_REG 0 32 - read-only + read-write - L1_DBUS1_ACS_MISS_CNT - L1-DCache bus1 Miss-Access Counter register - 0x1D8 + LOCK_SIZE + Lock (manual lock) size configure register + 0x94 0x20 - L1_DBUS1_MISS_CNT - The register records the number of missing when bus1 accesses L1-DCache. + LOCK_SIZE + Those bits are used to configure the size of the lock/unlock operation, which should be used together with CACHE_LOCK_ADDR_REG 0 - 32 - read-only + 16 + read-write - L1_DBUS1_ACS_CONFLICT_CNT - L1-DCache bus1 Conflict-Access Counter register - 0x1DC + SYNC_CTRL + Sync-class operation control register + 0x98 0x20 + 0x00000001 - L1_DBUS1_CONFLICT_CNT - The register records the number of access-conflicts when bus1 accesses L1-DCache. + INVALIDATE_ENA + The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done. Note that this bit and the other sync-bits (clean_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those bits can not be set to 1 at the same time. 0 - 32 + 1 + read-write + + + CLEAN_ENA + The bit is used to enable clean operation. It will be cleared by hardware after clean operation done. Note that this bit and the other sync-bits (invalidate_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those bits can not be set to 1 at the same time. + 1 + 1 + read-write + + + WRITEBACK_ENA + The bit is used to enable writeback operation. It will be cleared by hardware after writeback operation done. Note that this bit and the other sync-bits (invalidate_ena, clean_ena, writeback_invalidate_ena) are mutually exclusive, that is, those bits can not be set to 1 at the same time. + 2 + 1 + read-write + + + WRITEBACK_INVALIDATE_ENA + The bit is used to enable writeback-invalidate operation. It will be cleared by hardware after writeback-invalidate operation done. Note that this bit and the other sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive, that is, those bits can not be set to 1 at the same time. + 3 + 1 + read-write + + + SYNC_DONE + The bit is used to indicate whether sync operation (invalidate, clean, writeback, writeback_invalidate) is finished or not. 0: not finished. 1: finished. + 4 + 1 read-only + + SYNC_RGID + The bit is used to set the gid of cache sync operation (invalidate, clean, writeback, writeback_invalidate) + 5 + 4 + read-write + - L1_DBUS1_ACS_NXTLVL_RD_CNT - L1-DCache bus1 Next-Level-Access Counter register - 0x1E0 + SYNC_MAP + Sync map configure register + 0x9C 0x20 + 0x0000001F - L1_DBUS1_NXTLVL_RD_CNT - The register records the number of times that L1-DCache accesses L2-Cache due to bus1 accessing L1-DCache. + SYNC_MAP + Those bits are used to indicate which caches in the two-level cache structure will apply the sync operation. [0]: L1-ICache0, [1]: L1-ICache1, [2]: L1-ICache2, [3]: L1-ICache3, [4]: L1-DCache, [5]: L2-Cache. 0 - 32 - read-only + 6 + read-write - L1_DBUS1_ACS_NXTLVL_WR_CNT - L1-DCache bus1 WB-Access Counter register - 0x1E4 + SYNC_ADDR + Sync address configure register + 0xA0 0x20 - L1_DBUS1_NXTLVL_WR_CNT - The register records the number of write back when bus1 accesses L1-DCache. + SYNC_ADDR + Those bits are used to configure the start virtual address of the sync operation, which should be used together with CACHE_SYNC_SIZE_REG 0 32 - read-only + read-write - L1_DBUS2_ACS_HIT_CNT - L1-DCache bus2 Hit-Access Counter register - 0x1E8 + SYNC_SIZE + Sync size configure register + 0xA4 0x20 - L1_DBUS2_HIT_CNT - The register records the number of hits when bus2 accesses L1-DCache. + SYNC_SIZE + Those bits are used to configure the size of the sync operation, which should be used together with CACHE_SYNC_ADDR_REG 0 - 32 - read-only + 28 + read-write - L1_DBUS2_ACS_MISS_CNT - L1-DCache bus2 Miss-Access Counter register - 0x1EC + L1_ICACHE0_PRELOAD_CTRL + L1 instruction Cache 0 preload-operation control register + 0xA8 0x20 + 0x00000002 - L1_DBUS2_MISS_CNT - The register records the number of missing when bus2 accesses L1-DCache. + L1_ICACHE0_PRELOAD_ENA + The bit is used to enable preload operation on L1-ICache0. It will be cleared by hardware automatically after preload operation is done. 0 - 32 + 1 + read-write + + + L1_ICACHE0_PRELOAD_DONE + The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished. + 1 + 1 read-only + + L1_ICACHE0_PRELOAD_ORDER + The bit is used to configure the direction of preload operation. 0: ascending, 1: descending. + 2 + 1 + read-write + + + L1_ICACHE0_PRELOAD_RGID + The bit is used to set the gid of l1 icache0 preload. + 3 + 4 + read-write + - L1_DBUS2_ACS_CONFLICT_CNT - L1-DCache bus2 Conflict-Access Counter register - 0x1F0 + L1_ICACHE0_PRELOAD_ADDR + L1 instruction Cache 0 preload address configure register + 0xAC 0x20 - L1_DBUS2_CONFLICT_CNT - The register records the number of access-conflicts when bus2 accesses L1-DCache. + L1_ICACHE0_PRELOAD_ADDR + Those bits are used to configure the start virtual address of preload on L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_SIZE_REG 0 32 - read-only + read-write - L1_DBUS2_ACS_NXTLVL_RD_CNT - L1-DCache bus2 Next-Level-Access Counter register - 0x1F4 + L1_ICACHE0_PRELOAD_SIZE + L1 instruction Cache 0 preload size configure register + 0xB0 0x20 - L1_DBUS2_NXTLVL_RD_CNT - The register records the number of times that L1-DCache accesses L2-Cache due to bus2 accessing L1-DCache. + L1_ICACHE0_PRELOAD_SIZE + Those bits are used to configure the size of the first section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_ADDR_REG 0 - 32 - read-only + 14 + read-write - L1_DBUS2_ACS_NXTLVL_WR_CNT - L1-DCache bus2 WB-Access Counter register - 0x1F8 + L1_ICACHE1_PRELOAD_CTRL + L1 instruction Cache 1 preload-operation control register + 0xB4 0x20 + 0x00000002 - L1_DBUS2_NXTLVL_WR_CNT - The register records the number of write back when bus2 accesses L1-DCache. + L1_ICACHE1_PRELOAD_ENA + The bit is used to enable preload operation on L1-ICache1. It will be cleared by hardware automatically after preload operation is done. 0 - 32 - read-only + 1 + read-write - - - - L1_DBUS3_ACS_HIT_CNT - L1-DCache bus3 Hit-Access Counter register - 0x1FC - 0x20 - - L1_DBUS3_HIT_CNT - The register records the number of hits when bus3 accesses L1-DCache. - 0 - 32 + L1_ICACHE1_PRELOAD_DONE + The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished. + 1 + 1 read-only + + L1_ICACHE1_PRELOAD_ORDER + The bit is used to configure the direction of preload operation. 0: ascending, 1: descending. + 2 + 1 + read-write + + + L1_ICACHE1_PRELOAD_RGID + The bit is used to set the gid of l1 icache1 preload. + 3 + 4 + read-write + - L1_DBUS3_ACS_MISS_CNT - L1-DCache bus3 Miss-Access Counter register - 0x200 + L1_ICACHE1_PRELOAD_ADDR + L1 instruction Cache 1 preload address configure register + 0xB8 0x20 - L1_DBUS3_MISS_CNT - The register records the number of missing when bus3 accesses L1-DCache. + L1_ICACHE1_PRELOAD_ADDR + Those bits are used to configure the start virtual address of preload on L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_SIZE_REG 0 32 - read-only + read-write - L1_DBUS3_ACS_CONFLICT_CNT - L1-DCache bus3 Conflict-Access Counter register - 0x204 + L1_ICACHE1_PRELOAD_SIZE + L1 instruction Cache 1 preload size configure register + 0xBC 0x20 - L1_DBUS3_CONFLICT_CNT - The register records the number of access-conflicts when bus3 accesses L1-DCache. + L1_ICACHE1_PRELOAD_SIZE + Those bits are used to configure the size of the first section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_ADDR_REG 0 - 32 - read-only + 14 + read-write - L1_DBUS3_ACS_NXTLVL_RD_CNT - L1-DCache bus3 Next-Level-Access Counter register - 0x208 + L1_ICACHE2_PRELOAD_CTRL + L1 instruction Cache 2 preload-operation control register + 0xC0 0x20 + 0x00000002 - L1_DBUS3_NXTLVL_RD_CNT - The register records the number of times that L1-DCache accesses L2-Cache due to bus3 accessing L1-DCache. + L1_ICACHE2_PRELOAD_ENA + The bit is used to enable preload operation on L1-ICache2. It will be cleared by hardware automatically after preload operation is done. 0 - 32 + 1 read-only - - - - L1_DBUS3_ACS_NXTLVL_WR_CNT - L1-DCache bus3 WB-Access Counter register - 0x20C - 0x20 - - L1_DBUS3_NXTLVL_WR_CNT - The register records the number of write back when bus0 accesses L1-DCache. - 0 - 32 + L1_ICACHE2_PRELOAD_DONE + The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished. + 1 + 1 read-only - - - - L1_ICACHE0_ACS_FAIL_ID_ATTR - L1-ICache0 Access Fail ID/attribution information register - 0x210 - 0x20 - - L1_ICACHE0_FAIL_ID - The register records the ID of fail-access when cache0 accesses L1-ICache. - 0 - 16 + L1_ICACHE2_PRELOAD_ORDER + The bit is used to configure the direction of preload operation. 0: ascending, 1: descending. + 2 + 1 read-only - L1_ICACHE0_FAIL_ATTR - The register records the attribution of fail-access when cache0 accesses L1-ICache. - 16 - 16 + L1_ICACHE2_PRELOAD_RGID + The bit is used to set the gid of l1 icache2 preload. + 3 + 4 read-only - L1_ICACHE0_ACS_FAIL_ADDR - L1-ICache0 Access Fail Address information register - 0x214 + L1_ICACHE2_PRELOAD_ADDR + L1 instruction Cache 2 preload address configure register + 0xC4 0x20 - L1_ICACHE0_FAIL_ADDR - The register records the address of fail-access when cache0 accesses L1-ICache. + L1_ICACHE2_PRELOAD_ADDR + Those bits are used to configure the start virtual address of preload on L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_SIZE_REG 0 32 read-only @@ -10306,73 +10145,66 @@ - L1_ICACHE1_ACS_FAIL_ID_ATTR - L1-ICache0 Access Fail ID/attribution information register - 0x218 + L1_ICACHE2_PRELOAD_SIZE + L1 instruction Cache 2 preload size configure register + 0xC8 0x20 - L1_ICACHE1_FAIL_ID - The register records the ID of fail-access when cache1 accesses L1-ICache. + L1_ICACHE2_PRELOAD_SIZE + Those bits are used to configure the size of the first section of prelock on L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_ADDR_REG 0 - 16 - read-only - - - L1_ICACHE1_FAIL_ATTR - The register records the attribution of fail-access when cache1 accesses L1-ICache. - 16 - 16 + 14 read-only - L1_ICACHE1_ACS_FAIL_ADDR - L1-ICache0 Access Fail Address information register - 0x21C + L1_ICACHE3_PRELOAD_CTRL + L1 instruction Cache 3 preload-operation control register + 0xCC 0x20 + 0x00000002 - L1_ICACHE1_FAIL_ADDR - The register records the address of fail-access when cache1 accesses L1-ICache. + L1_ICACHE3_PRELOAD_ENA + The bit is used to enable preload operation on L1-ICache3. It will be cleared by hardware automatically after preload operation is done. 0 - 32 + 1 read-only - - - - L1_ICACHE2_ACS_FAIL_ID_ATTR - L1-ICache0 Access Fail ID/attribution information register - 0x220 - 0x20 - - L1_ICACHE2_FAIL_ID - The register records the ID of fail-access when cache2 accesses L1-ICache. - 0 - 16 + L1_ICACHE3_PRELOAD_DONE + The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished. + 1 + 1 read-only - L1_ICACHE2_FAIL_ATTR - The register records the attribution of fail-access when cache2 accesses L1-ICache. - 16 - 16 + L1_ICACHE3_PRELOAD_ORDER + The bit is used to configure the direction of preload operation. 0: ascending, 1: descending. + 2 + 1 + read-only + + + L1_ICACHE3_PRELOAD_RGID + The bit is used to set the gid of l1 icache3 preload. + 3 + 4 read-only - L1_ICACHE2_ACS_FAIL_ADDR - L1-ICache0 Access Fail Address information register - 0x224 + L1_ICACHE3_PRELOAD_ADDR + L1 instruction Cache 3 preload address configure register + 0xD0 0x20 - L1_ICACHE2_FAIL_ADDR - The register records the address of fail-access when cache2 accesses L1-ICache. + L1_ICACHE3_PRELOAD_ADDR + Those bits are used to configure the start virtual address of preload on L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_SIZE_REG 0 32 read-only @@ -10380,788 +10212,670 @@ - L1_ICACHE3_ACS_FAIL_ID_ATTR - L1-ICache0 Access Fail ID/attribution information register - 0x228 + L1_ICACHE3_PRELOAD_SIZE + L1 instruction Cache 3 preload size configure register + 0xD4 0x20 - L1_ICACHE3_FAIL_ID - The register records the ID of fail-access when cache3 accesses L1-ICache. + L1_ICACHE3_PRELOAD_SIZE + Those bits are used to configure the size of the first section of prelock on L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_ADDR_REG 0 - 16 - read-only - - - L1_ICACHE3_FAIL_ATTR - The register records the attribution of fail-access when cache3 accesses L1-ICache. - 16 - 16 + 14 read-only - L1_ICACHE3_ACS_FAIL_ADDR - L1-ICache0 Access Fail Address information register - 0x22C + L1_DCACHE_PRELOAD_CTRL + L1 data Cache preload-operation control register + 0xD8 0x20 + 0x00000002 - L1_ICACHE3_FAIL_ADDR - The register records the address of fail-access when cache3 accesses L1-ICache. + L1_DCACHE_PRELOAD_ENA + The bit is used to enable preload operation on L1-DCache. It will be cleared by hardware automatically after preload operation is done. 0 - 32 + 1 + read-write + + + L1_DCACHE_PRELOAD_DONE + The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished. + 1 + 1 read-only + + L1_DCACHE_PRELOAD_ORDER + The bit is used to configure the direction of preload operation. 0: ascending, 1: descending. + 2 + 1 + read-write + + + L1_DCACHE_PRELOAD_RGID + The bit is used to set the gid of l1 dcache preload. + 3 + 4 + read-write + - L1_DCACHE_ACS_FAIL_ID_ATTR - L1-DCache Access Fail ID/attribution information register - 0x230 + L1_DCACHE_PRELOAD_ADDR + L1 data Cache preload address configure register + 0xDC 0x20 - L1_DCACHE_FAIL_ID - The register records the ID of fail-access when cache accesses L1-DCache. + L1_DCACHE_PRELOAD_ADDR + Those bits are used to configure the start virtual address of preload on L1-DCache, which should be used together with L1_DCACHE_PRELOAD_SIZE_REG 0 - 16 - read-only - - - L1_DCACHE_FAIL_ATTR - The register records the attribution of fail-access when cache accesses L1-DCache. - 16 - 16 - read-only + 32 + read-write - L1_DCACHE_ACS_FAIL_ADDR - L1-DCache Access Fail Address information register - 0x234 + L1_DCACHE_PRELOAD_SIZE + L1 data Cache preload size configure register + 0xE0 0x20 - L1_DCACHE_FAIL_ADDR - The register records the address of fail-access when cache accesses L1-DCache. + L1_DCACHE_PRELOAD_SIZE + Those bits are used to configure the size of the first section of prelock on L1-DCache, which should be used together with L1_DCACHE_PRELOAD_ADDR_REG 0 - 32 - read-only + 14 + read-write - SYNC_L1_CACHE_PRELOAD_INT_ENA - L1-Cache Access Fail Interrupt enable register - 0x238 + L1_ICACHE0_AUTOLOAD_CTRL + L1 instruction Cache 0 autoload-operation control register + 0xE4 0x20 + 0x00000002 - L1_ICACHE0_PLD_DONE_INT_ENA - The bit is used to enable interrupt of L1-ICache0 preload-operation. If preload operation is done, interrupt occurs. + L1_ICACHE0_AUTOLOAD_ENA + The bit is used to enable and disable autoload operation on L1-ICache0. 1: enable, 0: disable. 0 1 read-write - L1_ICACHE1_PLD_DONE_INT_ENA - The bit is used to enable interrupt of L1-ICache1 preload-operation. If preload operation is done, interrupt occurs. + L1_ICACHE0_AUTOLOAD_DONE + The bit is used to indicate whether autoload operation on L1-ICache0 is finished or not. 0: not finished. 1: finished. 1 1 - read-write - - - L1_ICACHE2_PLD_DONE_INT_ENA - Reserved - 2 - 1 - read-only - - - L1_ICACHE3_PLD_DONE_INT_ENA - Reserved - 3 - 1 read-only - L1_DCACHE_PLD_DONE_INT_ENA - The bit is used to enable interrupt of L1-DCache preload-operation. If preload operation is done, interrupt occurs. - 4 - 1 - read-write - - - SYNC_DONE_INT_ENA - The bit is used to enable interrupt of Cache sync-operation done. - 6 + L1_ICACHE0_AUTOLOAD_ORDER + The bit is used to configure the direction of autoload operation on L1-ICache0. 0: ascending. 1: descending. + 2 1 read-write - L1_ICACHE0_PLD_ERR_INT_ENA - The bit is used to enable interrupt of L1-ICache0 preload-operation error. - 7 - 1 + L1_ICACHE0_AUTOLOAD_TRIGGER_MODE + The field is used to configure trigger mode of autoload operation on L1-ICache0. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + 3 + 2 read-write - L1_ICACHE1_PLD_ERR_INT_ENA - The bit is used to enable interrupt of L1-ICache1 preload-operation error. + L1_ICACHE0_AUTOLOAD_SCT0_ENA + The bit is used to enable the first section for autoload operation on L1-ICache0. 8 1 read-write - L1_ICACHE2_PLD_ERR_INT_ENA - Reserved + L1_ICACHE0_AUTOLOAD_SCT1_ENA + The bit is used to enable the second section for autoload operation on L1-ICache0. 9 1 - read-only + read-write - L1_ICACHE3_PLD_ERR_INT_ENA - Reserved + L1_ICACHE0_AUTOLOAD_RGID + The bit is used to set the gid of l1 icache0 autoload. 10 - 1 - read-only - - - L1_DCACHE_PLD_ERR_INT_ENA - The bit is used to enable interrupt of L1-DCache preload-operation error. - 11 - 1 + 4 read-write + + + + L1_ICACHE0_AUTOLOAD_SCT0_ADDR + L1 instruction Cache 0 autoload section 0 address configure register + 0xE8 + 0x20 + - SYNC_ERR_INT_ENA - The bit is used to enable interrupt of Cache sync-operation error. - 13 - 1 + L1_ICACHE0_AUTOLOAD_SCT0_ADDR + Those bits are used to configure the start virtual address of the first section for autoload operation on L1-ICache0. Note that it should be used together with L1_ICACHE0_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. + 0 + 32 read-write - SYNC_L1_CACHE_PRELOAD_INT_CLR - Sync Preload operation Interrupt clear register - 0x23C + L1_ICACHE0_AUTOLOAD_SCT0_SIZE + L1 instruction Cache 0 autoload section 0 size configure register + 0xEC 0x20 - L1_ICACHE0_PLD_DONE_INT_CLR - The bit is used to clear interrupt that occurs only when L1-ICache0 preload-operation is done. + L1_ICACHE0_AUTOLOAD_SCT0_SIZE + Those bits are used to configure the size of the first section for autoload operation on L1-ICache0. Note that it should be used together with L1_ICACHE0_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. 0 - 1 - write-only - - - L1_ICACHE1_PLD_DONE_INT_CLR - The bit is used to clear interrupt that occurs only when L1-ICache1 preload-operation is done. - 1 - 1 - write-only - - - L1_ICACHE2_PLD_DONE_INT_CLR - Reserved - 2 - 1 - read-only - - - L1_ICACHE3_PLD_DONE_INT_CLR - Reserved - 3 - 1 - read-only - - - L1_DCACHE_PLD_DONE_INT_CLR - The bit is used to clear interrupt that occurs only when L1-DCache preload-operation is done. - 4 - 1 - write-only - - - SYNC_DONE_INT_CLR - The bit is used to clear interrupt that occurs only when Cache sync-operation is done. - 6 - 1 - write-only - - - L1_ICACHE0_PLD_ERR_INT_CLR - The bit is used to clear interrupt of L1-ICache0 preload-operation error. - 7 - 1 - write-only - - - L1_ICACHE1_PLD_ERR_INT_CLR - The bit is used to clear interrupt of L1-ICache1 preload-operation error. - 8 - 1 - write-only - - - L1_ICACHE2_PLD_ERR_INT_CLR - Reserved - 9 - 1 - read-only - - - L1_ICACHE3_PLD_ERR_INT_CLR - Reserved - 10 - 1 - read-only + 28 + read-write + + + + L1_ICACHE0_AUTOLOAD_SCT1_ADDR + L1 instruction Cache 0 autoload section 1 address configure register + 0xF0 + 0x20 + - L1_DCACHE_PLD_ERR_INT_CLR - The bit is used to clear interrupt of L1-DCache preload-operation error. - 11 - 1 - write-only + L1_ICACHE0_AUTOLOAD_SCT1_ADDR + Those bits are used to configure the start virtual address of the second section for autoload operation on L1-ICache0. Note that it should be used together with L1_ICACHE0_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. + 0 + 32 + read-write + + + + L1_ICACHE0_AUTOLOAD_SCT1_SIZE + L1 instruction Cache 0 autoload section 1 size configure register + 0xF4 + 0x20 + - SYNC_ERR_INT_CLR - The bit is used to clear interrupt of Cache sync-operation error. - 13 - 1 - write-only + L1_ICACHE0_AUTOLOAD_SCT1_SIZE + Those bits are used to configure the size of the second section for autoload operation on L1-ICache0. Note that it should be used together with L1_ICACHE0_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA. + 0 + 28 + read-write - SYNC_L1_CACHE_PRELOAD_INT_RAW - Sync Preload operation Interrupt raw register - 0x240 + L1_ICACHE1_AUTOLOAD_CTRL + L1 instruction Cache 1 autoload-operation control register + 0xF8 0x20 + 0x00000002 - L1_ICACHE0_PLD_DONE_INT_RAW - The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation is done. + L1_ICACHE1_AUTOLOAD_ENA + The bit is used to enable and disable autoload operation on L1-ICache1. 1: enable, 0: disable. 0 1 read-write - L1_ICACHE1_PLD_DONE_INT_RAW - The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation is done. + L1_ICACHE1_AUTOLOAD_DONE + The bit is used to indicate whether autoload operation on L1-ICache1 is finished or not. 0: not finished. 1: finished. 1 1 - read-write + read-only - L1_ICACHE2_PLD_DONE_INT_RAW - Reserved + L1_ICACHE1_AUTOLOAD_ORDER + The bit is used to configure the direction of autoload operation on L1-ICache1. 0: ascending. 1: descending. 2 1 read-write - L1_ICACHE3_PLD_DONE_INT_RAW - Reserved + L1_ICACHE1_AUTOLOAD_TRIGGER_MODE + The field is used to configure trigger mode of autoload operation on L1-ICache1. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. 3 - 1 - read-write - - - L1_DCACHE_PLD_DONE_INT_RAW - The raw bit of the interrupt that occurs only when L1-DCache preload-operation is done. - 4 - 1 + 2 read-write - SYNC_DONE_INT_RAW - The raw bit of the interrupt that occurs only when Cache sync-operation is done. - 6 + L1_ICACHE1_AUTOLOAD_SCT0_ENA + The bit is used to enable the first section for autoload operation on L1-ICache1. + 8 1 read-write - L1_ICACHE0_PLD_ERR_INT_RAW - The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation error occurs. - 7 + L1_ICACHE1_AUTOLOAD_SCT1_ENA + The bit is used to enable the second section for autoload operation on L1-ICache1. + 9 1 read-write - L1_ICACHE1_PLD_ERR_INT_RAW - The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation error occurs. - 8 - 1 + L1_ICACHE1_AUTOLOAD_RGID + The bit is used to set the gid of l1 icache1 autoload. + 10 + 4 read-write + + + + L1_ICACHE1_AUTOLOAD_SCT0_ADDR + L1 instruction Cache 1 autoload section 0 address configure register + 0xFC + 0x20 + - L1_ICACHE2_PLD_ERR_INT_RAW - Reserved - 9 - 1 + L1_ICACHE1_AUTOLOAD_SCT0_ADDR + Those bits are used to configure the start virtual address of the first section for autoload operation on L1-ICache1. Note that it should be used together with L1_ICACHE1_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. + 0 + 32 read-write + + + + L1_ICACHE1_AUTOLOAD_SCT0_SIZE + L1 instruction Cache 1 autoload section 0 size configure register + 0x100 + 0x20 + - L1_ICACHE3_PLD_ERR_INT_RAW - Reserved - 10 - 1 + L1_ICACHE1_AUTOLOAD_SCT0_SIZE + Those bits are used to configure the size of the first section for autoload operation on L1-ICache1. Note that it should be used together with L1_ICACHE1_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. + 0 + 28 read-write + + + + L1_ICACHE1_AUTOLOAD_SCT1_ADDR + L1 instruction Cache 1 autoload section 1 address configure register + 0x104 + 0x20 + - L1_DCACHE_PLD_ERR_INT_RAW - The raw bit of the interrupt that occurs only when L1-DCache preload-operation error occurs. - 11 - 1 + L1_ICACHE1_AUTOLOAD_SCT1_ADDR + Those bits are used to configure the start virtual address of the second section for autoload operation on L1-ICache1. Note that it should be used together with L1_ICACHE1_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. + 0 + 32 read-write + + + + L1_ICACHE1_AUTOLOAD_SCT1_SIZE + L1 instruction Cache 1 autoload section 1 size configure register + 0x108 + 0x20 + - SYNC_ERR_INT_RAW - The raw bit of the interrupt that occurs only when Cache sync-operation error occurs. - 13 - 1 + L1_ICACHE1_AUTOLOAD_SCT1_SIZE + Those bits are used to configure the size of the second section for autoload operation on L1-ICache1. Note that it should be used together with L1_ICACHE1_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA. + 0 + 28 read-write - SYNC_L1_CACHE_PRELOAD_INT_ST - L1-Cache Access Fail Interrupt status register - 0x244 + L1_ICACHE2_AUTOLOAD_CTRL + L1 instruction Cache 2 autoload-operation control register + 0x10C 0x20 + 0x00000002 - L1_ICACHE0_PLD_DONE_INT_ST - The bit indicates the status of the interrupt that occurs only when L1-ICache0 preload-operation is done. + L1_ICACHE2_AUTOLOAD_ENA + The bit is used to enable and disable autoload operation on L1-ICache2. 1: enable, 0: disable. 0 1 read-only - L1_ICACHE1_PLD_DONE_INT_ST - The bit indicates the status of the interrupt that occurs only when L1-ICache1 preload-operation is done. + L1_ICACHE2_AUTOLOAD_DONE + The bit is used to indicate whether autoload operation on L1-ICache2 is finished or not. 0: not finished. 1: finished. 1 1 read-only - L1_ICACHE2_PLD_DONE_INT_ST - Reserved + L1_ICACHE2_AUTOLOAD_ORDER + The bit is used to configure the direction of autoload operation on L1-ICache2. 0: ascending. 1: descending. 2 1 read-only - L1_ICACHE3_PLD_DONE_INT_ST - Reserved + L1_ICACHE2_AUTOLOAD_TRIGGER_MODE + The field is used to configure trigger mode of autoload operation on L1-ICache2. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. 3 - 1 - read-only - - - L1_DCACHE_PLD_DONE_INT_ST - The bit indicates the status of the interrupt that occurs only when L1-DCache preload-operation is done. - 4 - 1 - read-only - - - SYNC_DONE_INT_ST - The bit indicates the status of the interrupt that occurs only when Cache sync-operation is done. - 6 - 1 - read-only - - - L1_ICACHE0_PLD_ERR_INT_ST - The bit indicates the status of the interrupt of L1-ICache0 preload-operation error. - 7 - 1 + 2 read-only - L1_ICACHE1_PLD_ERR_INT_ST - The bit indicates the status of the interrupt of L1-ICache1 preload-operation error. + L1_ICACHE2_AUTOLOAD_SCT0_ENA + The bit is used to enable the first section for autoload operation on L1-ICache2. 8 1 read-only - L1_ICACHE2_PLD_ERR_INT_ST - Reserved + L1_ICACHE2_AUTOLOAD_SCT1_ENA + The bit is used to enable the second section for autoload operation on L1-ICache2. 9 1 read-only - L1_ICACHE3_PLD_ERR_INT_ST - Reserved + L1_ICACHE2_AUTOLOAD_RGID + The bit is used to set the gid of l1 icache2 autoload. 10 - 1 - read-only - - - L1_DCACHE_PLD_ERR_INT_ST - The bit indicates the status of the interrupt of L1-DCache preload-operation error. - 11 - 1 - read-only - - - SYNC_ERR_INT_ST - The bit indicates the status of the interrupt of Cache sync-operation error. - 13 - 1 + 4 read-only - SYNC_L1_CACHE_PRELOAD_EXCEPTION - Cache Sync/Preload Operation exception register - 0x248 + L1_ICACHE2_AUTOLOAD_SCT0_ADDR + L1 instruction Cache 2 autoload section 0 address configure register + 0x110 0x20 - L1_ICACHE0_PLD_ERR_CODE - The value 2 is Only available which means preload size is error in L1-ICache0. + L1_ICACHE2_AUTOLOAD_SCT0_ADDR + Those bits are used to configure the start virtual address of the first section for autoload operation on L1-ICache2. Note that it should be used together with L1_ICACHE2_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. 0 - 2 - read-only - - - L1_ICACHE1_PLD_ERR_CODE - The value 2 is Only available which means preload size is error in L1-ICache1. - 2 - 2 - read-only - - - L1_ICACHE2_PLD_ERR_CODE - Reserved - 4 - 2 - read-only - - - L1_ICACHE3_PLD_ERR_CODE - Reserved - 6 - 2 - read-only - - - L1_DCACHE_PLD_ERR_CODE - The value 2 is Only available which means preload size is error in L1-DCache. - 8 - 2 + 32 read-only + + + + L1_ICACHE2_AUTOLOAD_SCT0_SIZE + L1 instruction Cache 2 autoload section 0 size configure register + 0x114 + 0x20 + - SYNC_ERR_CODE - The values 0-2 are available which means sync map, command conflict and size are error in Cache System. - 12 - 2 + L1_ICACHE2_AUTOLOAD_SCT0_SIZE + Those bits are used to configure the size of the first section for autoload operation on L1-ICache2. Note that it should be used together with L1_ICACHE2_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. + 0 + 28 read-only - L1_CACHE_SYNC_RST_CTRL - Cache Sync Reset control register - 0x24C + L1_ICACHE2_AUTOLOAD_SCT1_ADDR + L1 instruction Cache 2 autoload section 1 address configure register + 0x118 0x20 - L1_ICACHE0_SYNC_RST - set this bit to reset sync-logic inside L1-ICache0. Recommend that this should only be used to initialize sync-logic when some fatal error of sync-logic occurs. + L1_ICACHE2_AUTOLOAD_SCT1_ADDR + Those bits are used to configure the start virtual address of the second section for autoload operation on L1-ICache2. Note that it should be used together with L1_ICACHE2_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. 0 - 1 - read-write - - - L1_ICACHE1_SYNC_RST - set this bit to reset sync-logic inside L1-ICache1. Recommend that this should only be used to initialize sync-logic when some fatal error of sync-logic occurs. - 1 - 1 - read-write - - - L1_ICACHE2_SYNC_RST - Reserved - 2 - 1 + 32 read-only + + + + L1_ICACHE2_AUTOLOAD_SCT1_SIZE + L1 instruction Cache 2 autoload section 1 size configure register + 0x11C + 0x20 + - L1_ICACHE3_SYNC_RST - Reserved - 3 - 1 + L1_ICACHE2_AUTOLOAD_SCT1_SIZE + Those bits are used to configure the size of the second section for autoload operation on L1-ICache2. Note that it should be used together with L1_ICACHE2_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA. + 0 + 28 read-only - - L1_DCACHE_SYNC_RST - set this bit to reset sync-logic inside L1-DCache. Recommend that this should only be used to initialize sync-logic when some fatal error of sync-logic occurs. - 4 - 1 - read-write - - L1_CACHE_PRELOAD_RST_CTRL - Cache Preload Reset control register - 0x250 + L1_ICACHE3_AUTOLOAD_CTRL + L1 instruction Cache 3 autoload-operation control register + 0x120 0x20 + 0x00000002 - L1_ICACHE0_PLD_RST - set this bit to reset preload-logic inside L1-ICache0. Recommend that this should only be used to initialize preload-logic when some fatal error of preload-logic occurs. + L1_ICACHE3_AUTOLOAD_ENA + The bit is used to enable and disable autoload operation on L1-ICache3. 1: enable, 0: disable. 0 1 - read-write + read-only - L1_ICACHE1_PLD_RST - set this bit to reset preload-logic inside L1-ICache1. Recommend that this should only be used to initialize preload-logic when some fatal error of preload-logic occurs. + L1_ICACHE3_AUTOLOAD_DONE + The bit is used to indicate whether autoload operation on L1-ICache3 is finished or not. 0: not finished. 1: finished. 1 1 - read-write + read-only - L1_ICACHE2_PLD_RST - Reserved + L1_ICACHE3_AUTOLOAD_ORDER + The bit is used to configure the direction of autoload operation on L1-ICache3. 0: ascending. 1: descending. 2 1 read-only - L1_ICACHE3_PLD_RST - Reserved + L1_ICACHE3_AUTOLOAD_TRIGGER_MODE + The field is used to configure trigger mode of autoload operation on L1-ICache3. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. 3 + 2 + read-only + + + L1_ICACHE3_AUTOLOAD_SCT0_ENA + The bit is used to enable the first section for autoload operation on L1-ICache3. + 8 1 read-only - L1_DCACHE_PLD_RST - set this bit to reset preload-logic inside L1-DCache. Recommend that this should only be used to initialize preload-logic when some fatal error of preload-logic occurs. - 4 + L1_ICACHE3_AUTOLOAD_SCT1_ENA + The bit is used to enable the second section for autoload operation on L1-ICache3. + 9 1 - read-write + read-only + + + L1_ICACHE3_AUTOLOAD_RGID + The bit is used to set the gid of l1 icache3 autoload. + 10 + 4 + read-only - L1_CACHE_AUTOLOAD_BUF_CLR_CTRL - Cache Autoload buffer clear control register - 0x254 + L1_ICACHE3_AUTOLOAD_SCT0_ADDR + L1 instruction Cache 3 autoload section 0 address configure register + 0x124 0x20 - L1_ICACHE0_ALD_BUF_CLR - set this bit to clear autoload-buffer inside L1-ICache0. If this bit is active, autoload will not work in L1-ICache0. This bit should not be active when autoload works in L1-ICache0. + L1_ICACHE3_AUTOLOAD_SCT0_ADDR + Those bits are used to configure the start virtual address of the first section for autoload operation on L1-ICache3. Note that it should be used together with L1_ICACHE3_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. 0 - 1 - read-write - - - L1_ICACHE1_ALD_BUF_CLR - set this bit to clear autoload-buffer inside L1-ICache1. If this bit is active, autoload will not work in L1-ICache1. This bit should not be active when autoload works in L1-ICache1. - 1 - 1 - read-write - - - L1_ICACHE2_ALD_BUF_CLR - Reserved - 2 - 1 + 32 read-only + + + + L1_ICACHE3_AUTOLOAD_SCT0_SIZE + L1 instruction Cache 3 autoload section 0 size configure register + 0x128 + 0x20 + - L1_ICACHE3_ALD_BUF_CLR - Reserved - 3 - 1 + L1_ICACHE3_AUTOLOAD_SCT0_SIZE + Those bits are used to configure the size of the first section for autoload operation on L1-ICache3. Note that it should be used together with L1_ICACHE3_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. + 0 + 28 read-only - - L1_DCACHE_ALD_BUF_CLR - set this bit to clear autoload-buffer inside L1-DCache. If this bit is active, autoload will not work in L1-DCache. This bit should not be active when autoload works in L1-DCache. - 4 - 1 - read-write - - L1_UNALLOCATE_BUFFER_CLEAR - Unallocate request buffer clear registers - 0x258 + L1_ICACHE3_AUTOLOAD_SCT1_ADDR + L1 instruction Cache 3 autoload section 1 address configure register + 0x12C 0x20 - L1_ICACHE0_UNALLOC_CLR - The bit is used to clear the unallocate request buffer of l1 icache0 where the unallocate request is responsed but not completed. + L1_ICACHE3_AUTOLOAD_SCT1_ADDR + Those bits are used to configure the start virtual address of the second section for autoload operation on L1-ICache3. Note that it should be used together with L1_ICACHE3_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. 0 - 1 - read-write - - - L1_ICACHE1_UNALLOC_CLR - The bit is used to clear the unallocate request buffer of l1 icache1 where the unallocate request is responsed but not completed. - 1 - 1 - read-write - - - L1_ICACHE2_UNALLOC_CLR - Reserved - 2 - 1 + 32 read-only + + + + L1_ICACHE3_AUTOLOAD_SCT1_SIZE + L1 instruction Cache 3 autoload section 1 size configure register + 0x130 + 0x20 + - L1_ICACHE3_UNALLOC_CLR + L1_ICACHE3_AUTOLOAD_SCT1_SIZE Reserved - 3 - 1 + 0 + 28 read-only - - L1_DCACHE_UNALLOC_CLR - The bit is used to clear the unallocate request buffer of l1 dcache where the unallocate request is responsed but not completed. - 4 - 1 - read-write - - L1_CACHE_OBJECT_CTRL - Cache Tag and Data memory Object control register - 0x25C + L1_DCACHE_AUTOLOAD_CTRL + L1 data Cache autoload-operation control register + 0x134 0x20 + 0x00000002 - L1_ICACHE0_TAG_OBJECT - Set this bit to set L1-ICache0 tag memory as object. This bit should be onehot with the others fields inside this register. + L1_DCACHE_AUTOLOAD_ENA + The bit is used to enable and disable autoload operation on L1-DCache. 1: enable, 0: disable. 0 1 read-write - L1_ICACHE1_TAG_OBJECT - Set this bit to set L1-ICache1 tag memory as object. This bit should be onehot with the others fields inside this register. + L1_DCACHE_AUTOLOAD_DONE + The bit is used to indicate whether autoload operation on L1-DCache is finished or not. 0: not finished. 1: finished. 1 1 - read-write + read-only - L1_ICACHE2_TAG_OBJECT - Reserved + L1_DCACHE_AUTOLOAD_ORDER + The bit is used to configure the direction of autoload operation on L1-DCache. 0: ascending. 1: descending. 2 1 - read-only + read-write - L1_ICACHE3_TAG_OBJECT - Reserved + L1_DCACHE_AUTOLOAD_TRIGGER_MODE + The field is used to configure trigger mode of autoload operation on L1-DCache. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. 3 - 1 - read-only - - - L1_DCACHE_TAG_OBJECT - Set this bit to set L1-DCache tag memory as object. This bit should be onehot with the others fields inside this register. - 4 - 1 + 2 read-write - L1_ICACHE0_MEM_OBJECT - Set this bit to set L1-ICache0 data memory as object. This bit should be onehot with the others fields inside this register. - 6 + L1_DCACHE_AUTOLOAD_SCT0_ENA + The bit is used to enable the first section for autoload operation on L1-DCache. + 8 1 read-write - L1_ICACHE1_MEM_OBJECT - Set this bit to set L1-ICache1 data memory as object. This bit should be onehot with the others fields inside this register. - 7 + L1_DCACHE_AUTOLOAD_SCT1_ENA + The bit is used to enable the second section for autoload operation on L1-DCache. + 9 1 read-write - L1_ICACHE2_MEM_OBJECT - Reserved - 8 + L1_DCACHE_AUTOLOAD_SCT2_ENA + The bit is used to enable the third section for autoload operation on L1-DCache. + 10 1 - read-only + read-write - L1_ICACHE3_MEM_OBJECT - Reserved - 9 + L1_DCACHE_AUTOLOAD_SCT3_ENA + The bit is used to enable the fourth section for autoload operation on L1-DCache. + 11 1 - read-only + read-write - L1_DCACHE_MEM_OBJECT - Set this bit to set L1-DCache data memory as object. This bit should be onehot with the others fields inside this register. - 10 - 1 + L1_DCACHE_AUTOLOAD_RGID + The bit is used to set the gid of l1 dcache autoload. + 12 + 4 read-write - L1_CACHE_WAY_OBJECT - Cache Tag and Data memory way register - 0x260 + L1_DCACHE_AUTOLOAD_SCT0_ADDR + L1 data Cache autoload section 0 address configure register + 0x138 0x20 - L1_CACHE_WAY_OBJECT - Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: way1, 2: way2, 3: way3, ?, 7: way7. + L1_DCACHE_AUTOLOAD_SCT0_ADDR + Those bits are used to configure the start virtual address of the first section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT0_SIZE and L1_DCACHE_AUTOLOAD_SCT0_ENA. 0 - 3 + 32 read-write - L1_CACHE_VADDR - Cache Vaddr register - 0x264 + L1_DCACHE_AUTOLOAD_SCT0_SIZE + L1 data Cache autoload section 0 size configure register + 0x13C 0x20 - 0x40000000 - L1_CACHE_VADDR - Those bits stores the virtual address which will decide where inside the specified tag memory object will be accessed. + L1_DCACHE_AUTOLOAD_SCT0_SIZE + Those bits are used to configure the size of the first section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT0_ADDR and L1_DCACHE_AUTOLOAD_SCT0_ENA. 0 - 32 + 28 read-write - L1_CACHE_DEBUG_BUS - Cache Tag/data memory content register - 0x268 + L1_DCACHE_AUTOLOAD_SCT1_ADDR + L1 data Cache autoload section 1 address configure register + 0x140 0x20 - 0x00000268 - L1_CACHE_DEBUG_BUS - This is a constant place where we can write data to or read data from the tag/data memory on the specified cache. + L1_DCACHE_AUTOLOAD_SCT1_ADDR + Those bits are used to configure the start virtual address of the second section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT1_SIZE and L1_DCACHE_AUTOLOAD_SCT1_ENA. 0 32 read-write @@ -11169,1161 +10883,800 @@ - LEVEL_SPLIT0 - USED TO SPLIT L1 CACHE AND L2 CACHE - 0x26C + L1_DCACHE_AUTOLOAD_SCT1_SIZE + L1 data Cache autoload section 1 size configure register + 0x144 0x20 - 0x0000026C - LEVEL_SPLIT0 - Reserved + L1_DCACHE_AUTOLOAD_SCT1_SIZE + Those bits are used to configure the size of the second section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT1_ADDR and L1_DCACHE_AUTOLOAD_SCT1_ENA. + 0 + 28 + read-write + + + + + L1_DCACHE_AUTOLOAD_SCT2_ADDR + L1 data Cache autoload section 2 address configure register + 0x148 + 0x20 + + + L1_DCACHE_AUTOLOAD_SCT2_ADDR + Those bits are used to configure the start virtual address of the third section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT2_SIZE and L1_DCACHE_AUTOLOAD_SCT2_ENA. 0 32 - read-only + read-write - L2_CACHE_CTRL - L2 Cache(L2-Cache) control register - 0x270 + L1_DCACHE_AUTOLOAD_SCT2_SIZE + L1 data Cache autoload section 2 size configure register + 0x14C 0x20 - 0x00000010 - L2_CACHE_SHUT_DMA - The bit is used to disable DMA access L2-Cache, 0: enable, 1: disable - 4 - 1 + L1_DCACHE_AUTOLOAD_SCT2_SIZE + Those bits are used to configure the size of the third section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT2_ADDR and L1_DCACHE_AUTOLOAD_SCT2_ENA. + 0 + 28 read-write + + + + L1_DCACHE_AUTOLOAD_SCT3_ADDR + L1 data Cache autoload section 1 address configure register + 0x150 + 0x20 + - L2_CACHE_UNDEF_OP - Reserved - 8 - 8 + L1_DCACHE_AUTOLOAD_SCT3_ADDR + Those bits are used to configure the start virtual address of the fourth section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT3_SIZE and L1_DCACHE_AUTOLOAD_SCT3_ENA. + 0 + 32 read-write - L2_BYPASS_CACHE_CONF - Bypass Cache configure register - 0x274 + L1_DCACHE_AUTOLOAD_SCT3_SIZE + L1 data Cache autoload section 1 size configure register + 0x154 0x20 - BYPASS_L2_CACHE_EN - The bit is used to enable bypass L2-Cache. 0: disable bypass, 1: enable bypass. - 5 - 1 + L1_DCACHE_AUTOLOAD_SCT3_SIZE + Those bits are used to configure the size of the fourth section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT3_ADDR and L1_DCACHE_AUTOLOAD_SCT3_ENA. + 0 + 28 read-write - L2_CACHE_CACHESIZE_CONF - L2 Cache CacheSize mode configure register - 0x278 + L1_CACHE_ACS_CNT_INT_ENA + Cache Access Counter Interrupt enable register + 0x158 0x20 - 0x00000400 - L2_CACHE_CACHESIZE_256 - The field is used to configure cachesize of L2-Cache as 256 bytes. This field and all other fields within this register is onehot. + L1_IBUS0_OVF_INT_ENA + The bit is used to enable interrupt of one of counters overflow that occurs in L1-ICache0 due to bus0 accesses L1-ICache0. 0 1 - read-only + read-write - L2_CACHE_CACHESIZE_512 - The field is used to configure cachesize of L2-Cache as 512 bytes. This field and all other fields within this register is onehot. + L1_IBUS1_OVF_INT_ENA + The bit is used to enable interrupt of one of counters overflow that occurs in L1-ICache1 due to bus1 accesses L1-ICache1. 1 1 - read-only + read-write - L2_CACHE_CACHESIZE_1K - The field is used to configure cachesize of L2-Cache as 1k bytes. This field and all other fields within this register is onehot. + L1_IBUS2_OVF_INT_ENA + Reserved 2 1 read-only - L2_CACHE_CACHESIZE_2K - The field is used to configure cachesize of L2-Cache as 2k bytes. This field and all other fields within this register is onehot. + L1_IBUS3_OVF_INT_ENA + Reserved 3 1 read-only - L2_CACHE_CACHESIZE_4K - The field is used to configure cachesize of L2-Cache as 4k bytes. This field and all other fields within this register is onehot. + L1_DBUS0_OVF_INT_ENA + The bit is used to enable interrupt of one of counters overflow that occurs in L1-DCache due to bus0 accesses L1-DCache. 4 1 - read-only + read-write - L2_CACHE_CACHESIZE_8K - The field is used to configure cachesize of L2-Cache as 8k bytes. This field and all other fields within this register is onehot. + L1_DBUS1_OVF_INT_ENA + The bit is used to enable interrupt of one of counters overflow that occurs in L1-DCache due to bus1 accesses L1-DCache. 5 1 - read-only + read-write - L2_CACHE_CACHESIZE_16K - The field is used to configure cachesize of L2-Cache as 16k bytes. This field and all other fields within this register is onehot. + L1_DBUS2_OVF_INT_ENA + Reserved 6 1 read-only - L2_CACHE_CACHESIZE_32K - The field is used to configure cachesize of L2-Cache as 32k bytes. This field and all other fields within this register is onehot. + L1_DBUS3_OVF_INT_ENA + Reserved 7 1 read-only - - L2_CACHE_CACHESIZE_64K - The field is used to configure cachesize of L2-Cache as 64k bytes. This field and all other fields within this register is onehot. - 8 - 1 - read-only - - - L2_CACHE_CACHESIZE_128K - The field is used to configure cachesize of L2-Cache as 128k bytes. This field and all other fields within this register is onehot. - 9 - 1 - read-write - - - L2_CACHE_CACHESIZE_256K - The field is used to configure cachesize of L2-Cache as 256k bytes. This field and all other fields within this register is onehot. - 10 - 1 - read-write - - - L2_CACHE_CACHESIZE_512K - The field is used to configure cachesize of L2-Cache as 512k bytes. This field and all other fields within this register is onehot. - 11 - 1 - read-write - - - L2_CACHE_CACHESIZE_1024K - The field is used to configure cachesize of L2-Cache as 1024k bytes. This field and all other fields within this register is onehot. - 12 - 1 - read-only - - L2_CACHE_BLOCKSIZE_CONF - L2 Cache BlockSize mode configure register - 0x27C + L1_CACHE_ACS_CNT_INT_CLR + Cache Access Counter Interrupt clear register + 0x15C 0x20 - 0x00000008 - L2_CACHE_BLOCKSIZE_8 - The field is used to configureblocksize of L2-Cache as 8 bytes. This field and all other fields within this register is onehot. + L1_IBUS0_OVF_INT_CLR + The bit is used to clear counters overflow interrupt and counters in L1-ICache0 due to bus0 accesses L1-ICache0. 0 1 - read-only + write-only - L2_CACHE_BLOCKSIZE_16 - The field is used to configureblocksize of L2-Cache as 16 bytes. This field and all other fields within this register is onehot. + L1_IBUS1_OVF_INT_CLR + The bit is used to clear counters overflow interrupt and counters in L1-ICache1 due to bus1 accesses L1-ICache1. 1 1 - read-only + write-only - L2_CACHE_BLOCKSIZE_32 - The field is used to configureblocksize of L2-Cache as 32 bytes. This field and all other fields within this register is onehot. + L1_IBUS2_OVF_INT_CLR + Reserved 2 1 read-only - L2_CACHE_BLOCKSIZE_64 - The field is used to configureblocksize of L2-Cache as 64 bytes. This field and all other fields within this register is onehot. + L1_IBUS3_OVF_INT_CLR + Reserved 3 1 - read-write + read-only - L2_CACHE_BLOCKSIZE_128 - The field is used to configureblocksize of L2-Cache as 128 bytes. This field and all other fields within this register is onehot. + L1_DBUS0_OVF_INT_CLR + The bit is used to clear counters overflow interrupt and counters in L1-DCache due to bus0 accesses L1-DCache. 4 1 - read-write + write-only - L2_CACHE_BLOCKSIZE_256 - The field is used to configureblocksize of L2-Cache as 256 bytes. This field and all other fields within this register is onehot. + L1_DBUS1_OVF_INT_CLR + The bit is used to clear counters overflow interrupt and counters in L1-DCache due to bus1 accesses L1-DCache. 5 1 + write-only + + + L1_DBUS2_OVF_INT_CLR + Reserved + 6 + 1 + read-only + + + L1_DBUS3_OVF_INT_CLR + Reserved + 7 + 1 read-only - L2_CACHE_WRAP_AROUND_CTRL - Cache wrap around control register - 0x280 + L1_CACHE_ACS_CNT_INT_RAW + Cache Access Counter Interrupt raw register + 0x160 0x20 - L2_CACHE_WRAP - Set this bit as 1 to enable L2-Cache wrap around mode. - 5 + L1_IBUS0_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache0 due to bus0 accesses L1-ICache0. + 0 1 read-write - - - - L2_CACHE_TAG_MEM_POWER_CTRL - Cache tag memory power control register - 0x284 - 0x20 - 0x00500000 - - L2_CACHE_TAG_MEM_FORCE_ON - The bit is used to close clock gating of L2-Cache tag memory. 1: close gating, 0: open clock gating. - 20 + L1_IBUS1_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache1 due to bus1 accesses L1-ICache1. + 1 1 read-write - L2_CACHE_TAG_MEM_FORCE_PD - The bit is used to power L2-Cache tag memory down. 0: follow rtc_lslp, 1: power down - 21 + L1_IBUS2_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache2 due to bus2 accesses L1-ICache2. + 2 1 read-write - L2_CACHE_TAG_MEM_FORCE_PU - The bit is used to power L2-Cache tag memory up. 0: follow rtc_lslp, 1: power up - 22 + L1_IBUS3_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache3 due to bus3 accesses L1-ICache3. + 3 1 read-write - - - - L2_CACHE_DATA_MEM_POWER_CTRL - Cache data memory power control register - 0x288 - 0x20 - 0x00500000 - - L2_CACHE_DATA_MEM_FORCE_ON - The bit is used to close clock gating of L2-Cache data memory. 1: close gating, 0: open clock gating. - 20 + L1_DBUS0_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache due to bus0 accesses L1-DCache. + 4 1 read-write - L2_CACHE_DATA_MEM_FORCE_PD - The bit is used to power L2-Cache data memory down. 0: follow rtc_lslp, 1: power down - 21 + L1_DBUS1_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache due to bus1 accesses L1-DCache. + 5 1 read-write - L2_CACHE_DATA_MEM_FORCE_PU - The bit is used to power L2-Cache data memory up. 0: follow rtc_lslp, 1: power up - 22 + L1_DBUS2_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache due to bus2 accesses L1-DCache. + 6 + 1 + read-write + + + L1_DBUS3_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache due to bus3 accesses L1-DCache. + 7 1 read-write - L2_CACHE_FREEZE_CTRL - Cache Freeze control register - 0x28C + L1_CACHE_ACS_CNT_INT_ST + Cache Access Counter Interrupt status register + 0x164 0x20 - L2_CACHE_FREEZE_EN - The bit is used to enable freeze operation on L2-Cache. It can be cleared by software. - 20 + L1_IBUS0_OVF_INT_ST + The bit indicates the interrupt status of one of counters overflow that occurs in L1-ICache0 due to bus0 accesses L1-ICache0. + 0 1 - read-write + read-only - L2_CACHE_FREEZE_MODE - The bit is used to configure mode of freeze operation L2-Cache. 0: a miss-access will not stuck. 1: a miss-access will stuck. - 21 + L1_IBUS1_OVF_INT_ST + The bit indicates the interrupt status of one of counters overflow that occurs in L1-ICache1 due to bus1 accesses L1-ICache1. + 1 1 - read-write + read-only - L2_CACHE_FREEZE_DONE - The bit is used to indicate whether freeze operation on L2-Cache is finished or not. 0: not finished. 1: finished. - 22 + L1_IBUS2_OVF_INT_ST + Reserved + 2 1 read-only - - - - L2_CACHE_DATA_MEM_ACS_CONF - Cache data memory access configure register - 0x290 - 0x20 - 0x00300000 - - L2_CACHE_DATA_MEM_RD_EN - The bit is used to enable config-bus read L2-Cache data memoryory. 0: disable, 1: enable. - 20 + L1_IBUS3_OVF_INT_ST + Reserved + 3 1 - read-write + read-only - L2_CACHE_DATA_MEM_WR_EN - The bit is used to enable config-bus write L2-Cache data memoryory. 0: disable, 1: enable. - 21 + L1_DBUS0_OVF_INT_ST + The bit indicates the interrupt status of one of counters overflow that occurs in L1-DCache due to bus0 accesses L1-DCache. + 4 1 - read-write + read-only - - - - L2_CACHE_TAG_MEM_ACS_CONF - Cache tag memory access configure register - 0x294 - 0x20 - 0x00300000 - - L2_CACHE_TAG_MEM_RD_EN - The bit is used to enable config-bus read L2-Cache tag memoryory. 0: disable, 1: enable. - 20 + L1_DBUS1_OVF_INT_ST + The bit indicates the interrupt status of one of counters overflow that occurs in L1-DCache due to bus1 accesses L1-DCache. + 5 1 - read-write + read-only - L2_CACHE_TAG_MEM_WR_EN - The bit is used to enable config-bus write L2-Cache tag memoryory. 0: disable, 1: enable. - 21 + L1_DBUS2_OVF_INT_ST + Reserved + 6 1 - read-write + read-only + + + L1_DBUS3_OVF_INT_ST + Reserved + 7 + 1 + read-only - L2_CACHE_PRELOCK_CONF - L2 Cache prelock configure register - 0x298 + L1_CACHE_ACS_FAIL_CTRL + Cache Access Fail Configuration register + 0x168 0x20 - L2_CACHE_PRELOCK_SCT0_EN - The bit is used to enable the first section of prelock function on L2-Cache. + L1_ICACHE0_ACS_FAIL_CHECK_MODE + The bit is used to configure l1 icache0 access fail check mode. 0: the access fail is not propagated to the request, 1: the access fail is propagated to the request 0 1 read-write - L2_CACHE_PRELOCK_SCT1_EN - The bit is used to enable the second section of prelock function on L2-Cache. + L1_ICACHE1_ACS_FAIL_CHECK_MODE + The bit is used to configure l1 icache1 access fail check mode. 0: the access fail is not propagated to the request, 1: the access fail is propagated to the request 1 1 read-write - L2_CACHE_PRELOCK_RGID - The bit is used to set the gid of l2 cache prelock. + L1_ICACHE2_ACS_FAIL_CHECK_MODE + The bit is used to configure l1 icache2 access fail check mode. 0: the access fail is not propagated to the request, 1: the access fail is propagated to the request 2 - 4 - read-write - - - - - L2_CACHE_PRELOCK_SCT0_ADDR - L2 Cache prelock section0 address configure register - 0x29C - 0x20 - - - L2_CACHE_PRELOCK_SCT0_ADDR - Those bits are used to configure the start virtual address of the first section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT0_SIZE_REG - 0 - 32 - read-write - - - - - L2_CACHE_PRELOCK_SCT1_ADDR - L2 Cache prelock section1 address configure register - 0x2A0 - 0x20 - - - L2_CACHE_PRELOCK_SCT1_ADDR - Those bits are used to configure the start virtual address of the second section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT1_SIZE_REG - 0 - 32 + 1 read-write - - - - L2_CACHE_PRELOCK_SCT_SIZE - L2 Cache prelock section size configure register - 0x2A4 - 0x20 - 0xFFFFFFFF - - L2_CACHE_PRELOCK_SCT0_SIZE - Those bits are used to configure the size of the first section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT0_ADDR_REG - 0 - 16 + L1_ICACHE3_ACS_FAIL_CHECK_MODE + The bit is used to configure l1 icache3 access fail check mode. 0: the access fail is not propagated to the request, 1: the access fail is propagated to the request + 3 + 1 read-write - L2_CACHE_PRELOCK_SCT1_SIZE - Those bits are used to configure the size of the second section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT1_ADDR_REG - 16 - 16 + L1_DCACHE_ACS_FAIL_CHECK_MODE + The bit is used to configure l1 dcache access fail check mode. 0: the access fail is not propagated to the request, 1: the access fail is propagated to the request + 4 + 1 read-write - L2_CACHE_PRELOAD_CTRL - L2 Cache preload-operation control register - 0x2A8 + L1_CACHE_ACS_FAIL_INT_ENA + Cache Access Fail Interrupt enable register + 0x16C 0x20 - 0x00000002 - L2_CACHE_PRELOAD_ENA - The bit is used to enable preload operation on L2-Cache. It will be cleared by hardware automatically after preload operation is done. + L1_ICACHE0_FAIL_INT_ENA + The bit is used to enable interrupt of access fail that occurs in L1-ICache0 due to cpu accesses L1-ICache0. 0 1 read-write - L2_CACHE_PRELOAD_DONE - The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished. + L1_ICACHE1_FAIL_INT_ENA + The bit is used to enable interrupt of access fail that occurs in L1-ICache1 due to cpu accesses L1-ICache1. 1 1 - read-only + read-write - L2_CACHE_PRELOAD_ORDER - The bit is used to configure the direction of preload operation. 0: ascending, 1: descending. + L1_ICACHE2_FAIL_INT_ENA + Reserved 2 1 - read-write + read-only - L2_CACHE_PRELOAD_RGID - The bit is used to set the gid of l2 cache preload. + L1_ICACHE3_FAIL_INT_ENA + Reserved 3 - 4 - read-write - - - - - L2_CACHE_PRELOAD_ADDR - L2 Cache preload address configure register - 0x2AC - 0x20 - - - L2_CACHE_PRELOAD_ADDR - Those bits are used to configure the start virtual address of preload on L2-Cache, which should be used together with L2_CACHE_PRELOAD_SIZE_REG - 0 - 32 - read-write + 1 + read-only - - - - L2_CACHE_PRELOAD_SIZE - L2 Cache preload size configure register - 0x2B0 - 0x20 - - L2_CACHE_PRELOAD_SIZE - Those bits are used to configure the size of the first section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOAD_ADDR_REG - 0 - 16 + L1_DCACHE_FAIL_INT_ENA + The bit is used to enable interrupt of access fail that occurs in L1-DCache due to cpu accesses L1-DCache. + 4 + 1 read-write - L2_CACHE_AUTOLOAD_CTRL - L2 Cache autoload-operation control register - 0x2B4 + L1_CACHE_ACS_FAIL_INT_CLR + L1-Cache Access Fail Interrupt clear register + 0x170 0x20 - 0x00000002 - L2_CACHE_AUTOLOAD_ENA - The bit is used to enable and disable autoload operation on L2-Cache. 1: enable, 0: disable. + L1_ICACHE0_FAIL_INT_CLR + The bit is used to clear interrupt of access fail that occurs in L1-ICache0 due to cpu accesses L1-ICache0. 0 1 - read-write + write-only - L2_CACHE_AUTOLOAD_DONE - The bit is used to indicate whether autoload operation on L2-Cache is finished or not. 0: not finished. 1: finished. + L1_ICACHE1_FAIL_INT_CLR + The bit is used to clear interrupt of access fail that occurs in L1-ICache1 due to cpu accesses L1-ICache1. 1 1 - read-only + write-only - L2_CACHE_AUTOLOAD_ORDER - The bit is used to configure the direction of autoload operation on L2-Cache. 0: ascending. 1: descending. + L1_ICACHE2_FAIL_INT_CLR + Reserved 2 1 - read-write + read-only - L2_CACHE_AUTOLOAD_TRIGGER_MODE - The field is used to configure trigger mode of autoload operation on L2-Cache. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + L1_ICACHE3_FAIL_INT_CLR + Reserved 3 - 2 - read-write - - - L2_CACHE_AUTOLOAD_SCT0_ENA - The bit is used to enable the first section for autoload operation on L2-Cache. - 8 1 - read-write + read-only - L2_CACHE_AUTOLOAD_SCT1_ENA - The bit is used to enable the second section for autoload operation on L2-Cache. - 9 + L1_DCACHE_FAIL_INT_CLR + The bit is used to clear interrupt of access fail that occurs in L1-DCache due to cpu accesses L1-DCache. + 4 1 - read-write + write-only + + + + L1_CACHE_ACS_FAIL_INT_RAW + Cache Access Fail Interrupt raw register + 0x174 + 0x20 + - L2_CACHE_AUTOLOAD_SCT2_ENA - The bit is used to enable the third section for autoload operation on L2-Cache. - 10 + L1_ICACHE0_FAIL_INT_RAW + The raw bit of the interrupt of access fail that occurs in L1-ICache0. + 0 1 read-write - L2_CACHE_AUTOLOAD_SCT3_ENA - The bit is used to enable the fourth section for autoload operation on L2-Cache. - 11 + L1_ICACHE1_FAIL_INT_RAW + The raw bit of the interrupt of access fail that occurs in L1-ICache1. + 1 1 read-write - L2_CACHE_AUTOLOAD_RGID - The bit is used to set the gid of l2 cache autoload. - 12 - 4 + L1_ICACHE2_FAIL_INT_RAW + The raw bit of the interrupt of access fail that occurs in L1-ICache2. + 2 + 1 read-write - - - - L2_CACHE_AUTOLOAD_SCT0_ADDR - L2 Cache autoload section 0 address configure register - 0x2B8 - 0x20 - - L2_CACHE_AUTOLOAD_SCT0_ADDR - Those bits are used to configure the start virtual address of the first section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT0_SIZE and L2_CACHE_AUTOLOAD_SCT0_ENA. - 0 - 32 + L1_ICACHE3_FAIL_INT_RAW + The raw bit of the interrupt of access fail that occurs in L1-ICache3. + 3 + 1 read-write - - - - L2_CACHE_AUTOLOAD_SCT0_SIZE - L2 Cache autoload section 0 size configure register - 0x2BC - 0x20 - - L2_CACHE_AUTOLOAD_SCT0_SIZE - Those bits are used to configure the size of the first section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT0_ADDR and L2_CACHE_AUTOLOAD_SCT0_ENA. - 0 - 28 + L1_DCACHE_FAIL_INT_RAW + The raw bit of the interrupt of access fail that occurs in L1-DCache. + 4 + 1 read-write - L2_CACHE_AUTOLOAD_SCT1_ADDR - L2 Cache autoload section 1 address configure register - 0x2C0 + L1_CACHE_ACS_FAIL_INT_ST + Cache Access Fail Interrupt status register + 0x178 0x20 - L2_CACHE_AUTOLOAD_SCT1_ADDR - Those bits are used to configure the start virtual address of the second section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT1_SIZE and L2_CACHE_AUTOLOAD_SCT1_ENA. + L1_ICACHE0_FAIL_INT_ST + The bit indicates the interrupt status of access fail that occurs in L1-ICache0 due to cpu accesses L1-ICache. 0 - 32 - read-write + 1 + read-only - - - - L2_CACHE_AUTOLOAD_SCT1_SIZE - L2 Cache autoload section 1 size configure register - 0x2C4 - 0x20 - - L2_CACHE_AUTOLOAD_SCT1_SIZE - Those bits are used to configure the size of the second section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT1_ADDR and L2_CACHE_AUTOLOAD_SCT1_ENA. - 0 - 28 - read-write + L1_ICACHE1_FAIL_INT_ST + The bit indicates the interrupt status of access fail that occurs in L1-ICache1 due to cpu accesses L1-ICache. + 1 + 1 + read-only - - - - L2_CACHE_AUTOLOAD_SCT2_ADDR - L2 Cache autoload section 2 address configure register - 0x2C8 - 0x20 - - L2_CACHE_AUTOLOAD_SCT2_ADDR - Those bits are used to configure the start virtual address of the third section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT2_SIZE and L2_CACHE_AUTOLOAD_SCT2_ENA. - 0 - 32 - read-write + L1_ICACHE2_FAIL_INT_ST + Reserved + 2 + 1 + read-only - - - - L2_CACHE_AUTOLOAD_SCT2_SIZE - L2 Cache autoload section 2 size configure register - 0x2CC - 0x20 - - L2_CACHE_AUTOLOAD_SCT2_SIZE - Those bits are used to configure the size of the third section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT2_ADDR and L2_CACHE_AUTOLOAD_SCT2_ENA. - 0 - 28 - read-write + L1_ICACHE3_FAIL_INT_ST + Reserved + 3 + 1 + read-only - - - - L2_CACHE_AUTOLOAD_SCT3_ADDR - L2 Cache autoload section 3 address configure register - 0x2D0 - 0x20 - - L2_CACHE_AUTOLOAD_SCT3_ADDR - Those bits are used to configure the start virtual address of the fourth section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT3_SIZE and L2_CACHE_AUTOLOAD_SCT3_ENA. - 0 - 32 - read-write + L1_DCACHE_FAIL_INT_ST + The bit indicates the interrupt status of access fail that occurs in L1-DCache due to cpu accesses L1-DCache. + 4 + 1 + read-only - L2_CACHE_AUTOLOAD_SCT3_SIZE - L2 Cache autoload section 3 size configure register - 0x2D4 + L1_CACHE_ACS_CNT_CTRL + Cache Access Counter enable and clear register + 0x17C 0x20 - L2_CACHE_AUTOLOAD_SCT3_SIZE - Those bits are used to configure the size of the fourth section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT3_ADDR and L2_CACHE_AUTOLOAD_SCT3_ENA. + L1_IBUS0_CNT_ENA + The bit is used to enable ibus0 counter in L1-ICache0. 0 - 28 - read-write - - - - - L2_CACHE_ACS_CNT_INT_ENA - Cache Access Counter Interrupt enable register - 0x2D8 - 0x20 - - - L2_IBUS0_OVF_INT_ENA - The bit is used to enable interrupt of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-Cache. - 8 1 read-write - L2_IBUS1_OVF_INT_ENA - The bit is used to enable interrupt of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-Cache. - 9 + L1_IBUS1_CNT_ENA + The bit is used to enable ibus1 counter in L1-ICache1. + 1 1 read-write - L2_IBUS2_OVF_INT_ENA + L1_IBUS2_CNT_ENA Reserved - 10 + 2 1 read-only - L2_IBUS3_OVF_INT_ENA + L1_IBUS3_CNT_ENA Reserved - 11 + 3 1 read-only - L2_DBUS0_OVF_INT_ENA - The bit is used to enable interrupt of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-Cache. - 12 + L1_DBUS0_CNT_ENA + The bit is used to enable dbus0 counter in L1-DCache. + 4 1 read-write - L2_DBUS1_OVF_INT_ENA - The bit is used to enable interrupt of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-Cache. - 13 + L1_DBUS1_CNT_ENA + The bit is used to enable dbus1 counter in L1-DCache. + 5 1 read-write - L2_DBUS2_OVF_INT_ENA + L1_DBUS2_CNT_ENA Reserved - 14 + 6 1 read-only - L2_DBUS3_OVF_INT_ENA + L1_DBUS3_CNT_ENA Reserved - 15 + 7 1 read-only - - - - L2_CACHE_ACS_CNT_INT_CLR - Cache Access Counter Interrupt clear register - 0x2DC - 0x20 - - L2_IBUS0_OVF_INT_CLR - The bit is used to clear counters overflow interrupt and counters in L2-Cache due to bus0 accesses L2-Cache. - 8 + L1_IBUS0_CNT_CLR + The bit is used to clear ibus0 counter in L1-ICache0. + 16 1 write-only - L2_IBUS1_OVF_INT_CLR - The bit is used to clear counters overflow interrupt and counters in L2-Cache due to bus1 accesses L2-Cache. - 9 + L1_IBUS1_CNT_CLR + The bit is used to clear ibus1 counter in L1-ICache1. + 17 1 write-only - L2_IBUS2_OVF_INT_CLR + L1_IBUS2_CNT_CLR Reserved - 10 + 18 1 read-only - L2_IBUS3_OVF_INT_CLR + L1_IBUS3_CNT_CLR Reserved - 11 + 19 1 read-only - L2_DBUS0_OVF_INT_CLR - The bit is used to clear counters overflow interrupt and counters in L2-Cache due to bus0 accesses L2-Cache. - 12 + L1_DBUS0_CNT_CLR + The bit is used to clear dbus0 counter in L1-DCache. + 20 1 write-only - L2_DBUS1_OVF_INT_CLR - The bit is used to clear counters overflow interrupt and counters in L2-Cache due to bus1 accesses L2-Cache. - 13 + L1_DBUS1_CNT_CLR + The bit is used to clear dbus1 counter in L1-DCache. + 21 1 write-only - L2_DBUS2_OVF_INT_CLR + L1_DBUS2_CNT_CLR Reserved - 14 + 22 1 read-only - L2_DBUS3_OVF_INT_CLR + L1_DBUS3_CNT_CLR Reserved - 15 + 23 1 read-only - L2_CACHE_ACS_CNT_INT_RAW - Cache Access Counter Interrupt raw register - 0x2E0 + L1_IBUS0_ACS_HIT_CNT + L1-ICache bus0 Hit-Access Counter register + 0x180 0x20 - L2_IBUS0_OVF_INT_RAW - The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-ICache0. - 8 - 1 - read-write - - - L2_IBUS1_OVF_INT_RAW - The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-ICache1. - 9 - 1 - read-write - - - L2_IBUS2_OVF_INT_RAW - The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus2 accesses L2-ICache2. - 10 - 1 - read-write - - - L2_IBUS3_OVF_INT_RAW - The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus3 accesses L2-ICache3. - 11 - 1 - read-write - - - L2_DBUS0_OVF_INT_RAW - The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-DCache. - 12 - 1 - read-write - - - L2_DBUS1_OVF_INT_RAW - The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-DCache. - 13 - 1 - read-write - - - L2_DBUS2_OVF_INT_RAW - The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus2 accesses L2-DCache. - 14 - 1 - read-write - - - L2_DBUS3_OVF_INT_RAW - The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus3 accesses L2-DCache. - 15 - 1 - read-write + L1_IBUS0_HIT_CNT + The register records the number of hits when bus0 accesses L1-ICache0. + 0 + 32 + read-only - L2_CACHE_ACS_CNT_INT_ST - Cache Access Counter Interrupt status register - 0x2E4 + L1_IBUS0_ACS_MISS_CNT + L1-ICache bus0 Miss-Access Counter register + 0x184 0x20 - L2_IBUS0_OVF_INT_ST - The bit indicates the interrupt status of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-Cache. - 8 - 1 - read-only - - - L2_IBUS1_OVF_INT_ST - The bit indicates the interrupt status of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-Cache. - 9 - 1 - read-only - - - L2_IBUS2_OVF_INT_ST - Reserved - 10 - 1 - read-only - - - L2_IBUS3_OVF_INT_ST - Reserved - 11 - 1 - read-only - - - L2_DBUS0_OVF_INT_ST - The bit indicates the interrupt status of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-Cache. - 12 - 1 - read-only - - - L2_DBUS1_OVF_INT_ST - The bit indicates the interrupt status of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-Cache. - 13 - 1 - read-only - - - L2_DBUS2_OVF_INT_ST - Reserved - 14 - 1 - read-only - - - L2_DBUS3_OVF_INT_ST - Reserved - 15 - 1 + L1_IBUS0_MISS_CNT + The register records the number of missing when bus0 accesses L1-ICache0. + 0 + 32 read-only - L2_CACHE_ACS_FAIL_CTRL - Cache Access Fail Configuration register - 0x2E8 + L1_IBUS0_ACS_CONFLICT_CNT + L1-ICache bus0 Conflict-Access Counter register + 0x188 0x20 - L2_CACHE_ACS_FAIL_CHECK_MODE - The bit is used to configure l2 cache access fail check mode. 0: the access fail is not propagated to the request, 1: the access fail is propagated to the request + L1_IBUS0_CONFLICT_CNT + The register records the number of access-conflicts when bus0 accesses L1-ICache0. 0 - 1 - read-write + 32 + read-only - L2_CACHE_ACS_FAIL_INT_ENA - Cache Access Fail Interrupt enable register - 0x2EC + L1_IBUS0_ACS_NXTLVL_RD_CNT + L1-ICache bus0 Next-Level-Access Counter register + 0x18C 0x20 - L2_CACHE_FAIL_INT_ENA - The bit is used to enable interrupt of access fail that occurs in L2-Cache due to l1 cache accesses L2-Cache. - 5 - 1 - read-write + L1_IBUS0_NXTLVL_RD_CNT + The register records the number of times that L1-ICache accesses L2-Cache due to bus0 accessing L1-ICache0. + 0 + 32 + read-only - L2_CACHE_ACS_FAIL_INT_CLR - L1-Cache Access Fail Interrupt clear register - 0x2F0 + L1_IBUS1_ACS_HIT_CNT + L1-ICache bus1 Hit-Access Counter register + 0x190 0x20 - L2_CACHE_FAIL_INT_CLR - The bit is used to clear interrupt of access fail that occurs in L2-Cache due to l1 cache accesses L2-Cache. - 5 - 1 - write-only + L1_IBUS1_HIT_CNT + The register records the number of hits when bus1 accesses L1-ICache1. + 0 + 32 + read-only - L2_CACHE_ACS_FAIL_INT_RAW - Cache Access Fail Interrupt raw register - 0x2F4 + L1_IBUS1_ACS_MISS_CNT + L1-ICache bus1 Miss-Access Counter register + 0x194 0x20 - L2_CACHE_FAIL_INT_RAW - The raw bit of the interrupt of access fail that occurs in L2-Cache. - 5 - 1 - read-write + L1_IBUS1_MISS_CNT + The register records the number of missing when bus1 accesses L1-ICache1. + 0 + 32 + read-only - L2_CACHE_ACS_FAIL_INT_ST - Cache Access Fail Interrupt status register - 0x2F8 + L1_IBUS1_ACS_CONFLICT_CNT + L1-ICache bus1 Conflict-Access Counter register + 0x198 0x20 - L2_CACHE_FAIL_INT_ST - The bit indicates the interrupt status of access fail that occurs in L2-Cache due to l1 cache accesses L2-Cache. - 5 - 1 + L1_IBUS1_CONFLICT_CNT + The register records the number of access-conflicts when bus1 accesses L1-ICache1. + 0 + 32 read-only - L2_CACHE_ACS_CNT_CTRL - Cache Access Counter enable and clear register - 0x2FC + L1_IBUS1_ACS_NXTLVL_RD_CNT + L1-ICache bus1 Next-Level-Access Counter register + 0x19C 0x20 - L2_IBUS0_CNT_ENA - The bit is used to enable ibus0 counter in L2-Cache. - 8 - 1 - read-write - - - L2_IBUS1_CNT_ENA - The bit is used to enable ibus1 counter in L2-Cache. - 9 - 1 - read-write - - - L2_IBUS2_CNT_ENA - Reserved - 10 - 1 - read-only - - - L2_IBUS3_CNT_ENA - Reserved - 11 - 1 - read-only - - - L2_DBUS0_CNT_ENA - The bit is used to enable dbus0 counter in L2-Cache. - 12 - 1 - read-write - - - L2_DBUS1_CNT_ENA - The bit is used to enable dbus1 counter in L2-Cache. - 13 - 1 - read-write - - - L2_DBUS2_CNT_ENA - Reserved - 14 - 1 - read-only - - - L2_DBUS3_CNT_ENA - Reserved - 15 - 1 - read-only - - - L2_IBUS0_CNT_CLR - The bit is used to clear ibus0 counter in L2-Cache. - 24 - 1 - write-only - - - L2_IBUS1_CNT_CLR - The bit is used to clear ibus1 counter in L2-Cache. - 25 - 1 - write-only - - - L2_IBUS2_CNT_CLR - Reserved - 26 - 1 - read-only - - - L2_IBUS3_CNT_CLR - Reserved - 27 - 1 - read-only - - - L2_DBUS0_CNT_CLR - The bit is used to clear dbus0 counter in L2-Cache. - 28 - 1 - write-only - - - L2_DBUS1_CNT_CLR - The bit is used to clear dbus1 counter in L2-Cache. - 29 - 1 - write-only - - - L2_DBUS2_CNT_CLR - Reserved - 30 - 1 - read-only - - - L2_DBUS3_CNT_CLR - Reserved - 31 - 1 + L1_IBUS1_NXTLVL_RD_CNT + The register records the number of times that L1-ICache accesses L2-Cache due to bus1 accessing L1-ICache1. + 0 + 32 read-only - L2_IBUS0_ACS_HIT_CNT - L2-Cache bus0 Hit-Access Counter register - 0x300 + L1_IBUS2_ACS_HIT_CNT + L1-ICache bus2 Hit-Access Counter register + 0x1A0 0x20 - L2_IBUS0_HIT_CNT - The register records the number of hits when L1-ICache0 accesses L2-Cache due to bus0 accessing L1-ICache0. + L1_IBUS2_HIT_CNT + The register records the number of hits when bus2 accesses L1-ICache2. 0 32 read-only @@ -12331,14 +11684,14 @@ - L2_IBUS0_ACS_MISS_CNT - L2-Cache bus0 Miss-Access Counter register - 0x304 + L1_IBUS2_ACS_MISS_CNT + L1-ICache bus2 Miss-Access Counter register + 0x1A4 0x20 - L2_IBUS0_MISS_CNT - The register records the number of missing when L1-ICache0 accesses L2-Cache due to bus0 accessing L1-ICache0. + L1_IBUS2_MISS_CNT + The register records the number of missing when bus2 accesses L1-ICache2. 0 32 read-only @@ -12346,14 +11699,14 @@ - L2_IBUS0_ACS_CONFLICT_CNT - L2-Cache bus0 Conflict-Access Counter register - 0x308 + L1_IBUS2_ACS_CONFLICT_CNT + L1-ICache bus2 Conflict-Access Counter register + 0x1A8 0x20 - L2_IBUS0_CONFLICT_CNT - The register records the number of access-conflicts when L1-ICache0 accesses L2-Cache due to bus0 accessing L1-ICache0. + L1_IBUS2_CONFLICT_CNT + The register records the number of access-conflicts when bus2 accesses L1-ICache2. 0 32 read-only @@ -12361,14 +11714,14 @@ - L2_IBUS0_ACS_NXTLVL_RD_CNT - L2-Cache bus0 Next-Level-Access Counter register - 0x30C + L1_IBUS2_ACS_NXTLVL_RD_CNT + L1-ICache bus2 Next-Level-Access Counter register + 0x1AC 0x20 - L2_IBUS0_NXTLVL_RD_CNT - The register records the number of times that L2-Cache accesses external memory due to L1-ICache0 accessing L2-Cache due to bus0 accessing L1-ICache0. + L1_IBUS2_NXTLVL_RD_CNT + The register records the number of times that L1-ICache accesses L2-Cache due to bus2 accessing L1-ICache2. 0 32 read-only @@ -12376,14 +11729,14 @@ - L2_IBUS1_ACS_HIT_CNT - L2-Cache bus1 Hit-Access Counter register - 0x310 + L1_IBUS3_ACS_HIT_CNT + L1-ICache bus3 Hit-Access Counter register + 0x1B0 0x20 - L2_IBUS1_HIT_CNT - The register records the number of hits when L1-ICache1 accesses L2-Cache due to bus1 accessing L1-ICache1. + L1_IBUS3_HIT_CNT + The register records the number of hits when bus3 accesses L1-ICache3. 0 32 read-only @@ -12391,14 +11744,14 @@ - L2_IBUS1_ACS_MISS_CNT - L2-Cache bus1 Miss-Access Counter register - 0x314 + L1_IBUS3_ACS_MISS_CNT + L1-ICache bus3 Miss-Access Counter register + 0x1B4 0x20 - L2_IBUS1_MISS_CNT - The register records the number of missing when L1-ICache1 accesses L2-Cache due to bus1 accessing L1-ICache1. + L1_IBUS3_MISS_CNT + The register records the number of missing when bus3 accesses L1-ICache3. 0 32 read-only @@ -12406,14 +11759,14 @@ - L2_IBUS1_ACS_CONFLICT_CNT - L2-Cache bus1 Conflict-Access Counter register - 0x318 + L1_IBUS3_ACS_CONFLICT_CNT + L1-ICache bus3 Conflict-Access Counter register + 0x1B8 0x20 - L2_IBUS1_CONFLICT_CNT - The register records the number of access-conflicts when L1-ICache1 accesses L2-Cache due to bus1 accessing L1-ICache1. + L1_IBUS3_CONFLICT_CNT + The register records the number of access-conflicts when bus3 accesses L1-ICache3. 0 32 read-only @@ -12421,14 +11774,14 @@ - L2_IBUS1_ACS_NXTLVL_RD_CNT - L2-Cache bus1 Next-Level-Access Counter register - 0x31C + L1_IBUS3_ACS_NXTLVL_RD_CNT + L1-ICache bus3 Next-Level-Access Counter register + 0x1BC 0x20 - L2_IBUS1_NXTLVL_RD_CNT - The register records the number of times that L2-Cache accesses external memory due to L1-ICache1 accessing L2-Cache due to bus1 accessing L1-ICache1. + L1_IBUS3_NXTLVL_RD_CNT + The register records the number of times that L1-ICache accesses L2-Cache due to bus3 accessing L1-ICache3. 0 32 read-only @@ -12436,14 +11789,14 @@ - L2_IBUS2_ACS_HIT_CNT - L2-Cache bus2 Hit-Access Counter register - 0x320 + L1_DBUS0_ACS_HIT_CNT + L1-DCache bus0 Hit-Access Counter register + 0x1C0 0x20 - L2_IBUS2_HIT_CNT - The register records the number of hits when L1-ICache2 accesses L2-Cache due to bus2 accessing L1-ICache2. + L1_DBUS0_HIT_CNT + The register records the number of hits when bus0 accesses L1-DCache. 0 32 read-only @@ -12451,14 +11804,14 @@ - L2_IBUS2_ACS_MISS_CNT - L2-Cache bus2 Miss-Access Counter register - 0x324 + L1_DBUS0_ACS_MISS_CNT + L1-DCache bus0 Miss-Access Counter register + 0x1C4 0x20 - L2_IBUS2_MISS_CNT - The register records the number of missing when L1-ICache2 accesses L2-Cache due to bus2 accessing L1-ICache2. + L1_DBUS0_MISS_CNT + The register records the number of missing when bus0 accesses L1-DCache. 0 32 read-only @@ -12466,14 +11819,14 @@ - L2_IBUS2_ACS_CONFLICT_CNT - L2-Cache bus2 Conflict-Access Counter register - 0x328 + L1_DBUS0_ACS_CONFLICT_CNT + L1-DCache bus0 Conflict-Access Counter register + 0x1C8 0x20 - L2_IBUS2_CONFLICT_CNT - The register records the number of access-conflicts when L1-ICache2 accesses L2-Cache due to bus2 accessing L1-ICache2. + L1_DBUS0_CONFLICT_CNT + The register records the number of access-conflicts when bus0 accesses L1-DCache. 0 32 read-only @@ -12481,14 +11834,14 @@ - L2_IBUS2_ACS_NXTLVL_RD_CNT - L2-Cache bus2 Next-Level-Access Counter register - 0x32C + L1_DBUS0_ACS_NXTLVL_RD_CNT + L1-DCache bus0 Next-Level-Access Counter register + 0x1CC 0x20 - L2_IBUS2_NXTLVL_RD_CNT - The register records the number of times that L2-Cache accesses external memory due to L1-ICache2 accessing L2-Cache due to bus2 accessing L1-ICache2. + L1_DBUS0_NXTLVL_RD_CNT + The register records the number of times that L1-DCache accesses L2-Cache due to bus0 accessing L1-DCache. 0 32 read-only @@ -12496,14 +11849,14 @@ - L2_IBUS3_ACS_HIT_CNT - L2-Cache bus3 Hit-Access Counter register - 0x330 + L1_DBUS0_ACS_NXTLVL_WR_CNT + L1-DCache bus0 WB-Access Counter register + 0x1D0 0x20 - L2_IBUS3_HIT_CNT - The register records the number of hits when L1-ICache3 accesses L2-Cache due to bus3 accessing L1-ICache3. + L1_DBUS0_NXTLVL_WR_CNT + The register records the number of write back when bus0 accesses L1-DCache. 0 32 read-only @@ -12511,14 +11864,14 @@ - L2_IBUS3_ACS_MISS_CNT - L2-Cache bus3 Miss-Access Counter register - 0x334 + L1_DBUS1_ACS_HIT_CNT + L1-DCache bus1 Hit-Access Counter register + 0x1D4 0x20 - L2_IBUS3_MISS_CNT - The register records the number of missing when L1-ICache3 accesses L2-Cache due to bus3 accessing L1-ICache3. + L1_DBUS1_HIT_CNT + The register records the number of hits when bus1 accesses L1-DCache. 0 32 read-only @@ -12526,14 +11879,14 @@ - L2_IBUS3_ACS_CONFLICT_CNT - L2-Cache bus3 Conflict-Access Counter register - 0x338 + L1_DBUS1_ACS_MISS_CNT + L1-DCache bus1 Miss-Access Counter register + 0x1D8 0x20 - L2_IBUS3_CONFLICT_CNT - The register records the number of access-conflicts when L1-ICache3 accesses L2-Cache due to bus3 accessing L1-ICache3. + L1_DBUS1_MISS_CNT + The register records the number of missing when bus1 accesses L1-DCache. 0 32 read-only @@ -12541,14 +11894,14 @@ - L2_IBUS3_ACS_NXTLVL_RD_CNT - L2-Cache bus3 Next-Level-Access Counter register - 0x33C + L1_DBUS1_ACS_CONFLICT_CNT + L1-DCache bus1 Conflict-Access Counter register + 0x1DC 0x20 - L2_IBUS3_NXTLVL_RD_CNT - The register records the number of times that L2-Cache accesses external memory due to L1-ICache3 accessing L2-Cache due to bus3 accessing L1-ICache3. + L1_DBUS1_CONFLICT_CNT + The register records the number of access-conflicts when bus1 accesses L1-DCache. 0 32 read-only @@ -12556,14 +11909,14 @@ - L2_DBUS0_ACS_HIT_CNT - L2-Cache bus0 Hit-Access Counter register - 0x340 + L1_DBUS1_ACS_NXTLVL_RD_CNT + L1-DCache bus1 Next-Level-Access Counter register + 0x1E0 0x20 - L2_DBUS0_HIT_CNT - The register records the number of hits when L1-DCache accesses L2-Cache due to bus0 accessing L1-DCache. + L1_DBUS1_NXTLVL_RD_CNT + The register records the number of times that L1-DCache accesses L2-Cache due to bus1 accessing L1-DCache. 0 32 read-only @@ -12571,14 +11924,14 @@ - L2_DBUS0_ACS_MISS_CNT - L2-Cache bus0 Miss-Access Counter register - 0x344 + L1_DBUS1_ACS_NXTLVL_WR_CNT + L1-DCache bus1 WB-Access Counter register + 0x1E4 0x20 - L2_DBUS0_MISS_CNT - The register records the number of missing when L1-DCache accesses L2-Cache due to bus0 accessing L1-DCache. + L1_DBUS1_NXTLVL_WR_CNT + The register records the number of write back when bus1 accesses L1-DCache. 0 32 read-only @@ -12586,14 +11939,14 @@ - L2_DBUS0_ACS_CONFLICT_CNT - L2-Cache bus0 Conflict-Access Counter register - 0x348 + L1_DBUS2_ACS_HIT_CNT + L1-DCache bus2 Hit-Access Counter register + 0x1E8 0x20 - L2_DBUS0_CONFLICT_CNT - The register records the number of access-conflicts when L1-DCache accesses L2-Cache due to bus0 accessing L1-DCache. + L1_DBUS2_HIT_CNT + The register records the number of hits when bus2 accesses L1-DCache. 0 32 read-only @@ -12601,14 +11954,14 @@ - L2_DBUS0_ACS_NXTLVL_RD_CNT - L2-Cache bus0 Next-Level-Access Counter register - 0x34C + L1_DBUS2_ACS_MISS_CNT + L1-DCache bus2 Miss-Access Counter register + 0x1EC 0x20 - L2_DBUS0_NXTLVL_RD_CNT - The register records the number of times that L2-Cache accesses external memory due to L1-DCache accessing L2-Cache due to bus0 accessing L1-DCache. + L1_DBUS2_MISS_CNT + The register records the number of missing when bus2 accesses L1-DCache. 0 32 read-only @@ -12616,14 +11969,14 @@ - L2_DBUS0_ACS_NXTLVL_WR_CNT - L2-Cache bus0 WB-Access Counter register - 0x350 + L1_DBUS2_ACS_CONFLICT_CNT + L1-DCache bus2 Conflict-Access Counter register + 0x1F0 0x20 - L2_DBUS0_NXTLVL_WR_CNT - The register records the number of write back when L1-DCache accesses L2-Cache due to bus0 accessing L1-DCache. + L1_DBUS2_CONFLICT_CNT + The register records the number of access-conflicts when bus2 accesses L1-DCache. 0 32 read-only @@ -12631,14 +11984,14 @@ - L2_DBUS1_ACS_HIT_CNT - L2-Cache bus1 Hit-Access Counter register - 0x354 + L1_DBUS2_ACS_NXTLVL_RD_CNT + L1-DCache bus2 Next-Level-Access Counter register + 0x1F4 0x20 - L2_DBUS1_HIT_CNT - The register records the number of hits when L1-DCache accesses L2-Cache due to bus1 accessing L1-DCache. + L1_DBUS2_NXTLVL_RD_CNT + The register records the number of times that L1-DCache accesses L2-Cache due to bus2 accessing L1-DCache. 0 32 read-only @@ -12646,14 +11999,14 @@ - L2_DBUS1_ACS_MISS_CNT - L2-Cache bus1 Miss-Access Counter register - 0x358 + L1_DBUS2_ACS_NXTLVL_WR_CNT + L1-DCache bus2 WB-Access Counter register + 0x1F8 0x20 - L2_DBUS1_MISS_CNT - The register records the number of missing when L1-DCache accesses L2-Cache due to bus1 accessing L1-DCache. + L1_DBUS2_NXTLVL_WR_CNT + The register records the number of write back when bus2 accesses L1-DCache. 0 32 read-only @@ -12661,14 +12014,14 @@ - L2_DBUS1_ACS_CONFLICT_CNT - L2-Cache bus1 Conflict-Access Counter register - 0x35C + L1_DBUS3_ACS_HIT_CNT + L1-DCache bus3 Hit-Access Counter register + 0x1FC 0x20 - L2_DBUS1_CONFLICT_CNT - The register records the number of access-conflicts when L1-DCache accesses L2-Cache due to bus1 accessing L1-DCache. + L1_DBUS3_HIT_CNT + The register records the number of hits when bus3 accesses L1-DCache. 0 32 read-only @@ -12676,14 +12029,14 @@ - L2_DBUS1_ACS_NXTLVL_RD_CNT - L2-Cache bus1 Next-Level-Access Counter register - 0x360 + L1_DBUS3_ACS_MISS_CNT + L1-DCache bus3 Miss-Access Counter register + 0x200 0x20 - L2_DBUS1_NXTLVL_RD_CNT - The register records the number of times that L2-Cache accesses external memory due to L1-DCache accessing L2-Cache due to bus1 accessing L1-DCache. + L1_DBUS3_MISS_CNT + The register records the number of missing when bus3 accesses L1-DCache. 0 32 read-only @@ -12691,14 +12044,14 @@ - L2_DBUS1_ACS_NXTLVL_WR_CNT - L2-Cache bus1 WB-Access Counter register - 0x364 + L1_DBUS3_ACS_CONFLICT_CNT + L1-DCache bus3 Conflict-Access Counter register + 0x204 0x20 - L2_DBUS1_NXTLVL_WR_CNT - The register records the number of write back when L1-DCache accesses L2-Cache due to bus1 accessing L1-DCache. + L1_DBUS3_CONFLICT_CNT + The register records the number of access-conflicts when bus3 accesses L1-DCache. 0 32 read-only @@ -12706,14 +12059,14 @@ - L2_DBUS2_ACS_HIT_CNT - L2-Cache bus2 Hit-Access Counter register - 0x368 + L1_DBUS3_ACS_NXTLVL_RD_CNT + L1-DCache bus3 Next-Level-Access Counter register + 0x208 0x20 - L2_DBUS2_HIT_CNT - The register records the number of hits when L1-DCache accesses L2-Cache due to bus2 accessing L1-DCache. + L1_DBUS3_NXTLVL_RD_CNT + The register records the number of times that L1-DCache accesses L2-Cache due to bus3 accessing L1-DCache. 0 32 read-only @@ -12721,14 +12074,14 @@ - L2_DBUS2_ACS_MISS_CNT - L2-Cache bus2 Miss-Access Counter register - 0x36C + L1_DBUS3_ACS_NXTLVL_WR_CNT + L1-DCache bus3 WB-Access Counter register + 0x20C 0x20 - L2_DBUS2_MISS_CNT - The register records the number of missing when L1-DCache accesses L2-Cache due to bus2 accessing L1-DCache. + L1_DBUS3_NXTLVL_WR_CNT + The register records the number of write back when bus0 accesses L1-DCache. 0 32 read-only @@ -12736,29 +12089,36 @@ - L2_DBUS2_ACS_CONFLICT_CNT - L2-Cache bus2 Conflict-Access Counter register - 0x370 + L1_ICACHE0_ACS_FAIL_ID_ATTR + L1-ICache0 Access Fail ID/attribution information register + 0x210 0x20 - L2_DBUS2_CONFLICT_CNT - The register records the number of access-conflicts when L1-DCache accesses L2-Cache due to bus2 accessing L1-DCache. + L1_ICACHE0_FAIL_ID + The register records the ID of fail-access when cache0 accesses L1-ICache. 0 - 32 + 16 + read-only + + + L1_ICACHE0_FAIL_ATTR + The register records the attribution of fail-access when cache0 accesses L1-ICache. + 16 + 16 read-only - L2_DBUS2_ACS_NXTLVL_RD_CNT - L2-Cache bus2 Next-Level-Access Counter register - 0x374 + L1_ICACHE0_ACS_FAIL_ADDR + L1-ICache0 Access Fail Address information register + 0x214 0x20 - L2_DBUS2_NXTLVL_RD_CNT - The register records the number of times that L2-Cache accesses external memory due to L1-DCache accessing L2-Cache due to bus2 accessing L1-DCache. + L1_ICACHE0_FAIL_ADDR + The register records the address of fail-access when cache0 accesses L1-ICache. 0 32 read-only @@ -12766,29 +12126,36 @@ - L2_DBUS2_ACS_NXTLVL_WR_CNT - L2-Cache bus2 WB-Access Counter register - 0x378 + L1_ICACHE1_ACS_FAIL_ID_ATTR + L1-ICache0 Access Fail ID/attribution information register + 0x218 0x20 - L2_DBUS2_NXTLVL_WR_CNT - The register records the number of write back when L1-DCache accesses L2-Cache due to bus2 accessing L1-DCache. + L1_ICACHE1_FAIL_ID + The register records the ID of fail-access when cache1 accesses L1-ICache. 0 - 32 + 16 + read-only + + + L1_ICACHE1_FAIL_ATTR + The register records the attribution of fail-access when cache1 accesses L1-ICache. + 16 + 16 read-only - L2_DBUS3_ACS_HIT_CNT - L2-Cache bus3 Hit-Access Counter register - 0x37C + L1_ICACHE1_ACS_FAIL_ADDR + L1-ICache0 Access Fail Address information register + 0x21C 0x20 - L2_DBUS3_HIT_CNT - The register records the number of hits when L1-DCache accesses L2-Cache due to bus3 accessing L1-DCache. + L1_ICACHE1_FAIL_ADDR + The register records the address of fail-access when cache1 accesses L1-ICache. 0 32 read-only @@ -12796,29 +12163,36 @@ - L2_DBUS3_ACS_MISS_CNT - L2-Cache bus3 Miss-Access Counter register - 0x380 + L1_ICACHE2_ACS_FAIL_ID_ATTR + L1-ICache0 Access Fail ID/attribution information register + 0x220 0x20 - L2_DBUS3_MISS_CNT - The register records the number of missing when L1-DCache accesses L2-Cache due to bus3 accessing L1-DCache. + L1_ICACHE2_FAIL_ID + The register records the ID of fail-access when cache2 accesses L1-ICache. 0 - 32 + 16 + read-only + + + L1_ICACHE2_FAIL_ATTR + The register records the attribution of fail-access when cache2 accesses L1-ICache. + 16 + 16 read-only - L2_DBUS3_ACS_CONFLICT_CNT - L2-Cache bus3 Conflict-Access Counter register - 0x384 + L1_ICACHE2_ACS_FAIL_ADDR + L1-ICache0 Access Fail Address information register + 0x224 0x20 - L2_DBUS3_CONFLICT_CNT - The register records the number of access-conflicts when L1-DCache accesses L2-Cache due to bus3 accessing L1-DCache. + L1_ICACHE2_FAIL_ADDR + The register records the address of fail-access when cache2 accesses L1-ICache. 0 32 read-only @@ -12826,29 +12200,36 @@ - L2_DBUS3_ACS_NXTLVL_RD_CNT - L2-Cache bus3 Next-Level-Access Counter register - 0x388 + L1_ICACHE3_ACS_FAIL_ID_ATTR + L1-ICache0 Access Fail ID/attribution information register + 0x228 0x20 - L2_DBUS3_NXTLVL_RD_CNT - The register records the number of times that L2-Cache accesses external memory due to L1-DCache accessing L2-Cache due to bus3 accessing L1-DCache. + L1_ICACHE3_FAIL_ID + The register records the ID of fail-access when cache3 accesses L1-ICache. 0 - 32 + 16 + read-only + + + L1_ICACHE3_FAIL_ATTR + The register records the attribution of fail-access when cache3 accesses L1-ICache. + 16 + 16 read-only - L2_DBUS3_ACS_NXTLVL_WR_CNT - L2-Cache bus3 WB-Access Counter register - 0x38C + L1_ICACHE3_ACS_FAIL_ADDR + L1-ICache0 Access Fail Address information register + 0x22C 0x20 - L2_DBUS3_NXTLVL_WR_CNT - The register records the number of write back when L1-DCache accesses L2-Cache due to bus3 accessing L1-DCache. + L1_ICACHE3_FAIL_ADDR + The register records the address of fail-access when cache3 accesses L1-ICache. 0 32 read-only @@ -12856,21 +12237,21 @@ - L2_CACHE_ACS_FAIL_ID_ATTR - L2-Cache Access Fail ID/attribution information register - 0x390 + L1_DCACHE_ACS_FAIL_ID_ATTR + L1-DCache Access Fail ID/attribution information register + 0x230 0x20 - L2_CACHE_FAIL_ID - The register records the ID of fail-access when L1-Cache accesses L2-Cache. + L1_DCACHE_FAIL_ID + The register records the ID of fail-access when cache accesses L1-DCache. 0 16 read-only - L2_CACHE_FAIL_ATTR - The register records the attribution of fail-access when L1-Cache accesses L2-Cache due to cache accessing L1-Cache. + L1_DCACHE_FAIL_ATTR + The register records the attribution of fail-access when cache accesses L1-DCache. 16 16 read-only @@ -12878,14 +12259,14 @@ - L2_CACHE_ACS_FAIL_ADDR - L2-Cache Access Fail Address information register - 0x394 + L1_DCACHE_ACS_FAIL_ADDR + L1-DCache Access Fail Address information register + 0x234 0x20 - L2_CACHE_FAIL_ADDR - The register records the address of fail-access when L1-Cache accesses L2-Cache. + L1_DCACHE_FAIL_ADDR + The register records the address of fail-access when cache accesses L1-DCache. 0 32 read-only @@ -12893,2416 +12274,2830 @@ - L2_CACHE_SYNC_PRELOAD_INT_ENA + SYNC_L1_CACHE_PRELOAD_INT_ENA L1-Cache Access Fail Interrupt enable register - 0x398 + 0x238 0x20 - L2_CACHE_PLD_DONE_INT_ENA - The bit is used to enable interrupt of L2-Cache preload-operation done. - 5 + L1_ICACHE0_PLD_DONE_INT_ENA + The bit is used to enable interrupt of L1-ICache0 preload-operation. If preload operation is done, interrupt occurs. + 0 1 read-write - L2_CACHE_PLD_ERR_INT_ENA - The bit is used to enable interrupt of L2-Cache preload-operation error. - 12 + L1_ICACHE1_PLD_DONE_INT_ENA + The bit is used to enable interrupt of L1-ICache1 preload-operation. If preload operation is done, interrupt occurs. + 1 1 read-write - - - - L2_CACHE_SYNC_PRELOAD_INT_CLR - Sync Preload operation Interrupt clear register - 0x39C - 0x20 - - L2_CACHE_PLD_DONE_INT_CLR - The bit is used to clear interrupt that occurs only when L2-Cache preload-operation is done. - 5 + L1_ICACHE2_PLD_DONE_INT_ENA + Reserved + 2 1 - write-only + read-only - L2_CACHE_PLD_ERR_INT_CLR - The bit is used to clear interrupt of L2-Cache preload-operation error. - 12 + L1_ICACHE3_PLD_DONE_INT_ENA + Reserved + 3 1 - write-only + read-only - - - - L2_CACHE_SYNC_PRELOAD_INT_RAW - Sync Preload operation Interrupt raw register - 0x3A0 - 0x20 - - L2_CACHE_PLD_DONE_INT_RAW - The raw bit of the interrupt that occurs only when L2-Cache preload-operation is done. - 5 + L1_DCACHE_PLD_DONE_INT_ENA + The bit is used to enable interrupt of L1-DCache preload-operation. If preload operation is done, interrupt occurs. + 4 1 read-write - L2_CACHE_PLD_ERR_INT_RAW - The raw bit of the interrupt that occurs only when L2-Cache preload-operation error occurs. - 12 + SYNC_DONE_INT_ENA + The bit is used to enable interrupt of Cache sync-operation done. + 6 1 read-write - - - - L2_CACHE_SYNC_PRELOAD_INT_ST - L1-Cache Access Fail Interrupt status register - 0x3A4 - 0x20 - - L2_CACHE_PLD_DONE_INT_ST - The bit indicates the status of the interrupt that occurs only when L2-Cache preload-operation is done. - 5 + L1_ICACHE0_PLD_ERR_INT_ENA + The bit is used to enable interrupt of L1-ICache0 preload-operation error. + 7 1 - read-only + read-write - L2_CACHE_PLD_ERR_INT_ST - The bit indicates the status of the interrupt of L2-Cache preload-operation error. - 12 + L1_ICACHE1_PLD_ERR_INT_ENA + The bit is used to enable interrupt of L1-ICache1 preload-operation error. + 8 + 1 + read-write + + + L1_ICACHE2_PLD_ERR_INT_ENA + Reserved + 9 1 read-only - - - - L2_CACHE_SYNC_PRELOAD_EXCEPTION - Cache Sync/Preload Operation exception register - 0x3A8 - 0x20 - - L2_CACHE_PLD_ERR_CODE - The value 2 is Only available which means preload size is error in L2-Cache. + L1_ICACHE3_PLD_ERR_INT_ENA + Reserved 10 - 2 + 1 read-only - - - - L2_CACHE_SYNC_RST_CTRL - Cache Sync Reset control register - 0x3AC - 0x20 - - L2_CACHE_SYNC_RST - set this bit to reset sync-logic inside L2-Cache. Recommend that this should only be used to initialize sync-logic when some fatal error of sync-logic occurs. - 5 + L1_DCACHE_PLD_ERR_INT_ENA + The bit is used to enable interrupt of L1-DCache preload-operation error. + 11 1 read-write - - - - L2_CACHE_PRELOAD_RST_CTRL - Cache Preload Reset control register - 0x3B0 - 0x20 - - L2_CACHE_PLD_RST - set this bit to reset preload-logic inside L2-Cache. Recommend that this should only be used to initialize preload-logic when some fatal error of preload-logic occurs. - 5 + SYNC_ERR_INT_ENA + The bit is used to enable interrupt of Cache sync-operation error. + 13 1 read-write - L2_CACHE_AUTOLOAD_BUF_CLR_CTRL - Cache Autoload buffer clear control register - 0x3B4 + SYNC_L1_CACHE_PRELOAD_INT_CLR + Sync Preload operation Interrupt clear register + 0x23C 0x20 - L2_CACHE_ALD_BUF_CLR - set this bit to clear autoload-buffer inside L2-Cache. If this bit is active, autoload will not work in L2-Cache. This bit should not be active when autoload works in L2-Cache. - 5 + L1_ICACHE0_PLD_DONE_INT_CLR + The bit is used to clear interrupt that occurs only when L1-ICache0 preload-operation is done. + 0 1 - read-write + write-only - - - - L2_UNALLOCATE_BUFFER_CLEAR - Unallocate request buffer clear registers - 0x3B8 - 0x20 - - L2_CACHE_UNALLOC_CLR - The bit is used to clear the unallocate request buffer of l2 icache where the unallocate request is responsed but not completed. - 5 + L1_ICACHE1_PLD_DONE_INT_CLR + The bit is used to clear interrupt that occurs only when L1-ICache1 preload-operation is done. + 1 1 - read-write + write-only - - - - L2_CACHE_ACCESS_ATTR_CTRL - L2 cache access attribute control register - 0x3BC - 0x20 - 0x0000000F - - L2_CACHE_ACCESS_FORCE_CC - Set this bit to force the request to l2 cache with cacheable attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of cacheable and non-cacheable. - 0 + L1_ICACHE2_PLD_DONE_INT_CLR + Reserved + 2 1 - read-write + read-only - L2_CACHE_ACCESS_FORCE_WB - Set this bit to force the request to l2 cache with write-back attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of write-back and write-through. - 1 + L1_ICACHE3_PLD_DONE_INT_CLR + Reserved + 3 1 - read-write + read-only - L2_CACHE_ACCESS_FORCE_WMA - Set this bit to force the request to l2 cache with write-miss-allocate attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of write-miss-allocate and write-miss-no-allocate. - 2 + L1_DCACHE_PLD_DONE_INT_CLR + The bit is used to clear interrupt that occurs only when L1-DCache preload-operation is done. + 4 1 - read-write + write-only - L2_CACHE_ACCESS_FORCE_RMA - Set this bit to force the request to l2 cache with read-miss-allocate attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of read-miss-allocate and read-miss-no-allocate. - 3 + SYNC_DONE_INT_CLR + The bit is used to clear interrupt that occurs only when Cache sync-operation is done. + 6 1 - read-write + write-only - - - - L2_CACHE_OBJECT_CTRL - Cache Tag and Data memory Object control register - 0x3C0 - 0x20 - - L2_CACHE_TAG_OBJECT - Set this bit to set L2-Cache tag memory as object. This bit should be onehot with the others fields inside this register. - 5 + L1_ICACHE0_PLD_ERR_INT_CLR + The bit is used to clear interrupt of L1-ICache0 preload-operation error. + 7 1 - read-write + write-only - L2_CACHE_MEM_OBJECT - Set this bit to set L2-Cache data memory as object. This bit should be onehot with the others fields inside this register. + L1_ICACHE1_PLD_ERR_INT_CLR + The bit is used to clear interrupt of L1-ICache1 preload-operation error. + 8 + 1 + write-only + + + L1_ICACHE2_PLD_ERR_INT_CLR + Reserved + 9 + 1 + read-only + + + L1_ICACHE3_PLD_ERR_INT_CLR + Reserved + 10 + 1 + read-only + + + L1_DCACHE_PLD_ERR_INT_CLR + The bit is used to clear interrupt of L1-DCache preload-operation error. 11 1 - read-write + write-only - - - - L2_CACHE_WAY_OBJECT - Cache Tag and Data memory way register - 0x3C4 - 0x20 - - L2_CACHE_WAY_OBJECT - Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: way1, 2: way2, 3: way3, ?, 7: way7. - 0 - 3 - read-write + SYNC_ERR_INT_CLR + The bit is used to clear interrupt of Cache sync-operation error. + 13 + 1 + write-only - L2_CACHE_VADDR - Cache Vaddr register - 0x3C8 + SYNC_L1_CACHE_PRELOAD_INT_RAW + Sync Preload operation Interrupt raw register + 0x240 0x20 - 0x40000000 - L2_CACHE_VADDR - Those bits stores the virtual address which will decide where inside the specified tag memory object will be accessed. + L1_ICACHE0_PLD_DONE_INT_RAW + The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation is done. 0 - 32 + 1 read-write - - - - L2_CACHE_DEBUG_BUS - Cache Tag/data memory content register - 0x3CC - 0x20 - 0x000003CC - - L2_CACHE_DEBUG_BUS - This is a constant place where we can write data to or read data from the tag/data memory on the specified cache. - 0 - 32 + L1_ICACHE1_PLD_DONE_INT_RAW + The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation is done. + 1 + 1 read-write - - - - LEVEL_SPLIT1 - USED TO SPLIT L1 CACHE AND L2 CACHE - 0x3D0 - 0x20 - 0x000003D0 - - LEVEL_SPLIT1 + L1_ICACHE2_PLD_DONE_INT_RAW Reserved - 0 - 32 - read-only + 2 + 1 + read-write - - - - CLOCK_GATE - Clock gate control register - 0x3D4 - 0x20 - 0x00000001 - - CLK_EN - The bit is used to enable clock gate when access all registers in this module. - 0 + L1_ICACHE3_PLD_DONE_INT_RAW + Reserved + 3 1 read-write - - - - REDUNDANCY_SIG0 - Cache redundancy signal 0 register - 0x3D8 - 0x20 - - REDCY_SIG0 - Those bits are prepared for ECO. - 0 - 32 + L1_DCACHE_PLD_DONE_INT_RAW + The raw bit of the interrupt that occurs only when L1-DCache preload-operation is done. + 4 + 1 read-write - - - - REDUNDANCY_SIG1 - Cache redundancy signal 1 register - 0x3DC - 0x20 - - REDCY_SIG1 - Those bits are prepared for ECO. - 0 - 32 + SYNC_DONE_INT_RAW + The raw bit of the interrupt that occurs only when Cache sync-operation is done. + 6 + 1 read-write - - - - REDUNDANCY_SIG2 - Cache redundancy signal 2 register - 0x3E0 - 0x20 - - REDCY_SIG2 - Those bits are prepared for ECO. - 0 - 32 + L1_ICACHE0_PLD_ERR_INT_RAW + The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation error occurs. + 7 + 1 read-write - - - - REDUNDANCY_SIG3 - Cache redundancy signal 3 register - 0x3E4 - 0x20 - - REDCY_SIG3 - Those bits are prepared for ECO. - 0 - 32 + L1_ICACHE1_PLD_ERR_INT_RAW + The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation error occurs. + 8 + 1 read-write - - - - REDUNDANCY_SIG4 - Cache redundancy signal 0 register - 0x3E8 - 0x20 - - REDCY_SIG4 - Those bits are prepared for ECO. - 0 - 4 - read-only + L1_ICACHE2_PLD_ERR_INT_RAW + Reserved + 9 + 1 + read-write - - - - DATE - Version control register - 0x3FC - 0x20 - 0x02304130 - - DATE - version control register. Note that this default value stored is the latest date when the hardware logic was updated. - 0 - 28 + L1_ICACHE3_PLD_ERR_INT_RAW + Reserved + 10 + 1 read-write - - - - - - INTERRUPT_CORE0 - Interrupt Controller (Core 0) - CORE0 - 0x500D6000 - - 0x0 - 0x218 - registers - - - - LP_RTC_INT_MAP - NA - 0x0 - 0x20 - - CORE0_LP_RTC_INT_MAP - NA - 0 - 6 + L1_DCACHE_PLD_ERR_INT_RAW + The raw bit of the interrupt that occurs only when L1-DCache preload-operation error occurs. + 11 + 1 read-write - - - - LP_WDT_INT_MAP - NA - 0x4 - 0x20 - - CORE0_LP_WDT_INT_MAP - NA - 0 - 6 + SYNC_ERR_INT_RAW + The raw bit of the interrupt that occurs only when Cache sync-operation error occurs. + 13 + 1 read-write - LP_TIMER_REG_0_INT_MAP - NA - 0x8 + SYNC_L1_CACHE_PRELOAD_INT_ST + L1-Cache Access Fail Interrupt status register + 0x244 0x20 - CORE0_LP_TIMER_REG_0_INT_MAP - NA + L1_ICACHE0_PLD_DONE_INT_ST + The bit indicates the status of the interrupt that occurs only when L1-ICache0 preload-operation is done. 0 - 6 - read-write + 1 + read-only - - - - LP_TIMER_REG_1_INT_MAP - NA - 0xC - 0x20 - - CORE0_LP_TIMER_REG_1_INT_MAP - NA - 0 - 6 - read-write + L1_ICACHE1_PLD_DONE_INT_ST + The bit indicates the status of the interrupt that occurs only when L1-ICache1 preload-operation is done. + 1 + 1 + read-only + + + L1_ICACHE2_PLD_DONE_INT_ST + Reserved + 2 + 1 + read-only + + + L1_ICACHE3_PLD_DONE_INT_ST + Reserved + 3 + 1 + read-only + + + L1_DCACHE_PLD_DONE_INT_ST + The bit indicates the status of the interrupt that occurs only when L1-DCache preload-operation is done. + 4 + 1 + read-only + + + SYNC_DONE_INT_ST + The bit indicates the status of the interrupt that occurs only when Cache sync-operation is done. + 6 + 1 + read-only + + + L1_ICACHE0_PLD_ERR_INT_ST + The bit indicates the status of the interrupt of L1-ICache0 preload-operation error. + 7 + 1 + read-only + + + L1_ICACHE1_PLD_ERR_INT_ST + The bit indicates the status of the interrupt of L1-ICache1 preload-operation error. + 8 + 1 + read-only + + + L1_ICACHE2_PLD_ERR_INT_ST + Reserved + 9 + 1 + read-only + + + L1_ICACHE3_PLD_ERR_INT_ST + Reserved + 10 + 1 + read-only + + + L1_DCACHE_PLD_ERR_INT_ST + The bit indicates the status of the interrupt of L1-DCache preload-operation error. + 11 + 1 + read-only + + + SYNC_ERR_INT_ST + The bit indicates the status of the interrupt of Cache sync-operation error. + 13 + 1 + read-only - MB_HP_INT_MAP - NA - 0x10 + SYNC_L1_CACHE_PRELOAD_EXCEPTION + Cache Sync/Preload Operation exception register + 0x248 0x20 - CORE0_MB_HP_INT_MAP - NA + L1_ICACHE0_PLD_ERR_CODE + The value 2 is Only available which means preload size is error in L1-ICache0. 0 - 6 - read-write + 2 + read-only + + + L1_ICACHE1_PLD_ERR_CODE + The value 2 is Only available which means preload size is error in L1-ICache1. + 2 + 2 + read-only + + + L1_ICACHE2_PLD_ERR_CODE + Reserved + 4 + 2 + read-only + + + L1_ICACHE3_PLD_ERR_CODE + Reserved + 6 + 2 + read-only + + + L1_DCACHE_PLD_ERR_CODE + The value 2 is Only available which means preload size is error in L1-DCache. + 8 + 2 + read-only + + + SYNC_ERR_CODE + The values 0-2 are available which means sync map, command conflict and size are error in Cache System. + 12 + 2 + read-only - MB_LP_INT_MAP - NA - 0x14 + L1_CACHE_SYNC_RST_CTRL + Cache Sync Reset control register + 0x24C 0x20 - CORE0_MB_LP_INT_MAP - NA + L1_ICACHE0_SYNC_RST + set this bit to reset sync-logic inside L1-ICache0. Recommend that this should only be used to initialize sync-logic when some fatal error of sync-logic occurs. 0 - 6 + 1 + read-write + + + L1_ICACHE1_SYNC_RST + set this bit to reset sync-logic inside L1-ICache1. Recommend that this should only be used to initialize sync-logic when some fatal error of sync-logic occurs. + 1 + 1 + read-write + + + L1_ICACHE2_SYNC_RST + Reserved + 2 + 1 + read-only + + + L1_ICACHE3_SYNC_RST + Reserved + 3 + 1 + read-only + + + L1_DCACHE_SYNC_RST + set this bit to reset sync-logic inside L1-DCache. Recommend that this should only be used to initialize sync-logic when some fatal error of sync-logic occurs. + 4 + 1 read-write - PMU_REG_0_INT_MAP - NA - 0x18 + L1_CACHE_PRELOAD_RST_CTRL + Cache Preload Reset control register + 0x250 0x20 - CORE0_PMU_REG_0_INT_MAP - NA + L1_ICACHE0_PLD_RST + set this bit to reset preload-logic inside L1-ICache0. Recommend that this should only be used to initialize preload-logic when some fatal error of preload-logic occurs. 0 - 6 + 1 + read-write + + + L1_ICACHE1_PLD_RST + set this bit to reset preload-logic inside L1-ICache1. Recommend that this should only be used to initialize preload-logic when some fatal error of preload-logic occurs. + 1 + 1 + read-write + + + L1_ICACHE2_PLD_RST + Reserved + 2 + 1 + read-only + + + L1_ICACHE3_PLD_RST + Reserved + 3 + 1 + read-only + + + L1_DCACHE_PLD_RST + set this bit to reset preload-logic inside L1-DCache. Recommend that this should only be used to initialize preload-logic when some fatal error of preload-logic occurs. + 4 + 1 read-write - PMU_REG_1_INT_MAP - NA - 0x1C + L1_CACHE_AUTOLOAD_BUF_CLR_CTRL + Cache Autoload buffer clear control register + 0x254 0x20 - CORE0_PMU_REG_1_INT_MAP - NA + L1_ICACHE0_ALD_BUF_CLR + set this bit to clear autoload-buffer inside L1-ICache0. If this bit is active, autoload will not work in L1-ICache0. This bit should not be active when autoload works in L1-ICache0. 0 - 6 + 1 + read-write + + + L1_ICACHE1_ALD_BUF_CLR + set this bit to clear autoload-buffer inside L1-ICache1. If this bit is active, autoload will not work in L1-ICache1. This bit should not be active when autoload works in L1-ICache1. + 1 + 1 + read-write + + + L1_ICACHE2_ALD_BUF_CLR + Reserved + 2 + 1 + read-only + + + L1_ICACHE3_ALD_BUF_CLR + Reserved + 3 + 1 + read-only + + + L1_DCACHE_ALD_BUF_CLR + set this bit to clear autoload-buffer inside L1-DCache. If this bit is active, autoload will not work in L1-DCache. This bit should not be active when autoload works in L1-DCache. + 4 + 1 read-write - LP_ANAPERI_INT_MAP - NA - 0x20 + L1_UNALLOCATE_BUFFER_CLEAR + Unallocate request buffer clear registers + 0x258 0x20 - CORE0_LP_ANAPERI_INT_MAP - NA + L1_ICACHE0_UNALLOC_CLR + The bit is used to clear the unallocate request buffer of l1 icache0 where the unallocate request is responsed but not completed. 0 - 6 + 1 + read-write + + + L1_ICACHE1_UNALLOC_CLR + The bit is used to clear the unallocate request buffer of l1 icache1 where the unallocate request is responsed but not completed. + 1 + 1 + read-write + + + L1_ICACHE2_UNALLOC_CLR + Reserved + 2 + 1 + read-only + + + L1_ICACHE3_UNALLOC_CLR + Reserved + 3 + 1 + read-only + + + L1_DCACHE_UNALLOC_CLR + The bit is used to clear the unallocate request buffer of l1 dcache where the unallocate request is responsed but not completed. + 4 + 1 read-write - LP_ADC_INT_MAP - NA - 0x24 + L1_CACHE_OBJECT_CTRL + Cache Tag and Data memory Object control register + 0x25C 0x20 - CORE0_LP_ADC_INT_MAP - NA + L1_ICACHE0_TAG_OBJECT + Set this bit to set L1-ICache0 tag memory as object. This bit should be onehot with the others fields inside this register. 0 - 6 + 1 + read-write + + + L1_ICACHE1_TAG_OBJECT + Set this bit to set L1-ICache1 tag memory as object. This bit should be onehot with the others fields inside this register. + 1 + 1 + read-write + + + L1_ICACHE2_TAG_OBJECT + Reserved + 2 + 1 + read-only + + + L1_ICACHE3_TAG_OBJECT + Reserved + 3 + 1 + read-only + + + L1_DCACHE_TAG_OBJECT + Set this bit to set L1-DCache tag memory as object. This bit should be onehot with the others fields inside this register. + 4 + 1 + read-write + + + L1_ICACHE0_MEM_OBJECT + Set this bit to set L1-ICache0 data memory as object. This bit should be onehot with the others fields inside this register. + 6 + 1 + read-write + + + L1_ICACHE1_MEM_OBJECT + Set this bit to set L1-ICache1 data memory as object. This bit should be onehot with the others fields inside this register. + 7 + 1 + read-write + + + L1_ICACHE2_MEM_OBJECT + Reserved + 8 + 1 + read-only + + + L1_ICACHE3_MEM_OBJECT + Reserved + 9 + 1 + read-only + + + L1_DCACHE_MEM_OBJECT + Set this bit to set L1-DCache data memory as object. This bit should be onehot with the others fields inside this register. + 10 + 1 read-write - LP_GPIO_INT_MAP - NA - 0x28 + L1_CACHE_WAY_OBJECT + Cache Tag and Data memory way register + 0x260 0x20 - CORE0_LP_GPIO_INT_MAP - NA + L1_CACHE_WAY_OBJECT + Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: way1, 2: way2, 3: way3, ?, 7: way7. 0 - 6 + 3 read-write - LP_I2C_INT_MAP - NA - 0x2C + L1_CACHE_VADDR + Cache Vaddr register + 0x264 0x20 + 0x40000000 - CORE0_LP_I2C_INT_MAP - NA + L1_CACHE_VADDR + Those bits stores the virtual address which will decide where inside the specified tag memory object will be accessed. 0 - 6 + 32 read-write - LP_I2S_INT_MAP - NA - 0x30 + L1_CACHE_DEBUG_BUS + Cache Tag/data memory content register + 0x268 0x20 + 0x00000268 - CORE0_LP_I2S_INT_MAP - NA + L1_CACHE_DEBUG_BUS + This is a constant place where we can write data to or read data from the tag/data memory on the specified cache. 0 - 6 + 32 read-write - LP_SPI_INT_MAP - NA - 0x34 + LEVEL_SPLIT0 + USED TO SPLIT L1 CACHE AND L2 CACHE + 0x26C 0x20 + 0x0000026C - CORE0_LP_SPI_INT_MAP - NA + LEVEL_SPLIT0 + Reserved 0 - 6 - read-write + 32 + read-only - LP_TOUCH_INT_MAP - NA - 0x38 + L2_CACHE_CTRL + L2 Cache(L2-Cache) control register + 0x270 0x20 + 0x00000010 - CORE0_LP_TOUCH_INT_MAP - NA - 0 - 6 + L2_CACHE_SHUT_DMA + The bit is used to disable DMA access L2-Cache, 0: enable, 1: disable + 4 + 1 + read-write + + + L2_CACHE_UNDEF_OP + Reserved + 8 + 8 read-write - LP_TSENS_INT_MAP - NA - 0x3C + L2_BYPASS_CACHE_CONF + Bypass Cache configure register + 0x274 0x20 - CORE0_LP_TSENS_INT_MAP - NA - 0 - 6 + BYPASS_L2_CACHE_EN + The bit is used to enable bypass L2-Cache. 0: disable bypass, 1: enable bypass. + 5 + 1 read-write - LP_UART_INT_MAP - NA - 0x40 + L2_CACHE_CACHESIZE_CONF + L2 Cache CacheSize mode configure register + 0x278 0x20 + 0x00000400 - CORE0_LP_UART_INT_MAP - NA + L2_CACHE_CACHESIZE_256 + The field is used to configure cachesize of L2-Cache as 256 bytes. This field and all other fields within this register is onehot. 0 - 6 + 1 + read-only + + + L2_CACHE_CACHESIZE_512 + The field is used to configure cachesize of L2-Cache as 512 bytes. This field and all other fields within this register is onehot. + 1 + 1 + read-only + + + L2_CACHE_CACHESIZE_1K + The field is used to configure cachesize of L2-Cache as 1k bytes. This field and all other fields within this register is onehot. + 2 + 1 + read-only + + + L2_CACHE_CACHESIZE_2K + The field is used to configure cachesize of L2-Cache as 2k bytes. This field and all other fields within this register is onehot. + 3 + 1 + read-only + + + L2_CACHE_CACHESIZE_4K + The field is used to configure cachesize of L2-Cache as 4k bytes. This field and all other fields within this register is onehot. + 4 + 1 + read-only + + + L2_CACHE_CACHESIZE_8K + The field is used to configure cachesize of L2-Cache as 8k bytes. This field and all other fields within this register is onehot. + 5 + 1 + read-only + + + L2_CACHE_CACHESIZE_16K + The field is used to configure cachesize of L2-Cache as 16k bytes. This field and all other fields within this register is onehot. + 6 + 1 + read-only + + + L2_CACHE_CACHESIZE_32K + The field is used to configure cachesize of L2-Cache as 32k bytes. This field and all other fields within this register is onehot. + 7 + 1 + read-only + + + L2_CACHE_CACHESIZE_64K + The field is used to configure cachesize of L2-Cache as 64k bytes. This field and all other fields within this register is onehot. + 8 + 1 + read-only + + + L2_CACHE_CACHESIZE_128K + The field is used to configure cachesize of L2-Cache as 128k bytes. This field and all other fields within this register is onehot. + 9 + 1 + read-write + + + L2_CACHE_CACHESIZE_256K + The field is used to configure cachesize of L2-Cache as 256k bytes. This field and all other fields within this register is onehot. + 10 + 1 + read-write + + + L2_CACHE_CACHESIZE_512K + The field is used to configure cachesize of L2-Cache as 512k bytes. This field and all other fields within this register is onehot. + 11 + 1 read-write + + L2_CACHE_CACHESIZE_1024K + The field is used to configure cachesize of L2-Cache as 1024k bytes. This field and all other fields within this register is onehot. + 12 + 1 + read-only + - LP_EFUSE_INT_MAP - NA - 0x44 + L2_CACHE_BLOCKSIZE_CONF + L2 Cache BlockSize mode configure register + 0x27C 0x20 + 0x00000008 - CORE0_LP_EFUSE_INT_MAP - NA + L2_CACHE_BLOCKSIZE_8 + The field is used to configureblocksize of L2-Cache as 8 bytes. This field and all other fields within this register is onehot. 0 - 6 + 1 + read-only + + + L2_CACHE_BLOCKSIZE_16 + The field is used to configureblocksize of L2-Cache as 16 bytes. This field and all other fields within this register is onehot. + 1 + 1 + read-only + + + L2_CACHE_BLOCKSIZE_32 + The field is used to configureblocksize of L2-Cache as 32 bytes. This field and all other fields within this register is onehot. + 2 + 1 + read-only + + + L2_CACHE_BLOCKSIZE_64 + The field is used to configureblocksize of L2-Cache as 64 bytes. This field and all other fields within this register is onehot. + 3 + 1 + read-write + + + L2_CACHE_BLOCKSIZE_128 + The field is used to configureblocksize of L2-Cache as 128 bytes. This field and all other fields within this register is onehot. + 4 + 1 read-write + + L2_CACHE_BLOCKSIZE_256 + The field is used to configureblocksize of L2-Cache as 256 bytes. This field and all other fields within this register is onehot. + 5 + 1 + read-only + - LP_SW_INT_MAP - NA - 0x48 + L2_CACHE_WRAP_AROUND_CTRL + Cache wrap around control register + 0x280 0x20 - CORE0_LP_SW_INT_MAP - NA - 0 - 6 + L2_CACHE_WRAP + Set this bit as 1 to enable L2-Cache wrap around mode. + 5 + 1 read-write - LP_SYSREG_INT_MAP - NA - 0x4C + L2_CACHE_TAG_MEM_POWER_CTRL + Cache tag memory power control register + 0x284 0x20 + 0x00500000 - CORE0_LP_SYSREG_INT_MAP - NA - 0 - 6 + L2_CACHE_TAG_MEM_FORCE_ON + The bit is used to close clock gating of L2-Cache tag memory. 1: close gating, 0: open clock gating. + 20 + 1 + read-write + + + L2_CACHE_TAG_MEM_FORCE_PD + The bit is used to power L2-Cache tag memory down. 0: follow rtc_lslp, 1: power down + 21 + 1 + read-write + + + L2_CACHE_TAG_MEM_FORCE_PU + The bit is used to power L2-Cache tag memory up. 0: follow rtc_lslp, 1: power up + 22 + 1 read-write - LP_HUK_INT_MAP - NA - 0x50 + L2_CACHE_DATA_MEM_POWER_CTRL + Cache data memory power control register + 0x288 0x20 + 0x00500000 - CORE0_LP_HUK_INT_MAP - NA - 0 - 6 + L2_CACHE_DATA_MEM_FORCE_ON + The bit is used to close clock gating of L2-Cache data memory. 1: close gating, 0: open clock gating. + 20 + 1 + read-write + + + L2_CACHE_DATA_MEM_FORCE_PD + The bit is used to power L2-Cache data memory down. 0: follow rtc_lslp, 1: power down + 21 + 1 + read-write + + + L2_CACHE_DATA_MEM_FORCE_PU + The bit is used to power L2-Cache data memory up. 0: follow rtc_lslp, 1: power up + 22 + 1 read-write - SYS_ICM_INT_MAP - NA - 0x54 + L2_CACHE_FREEZE_CTRL + Cache Freeze control register + 0x28C 0x20 - CORE0_SYS_ICM_INT_MAP - NA - 0 - 6 + L2_CACHE_FREEZE_EN + The bit is used to enable freeze operation on L2-Cache. It can be cleared by software. + 20 + 1 read-write + + L2_CACHE_FREEZE_MODE + The bit is used to configure mode of freeze operation L2-Cache. 0: a miss-access will not stuck. 1: a miss-access will stuck. + 21 + 1 + read-write + + + L2_CACHE_FREEZE_DONE + The bit is used to indicate whether freeze operation on L2-Cache is finished or not. 0: not finished. 1: finished. + 22 + 1 + read-only + - USB_DEVICE_INT_MAP - NA - 0x58 + L2_CACHE_DATA_MEM_ACS_CONF + Cache data memory access configure register + 0x290 0x20 + 0x00300000 - CORE0_USB_DEVICE_INT_MAP - NA - 0 - 6 + L2_CACHE_DATA_MEM_RD_EN + The bit is used to enable config-bus read L2-Cache data memoryory. 0: disable, 1: enable. + 20 + 1 + read-write + + + L2_CACHE_DATA_MEM_WR_EN + The bit is used to enable config-bus write L2-Cache data memoryory. 0: disable, 1: enable. + 21 + 1 read-write - SDIO_HOST_INT_MAP - NA - 0x5C + L2_CACHE_TAG_MEM_ACS_CONF + Cache tag memory access configure register + 0x294 0x20 + 0x00300000 - CORE0_SDIO_HOST_INT_MAP - NA - 0 - 6 + L2_CACHE_TAG_MEM_RD_EN + The bit is used to enable config-bus read L2-Cache tag memoryory. 0: disable, 1: enable. + 20 + 1 + read-write + + + L2_CACHE_TAG_MEM_WR_EN + The bit is used to enable config-bus write L2-Cache tag memoryory. 0: disable, 1: enable. + 21 + 1 read-write - GDMA_INT_MAP - NA - 0x60 + L2_CACHE_PRELOCK_CONF + L2 Cache prelock configure register + 0x298 0x20 - CORE0_GDMA_INT_MAP - NA + L2_CACHE_PRELOCK_SCT0_EN + The bit is used to enable the first section of prelock function on L2-Cache. 0 - 6 + 1 + read-write + + + L2_CACHE_PRELOCK_SCT1_EN + The bit is used to enable the second section of prelock function on L2-Cache. + 1 + 1 + read-write + + + L2_CACHE_PRELOCK_RGID + The bit is used to set the gid of l2 cache prelock. + 2 + 4 read-write - SPI2_INT_MAP - NA - 0x64 + L2_CACHE_PRELOCK_SCT0_ADDR + L2 Cache prelock section0 address configure register + 0x29C 0x20 - CORE0_SPI2_INT_MAP - NA + L2_CACHE_PRELOCK_SCT0_ADDR + Those bits are used to configure the start virtual address of the first section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT0_SIZE_REG 0 - 6 + 32 read-write - SPI3_INT_MAP - NA - 0x68 + L2_CACHE_PRELOCK_SCT1_ADDR + L2 Cache prelock section1 address configure register + 0x2A0 0x20 - CORE0_SPI3_INT_MAP - NA + L2_CACHE_PRELOCK_SCT1_ADDR + Those bits are used to configure the start virtual address of the second section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT1_SIZE_REG 0 - 6 + 32 read-write - I2S0_INT_MAP - NA - 0x6C + L2_CACHE_PRELOCK_SCT_SIZE + L2 Cache prelock section size configure register + 0x2A4 0x20 + 0xFFFFFFFF - CORE0_I2S0_INT_MAP - NA + L2_CACHE_PRELOCK_SCT0_SIZE + Those bits are used to configure the size of the first section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT0_ADDR_REG 0 - 6 + 16 + read-write + + + L2_CACHE_PRELOCK_SCT1_SIZE + Those bits are used to configure the size of the second section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT1_ADDR_REG + 16 + 16 read-write - I2S1_INT_MAP - NA - 0x70 + L2_CACHE_PRELOAD_CTRL + L2 Cache preload-operation control register + 0x2A8 0x20 + 0x00000002 - CORE0_I2S1_INT_MAP - NA + L2_CACHE_PRELOAD_ENA + The bit is used to enable preload operation on L2-Cache. It will be cleared by hardware automatically after preload operation is done. 0 - 6 + 1 + read-write + + + L2_CACHE_PRELOAD_DONE + The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished. + 1 + 1 + read-only + + + L2_CACHE_PRELOAD_ORDER + The bit is used to configure the direction of preload operation. 0: ascending, 1: descending. + 2 + 1 + read-write + + + L2_CACHE_PRELOAD_RGID + The bit is used to set the gid of l2 cache preload. + 3 + 4 read-write - I2S2_INT_MAP - NA - 0x74 + L2_CACHE_PRELOAD_ADDR + L2 Cache preload address configure register + 0x2AC 0x20 - CORE0_I2S2_INT_MAP - NA + L2_CACHE_PRELOAD_ADDR + Those bits are used to configure the start virtual address of preload on L2-Cache, which should be used together with L2_CACHE_PRELOAD_SIZE_REG 0 - 6 + 32 read-write - UHCI0_INT_MAP - NA - 0x78 + L2_CACHE_PRELOAD_SIZE + L2 Cache preload size configure register + 0x2B0 0x20 - CORE0_UHCI0_INT_MAP - NA + L2_CACHE_PRELOAD_SIZE + Those bits are used to configure the size of the first section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOAD_ADDR_REG 0 - 6 + 16 read-write - UART0_INT_MAP - NA - 0x7C + L2_CACHE_AUTOLOAD_CTRL + L2 Cache autoload-operation control register + 0x2B4 0x20 + 0x00000002 - CORE0_UART0_INT_MAP - NA + L2_CACHE_AUTOLOAD_ENA + The bit is used to enable and disable autoload operation on L2-Cache. 1: enable, 0: disable. 0 - 6 + 1 + read-write + + + L2_CACHE_AUTOLOAD_DONE + The bit is used to indicate whether autoload operation on L2-Cache is finished or not. 0: not finished. 1: finished. + 1 + 1 + read-only + + + L2_CACHE_AUTOLOAD_ORDER + The bit is used to configure the direction of autoload operation on L2-Cache. 0: ascending. 1: descending. + 2 + 1 + read-write + + + L2_CACHE_AUTOLOAD_TRIGGER_MODE + The field is used to configure trigger mode of autoload operation on L2-Cache. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + 3 + 2 + read-write + + + L2_CACHE_AUTOLOAD_SCT0_ENA + The bit is used to enable the first section for autoload operation on L2-Cache. + 8 + 1 + read-write + + + L2_CACHE_AUTOLOAD_SCT1_ENA + The bit is used to enable the second section for autoload operation on L2-Cache. + 9 + 1 + read-write + + + L2_CACHE_AUTOLOAD_SCT2_ENA + The bit is used to enable the third section for autoload operation on L2-Cache. + 10 + 1 + read-write + + + L2_CACHE_AUTOLOAD_SCT3_ENA + The bit is used to enable the fourth section for autoload operation on L2-Cache. + 11 + 1 + read-write + + + L2_CACHE_AUTOLOAD_RGID + The bit is used to set the gid of l2 cache autoload. + 12 + 4 read-write - UART1_INT_MAP - NA - 0x80 + L2_CACHE_AUTOLOAD_SCT0_ADDR + L2 Cache autoload section 0 address configure register + 0x2B8 0x20 - CORE0_UART1_INT_MAP - NA + L2_CACHE_AUTOLOAD_SCT0_ADDR + Those bits are used to configure the start virtual address of the first section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT0_SIZE and L2_CACHE_AUTOLOAD_SCT0_ENA. 0 - 6 + 32 read-write - UART2_INT_MAP - NA - 0x84 + L2_CACHE_AUTOLOAD_SCT0_SIZE + L2 Cache autoload section 0 size configure register + 0x2BC 0x20 - CORE0_UART2_INT_MAP - NA + L2_CACHE_AUTOLOAD_SCT0_SIZE + Those bits are used to configure the size of the first section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT0_ADDR and L2_CACHE_AUTOLOAD_SCT0_ENA. 0 - 6 + 28 read-write - UART3_INT_MAP - NA - 0x88 + L2_CACHE_AUTOLOAD_SCT1_ADDR + L2 Cache autoload section 1 address configure register + 0x2C0 0x20 - CORE0_UART3_INT_MAP - NA + L2_CACHE_AUTOLOAD_SCT1_ADDR + Those bits are used to configure the start virtual address of the second section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT1_SIZE and L2_CACHE_AUTOLOAD_SCT1_ENA. 0 - 6 + 32 read-write - UART4_INT_MAP - NA - 0x8C + L2_CACHE_AUTOLOAD_SCT1_SIZE + L2 Cache autoload section 1 size configure register + 0x2C4 0x20 - CORE0_UART4_INT_MAP - NA + L2_CACHE_AUTOLOAD_SCT1_SIZE + Those bits are used to configure the size of the second section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT1_ADDR and L2_CACHE_AUTOLOAD_SCT1_ENA. 0 - 6 + 28 read-write - LCD_CAM_INT_MAP - NA - 0x90 + L2_CACHE_AUTOLOAD_SCT2_ADDR + L2 Cache autoload section 2 address configure register + 0x2C8 0x20 - CORE0_LCD_CAM_INT_MAP - NA + L2_CACHE_AUTOLOAD_SCT2_ADDR + Those bits are used to configure the start virtual address of the third section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT2_SIZE and L2_CACHE_AUTOLOAD_SCT2_ENA. 0 - 6 + 32 read-write - ADC_INT_MAP - NA - 0x94 + L2_CACHE_AUTOLOAD_SCT2_SIZE + L2 Cache autoload section 2 size configure register + 0x2CC 0x20 - CORE0_ADC_INT_MAP - NA + L2_CACHE_AUTOLOAD_SCT2_SIZE + Those bits are used to configure the size of the third section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT2_ADDR and L2_CACHE_AUTOLOAD_SCT2_ENA. 0 - 6 + 28 read-write - PWM0_INT_MAP - NA - 0x98 + L2_CACHE_AUTOLOAD_SCT3_ADDR + L2 Cache autoload section 3 address configure register + 0x2D0 0x20 - CORE0_PWM0_INT_MAP - NA + L2_CACHE_AUTOLOAD_SCT3_ADDR + Those bits are used to configure the start virtual address of the fourth section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT3_SIZE and L2_CACHE_AUTOLOAD_SCT3_ENA. 0 - 6 + 32 read-write - PWM1_INT_MAP - NA - 0x9C - 0x20 - + L2_CACHE_AUTOLOAD_SCT3_SIZE + L2 Cache autoload section 3 size configure register + 0x2D4 + 0x20 + - CORE0_PWM1_INT_MAP - NA + L2_CACHE_AUTOLOAD_SCT3_SIZE + Those bits are used to configure the size of the fourth section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT3_ADDR and L2_CACHE_AUTOLOAD_SCT3_ENA. 0 - 6 + 28 read-write - CAN0_INT_MAP - NA - 0xA0 + L2_CACHE_ACS_CNT_INT_ENA + Cache Access Counter Interrupt enable register + 0x2D8 0x20 - CORE0_CAN0_INT_MAP - NA - 0 - 6 + L2_IBUS0_OVF_INT_ENA + The bit is used to enable interrupt of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-Cache. + 8 + 1 + read-write + + + L2_IBUS1_OVF_INT_ENA + The bit is used to enable interrupt of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-Cache. + 9 + 1 read-write + + L2_IBUS2_OVF_INT_ENA + Reserved + 10 + 1 + read-only + + + L2_IBUS3_OVF_INT_ENA + Reserved + 11 + 1 + read-only + + + L2_DBUS0_OVF_INT_ENA + The bit is used to enable interrupt of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-Cache. + 12 + 1 + read-write + + + L2_DBUS1_OVF_INT_ENA + The bit is used to enable interrupt of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-Cache. + 13 + 1 + read-write + + + L2_DBUS2_OVF_INT_ENA + Reserved + 14 + 1 + read-only + + + L2_DBUS3_OVF_INT_ENA + Reserved + 15 + 1 + read-only + - CAN1_INT_MAP - NA - 0xA4 + L2_CACHE_ACS_CNT_INT_CLR + Cache Access Counter Interrupt clear register + 0x2DC 0x20 - CORE0_CAN1_INT_MAP - NA - 0 - 6 - read-write + L2_IBUS0_OVF_INT_CLR + The bit is used to clear counters overflow interrupt and counters in L2-Cache due to bus0 accesses L2-Cache. + 8 + 1 + write-only + + + L2_IBUS1_OVF_INT_CLR + The bit is used to clear counters overflow interrupt and counters in L2-Cache due to bus1 accesses L2-Cache. + 9 + 1 + write-only + + + L2_IBUS2_OVF_INT_CLR + Reserved + 10 + 1 + read-only + + + L2_IBUS3_OVF_INT_CLR + Reserved + 11 + 1 + read-only + + + L2_DBUS0_OVF_INT_CLR + The bit is used to clear counters overflow interrupt and counters in L2-Cache due to bus0 accesses L2-Cache. + 12 + 1 + write-only + + + L2_DBUS1_OVF_INT_CLR + The bit is used to clear counters overflow interrupt and counters in L2-Cache due to bus1 accesses L2-Cache. + 13 + 1 + write-only + + + L2_DBUS2_OVF_INT_CLR + Reserved + 14 + 1 + read-only + + + L2_DBUS3_OVF_INT_CLR + Reserved + 15 + 1 + read-only - CAN2_INT_MAP - NA - 0xA8 + L2_CACHE_ACS_CNT_INT_RAW + Cache Access Counter Interrupt raw register + 0x2E0 0x20 - CORE0_CAN2_INT_MAP - NA - 0 - 6 + L2_IBUS0_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-ICache0. + 8 + 1 + read-write + + + L2_IBUS1_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-ICache1. + 9 + 1 + read-write + + + L2_IBUS2_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus2 accesses L2-ICache2. + 10 + 1 + read-write + + + L2_IBUS3_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus3 accesses L2-ICache3. + 11 + 1 + read-write + + + L2_DBUS0_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-DCache. + 12 + 1 + read-write + + + L2_DBUS1_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-DCache. + 13 + 1 + read-write + + + L2_DBUS2_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus2 accesses L2-DCache. + 14 + 1 + read-write + + + L2_DBUS3_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus3 accesses L2-DCache. + 15 + 1 read-write - RMT_INT_MAP - NA - 0xAC + L2_CACHE_ACS_CNT_INT_ST + Cache Access Counter Interrupt status register + 0x2E4 0x20 - CORE0_RMT_INT_MAP - NA - 0 - 6 - read-write + L2_IBUS0_OVF_INT_ST + The bit indicates the interrupt status of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-Cache. + 8 + 1 + read-only + + + L2_IBUS1_OVF_INT_ST + The bit indicates the interrupt status of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-Cache. + 9 + 1 + read-only + + + L2_IBUS2_OVF_INT_ST + Reserved + 10 + 1 + read-only + + + L2_IBUS3_OVF_INT_ST + Reserved + 11 + 1 + read-only + + + L2_DBUS0_OVF_INT_ST + The bit indicates the interrupt status of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-Cache. + 12 + 1 + read-only + + + L2_DBUS1_OVF_INT_ST + The bit indicates the interrupt status of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-Cache. + 13 + 1 + read-only + + + L2_DBUS2_OVF_INT_ST + Reserved + 14 + 1 + read-only + + + L2_DBUS3_OVF_INT_ST + Reserved + 15 + 1 + read-only - I2C0_INT_MAP - NA - 0xB0 + L2_CACHE_ACS_FAIL_CTRL + Cache Access Fail Configuration register + 0x2E8 0x20 - CORE0_I2C0_INT_MAP - NA + L2_CACHE_ACS_FAIL_CHECK_MODE + The bit is used to configure l2 cache access fail check mode. 0: the access fail is not propagated to the request, 1: the access fail is propagated to the request 0 - 6 + 1 read-write - I2C1_INT_MAP - NA - 0xB4 + L2_CACHE_ACS_FAIL_INT_ENA + Cache Access Fail Interrupt enable register + 0x2EC 0x20 - CORE0_I2C1_INT_MAP - NA - 0 - 6 + L2_CACHE_FAIL_INT_ENA + The bit is used to enable interrupt of access fail that occurs in L2-Cache due to l1 cache accesses L2-Cache. + 5 + 1 read-write - TIMERGRP0_T0_INT_MAP - NA - 0xB8 + L2_CACHE_ACS_FAIL_INT_CLR + L1-Cache Access Fail Interrupt clear register + 0x2F0 0x20 - CORE0_TIMERGRP0_T0_INT_MAP - NA - 0 - 6 - read-write + L2_CACHE_FAIL_INT_CLR + The bit is used to clear interrupt of access fail that occurs in L2-Cache due to l1 cache accesses L2-Cache. + 5 + 1 + write-only - TIMERGRP0_T1_INT_MAP - NA - 0xBC + L2_CACHE_ACS_FAIL_INT_RAW + Cache Access Fail Interrupt raw register + 0x2F4 0x20 - CORE0_TIMERGRP0_T1_INT_MAP - NA - 0 - 6 + L2_CACHE_FAIL_INT_RAW + The raw bit of the interrupt of access fail that occurs in L2-Cache. + 5 + 1 read-write - TIMERGRP0_WDT_INT_MAP - NA - 0xC0 + L2_CACHE_ACS_FAIL_INT_ST + Cache Access Fail Interrupt status register + 0x2F8 0x20 - CORE0_TIMERGRP0_WDT_INT_MAP - NA - 0 - 6 - read-write + L2_CACHE_FAIL_INT_ST + The bit indicates the interrupt status of access fail that occurs in L2-Cache due to l1 cache accesses L2-Cache. + 5 + 1 + read-only - TIMERGRP1_T0_INT_MAP - NA - 0xC4 + L2_CACHE_ACS_CNT_CTRL + Cache Access Counter enable and clear register + 0x2FC 0x20 - CORE0_TIMERGRP1_T0_INT_MAP - NA - 0 - 6 + L2_IBUS0_CNT_ENA + The bit is used to enable ibus0 counter in L2-Cache. + 8 + 1 + read-write + + + L2_IBUS1_CNT_ENA + The bit is used to enable ibus1 counter in L2-Cache. + 9 + 1 + read-write + + + L2_IBUS2_CNT_ENA + Reserved + 10 + 1 + read-only + + + L2_IBUS3_CNT_ENA + Reserved + 11 + 1 + read-only + + + L2_DBUS0_CNT_ENA + The bit is used to enable dbus0 counter in L2-Cache. + 12 + 1 + read-write + + + L2_DBUS1_CNT_ENA + The bit is used to enable dbus1 counter in L2-Cache. + 13 + 1 read-write + + L2_DBUS2_CNT_ENA + Reserved + 14 + 1 + read-only + + + L2_DBUS3_CNT_ENA + Reserved + 15 + 1 + read-only + + + L2_IBUS0_CNT_CLR + The bit is used to clear ibus0 counter in L2-Cache. + 24 + 1 + write-only + + + L2_IBUS1_CNT_CLR + The bit is used to clear ibus1 counter in L2-Cache. + 25 + 1 + write-only + + + L2_IBUS2_CNT_CLR + Reserved + 26 + 1 + read-only + + + L2_IBUS3_CNT_CLR + Reserved + 27 + 1 + read-only + + + L2_DBUS0_CNT_CLR + The bit is used to clear dbus0 counter in L2-Cache. + 28 + 1 + write-only + + + L2_DBUS1_CNT_CLR + The bit is used to clear dbus1 counter in L2-Cache. + 29 + 1 + write-only + + + L2_DBUS2_CNT_CLR + Reserved + 30 + 1 + read-only + + + L2_DBUS3_CNT_CLR + Reserved + 31 + 1 + read-only + - TIMERGRP1_T1_INT_MAP - NA - 0xC8 + L2_IBUS0_ACS_HIT_CNT + L2-Cache bus0 Hit-Access Counter register + 0x300 0x20 - CORE0_TIMERGRP1_T1_INT_MAP - NA + L2_IBUS0_HIT_CNT + The register records the number of hits when L1-ICache0 accesses L2-Cache due to bus0 accessing L1-ICache0. 0 - 6 - read-write + 32 + read-only - TIMERGRP1_WDT_INT_MAP - NA - 0xCC + L2_IBUS0_ACS_MISS_CNT + L2-Cache bus0 Miss-Access Counter register + 0x304 0x20 - CORE0_TIMERGRP1_WDT_INT_MAP - NA + L2_IBUS0_MISS_CNT + The register records the number of missing when L1-ICache0 accesses L2-Cache due to bus0 accessing L1-ICache0. 0 - 6 - read-write + 32 + read-only - LEDC_INT_MAP - NA - 0xD0 + L2_IBUS0_ACS_CONFLICT_CNT + L2-Cache bus0 Conflict-Access Counter register + 0x308 0x20 - CORE0_LEDC_INT_MAP - NA + L2_IBUS0_CONFLICT_CNT + The register records the number of access-conflicts when L1-ICache0 accesses L2-Cache due to bus0 accessing L1-ICache0. 0 - 6 - read-write + 32 + read-only - SYSTIMER_TARGET0_INT_MAP - NA - 0xD4 + L2_IBUS0_ACS_NXTLVL_RD_CNT + L2-Cache bus0 Next-Level-Access Counter register + 0x30C 0x20 - CORE0_SYSTIMER_TARGET0_INT_MAP - NA + L2_IBUS0_NXTLVL_RD_CNT + The register records the number of times that L2-Cache accesses external memory due to L1-ICache0 accessing L2-Cache due to bus0 accessing L1-ICache0. 0 - 6 - read-write + 32 + read-only - SYSTIMER_TARGET1_INT_MAP - NA - 0xD8 + L2_IBUS1_ACS_HIT_CNT + L2-Cache bus1 Hit-Access Counter register + 0x310 0x20 - CORE0_SYSTIMER_TARGET1_INT_MAP - NA + L2_IBUS1_HIT_CNT + The register records the number of hits when L1-ICache1 accesses L2-Cache due to bus1 accessing L1-ICache1. 0 - 6 - read-write + 32 + read-only - SYSTIMER_TARGET2_INT_MAP - NA - 0xDC + L2_IBUS1_ACS_MISS_CNT + L2-Cache bus1 Miss-Access Counter register + 0x314 0x20 - CORE0_SYSTIMER_TARGET2_INT_MAP - NA + L2_IBUS1_MISS_CNT + The register records the number of missing when L1-ICache1 accesses L2-Cache due to bus1 accessing L1-ICache1. 0 - 6 - read-write + 32 + read-only - AHB_PDMA_IN_CH0_INT_MAP - NA - 0xE0 + L2_IBUS1_ACS_CONFLICT_CNT + L2-Cache bus1 Conflict-Access Counter register + 0x318 0x20 - CORE0_AHB_PDMA_IN_CH0_INT_MAP - NA + L2_IBUS1_CONFLICT_CNT + The register records the number of access-conflicts when L1-ICache1 accesses L2-Cache due to bus1 accessing L1-ICache1. 0 - 6 - read-write + 32 + read-only - AHB_PDMA_IN_CH1_INT_MAP - NA - 0xE4 + L2_IBUS1_ACS_NXTLVL_RD_CNT + L2-Cache bus1 Next-Level-Access Counter register + 0x31C 0x20 - CORE0_AHB_PDMA_IN_CH1_INT_MAP - NA + L2_IBUS1_NXTLVL_RD_CNT + The register records the number of times that L2-Cache accesses external memory due to L1-ICache1 accessing L2-Cache due to bus1 accessing L1-ICache1. 0 - 6 - read-write + 32 + read-only - AHB_PDMA_IN_CH2_INT_MAP - NA - 0xE8 + L2_IBUS2_ACS_HIT_CNT + L2-Cache bus2 Hit-Access Counter register + 0x320 0x20 - CORE0_AHB_PDMA_IN_CH2_INT_MAP - NA + L2_IBUS2_HIT_CNT + The register records the number of hits when L1-ICache2 accesses L2-Cache due to bus2 accessing L1-ICache2. 0 - 6 - read-write + 32 + read-only - AHB_PDMA_OUT_CH0_INT_MAP - NA - 0xEC + L2_IBUS2_ACS_MISS_CNT + L2-Cache bus2 Miss-Access Counter register + 0x324 0x20 - CORE0_AHB_PDMA_OUT_CH0_INT_MAP - NA + L2_IBUS2_MISS_CNT + The register records the number of missing when L1-ICache2 accesses L2-Cache due to bus2 accessing L1-ICache2. 0 - 6 - read-write + 32 + read-only - AHB_PDMA_OUT_CH1_INT_MAP - NA - 0xF0 + L2_IBUS2_ACS_CONFLICT_CNT + L2-Cache bus2 Conflict-Access Counter register + 0x328 0x20 - CORE0_AHB_PDMA_OUT_CH1_INT_MAP - NA + L2_IBUS2_CONFLICT_CNT + The register records the number of access-conflicts when L1-ICache2 accesses L2-Cache due to bus2 accessing L1-ICache2. 0 - 6 - read-write + 32 + read-only - AHB_PDMA_OUT_CH2_INT_MAP - NA - 0xF4 + L2_IBUS2_ACS_NXTLVL_RD_CNT + L2-Cache bus2 Next-Level-Access Counter register + 0x32C 0x20 - CORE0_AHB_PDMA_OUT_CH2_INT_MAP - NA + L2_IBUS2_NXTLVL_RD_CNT + The register records the number of times that L2-Cache accesses external memory due to L1-ICache2 accessing L2-Cache due to bus2 accessing L1-ICache2. 0 - 6 - read-write + 32 + read-only - AXI_PDMA_IN_CH0_INT_MAP - NA - 0xF8 + L2_IBUS3_ACS_HIT_CNT + L2-Cache bus3 Hit-Access Counter register + 0x330 0x20 - CORE0_AXI_PDMA_IN_CH0_INT_MAP - NA + L2_IBUS3_HIT_CNT + The register records the number of hits when L1-ICache3 accesses L2-Cache due to bus3 accessing L1-ICache3. 0 - 6 - read-write + 32 + read-only - AXI_PDMA_IN_CH1_INT_MAP - NA - 0xFC + L2_IBUS3_ACS_MISS_CNT + L2-Cache bus3 Miss-Access Counter register + 0x334 0x20 - CORE0_AXI_PDMA_IN_CH1_INT_MAP - NA + L2_IBUS3_MISS_CNT + The register records the number of missing when L1-ICache3 accesses L2-Cache due to bus3 accessing L1-ICache3. 0 - 6 - read-write + 32 + read-only - AXI_PDMA_IN_CH2_INT_MAP - NA - 0x100 + L2_IBUS3_ACS_CONFLICT_CNT + L2-Cache bus3 Conflict-Access Counter register + 0x338 0x20 - CORE0_AXI_PDMA_IN_CH2_INT_MAP - NA + L2_IBUS3_CONFLICT_CNT + The register records the number of access-conflicts when L1-ICache3 accesses L2-Cache due to bus3 accessing L1-ICache3. 0 - 6 - read-write + 32 + read-only - AXI_PDMA_OUT_CH0_INT_MAP - NA - 0x104 + L2_IBUS3_ACS_NXTLVL_RD_CNT + L2-Cache bus3 Next-Level-Access Counter register + 0x33C 0x20 - CORE0_AXI_PDMA_OUT_CH0_INT_MAP - NA + L2_IBUS3_NXTLVL_RD_CNT + The register records the number of times that L2-Cache accesses external memory due to L1-ICache3 accessing L2-Cache due to bus3 accessing L1-ICache3. 0 - 6 - read-write + 32 + read-only - AXI_PDMA_OUT_CH1_INT_MAP - NA - 0x108 + L2_DBUS0_ACS_HIT_CNT + L2-Cache bus0 Hit-Access Counter register + 0x340 0x20 - CORE0_AXI_PDMA_OUT_CH1_INT_MAP - NA + L2_DBUS0_HIT_CNT + The register records the number of hits when L1-DCache accesses L2-Cache due to bus0 accessing L1-DCache. 0 - 6 - read-write + 32 + read-only - AXI_PDMA_OUT_CH2_INT_MAP - NA - 0x10C + L2_DBUS0_ACS_MISS_CNT + L2-Cache bus0 Miss-Access Counter register + 0x344 0x20 - CORE0_AXI_PDMA_OUT_CH2_INT_MAP - NA + L2_DBUS0_MISS_CNT + The register records the number of missing when L1-DCache accesses L2-Cache due to bus0 accessing L1-DCache. 0 - 6 - read-write + 32 + read-only - RSA_INT_MAP - NA - 0x110 + L2_DBUS0_ACS_CONFLICT_CNT + L2-Cache bus0 Conflict-Access Counter register + 0x348 0x20 - CORE0_RSA_INT_MAP - NA + L2_DBUS0_CONFLICT_CNT + The register records the number of access-conflicts when L1-DCache accesses L2-Cache due to bus0 accessing L1-DCache. 0 - 6 - read-write + 32 + read-only - AES_INT_MAP - NA - 0x114 + L2_DBUS0_ACS_NXTLVL_RD_CNT + L2-Cache bus0 Next-Level-Access Counter register + 0x34C 0x20 - CORE0_AES_INT_MAP - NA + L2_DBUS0_NXTLVL_RD_CNT + The register records the number of times that L2-Cache accesses external memory due to L1-DCache accessing L2-Cache due to bus0 accessing L1-DCache. 0 - 6 - read-write + 32 + read-only - SHA_INT_MAP - NA - 0x118 + L2_DBUS0_ACS_NXTLVL_WR_CNT + L2-Cache bus0 WB-Access Counter register + 0x350 0x20 - CORE0_SHA_INT_MAP - NA + L2_DBUS0_NXTLVL_WR_CNT + The register records the number of write back when L1-DCache accesses L2-Cache due to bus0 accessing L1-DCache. 0 - 6 - read-write + 32 + read-only - ECC_INT_MAP - NA - 0x11C + L2_DBUS1_ACS_HIT_CNT + L2-Cache bus1 Hit-Access Counter register + 0x354 0x20 - CORE0_ECC_INT_MAP - NA + L2_DBUS1_HIT_CNT + The register records the number of hits when L1-DCache accesses L2-Cache due to bus1 accessing L1-DCache. 0 - 6 - read-write + 32 + read-only - ECDSA_INT_MAP - NA - 0x120 + L2_DBUS1_ACS_MISS_CNT + L2-Cache bus1 Miss-Access Counter register + 0x358 0x20 - CORE0_ECDSA_INT_MAP - NA + L2_DBUS1_MISS_CNT + The register records the number of missing when L1-DCache accesses L2-Cache due to bus1 accessing L1-DCache. 0 - 6 - read-write + 32 + read-only - KM_INT_MAP - NA - 0x124 + L2_DBUS1_ACS_CONFLICT_CNT + L2-Cache bus1 Conflict-Access Counter register + 0x35C 0x20 - CORE0_KM_INT_MAP - NA + L2_DBUS1_CONFLICT_CNT + The register records the number of access-conflicts when L1-DCache accesses L2-Cache due to bus1 accessing L1-DCache. 0 - 6 - read-write + 32 + read-only - GPIO_INT0_MAP - NA - 0x128 + L2_DBUS1_ACS_NXTLVL_RD_CNT + L2-Cache bus1 Next-Level-Access Counter register + 0x360 0x20 - CORE0_GPIO_INT0_MAP - NA + L2_DBUS1_NXTLVL_RD_CNT + The register records the number of times that L2-Cache accesses external memory due to L1-DCache accessing L2-Cache due to bus1 accessing L1-DCache. 0 - 6 - read-write + 32 + read-only - GPIO_INT1_MAP - NA - 0x12C + L2_DBUS1_ACS_NXTLVL_WR_CNT + L2-Cache bus1 WB-Access Counter register + 0x364 0x20 - CORE0_GPIO_INT1_MAP - NA + L2_DBUS1_NXTLVL_WR_CNT + The register records the number of write back when L1-DCache accesses L2-Cache due to bus1 accessing L1-DCache. 0 - 6 - read-write + 32 + read-only - GPIO_INT2_MAP - NA - 0x130 + L2_DBUS2_ACS_HIT_CNT + L2-Cache bus2 Hit-Access Counter register + 0x368 0x20 - CORE0_GPIO_INT2_MAP - NA + L2_DBUS2_HIT_CNT + The register records the number of hits when L1-DCache accesses L2-Cache due to bus2 accessing L1-DCache. 0 - 6 - read-write + 32 + read-only - GPIO_INT3_MAP - NA - 0x134 + L2_DBUS2_ACS_MISS_CNT + L2-Cache bus2 Miss-Access Counter register + 0x36C 0x20 - CORE0_GPIO_INT3_MAP - NA + L2_DBUS2_MISS_CNT + The register records the number of missing when L1-DCache accesses L2-Cache due to bus2 accessing L1-DCache. 0 - 6 - read-write + 32 + read-only - GPIO_PAD_COMP_INT_MAP - NA - 0x138 + L2_DBUS2_ACS_CONFLICT_CNT + L2-Cache bus2 Conflict-Access Counter register + 0x370 0x20 - CORE0_GPIO_PAD_COMP_INT_MAP - NA + L2_DBUS2_CONFLICT_CNT + The register records the number of access-conflicts when L1-DCache accesses L2-Cache due to bus2 accessing L1-DCache. 0 - 6 - read-write + 32 + read-only - CPU_INT_FROM_CPU_0_MAP - NA - 0x13C + L2_DBUS2_ACS_NXTLVL_RD_CNT + L2-Cache bus2 Next-Level-Access Counter register + 0x374 0x20 - CORE0_CPU_INT_FROM_CPU_0_MAP - NA + L2_DBUS2_NXTLVL_RD_CNT + The register records the number of times that L2-Cache accesses external memory due to L1-DCache accessing L2-Cache due to bus2 accessing L1-DCache. 0 - 6 - read-write + 32 + read-only - CPU_INT_FROM_CPU_1_MAP - NA - 0x140 + L2_DBUS2_ACS_NXTLVL_WR_CNT + L2-Cache bus2 WB-Access Counter register + 0x378 0x20 - CORE0_CPU_INT_FROM_CPU_1_MAP - NA + L2_DBUS2_NXTLVL_WR_CNT + The register records the number of write back when L1-DCache accesses L2-Cache due to bus2 accessing L1-DCache. 0 - 6 - read-write + 32 + read-only - CPU_INT_FROM_CPU_2_MAP - NA - 0x144 + L2_DBUS3_ACS_HIT_CNT + L2-Cache bus3 Hit-Access Counter register + 0x37C 0x20 - CORE0_CPU_INT_FROM_CPU_2_MAP - NA + L2_DBUS3_HIT_CNT + The register records the number of hits when L1-DCache accesses L2-Cache due to bus3 accessing L1-DCache. 0 - 6 - read-write + 32 + read-only - CPU_INT_FROM_CPU_3_MAP - NA - 0x148 + L2_DBUS3_ACS_MISS_CNT + L2-Cache bus3 Miss-Access Counter register + 0x380 0x20 - CORE0_CPU_INT_FROM_CPU_3_MAP - NA + L2_DBUS3_MISS_CNT + The register records the number of missing when L1-DCache accesses L2-Cache due to bus3 accessing L1-DCache. 0 - 6 - read-write + 32 + read-only - CACHE_INT_MAP - NA - 0x14C + L2_DBUS3_ACS_CONFLICT_CNT + L2-Cache bus3 Conflict-Access Counter register + 0x384 0x20 - CORE0_CACHE_INT_MAP - NA + L2_DBUS3_CONFLICT_CNT + The register records the number of access-conflicts when L1-DCache accesses L2-Cache due to bus3 accessing L1-DCache. 0 - 6 - read-write + 32 + read-only - FLASH_MSPI_INT_MAP - NA - 0x150 + L2_DBUS3_ACS_NXTLVL_RD_CNT + L2-Cache bus3 Next-Level-Access Counter register + 0x388 0x20 - CORE0_FLASH_MSPI_INT_MAP - NA + L2_DBUS3_NXTLVL_RD_CNT + The register records the number of times that L2-Cache accesses external memory due to L1-DCache accessing L2-Cache due to bus3 accessing L1-DCache. 0 - 6 - read-write + 32 + read-only - CSI_BRIDGE_INT_MAP - NA - 0x154 + L2_DBUS3_ACS_NXTLVL_WR_CNT + L2-Cache bus3 WB-Access Counter register + 0x38C 0x20 - CORE0_CSI_BRIDGE_INT_MAP - NA + L2_DBUS3_NXTLVL_WR_CNT + The register records the number of write back when L1-DCache accesses L2-Cache due to bus3 accessing L1-DCache. 0 - 6 - read-write + 32 + read-only - DSI_BRIDGE_INT_MAP - NA - 0x158 + L2_CACHE_ACS_FAIL_ID_ATTR + L2-Cache Access Fail ID/attribution information register + 0x390 0x20 - CORE0_DSI_BRIDGE_INT_MAP - NA + L2_CACHE_FAIL_ID + The register records the ID of fail-access when L1-Cache accesses L2-Cache. 0 - 6 - read-write + 16 + read-only + + + L2_CACHE_FAIL_ATTR + The register records the attribution of fail-access when L1-Cache accesses L2-Cache due to cache accessing L1-Cache. + 16 + 16 + read-only - CSI_INT_MAP - NA - 0x15C + L2_CACHE_ACS_FAIL_ADDR + L2-Cache Access Fail Address information register + 0x394 0x20 - CORE0_CSI_INT_MAP - NA + L2_CACHE_FAIL_ADDR + The register records the address of fail-access when L1-Cache accesses L2-Cache. 0 - 6 - read-write + 32 + read-only - DSI_INT_MAP - NA - 0x160 + L2_CACHE_SYNC_PRELOAD_INT_ENA + L1-Cache Access Fail Interrupt enable register + 0x398 0x20 - CORE0_DSI_INT_MAP - NA - 0 - 6 + L2_CACHE_PLD_DONE_INT_ENA + The bit is used to enable interrupt of L2-Cache preload-operation done. + 5 + 1 + read-write + + + L2_CACHE_PLD_ERR_INT_ENA + The bit is used to enable interrupt of L2-Cache preload-operation error. + 12 + 1 read-write - GMII_PHY_INT_MAP - NA - 0x164 + L2_CACHE_SYNC_PRELOAD_INT_CLR + Sync Preload operation Interrupt clear register + 0x39C 0x20 - CORE0_GMII_PHY_INT_MAP - NA - 0 - 6 - read-write - - - - - LPI_INT_MAP - NA - 0x168 - 0x20 - - - CORE0_LPI_INT_MAP - NA - 0 - 6 - read-write - - - - - PMT_INT_MAP - NA - 0x16C - 0x20 - - - CORE0_PMT_INT_MAP - NA - 0 - 6 - read-write - - - - - SBD_INT_MAP - NA - 0x170 - 0x20 - - - CORE0_SBD_INT_MAP - NA - 0 - 6 - read-write - - - - - USB_OTG_INT_MAP - NA - 0x174 - 0x20 - - - CORE0_USB_OTG_INT_MAP - NA - 0 - 6 - read-write - - - - - USB_OTG_ENDP_MULTI_PROC_INT_MAP - NA - 0x178 - 0x20 - - - CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP - NA - 0 - 6 - read-write - - - - - JPEG_INT_MAP - NA - 0x17C - 0x20 - - - CORE0_JPEG_INT_MAP - NA - 0 - 6 - read-write - - - - - PPA_INT_MAP - NA - 0x180 - 0x20 - - - CORE0_PPA_INT_MAP - NA - 0 - 6 - read-write - - - - - CORE0_TRACE_INT_MAP - NA - 0x184 - 0x20 - - - CORE0_CORE0_TRACE_INT_MAP - NA - 0 - 6 - read-write - - - - - CORE1_TRACE_INT_MAP - NA - 0x188 - 0x20 - - - CORE0_CORE1_TRACE_INT_MAP - NA - 0 - 6 - read-write - - - - - HP_CORE_CTRL_INT_MAP - NA - 0x18C - 0x20 - - - CORE0_HP_CORE_CTRL_INT_MAP - NA - 0 - 6 - read-write - - - - - ISP_INT_MAP - NA - 0x190 - 0x20 - - - CORE0_ISP_INT_MAP - NA - 0 - 6 - read-write - - - - - I3C_MST_INT_MAP - NA - 0x194 - 0x20 - - - CORE0_I3C_MST_INT_MAP - NA - 0 - 6 - read-write - - - - - I3C_SLV_INT_MAP - NA - 0x198 - 0x20 - - - CORE0_I3C_SLV_INT_MAP - NA - 0 - 6 - read-write - - - - - USB_OTG11_INT_MAP - NA - 0x19C - 0x20 - - - CORE0_USB_OTG11_INT_MAP - NA - 0 - 6 - read-write - - - - - DMA2D_IN_CH0_INT_MAP - NA - 0x1A0 - 0x20 - - - CORE0_DMA2D_IN_CH0_INT_MAP - NA - 0 - 6 - read-write - - - - - DMA2D_IN_CH1_INT_MAP - NA - 0x1A4 - 0x20 - - - CORE0_DMA2D_IN_CH1_INT_MAP - NA - 0 - 6 - read-write + L2_CACHE_PLD_DONE_INT_CLR + The bit is used to clear interrupt that occurs only when L2-Cache preload-operation is done. + 5 + 1 + write-only - - - - DMA2D_OUT_CH0_INT_MAP - NA - 0x1A8 - 0x20 - - CORE0_DMA2D_OUT_CH0_INT_MAP - NA - 0 - 6 - read-write + L2_CACHE_PLD_ERR_INT_CLR + The bit is used to clear interrupt of L2-Cache preload-operation error. + 12 + 1 + write-only - DMA2D_OUT_CH1_INT_MAP - NA - 0x1AC + L2_CACHE_SYNC_PRELOAD_INT_RAW + Sync Preload operation Interrupt raw register + 0x3A0 0x20 - CORE0_DMA2D_OUT_CH1_INT_MAP - NA - 0 - 6 + L2_CACHE_PLD_DONE_INT_RAW + The raw bit of the interrupt that occurs only when L2-Cache preload-operation is done. + 5 + 1 read-write - - - - DMA2D_OUT_CH2_INT_MAP - NA - 0x1B0 - 0x20 - - CORE0_DMA2D_OUT_CH2_INT_MAP - NA - 0 - 6 + L2_CACHE_PLD_ERR_INT_RAW + The raw bit of the interrupt that occurs only when L2-Cache preload-operation error occurs. + 12 + 1 read-write - PSRAM_MSPI_INT_MAP - NA - 0x1B4 + L2_CACHE_SYNC_PRELOAD_INT_ST + L1-Cache Access Fail Interrupt status register + 0x3A4 0x20 - CORE0_PSRAM_MSPI_INT_MAP - NA - 0 - 6 - read-write + L2_CACHE_PLD_DONE_INT_ST + The bit indicates the status of the interrupt that occurs only when L2-Cache preload-operation is done. + 5 + 1 + read-only - - - - HP_SYSREG_INT_MAP - NA - 0x1B8 - 0x20 - - CORE0_HP_SYSREG_INT_MAP - NA - 0 - 6 - read-write + L2_CACHE_PLD_ERR_INT_ST + The bit indicates the status of the interrupt of L2-Cache preload-operation error. + 12 + 1 + read-only - PCNT_INT_MAP - NA - 0x1BC + L2_CACHE_SYNC_PRELOAD_EXCEPTION + Cache Sync/Preload Operation exception register + 0x3A8 0x20 - CORE0_PCNT_INT_MAP - NA - 0 - 6 - read-write + L2_CACHE_PLD_ERR_CODE + The value 2 is Only available which means preload size is error in L2-Cache. + 10 + 2 + read-only - HP_PAU_INT_MAP - NA - 0x1C0 + L2_CACHE_SYNC_RST_CTRL + Cache Sync Reset control register + 0x3AC 0x20 - CORE0_HP_PAU_INT_MAP - NA - 0 - 6 + L2_CACHE_SYNC_RST + set this bit to reset sync-logic inside L2-Cache. Recommend that this should only be used to initialize sync-logic when some fatal error of sync-logic occurs. + 5 + 1 read-write - HP_PARLIO_RX_INT_MAP - NA - 0x1C4 + L2_CACHE_PRELOAD_RST_CTRL + Cache Preload Reset control register + 0x3B0 0x20 - CORE0_HP_PARLIO_RX_INT_MAP - NA - 0 - 6 + L2_CACHE_PLD_RST + set this bit to reset preload-logic inside L2-Cache. Recommend that this should only be used to initialize preload-logic when some fatal error of preload-logic occurs. + 5 + 1 read-write - HP_PARLIO_TX_INT_MAP - NA - 0x1C8 + L2_CACHE_AUTOLOAD_BUF_CLR_CTRL + Cache Autoload buffer clear control register + 0x3B4 0x20 - CORE0_HP_PARLIO_TX_INT_MAP - NA - 0 - 6 + L2_CACHE_ALD_BUF_CLR + set this bit to clear autoload-buffer inside L2-Cache. If this bit is active, autoload will not work in L2-Cache. This bit should not be active when autoload works in L2-Cache. + 5 + 1 read-write - H264_DMA2D_OUT_CH0_INT_MAP - NA - 0x1CC + L2_UNALLOCATE_BUFFER_CLEAR + Unallocate request buffer clear registers + 0x3B8 0x20 - CORE0_H264_DMA2D_OUT_CH0_INT_MAP - NA - 0 - 6 + L2_CACHE_UNALLOC_CLR + The bit is used to clear the unallocate request buffer of l2 icache where the unallocate request is responsed but not completed. + 5 + 1 read-write - H264_DMA2D_OUT_CH1_INT_MAP - NA - 0x1D0 + L2_CACHE_ACCESS_ATTR_CTRL + L2 cache access attribute control register + 0x3BC 0x20 + 0x0000000F - CORE0_H264_DMA2D_OUT_CH1_INT_MAP - NA + L2_CACHE_ACCESS_FORCE_CC + Set this bit to force the request to l2 cache with cacheable attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of cacheable and non-cacheable. 0 - 6 + 1 read-write - - - - H264_DMA2D_OUT_CH2_INT_MAP - NA - 0x1D4 - 0x20 - - CORE0_H264_DMA2D_OUT_CH2_INT_MAP - NA - 0 - 6 + L2_CACHE_ACCESS_FORCE_WB + Set this bit to force the request to l2 cache with write-back attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of write-back and write-through. + 1 + 1 read-write - - - - H264_DMA2D_OUT_CH3_INT_MAP - NA - 0x1D8 - 0x20 - - CORE0_H264_DMA2D_OUT_CH3_INT_MAP - NA - 0 - 6 + L2_CACHE_ACCESS_FORCE_WMA + Set this bit to force the request to l2 cache with write-miss-allocate attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of write-miss-allocate and write-miss-no-allocate. + 2 + 1 read-write - - - - H264_DMA2D_OUT_CH4_INT_MAP - NA - 0x1DC - 0x20 - - CORE0_H264_DMA2D_OUT_CH4_INT_MAP - NA - 0 - 6 + L2_CACHE_ACCESS_FORCE_RMA + Set this bit to force the request to l2 cache with read-miss-allocate attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of read-miss-allocate and read-miss-no-allocate. + 3 + 1 read-write - H264_DMA2D_IN_CH0_INT_MAP - NA - 0x1E0 + L2_CACHE_OBJECT_CTRL + Cache Tag and Data memory Object control register + 0x3C0 0x20 - CORE0_H264_DMA2D_IN_CH0_INT_MAP - NA - 0 - 6 + L2_CACHE_TAG_OBJECT + Set this bit to set L2-Cache tag memory as object. This bit should be onehot with the others fields inside this register. + 5 + 1 read-write - - - - H264_DMA2D_IN_CH1_INT_MAP - NA - 0x1E4 - 0x20 - - CORE0_H264_DMA2D_IN_CH1_INT_MAP - NA - 0 - 6 + L2_CACHE_MEM_OBJECT + Set this bit to set L2-Cache data memory as object. This bit should be onehot with the others fields inside this register. + 11 + 1 read-write - H264_DMA2D_IN_CH2_INT_MAP - NA - 0x1E8 + L2_CACHE_WAY_OBJECT + Cache Tag and Data memory way register + 0x3C4 0x20 - CORE0_H264_DMA2D_IN_CH2_INT_MAP - NA + L2_CACHE_WAY_OBJECT + Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: way1, 2: way2, 3: way3, ?, 7: way7. 0 - 6 + 3 read-write - H264_DMA2D_IN_CH3_INT_MAP - NA - 0x1EC + L2_CACHE_VADDR + Cache Vaddr register + 0x3C8 0x20 + 0x40000000 - CORE0_H264_DMA2D_IN_CH3_INT_MAP - NA + L2_CACHE_VADDR + Those bits stores the virtual address which will decide where inside the specified tag memory object will be accessed. 0 - 6 + 32 read-write - H264_DMA2D_IN_CH4_INT_MAP - NA - 0x1F0 + L2_CACHE_DEBUG_BUS + Cache Tag/data memory content register + 0x3CC 0x20 + 0x000003CC - CORE0_H264_DMA2D_IN_CH4_INT_MAP - NA + L2_CACHE_DEBUG_BUS + This is a constant place where we can write data to or read data from the tag/data memory on the specified cache. 0 - 6 + 32 read-write - H264_DMA2D_IN_CH5_INT_MAP - NA - 0x1F4 + LEVEL_SPLIT1 + USED TO SPLIT L1 CACHE AND L2 CACHE + 0x3D0 0x20 + 0x000003D0 - CORE0_H264_DMA2D_IN_CH5_INT_MAP - NA + LEVEL_SPLIT1 + Reserved 0 - 6 - read-write + 32 + read-only - H264_REG_INT_MAP - NA - 0x1F8 + CLOCK_GATE + Clock gate control register + 0x3D4 0x20 + 0x00000001 - CORE0_H264_REG_INT_MAP - NA + CLK_EN + The bit is used to enable clock gate when access all registers in this module. 0 - 6 + 1 read-write - ASSIST_DEBUG_INT_MAP - NA - 0x1FC + REDUNDANCY_SIG0 + Cache redundancy signal 0 register + 0x3D8 0x20 - CORE0_ASSIST_DEBUG_INT_MAP - NA + REDCY_SIG0 + Those bits are prepared for ECO. 0 - 6 + 32 read-write - INTR_STATUS_REG_0 - NA - 0x200 + REDUNDANCY_SIG1 + Cache redundancy signal 1 register + 0x3DC 0x20 - CORE0_INTR_STATUS_0 - NA + REDCY_SIG1 + Those bits are prepared for ECO. 0 32 - read-only + read-write - INTR_STATUS_REG_1 - NA - 0x204 + REDUNDANCY_SIG2 + Cache redundancy signal 2 register + 0x3E0 0x20 - CORE0_INTR_STATUS_1 - NA + REDCY_SIG2 + Those bits are prepared for ECO. 0 32 - read-only + read-write - INTR_STATUS_REG_2 - NA - 0x208 + REDUNDANCY_SIG3 + Cache redundancy signal 3 register + 0x3E4 0x20 - CORE0_INTR_STATUS_2 - NA + REDCY_SIG3 + Those bits are prepared for ECO. 0 32 - read-only + read-write - INTR_STATUS_REG_3 - NA - 0x20C + REDUNDANCY_SIG4 + Cache redundancy signal 0 register + 0x3E8 0x20 - CORE0_INTR_STATUS_3 - NA + REDCY_SIG4 + Those bits are prepared for ECO. 0 - 32 + 4 read-only - CLOCK_GATE - NA - 0x210 - 0x20 - 0x00000001 - - - CORE0_REG_CLK_EN - NA - 0 - 1 - read-write - - - - - INTERRUPT_REG_DATE - NA + DATE + Version control register 0x3FC 0x20 - 0x02003020 + 0x02304130 - CORE0_INTERRUPT_REG_DATE - NA + DATE + version control register. Note that this default value stored is the latest date when the hardware logic was updated. 0 28 read-write @@ -15312,10 +15107,10 @@ - INTERRUPT_CORE1 - Interrupt Controller (Core 1) - CORE1 - 0x500D6800 + INTERRUPT_CORE0 + Interrupt Controller (Core 0) + CORE0 + 0x500D6000 0x0 0x218 @@ -15329,7 +15124,7 @@ 0x20 - CORE1_LP_RTC_INT_MAP + CORE0_LP_RTC_INT_MAP NA 0 6 @@ -15344,7 +15139,7 @@ 0x20 - CORE1_LP_WDT_INT_MAP + CORE0_LP_WDT_INT_MAP NA 0 6 @@ -15359,7 +15154,7 @@ 0x20 - CORE1_LP_TIMER_REG_0_INT_MAP + CORE0_LP_TIMER_REG_0_INT_MAP NA 0 6 @@ -15374,7 +15169,7 @@ 0x20 - CORE1_LP_TIMER_REG_1_INT_MAP + CORE0_LP_TIMER_REG_1_INT_MAP NA 0 6 @@ -15389,7 +15184,7 @@ 0x20 - CORE1_MB_HP_INT_MAP + CORE0_MB_HP_INT_MAP NA 0 6 @@ -15404,7 +15199,7 @@ 0x20 - CORE1_MB_LP_INT_MAP + CORE0_MB_LP_INT_MAP NA 0 6 @@ -15419,7 +15214,7 @@ 0x20 - CORE1_PMU_REG_0_INT_MAP + CORE0_PMU_REG_0_INT_MAP NA 0 6 @@ -15434,7 +15229,7 @@ 0x20 - CORE1_PMU_REG_1_INT_MAP + CORE0_PMU_REG_1_INT_MAP NA 0 6 @@ -15449,7 +15244,7 @@ 0x20 - CORE1_LP_ANAPERI_INT_MAP + CORE0_LP_ANAPERI_INT_MAP NA 0 6 @@ -15464,7 +15259,7 @@ 0x20 - CORE1_LP_ADC_INT_MAP + CORE0_LP_ADC_INT_MAP NA 0 6 @@ -15479,7 +15274,7 @@ 0x20 - CORE1_LP_GPIO_INT_MAP + CORE0_LP_GPIO_INT_MAP NA 0 6 @@ -15494,7 +15289,7 @@ 0x20 - CORE1_LP_I2C_INT_MAP + CORE0_LP_I2C_INT_MAP NA 0 6 @@ -15509,7 +15304,7 @@ 0x20 - CORE1_LP_I2S_INT_MAP + CORE0_LP_I2S_INT_MAP NA 0 6 @@ -15524,7 +15319,7 @@ 0x20 - CORE1_LP_SPI_INT_MAP + CORE0_LP_SPI_INT_MAP NA 0 6 @@ -15539,7 +15334,7 @@ 0x20 - CORE1_LP_TOUCH_INT_MAP + CORE0_LP_TOUCH_INT_MAP NA 0 6 @@ -15554,7 +15349,7 @@ 0x20 - CORE1_LP_TSENS_INT_MAP + CORE0_LP_TSENS_INT_MAP NA 0 6 @@ -15569,7 +15364,7 @@ 0x20 - CORE1_LP_UART_INT_MAP + CORE0_LP_UART_INT_MAP NA 0 6 @@ -15584,7 +15379,7 @@ 0x20 - CORE1_LP_EFUSE_INT_MAP + CORE0_LP_EFUSE_INT_MAP NA 0 6 @@ -15599,7 +15394,7 @@ 0x20 - CORE1_LP_SW_INT_MAP + CORE0_LP_SW_INT_MAP NA 0 6 @@ -15614,7 +15409,7 @@ 0x20 - CORE1_LP_SYSREG_INT_MAP + CORE0_LP_SYSREG_INT_MAP NA 0 6 @@ -15629,7 +15424,7 @@ 0x20 - CORE1_LP_HUK_INT_MAP + CORE0_LP_HUK_INT_MAP NA 0 6 @@ -15644,7 +15439,7 @@ 0x20 - CORE1_SYS_ICM_INT_MAP + CORE0_SYS_ICM_INT_MAP NA 0 6 @@ -15659,7 +15454,7 @@ 0x20 - CORE1_USB_DEVICE_INT_MAP + CORE0_USB_DEVICE_INT_MAP NA 0 6 @@ -15674,7 +15469,7 @@ 0x20 - CORE1_SDIO_HOST_INT_MAP + CORE0_SDIO_HOST_INT_MAP NA 0 6 @@ -15689,7 +15484,7 @@ 0x20 - CORE1_GDMA_INT_MAP + CORE0_GDMA_INT_MAP NA 0 6 @@ -15704,7 +15499,7 @@ 0x20 - CORE1_SPI2_INT_MAP + CORE0_SPI2_INT_MAP NA 0 6 @@ -15719,7 +15514,7 @@ 0x20 - CORE1_SPI3_INT_MAP + CORE0_SPI3_INT_MAP NA 0 6 @@ -15734,7 +15529,7 @@ 0x20 - CORE1_I2S0_INT_MAP + CORE0_I2S0_INT_MAP NA 0 6 @@ -15749,7 +15544,7 @@ 0x20 - CORE1_I2S1_INT_MAP + CORE0_I2S1_INT_MAP NA 0 6 @@ -15764,7 +15559,7 @@ 0x20 - CORE1_I2S2_INT_MAP + CORE0_I2S2_INT_MAP NA 0 6 @@ -15779,7 +15574,7 @@ 0x20 - CORE1_UHCI0_INT_MAP + CORE0_UHCI0_INT_MAP NA 0 6 @@ -15794,7 +15589,7 @@ 0x20 - CORE1_UART0_INT_MAP + CORE0_UART0_INT_MAP NA 0 6 @@ -15809,7 +15604,7 @@ 0x20 - CORE1_UART1_INT_MAP + CORE0_UART1_INT_MAP NA 0 6 @@ -15824,7 +15619,7 @@ 0x20 - CORE1_UART2_INT_MAP + CORE0_UART2_INT_MAP NA 0 6 @@ -15839,7 +15634,7 @@ 0x20 - CORE1_UART3_INT_MAP + CORE0_UART3_INT_MAP NA 0 6 @@ -15854,7 +15649,7 @@ 0x20 - CORE1_UART4_INT_MAP + CORE0_UART4_INT_MAP NA 0 6 @@ -15869,7 +15664,7 @@ 0x20 - CORE1_LCD_CAM_INT_MAP + CORE0_LCD_CAM_INT_MAP NA 0 6 @@ -15884,7 +15679,7 @@ 0x20 - CORE1_ADC_INT_MAP + CORE0_ADC_INT_MAP NA 0 6 @@ -15899,7 +15694,7 @@ 0x20 - CORE1_PWM0_INT_MAP + CORE0_PWM0_INT_MAP NA 0 6 @@ -15914,7 +15709,7 @@ 0x20 - CORE1_PWM1_INT_MAP + CORE0_PWM1_INT_MAP NA 0 6 @@ -15929,7 +15724,7 @@ 0x20 - CORE1_CAN0_INT_MAP + CORE0_CAN0_INT_MAP NA 0 6 @@ -15944,7 +15739,7 @@ 0x20 - CORE1_CAN1_INT_MAP + CORE0_CAN1_INT_MAP NA 0 6 @@ -15959,7 +15754,7 @@ 0x20 - CORE1_CAN2_INT_MAP + CORE0_CAN2_INT_MAP NA 0 6 @@ -15974,7 +15769,7 @@ 0x20 - CORE1_RMT_INT_MAP + CORE0_RMT_INT_MAP NA 0 6 @@ -15989,7 +15784,7 @@ 0x20 - CORE1_I2C0_INT_MAP + CORE0_I2C0_INT_MAP NA 0 6 @@ -16004,7 +15799,7 @@ 0x20 - CORE1_I2C1_INT_MAP + CORE0_I2C1_INT_MAP NA 0 6 @@ -16019,7 +15814,7 @@ 0x20 - CORE1_TIMERGRP0_T0_INT_MAP + CORE0_TIMERGRP0_T0_INT_MAP NA 0 6 @@ -16034,7 +15829,7 @@ 0x20 - CORE1_TIMERGRP0_T1_INT_MAP + CORE0_TIMERGRP0_T1_INT_MAP NA 0 6 @@ -16049,7 +15844,7 @@ 0x20 - CORE1_TIMERGRP0_WDT_INT_MAP + CORE0_TIMERGRP0_WDT_INT_MAP NA 0 6 @@ -16064,7 +15859,7 @@ 0x20 - CORE1_TIMERGRP1_T0_INT_MAP + CORE0_TIMERGRP1_T0_INT_MAP NA 0 6 @@ -16079,7 +15874,7 @@ 0x20 - CORE1_TIMERGRP1_T1_INT_MAP + CORE0_TIMERGRP1_T1_INT_MAP NA 0 6 @@ -16094,7 +15889,7 @@ 0x20 - CORE1_TIMERGRP1_WDT_INT_MAP + CORE0_TIMERGRP1_WDT_INT_MAP NA 0 6 @@ -16109,7 +15904,7 @@ 0x20 - CORE1_LEDC_INT_MAP + CORE0_LEDC_INT_MAP NA 0 6 @@ -16124,7 +15919,7 @@ 0x20 - CORE1_SYSTIMER_TARGET0_INT_MAP + CORE0_SYSTIMER_TARGET0_INT_MAP NA 0 6 @@ -16139,7 +15934,7 @@ 0x20 - CORE1_SYSTIMER_TARGET1_INT_MAP + CORE0_SYSTIMER_TARGET1_INT_MAP NA 0 6 @@ -16154,7 +15949,7 @@ 0x20 - CORE1_SYSTIMER_TARGET2_INT_MAP + CORE0_SYSTIMER_TARGET2_INT_MAP NA 0 6 @@ -16169,7 +15964,7 @@ 0x20 - CORE1_AHB_PDMA_IN_CH0_INT_MAP + CORE0_AHB_PDMA_IN_CH0_INT_MAP NA 0 6 @@ -16184,7 +15979,7 @@ 0x20 - CORE1_AHB_PDMA_IN_CH1_INT_MAP + CORE0_AHB_PDMA_IN_CH1_INT_MAP NA 0 6 @@ -16199,7 +15994,7 @@ 0x20 - CORE1_AHB_PDMA_IN_CH2_INT_MAP + CORE0_AHB_PDMA_IN_CH2_INT_MAP NA 0 6 @@ -16214,7 +16009,7 @@ 0x20 - CORE1_AHB_PDMA_OUT_CH0_INT_MAP + CORE0_AHB_PDMA_OUT_CH0_INT_MAP NA 0 6 @@ -16229,7 +16024,7 @@ 0x20 - CORE1_AHB_PDMA_OUT_CH1_INT_MAP + CORE0_AHB_PDMA_OUT_CH1_INT_MAP NA 0 6 @@ -16244,7 +16039,7 @@ 0x20 - CORE1_AHB_PDMA_OUT_CH2_INT_MAP + CORE0_AHB_PDMA_OUT_CH2_INT_MAP NA 0 6 @@ -16259,7 +16054,7 @@ 0x20 - CORE1_AXI_PDMA_IN_CH0_INT_MAP + CORE0_AXI_PDMA_IN_CH0_INT_MAP NA 0 6 @@ -16274,7 +16069,7 @@ 0x20 - CORE1_AXI_PDMA_IN_CH1_INT_MAP + CORE0_AXI_PDMA_IN_CH1_INT_MAP NA 0 6 @@ -16289,7 +16084,7 @@ 0x20 - CORE1_AXI_PDMA_IN_CH2_INT_MAP + CORE0_AXI_PDMA_IN_CH2_INT_MAP NA 0 6 @@ -16304,7 +16099,7 @@ 0x20 - CORE1_AXI_PDMA_OUT_CH0_INT_MAP + CORE0_AXI_PDMA_OUT_CH0_INT_MAP NA 0 6 @@ -16319,7 +16114,7 @@ 0x20 - CORE1_AXI_PDMA_OUT_CH1_INT_MAP + CORE0_AXI_PDMA_OUT_CH1_INT_MAP NA 0 6 @@ -16334,7 +16129,7 @@ 0x20 - CORE1_AXI_PDMA_OUT_CH2_INT_MAP + CORE0_AXI_PDMA_OUT_CH2_INT_MAP NA 0 6 @@ -16349,7 +16144,7 @@ 0x20 - CORE1_RSA_INT_MAP + CORE0_RSA_INT_MAP NA 0 6 @@ -16364,7 +16159,7 @@ 0x20 - CORE1_AES_INT_MAP + CORE0_AES_INT_MAP NA 0 6 @@ -16379,7 +16174,7 @@ 0x20 - CORE1_SHA_INT_MAP + CORE0_SHA_INT_MAP NA 0 6 @@ -16394,7 +16189,7 @@ 0x20 - CORE1_ECC_INT_MAP + CORE0_ECC_INT_MAP NA 0 6 @@ -16409,7 +16204,7 @@ 0x20 - CORE1_ECDSA_INT_MAP + CORE0_ECDSA_INT_MAP NA 0 6 @@ -16424,7 +16219,7 @@ 0x20 - CORE1_KM_INT_MAP + CORE0_KM_INT_MAP NA 0 6 @@ -16439,7 +16234,7 @@ 0x20 - CORE1_GPIO_INT0_MAP + CORE0_GPIO_INT0_MAP NA 0 6 @@ -16454,7 +16249,7 @@ 0x20 - CORE1_GPIO_INT1_MAP + CORE0_GPIO_INT1_MAP NA 0 6 @@ -16469,7 +16264,7 @@ 0x20 - CORE1_GPIO_INT2_MAP + CORE0_GPIO_INT2_MAP NA 0 6 @@ -16484,7 +16279,7 @@ 0x20 - CORE1_GPIO_INT3_MAP + CORE0_GPIO_INT3_MAP NA 0 6 @@ -16499,7 +16294,7 @@ 0x20 - CORE1_GPIO_PAD_COMP_INT_MAP + CORE0_GPIO_PAD_COMP_INT_MAP NA 0 6 @@ -16514,7 +16309,7 @@ 0x20 - CORE1_CPU_INT_FROM_CPU_0_MAP + CORE0_CPU_INT_FROM_CPU_0_MAP NA 0 6 @@ -16529,7 +16324,7 @@ 0x20 - CORE1_CPU_INT_FROM_CPU_1_MAP + CORE0_CPU_INT_FROM_CPU_1_MAP NA 0 6 @@ -16544,7 +16339,7 @@ 0x20 - CORE1_CPU_INT_FROM_CPU_2_MAP + CORE0_CPU_INT_FROM_CPU_2_MAP NA 0 6 @@ -16559,7 +16354,7 @@ 0x20 - CORE1_CPU_INT_FROM_CPU_3_MAP + CORE0_CPU_INT_FROM_CPU_3_MAP NA 0 6 @@ -16574,7 +16369,7 @@ 0x20 - CORE1_CACHE_INT_MAP + CORE0_CACHE_INT_MAP NA 0 6 @@ -16589,7 +16384,7 @@ 0x20 - CORE1_FLASH_MSPI_INT_MAP + CORE0_FLASH_MSPI_INT_MAP NA 0 6 @@ -16604,7 +16399,7 @@ 0x20 - CORE1_CSI_BRIDGE_INT_MAP + CORE0_CSI_BRIDGE_INT_MAP NA 0 6 @@ -16619,7 +16414,7 @@ 0x20 - CORE1_DSI_BRIDGE_INT_MAP + CORE0_DSI_BRIDGE_INT_MAP NA 0 6 @@ -16634,7 +16429,7 @@ 0x20 - CORE1_CSI_INT_MAP + CORE0_CSI_INT_MAP NA 0 6 @@ -16649,7 +16444,7 @@ 0x20 - CORE1_DSI_INT_MAP + CORE0_DSI_INT_MAP NA 0 6 @@ -16664,7 +16459,7 @@ 0x20 - CORE1_GMII_PHY_INT_MAP + CORE0_GMII_PHY_INT_MAP NA 0 6 @@ -16679,7 +16474,7 @@ 0x20 - CORE1_LPI_INT_MAP + CORE0_LPI_INT_MAP NA 0 6 @@ -16694,7 +16489,7 @@ 0x20 - CORE1_PMT_INT_MAP + CORE0_PMT_INT_MAP NA 0 6 @@ -16709,7 +16504,7 @@ 0x20 - CORE1_SBD_INT_MAP + CORE0_SBD_INT_MAP NA 0 6 @@ -16724,7 +16519,7 @@ 0x20 - CORE1_USB_OTG_INT_MAP + CORE0_USB_OTG_INT_MAP NA 0 6 @@ -16739,7 +16534,7 @@ 0x20 - CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP + CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP NA 0 6 @@ -16754,7 +16549,7 @@ 0x20 - CORE1_JPEG_INT_MAP + CORE0_JPEG_INT_MAP NA 0 6 @@ -16769,7 +16564,7 @@ 0x20 - CORE1_PPA_INT_MAP + CORE0_PPA_INT_MAP NA 0 6 @@ -16784,7 +16579,7 @@ 0x20 - CORE1_CORE0_TRACE_INT_MAP + CORE0_CORE0_TRACE_INT_MAP NA 0 6 @@ -16799,7 +16594,7 @@ 0x20 - CORE1_CORE1_TRACE_INT_MAP + CORE0_CORE1_TRACE_INT_MAP NA 0 6 @@ -16814,7 +16609,7 @@ 0x20 - CORE1_HP_CORE_CTRL_INT_MAP + CORE0_HP_CORE_CTRL_INT_MAP NA 0 6 @@ -16829,7 +16624,7 @@ 0x20 - CORE1_ISP_INT_MAP + CORE0_ISP_INT_MAP NA 0 6 @@ -16844,7 +16639,7 @@ 0x20 - CORE1_I3C_MST_INT_MAP + CORE0_I3C_MST_INT_MAP NA 0 6 @@ -16859,7 +16654,7 @@ 0x20 - CORE1_I3C_SLV_INT_MAP + CORE0_I3C_SLV_INT_MAP NA 0 6 @@ -16874,7 +16669,7 @@ 0x20 - CORE1_USB_OTG11_INT_MAP + CORE0_USB_OTG11_INT_MAP NA 0 6 @@ -16889,7 +16684,7 @@ 0x20 - CORE1_DMA2D_IN_CH0_INT_MAP + CORE0_DMA2D_IN_CH0_INT_MAP NA 0 6 @@ -16904,7 +16699,7 @@ 0x20 - CORE1_DMA2D_IN_CH1_INT_MAP + CORE0_DMA2D_IN_CH1_INT_MAP NA 0 6 @@ -16919,7 +16714,7 @@ 0x20 - CORE1_DMA2D_OUT_CH0_INT_MAP + CORE0_DMA2D_OUT_CH0_INT_MAP NA 0 6 @@ -16934,7 +16729,7 @@ 0x20 - CORE1_DMA2D_OUT_CH1_INT_MAP + CORE0_DMA2D_OUT_CH1_INT_MAP NA 0 6 @@ -16949,7 +16744,7 @@ 0x20 - CORE1_DMA2D_OUT_CH2_INT_MAP + CORE0_DMA2D_OUT_CH2_INT_MAP NA 0 6 @@ -16964,7 +16759,7 @@ 0x20 - CORE1_PSRAM_MSPI_INT_MAP + CORE0_PSRAM_MSPI_INT_MAP NA 0 6 @@ -16979,7 +16774,7 @@ 0x20 - CORE1_HP_SYSREG_INT_MAP + CORE0_HP_SYSREG_INT_MAP NA 0 6 @@ -16994,7 +16789,7 @@ 0x20 - CORE1_PCNT_INT_MAP + CORE0_PCNT_INT_MAP NA 0 6 @@ -17009,7 +16804,7 @@ 0x20 - CORE1_HP_PAU_INT_MAP + CORE0_HP_PAU_INT_MAP NA 0 6 @@ -17024,7 +16819,7 @@ 0x20 - CORE1_HP_PARLIO_RX_INT_MAP + CORE0_HP_PARLIO_RX_INT_MAP NA 0 6 @@ -17039,7 +16834,7 @@ 0x20 - CORE1_HP_PARLIO_TX_INT_MAP + CORE0_HP_PARLIO_TX_INT_MAP NA 0 6 @@ -17054,7 +16849,7 @@ 0x20 - CORE1_H264_DMA2D_OUT_CH0_INT_MAP + CORE0_H264_DMA2D_OUT_CH0_INT_MAP NA 0 6 @@ -17069,7 +16864,7 @@ 0x20 - CORE1_H264_DMA2D_OUT_CH1_INT_MAP + CORE0_H264_DMA2D_OUT_CH1_INT_MAP NA 0 6 @@ -17084,7 +16879,7 @@ 0x20 - CORE1_H264_DMA2D_OUT_CH2_INT_MAP + CORE0_H264_DMA2D_OUT_CH2_INT_MAP NA 0 6 @@ -17099,7 +16894,7 @@ 0x20 - CORE1_H264_DMA2D_OUT_CH3_INT_MAP + CORE0_H264_DMA2D_OUT_CH3_INT_MAP NA 0 6 @@ -17114,7 +16909,7 @@ 0x20 - CORE1_H264_DMA2D_OUT_CH4_INT_MAP + CORE0_H264_DMA2D_OUT_CH4_INT_MAP NA 0 6 @@ -17129,7 +16924,7 @@ 0x20 - CORE1_H264_DMA2D_IN_CH0_INT_MAP + CORE0_H264_DMA2D_IN_CH0_INT_MAP NA 0 6 @@ -17144,7 +16939,7 @@ 0x20 - CORE1_H264_DMA2D_IN_CH1_INT_MAP + CORE0_H264_DMA2D_IN_CH1_INT_MAP NA 0 6 @@ -17159,7 +16954,7 @@ 0x20 - CORE1_H264_DMA2D_IN_CH2_INT_MAP + CORE0_H264_DMA2D_IN_CH2_INT_MAP NA 0 6 @@ -17174,7 +16969,7 @@ 0x20 - CORE1_H264_DMA2D_IN_CH3_INT_MAP + CORE0_H264_DMA2D_IN_CH3_INT_MAP NA 0 6 @@ -17189,7 +16984,7 @@ 0x20 - CORE1_H264_DMA2D_IN_CH4_INT_MAP + CORE0_H264_DMA2D_IN_CH4_INT_MAP NA 0 6 @@ -17204,7 +16999,7 @@ 0x20 - CORE1_H264_DMA2D_IN_CH5_INT_MAP + CORE0_H264_DMA2D_IN_CH5_INT_MAP NA 0 6 @@ -17219,7 +17014,7 @@ 0x20 - CORE1_H264_REG_INT_MAP + CORE0_H264_REG_INT_MAP NA 0 6 @@ -17234,7 +17029,7 @@ 0x20 - CORE1_ASSIST_DEBUG_INT_MAP + CORE0_ASSIST_DEBUG_INT_MAP NA 0 6 @@ -17249,7 +17044,7 @@ 0x20 - CORE1_INTR_STATUS_0 + CORE0_INTR_STATUS_0 NA 0 32 @@ -17264,7 +17059,7 @@ 0x20 - CORE1_INTR_STATUS_1 + CORE0_INTR_STATUS_1 NA 0 32 @@ -17279,7 +17074,7 @@ 0x20 - CORE1_INTR_STATUS_2 + CORE0_INTR_STATUS_2 NA 0 32 @@ -17294,7 +17089,7 @@ 0x20 - CORE1_INTR_STATUS_3 + CORE0_INTR_STATUS_3 NA 0 32 @@ -17310,7 +17105,7 @@ 0x00000001 - CORE1_REG_CLK_EN + CORE0_REG_CLK_EN NA 0 1 @@ -17326,7 +17121,7 @@ 0x02003020 - CORE1_INTERRUPT_REG_DATE + CORE0_INTERRUPT_REG_DATE NA 0 28 @@ -17337,2269 +17132,3214 @@ - MIPI_CSI_BRIDGE - MIPI Camera Interface Bridge - CSI_BRIG - 0x5009F800 + INTERRUPT_CORE1 + Interrupt Controller (Core 1) + CORE1 + 0x500D6800 0x0 - 0x48 + 0x218 registers - - CSI_BRIDGE - 85 - - CLK_EN - csi bridge register mapping unit clock gating. + LP_RTC_INT_MAP + NA 0x0 0x20 - CLK_EN - 0: enable clock gating. 1: disable clock gating, clock always on. + CORE1_LP_RTC_INT_MAP + NA 0 - 1 + 6 read-write - CSI_EN - csi bridge enable. + LP_WDT_INT_MAP + NA 0x4 0x20 - CSI_BRIG_EN - 0: disable csi bridge. 1: enable csi bridge. + CORE1_LP_WDT_INT_MAP + NA 0 - 1 + 6 read-write - DMA_REQ_CFG - dma request configuration. + LP_TIMER_REG_0_INT_MAP + NA 0x8 0x20 - 0x00000080 - DMA_BURST_LEN - DMA burst length. + CORE1_LP_TIMER_REG_0_INT_MAP + NA 0 - 12 - read-write - - - DMA_CFG_UPD_BY_BLK - 1: reg_dma_burst_len & reg_dma_burst_len will be updated by dma block finish. 0: updated by frame. - 12 - 1 - read-write - - - DMA_FORCE_RD_STATUS - 1: mask dma request when reading frame info. 0: disable mask. - 16 - 1 + 6 read-write - BUF_FLOW_CTL - csi bridge buffer control. + LP_TIMER_REG_1_INT_MAP + NA 0xC 0x20 - 0x000007F8 - CSI_BUF_AFULL_THRD - buffer almost full threshold. + CORE1_LP_TIMER_REG_1_INT_MAP + NA 0 - 14 + 6 read-write - - CSI_BUF_DEPTH - buffer data count. - 16 - 14 - read-only - - DATA_TYPE_CFG - pixel data type configuration. + MB_HP_INT_MAP + NA 0x10 0x20 - 0x00002F18 - DATA_TYPE_MIN - the min value of data type used for pixel filter. + CORE1_MB_HP_INT_MAP + NA 0 6 read-write - - DATA_TYPE_MAX - the max value of data type used for pixel filter. - 8 - 6 - read-write - - FRAME_CFG - frame configuration. + MB_LP_INT_MAP + NA 0x14 0x20 - 0x011E01E0 - VADR_NUM - vadr of frame data. - 0 - 12 - read-write - - - HADR_NUM - hadr of frame data. - 12 - 12 - read-write - - - HAS_HSYNC_E - 0: frame data doesn't contain hsync. 1: frame data contains hsync. - 24 - 1 - read-write - - - VADR_NUM_CHECK - 0: disable vadr check. 1: enable vadr check. - 25 - 1 + CORE1_MB_LP_INT_MAP + NA + 0 + 6 read-write - ENDIAN_MODE - data endianness order configuration. + PMU_REG_0_INT_MAP + NA 0x18 0x20 - BYTE_ENDIAN_ORDER - endianness order in bytes. 2'h0 is normal mode and 2'h3 is useful to YUV420(Legacy) when isp is bapassed. + CORE1_PMU_REG_0_INT_MAP + NA 0 - 1 - read-write - - - BIT_ENDIAN_ORDER - N/A - 1 - 1 + 6 read-write - INT_RAW - csi bridge interrupt raw. + PMU_REG_1_INT_MAP + NA 0x1C 0x20 - VADR_NUM_GT_INT_RAW - reg_vadr_num is greater than real interrupt raw. + CORE1_PMU_REG_1_INT_MAP + NA 0 - 1 - read-write - - - VADR_NUM_LT_INT_RAW - reg_vadr_num is less than real interrupt raw. - 1 - 1 - read-write - - - DISCARD_INT_RAW - an incomplete frame of data was sent interrupt raw. - 2 - 1 - read-write - - - CSI_BUF_OVERRUN_INT_RAW - buffer overrun interrupt raw. - 3 - 1 - read-write - - - CSI_ASYNC_FIFO_OVF_INT_RAW - buffer overflow interrupt raw. - 4 - 1 - read-write - - - DMA_CFG_HAS_UPDATED_INT_RAW - dma configuration update complete interrupt raw. - 5 - 1 + 6 read-write - INT_CLR - csi bridge interrupt clr. + LP_ANAPERI_INT_MAP + NA 0x20 0x20 - VADR_NUM_GT_REAL_INT_CLR - reg_vadr_num is greater than real interrupt clr. + CORE1_LP_ANAPERI_INT_MAP + NA 0 - 1 - write-only - - - VADR_NUM_LT_REAL_INT_CLR - reg_vadr_num is less than real interrupt clr. - 1 - 1 - write-only - - - DISCARD_INT_CLR - an incomplete frame of data was sent interrupt clr. - 2 - 1 - write-only - - - CSI_BUF_OVERRUN_INT_CLR - buffer overrun interrupt clr. - 3 - 1 - write-only - - - CSI_ASYNC_FIFO_OVF_INT_CLR - buffer overflow interrupt clr. - 4 - 1 - write-only - - - DMA_CFG_HAS_UPDATED_INT_CLR - dma configuration update complete interrupt clr. - 5 - 1 - write-only + 6 + read-write - INT_ST - csi bridge interrupt st. + LP_ADC_INT_MAP + NA 0x24 0x20 - VADR_NUM_GT_INT_ST - reg_vadr_num is greater than real interrupt st. + CORE1_LP_ADC_INT_MAP + NA 0 - 1 - read-only - - - VADR_NUM_LT_INT_ST - reg_vadr_num is less than real interrupt st. - 1 - 1 - read-only - - - DISCARD_INT_ST - an incomplete frame of data was sent interrupt st. - 2 - 1 - read-only - - - CSI_BUF_OVERRUN_INT_ST - buffer overrun interrupt st. - 3 - 1 - read-only - - - CSI_ASYNC_FIFO_OVF_INT_ST - buffer overflow interrupt st. - 4 - 1 - read-only - - - DMA_CFG_HAS_UPDATED_INT_ST - dma configuration update complete interrupt st. - 5 - 1 - read-only + 6 + read-write - INT_ENA - csi bridge interrupt enable. + LP_GPIO_INT_MAP + NA 0x28 0x20 - VADR_NUM_GT_INT_ENA - reg_vadr_num is greater than real interrupt enable. + CORE1_LP_GPIO_INT_MAP + NA 0 - 1 - read-write - - - VADR_NUM_LT_INT_ENA - reg_vadr_num is less than real interrupt enable. - 1 - 1 - read-write - - - DISCARD_INT_ENA - an incomplete frame of data was sent interrupt enable. - 2 - 1 - read-write - - - CSI_BUF_OVERRUN_INT_ENA - buffer overrun interrupt enable. - 3 - 1 - read-write - - - CSI_ASYNC_FIFO_OVF_INT_ENA - buffer overflow interrupt enable. - 4 - 1 - read-write - - - DMA_CFG_HAS_UPDATED_INT_ENA - dma configuration update complete interrupt enable. - 5 - 1 + 6 read-write - DMA_REQ_INTERVAL - DMA interval configuration. + LP_I2C_INT_MAP + NA 0x2C 0x20 - 0x00000001 - DMA_REQ_INTERVAL - 16'b1: 1 cycle. 16'b11: 2 cycle. ... ... 16'hFFFF: 16 cycle. + CORE1_LP_I2C_INT_MAP + NA 0 - 16 + 6 read-write - DMABLK_SIZE - DMA block size configuration. + LP_I2S_INT_MAP + NA 0x30 0x20 - 0x00001FFF - DMABLK_SIZE - the number of reg_dma_burst_len in a block + CORE1_LP_I2S_INT_MAP + NA 0 - 13 + 6 read-write - RDN_ECO_CS - N/A + LP_SPI_INT_MAP + NA 0x34 0x20 - RDN_ECO_EN - N/A + CORE1_LP_SPI_INT_MAP + NA 0 - 1 + 6 read-write - - RDN_ECO_RESULT - N/A - 1 - 1 - read-only - - RDN_ECO_LOW - N/A + LP_TOUCH_INT_MAP + NA 0x38 0x20 - RDN_ECO_LOW - N/A + CORE1_LP_TOUCH_INT_MAP + NA 0 - 32 + 6 read-write - RDN_ECO_HIGH - N/A + LP_TSENS_INT_MAP + NA 0x3C 0x20 - 0xFFFFFFFF - RDN_ECO_HIGH - N/A + CORE1_LP_TSENS_INT_MAP + NA 0 - 32 + 6 read-write - HOST_CTRL - csi host control by csi bridge. + LP_UART_INT_MAP + NA 0x40 0x20 - 0x00000003 - CSI_ENABLECLK - enable clock lane module of csi phy. + CORE1_LP_UART_INT_MAP + NA 0 - 1 - read-write - - - CSI_CFG_CLK_EN - enable cfg_clk of csi host module. - 1 - 1 - read-write - - - LOOPBK_TEST_EN - for phy test by loopback dsi phy to csi phy. - 2 - 1 + 6 read-write - MEM_CTRL - csi bridge buffer control. + LP_EFUSE_INT_MAP + NA 0x44 0x20 - 0x00002640 - CSI_BRIDGE_MEM_CLK_FORCE_ON - csi bridge memory clock gating force on. + CORE1_LP_EFUSE_INT_MAP + NA 0 - 1 + 6 read-write + + + + LP_SW_INT_MAP + NA + 0x48 + 0x20 + - CSI_MEM_AUX_CTRL - N/A - 1 - 14 + CORE1_LP_SW_INT_MAP + NA + 0 + 6 read-write - - - - MIPI_CSI_HOST - MIPI Camera Interface Host - CSI_HOST - 0x5009F000 - - 0x0 - 0xA8 - registers - - - CSI - 87 - - - VERSION + LP_SYSREG_INT_MAP NA - 0x0 + 0x4C 0x20 - 0x3135302A - VERSION + CORE1_LP_SYSREG_INT_MAP NA 0 - 32 - read-only + 6 + read-write - N_LANES + LP_HUK_INT_MAP NA - 0x4 + 0x50 0x20 - 0x00000001 - N_LANES + CORE1_LP_HUK_INT_MAP NA 0 - 3 + 6 read-write - CSI2_RESETN + SYS_ICM_INT_MAP NA - 0x8 + 0x54 0x20 - CSI2_RESETN + CORE1_SYS_ICM_INT_MAP NA 0 - 1 + 6 read-write - INT_ST_MAIN + USB_DEVICE_INT_MAP NA - 0xC + 0x58 0x20 - ST_STATUS_INT_PHY_FATAL + CORE1_USB_DEVICE_INT_MAP NA 0 - 1 - read-only + 6 + read-write + + + + SDIO_HOST_INT_MAP + NA + 0x5C + 0x20 + - ST_STATUS_INT_PKT_FATAL + CORE1_SDIO_HOST_INT_MAP NA - 1 - 1 - read-only + 0 + 6 + read-write + + + + GDMA_INT_MAP + NA + 0x60 + 0x20 + - ST_STATUS_INT_BNDRY_FRAME_FATAL + CORE1_GDMA_INT_MAP NA - 2 - 1 - read-only + 0 + 6 + read-write + + + + SPI2_INT_MAP + NA + 0x64 + 0x20 + - ST_STATUS_INT_SEQ_FRAME_FATAL + CORE1_SPI2_INT_MAP NA - 3 - 1 - read-only + 0 + 6 + read-write + + + + SPI3_INT_MAP + NA + 0x68 + 0x20 + - ST_STATUS_INT_CRC_FRAME_FATAL + CORE1_SPI3_INT_MAP NA - 4 - 1 - read-only + 0 + 6 + read-write + + + + I2S0_INT_MAP + NA + 0x6C + 0x20 + - ST_STATUS_INT_PLD_CRC_FATAL + CORE1_I2S0_INT_MAP NA - 5 - 1 - read-only + 0 + 6 + read-write + + + + I2S1_INT_MAP + NA + 0x70 + 0x20 + - ST_STATUS_INT_DATA_ID + CORE1_I2S1_INT_MAP NA - 6 - 1 - read-only + 0 + 6 + read-write + + + + I2S2_INT_MAP + NA + 0x74 + 0x20 + - ST_STATUS_INT_ECC_CORRECTED + CORE1_I2S2_INT_MAP NA - 7 - 1 - read-only + 0 + 6 + read-write + + + + UHCI0_INT_MAP + NA + 0x78 + 0x20 + - ST_STATUS_INT_PHY + CORE1_UHCI0_INT_MAP NA - 16 - 1 - read-only + 0 + 6 + read-write - PHY_SHUTDOWNZ + UART0_INT_MAP NA - 0x40 + 0x7C 0x20 - PHY_SHUTDOWNZ + CORE1_UART0_INT_MAP NA 0 - 1 + 6 read-write - DPHY_RSTZ + UART1_INT_MAP NA - 0x44 + 0x80 0x20 - DPHY_RSTZ + CORE1_UART1_INT_MAP NA 0 - 1 + 6 read-write - PHY_RX + UART2_INT_MAP NA - 0x48 + 0x84 0x20 - 0x00010000 - PHY_RXULPSESC_0 + CORE1_UART2_INT_MAP NA 0 - 1 - read-only + 6 + read-write + + + + UART3_INT_MAP + NA + 0x88 + 0x20 + - PHY_RXULPSESC_1 + CORE1_UART3_INT_MAP NA - 1 - 1 - read-only + 0 + 6 + read-write + + + + UART4_INT_MAP + NA + 0x8C + 0x20 + - PHY_RXULPSCLKNOT + CORE1_UART4_INT_MAP NA - 16 - 1 - read-only + 0 + 6 + read-write + + + + LCD_CAM_INT_MAP + NA + 0x90 + 0x20 + - PHY_RXCLKACTIVEHS + CORE1_LCD_CAM_INT_MAP NA - 17 - 1 - read-only + 0 + 6 + read-write - PHY_STOPSTATE + ADC_INT_MAP NA - 0x4C + 0x94 0x20 - PHY_STOPSTATEDATA_0 + CORE1_ADC_INT_MAP NA 0 - 1 - read-only + 6 + read-write + + + + PWM0_INT_MAP + NA + 0x98 + 0x20 + - PHY_STOPSTATEDATA_1 + CORE1_PWM0_INT_MAP NA - 1 - 1 - read-only + 0 + 6 + read-write + + + + PWM1_INT_MAP + NA + 0x9C + 0x20 + - PHY_STOPSTATECLK + CORE1_PWM1_INT_MAP NA - 16 - 1 - read-only + 0 + 6 + read-write - PHY_TEST_CTRL0 + CAN0_INT_MAP NA - 0x50 + 0xA0 0x20 - 0x00000001 - PHY_TESTCLR + CORE1_CAN0_INT_MAP NA 0 - 1 + 6 read-write + + + + CAN1_INT_MAP + NA + 0xA4 + 0x20 + - PHY_TESTCLK + CORE1_CAN1_INT_MAP NA - 1 - 1 + 0 + 6 read-write - PHY_TEST_CTRL1 + CAN2_INT_MAP NA - 0x54 + 0xA8 0x20 - PHY_TESTDIN + CORE1_CAN2_INT_MAP NA 0 - 8 + 6 read-write + + + + RMT_INT_MAP + NA + 0xAC + 0x20 + - PHY_TESTDOUT + CORE1_RMT_INT_MAP NA - 8 - 8 - read-only + 0 + 6 + read-write + + + + I2C0_INT_MAP + NA + 0xB0 + 0x20 + - PHY_TESTEN + CORE1_I2C0_INT_MAP NA - 16 - 1 + 0 + 6 read-write - VC_EXTENSION + I2C1_INT_MAP NA - 0xC8 + 0xB4 0x20 - VCX + CORE1_I2C1_INT_MAP NA 0 - 1 + 6 read-write - PHY_CAL + TIMERGRP0_T0_INT_MAP NA - 0xCC + 0xB8 0x20 - RXSKEWCALHS + CORE1_TIMERGRP0_T0_INT_MAP NA 0 - 1 - read-only + 6 + read-write - INT_ST_PHY_FATAL + TIMERGRP0_T1_INT_MAP NA - 0xE0 + 0xBC 0x20 - ST_PHY_ERRSOTSYNCHS_0 + CORE1_TIMERGRP0_T1_INT_MAP NA 0 - 1 - read-only + 6 + read-write + + + + TIMERGRP0_WDT_INT_MAP + NA + 0xC0 + 0x20 + - ST_PHY_ERRSOTSYNCHS_1 + CORE1_TIMERGRP0_WDT_INT_MAP NA - 1 - 1 - read-only + 0 + 6 + read-write - INT_MSK_PHY_FATAL + TIMERGRP1_T0_INT_MAP NA - 0xE4 + 0xC4 0x20 - MASK_PHY_ERRSOTSYNCHS_0 + CORE1_TIMERGRP1_T0_INT_MAP NA 0 - 1 + 6 read-write + + + + TIMERGRP1_T1_INT_MAP + NA + 0xC8 + 0x20 + - MASK_PHY_ERRSOTSYNCHS_1 + CORE1_TIMERGRP1_T1_INT_MAP NA - 1 - 1 + 0 + 6 read-write - INT_FORCE_PHY_FATAL + TIMERGRP1_WDT_INT_MAP NA - 0xE8 + 0xCC 0x20 - FORCE_PHY_ERRSOTSYNCHS_0 + CORE1_TIMERGRP1_WDT_INT_MAP NA 0 - 1 + 6 read-write + + + + LEDC_INT_MAP + NA + 0xD0 + 0x20 + - FORCE_PHY_ERRSOTSYNCHS_1 + CORE1_LEDC_INT_MAP NA - 1 - 1 + 0 + 6 read-write - INT_ST_PKT_FATAL + SYSTIMER_TARGET0_INT_MAP NA - 0xF0 + 0xD4 0x20 - ST_ERR_ECC_DOUBLE + CORE1_SYSTIMER_TARGET0_INT_MAP NA 0 - 1 - read-only + 6 + read-write + + + + SYSTIMER_TARGET1_INT_MAP + NA + 0xD8 + 0x20 + - ST_SHORTER_PAYLOAD + CORE1_SYSTIMER_TARGET1_INT_MAP NA - 1 - 1 - read-only + 0 + 6 + read-write - INT_MSK_PKT_FATAL + SYSTIMER_TARGET2_INT_MAP NA - 0xF4 + 0xDC 0x20 - MASK_ERR_ECC_DOUBLE + CORE1_SYSTIMER_TARGET2_INT_MAP NA 0 - 1 + 6 read-write + + + + AHB_PDMA_IN_CH0_INT_MAP + NA + 0xE0 + 0x20 + - MASK_SHORTER_PAYLOAD + CORE1_AHB_PDMA_IN_CH0_INT_MAP NA - 1 - 1 + 0 + 6 read-write - INT_FORCE_PKT_FATAL + AHB_PDMA_IN_CH1_INT_MAP NA - 0xF8 + 0xE4 0x20 - FORCE_ERR_ECC_DOUBLE + CORE1_AHB_PDMA_IN_CH1_INT_MAP NA 0 - 1 + 6 read-write + + + + AHB_PDMA_IN_CH2_INT_MAP + NA + 0xE8 + 0x20 + - FORCE_SHORTER_PAYLOAD + CORE1_AHB_PDMA_IN_CH2_INT_MAP NA - 1 - 1 + 0 + 6 read-write - INT_ST_PHY + AHB_PDMA_OUT_CH0_INT_MAP NA - 0x110 + 0xEC 0x20 - ST_PHY_ERRSOTHS_0 + CORE1_AHB_PDMA_OUT_CH0_INT_MAP NA 0 - 1 - read-only + 6 + read-write + + + + AHB_PDMA_OUT_CH1_INT_MAP + NA + 0xF0 + 0x20 + - ST_PHY_ERRSOTHS_1 + CORE1_AHB_PDMA_OUT_CH1_INT_MAP NA - 1 - 1 - read-only + 0 + 6 + read-write + + + + AHB_PDMA_OUT_CH2_INT_MAP + NA + 0xF4 + 0x20 + - ST_PHY_ERRESC_0 + CORE1_AHB_PDMA_OUT_CH2_INT_MAP NA - 16 - 1 - read-only + 0 + 6 + read-write + + + + AXI_PDMA_IN_CH0_INT_MAP + NA + 0xF8 + 0x20 + - ST_PHY_ERRESC_1 + CORE1_AXI_PDMA_IN_CH0_INT_MAP NA - 17 - 1 - read-only + 0 + 6 + read-write - INT_MSK_PHY + AXI_PDMA_IN_CH1_INT_MAP NA - 0x114 + 0xFC 0x20 - MASK_PHY_ERRSOTHS_0 + CORE1_AXI_PDMA_IN_CH1_INT_MAP NA 0 - 1 + 6 read-write + + + + AXI_PDMA_IN_CH2_INT_MAP + NA + 0x100 + 0x20 + - MASK_PHY_ERRSOTHS_1 + CORE1_AXI_PDMA_IN_CH2_INT_MAP NA - 1 - 1 + 0 + 6 read-write + + + + AXI_PDMA_OUT_CH0_INT_MAP + NA + 0x104 + 0x20 + - MASK_PHY_ERRESC_0 + CORE1_AXI_PDMA_OUT_CH0_INT_MAP NA - 16 - 1 + 0 + 6 read-write + + + + AXI_PDMA_OUT_CH1_INT_MAP + NA + 0x108 + 0x20 + - MASK_PHY_ERRESC_1 + CORE1_AXI_PDMA_OUT_CH1_INT_MAP NA - 17 - 1 + 0 + 6 read-write - INT_FORCE_PHY + AXI_PDMA_OUT_CH2_INT_MAP NA - 0x118 + 0x10C 0x20 - FORCE_PHY_ERRSOTHS_0 + CORE1_AXI_PDMA_OUT_CH2_INT_MAP NA 0 - 1 + 6 read-write + + + + RSA_INT_MAP + NA + 0x110 + 0x20 + - FORCE_PHY_ERRSOTHS_1 + CORE1_RSA_INT_MAP NA - 1 - 1 + 0 + 6 read-write + + + + AES_INT_MAP + NA + 0x114 + 0x20 + - FORCE_PHY_ERRESC_0 + CORE1_AES_INT_MAP NA - 16 - 1 + 0 + 6 read-write + + + + SHA_INT_MAP + NA + 0x118 + 0x20 + - FORCE_PHY_ERRESC_1 + CORE1_SHA_INT_MAP NA - 17 - 1 + 0 + 6 read-write - INT_ST_BNDRY_FRAME_FATAL + ECC_INT_MAP NA - 0x280 + 0x11C 0x20 - ST_ERR_F_BNDRY_MATCH_VC0 + CORE1_ECC_INT_MAP NA 0 - 1 - read-only - - - ST_ERR_F_BNDRY_MATCH_VC1 - NA - 1 - 1 - read-only - - - ST_ERR_F_BNDRY_MATCH_VC2 - NA - 2 - 1 - read-only - - - ST_ERR_F_BNDRY_MATCH_VC3 - NA - 3 - 1 - read-only + 6 + read-write + + + + ECDSA_INT_MAP + NA + 0x120 + 0x20 + - ST_ERR_F_BNDRY_MATCH_VC4 + CORE1_ECDSA_INT_MAP NA - 4 - 1 - read-only + 0 + 6 + read-write + + + + KM_INT_MAP + NA + 0x124 + 0x20 + - ST_ERR_F_BNDRY_MATCH_VC5 + CORE1_KM_INT_MAP NA - 5 - 1 - read-only + 0 + 6 + read-write + + + + GPIO_INT0_MAP + NA + 0x128 + 0x20 + - ST_ERR_F_BNDRY_MATCH_VC6 + CORE1_GPIO_INT0_MAP NA - 6 - 1 - read-only + 0 + 6 + read-write + + + + GPIO_INT1_MAP + NA + 0x12C + 0x20 + - ST_ERR_F_BNDRY_MATCH_VC7 + CORE1_GPIO_INT1_MAP NA - 7 - 1 - read-only + 0 + 6 + read-write + + + + GPIO_INT2_MAP + NA + 0x130 + 0x20 + - ST_ERR_F_BNDRY_MATCH_VC8 + CORE1_GPIO_INT2_MAP NA - 8 - 1 - read-only + 0 + 6 + read-write + + + + GPIO_INT3_MAP + NA + 0x134 + 0x20 + - ST_ERR_F_BNDRY_MATCH_VC9 + CORE1_GPIO_INT3_MAP NA - 9 - 1 - read-only + 0 + 6 + read-write + + + + GPIO_PAD_COMP_INT_MAP + NA + 0x138 + 0x20 + - ST_ERR_F_BNDRY_MATCH_VC10 + CORE1_GPIO_PAD_COMP_INT_MAP NA - 10 - 1 - read-only + 0 + 6 + read-write + + + + CPU_INT_FROM_CPU_0_MAP + NA + 0x13C + 0x20 + - ST_ERR_F_BNDRY_MATCH_VC11 + CORE1_CPU_INT_FROM_CPU_0_MAP NA - 11 - 1 - read-only + 0 + 6 + read-write + + + + CPU_INT_FROM_CPU_1_MAP + NA + 0x140 + 0x20 + - ST_ERR_F_BNDRY_MATCH_VC12 + CORE1_CPU_INT_FROM_CPU_1_MAP NA - 12 - 1 - read-only + 0 + 6 + read-write + + + + CPU_INT_FROM_CPU_2_MAP + NA + 0x144 + 0x20 + - ST_ERR_F_BNDRY_MATCH_VC13 + CORE1_CPU_INT_FROM_CPU_2_MAP NA - 13 - 1 - read-only + 0 + 6 + read-write + + + + CPU_INT_FROM_CPU_3_MAP + NA + 0x148 + 0x20 + - ST_ERR_F_BNDRY_MATCH_VC14 + CORE1_CPU_INT_FROM_CPU_3_MAP NA - 14 - 1 - read-only + 0 + 6 + read-write + + + + CACHE_INT_MAP + NA + 0x14C + 0x20 + - ST_ERR_F_BNDRY_MATCH_VC15 + CORE1_CACHE_INT_MAP NA - 15 - 1 - read-only + 0 + 6 + read-write - INT_MSK_BNDRY_FRAME_FATAL + FLASH_MSPI_INT_MAP NA - 0x284 + 0x150 0x20 - MASK_ERR_F_BNDRY_MATCH_VC0 + CORE1_FLASH_MSPI_INT_MAP NA 0 - 1 + 6 read-write + + + + CSI_BRIDGE_INT_MAP + NA + 0x154 + 0x20 + - MASK_ERR_F_BNDRY_MATCH_VC1 + CORE1_CSI_BRIDGE_INT_MAP NA - 1 - 1 + 0 + 6 read-write + + + + DSI_BRIDGE_INT_MAP + NA + 0x158 + 0x20 + - MASK_ERR_F_BNDRY_MATCH_VC2 + CORE1_DSI_BRIDGE_INT_MAP NA - 2 - 1 + 0 + 6 read-write + + + + CSI_INT_MAP + NA + 0x15C + 0x20 + - MASK_ERR_F_BNDRY_MATCH_VC3 + CORE1_CSI_INT_MAP NA - 3 - 1 + 0 + 6 read-write + + + + DSI_INT_MAP + NA + 0x160 + 0x20 + - MASK_ERR_F_BNDRY_MATCH_VC4 + CORE1_DSI_INT_MAP NA - 4 - 1 + 0 + 6 read-write + + + + GMII_PHY_INT_MAP + NA + 0x164 + 0x20 + - MASK_ERR_F_BNDRY_MATCH_VC5 + CORE1_GMII_PHY_INT_MAP NA - 5 - 1 + 0 + 6 read-write + + + + LPI_INT_MAP + NA + 0x168 + 0x20 + - MASK_ERR_F_BNDRY_MATCH_VC6 + CORE1_LPI_INT_MAP NA - 6 - 1 + 0 + 6 read-write + + + + PMT_INT_MAP + NA + 0x16C + 0x20 + - MASK_ERR_F_BNDRY_MATCH_VC7 + CORE1_PMT_INT_MAP NA - 7 - 1 + 0 + 6 read-write + + + + SBD_INT_MAP + NA + 0x170 + 0x20 + - MASK_ERR_F_BNDRY_MATCH_VC8 + CORE1_SBD_INT_MAP NA - 8 - 1 + 0 + 6 read-write + + + + USB_OTG_INT_MAP + NA + 0x174 + 0x20 + - MASK_ERR_F_BNDRY_MATCH_VC9 + CORE1_USB_OTG_INT_MAP NA - 9 - 1 + 0 + 6 read-write + + + + USB_OTG_ENDP_MULTI_PROC_INT_MAP + NA + 0x178 + 0x20 + - MASK_ERR_F_BNDRY_MATCH_VC10 + CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP NA - 10 - 1 + 0 + 6 read-write + + + + JPEG_INT_MAP + NA + 0x17C + 0x20 + - MASK_ERR_F_BNDRY_MATCH_VC11 + CORE1_JPEG_INT_MAP NA - 11 - 1 + 0 + 6 read-write + + + + PPA_INT_MAP + NA + 0x180 + 0x20 + - MASK_ERR_F_BNDRY_MATCH_VC12 + CORE1_PPA_INT_MAP NA - 12 - 1 + 0 + 6 read-write + + + + CORE0_TRACE_INT_MAP + NA + 0x184 + 0x20 + - MASK_ERR_F_BNDRY_MATCH_VC13 + CORE1_CORE0_TRACE_INT_MAP NA - 13 - 1 + 0 + 6 read-write + + + + CORE1_TRACE_INT_MAP + NA + 0x188 + 0x20 + - MASK_ERR_F_BNDRY_MATCH_VC14 + CORE1_CORE1_TRACE_INT_MAP NA - 14 - 1 + 0 + 6 read-write + + + + HP_CORE_CTRL_INT_MAP + NA + 0x18C + 0x20 + - MASK_ERR_F_BNDRY_MATCH_VC15 + CORE1_HP_CORE_CTRL_INT_MAP NA - 15 - 1 + 0 + 6 read-write - INT_FORCE_BNDRY_FRAME_FATAL + ISP_INT_MAP NA - 0x288 + 0x190 0x20 - FORCE_ERR_F_BNDRY_MATCH_VC0 + CORE1_ISP_INT_MAP NA 0 - 1 + 6 read-write + + + + I3C_MST_INT_MAP + NA + 0x194 + 0x20 + - FORCE_ERR_F_BNDRY_MATCH_VC1 + CORE1_I3C_MST_INT_MAP NA - 1 - 1 + 0 + 6 read-write + + + + I3C_SLV_INT_MAP + NA + 0x198 + 0x20 + - FORCE_ERR_F_BNDRY_MATCH_VC2 + CORE1_I3C_SLV_INT_MAP NA - 2 - 1 + 0 + 6 read-write + + + + USB_OTG11_INT_MAP + NA + 0x19C + 0x20 + - FORCE_ERR_F_BNDRY_MATCH_VC3 + CORE1_USB_OTG11_INT_MAP NA - 3 - 1 + 0 + 6 read-write + + + + DMA2D_IN_CH0_INT_MAP + NA + 0x1A0 + 0x20 + - FORCE_ERR_F_BNDRY_MATCH_VC4 + CORE1_DMA2D_IN_CH0_INT_MAP NA - 4 - 1 + 0 + 6 read-write + + + + DMA2D_IN_CH1_INT_MAP + NA + 0x1A4 + 0x20 + - FORCE_ERR_F_BNDRY_MATCH_VC5 + CORE1_DMA2D_IN_CH1_INT_MAP NA - 5 - 1 + 0 + 6 read-write + + + + DMA2D_OUT_CH0_INT_MAP + NA + 0x1A8 + 0x20 + - FORCE_ERR_F_BNDRY_MATCH_VC6 + CORE1_DMA2D_OUT_CH0_INT_MAP NA - 6 - 1 + 0 + 6 read-write + + + + DMA2D_OUT_CH1_INT_MAP + NA + 0x1AC + 0x20 + - FORCE_ERR_F_BNDRY_MATCH_VC7 + CORE1_DMA2D_OUT_CH1_INT_MAP NA - 7 - 1 + 0 + 6 read-write + + + + DMA2D_OUT_CH2_INT_MAP + NA + 0x1B0 + 0x20 + - FORCE_ERR_F_BNDRY_MATCH_VC8 + CORE1_DMA2D_OUT_CH2_INT_MAP NA - 8 - 1 + 0 + 6 read-write + + + + PSRAM_MSPI_INT_MAP + NA + 0x1B4 + 0x20 + - FORCE_ERR_F_BNDRY_MATCH_VC9 + CORE1_PSRAM_MSPI_INT_MAP NA - 9 - 1 + 0 + 6 read-write + + + + HP_SYSREG_INT_MAP + NA + 0x1B8 + 0x20 + - FORCE_ERR_F_BNDRY_MATCH_VC10 + CORE1_HP_SYSREG_INT_MAP NA - 10 - 1 + 0 + 6 read-write + + + + PCNT_INT_MAP + NA + 0x1BC + 0x20 + - FORCE_ERR_F_BNDRY_MATCH_VC11 + CORE1_PCNT_INT_MAP NA - 11 - 1 + 0 + 6 read-write + + + + HP_PAU_INT_MAP + NA + 0x1C0 + 0x20 + - FORCE_ERR_F_BNDRY_MATCH_VC12 + CORE1_HP_PAU_INT_MAP NA - 12 - 1 + 0 + 6 read-write + + + + HP_PARLIO_RX_INT_MAP + NA + 0x1C4 + 0x20 + - FORCE_ERR_F_BNDRY_MATCH_VC13 + CORE1_HP_PARLIO_RX_INT_MAP NA - 13 - 1 + 0 + 6 read-write + + + + HP_PARLIO_TX_INT_MAP + NA + 0x1C8 + 0x20 + - FORCE_ERR_F_BNDRY_MATCH_VC14 + CORE1_HP_PARLIO_TX_INT_MAP NA - 14 - 1 + 0 + 6 read-write + + + + H264_DMA2D_OUT_CH0_INT_MAP + NA + 0x1CC + 0x20 + - FORCE_ERR_F_BNDRY_MATCH_VC15 + CORE1_H264_DMA2D_OUT_CH0_INT_MAP NA - 15 - 1 + 0 + 6 read-write - INT_ST_SEQ_FRAME_FATAL + H264_DMA2D_OUT_CH1_INT_MAP NA - 0x290 + 0x1D0 0x20 - ST_ERR_F_SEQ_VC0 + CORE1_H264_DMA2D_OUT_CH1_INT_MAP NA 0 - 1 - read-only + 6 + read-write + + + + H264_DMA2D_OUT_CH2_INT_MAP + NA + 0x1D4 + 0x20 + - ST_ERR_F_SEQ_VC1 + CORE1_H264_DMA2D_OUT_CH2_INT_MAP NA - 1 - 1 - read-only + 0 + 6 + read-write + + + + H264_DMA2D_OUT_CH3_INT_MAP + NA + 0x1D8 + 0x20 + - ST_ERR_F_SEQ_VC2 + CORE1_H264_DMA2D_OUT_CH3_INT_MAP NA - 2 - 1 - read-only + 0 + 6 + read-write + + + + H264_DMA2D_OUT_CH4_INT_MAP + NA + 0x1DC + 0x20 + - ST_ERR_F_SEQ_VC3 + CORE1_H264_DMA2D_OUT_CH4_INT_MAP NA - 3 - 1 - read-only + 0 + 6 + read-write + + + + H264_DMA2D_IN_CH0_INT_MAP + NA + 0x1E0 + 0x20 + - ST_ERR_F_SEQ_VC4 + CORE1_H264_DMA2D_IN_CH0_INT_MAP NA - 4 - 1 - read-only + 0 + 6 + read-write + + + + H264_DMA2D_IN_CH1_INT_MAP + NA + 0x1E4 + 0x20 + - ST_ERR_F_SEQ_VC5 + CORE1_H264_DMA2D_IN_CH1_INT_MAP NA - 5 - 1 - read-only + 0 + 6 + read-write + + + + H264_DMA2D_IN_CH2_INT_MAP + NA + 0x1E8 + 0x20 + - ST_ERR_F_SEQ_VC6 + CORE1_H264_DMA2D_IN_CH2_INT_MAP NA - 6 - 1 - read-only + 0 + 6 + read-write + + + + H264_DMA2D_IN_CH3_INT_MAP + NA + 0x1EC + 0x20 + - ST_ERR_F_SEQ_VC7 + CORE1_H264_DMA2D_IN_CH3_INT_MAP NA - 7 - 1 - read-only + 0 + 6 + read-write + + + + H264_DMA2D_IN_CH4_INT_MAP + NA + 0x1F0 + 0x20 + - ST_ERR_F_SEQ_VC8 + CORE1_H264_DMA2D_IN_CH4_INT_MAP NA - 8 - 1 - read-only + 0 + 6 + read-write + + + + H264_DMA2D_IN_CH5_INT_MAP + NA + 0x1F4 + 0x20 + - ST_ERR_F_SEQ_VC9 + CORE1_H264_DMA2D_IN_CH5_INT_MAP NA - 9 - 1 - read-only + 0 + 6 + read-write + + + + H264_REG_INT_MAP + NA + 0x1F8 + 0x20 + - ST_ERR_F_SEQ_VC10 + CORE1_H264_REG_INT_MAP NA - 10 - 1 - read-only + 0 + 6 + read-write + + + + ASSIST_DEBUG_INT_MAP + NA + 0x1FC + 0x20 + - ST_ERR_F_SEQ_VC11 + CORE1_ASSIST_DEBUG_INT_MAP NA - 11 - 1 - read-only + 0 + 6 + read-write + + + + INTR_STATUS_REG_0 + NA + 0x200 + 0x20 + - ST_ERR_F_SEQ_VC12 + CORE1_INTR_STATUS_0 NA - 12 - 1 + 0 + 32 read-only + + + + INTR_STATUS_REG_1 + NA + 0x204 + 0x20 + - ST_ERR_F_SEQ_VC13 + CORE1_INTR_STATUS_1 NA - 13 - 1 + 0 + 32 read-only + + + + INTR_STATUS_REG_2 + NA + 0x208 + 0x20 + - ST_ERR_F_SEQ_VC14 + CORE1_INTR_STATUS_2 NA - 14 - 1 + 0 + 32 read-only + + + + INTR_STATUS_REG_3 + NA + 0x20C + 0x20 + - ST_ERR_F_SEQ_VC15 + CORE1_INTR_STATUS_3 NA - 15 - 1 + 0 + 32 read-only - INT_MSK_SEQ_FRAME_FATAL + CLOCK_GATE NA - 0x294 + 0x210 0x20 + 0x00000001 - MASK_ERR_F_SEQ_VC0 + CORE1_REG_CLK_EN NA 0 1 read-write + + + + INTERRUPT_REG_DATE + NA + 0x3FC + 0x20 + 0x02003020 + - MASK_ERR_F_SEQ_VC1 - NA - 1 - 1 - read-write - - - MASK_ERR_F_SEQ_VC2 + CORE1_INTERRUPT_REG_DATE NA - 2 - 1 + 0 + 28 read-write + + + + + + MIPI_CSI_BRIDGE + MIPI Camera Interface Bridge + CSI_BRIG + 0x5009F800 + + 0x0 + 0x48 + registers + + + CSI_BRIDGE + 85 + + + + CLK_EN + csi bridge register mapping unit clock gating. + 0x0 + 0x20 + - MASK_ERR_F_SEQ_VC3 - NA - 3 + CLK_EN + 0: enable clock gating. 1: disable clock gating, clock always on. + 0 1 read-write + + + + CSI_EN + csi bridge enable. + 0x4 + 0x20 + - MASK_ERR_F_SEQ_VC4 - NA - 4 + CSI_BRIG_EN + 0: disable csi bridge. 1: enable csi bridge. + 0 1 read-write + + + + DMA_REQ_CFG + dma request configuration. + 0x8 + 0x20 + 0x00000080 + - MASK_ERR_F_SEQ_VC5 - NA - 5 - 1 + DMA_BURST_LEN + DMA burst length. + 0 + 12 read-write - MASK_ERR_F_SEQ_VC6 - NA - 6 + DMA_CFG_UPD_BY_BLK + 1: reg_dma_burst_len & reg_dma_burst_len will be updated by dma block finish. 0: updated by frame. + 12 1 read-write - MASK_ERR_F_SEQ_VC7 - NA - 7 + DMA_FORCE_RD_STATUS + 1: mask dma request when reading frame info. 0: disable mask. + 16 1 read-write + + + + BUF_FLOW_CTL + csi bridge buffer control. + 0xC + 0x20 + 0x000007F8 + - MASK_ERR_F_SEQ_VC8 - NA - 8 - 1 + CSI_BUF_AFULL_THRD + buffer almost full threshold. + 0 + 14 read-write - MASK_ERR_F_SEQ_VC9 - NA - 9 - 1 - read-write + CSI_BUF_DEPTH + buffer data count. + 16 + 14 + read-only - - MASK_ERR_F_SEQ_VC10 - NA - 10 - 1 + + + + DATA_TYPE_CFG + pixel data type configuration. + 0x10 + 0x20 + 0x00002F18 + + + DATA_TYPE_MIN + the min value of data type used for pixel filter. + 0 + 6 read-write - MASK_ERR_F_SEQ_VC11 - NA - 11 - 1 + DATA_TYPE_MAX + the max value of data type used for pixel filter. + 8 + 6 + read-write + + + + + FRAME_CFG + frame configuration. + 0x14 + 0x20 + 0x011E01E0 + + + VADR_NUM + vadr of frame data. + 0 + 12 read-write - MASK_ERR_F_SEQ_VC12 - NA + HADR_NUM + hadr of frame data. 12 + 12 + read-write + + + HAS_HSYNC_E + 0: frame data doesn't contain hsync. 1: frame data contains hsync. + 24 1 read-write - MASK_ERR_F_SEQ_VC13 - NA - 13 + VADR_NUM_CHECK + 0: disable vadr check. 1: enable vadr check. + 25 1 read-write + + + + ENDIAN_MODE + data endianness order configuration. + 0x18 + 0x20 + - MASK_ERR_F_SEQ_VC14 - NA - 14 + BYTE_ENDIAN_ORDER + endianness order in bytes. 2'h0 is normal mode and 2'h3 is useful to YUV420(Legacy) when isp is bapassed. + 0 1 read-write - MASK_ERR_F_SEQ_VC15 - NA - 15 + BIT_ENDIAN_ORDER + N/A + 1 1 read-write - INT_FORCE_SEQ_FRAME_FATAL - NA - 0x298 + INT_RAW + csi bridge interrupt raw. + 0x1C 0x20 - FORCE_ERR_F_SEQ_VC0 - NA + VADR_NUM_GT_INT_RAW + reg_vadr_num is greater than real interrupt raw. 0 1 read-write - FORCE_ERR_F_SEQ_VC1 - NA + VADR_NUM_LT_INT_RAW + reg_vadr_num is less than real interrupt raw. 1 1 read-write - FORCE_ERR_F_SEQ_VC2 - NA + DISCARD_INT_RAW + an incomplete frame of data was sent interrupt raw. 2 1 read-write - FORCE_ERR_F_SEQ_VC3 - NA + CSI_BUF_OVERRUN_INT_RAW + buffer overrun interrupt raw. 3 1 read-write - FORCE_ERR_F_SEQ_VC4 - NA + CSI_ASYNC_FIFO_OVF_INT_RAW + buffer overflow interrupt raw. 4 1 read-write - FORCE_ERR_F_SEQ_VC5 - NA + DMA_CFG_HAS_UPDATED_INT_RAW + dma configuration update complete interrupt raw. 5 1 read-write + + + + INT_CLR + csi bridge interrupt clr. + 0x20 + 0x20 + + + VADR_NUM_GT_REAL_INT_CLR + reg_vadr_num is greater than real interrupt clr. + 0 + 1 + write-only + - FORCE_ERR_F_SEQ_VC6 - NA - 6 + VADR_NUM_LT_REAL_INT_CLR + reg_vadr_num is less than real interrupt clr. + 1 + 1 + write-only + + + DISCARD_INT_CLR + an incomplete frame of data was sent interrupt clr. + 2 + 1 + write-only + + + CSI_BUF_OVERRUN_INT_CLR + buffer overrun interrupt clr. + 3 + 1 + write-only + + + CSI_ASYNC_FIFO_OVF_INT_CLR + buffer overflow interrupt clr. + 4 + 1 + write-only + + + DMA_CFG_HAS_UPDATED_INT_CLR + dma configuration update complete interrupt clr. + 5 + 1 + write-only + + + + + INT_ST + csi bridge interrupt st. + 0x24 + 0x20 + + + VADR_NUM_GT_INT_ST + reg_vadr_num is greater than real interrupt st. + 0 + 1 + read-only + + + VADR_NUM_LT_INT_ST + reg_vadr_num is less than real interrupt st. + 1 + 1 + read-only + + + DISCARD_INT_ST + an incomplete frame of data was sent interrupt st. + 2 + 1 + read-only + + + CSI_BUF_OVERRUN_INT_ST + buffer overrun interrupt st. + 3 + 1 + read-only + + + CSI_ASYNC_FIFO_OVF_INT_ST + buffer overflow interrupt st. + 4 + 1 + read-only + + + DMA_CFG_HAS_UPDATED_INT_ST + dma configuration update complete interrupt st. + 5 + 1 + read-only + + + + + INT_ENA + csi bridge interrupt enable. + 0x28 + 0x20 + + + VADR_NUM_GT_INT_ENA + reg_vadr_num is greater than real interrupt enable. + 0 1 read-write - FORCE_ERR_F_SEQ_VC7 - NA - 7 + VADR_NUM_LT_INT_ENA + reg_vadr_num is less than real interrupt enable. + 1 1 read-write - FORCE_ERR_F_SEQ_VC8 - NA - 8 + DISCARD_INT_ENA + an incomplete frame of data was sent interrupt enable. + 2 1 read-write - FORCE_ERR_F_SEQ_VC9 - NA - 9 + CSI_BUF_OVERRUN_INT_ENA + buffer overrun interrupt enable. + 3 1 read-write - FORCE_ERR_F_SEQ_VC10 - NA - 10 + CSI_ASYNC_FIFO_OVF_INT_ENA + buffer overflow interrupt enable. + 4 1 read-write - FORCE_ERR_F_SEQ_VC11 - NA - 11 + DMA_CFG_HAS_UPDATED_INT_ENA + dma configuration update complete interrupt enable. + 5 + 1 + read-write + + + + + DMA_REQ_INTERVAL + DMA interval configuration. + 0x2C + 0x20 + 0x00000001 + + + DMA_REQ_INTERVAL + 16'b1: 1 cycle. 16'b11: 2 cycle. ... ... 16'hFFFF: 16 cycle. + 0 + 16 + read-write + + + + + DMABLK_SIZE + DMA block size configuration. + 0x30 + 0x20 + 0x00001FFF + + + DMABLK_SIZE + the number of reg_dma_burst_len in a block + 0 + 13 + read-write + + + + + RDN_ECO_CS + N/A + 0x34 + 0x20 + + + RDN_ECO_EN + N/A + 0 1 read-write - FORCE_ERR_F_SEQ_VC12 - NA - 12 + RDN_ECO_RESULT + N/A + 1 + 1 + read-only + + + + + RDN_ECO_LOW + N/A + 0x38 + 0x20 + + + RDN_ECO_LOW + N/A + 0 + 32 + read-write + + + + + RDN_ECO_HIGH + N/A + 0x3C + 0x20 + 0xFFFFFFFF + + + RDN_ECO_HIGH + N/A + 0 + 32 + read-write + + + + + HOST_CTRL + csi host control by csi bridge. + 0x40 + 0x20 + 0x00000003 + + + CSI_ENABLECLK + enable clock lane module of csi phy. + 0 1 read-write - FORCE_ERR_F_SEQ_VC13 - NA - 13 + CSI_CFG_CLK_EN + enable cfg_clk of csi host module. + 1 1 read-write - FORCE_ERR_F_SEQ_VC14 - NA - 14 + LOOPBK_TEST_EN + for phy test by loopback dsi phy to csi phy. + 2 + 1 + read-write + + + + + MEM_CTRL + csi bridge buffer control. + 0x44 + 0x20 + 0x00002640 + + + CSI_BRIDGE_MEM_CLK_FORCE_ON + csi bridge memory clock gating force on. + 0 1 read-write - FORCE_ERR_F_SEQ_VC15 + CSI_MEM_AUX_CTRL + N/A + 1 + 14 + read-write + + + + + + + MIPI_CSI_HOST + MIPI Camera Interface Host + CSI_HOST + 0x5009F000 + + 0x0 + 0xA8 + registers + + + CSI + 87 + + + + VERSION + NA + 0x0 + 0x20 + 0x3135302A + + + VERSION NA - 15 + 0 + 32 + read-only + + + + + N_LANES + NA + 0x4 + 0x20 + 0x00000001 + + + N_LANES + NA + 0 + 3 + read-write + + + + + CSI2_RESETN + NA + 0x8 + 0x20 + + + CSI2_RESETN + NA + 0 1 read-write - INT_ST_CRC_FRAME_FATAL + INT_ST_MAIN NA - 0x2A0 + 0xC 0x20 - ST_ERR_FRAME_DATA_VC0 + ST_STATUS_INT_PHY_FATAL NA 0 1 read-only - ST_ERR_FRAME_DATA_VC1 + ST_STATUS_INT_PKT_FATAL NA 1 1 read-only - ST_ERR_FRAME_DATA_VC2 + ST_STATUS_INT_BNDRY_FRAME_FATAL NA 2 1 read-only - ST_ERR_FRAME_DATA_VC3 + ST_STATUS_INT_SEQ_FRAME_FATAL NA 3 1 read-only - ST_ERR_FRAME_DATA_VC4 + ST_STATUS_INT_CRC_FRAME_FATAL NA 4 1 read-only - ST_ERR_FRAME_DATA_VC5 + ST_STATUS_INT_PLD_CRC_FATAL NA 5 1 read-only - ST_ERR_FRAME_DATA_VC6 + ST_STATUS_INT_DATA_ID NA 6 1 read-only - ST_ERR_FRAME_DATA_VC7 + ST_STATUS_INT_ECC_CORRECTED NA 7 1 read-only - ST_ERR_FRAME_DATA_VC8 + ST_STATUS_INT_PHY NA - 8 + 16 1 read-only + + + + PHY_SHUTDOWNZ + NA + 0x40 + 0x20 + + + PHY_SHUTDOWNZ + NA + 0 + 1 + read-write + + + + + DPHY_RSTZ + NA + 0x44 + 0x20 + - ST_ERR_FRAME_DATA_VC9 + DPHY_RSTZ NA - 9 + 0 + 1 + read-write + + + + + PHY_RX + NA + 0x48 + 0x20 + 0x00010000 + + + PHY_RXULPSESC_0 + NA + 0 1 read-only - ST_ERR_FRAME_DATA_VC10 + PHY_RXULPSESC_1 NA - 10 + 1 1 read-only - ST_ERR_FRAME_DATA_VC11 + PHY_RXULPSCLKNOT NA - 11 + 16 1 read-only - ST_ERR_FRAME_DATA_VC12 + PHY_RXCLKACTIVEHS NA - 12 + 17 1 read-only + + + + PHY_STOPSTATE + NA + 0x4C + 0x20 + - ST_ERR_FRAME_DATA_VC13 + PHY_STOPSTATEDATA_0 NA - 13 + 0 1 read-only - ST_ERR_FRAME_DATA_VC14 + PHY_STOPSTATEDATA_1 NA - 14 + 1 1 read-only - ST_ERR_FRAME_DATA_VC15 + PHY_STOPSTATECLK NA - 15 + 16 1 read-only - INT_MSK_CRC_FRAME_FATAL + PHY_TEST_CTRL0 NA - 0x2A4 + 0x50 0x20 + 0x00000001 - MASK_ERR_FRAME_DATA_VC0 + PHY_TESTCLR NA 0 1 read-write - MASK_ERR_FRAME_DATA_VC1 + PHY_TESTCLK NA 1 1 read-write + + + + PHY_TEST_CTRL1 + NA + 0x54 + 0x20 + - MASK_ERR_FRAME_DATA_VC2 - NA - 2 - 1 - read-write - - - MASK_ERR_FRAME_DATA_VC3 + PHY_TESTDIN NA - 3 - 1 + 0 + 8 read-write - MASK_ERR_FRAME_DATA_VC4 + PHY_TESTDOUT NA - 4 - 1 - read-write + 8 + 8 + read-only - MASK_ERR_FRAME_DATA_VC5 + PHY_TESTEN NA - 5 + 16 1 read-write + + + + VC_EXTENSION + NA + 0xC8 + 0x20 + - MASK_ERR_FRAME_DATA_VC6 + VCX NA - 6 + 0 1 read-write + + + + PHY_CAL + NA + 0xCC + 0x20 + - MASK_ERR_FRAME_DATA_VC7 + RXSKEWCALHS NA - 7 + 0 1 - read-write + read-only + + + + INT_ST_PHY_FATAL + NA + 0xE0 + 0x20 + - MASK_ERR_FRAME_DATA_VC8 + ST_PHY_ERRSOTSYNCHS_0 NA - 8 + 0 1 - read-write + read-only - MASK_ERR_FRAME_DATA_VC9 + ST_PHY_ERRSOTSYNCHS_1 NA - 9 + 1 1 - read-write + read-only + + + + INT_MSK_PHY_FATAL + NA + 0xE4 + 0x20 + - MASK_ERR_FRAME_DATA_VC10 + MASK_PHY_ERRSOTSYNCHS_0 NA - 10 + 0 1 read-write - MASK_ERR_FRAME_DATA_VC11 + MASK_PHY_ERRSOTSYNCHS_1 NA - 11 + 1 1 read-write + + + + INT_FORCE_PHY_FATAL + NA + 0xE8 + 0x20 + - MASK_ERR_FRAME_DATA_VC12 + FORCE_PHY_ERRSOTSYNCHS_0 NA - 12 + 0 1 read-write - MASK_ERR_FRAME_DATA_VC13 + FORCE_PHY_ERRSOTSYNCHS_1 NA - 13 + 1 1 read-write + + + + INT_ST_PKT_FATAL + NA + 0xF0 + 0x20 + - MASK_ERR_FRAME_DATA_VC14 + ST_ERR_ECC_DOUBLE NA - 14 + 0 1 - read-write + read-only - MASK_ERR_FRAME_DATA_VC15 + ST_SHORTER_PAYLOAD NA - 15 + 1 1 - read-write + read-only - INT_FORCE_CRC_FRAME_FATAL + INT_MSK_PKT_FATAL NA - 0x2A8 + 0xF4 0x20 - FORCE_ERR_FRAME_DATA_VC0 + MASK_ERR_ECC_DOUBLE NA 0 1 read-write - FORCE_ERR_FRAME_DATA_VC1 + MASK_SHORTER_PAYLOAD NA 1 1 read-write + + + + INT_FORCE_PKT_FATAL + NA + 0xF8 + 0x20 + - FORCE_ERR_FRAME_DATA_VC2 + FORCE_ERR_ECC_DOUBLE NA - 2 + 0 1 read-write - FORCE_ERR_FRAME_DATA_VC3 + FORCE_SHORTER_PAYLOAD NA - 3 + 1 1 read-write + + + + INT_ST_PHY + NA + 0x110 + 0x20 + - FORCE_ERR_FRAME_DATA_VC4 + ST_PHY_ERRSOTHS_0 NA - 4 + 0 1 - read-write + read-only - FORCE_ERR_FRAME_DATA_VC5 + ST_PHY_ERRSOTHS_1 NA - 5 + 1 1 - read-write + read-only - FORCE_ERR_FRAME_DATA_VC6 + ST_PHY_ERRESC_0 NA - 6 + 16 1 - read-write + read-only - FORCE_ERR_FRAME_DATA_VC7 + ST_PHY_ERRESC_1 NA - 7 + 17 1 - read-write + read-only + + + + INT_MSK_PHY + NA + 0x114 + 0x20 + - FORCE_ERR_FRAME_DATA_VC8 + MASK_PHY_ERRSOTHS_0 NA - 8 + 0 1 read-write - FORCE_ERR_FRAME_DATA_VC9 + MASK_PHY_ERRSOTHS_1 NA - 9 + 1 1 read-write - FORCE_ERR_FRAME_DATA_VC10 + MASK_PHY_ERRESC_0 NA - 10 + 16 1 read-write - FORCE_ERR_FRAME_DATA_VC11 + MASK_PHY_ERRESC_1 NA - 11 + 17 1 read-write + + + + INT_FORCE_PHY + NA + 0x118 + 0x20 + - FORCE_ERR_FRAME_DATA_VC12 + FORCE_PHY_ERRSOTHS_0 NA - 12 + 0 1 read-write - FORCE_ERR_FRAME_DATA_VC13 + FORCE_PHY_ERRSOTHS_1 NA - 13 + 1 1 read-write - FORCE_ERR_FRAME_DATA_VC14 + FORCE_PHY_ERRESC_0 NA - 14 + 16 1 read-write - FORCE_ERR_FRAME_DATA_VC15 + FORCE_PHY_ERRESC_1 NA - 15 + 17 1 read-write - INT_ST_PLD_CRC_FATAL + INT_ST_BNDRY_FRAME_FATAL NA - 0x2B0 + 0x280 0x20 - ST_ERR_CRC_VC0 + ST_ERR_F_BNDRY_MATCH_VC0 NA 0 1 read-only - ST_ERR_CRC_VC1 + ST_ERR_F_BNDRY_MATCH_VC1 NA 1 1 read-only - ST_ERR_CRC_VC2 + ST_ERR_F_BNDRY_MATCH_VC2 NA 2 1 read-only - ST_ERR_CRC_VC3 + ST_ERR_F_BNDRY_MATCH_VC3 NA 3 1 read-only - ST_ERR_CRC_VC4 + ST_ERR_F_BNDRY_MATCH_VC4 NA 4 1 read-only - ST_ERR_CRC_VC5 + ST_ERR_F_BNDRY_MATCH_VC5 NA 5 1 read-only - ST_ERR_CRC_VC6 + ST_ERR_F_BNDRY_MATCH_VC6 NA 6 1 read-only - ST_ERR_CRC_VC7 + ST_ERR_F_BNDRY_MATCH_VC7 NA 7 1 read-only - ST_ERR_CRC_VC8 + ST_ERR_F_BNDRY_MATCH_VC8 NA 8 1 read-only - ST_ERR_CRC_VC9 + ST_ERR_F_BNDRY_MATCH_VC9 NA 9 1 read-only - ST_ERR_CRC_VC10 + ST_ERR_F_BNDRY_MATCH_VC10 NA 10 1 read-only - ST_ERR_CRC_VC11 + ST_ERR_F_BNDRY_MATCH_VC11 NA 11 1 read-only - ST_ERR_CRC_VC12 + ST_ERR_F_BNDRY_MATCH_VC12 NA 12 1 read-only - ST_ERR_CRC_VC13 + ST_ERR_F_BNDRY_MATCH_VC13 NA 13 1 read-only - ST_ERR_CRC_VC14 + ST_ERR_F_BNDRY_MATCH_VC14 NA 14 1 read-only - ST_ERR_CRC_VC15 + ST_ERR_F_BNDRY_MATCH_VC15 NA 15 1 @@ -19608,118 +20348,118 @@ - INT_MSK_PLD_CRC_FATAL + INT_MSK_BNDRY_FRAME_FATAL NA - 0x2B4 + 0x284 0x20 - MASK_ERR_CRC_VC0 + MASK_ERR_F_BNDRY_MATCH_VC0 NA 0 1 read-write - MASK_ERR_CRC_VC1 + MASK_ERR_F_BNDRY_MATCH_VC1 NA 1 1 read-write - MASK_ERR_CRC_VC2 + MASK_ERR_F_BNDRY_MATCH_VC2 NA 2 1 read-write - MASK_ERR_CRC_VC3 + MASK_ERR_F_BNDRY_MATCH_VC3 NA 3 1 read-write - MASK_ERR_CRC_VC4 + MASK_ERR_F_BNDRY_MATCH_VC4 NA 4 1 read-write - MASK_ERR_CRC_VC5 + MASK_ERR_F_BNDRY_MATCH_VC5 NA 5 1 read-write - MASK_ERR_CRC_VC6 + MASK_ERR_F_BNDRY_MATCH_VC6 NA 6 1 read-write - MASK_ERR_CRC_VC7 + MASK_ERR_F_BNDRY_MATCH_VC7 NA 7 1 read-write - MASK_ERR_CRC_VC8 + MASK_ERR_F_BNDRY_MATCH_VC8 NA 8 1 read-write - MASK_ERR_CRC_VC9 + MASK_ERR_F_BNDRY_MATCH_VC9 NA 9 1 read-write - MASK_ERR_CRC_VC10 + MASK_ERR_F_BNDRY_MATCH_VC10 NA 10 1 read-write - MASK_ERR_CRC_VC11 + MASK_ERR_F_BNDRY_MATCH_VC11 NA 11 1 read-write - MASK_ERR_CRC_VC12 + MASK_ERR_F_BNDRY_MATCH_VC12 NA 12 1 read-write - MASK_ERR_CRC_VC13 + MASK_ERR_F_BNDRY_MATCH_VC13 NA 13 1 read-write - MASK_ERR_CRC_VC14 + MASK_ERR_F_BNDRY_MATCH_VC14 NA 14 1 read-write - MASK_ERR_CRC_VC15 + MASK_ERR_F_BNDRY_MATCH_VC15 NA 15 1 @@ -19728,118 +20468,118 @@ - INT_FORCE_PLD_CRC_FATAL + INT_FORCE_BNDRY_FRAME_FATAL NA - 0x2B8 + 0x288 0x20 - FORCE_ERR_CRC_VC0 + FORCE_ERR_F_BNDRY_MATCH_VC0 NA 0 1 read-write - FORCE_ERR_CRC_VC1 + FORCE_ERR_F_BNDRY_MATCH_VC1 NA 1 1 read-write - FORCE_ERR_CRC_VC2 + FORCE_ERR_F_BNDRY_MATCH_VC2 NA 2 1 read-write - FORCE_ERR_CRC_VC3 + FORCE_ERR_F_BNDRY_MATCH_VC3 NA 3 1 read-write - FORCE_ERR_CRC_VC4 + FORCE_ERR_F_BNDRY_MATCH_VC4 NA 4 1 read-write - FORCE_ERR_CRC_VC5 + FORCE_ERR_F_BNDRY_MATCH_VC5 NA 5 1 read-write - FORCE_ERR_CRC_VC6 + FORCE_ERR_F_BNDRY_MATCH_VC6 NA 6 1 read-write - FORCE_ERR_CRC_VC7 + FORCE_ERR_F_BNDRY_MATCH_VC7 NA 7 1 read-write - FORCE_ERR_CRC_VC8 + FORCE_ERR_F_BNDRY_MATCH_VC8 NA 8 1 read-write - FORCE_ERR_CRC_VC9 + FORCE_ERR_F_BNDRY_MATCH_VC9 NA 9 1 read-write - FORCE_ERR_CRC_VC10 + FORCE_ERR_F_BNDRY_MATCH_VC10 NA 10 1 read-write - FORCE_ERR_CRC_VC11 + FORCE_ERR_F_BNDRY_MATCH_VC11 NA 11 1 read-write - FORCE_ERR_CRC_VC12 + FORCE_ERR_F_BNDRY_MATCH_VC12 NA 12 1 read-write - FORCE_ERR_CRC_VC13 + FORCE_ERR_F_BNDRY_MATCH_VC13 NA 13 1 read-write - FORCE_ERR_CRC_VC14 + FORCE_ERR_F_BNDRY_MATCH_VC14 NA 14 1 read-write - FORCE_ERR_CRC_VC15 + FORCE_ERR_F_BNDRY_MATCH_VC15 NA 15 1 @@ -19848,118 +20588,118 @@ - INT_ST_DATA_ID + INT_ST_SEQ_FRAME_FATAL NA - 0x2C0 + 0x290 0x20 - ST_ERR_ID_VC0 + ST_ERR_F_SEQ_VC0 NA 0 1 read-only - ST_ERR_ID_VC1 + ST_ERR_F_SEQ_VC1 NA 1 1 read-only - ST_ERR_ID_VC2 + ST_ERR_F_SEQ_VC2 NA 2 1 read-only - ST_ERR_ID_VC3 + ST_ERR_F_SEQ_VC3 NA 3 1 read-only - ST_ERR_ID_VC4 + ST_ERR_F_SEQ_VC4 NA 4 1 read-only - ST_ERR_ID_VC5 + ST_ERR_F_SEQ_VC5 NA 5 1 read-only - ST_ERR_ID_VC6 + ST_ERR_F_SEQ_VC6 NA 6 1 read-only - ST_ERR_ID_VC7 + ST_ERR_F_SEQ_VC7 NA 7 1 read-only - ST_ERR_ID_VC8 + ST_ERR_F_SEQ_VC8 NA 8 1 read-only - ST_ERR_ID_VC9 + ST_ERR_F_SEQ_VC9 NA 9 1 read-only - ST_ERR_ID_VC10 + ST_ERR_F_SEQ_VC10 NA 10 1 read-only - ST_ERR_ID_VC11 + ST_ERR_F_SEQ_VC11 NA 11 1 read-only - ST_ERR_ID_VC12 + ST_ERR_F_SEQ_VC12 NA 12 1 read-only - ST_ERR_ID_VC13 + ST_ERR_F_SEQ_VC13 NA 13 1 read-only - ST_ERR_ID_VC14 + ST_ERR_F_SEQ_VC14 NA 14 1 read-only - ST_ERR_ID_VC15 + ST_ERR_F_SEQ_VC15 NA 15 1 @@ -19968,118 +20708,118 @@ - INT_MSK_DATA_ID + INT_MSK_SEQ_FRAME_FATAL NA - 0x2C4 + 0x294 0x20 - MASK_ERR_ID_VC0 + MASK_ERR_F_SEQ_VC0 NA 0 1 read-write - MASK_ERR_ID_VC1 + MASK_ERR_F_SEQ_VC1 NA 1 1 read-write - MASK_ERR_ID_VC2 + MASK_ERR_F_SEQ_VC2 NA 2 1 read-write - MASK_ERR_ID_VC3 + MASK_ERR_F_SEQ_VC3 NA 3 1 read-write - MASK_ERR_ID_VC4 + MASK_ERR_F_SEQ_VC4 NA 4 1 read-write - MASK_ERR_ID_VC5 + MASK_ERR_F_SEQ_VC5 NA 5 1 read-write - MASK_ERR_ID_VC6 + MASK_ERR_F_SEQ_VC6 NA 6 1 read-write - MASK_ERR_ID_VC7 + MASK_ERR_F_SEQ_VC7 NA 7 1 read-write - MASK_ERR_ID_VC8 + MASK_ERR_F_SEQ_VC8 NA 8 1 read-write - MASK_ERR_ID_VC9 + MASK_ERR_F_SEQ_VC9 NA 9 1 read-write - MASK_ERR_ID_VC10 + MASK_ERR_F_SEQ_VC10 NA 10 1 read-write - MASK_ERR_ID_VC11 + MASK_ERR_F_SEQ_VC11 NA 11 1 read-write - MASK_ERR_ID_VC12 + MASK_ERR_F_SEQ_VC12 NA 12 1 read-write - MASK_ERR_ID_VC13 + MASK_ERR_F_SEQ_VC13 NA 13 1 read-write - MASK_ERR_ID_VC14 + MASK_ERR_F_SEQ_VC14 NA 14 1 read-write - MASK_ERR_ID_VC15 + MASK_ERR_F_SEQ_VC15 NA 15 1 @@ -20088,118 +20828,118 @@ - INT_FORCE_DATA_ID + INT_FORCE_SEQ_FRAME_FATAL NA - 0x2C8 + 0x298 0x20 - FORCE_ERR_ID_VC0 + FORCE_ERR_F_SEQ_VC0 NA 0 1 read-write - FORCE_ERR_ID_VC1 + FORCE_ERR_F_SEQ_VC1 NA 1 1 read-write - FORCE_ERR_ID_VC2 + FORCE_ERR_F_SEQ_VC2 NA 2 1 read-write - FORCE_ERR_ID_VC3 + FORCE_ERR_F_SEQ_VC3 NA 3 1 read-write - FORCE_ERR_ID_VC4 + FORCE_ERR_F_SEQ_VC4 NA 4 1 read-write - FORCE_ERR_ID_VC5 + FORCE_ERR_F_SEQ_VC5 NA 5 1 read-write - FORCE_ERR_ID_VC6 + FORCE_ERR_F_SEQ_VC6 NA 6 1 read-write - FORCE_ERR_ID_VC7 + FORCE_ERR_F_SEQ_VC7 NA 7 1 read-write - FORCE_ERR_ID_VC8 + FORCE_ERR_F_SEQ_VC8 NA 8 1 read-write - FORCE_ERR_ID_VC9 + FORCE_ERR_F_SEQ_VC9 NA 9 1 read-write - FORCE_ERR_ID_VC10 + FORCE_ERR_F_SEQ_VC10 NA 10 1 read-write - FORCE_ERR_ID_VC11 + FORCE_ERR_F_SEQ_VC11 NA 11 1 read-write - FORCE_ERR_ID_VC12 + FORCE_ERR_F_SEQ_VC12 NA 12 1 read-write - FORCE_ERR_ID_VC13 + FORCE_ERR_F_SEQ_VC13 NA 13 1 read-write - FORCE_ERR_ID_VC14 + FORCE_ERR_F_SEQ_VC14 NA 14 1 read-write - FORCE_ERR_ID_VC15 + FORCE_ERR_F_SEQ_VC15 NA 15 1 @@ -20208,118 +20948,118 @@ - INT_ST_ECC_CORRECTED + INT_ST_CRC_FRAME_FATAL NA - 0x2D0 + 0x2A0 0x20 - ST_ERR_ECC_CORRECTED_VC0 + ST_ERR_FRAME_DATA_VC0 NA 0 1 read-only - ST_ERR_ECC_CORRECTED_VC1 + ST_ERR_FRAME_DATA_VC1 NA 1 1 read-only - ST_ERR_ECC_CORRECTED_VC2 + ST_ERR_FRAME_DATA_VC2 NA 2 1 read-only - ST_ERR_ECC_CORRECTED_VC3 + ST_ERR_FRAME_DATA_VC3 NA 3 1 read-only - ST_ERR_ECC_CORRECTED_VC4 + ST_ERR_FRAME_DATA_VC4 NA 4 1 read-only - ST_ERR_ECC_CORRECTED_VC5 + ST_ERR_FRAME_DATA_VC5 NA 5 1 read-only - ST_ERR_ECC_CORRECTED_VC6 + ST_ERR_FRAME_DATA_VC6 NA 6 1 read-only - ST_ERR_ECC_CORRECTED_VC7 + ST_ERR_FRAME_DATA_VC7 NA 7 1 read-only - ST_ERR_ECC_CORRECTED_VC8 + ST_ERR_FRAME_DATA_VC8 NA 8 1 read-only - ST_ERR_ECC_CORRECTED_VC9 + ST_ERR_FRAME_DATA_VC9 NA 9 1 read-only - ST_ERR_ECC_CORRECTED_VC10 + ST_ERR_FRAME_DATA_VC10 NA 10 1 read-only - ST_ERR_ECC_CORRECTED_VC11 + ST_ERR_FRAME_DATA_VC11 NA 11 1 read-only - ST_ERR_ECC_CORRECTED_VC12 + ST_ERR_FRAME_DATA_VC12 NA 12 1 read-only - ST_ERR_ECC_CORRECTED_VC13 + ST_ERR_FRAME_DATA_VC13 NA 13 1 read-only - ST_ERR_ECC_CORRECTED_VC14 + ST_ERR_FRAME_DATA_VC14 NA 14 1 read-only - ST_ERR_ECC_CORRECTED_VC15 + ST_ERR_FRAME_DATA_VC15 NA 15 1 @@ -20328,118 +21068,118 @@ - INT_MSK_ECC_CORRECTED + INT_MSK_CRC_FRAME_FATAL NA - 0x2D4 + 0x2A4 0x20 - MASK_ERR_ECC_CORRECTED_VC0 + MASK_ERR_FRAME_DATA_VC0 NA 0 1 read-write - MASK_ERR_ECC_CORRECTED_VC1 + MASK_ERR_FRAME_DATA_VC1 NA 1 1 read-write - MASK_ERR_ECC_CORRECTED_VC2 + MASK_ERR_FRAME_DATA_VC2 NA 2 1 read-write - MASK_ERR_ECC_CORRECTED_VC3 + MASK_ERR_FRAME_DATA_VC3 NA 3 1 read-write - MASK_ERR_ECC_CORRECTED_VC4 + MASK_ERR_FRAME_DATA_VC4 NA 4 1 read-write - MASK_ERR_ECC_CORRECTED_VC5 + MASK_ERR_FRAME_DATA_VC5 NA 5 1 read-write - MASK_ERR_ECC_CORRECTED_VC6 + MASK_ERR_FRAME_DATA_VC6 NA 6 1 read-write - MASK_ERR_ECC_CORRECTED_VC7 + MASK_ERR_FRAME_DATA_VC7 NA 7 1 read-write - MASK_ERR_ECC_CORRECTED_VC8 + MASK_ERR_FRAME_DATA_VC8 NA 8 1 read-write - MASK_ERR_ECC_CORRECTED_VC9 + MASK_ERR_FRAME_DATA_VC9 NA 9 1 read-write - MASK_ERR_ECC_CORRECTED_VC10 + MASK_ERR_FRAME_DATA_VC10 NA 10 1 read-write - MASK_ERR_ECC_CORRECTED_VC11 + MASK_ERR_FRAME_DATA_VC11 NA 11 1 read-write - MASK_ERR_ECC_CORRECTED_VC12 + MASK_ERR_FRAME_DATA_VC12 NA 12 1 read-write - MASK_ERR_ECC_CORRECTED_VC13 + MASK_ERR_FRAME_DATA_VC13 NA 13 1 read-write - MASK_ERR_ECC_CORRECTED_VC14 + MASK_ERR_FRAME_DATA_VC14 NA 14 1 read-write - MASK_ERR_ECC_CORRECTED_VC15 + MASK_ERR_FRAME_DATA_VC15 NA 15 1 @@ -20448,118 +21188,118 @@ - INT_FORCE_ECC_CORRECTED + INT_FORCE_CRC_FRAME_FATAL NA - 0x2D8 + 0x2A8 0x20 - FORCE_ERR_ECC_CORRECTED_VC0 + FORCE_ERR_FRAME_DATA_VC0 NA 0 1 read-write - FORCE_ERR_ECC_CORRECTED_VC1 + FORCE_ERR_FRAME_DATA_VC1 NA 1 1 read-write - FORCE_ERR_ECC_CORRECTED_VC2 + FORCE_ERR_FRAME_DATA_VC2 NA 2 1 read-write - FORCE_ERR_ECC_CORRECTED_VC3 + FORCE_ERR_FRAME_DATA_VC3 NA 3 1 read-write - FORCE_ERR_ECC_CORRECTED_VC4 + FORCE_ERR_FRAME_DATA_VC4 NA 4 1 read-write - FORCE_ERR_ECC_CORRECTED_VC5 + FORCE_ERR_FRAME_DATA_VC5 NA 5 1 read-write - FORCE_ERR_ECC_CORRECTED_VC6 + FORCE_ERR_FRAME_DATA_VC6 NA 6 1 read-write - FORCE_ERR_ECC_CORRECTED_VC7 + FORCE_ERR_FRAME_DATA_VC7 NA 7 1 read-write - FORCE_ERR_ECC_CORRECTED_VC8 + FORCE_ERR_FRAME_DATA_VC8 NA 8 1 read-write - FORCE_ERR_ECC_CORRECTED_VC9 + FORCE_ERR_FRAME_DATA_VC9 NA 9 1 read-write - FORCE_ERR_ECC_CORRECTED_VC10 + FORCE_ERR_FRAME_DATA_VC10 NA 10 1 read-write - FORCE_ERR_ECC_CORRECTED_VC11 + FORCE_ERR_FRAME_DATA_VC11 NA 11 1 read-write - FORCE_ERR_ECC_CORRECTED_VC12 + FORCE_ERR_FRAME_DATA_VC12 NA 12 1 read-write - FORCE_ERR_ECC_CORRECTED_VC13 + FORCE_ERR_FRAME_DATA_VC13 NA 13 1 read-write - FORCE_ERR_ECC_CORRECTED_VC14 + FORCE_ERR_FRAME_DATA_VC14 NA 14 1 read-write - FORCE_ERR_ECC_CORRECTED_VC15 + FORCE_ERR_FRAME_DATA_VC15 NA 15 1 @@ -20568,2807 +21308,2288 @@ - SCRAMBLING + INT_ST_PLD_CRC_FATAL NA - 0x300 + 0x2B0 0x20 - SCRAMBLE_ENABLE + ST_ERR_CRC_VC0 NA 0 1 - read-write + read-only - - - - SCRAMBLING_SEED1 - NA - 0x304 - 0x20 - 0x00001008 - - SCRAMBLE_SEED_LANE1 + ST_ERR_CRC_VC1 NA - 0 - 16 - read-write + 1 + 1 + read-only - - - - SCRAMBLING_SEED2 - NA - 0x308 - 0x20 - 0x00001188 - - SCRAMBLE_SEED_LANE2 + ST_ERR_CRC_VC2 NA - 0 - 16 - read-write + 2 + 1 + read-only - - - - - - DMA - DMA (Direct Memory Access) Controller - DMAC - 0x50081000 - - 0x0 - 0x234 - registers - - - DMA - 24 - - - - ID0 - NA - 0x0 - 0x20 - - DMAC_ID + ST_ERR_CRC_VC3 NA - 0 - 32 + 3 + 1 read-only - - - - COMPVER0 - NA - 0x8 - 0x20 - 0x3230302A - - DMAC_COMPVER + ST_ERR_CRC_VC4 NA - 0 - 32 + 4 + 1 read-only - - - - CFG0 - NA - 0x10 - 0x20 - - DMAC_EN + ST_ERR_CRC_VC5 NA - 0 + 5 1 - read-write + read-only - INT_EN + ST_ERR_CRC_VC6 NA - 1 + 6 1 - read-write + read-only + + + ST_ERR_CRC_VC7 + NA + 7 + 1 + read-only + + + ST_ERR_CRC_VC8 + NA + 8 + 1 + read-only + + + ST_ERR_CRC_VC9 + NA + 9 + 1 + read-only + + + ST_ERR_CRC_VC10 + NA + 10 + 1 + read-only + + + ST_ERR_CRC_VC11 + NA + 11 + 1 + read-only + + + ST_ERR_CRC_VC12 + NA + 12 + 1 + read-only + + + ST_ERR_CRC_VC13 + NA + 13 + 1 + read-only + + + ST_ERR_CRC_VC14 + NA + 14 + 1 + read-only + + + ST_ERR_CRC_VC15 + NA + 15 + 1 + read-only - CHEN0 + INT_MSK_PLD_CRC_FATAL NA - 0x18 + 0x2B4 0x20 - CH1_EN + MASK_ERR_CRC_VC0 NA 0 1 read-write - CH2_EN + MASK_ERR_CRC_VC1 NA 1 1 read-write - CH3_EN + MASK_ERR_CRC_VC2 NA 2 1 read-write - CH4_EN + MASK_ERR_CRC_VC3 NA 3 1 read-write - CH1_EN_WE + MASK_ERR_CRC_VC4 NA - 8 + 4 1 - write-only + read-write - CH2_EN_WE + MASK_ERR_CRC_VC5 NA - 9 + 5 1 - write-only + read-write - CH3_EN_WE + MASK_ERR_CRC_VC6 NA - 10 + 6 1 - write-only + read-write - CH4_EN_WE + MASK_ERR_CRC_VC7 NA - 11 + 7 1 - write-only + read-write - CH1_SUSP + MASK_ERR_CRC_VC8 NA - 16 + 8 1 read-write - CH2_SUSP + MASK_ERR_CRC_VC9 NA - 17 + 9 1 read-write - CH3_SUSP + MASK_ERR_CRC_VC10 NA - 18 + 10 1 read-write - CH4_SUSP + MASK_ERR_CRC_VC11 NA - 19 + 11 1 read-write - CH1_SUSP_WE + MASK_ERR_CRC_VC12 NA - 24 + 12 1 - write-only + read-write - CH2_SUSP_WE + MASK_ERR_CRC_VC13 NA - 25 + 13 1 - write-only + read-write - CH3_SUSP_WE + MASK_ERR_CRC_VC14 NA - 26 + 14 1 - write-only + read-write - CH4_SUSP_WE + MASK_ERR_CRC_VC15 NA - 27 + 15 1 - write-only + read-write - CHEN1 + INT_FORCE_PLD_CRC_FATAL NA - 0x1C + 0x2B8 0x20 - CH1_ABORT + FORCE_ERR_CRC_VC0 NA 0 1 read-write - CH2_ABORT + FORCE_ERR_CRC_VC1 NA 1 1 read-write - CH3_ABORT + FORCE_ERR_CRC_VC2 NA 2 1 read-write - CH4_ABORT + FORCE_ERR_CRC_VC3 NA 3 1 read-write - CH1_ABORT_WE + FORCE_ERR_CRC_VC4 NA - 8 + 4 1 - write-only + read-write - CH2_ABORT_WE + FORCE_ERR_CRC_VC5 NA - 9 + 5 1 - write-only + read-write - CH3_ABORT_WE + FORCE_ERR_CRC_VC6 NA - 10 + 6 1 - write-only + read-write - CH4_ABORT_WE + FORCE_ERR_CRC_VC7 NA - 11 + 7 1 - write-only + read-write - - - - INTSTATUS0 - NA - 0x30 - 0x20 - - CH1_INTSTAT + FORCE_ERR_CRC_VC8 NA - 0 + 8 1 - read-only + read-write - CH2_INTSTAT + FORCE_ERR_CRC_VC9 NA - 1 + 9 1 - read-only + read-write - CH3_INTSTAT + FORCE_ERR_CRC_VC10 NA - 2 + 10 1 - read-only + read-write - CH4_INTSTAT + FORCE_ERR_CRC_VC11 NA - 3 + 11 1 - read-only + read-write - COMMONREG_INTSTAT + FORCE_ERR_CRC_VC12 NA - 16 + 12 1 - read-only + read-write + + + FORCE_ERR_CRC_VC13 + NA + 13 + 1 + read-write + + + FORCE_ERR_CRC_VC14 + NA + 14 + 1 + read-write + + + FORCE_ERR_CRC_VC15 + NA + 15 + 1 + read-write - COMMONREG_INTCLEAR0 + INT_ST_DATA_ID NA - 0x38 + 0x2C0 0x20 - CLEAR_SLVIF_COMMONREG_DEC_ERR_INTSTAT + ST_ERR_ID_VC0 NA 0 1 - write-only + read-only - CLEAR_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT + ST_ERR_ID_VC1 NA 1 1 - write-only + read-only - CLEAR_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT + ST_ERR_ID_VC2 NA 2 1 - write-only + read-only - CLEAR_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT + ST_ERR_ID_VC3 NA 3 1 - write-only - - - CLEAR_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT - NA - 7 - 1 - write-only - - - CLEAR_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT - NA - 8 - 1 - write-only + read-only - CLEAR_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT + ST_ERR_ID_VC4 NA - 9 + 4 1 - write-only + read-only - CLEAR_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT + ST_ERR_ID_VC5 NA - 10 + 5 1 - write-only + read-only - CLEAR_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT + ST_ERR_ID_VC6 NA - 11 + 6 1 - write-only + read-only - CLEAR_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT + ST_ERR_ID_VC7 NA - 12 + 7 1 - write-only + read-only - CLEAR_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT + ST_ERR_ID_VC8 NA - 13 + 8 1 - write-only + read-only - CLEAR_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT + ST_ERR_ID_VC9 NA - 14 + 9 1 - write-only + read-only - CLEAR_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT + ST_ERR_ID_VC10 NA - 15 + 10 1 - write-only + read-only - CLEAR_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT + ST_ERR_ID_VC11 NA - 16 + 11 1 - write-only + read-only - CLEAR_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT + ST_ERR_ID_VC12 NA - 17 + 12 1 - write-only + read-only - CLEAR_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT + ST_ERR_ID_VC13 NA - 18 + 13 1 - write-only + read-only - CLEAR_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT + ST_ERR_ID_VC14 NA - 19 + 14 1 - write-only + read-only - CLEAR_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT + ST_ERR_ID_VC15 NA - 20 + 15 1 - write-only + read-only - COMMONREG_INTSTATUS_ENABLE0 + INT_MSK_DATA_ID NA - 0x40 + 0x2C4 0x20 - 0x001FFF8F - ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSTAT + MASK_ERR_ID_VC0 NA 0 1 read-write - ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT + MASK_ERR_ID_VC1 NA 1 1 read-write - ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT + MASK_ERR_ID_VC2 NA 2 1 read-write - ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT + MASK_ERR_ID_VC3 NA 3 1 read-write - ENABLE_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT - NA - 7 - 1 - read-only - - - ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT + MASK_ERR_ID_VC4 NA - 8 + 4 1 read-write - ENABLE_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT - NA - 9 - 1 - read-only - - - ENABLE_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT + MASK_ERR_ID_VC5 NA - 10 + 5 1 - read-only + read-write - ENABLE_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT + MASK_ERR_ID_VC6 NA - 11 + 6 1 - read-only + read-write - ENABLE_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT + MASK_ERR_ID_VC7 NA - 12 + 7 1 - read-only + read-write - ENABLE_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT + MASK_ERR_ID_VC8 NA - 13 + 8 1 - read-only + read-write - ENABLE_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT + MASK_ERR_ID_VC9 NA - 14 + 9 1 - read-only + read-write - ENABLE_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT + MASK_ERR_ID_VC10 NA - 15 + 10 1 - read-only + read-write - ENABLE_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT + MASK_ERR_ID_VC11 NA - 16 + 11 1 - read-only + read-write - ENABLE_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT + MASK_ERR_ID_VC12 NA - 17 + 12 1 - read-only + read-write - ENABLE_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT + MASK_ERR_ID_VC13 NA - 18 + 13 1 - read-only + read-write - ENABLE_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT + MASK_ERR_ID_VC14 NA - 19 + 14 1 - read-only + read-write - ENABLE_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT + MASK_ERR_ID_VC15 NA - 20 + 15 1 - read-only + read-write - COMMONREG_INTSIGNAL_ENABLE0 + INT_FORCE_DATA_ID NA - 0x48 + 0x2C8 0x20 - 0x001FFF8F - ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSIGNAL + FORCE_ERR_ID_VC0 NA 0 1 read-write - ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSIGNAL + FORCE_ERR_ID_VC1 NA 1 1 read-write - ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSIGNAL + FORCE_ERR_ID_VC2 NA 2 1 read-write - ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSIGNAL + FORCE_ERR_ID_VC3 NA 3 1 read-write - ENABLE_SLVIF_COMMONREG_WRPARITY_ERR_INTSIGNAL + FORCE_ERR_ID_VC4 + NA + 4 + 1 + read-write + + + FORCE_ERR_ID_VC5 + NA + 5 + 1 + read-write + + + FORCE_ERR_ID_VC6 + NA + 6 + 1 + read-write + + + FORCE_ERR_ID_VC7 NA 7 1 - read-only + read-write - ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSIGNAL + FORCE_ERR_ID_VC8 NA 8 1 read-write - ENABLE_MXIF1_RCH0_ECCPROT_CORRERR_INTSIGNAL + FORCE_ERR_ID_VC9 NA 9 1 - read-only + read-write - ENABLE_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSIGNAL + FORCE_ERR_ID_VC10 NA 10 1 - read-only + read-write - ENABLE_MXIF1_RCH1_ECCPROT_CORRERR_INTSIGNAL + FORCE_ERR_ID_VC11 NA 11 1 - read-only + read-write - ENABLE_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSIGNAL + FORCE_ERR_ID_VC12 NA 12 1 - read-only + read-write - ENABLE_MXIF1_BCH_ECCPROT_CORRERR_INTSIGNAL + FORCE_ERR_ID_VC13 NA 13 1 - read-only + read-write - ENABLE_MXIF1_BCH_ECCPROT_UNCORRERR_INTSIGNAL + FORCE_ERR_ID_VC14 NA 14 1 - read-only + read-write - ENABLE_MXIF2_RCH0_ECCPROT_CORRERR_INTSIGNAL + FORCE_ERR_ID_VC15 NA 15 1 - read-only - - - ENABLE_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSIGNAL - NA - 16 - 1 - read-only - - - ENABLE_MXIF2_RCH1_ECCPROT_CORRERR_INTSIGNAL - NA - 17 - 1 - read-only + read-write + + + + INT_ST_ECC_CORRECTED + NA + 0x2D0 + 0x20 + - ENABLE_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSIGNAL + ST_ERR_ECC_CORRECTED_VC0 NA - 18 + 0 1 read-only - ENABLE_MXIF2_BCH_ECCPROT_CORRERR_INTSIGNAL + ST_ERR_ECC_CORRECTED_VC1 NA - 19 + 1 1 read-only - ENABLE_MXIF2_BCH_ECCPROT_UNCORRERR_INTSIGNAL + ST_ERR_ECC_CORRECTED_VC2 NA - 20 + 2 1 read-only - - - - COMMONREG_INTSTATUS0 - NA - 0x50 - 0x20 - - SLVIF_COMMONREG_DEC_ERR_INTSTAT + ST_ERR_ECC_CORRECTED_VC3 NA - 0 + 3 1 read-only - SLVIF_COMMONREG_WR2RO_ERR_INTSTAT + ST_ERR_ECC_CORRECTED_VC4 NA - 1 + 4 1 read-only - SLVIF_COMMONREG_RD2WO_ERR_INTSTAT + ST_ERR_ECC_CORRECTED_VC5 NA - 2 + 5 1 read-only - SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT + ST_ERR_ECC_CORRECTED_VC6 NA - 3 + 6 1 read-only - SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT + ST_ERR_ECC_CORRECTED_VC7 NA 7 1 read-only - SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT + ST_ERR_ECC_CORRECTED_VC8 NA 8 1 read-only - MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT + ST_ERR_ECC_CORRECTED_VC9 NA 9 1 read-only - MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT + ST_ERR_ECC_CORRECTED_VC10 NA 10 1 read-only - MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT + ST_ERR_ECC_CORRECTED_VC11 NA 11 1 read-only - MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT + ST_ERR_ECC_CORRECTED_VC12 NA 12 1 read-only - MXIF1_BCH_ECCPROT_CORRERR_INTSTAT + ST_ERR_ECC_CORRECTED_VC13 NA 13 1 read-only - MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT + ST_ERR_ECC_CORRECTED_VC14 NA 14 1 read-only - MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT + ST_ERR_ECC_CORRECTED_VC15 NA 15 1 read-only + + + + INT_MSK_ECC_CORRECTED + NA + 0x2D4 + 0x20 + - MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT + MASK_ERR_ECC_CORRECTED_VC0 NA - 16 + 0 1 - read-only + read-write - MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT + MASK_ERR_ECC_CORRECTED_VC1 NA - 17 + 1 1 - read-only + read-write - MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT + MASK_ERR_ECC_CORRECTED_VC2 NA - 18 + 2 1 - read-only + read-write - MXIF2_BCH_ECCPROT_CORRERR_INTSTAT + MASK_ERR_ECC_CORRECTED_VC3 NA - 19 + 3 1 - read-only + read-write - MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT + MASK_ERR_ECC_CORRECTED_VC4 NA - 20 + 4 1 - read-only + read-write - - - - RESET0 - NA - 0x58 - 0x20 - - DMAC_RST + MASK_ERR_ECC_CORRECTED_VC5 NA - 0 + 5 1 read-write - - - - LOWPOWER_CFG0 - NA - 0x60 - 0x20 - 0x0000000F - - GBL_CSLP_EN + MASK_ERR_ECC_CORRECTED_VC6 NA - 0 + 6 1 read-write - CHNL_CSLP_EN + MASK_ERR_ECC_CORRECTED_VC7 NA - 1 + 7 1 read-write - SBIU_CSLP_EN + MASK_ERR_ECC_CORRECTED_VC8 NA - 2 + 8 1 read-write - MXIF_CSLP_EN + MASK_ERR_ECC_CORRECTED_VC9 NA - 3 + 9 1 read-write - - - - LOWPOWER_CFG1 - NA - 0x64 - 0x20 - 0x00404040 - - GLCH_LPDLY + MASK_ERR_ECC_CORRECTED_VC10 NA - 0 - 8 + 10 + 1 read-write - SBIU_LPDLY + MASK_ERR_ECC_CORRECTED_VC11 NA - 8 - 8 + 11 + 1 read-write - MXIF_LPDLY + MASK_ERR_ECC_CORRECTED_VC12 NA - 16 - 8 + 12 + 1 read-write - - - - CH1_SAR0 - NA - 0x100 - 0x20 - - CH1_SAR0 + MASK_ERR_ECC_CORRECTED_VC13 NA - 0 - 32 + 13 + 1 read-write - - - - CH1_SAR1 - NA - 0x104 - 0x20 - - CH1_SAR1 + MASK_ERR_ECC_CORRECTED_VC14 NA - 0 - 32 + 14 + 1 read-write - - - - CH1_DAR0 - NA - 0x108 - 0x20 - - CH1_DAR0 + MASK_ERR_ECC_CORRECTED_VC15 NA - 0 - 32 + 15 + 1 read-write - CH1_DAR1 + INT_FORCE_ECC_CORRECTED NA - 0x10C + 0x2D8 0x20 - CH1_DAR1 + FORCE_ERR_ECC_CORRECTED_VC0 NA 0 - 32 + 1 read-write - - - - CH1_BLOCK_TS0 - NA - 0x110 - 0x20 - - CH1_BLOCK_TS + FORCE_ERR_ECC_CORRECTED_VC1 NA - 0 - 22 + 1 + 1 read-write - - - - CH1_CTL0 - NA - 0x118 - 0x20 - 0x00001200 - - CH1_SMS + FORCE_ERR_ECC_CORRECTED_VC2 NA - 0 + 2 1 read-write - CH1_DMS + FORCE_ERR_ECC_CORRECTED_VC3 NA - 2 + 3 1 read-write - CH1_SINC + FORCE_ERR_ECC_CORRECTED_VC4 NA 4 1 read-write - CH1_DINC + FORCE_ERR_ECC_CORRECTED_VC5 NA - 6 + 5 1 read-write - CH1_SRC_TR_WIDTH + FORCE_ERR_ECC_CORRECTED_VC6 NA - 8 - 3 + 6 + 1 read-write - CH1_DST_TR_WIDTH + FORCE_ERR_ECC_CORRECTED_VC7 NA - 11 - 3 + 7 + 1 read-write - CH1_SRC_MSIZE + FORCE_ERR_ECC_CORRECTED_VC8 NA - 14 - 4 + 8 + 1 read-write - CH1_DST_MSIZE + FORCE_ERR_ECC_CORRECTED_VC9 NA - 18 - 4 + 9 + 1 read-write - CH1_AR_CACHE + FORCE_ERR_ECC_CORRECTED_VC10 NA - 22 - 4 + 10 + 1 read-write - CH1_AW_CACHE + FORCE_ERR_ECC_CORRECTED_VC11 NA - 26 - 4 + 11 + 1 read-write - CH1_NONPOSTED_LASTWRITE_EN + FORCE_ERR_ECC_CORRECTED_VC12 NA - 30 + 12 1 read-write - - - - CH1_CTL1 - NA - 0x11C - 0x20 - - CH1_AR_PROT + FORCE_ERR_ECC_CORRECTED_VC13 NA - 0 - 3 + 13 + 1 read-write - CH1_AW_PROT - NA - 3 - 3 - read-write - - - CH1_ARLEN_EN + FORCE_ERR_ECC_CORRECTED_VC14 NA - 6 + 14 1 read-write - CH1_ARLEN + FORCE_ERR_ECC_CORRECTED_VC15 NA - 7 - 8 + 15 + 1 read-write + + + + SCRAMBLING + NA + 0x300 + 0x20 + - CH1_AWLEN_EN + SCRAMBLE_ENABLE NA - 15 + 0 1 read-write + + + + SCRAMBLING_SEED1 + NA + 0x304 + 0x20 + 0x00001008 + - CH1_AWLEN + SCRAMBLE_SEED_LANE1 NA - 16 - 8 + 0 + 16 read-write + + + + SCRAMBLING_SEED2 + NA + 0x308 + 0x20 + 0x00001188 + - CH1_SRC_STAT_EN + SCRAMBLE_SEED_LANE2 NA - 24 - 1 + 0 + 16 read-write + + + + + + DMA + DMA (Direct Memory Access) Controller + DMAC + 0x50081000 + + 0x0 + 0x234 + registers + + + DMA + 24 + + + + ID0 + NA + 0x0 + 0x20 + - CH1_DST_STAT_EN + DMAC_ID NA - 25 - 1 - read-write + 0 + 32 + read-only + + + + COMPVER0 + NA + 0x8 + 0x20 + 0x3230302A + - CH1_IOC_BLKTFR + DMAC_COMPVER NA - 26 - 1 - read-write + 0 + 32 + read-only + + + + CFG0 + NA + 0x10 + 0x20 + - CH1_SHADOWREG_OR_LLI_LAST + DMAC_EN NA - 30 + 0 1 read-write - CH1_SHADOWREG_OR_LLI_VALID + INT_EN NA - 31 + 1 1 read-write - CH1_CFG0 + CHEN0 NA - 0x120 + 0x18 0x20 - CH1_SRC_MULTBLK_TYPE + CH1_EN NA 0 - 2 + 1 read-write - CH1_DST_MULTBLK_TYPE + CH2_EN NA - 2 - 2 + 1 + 1 read-write - CH1_RD_UID + CH3_EN NA - 18 - 4 - read-only + 2 + 1 + read-write - CH1_WR_UID + CH4_EN NA - 25 - 4 - read-only + 3 + 1 + read-write - - - - CH1_CFG1 - NA - 0x124 - 0x20 - 0x0006001B - - CH1_TT_FC + CH1_EN_WE NA - 0 - 3 - read-write + 8 + 1 + write-only - CH1_HS_SEL_SRC + CH2_EN_WE NA - 3 + 9 1 - read-write + write-only - CH1_HS_SEL_DST + CH3_EN_WE NA - 4 + 10 1 - read-write + write-only - CH1_SRC_HWHS_POL + CH4_EN_WE NA - 5 + 11 1 - read-only + write-only - CH1_DST_HWHS_POL + CH1_SUSP NA - 6 + 16 1 - read-only + read-write - CH1_SRC_PER + CH2_SUSP NA - 7 - 2 + 17 + 1 read-write - CH1_DST_PER + CH3_SUSP NA - 12 - 2 + 18 + 1 read-write - CH1_CH_PRIOR + CH4_SUSP NA - 17 - 3 + 19 + 1 read-write - CH1_LOCK_CH + CH1_SUSP_WE NA - 20 + 24 1 - read-only + write-only - CH1_LOCK_CH_L + CH2_SUSP_WE NA - 21 - 2 - read-only + 25 + 1 + write-only - CH1_SRC_OSR_LMT + CH3_SUSP_WE NA - 23 - 4 - read-write + 26 + 1 + write-only - CH1_DST_OSR_LMT + CH4_SUSP_WE NA 27 - 4 - read-write + 1 + write-only - CH1_LLP0 + CHEN1 NA - 0x128 + 0x1C 0x20 - CH1_LMS + CH1_ABORT NA 0 1 read-write - CH1_LOC0 + CH2_ABORT NA - 6 - 26 + 1 + 1 read-write - - - - CH1_LLP1 - NA - 0x12C - 0x20 - - CH1_LOC1 + CH3_ABORT NA - 0 - 32 + 2 + 1 read-write - - - - CH1_STATUS0 - NA - 0x130 - 0x20 - - CH1_CMPLTD_BLK_TFR_SIZE + CH4_ABORT NA - 0 - 22 - read-only + 3 + 1 + read-write - - - - CH1_STATUS1 - NA - 0x134 - 0x20 - - CH1_DATA_LEFT_IN_FIFO + CH1_ABORT_WE NA - 0 - 15 - read-only + 8 + 1 + write-only + + + CH2_ABORT_WE + NA + 9 + 1 + write-only + + + CH3_ABORT_WE + NA + 10 + 1 + write-only + + + CH4_ABORT_WE + NA + 11 + 1 + write-only - CH1_SWHSSRC0 + INTSTATUS0 NA - 0x138 + 0x30 0x20 - CH1_SWHS_REQ_SRC + CH1_INTSTAT NA 0 1 - read-write + read-only - CH1_SWHS_REQ_SRC_WE + CH2_INTSTAT NA 1 1 - write-only + read-only - CH1_SWHS_SGLREQ_SRC + CH3_INTSTAT NA 2 1 - read-write + read-only - CH1_SWHS_SGLREQ_SRC_WE + CH4_INTSTAT NA 3 1 - write-only - - - CH1_SWHS_LST_SRC - NA - 4 - 1 - read-write + read-only - CH1_SWHS_LST_SRC_WE + COMMONREG_INTSTAT NA - 5 + 16 1 - write-only + read-only - CH1_SWHSDST0 + COMMONREG_INTCLEAR0 NA - 0x140 + 0x38 0x20 - CH1_SWHS_REQ_DST + CLEAR_SLVIF_COMMONREG_DEC_ERR_INTSTAT NA 0 1 - read-write + write-only - CH1_SWHS_REQ_DST_WE + CLEAR_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT NA 1 1 write-only - CH1_SWHS_SGLREQ_DST + CLEAR_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT NA 2 1 - read-write + write-only - CH1_SWHS_SGLREQ_DST_WE + CLEAR_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT NA 3 1 write-only - CH1_SWHS_LST_DST + CLEAR_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT NA - 4 + 7 1 - read-write + write-only - CH1_SWHS_LST_DST_WE + CLEAR_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT NA - 5 + 8 1 write-only - - - - CH1_BLK_TFR_RESUMEREQ0 - NA - 0x148 - 0x20 - - CH1_BLK_TFR_RESUMEREQ + CLEAR_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT NA - 0 + 9 1 write-only - - - - CH1_AXI_ID0 - NA - 0x150 - 0x20 - - CH1_AXI_READ_ID_SUFFIX + CLEAR_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT NA - 0 + 10 1 - read-write + write-only - CH1_AXI_WRITE_ID_SUFFIX + CLEAR_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT NA - 16 + 11 1 - read-write + write-only - - - - CH1_AXI_QOS0 - NA - 0x158 - 0x20 - - CH1_AXI_AWQOS + CLEAR_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT NA - 0 - 4 - read-write + 12 + 1 + write-only - CH1_AXI_ARQOS + CLEAR_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT NA - 4 - 4 - read-write + 13 + 1 + write-only - - - - CH1_SSTAT0 - NA - 0x160 - 0x20 - - CH1_SSTAT + CLEAR_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT NA - 0 - 32 - read-only + 14 + 1 + write-only - - - - CH1_DSTAT0 - NA - 0x168 - 0x20 - - CH1_DSTAT + CLEAR_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT NA - 0 - 32 - read-only + 15 + 1 + write-only - - - - CH1_SSTATAR0 - NA - 0x170 - 0x20 - - CH1_SSTATAR0 + CLEAR_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT NA - 0 - 32 - read-write + 16 + 1 + write-only - - - - CH1_SSTATAR1 - NA - 0x174 - 0x20 - - CH1_SSTATAR1 + CLEAR_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT NA - 0 - 32 - read-write + 17 + 1 + write-only - - - - CH1_DSTATAR0 - NA - 0x178 - 0x20 - - CH1_DSTATAR0 + CLEAR_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT NA - 0 - 32 - read-write + 18 + 1 + write-only - - - - CH1_DSTATAR1 - NA - 0x17C - 0x20 - - CH1_DSTATAR1 + CLEAR_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT NA - 0 - 32 - read-write + 19 + 1 + write-only + + + CLEAR_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT + NA + 20 + 1 + write-only - CH1_INTSTATUS_ENABLE0 + COMMONREG_INTSTATUS_ENABLE0 NA - 0x180 + 0x40 0x20 - 0xFA3F7FFB + 0x001FFF8F - CH1_ENABLE_BLOCK_TFR_DONE_INTSTAT + ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSTAT NA 0 1 read-write - CH1_ENABLE_DMA_TFR_DONE_INTSTAT + ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT NA 1 1 read-write - CH1_ENABLE_SRC_TRANSCOMP_INTSTAT - NA - 3 - 1 - read-write - - - CH1_ENABLE_DST_TRANSCOMP_INTSTAT - NA - 4 - 1 - read-write - - - CH1_ENABLE_SRC_DEC_ERR_INTSTAT + ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT NA - 5 + 2 1 read-write - CH1_ENABLE_DST_DEC_ERR_INTSTAT + ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT NA - 6 + 3 1 read-write - CH1_ENABLE_SRC_SLV_ERR_INTSTAT + ENABLE_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT NA 7 1 - read-write + read-only - CH1_ENABLE_DST_SLV_ERR_INTSTAT + ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT NA 8 1 read-write - CH1_ENABLE_LLI_RD_DEC_ERR_INTSTAT + ENABLE_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT NA 9 1 - read-write + read-only - CH1_ENABLE_LLI_WR_DEC_ERR_INTSTAT + ENABLE_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT NA 10 1 - read-write + read-only - CH1_ENABLE_LLI_RD_SLV_ERR_INTSTAT + ENABLE_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT NA 11 1 - read-write + read-only - CH1_ENABLE_LLI_WR_SLV_ERR_INTSTAT + ENABLE_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT NA 12 1 - read-write + read-only - CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT + ENABLE_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT NA 13 1 - read-write + read-only - CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT + ENABLE_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT NA 14 1 - read-write + read-only - CH1_ENABLE_SLVIF_DEC_ERR_INTSTAT + ENABLE_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT + NA + 15 + 1 + read-only + + + ENABLE_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT NA 16 1 - read-write + read-only - CH1_ENABLE_SLVIF_WR2RO_ERR_INTSTAT + ENABLE_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT NA 17 1 - read-write + read-only - CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT + ENABLE_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT NA 18 1 - read-write + read-only - CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT + ENABLE_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT NA 19 1 - read-write + read-only - CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT + ENABLE_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT NA 20 1 - read-write + read-only + + + + COMMONREG_INTSIGNAL_ENABLE0 + NA + 0x48 + 0x20 + 0x001FFF8F + - CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT + ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSIGNAL NA - 21 + 0 1 read-write - CH1_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT + ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSIGNAL NA - 25 + 1 1 - read-only + read-write - CH1_ENABLE_CH_LOCK_CLEARED_INTSTAT + ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSIGNAL NA - 27 + 2 1 read-write - CH1_ENABLE_CH_SRC_SUSPENDED_INTSTAT + ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSIGNAL NA - 28 + 3 1 read-write - CH1_ENABLE_CH_SUSPENDED_INTSTAT + ENABLE_SLVIF_COMMONREG_WRPARITY_ERR_INTSIGNAL NA - 29 + 7 1 - read-write + read-only - CH1_ENABLE_CH_DISABLED_INTSTAT + ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSIGNAL NA - 30 + 8 1 read-write - CH1_ENABLE_CH_ABORTED_INTSTAT + ENABLE_MXIF1_RCH0_ECCPROT_CORRERR_INTSIGNAL NA - 31 + 9 1 - read-write + read-only - - - - CH1_INTSTATUS_ENABLE1 - NA - 0x184 - 0x20 - 0x0000000F - - CH1_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT + ENABLE_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSIGNAL NA - 0 + 10 1 read-only - CH1_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT + ENABLE_MXIF1_RCH1_ECCPROT_CORRERR_INTSIGNAL NA - 1 + 11 1 read-only - CH1_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT + ENABLE_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSIGNAL NA - 2 + 12 1 read-only - CH1_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT + ENABLE_MXIF1_BCH_ECCPROT_CORRERR_INTSIGNAL NA - 3 + 13 1 read-only - - - - CH1_INTSTATUS0 - NA - 0x188 - 0x20 - - CH1_BLOCK_TFR_DONE_INTSTAT + ENABLE_MXIF1_BCH_ECCPROT_UNCORRERR_INTSIGNAL NA - 0 + 14 1 read-only - CH1_DMA_TFR_DONE_INTSTAT + ENABLE_MXIF2_RCH0_ECCPROT_CORRERR_INTSIGNAL NA - 1 + 15 1 read-only - CH1_SRC_TRANSCOMP_INTSTAT + ENABLE_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSIGNAL NA - 3 + 16 1 read-only - CH1_DST_TRANSCOMP_INTSTAT + ENABLE_MXIF2_RCH1_ECCPROT_CORRERR_INTSIGNAL NA - 4 + 17 1 read-only - CH1_SRC_DEC_ERR_INTSTAT + ENABLE_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSIGNAL NA - 5 + 18 1 read-only - CH1_DST_DEC_ERR_INTSTAT + ENABLE_MXIF2_BCH_ECCPROT_CORRERR_INTSIGNAL NA - 6 + 19 1 read-only - CH1_SRC_SLV_ERR_INTSTAT + ENABLE_MXIF2_BCH_ECCPROT_UNCORRERR_INTSIGNAL NA - 7 + 20 1 read-only + + + + COMMONREG_INTSTATUS0 + NA + 0x50 + 0x20 + - CH1_DST_SLV_ERR_INTSTAT + SLVIF_COMMONREG_DEC_ERR_INTSTAT NA - 8 + 0 1 read-only - CH1_LLI_RD_DEC_ERR_INTSTAT + SLVIF_COMMONREG_WR2RO_ERR_INTSTAT NA - 9 + 1 1 read-only - CH1_LLI_WR_DEC_ERR_INTSTAT + SLVIF_COMMONREG_RD2WO_ERR_INTSTAT NA - 10 + 2 1 read-only - CH1_LLI_RD_SLV_ERR_INTSTAT + SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT NA - 11 + 3 1 read-only - CH1_LLI_WR_SLV_ERR_INTSTAT + SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT NA - 12 + 7 1 read-only - CH1_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT + SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT NA - 13 + 8 1 read-only - CH1_SLVIF_MULTIBLKTYPE_ERR_INTSTAT + MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT NA - 14 + 9 1 read-only - CH1_SLVIF_DEC_ERR_INTSTAT + MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT NA - 16 + 10 1 read-only - CH1_SLVIF_WR2RO_ERR_INTSTAT + MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT NA - 17 + 11 1 read-only - CH1_SLVIF_RD2RWO_ERR_INTSTAT + MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT NA - 18 + 12 1 read-only - CH1_SLVIF_WRONCHEN_ERR_INTSTAT + MXIF1_BCH_ECCPROT_CORRERR_INTSTAT NA - 19 + 13 1 read-only - CH1_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT + MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT NA - 20 + 14 1 read-only - CH1_SLVIF_WRONHOLD_ERR_INTSTAT + MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT NA - 21 + 15 1 read-only - CH1_SLVIF_WRPARITY_ERR_INTSTAT + MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT NA - 25 + 16 1 read-only - CH1_CH_LOCK_CLEARED_INTSTAT + MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT NA - 27 + 17 1 read-only - CH1_CH_SRC_SUSPENDED_INTSTAT + MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT NA - 28 + 18 1 read-only - CH1_CH_SUSPENDED_INTSTAT + MXIF2_BCH_ECCPROT_CORRERR_INTSTAT NA - 29 + 19 1 read-only - CH1_CH_DISABLED_INTSTAT + MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT NA - 30 + 20 1 read-only + + + + RESET0 + NA + 0x58 + 0x20 + - CH1_CH_ABORTED_INTSTAT + DMAC_RST NA - 31 + 0 1 - read-only + read-write - CH1_INTSTATUS1 + LOWPOWER_CFG0 NA - 0x18C + 0x60 0x20 + 0x0000000F - CH1_ECC_PROT_CHMEM_CORRERR_INTSTAT + GBL_CSLP_EN NA 0 1 - read-only + read-write - CH1_ECC_PROT_CHMEM_UNCORRERR_INTSTAT + CHNL_CSLP_EN NA 1 1 - read-only + read-write - CH1_ECC_PROT_UIDMEM_CORRERR_INTSTAT + SBIU_CSLP_EN NA 2 1 - read-only + read-write - CH1_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT + MXIF_CSLP_EN NA 3 1 - read-only + read-write - CH1_INTSIGNAL_ENABLE0 + LOWPOWER_CFG1 NA - 0x190 + 0x64 0x20 - 0xFA3F7FFB + 0x00404040 - CH1_ENABLE_BLOCK_TFR_DONE_INTSIGNAL + GLCH_LPDLY NA 0 - 1 + 8 read-write - CH1_ENABLE_DMA_TFR_DONE_INTSIGNAL + SBIU_LPDLY NA - 1 - 1 + 8 + 8 read-write - CH1_ENABLE_SRC_TRANSCOMP_INTSIGNAL + MXIF_LPDLY NA - 3 - 1 + 16 + 8 read-write + + + + CH1_SAR0 + NA + 0x100 + 0x20 + - CH1_ENABLE_DST_TRANSCOMP_INTSIGNAL + CH1_SAR0 NA - 4 - 1 + 0 + 32 read-write + + + + CH1_SAR1 + NA + 0x104 + 0x20 + - CH1_ENABLE_SRC_DEC_ERR_INTSIGNAL + CH1_SAR1 NA - 5 - 1 + 0 + 32 read-write + + + + CH1_DAR0 + NA + 0x108 + 0x20 + - CH1_ENABLE_DST_DEC_ERR_INTSIGNAL + CH1_DAR0 NA - 6 - 1 + 0 + 32 read-write + + + + CH1_DAR1 + NA + 0x10C + 0x20 + - CH1_ENABLE_SRC_SLV_ERR_INTSIGNAL + CH1_DAR1 NA - 7 - 1 + 0 + 32 read-write + + + + CH1_BLOCK_TS0 + NA + 0x110 + 0x20 + - CH1_ENABLE_DST_SLV_ERR_INTSIGNAL + CH1_BLOCK_TS NA - 8 - 1 + 0 + 22 read-write + + + + CH1_CTL0 + NA + 0x118 + 0x20 + 0x00001200 + - CH1_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL + CH1_SMS NA - 9 + 0 1 read-write - CH1_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL + CH1_DMS NA - 10 + 2 1 read-write - CH1_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL + CH1_SINC NA - 11 + 4 1 read-write - CH1_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL + CH1_DINC NA - 12 + 6 1 read-write - CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL + CH1_SRC_TR_WIDTH NA - 13 - 1 + 8 + 3 read-write - CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL + CH1_DST_TR_WIDTH NA - 14 - 1 + 11 + 3 read-write - CH1_ENABLE_SLVIF_DEC_ERR_INTSIGNAL + CH1_SRC_MSIZE NA - 16 - 1 + 14 + 4 read-write - CH1_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL + CH1_DST_MSIZE NA - 17 - 1 + 18 + 4 read-write - CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL + CH1_AR_CACHE NA - 18 - 1 + 22 + 4 read-write - CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL + CH1_AW_CACHE NA - 19 - 1 + 26 + 4 read-write - CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL + CH1_NONPOSTED_LASTWRITE_EN NA - 20 + 30 1 read-write + + + + CH1_CTL1 + NA + 0x11C + 0x20 + - CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL + CH1_AR_PROT NA - 21 - 1 + 0 + 3 read-write - CH1_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL - NA - 25 - 1 - read-only - - - CH1_ENABLE_CH_LOCK_CLEARED_INTSIGNAL - NA - 27 - 1 - read-write - - - CH1_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL - NA - 28 - 1 - read-write - - - CH1_ENABLE_CH_SUSPENDED_INTSIGNAL - NA - 29 - 1 - read-write - - - CH1_ENABLE_CH_DISABLED_INTSIGNAL - NA - 30 - 1 - read-write - - - CH1_ENABLE_CH_ABORTED_INTSIGNAL - NA - 31 - 1 - read-write - - - - - CH1_INTSIGNAL_ENABLE1 - NA - 0x194 - 0x20 - 0x0000000F - - - CH1_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL - NA - 0 - 1 - read-only - - - CH1_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL - NA - 1 - 1 - read-only - - - CH1_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL - NA - 2 - 1 - read-only - - - CH1_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL - NA - 3 - 1 - read-only - - - - - CH1_INTCLEAR0 - NA - 0x198 - 0x20 - - - CH1_CLEAR_BLOCK_TFR_DONE_INTSTAT - NA - 0 - 1 - write-only - - - CH1_CLEAR_DMA_TFR_DONE_INTSTAT - NA - 1 - 1 - write-only - - - CH1_CLEAR_SRC_TRANSCOMP_INTSTAT - NA - 3 - 1 - write-only - - - CH1_CLEAR_DST_TRANSCOMP_INTSTAT - NA - 4 - 1 - write-only - - - CH1_CLEAR_SRC_DEC_ERR_INTSTAT - NA - 5 - 1 - write-only - - - CH1_CLEAR_DST_DEC_ERR_INTSTAT - NA - 6 - 1 - write-only - - - CH1_CLEAR_SRC_SLV_ERR_INTSTAT - NA - 7 - 1 - write-only - - - CH1_CLEAR_DST_SLV_ERR_INTSTAT - NA - 8 - 1 - write-only - - - CH1_CLEAR_LLI_RD_DEC_ERR_INTSTAT - NA - 9 - 1 - write-only - - - CH1_CLEAR_LLI_WR_DEC_ERR_INTSTAT - NA - 10 - 1 - write-only - - - CH1_CLEAR_LLI_RD_SLV_ERR_INTSTAT - NA - 11 - 1 - write-only - - - CH1_CLEAR_LLI_WR_SLV_ERR_INTSTAT - NA - 12 - 1 - write-only - - - CH1_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT - NA - 13 - 1 - write-only - - - CH1_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT - NA - 14 - 1 - write-only - - - CH1_CLEAR_SLVIF_DEC_ERR_INTSTAT - NA - 16 - 1 - write-only - - - CH1_CLEAR_SLVIF_WR2RO_ERR_INTSTAT - NA - 17 - 1 - write-only - - - CH1_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT - NA - 18 - 1 - write-only - - - CH1_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT - NA - 19 - 1 - write-only - - - CH1_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT - NA - 20 - 1 - write-only - - - CH1_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT - NA - 21 - 1 - write-only - - - CH1_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT - NA - 25 - 1 - write-only - - - CH1_CLEAR_CH_LOCK_CLEARED_INTSTAT - NA - 27 - 1 - write-only - - - CH1_CLEAR_CH_SRC_SUSPENDED_INTSTAT - NA - 28 - 1 - write-only - - - CH1_CLEAR_CH_SUSPENDED_INTSTAT - NA - 29 - 1 - write-only - - - CH1_CLEAR_CH_DISABLED_INTSTAT - NA - 30 - 1 - write-only - - - CH1_CLEAR_CH_ABORTED_INTSTAT - NA - 31 - 1 - write-only - - - - - CH1_INTCLEAR1 - NA - 0x19C - 0x20 - - - CH1_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT - NA - 0 - 1 - write-only - - - CH1_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT - NA - 1 - 1 - write-only - - - CH1_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT - NA - 2 - 1 - write-only - - - CH1_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT - NA - 3 - 1 - write-only - - - - - CH2_SAR0 - NA - 0x200 - 0x20 - - - CH2_SAR0 - NA - 0 - 32 - read-write - - - - - CH2_SAR1 - NA - 0x204 - 0x20 - - - CH2_SAR1 - NA - 0 - 32 - read-write - - - - - CH2_DAR0 - NA - 0x208 - 0x20 - - - CH2_DAR0 - NA - 0 - 32 - read-write - - - - - CH2_DAR1 - NA - 0x20C - 0x20 - - - CH2_DAR1 - NA - 0 - 32 - read-write - - - - - CH2_BLOCK_TS0 - NA - 0x210 - 0x20 - - - CH2_BLOCK_TS - NA - 0 - 22 - read-write - - - - - CH2_CTL0 - NA - 0x218 - 0x20 - 0x00001200 - - - CH2_SMS - NA - 0 - 1 - read-write - - - CH2_DMS - NA - 2 - 1 - read-write - - - CH2_SINC - NA - 4 - 1 - read-write - - - CH2_DINC - NA - 6 - 1 - read-write - - - CH2_SRC_TR_WIDTH - NA - 8 - 3 - read-write - - - CH2_DST_TR_WIDTH - NA - 11 - 3 - read-write - - - CH2_SRC_MSIZE - NA - 14 - 4 - read-write - - - CH2_DST_MSIZE - NA - 18 - 4 - read-write - - - CH2_AR_CACHE - NA - 22 - 4 - read-write - - - CH2_AW_CACHE - NA - 26 - 4 - read-write - - - CH2_NONPOSTED_LASTWRITE_EN - NA - 30 - 1 - read-write - - - - - CH2_CTL1 - NA - 0x21C - 0x20 - - - CH2_AR_PROT - NA - 0 - 3 - read-write - - - CH2_AW_PROT + CH1_AW_PROT NA 3 3 read-write - CH2_ARLEN_EN + CH1_ARLEN_EN NA 6 1 read-write - CH2_ARLEN + CH1_ARLEN NA 7 8 read-write - CH2_AWLEN_EN + CH1_AWLEN_EN NA 15 1 read-write - CH2_AWLEN + CH1_AWLEN NA 16 8 read-write - CH2_SRC_STAT_EN + CH1_SRC_STAT_EN NA 24 1 read-write - CH2_DST_STAT_EN + CH1_DST_STAT_EN NA 25 1 read-write - CH2_IOC_BLKTFR + CH1_IOC_BLKTFR NA 26 1 read-write - CH2_SHADOWREG_OR_LLI_LAST + CH1_SHADOWREG_OR_LLI_LAST NA 30 1 read-write - CH2_SHADOWREG_OR_LLI_VALID + CH1_SHADOWREG_OR_LLI_VALID NA 31 1 @@ -23377,34 +23598,34 @@ - CH2_CFG0 + CH1_CFG0 NA - 0x220 + 0x120 0x20 - CH2_SRC_MULTBLK_TYPE + CH1_SRC_MULTBLK_TYPE NA 0 2 read-write - CH2_DST_MULTBLK_TYPE + CH1_DST_MULTBLK_TYPE NA 2 2 read-write - CH2_RD_UID + CH1_RD_UID NA 18 4 read-only - CH2_WR_UID + CH1_WR_UID NA 25 4 @@ -23413,91 +23634,91 @@ - CH2_CFG1 + CH1_CFG1 NA - 0x224 + 0x124 0x20 - 0x0004001B + 0x0006001B - CH2_TT_FC + CH1_TT_FC NA 0 3 read-write - CH2_HS_SEL_SRC + CH1_HS_SEL_SRC NA 3 1 read-write - CH2_HS_SEL_DST + CH1_HS_SEL_DST NA 4 1 read-write - CH2_SRC_HWHS_POL + CH1_SRC_HWHS_POL NA 5 1 read-only - CH2_DST_HWHS_POL + CH1_DST_HWHS_POL NA 6 1 read-only - CH2_SRC_PER + CH1_SRC_PER NA 7 2 read-write - CH2_DST_PER + CH1_DST_PER NA 12 2 read-write - CH2_CH_PRIOR + CH1_CH_PRIOR NA 17 3 read-write - CH2_LOCK_CH + CH1_LOCK_CH NA 20 1 read-only - CH2_LOCK_CH_L + CH1_LOCK_CH_L NA 21 2 read-only - CH2_SRC_OSR_LMT + CH1_SRC_OSR_LMT NA 23 4 read-write - CH2_DST_OSR_LMT + CH1_DST_OSR_LMT NA 27 4 @@ -23506,20 +23727,20 @@ - CH2_LLP0 + CH1_LLP0 NA - 0x228 + 0x128 0x20 - CH2_LMS + CH1_LMS NA 0 1 read-write - CH2_LOC0 + CH1_LOC0 NA 6 26 @@ -23528,13 +23749,13 @@ - CH2_LLP1 + CH1_LLP1 NA - 0x22C + 0x12C 0x20 - CH2_LOC1 + CH1_LOC1 NA 0 32 @@ -23543,13 +23764,13 @@ - CH2_STATUS0 + CH1_STATUS0 NA - 0x230 + 0x130 0x20 - CH2_CMPLTD_BLK_TFR_SIZE + CH1_CMPLTD_BLK_TFR_SIZE NA 0 22 @@ -23558,13 +23779,13 @@ - CH2_STATUS1 + CH1_STATUS1 NA - 0x234 + 0x134 0x20 - CH2_DATA_LEFT_IN_FIFO + CH1_DATA_LEFT_IN_FIFO NA 0 15 @@ -23573,48 +23794,48 @@ - CH2_SWHSSRC0 + CH1_SWHSSRC0 NA - 0x238 + 0x138 0x20 - CH2_SWHS_REQ_SRC + CH1_SWHS_REQ_SRC NA 0 1 read-write - CH2_SWHS_REQ_SRC_WE + CH1_SWHS_REQ_SRC_WE NA 1 1 write-only - CH2_SWHS_SGLREQ_SRC + CH1_SWHS_SGLREQ_SRC NA 2 1 read-write - CH2_SWHS_SGLREQ_SRC_WE + CH1_SWHS_SGLREQ_SRC_WE NA 3 1 write-only - CH2_SWHS_LST_SRC + CH1_SWHS_LST_SRC NA 4 1 read-write - CH2_SWHS_LST_SRC_WE + CH1_SWHS_LST_SRC_WE NA 5 1 @@ -23623,48 +23844,48 @@ - CH2_SWHSDST0 + CH1_SWHSDST0 NA - 0x240 + 0x140 0x20 - CH2_SWHS_REQ_DST + CH1_SWHS_REQ_DST NA 0 1 read-write - CH2_SWHS_REQ_DST_WE + CH1_SWHS_REQ_DST_WE NA 1 1 write-only - CH2_SWHS_SGLREQ_DST + CH1_SWHS_SGLREQ_DST NA 2 1 read-write - CH2_SWHS_SGLREQ_DST_WE + CH1_SWHS_SGLREQ_DST_WE NA 3 1 write-only - CH2_SWHS_LST_DST + CH1_SWHS_LST_DST NA 4 1 read-write - CH2_SWHS_LST_DST_WE + CH1_SWHS_LST_DST_WE NA 5 1 @@ -23673,13 +23894,13 @@ - CH2_BLK_TFR_RESUMEREQ0 + CH1_BLK_TFR_RESUMEREQ0 NA - 0x248 + 0x148 0x20 - CH2_BLK_TFR_RESUMEREQ + CH1_BLK_TFR_RESUMEREQ NA 0 1 @@ -23688,20 +23909,20 @@ - CH2_AXI_ID0 + CH1_AXI_ID0 NA - 0x250 + 0x150 0x20 - CH2_AXI_READ_ID_SUFFIX + CH1_AXI_READ_ID_SUFFIX NA 0 1 read-write - CH2_AXI_WRITE_ID_SUFFIX + CH1_AXI_WRITE_ID_SUFFIX NA 16 1 @@ -23710,20 +23931,20 @@ - CH2_AXI_QOS0 + CH1_AXI_QOS0 NA - 0x258 + 0x158 0x20 - CH2_AXI_AWQOS + CH1_AXI_AWQOS NA 0 4 read-write - CH2_AXI_ARQOS + CH1_AXI_ARQOS NA 4 4 @@ -23732,13 +23953,13 @@ - CH2_SSTAT0 + CH1_SSTAT0 NA - 0x260 + 0x160 0x20 - CH2_SSTAT + CH1_SSTAT NA 0 32 @@ -23747,13 +23968,13 @@ - CH2_DSTAT0 + CH1_DSTAT0 NA - 0x268 + 0x168 0x20 - CH2_DSTAT + CH1_DSTAT NA 0 32 @@ -23762,13 +23983,13 @@ - CH2_SSTATAR0 + CH1_SSTATAR0 NA - 0x270 + 0x170 0x20 - CH2_SSTATAR0 + CH1_SSTATAR0 NA 0 32 @@ -23777,13 +23998,13 @@ - CH2_SSTATAR1 + CH1_SSTATAR1 NA - 0x274 + 0x174 0x20 - CH2_SSTATAR1 + CH1_SSTATAR1 NA 0 32 @@ -23792,13 +24013,13 @@ - CH2_DSTATAR0 + CH1_DSTATAR0 NA - 0x278 + 0x178 0x20 - CH2_DSTATAR0 + CH1_DSTATAR0 NA 0 32 @@ -23807,13 +24028,13 @@ - CH2_DSTATAR1 + CH1_DSTATAR1 NA - 0x27C + 0x17C 0x20 - CH2_DSTATAR1 + CH1_DSTATAR1 NA 0 32 @@ -23822,189 +24043,189 @@ - CH2_INTSTATUS_ENABLE0 + CH1_INTSTATUS_ENABLE0 NA - 0x280 + 0x180 0x20 0xFA3F7FFB - CH2_ENABLE_BLOCK_TFR_DONE_INTSTAT + CH1_ENABLE_BLOCK_TFR_DONE_INTSTAT NA 0 1 read-write - CH2_ENABLE_DMA_TFR_DONE_INTSTAT + CH1_ENABLE_DMA_TFR_DONE_INTSTAT NA 1 1 read-write - CH2_ENABLE_SRC_TRANSCOMP_INTSTAT + CH1_ENABLE_SRC_TRANSCOMP_INTSTAT NA 3 1 read-write - CH2_ENABLE_DST_TRANSCOMP_INTSTAT + CH1_ENABLE_DST_TRANSCOMP_INTSTAT NA 4 1 read-write - CH2_ENABLE_SRC_DEC_ERR_INTSTAT + CH1_ENABLE_SRC_DEC_ERR_INTSTAT NA 5 1 read-write - CH2_ENABLE_DST_DEC_ERR_INTSTAT + CH1_ENABLE_DST_DEC_ERR_INTSTAT NA 6 1 read-write - CH2_ENABLE_SRC_SLV_ERR_INTSTAT + CH1_ENABLE_SRC_SLV_ERR_INTSTAT NA 7 1 read-write - CH2_ENABLE_DST_SLV_ERR_INTSTAT + CH1_ENABLE_DST_SLV_ERR_INTSTAT NA 8 1 read-write - CH2_ENABLE_LLI_RD_DEC_ERR_INTSTAT + CH1_ENABLE_LLI_RD_DEC_ERR_INTSTAT NA 9 1 read-write - CH2_ENABLE_LLI_WR_DEC_ERR_INTSTAT + CH1_ENABLE_LLI_WR_DEC_ERR_INTSTAT NA 10 1 read-write - CH2_ENABLE_LLI_RD_SLV_ERR_INTSTAT + CH1_ENABLE_LLI_RD_SLV_ERR_INTSTAT NA 11 1 read-write - CH2_ENABLE_LLI_WR_SLV_ERR_INTSTAT + CH1_ENABLE_LLI_WR_SLV_ERR_INTSTAT NA 12 1 read-write - CH2_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT + CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT NA 13 1 read-write - CH2_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT + CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT NA 14 1 read-write - CH2_ENABLE_SLVIF_DEC_ERR_INTSTAT + CH1_ENABLE_SLVIF_DEC_ERR_INTSTAT NA 16 1 read-write - CH2_ENABLE_SLVIF_WR2RO_ERR_INTSTAT + CH1_ENABLE_SLVIF_WR2RO_ERR_INTSTAT NA 17 1 read-write - CH2_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT + CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT NA 18 1 read-write - CH2_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT + CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT NA 19 1 read-write - CH2_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT + CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT NA 20 1 read-write - CH2_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT + CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT NA 21 1 read-write - CH2_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT + CH1_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT NA 25 1 read-only - CH2_ENABLE_CH_LOCK_CLEARED_INTSTAT + CH1_ENABLE_CH_LOCK_CLEARED_INTSTAT NA 27 1 read-write - CH2_ENABLE_CH_SRC_SUSPENDED_INTSTAT + CH1_ENABLE_CH_SRC_SUSPENDED_INTSTAT NA 28 1 read-write - CH2_ENABLE_CH_SUSPENDED_INTSTAT + CH1_ENABLE_CH_SUSPENDED_INTSTAT NA 29 1 read-write - CH2_ENABLE_CH_DISABLED_INTSTAT + CH1_ENABLE_CH_DISABLED_INTSTAT NA 30 1 read-write - CH2_ENABLE_CH_ABORTED_INTSTAT + CH1_ENABLE_CH_ABORTED_INTSTAT NA 31 1 @@ -24013,35 +24234,35 @@ - CH2_INTSTATUS_ENABLE1 + CH1_INTSTATUS_ENABLE1 NA - 0x284 + 0x184 0x20 0x0000000F - CH2_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT + CH1_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT NA 0 1 read-only - CH2_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT + CH1_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT NA 1 1 read-only - CH2_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT + CH1_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT NA 2 1 read-only - CH2_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT + CH1_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT NA 3 1 @@ -24050,188 +24271,188 @@ - CH2_INTSTATUS0 + CH1_INTSTATUS0 NA - 0x288 + 0x188 0x20 - CH2_BLOCK_TFR_DONE_INTSTAT + CH1_BLOCK_TFR_DONE_INTSTAT NA 0 1 read-only - CH2_DMA_TFR_DONE_INTSTAT + CH1_DMA_TFR_DONE_INTSTAT NA 1 1 read-only - CH2_SRC_TRANSCOMP_INTSTAT + CH1_SRC_TRANSCOMP_INTSTAT NA 3 1 read-only - CH2_DST_TRANSCOMP_INTSTAT + CH1_DST_TRANSCOMP_INTSTAT NA 4 1 read-only - CH2_SRC_DEC_ERR_INTSTAT + CH1_SRC_DEC_ERR_INTSTAT NA 5 1 read-only - CH2_DST_DEC_ERR_INTSTAT + CH1_DST_DEC_ERR_INTSTAT NA 6 1 read-only - CH2_SRC_SLV_ERR_INTSTAT + CH1_SRC_SLV_ERR_INTSTAT NA 7 1 read-only - CH2_DST_SLV_ERR_INTSTAT + CH1_DST_SLV_ERR_INTSTAT NA 8 1 read-only - CH2_LLI_RD_DEC_ERR_INTSTAT + CH1_LLI_RD_DEC_ERR_INTSTAT NA 9 1 read-only - CH2_LLI_WR_DEC_ERR_INTSTAT + CH1_LLI_WR_DEC_ERR_INTSTAT NA 10 1 read-only - CH2_LLI_RD_SLV_ERR_INTSTAT + CH1_LLI_RD_SLV_ERR_INTSTAT NA 11 1 read-only - CH2_LLI_WR_SLV_ERR_INTSTAT + CH1_LLI_WR_SLV_ERR_INTSTAT NA 12 1 read-only - CH2_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT + CH1_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT NA 13 1 read-only - CH2_SLVIF_MULTIBLKTYPE_ERR_INTSTAT + CH1_SLVIF_MULTIBLKTYPE_ERR_INTSTAT NA 14 1 read-only - CH2_SLVIF_DEC_ERR_INTSTAT + CH1_SLVIF_DEC_ERR_INTSTAT NA 16 1 read-only - CH2_SLVIF_WR2RO_ERR_INTSTAT + CH1_SLVIF_WR2RO_ERR_INTSTAT NA 17 1 read-only - CH2_SLVIF_RD2RWO_ERR_INTSTAT + CH1_SLVIF_RD2RWO_ERR_INTSTAT NA 18 1 read-only - CH2_SLVIF_WRONCHEN_ERR_INTSTAT + CH1_SLVIF_WRONCHEN_ERR_INTSTAT NA 19 1 read-only - CH2_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT + CH1_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT NA 20 1 read-only - CH2_SLVIF_WRONHOLD_ERR_INTSTAT + CH1_SLVIF_WRONHOLD_ERR_INTSTAT NA 21 1 read-only - CH2_SLVIF_WRPARITY_ERR_INTSTAT + CH1_SLVIF_WRPARITY_ERR_INTSTAT NA 25 1 read-only - CH2_CH_LOCK_CLEARED_INTSTAT + CH1_CH_LOCK_CLEARED_INTSTAT NA 27 1 read-only - CH2_CH_SRC_SUSPENDED_INTSTAT + CH1_CH_SRC_SUSPENDED_INTSTAT NA 28 1 read-only - CH2_CH_SUSPENDED_INTSTAT + CH1_CH_SUSPENDED_INTSTAT NA 29 1 read-only - CH2_CH_DISABLED_INTSTAT + CH1_CH_DISABLED_INTSTAT NA 30 1 read-only - CH2_CH_ABORTED_INTSTAT + CH1_CH_ABORTED_INTSTAT NA 31 1 @@ -24240,34 +24461,34 @@ - CH2_INTSTATUS1 + CH1_INTSTATUS1 NA - 0x28C + 0x18C 0x20 - CH2_ECC_PROT_CHMEM_CORRERR_INTSTAT + CH1_ECC_PROT_CHMEM_CORRERR_INTSTAT NA 0 1 read-only - CH2_ECC_PROT_CHMEM_UNCORRERR_INTSTAT + CH1_ECC_PROT_CHMEM_UNCORRERR_INTSTAT NA 1 1 read-only - CH2_ECC_PROT_UIDMEM_CORRERR_INTSTAT + CH1_ECC_PROT_UIDMEM_CORRERR_INTSTAT NA 2 1 read-only - CH2_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT + CH1_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT NA 3 1 @@ -24276,189 +24497,189 @@ - CH2_INTSIGNAL_ENABLE0 + CH1_INTSIGNAL_ENABLE0 NA - 0x290 + 0x190 0x20 0xFA3F7FFB - CH2_ENABLE_BLOCK_TFR_DONE_INTSIGNAL + CH1_ENABLE_BLOCK_TFR_DONE_INTSIGNAL NA 0 1 read-write - CH2_ENABLE_DMA_TFR_DONE_INTSIGNAL + CH1_ENABLE_DMA_TFR_DONE_INTSIGNAL NA 1 1 read-write - CH2_ENABLE_SRC_TRANSCOMP_INTSIGNAL + CH1_ENABLE_SRC_TRANSCOMP_INTSIGNAL NA 3 1 read-write - CH2_ENABLE_DST_TRANSCOMP_INTSIGNAL + CH1_ENABLE_DST_TRANSCOMP_INTSIGNAL NA 4 1 read-write - CH2_ENABLE_SRC_DEC_ERR_INTSIGNAL + CH1_ENABLE_SRC_DEC_ERR_INTSIGNAL NA 5 1 read-write - CH2_ENABLE_DST_DEC_ERR_INTSIGNAL + CH1_ENABLE_DST_DEC_ERR_INTSIGNAL NA 6 1 read-write - CH2_ENABLE_SRC_SLV_ERR_INTSIGNAL + CH1_ENABLE_SRC_SLV_ERR_INTSIGNAL NA 7 1 read-write - CH2_ENABLE_DST_SLV_ERR_INTSIGNAL + CH1_ENABLE_DST_SLV_ERR_INTSIGNAL NA 8 1 read-write - CH2_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL + CH1_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL NA 9 1 read-write - CH2_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL + CH1_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL NA 10 1 read-write - CH2_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL + CH1_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL NA 11 1 read-write - CH2_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL + CH1_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL NA 12 1 read-write - CH2_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL + CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL NA 13 1 read-write - CH2_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL + CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL NA 14 1 read-write - CH2_ENABLE_SLVIF_DEC_ERR_INTSIGNAL + CH1_ENABLE_SLVIF_DEC_ERR_INTSIGNAL NA 16 1 read-write - CH2_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL + CH1_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL NA 17 1 read-write - CH2_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL + CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL NA 18 1 read-write - CH2_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL + CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL NA 19 1 read-write - CH2_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL + CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL NA 20 1 read-write - CH2_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL + CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL NA 21 1 read-write - CH2_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL + CH1_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL NA 25 1 read-only - CH2_ENABLE_CH_LOCK_CLEARED_INTSIGNAL + CH1_ENABLE_CH_LOCK_CLEARED_INTSIGNAL NA 27 1 read-write - CH2_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL + CH1_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL NA 28 1 read-write - CH2_ENABLE_CH_SUSPENDED_INTSIGNAL + CH1_ENABLE_CH_SUSPENDED_INTSIGNAL NA 29 1 read-write - CH2_ENABLE_CH_DISABLED_INTSIGNAL + CH1_ENABLE_CH_DISABLED_INTSIGNAL NA 30 1 read-write - CH2_ENABLE_CH_ABORTED_INTSIGNAL + CH1_ENABLE_CH_ABORTED_INTSIGNAL NA 31 1 @@ -24467,35 +24688,35 @@ - CH2_INTSIGNAL_ENABLE1 + CH1_INTSIGNAL_ENABLE1 NA - 0x294 + 0x194 0x20 0x0000000F - CH2_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL + CH1_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL NA 0 1 read-only - CH2_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL + CH1_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL NA 1 1 read-only - CH2_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL + CH1_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL NA 2 1 read-only - CH2_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL + CH1_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL NA 3 1 @@ -24504,188 +24725,188 @@ - CH2_INTCLEAR0 + CH1_INTCLEAR0 NA - 0x298 + 0x198 0x20 - CH2_CLEAR_BLOCK_TFR_DONE_INTSTAT + CH1_CLEAR_BLOCK_TFR_DONE_INTSTAT NA 0 1 write-only - CH2_CLEAR_DMA_TFR_DONE_INTSTAT + CH1_CLEAR_DMA_TFR_DONE_INTSTAT NA 1 1 write-only - CH2_CLEAR_SRC_TRANSCOMP_INTSTAT + CH1_CLEAR_SRC_TRANSCOMP_INTSTAT NA 3 1 write-only - CH2_CLEAR_DST_TRANSCOMP_INTSTAT + CH1_CLEAR_DST_TRANSCOMP_INTSTAT NA 4 1 write-only - CH2_CLEAR_SRC_DEC_ERR_INTSTAT + CH1_CLEAR_SRC_DEC_ERR_INTSTAT NA 5 1 write-only - CH2_CLEAR_DST_DEC_ERR_INTSTAT + CH1_CLEAR_DST_DEC_ERR_INTSTAT NA 6 1 write-only - CH2_CLEAR_SRC_SLV_ERR_INTSTAT + CH1_CLEAR_SRC_SLV_ERR_INTSTAT NA 7 1 write-only - CH2_CLEAR_DST_SLV_ERR_INTSTAT + CH1_CLEAR_DST_SLV_ERR_INTSTAT NA 8 1 write-only - CH2_CLEAR_LLI_RD_DEC_ERR_INTSTAT + CH1_CLEAR_LLI_RD_DEC_ERR_INTSTAT NA 9 1 write-only - CH2_CLEAR_LLI_WR_DEC_ERR_INTSTAT + CH1_CLEAR_LLI_WR_DEC_ERR_INTSTAT NA 10 1 write-only - CH2_CLEAR_LLI_RD_SLV_ERR_INTSTAT + CH1_CLEAR_LLI_RD_SLV_ERR_INTSTAT NA 11 1 write-only - CH2_CLEAR_LLI_WR_SLV_ERR_INTSTAT + CH1_CLEAR_LLI_WR_SLV_ERR_INTSTAT NA 12 1 write-only - CH2_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT + CH1_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT NA 13 1 write-only - CH2_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT + CH1_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT NA 14 1 write-only - CH2_CLEAR_SLVIF_DEC_ERR_INTSTAT + CH1_CLEAR_SLVIF_DEC_ERR_INTSTAT NA 16 1 write-only - CH2_CLEAR_SLVIF_WR2RO_ERR_INTSTAT + CH1_CLEAR_SLVIF_WR2RO_ERR_INTSTAT NA 17 1 write-only - CH2_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT + CH1_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT NA 18 1 write-only - CH2_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT + CH1_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT NA 19 1 write-only - CH2_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT + CH1_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT NA 20 1 write-only - CH2_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT + CH1_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT NA 21 1 write-only - CH2_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT + CH1_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT NA 25 1 write-only - CH2_CLEAR_CH_LOCK_CLEARED_INTSTAT + CH1_CLEAR_CH_LOCK_CLEARED_INTSTAT NA 27 1 write-only - CH2_CLEAR_CH_SRC_SUSPENDED_INTSTAT + CH1_CLEAR_CH_SRC_SUSPENDED_INTSTAT NA 28 1 write-only - CH2_CLEAR_CH_SUSPENDED_INTSTAT + CH1_CLEAR_CH_SUSPENDED_INTSTAT NA 29 1 write-only - CH2_CLEAR_CH_DISABLED_INTSTAT + CH1_CLEAR_CH_DISABLED_INTSTAT NA 30 1 write-only - CH2_CLEAR_CH_ABORTED_INTSTAT + CH1_CLEAR_CH_ABORTED_INTSTAT NA 31 1 @@ -24694,34 +24915,34 @@ - CH2_INTCLEAR1 + CH1_INTCLEAR1 NA - 0x29C + 0x19C 0x20 - CH2_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT + CH1_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT NA 0 1 write-only - CH2_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT + CH1_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT NA 1 1 write-only - CH2_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT + CH1_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT NA 2 1 write-only - CH2_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT + CH1_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT NA 3 1 @@ -24730,13 +24951,13 @@ - CH3_SAR0 + CH2_SAR0 NA - 0x300 + 0x200 0x20 - CH3_SAR0 + CH2_SAR0 NA 0 32 @@ -24745,13 +24966,13 @@ - CH3_SAR1 + CH2_SAR1 NA - 0x304 + 0x204 0x20 - CH3_SAR1 + CH2_SAR1 NA 0 32 @@ -24760,13 +24981,13 @@ - CH3_DAR0 + CH2_DAR0 NA - 0x308 + 0x208 0x20 - CH3_DAR0 + CH2_DAR0 NA 0 32 @@ -24775,13 +24996,13 @@ - CH3_DAR1 + CH2_DAR1 NA - 0x30C + 0x20C 0x20 - CH3_DAR1 + CH2_DAR1 NA 0 32 @@ -24790,13 +25011,13 @@ - CH3_BLOCK_TS0 + CH2_BLOCK_TS0 NA - 0x310 + 0x210 0x20 - CH3_BLOCK_TS + CH2_BLOCK_TS NA 0 22 @@ -24805,84 +25026,84 @@ - CH3_CTL0 + CH2_CTL0 NA - 0x318 + 0x218 0x20 0x00001200 - CH3_SMS + CH2_SMS NA 0 1 read-write - CH3_DMS + CH2_DMS NA 2 1 read-write - CH3_SINC + CH2_SINC NA 4 1 read-write - CH3_DINC + CH2_DINC NA 6 1 read-write - CH3_SRC_TR_WIDTH + CH2_SRC_TR_WIDTH NA 8 3 read-write - CH3_DST_TR_WIDTH + CH2_DST_TR_WIDTH NA 11 3 read-write - CH3_SRC_MSIZE + CH2_SRC_MSIZE NA 14 4 read-write - CH3_DST_MSIZE + CH2_DST_MSIZE NA 18 4 read-write - CH3_AR_CACHE + CH2_AR_CACHE NA 22 4 read-write - CH3_AW_CACHE + CH2_AW_CACHE NA 26 4 read-write - CH3_NONPOSTED_LASTWRITE_EN + CH2_NONPOSTED_LASTWRITE_EN NA 30 1 @@ -24891,83 +25112,83 @@ - CH3_CTL1 + CH2_CTL1 NA - 0x31C + 0x21C 0x20 - CH3_AR_PROT + CH2_AR_PROT NA 0 3 read-write - CH3_AW_PROT + CH2_AW_PROT NA 3 3 read-write - CH3_ARLEN_EN + CH2_ARLEN_EN NA 6 1 read-write - CH3_ARLEN + CH2_ARLEN NA 7 8 read-write - CH3_AWLEN_EN + CH2_AWLEN_EN NA 15 1 read-write - CH3_AWLEN + CH2_AWLEN NA 16 8 read-write - CH3_SRC_STAT_EN + CH2_SRC_STAT_EN NA 24 1 read-write - CH3_DST_STAT_EN + CH2_DST_STAT_EN NA 25 1 read-write - CH3_IOC_BLKTFR + CH2_IOC_BLKTFR NA 26 1 read-write - CH3_SHADOWREG_OR_LLI_LAST + CH2_SHADOWREG_OR_LLI_LAST NA 30 1 read-write - CH3_SHADOWREG_OR_LLI_VALID + CH2_SHADOWREG_OR_LLI_VALID NA 31 1 @@ -24976,34 +25197,34 @@ - CH3_CFG0 + CH2_CFG0 NA - 0x320 + 0x220 0x20 - CH3_SRC_MULTBLK_TYPE + CH2_SRC_MULTBLK_TYPE NA 0 2 read-write - CH3_DST_MULTBLK_TYPE + CH2_DST_MULTBLK_TYPE NA 2 2 read-write - CH3_RD_UID + CH2_RD_UID NA 18 4 read-only - CH3_WR_UID + CH2_WR_UID NA 25 4 @@ -25012,91 +25233,91 @@ - CH3_CFG1 + CH2_CFG1 NA - 0x324 + 0x224 0x20 - 0x0002001B + 0x0004001B - CH3_TT_FC + CH2_TT_FC NA 0 3 read-write - CH3_HS_SEL_SRC + CH2_HS_SEL_SRC NA 3 1 read-write - CH3_HS_SEL_DST + CH2_HS_SEL_DST NA 4 1 read-write - CH3_SRC_HWHS_POL + CH2_SRC_HWHS_POL NA 5 1 read-only - CH3_DST_HWHS_POL + CH2_DST_HWHS_POL NA 6 1 read-only - CH3_SRC_PER + CH2_SRC_PER NA 7 2 read-write - CH3_DST_PER + CH2_DST_PER NA 12 2 read-write - CH3_CH_PRIOR + CH2_CH_PRIOR NA 17 3 read-write - CH3_LOCK_CH + CH2_LOCK_CH NA 20 1 read-only - CH3_LOCK_CH_L + CH2_LOCK_CH_L NA 21 2 read-only - CH3_SRC_OSR_LMT + CH2_SRC_OSR_LMT NA 23 4 read-write - CH3_DST_OSR_LMT + CH2_DST_OSR_LMT NA 27 4 @@ -25105,20 +25326,20 @@ - CH3_LLP0 + CH2_LLP0 NA - 0x328 + 0x228 0x20 - CH3_LMS + CH2_LMS NA 0 1 read-write - CH3_LOC0 + CH2_LOC0 NA 6 26 @@ -25127,13 +25348,13 @@ - CH3_LLP1 + CH2_LLP1 NA - 0x32C + 0x22C 0x20 - CH3_LOC1 + CH2_LOC1 NA 0 32 @@ -25142,13 +25363,13 @@ - CH3_STATUS0 + CH2_STATUS0 NA - 0x330 + 0x230 0x20 - CH3_CMPLTD_BLK_TFR_SIZE + CH2_CMPLTD_BLK_TFR_SIZE NA 0 22 @@ -25157,13 +25378,13 @@ - CH3_STATUS1 + CH2_STATUS1 NA - 0x334 + 0x234 0x20 - CH3_DATA_LEFT_IN_FIFO + CH2_DATA_LEFT_IN_FIFO NA 0 15 @@ -25172,48 +25393,48 @@ - CH3_SWHSSRC0 + CH2_SWHSSRC0 NA - 0x338 + 0x238 0x20 - CH3_SWHS_REQ_SRC + CH2_SWHS_REQ_SRC NA 0 1 read-write - CH3_SWHS_REQ_SRC_WE + CH2_SWHS_REQ_SRC_WE NA 1 1 write-only - CH3_SWHS_SGLREQ_SRC + CH2_SWHS_SGLREQ_SRC NA 2 1 read-write - CH3_SWHS_SGLREQ_SRC_WE + CH2_SWHS_SGLREQ_SRC_WE NA 3 1 write-only - CH3_SWHS_LST_SRC + CH2_SWHS_LST_SRC NA 4 1 read-write - CH3_SWHS_LST_SRC_WE + CH2_SWHS_LST_SRC_WE NA 5 1 @@ -25222,48 +25443,48 @@ - CH3_SWHSDST0 + CH2_SWHSDST0 NA - 0x340 + 0x240 0x20 - CH3_SWHS_REQ_DST + CH2_SWHS_REQ_DST NA 0 1 read-write - CH3_SWHS_REQ_DST_WE + CH2_SWHS_REQ_DST_WE NA 1 1 write-only - CH3_SWHS_SGLREQ_DST + CH2_SWHS_SGLREQ_DST NA 2 1 read-write - CH3_SWHS_SGLREQ_DST_WE + CH2_SWHS_SGLREQ_DST_WE NA 3 1 write-only - CH3_SWHS_LST_DST + CH2_SWHS_LST_DST NA 4 1 read-write - CH3_SWHS_LST_DST_WE + CH2_SWHS_LST_DST_WE NA 5 1 @@ -25272,13 +25493,13 @@ - CH3_BLK_TFR_RESUMEREQ0 + CH2_BLK_TFR_RESUMEREQ0 NA - 0x348 + 0x248 0x20 - CH3_BLK_TFR_RESUMEREQ + CH2_BLK_TFR_RESUMEREQ NA 0 1 @@ -25287,20 +25508,20 @@ - CH3_AXI_ID0 + CH2_AXI_ID0 NA - 0x350 + 0x250 0x20 - CH3_AXI_READ_ID_SUFFIX + CH2_AXI_READ_ID_SUFFIX NA 0 1 read-write - CH3_AXI_WRITE_ID_SUFFIX + CH2_AXI_WRITE_ID_SUFFIX NA 16 1 @@ -25309,20 +25530,20 @@ - CH3_AXI_QOS0 + CH2_AXI_QOS0 NA - 0x358 + 0x258 0x20 - CH3_AXI_AWQOS + CH2_AXI_AWQOS NA 0 4 read-write - CH3_AXI_ARQOS + CH2_AXI_ARQOS NA 4 4 @@ -25331,13 +25552,13 @@ - CH3_SSTAT0 + CH2_SSTAT0 NA - 0x360 + 0x260 0x20 - CH3_SSTAT + CH2_SSTAT NA 0 32 @@ -25346,13 +25567,13 @@ - CH3_DSTAT0 + CH2_DSTAT0 NA - 0x368 + 0x268 0x20 - CH3_DSTAT + CH2_DSTAT NA 0 32 @@ -25361,13 +25582,13 @@ - CH3_SSTATAR0 + CH2_SSTATAR0 NA - 0x370 + 0x270 0x20 - CH3_SSTATAR0 + CH2_SSTATAR0 NA 0 32 @@ -25376,13 +25597,13 @@ - CH3_SSTATAR1 + CH2_SSTATAR1 NA - 0x374 + 0x274 0x20 - CH3_SSTATAR1 + CH2_SSTATAR1 NA 0 32 @@ -25391,13 +25612,13 @@ - CH3_DSTATAR0 + CH2_DSTATAR0 NA - 0x378 + 0x278 0x20 - CH3_DSTATAR0 + CH2_DSTATAR0 NA 0 32 @@ -25406,13 +25627,13 @@ - CH3_DSTATAR1 + CH2_DSTATAR1 NA - 0x37C + 0x27C 0x20 - CH3_DSTATAR1 + CH2_DSTATAR1 NA 0 32 @@ -25421,189 +25642,189 @@ - CH3_INTSTATUS_ENABLE0 + CH2_INTSTATUS_ENABLE0 NA - 0x380 + 0x280 0x20 0xFA3F7FFB - CH3_ENABLE_BLOCK_TFR_DONE_INTSTAT + CH2_ENABLE_BLOCK_TFR_DONE_INTSTAT NA 0 1 read-write - CH3_ENABLE_DMA_TFR_DONE_INTSTAT + CH2_ENABLE_DMA_TFR_DONE_INTSTAT NA 1 1 read-write - CH3_ENABLE_SRC_TRANSCOMP_INTSTAT + CH2_ENABLE_SRC_TRANSCOMP_INTSTAT NA 3 1 read-write - CH3_ENABLE_DST_TRANSCOMP_INTSTAT + CH2_ENABLE_DST_TRANSCOMP_INTSTAT NA 4 1 read-write - CH3_ENABLE_SRC_DEC_ERR_INTSTAT + CH2_ENABLE_SRC_DEC_ERR_INTSTAT NA 5 1 read-write - CH3_ENABLE_DST_DEC_ERR_INTSTAT + CH2_ENABLE_DST_DEC_ERR_INTSTAT NA 6 1 read-write - CH3_ENABLE_SRC_SLV_ERR_INTSTAT + CH2_ENABLE_SRC_SLV_ERR_INTSTAT NA 7 1 read-write - CH3_ENABLE_DST_SLV_ERR_INTSTAT + CH2_ENABLE_DST_SLV_ERR_INTSTAT NA 8 1 read-write - CH3_ENABLE_LLI_RD_DEC_ERR_INTSTAT + CH2_ENABLE_LLI_RD_DEC_ERR_INTSTAT NA 9 1 read-write - CH3_ENABLE_LLI_WR_DEC_ERR_INTSTAT + CH2_ENABLE_LLI_WR_DEC_ERR_INTSTAT NA 10 1 read-write - CH3_ENABLE_LLI_RD_SLV_ERR_INTSTAT + CH2_ENABLE_LLI_RD_SLV_ERR_INTSTAT NA 11 1 read-write - CH3_ENABLE_LLI_WR_SLV_ERR_INTSTAT + CH2_ENABLE_LLI_WR_SLV_ERR_INTSTAT NA 12 1 read-write - CH3_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT + CH2_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT NA 13 1 read-write - CH3_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT + CH2_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT NA 14 1 read-write - CH3_ENABLE_SLVIF_DEC_ERR_INTSTAT + CH2_ENABLE_SLVIF_DEC_ERR_INTSTAT NA 16 1 read-write - CH3_ENABLE_SLVIF_WR2RO_ERR_INTSTAT + CH2_ENABLE_SLVIF_WR2RO_ERR_INTSTAT NA 17 1 read-write - CH3_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT + CH2_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT NA 18 1 read-write - CH3_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT + CH2_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT NA 19 1 read-write - CH3_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT + CH2_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT NA 20 1 read-write - CH3_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT + CH2_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT NA 21 1 read-write - CH3_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT + CH2_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT NA 25 1 read-only - CH3_ENABLE_CH_LOCK_CLEARED_INTSTAT + CH2_ENABLE_CH_LOCK_CLEARED_INTSTAT NA 27 1 read-write - CH3_ENABLE_CH_SRC_SUSPENDED_INTSTAT + CH2_ENABLE_CH_SRC_SUSPENDED_INTSTAT NA 28 1 read-write - CH3_ENABLE_CH_SUSPENDED_INTSTAT + CH2_ENABLE_CH_SUSPENDED_INTSTAT NA 29 1 read-write - CH3_ENABLE_CH_DISABLED_INTSTAT + CH2_ENABLE_CH_DISABLED_INTSTAT NA 30 1 read-write - CH3_ENABLE_CH_ABORTED_INTSTAT + CH2_ENABLE_CH_ABORTED_INTSTAT NA 31 1 @@ -25612,35 +25833,35 @@ - CH3_INTSTATUS_ENABLE1 + CH2_INTSTATUS_ENABLE1 NA - 0x384 + 0x284 0x20 0x0000000F - CH3_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT + CH2_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT NA 0 1 read-only - CH3_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT + CH2_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT NA 1 1 read-only - CH3_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT + CH2_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT NA 2 1 read-only - CH3_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT + CH2_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT NA 3 1 @@ -25649,188 +25870,188 @@ - CH3_INTSTATUS0 + CH2_INTSTATUS0 NA - 0x388 + 0x288 0x20 - CH3_BLOCK_TFR_DONE_INTSTAT + CH2_BLOCK_TFR_DONE_INTSTAT NA 0 1 read-only - CH3_DMA_TFR_DONE_INTSTAT + CH2_DMA_TFR_DONE_INTSTAT NA 1 1 read-only - CH3_SRC_TRANSCOMP_INTSTAT + CH2_SRC_TRANSCOMP_INTSTAT NA 3 1 read-only - CH3_DST_TRANSCOMP_INTSTAT + CH2_DST_TRANSCOMP_INTSTAT NA 4 1 read-only - CH3_SRC_DEC_ERR_INTSTAT + CH2_SRC_DEC_ERR_INTSTAT NA 5 1 read-only - CH3_DST_DEC_ERR_INTSTAT + CH2_DST_DEC_ERR_INTSTAT NA 6 1 read-only - CH3_SRC_SLV_ERR_INTSTAT + CH2_SRC_SLV_ERR_INTSTAT NA 7 1 read-only - CH3_DST_SLV_ERR_INTSTAT + CH2_DST_SLV_ERR_INTSTAT NA 8 1 read-only - CH3_LLI_RD_DEC_ERR_INTSTAT + CH2_LLI_RD_DEC_ERR_INTSTAT NA 9 1 read-only - CH3_LLI_WR_DEC_ERR_INTSTAT + CH2_LLI_WR_DEC_ERR_INTSTAT NA 10 1 read-only - CH3_LLI_RD_SLV_ERR_INTSTAT + CH2_LLI_RD_SLV_ERR_INTSTAT NA 11 1 read-only - CH3_LLI_WR_SLV_ERR_INTSTAT + CH2_LLI_WR_SLV_ERR_INTSTAT NA 12 1 read-only - CH3_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT + CH2_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT NA 13 1 read-only - CH3_SLVIF_MULTIBLKTYPE_ERR_INTSTAT + CH2_SLVIF_MULTIBLKTYPE_ERR_INTSTAT NA 14 1 read-only - CH3_SLVIF_DEC_ERR_INTSTAT + CH2_SLVIF_DEC_ERR_INTSTAT NA 16 1 read-only - CH3_SLVIF_WR2RO_ERR_INTSTAT + CH2_SLVIF_WR2RO_ERR_INTSTAT NA 17 1 read-only - CH3_SLVIF_RD2RWO_ERR_INTSTAT + CH2_SLVIF_RD2RWO_ERR_INTSTAT NA 18 1 read-only - CH3_SLVIF_WRONCHEN_ERR_INTSTAT + CH2_SLVIF_WRONCHEN_ERR_INTSTAT NA 19 1 read-only - CH3_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT + CH2_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT NA 20 1 read-only - CH3_SLVIF_WRONHOLD_ERR_INTSTAT + CH2_SLVIF_WRONHOLD_ERR_INTSTAT NA 21 1 read-only - CH3_SLVIF_WRPARITY_ERR_INTSTAT + CH2_SLVIF_WRPARITY_ERR_INTSTAT NA 25 1 read-only - CH3_CH_LOCK_CLEARED_INTSTAT + CH2_CH_LOCK_CLEARED_INTSTAT NA 27 1 read-only - CH3_CH_SRC_SUSPENDED_INTSTAT + CH2_CH_SRC_SUSPENDED_INTSTAT NA 28 1 read-only - CH3_CH_SUSPENDED_INTSTAT + CH2_CH_SUSPENDED_INTSTAT NA 29 1 read-only - CH3_CH_DISABLED_INTSTAT + CH2_CH_DISABLED_INTSTAT NA 30 1 read-only - CH3_CH_ABORTED_INTSTAT + CH2_CH_ABORTED_INTSTAT NA 31 1 @@ -25839,34 +26060,34 @@ - CH3_INTSTATUS1 + CH2_INTSTATUS1 NA - 0x38C + 0x28C 0x20 - CH3_ECC_PROT_CHMEM_CORRERR_INTSTAT + CH2_ECC_PROT_CHMEM_CORRERR_INTSTAT NA 0 1 read-only - CH3_ECC_PROT_CHMEM_UNCORRERR_INTSTAT + CH2_ECC_PROT_CHMEM_UNCORRERR_INTSTAT NA 1 1 read-only - CH3_ECC_PROT_UIDMEM_CORRERR_INTSTAT + CH2_ECC_PROT_UIDMEM_CORRERR_INTSTAT NA 2 1 read-only - CH3_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT + CH2_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT NA 3 1 @@ -25875,189 +26096,189 @@ - CH3_INTSIGNAL_ENABLE0 + CH2_INTSIGNAL_ENABLE0 NA - 0x390 + 0x290 0x20 0xFA3F7FFB - CH3_ENABLE_BLOCK_TFR_DONE_INTSIGNAL + CH2_ENABLE_BLOCK_TFR_DONE_INTSIGNAL NA 0 1 read-write - CH3_ENABLE_DMA_TFR_DONE_INTSIGNAL + CH2_ENABLE_DMA_TFR_DONE_INTSIGNAL NA 1 1 read-write - CH3_ENABLE_SRC_TRANSCOMP_INTSIGNAL + CH2_ENABLE_SRC_TRANSCOMP_INTSIGNAL NA 3 1 read-write - CH3_ENABLE_DST_TRANSCOMP_INTSIGNAL + CH2_ENABLE_DST_TRANSCOMP_INTSIGNAL NA 4 1 read-write - CH3_ENABLE_SRC_DEC_ERR_INTSIGNAL + CH2_ENABLE_SRC_DEC_ERR_INTSIGNAL NA 5 1 read-write - CH3_ENABLE_DST_DEC_ERR_INTSIGNAL + CH2_ENABLE_DST_DEC_ERR_INTSIGNAL NA 6 1 read-write - CH3_ENABLE_SRC_SLV_ERR_INTSIGNAL + CH2_ENABLE_SRC_SLV_ERR_INTSIGNAL NA 7 1 read-write - CH3_ENABLE_DST_SLV_ERR_INTSIGNAL + CH2_ENABLE_DST_SLV_ERR_INTSIGNAL NA 8 1 read-write - CH3_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL + CH2_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL NA 9 1 read-write - CH3_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL + CH2_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL NA 10 1 read-write - CH3_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL + CH2_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL NA 11 1 read-write - CH3_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL + CH2_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL NA 12 1 read-write - CH3_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL + CH2_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL NA 13 1 read-write - CH3_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL + CH2_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL NA 14 1 read-write - CH3_ENABLE_SLVIF_DEC_ERR_INTSIGNAL + CH2_ENABLE_SLVIF_DEC_ERR_INTSIGNAL NA 16 1 read-write - CH3_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL + CH2_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL NA 17 1 read-write - CH3_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL + CH2_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL NA 18 1 read-write - CH3_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL + CH2_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL NA 19 1 read-write - CH3_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL + CH2_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL NA 20 1 read-write - CH3_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL + CH2_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL NA 21 1 read-write - CH3_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL + CH2_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL NA 25 1 read-only - CH3_ENABLE_CH_LOCK_CLEARED_INTSIGNAL + CH2_ENABLE_CH_LOCK_CLEARED_INTSIGNAL NA 27 1 read-write - CH3_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL + CH2_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL NA 28 1 read-write - CH3_ENABLE_CH_SUSPENDED_INTSIGNAL + CH2_ENABLE_CH_SUSPENDED_INTSIGNAL NA 29 1 read-write - CH3_ENABLE_CH_DISABLED_INTSIGNAL + CH2_ENABLE_CH_DISABLED_INTSIGNAL NA 30 1 read-write - CH3_ENABLE_CH_ABORTED_INTSIGNAL + CH2_ENABLE_CH_ABORTED_INTSIGNAL NA 31 1 @@ -26066,35 +26287,35 @@ - CH3_INTSIGNAL_ENABLE1 + CH2_INTSIGNAL_ENABLE1 NA - 0x394 + 0x294 0x20 0x0000000F - CH3_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL + CH2_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL NA 0 1 read-only - CH3_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL + CH2_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL NA 1 1 read-only - CH3_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL + CH2_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL NA 2 1 read-only - CH3_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL + CH2_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL NA 3 1 @@ -26103,188 +26324,188 @@ - CH3_INTCLEAR0 + CH2_INTCLEAR0 NA - 0x398 + 0x298 0x20 - CH3_CLEAR_BLOCK_TFR_DONE_INTSTAT + CH2_CLEAR_BLOCK_TFR_DONE_INTSTAT NA 0 1 write-only - CH3_CLEAR_DMA_TFR_DONE_INTSTAT + CH2_CLEAR_DMA_TFR_DONE_INTSTAT NA 1 1 write-only - CH3_CLEAR_SRC_TRANSCOMP_INTSTAT + CH2_CLEAR_SRC_TRANSCOMP_INTSTAT NA 3 1 write-only - CH3_CLEAR_DST_TRANSCOMP_INTSTAT + CH2_CLEAR_DST_TRANSCOMP_INTSTAT NA 4 1 write-only - CH3_CLEAR_SRC_DEC_ERR_INTSTAT + CH2_CLEAR_SRC_DEC_ERR_INTSTAT NA 5 1 write-only - CH3_CLEAR_DST_DEC_ERR_INTSTAT + CH2_CLEAR_DST_DEC_ERR_INTSTAT NA 6 1 write-only - CH3_CLEAR_SRC_SLV_ERR_INTSTAT + CH2_CLEAR_SRC_SLV_ERR_INTSTAT NA 7 1 write-only - CH3_CLEAR_DST_SLV_ERR_INTSTAT + CH2_CLEAR_DST_SLV_ERR_INTSTAT NA 8 1 write-only - CH3_CLEAR_LLI_RD_DEC_ERR_INTSTAT + CH2_CLEAR_LLI_RD_DEC_ERR_INTSTAT NA 9 1 write-only - CH3_CLEAR_LLI_WR_DEC_ERR_INTSTAT + CH2_CLEAR_LLI_WR_DEC_ERR_INTSTAT NA 10 1 write-only - CH3_CLEAR_LLI_RD_SLV_ERR_INTSTAT + CH2_CLEAR_LLI_RD_SLV_ERR_INTSTAT NA 11 1 write-only - CH3_CLEAR_LLI_WR_SLV_ERR_INTSTAT + CH2_CLEAR_LLI_WR_SLV_ERR_INTSTAT NA 12 1 write-only - CH3_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT + CH2_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT NA 13 1 write-only - CH3_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT + CH2_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT NA 14 1 write-only - CH3_CLEAR_SLVIF_DEC_ERR_INTSTAT + CH2_CLEAR_SLVIF_DEC_ERR_INTSTAT NA 16 1 write-only - CH3_CLEAR_SLVIF_WR2RO_ERR_INTSTAT + CH2_CLEAR_SLVIF_WR2RO_ERR_INTSTAT NA 17 1 write-only - CH3_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT + CH2_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT NA 18 1 write-only - CH3_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT + CH2_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT NA 19 1 write-only - CH3_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT + CH2_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT NA 20 1 write-only - CH3_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT + CH2_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT NA 21 1 write-only - CH3_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT + CH2_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT NA 25 1 write-only - CH3_CLEAR_CH_LOCK_CLEARED_INTSTAT + CH2_CLEAR_CH_LOCK_CLEARED_INTSTAT NA 27 1 write-only - CH3_CLEAR_CH_SRC_SUSPENDED_INTSTAT + CH2_CLEAR_CH_SRC_SUSPENDED_INTSTAT NA 28 1 write-only - CH3_CLEAR_CH_SUSPENDED_INTSTAT + CH2_CLEAR_CH_SUSPENDED_INTSTAT NA 29 1 write-only - CH3_CLEAR_CH_DISABLED_INTSTAT + CH2_CLEAR_CH_DISABLED_INTSTAT NA 30 1 write-only - CH3_CLEAR_CH_ABORTED_INTSTAT + CH2_CLEAR_CH_ABORTED_INTSTAT NA 31 1 @@ -26293,34 +26514,34 @@ - CH3_INTCLEAR1 + CH2_INTCLEAR1 NA - 0x39C + 0x29C 0x20 - CH3_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT + CH2_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT NA 0 1 write-only - CH3_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT + CH2_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT NA 1 1 write-only - CH3_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT + CH2_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT NA 2 1 write-only - CH3_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT + CH2_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT NA 3 1 @@ -26329,13 +26550,13 @@ - CH4_SAR0 + CH3_SAR0 NA - 0x400 + 0x300 0x20 - CH4_SAR0 + CH3_SAR0 NA 0 32 @@ -26344,13 +26565,13 @@ - CH4_SAR1 + CH3_SAR1 NA - 0x404 + 0x304 0x20 - CH4_SAR1 + CH3_SAR1 NA 0 32 @@ -26359,13 +26580,13 @@ - CH4_DAR0 + CH3_DAR0 NA - 0x408 + 0x308 0x20 - CH4_DAR0 + CH3_DAR0 NA 0 32 @@ -26374,13 +26595,13 @@ - CH4_DAR1 + CH3_DAR1 NA - 0x40C + 0x30C 0x20 - CH4_DAR1 + CH3_DAR1 NA 0 32 @@ -26389,13 +26610,13 @@ - CH4_BLOCK_TS0 + CH3_BLOCK_TS0 NA - 0x410 + 0x310 0x20 - CH4_BLOCK_TS + CH3_BLOCK_TS NA 0 22 @@ -26404,84 +26625,84 @@ - CH4_CTL0 + CH3_CTL0 NA - 0x418 + 0x318 0x20 0x00001200 - CH4_SMS + CH3_SMS NA 0 1 read-write - CH4_DMS + CH3_DMS NA 2 1 read-write - CH4_SINC + CH3_SINC NA 4 1 read-write - CH4_DINC + CH3_DINC NA 6 1 read-write - CH4_SRC_TR_WIDTH + CH3_SRC_TR_WIDTH NA 8 3 read-write - CH4_DST_TR_WIDTH + CH3_DST_TR_WIDTH NA 11 3 read-write - CH4_SRC_MSIZE + CH3_SRC_MSIZE NA 14 4 read-write - CH4_DST_MSIZE + CH3_DST_MSIZE NA 18 4 read-write - CH4_AR_CACHE + CH3_AR_CACHE NA 22 4 read-write - CH4_AW_CACHE + CH3_AW_CACHE NA 26 4 read-write - CH4_NONPOSTED_LASTWRITE_EN + CH3_NONPOSTED_LASTWRITE_EN NA 30 1 @@ -26490,83 +26711,83 @@ - CH4_CTL1 + CH3_CTL1 NA - 0x41C + 0x31C 0x20 - CH4_AR_PROT + CH3_AR_PROT NA 0 3 read-write - CH4_AW_PROT + CH3_AW_PROT NA 3 3 read-write - CH4_ARLEN_EN + CH3_ARLEN_EN NA 6 1 read-write - CH4_ARLEN + CH3_ARLEN NA 7 8 read-write - CH4_AWLEN_EN + CH3_AWLEN_EN NA 15 1 read-write - CH4_AWLEN + CH3_AWLEN NA 16 8 read-write - CH4_SRC_STAT_EN + CH3_SRC_STAT_EN NA 24 1 read-write - CH4_DST_STAT_EN + CH3_DST_STAT_EN NA 25 1 read-write - CH4_IOC_BLKTFR + CH3_IOC_BLKTFR NA 26 1 read-write - CH4_SHADOWREG_OR_LLI_LAST + CH3_SHADOWREG_OR_LLI_LAST NA 30 1 read-write - CH4_SHADOWREG_OR_LLI_VALID + CH3_SHADOWREG_OR_LLI_VALID NA 31 1 @@ -26575,34 +26796,34 @@ - CH4_CFG0 + CH3_CFG0 NA - 0x420 + 0x320 0x20 - CH4_SRC_MULTBLK_TYPE + CH3_SRC_MULTBLK_TYPE NA 0 2 read-write - CH4_DST_MULTBLK_TYPE + CH3_DST_MULTBLK_TYPE NA 2 2 read-write - CH4_RD_UID + CH3_RD_UID NA 18 4 read-only - CH4_WR_UID + CH3_WR_UID NA 25 4 @@ -26611,91 +26832,91 @@ - CH4_CFG1 + CH3_CFG1 NA - 0x424 + 0x324 0x20 - 0x0000001B + 0x0002001B - CH4_TT_FC + CH3_TT_FC NA 0 3 read-write - CH4_HS_SEL_SRC + CH3_HS_SEL_SRC NA 3 1 read-write - CH4_HS_SEL_DST + CH3_HS_SEL_DST NA 4 1 read-write - CH4_SRC_HWHS_POL + CH3_SRC_HWHS_POL NA 5 1 read-only - CH4_DST_HWHS_POL + CH3_DST_HWHS_POL NA 6 1 read-only - CH4_SRC_PER + CH3_SRC_PER NA 7 2 read-write - CH4_DST_PER + CH3_DST_PER NA 12 2 read-write - CH4_CH_PRIOR + CH3_CH_PRIOR NA 17 3 read-write - CH4_LOCK_CH + CH3_LOCK_CH NA 20 1 read-only - CH4_LOCK_CH_L + CH3_LOCK_CH_L NA 21 2 read-only - CH4_SRC_OSR_LMT + CH3_SRC_OSR_LMT NA 23 4 read-write - CH4_DST_OSR_LMT + CH3_DST_OSR_LMT NA 27 4 @@ -26704,20 +26925,20 @@ - CH4_LLP0 + CH3_LLP0 NA - 0x428 + 0x328 0x20 - CH4_LMS + CH3_LMS NA 0 1 read-write - CH4_LOC0 + CH3_LOC0 NA 6 26 @@ -26726,13 +26947,13 @@ - CH4_LLP1 + CH3_LLP1 NA - 0x42C + 0x32C 0x20 - CH4_LOC1 + CH3_LOC1 NA 0 32 @@ -26741,13 +26962,13 @@ - CH4_STATUS0 + CH3_STATUS0 NA - 0x430 + 0x330 0x20 - CH4_CMPLTD_BLK_TFR_SIZE + CH3_CMPLTD_BLK_TFR_SIZE NA 0 22 @@ -26756,13 +26977,13 @@ - CH4_STATUS1 + CH3_STATUS1 NA - 0x434 + 0x334 0x20 - CH4_DATA_LEFT_IN_FIFO + CH3_DATA_LEFT_IN_FIFO NA 0 15 @@ -26771,48 +26992,48 @@ - CH4_SWHSSRC0 + CH3_SWHSSRC0 NA - 0x438 + 0x338 0x20 - CH4_SWHS_REQ_SRC + CH3_SWHS_REQ_SRC NA 0 1 read-write - CH4_SWHS_REQ_SRC_WE + CH3_SWHS_REQ_SRC_WE NA 1 1 write-only - CH4_SWHS_SGLREQ_SRC + CH3_SWHS_SGLREQ_SRC NA 2 1 read-write - CH4_SWHS_SGLREQ_SRC_WE + CH3_SWHS_SGLREQ_SRC_WE NA 3 1 write-only - CH4_SWHS_LST_SRC + CH3_SWHS_LST_SRC NA 4 1 read-write - CH4_SWHS_LST_SRC_WE + CH3_SWHS_LST_SRC_WE NA 5 1 @@ -26821,48 +27042,48 @@ - CH4_SWHSDST0 + CH3_SWHSDST0 NA - 0x440 + 0x340 0x20 - CH4_SWHS_REQ_DST + CH3_SWHS_REQ_DST NA 0 1 read-write - CH4_SWHS_REQ_DST_WE + CH3_SWHS_REQ_DST_WE NA 1 1 write-only - CH4_SWHS_SGLREQ_DST + CH3_SWHS_SGLREQ_DST NA 2 1 read-write - CH4_SWHS_SGLREQ_DST_WE + CH3_SWHS_SGLREQ_DST_WE NA 3 1 write-only - CH4_SWHS_LST_DST + CH3_SWHS_LST_DST NA 4 1 read-write - CH4_SWHS_LST_DST_WE + CH3_SWHS_LST_DST_WE NA 5 1 @@ -26871,13 +27092,13 @@ - CH4_BLK_TFR_RESUMEREQ0 + CH3_BLK_TFR_RESUMEREQ0 NA - 0x448 + 0x348 0x20 - CH4_BLK_TFR_RESUMEREQ + CH3_BLK_TFR_RESUMEREQ NA 0 1 @@ -26886,20 +27107,20 @@ - CH4_AXI_ID0 + CH3_AXI_ID0 NA - 0x450 + 0x350 0x20 - CH4_AXI_READ_ID_SUFFIX + CH3_AXI_READ_ID_SUFFIX NA 0 1 read-write - CH4_AXI_WRITE_ID_SUFFIX + CH3_AXI_WRITE_ID_SUFFIX NA 16 1 @@ -26908,20 +27129,20 @@ - CH4_AXI_QOS0 + CH3_AXI_QOS0 NA - 0x458 + 0x358 0x20 - CH4_AXI_AWQOS + CH3_AXI_AWQOS NA 0 4 read-write - CH4_AXI_ARQOS + CH3_AXI_ARQOS NA 4 4 @@ -26930,13 +27151,13 @@ - CH4_SSTAT0 + CH3_SSTAT0 NA - 0x460 + 0x360 0x20 - CH4_SSTAT + CH3_SSTAT NA 0 32 @@ -26945,13 +27166,13 @@ - CH4_DSTAT0 + CH3_DSTAT0 NA - 0x468 + 0x368 0x20 - CH4_DSTAT + CH3_DSTAT NA 0 32 @@ -26960,13 +27181,13 @@ - CH4_SSTATAR0 + CH3_SSTATAR0 NA - 0x470 + 0x370 0x20 - CH4_SSTATAR0 + CH3_SSTATAR0 NA 0 32 @@ -26975,13 +27196,13 @@ - CH4_SSTATAR1 + CH3_SSTATAR1 NA - 0x474 + 0x374 0x20 - CH4_SSTATAR1 + CH3_SSTATAR1 NA 0 32 @@ -26990,13 +27211,13 @@ - CH4_DSTATAR0 + CH3_DSTATAR0 NA - 0x478 + 0x378 0x20 - CH4_DSTATAR0 + CH3_DSTATAR0 NA 0 32 @@ -27005,13 +27226,13 @@ - CH4_DSTATAR1 + CH3_DSTATAR1 NA - 0x47C + 0x37C 0x20 - CH4_DSTATAR1 + CH3_DSTATAR1 NA 0 32 @@ -27020,189 +27241,189 @@ - CH4_INTSTATUS_ENABLE0 + CH3_INTSTATUS_ENABLE0 NA - 0x480 + 0x380 0x20 0xFA3F7FFB - CH4_ENABLE_BLOCK_TFR_DONE_INTSTAT + CH3_ENABLE_BLOCK_TFR_DONE_INTSTAT NA 0 1 read-write - CH4_ENABLE_DMA_TFR_DONE_INTSTAT + CH3_ENABLE_DMA_TFR_DONE_INTSTAT NA 1 1 read-write - CH4_ENABLE_SRC_TRANSCOMP_INTSTAT + CH3_ENABLE_SRC_TRANSCOMP_INTSTAT NA 3 1 read-write - CH4_ENABLE_DST_TRANSCOMP_INTSTAT + CH3_ENABLE_DST_TRANSCOMP_INTSTAT NA 4 1 read-write - CH4_ENABLE_SRC_DEC_ERR_INTSTAT + CH3_ENABLE_SRC_DEC_ERR_INTSTAT NA 5 1 read-write - CH4_ENABLE_DST_DEC_ERR_INTSTAT + CH3_ENABLE_DST_DEC_ERR_INTSTAT NA 6 1 read-write - CH4_ENABLE_SRC_SLV_ERR_INTSTAT + CH3_ENABLE_SRC_SLV_ERR_INTSTAT NA 7 1 read-write - CH4_ENABLE_DST_SLV_ERR_INTSTAT + CH3_ENABLE_DST_SLV_ERR_INTSTAT NA 8 1 read-write - CH4_ENABLE_LLI_RD_DEC_ERR_INTSTAT + CH3_ENABLE_LLI_RD_DEC_ERR_INTSTAT NA 9 1 read-write - CH4_ENABLE_LLI_WR_DEC_ERR_INTSTAT + CH3_ENABLE_LLI_WR_DEC_ERR_INTSTAT NA 10 1 read-write - CH4_ENABLE_LLI_RD_SLV_ERR_INTSTAT + CH3_ENABLE_LLI_RD_SLV_ERR_INTSTAT NA 11 1 read-write - CH4_ENABLE_LLI_WR_SLV_ERR_INTSTAT + CH3_ENABLE_LLI_WR_SLV_ERR_INTSTAT NA 12 1 read-write - CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT + CH3_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT NA 13 1 read-write - CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT + CH3_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT NA 14 1 read-write - CH4_ENABLE_SLVIF_DEC_ERR_INTSTAT + CH3_ENABLE_SLVIF_DEC_ERR_INTSTAT NA 16 1 read-write - CH4_ENABLE_SLVIF_WR2RO_ERR_INTSTAT + CH3_ENABLE_SLVIF_WR2RO_ERR_INTSTAT NA 17 1 read-write - CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT + CH3_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT NA 18 1 read-write - CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT + CH3_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT NA 19 1 read-write - CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT + CH3_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT NA 20 1 read-write - CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT + CH3_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT NA 21 1 read-write - CH4_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT + CH3_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT NA 25 1 read-only - CH4_ENABLE_CH_LOCK_CLEARED_INTSTAT + CH3_ENABLE_CH_LOCK_CLEARED_INTSTAT NA 27 1 read-write - CH4_ENABLE_CH_SRC_SUSPENDED_INTSTAT + CH3_ENABLE_CH_SRC_SUSPENDED_INTSTAT NA 28 1 read-write - CH4_ENABLE_CH_SUSPENDED_INTSTAT + CH3_ENABLE_CH_SUSPENDED_INTSTAT NA 29 1 read-write - CH4_ENABLE_CH_DISABLED_INTSTAT + CH3_ENABLE_CH_DISABLED_INTSTAT NA 30 1 read-write - CH4_ENABLE_CH_ABORTED_INTSTAT + CH3_ENABLE_CH_ABORTED_INTSTAT NA 31 1 @@ -27211,35 +27432,35 @@ - CH4_INTSTATUS_ENABLE1 + CH3_INTSTATUS_ENABLE1 NA - 0x484 + 0x384 0x20 0x0000000F - CH4_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT + CH3_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT NA 0 1 read-only - CH4_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT + CH3_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT NA 1 1 read-only - CH4_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT + CH3_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT NA 2 1 read-only - CH4_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT + CH3_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT NA 3 1 @@ -27248,188 +27469,188 @@ - CH4_INTSTATUS0 + CH3_INTSTATUS0 NA - 0x488 + 0x388 0x20 - CH4_BLOCK_TFR_DONE_INTSTAT + CH3_BLOCK_TFR_DONE_INTSTAT NA 0 1 read-only - CH4_DMA_TFR_DONE_INTSTAT + CH3_DMA_TFR_DONE_INTSTAT NA 1 1 read-only - CH4_SRC_TRANSCOMP_INTSTAT + CH3_SRC_TRANSCOMP_INTSTAT NA 3 1 read-only - CH4_DST_TRANSCOMP_INTSTAT + CH3_DST_TRANSCOMP_INTSTAT NA 4 1 read-only - CH4_SRC_DEC_ERR_INTSTAT + CH3_SRC_DEC_ERR_INTSTAT NA 5 1 read-only - CH4_DST_DEC_ERR_INTSTAT + CH3_DST_DEC_ERR_INTSTAT NA 6 1 read-only - CH4_SRC_SLV_ERR_INTSTAT + CH3_SRC_SLV_ERR_INTSTAT NA 7 1 read-only - CH4_DST_SLV_ERR_INTSTAT + CH3_DST_SLV_ERR_INTSTAT NA 8 1 read-only - CH4_LLI_RD_DEC_ERR_INTSTAT + CH3_LLI_RD_DEC_ERR_INTSTAT NA 9 1 read-only - CH4_LLI_WR_DEC_ERR_INTSTAT + CH3_LLI_WR_DEC_ERR_INTSTAT NA 10 1 read-only - CH4_LLI_RD_SLV_ERR_INTSTAT + CH3_LLI_RD_SLV_ERR_INTSTAT NA 11 1 read-only - CH4_LLI_WR_SLV_ERR_INTSTAT + CH3_LLI_WR_SLV_ERR_INTSTAT NA 12 1 read-only - CH4_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT + CH3_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT NA 13 1 read-only - CH4_SLVIF_MULTIBLKTYPE_ERR_INTSTAT + CH3_SLVIF_MULTIBLKTYPE_ERR_INTSTAT NA 14 1 read-only - CH4_SLVIF_DEC_ERR_INTSTAT + CH3_SLVIF_DEC_ERR_INTSTAT NA 16 1 read-only - CH4_SLVIF_WR2RO_ERR_INTSTAT + CH3_SLVIF_WR2RO_ERR_INTSTAT NA 17 1 read-only - CH4_SLVIF_RD2RWO_ERR_INTSTAT + CH3_SLVIF_RD2RWO_ERR_INTSTAT NA 18 1 read-only - CH4_SLVIF_WRONCHEN_ERR_INTSTAT + CH3_SLVIF_WRONCHEN_ERR_INTSTAT NA 19 1 read-only - CH4_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT + CH3_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT NA 20 1 read-only - CH4_SLVIF_WRONHOLD_ERR_INTSTAT + CH3_SLVIF_WRONHOLD_ERR_INTSTAT NA 21 1 read-only - CH4_SLVIF_WRPARITY_ERR_INTSTAT + CH3_SLVIF_WRPARITY_ERR_INTSTAT NA 25 1 read-only - CH4_CH_LOCK_CLEARED_INTSTAT + CH3_CH_LOCK_CLEARED_INTSTAT NA 27 1 read-only - CH4_CH_SRC_SUSPENDED_INTSTAT + CH3_CH_SRC_SUSPENDED_INTSTAT NA 28 1 read-only - CH4_CH_SUSPENDED_INTSTAT + CH3_CH_SUSPENDED_INTSTAT NA 29 1 read-only - CH4_CH_DISABLED_INTSTAT + CH3_CH_DISABLED_INTSTAT NA 30 1 read-only - CH4_CH_ABORTED_INTSTAT + CH3_CH_ABORTED_INTSTAT NA 31 1 @@ -27438,34 +27659,34 @@ - CH4_INTSTATUS1 + CH3_INTSTATUS1 NA - 0x48C + 0x38C 0x20 - CH4_ECC_PROT_CHMEM_CORRERR_INTSTAT + CH3_ECC_PROT_CHMEM_CORRERR_INTSTAT NA 0 1 read-only - CH4_ECC_PROT_CHMEM_UNCORRERR_INTSTAT + CH3_ECC_PROT_CHMEM_UNCORRERR_INTSTAT NA 1 1 read-only - CH4_ECC_PROT_UIDMEM_CORRERR_INTSTAT + CH3_ECC_PROT_UIDMEM_CORRERR_INTSTAT NA 2 1 read-only - CH4_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT + CH3_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT NA 3 1 @@ -27474,189 +27695,189 @@ - CH4_INTSIGNAL_ENABLE0 + CH3_INTSIGNAL_ENABLE0 NA - 0x490 + 0x390 0x20 0xFA3F7FFB - CH4_ENABLE_BLOCK_TFR_DONE_INTSIGNAL + CH3_ENABLE_BLOCK_TFR_DONE_INTSIGNAL NA 0 1 read-write - CH4_ENABLE_DMA_TFR_DONE_INTSIGNAL + CH3_ENABLE_DMA_TFR_DONE_INTSIGNAL NA 1 1 read-write - CH4_ENABLE_SRC_TRANSCOMP_INTSIGNAL + CH3_ENABLE_SRC_TRANSCOMP_INTSIGNAL NA 3 1 read-write - CH4_ENABLE_DST_TRANSCOMP_INTSIGNAL + CH3_ENABLE_DST_TRANSCOMP_INTSIGNAL NA 4 1 read-write - CH4_ENABLE_SRC_DEC_ERR_INTSIGNAL + CH3_ENABLE_SRC_DEC_ERR_INTSIGNAL NA 5 1 read-write - CH4_ENABLE_DST_DEC_ERR_INTSIGNAL + CH3_ENABLE_DST_DEC_ERR_INTSIGNAL NA 6 1 read-write - CH4_ENABLE_SRC_SLV_ERR_INTSIGNAL + CH3_ENABLE_SRC_SLV_ERR_INTSIGNAL NA 7 1 read-write - CH4_ENABLE_DST_SLV_ERR_INTSIGNAL + CH3_ENABLE_DST_SLV_ERR_INTSIGNAL NA 8 1 read-write - CH4_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL + CH3_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL NA 9 1 read-write - CH4_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL + CH3_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL NA 10 1 read-write - CH4_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL + CH3_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL NA 11 1 read-write - CH4_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL + CH3_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL NA 12 1 read-write - CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL + CH3_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL NA 13 1 read-write - CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL + CH3_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL NA 14 1 read-write - CH4_ENABLE_SLVIF_DEC_ERR_INTSIGNAL + CH3_ENABLE_SLVIF_DEC_ERR_INTSIGNAL NA 16 1 read-write - CH4_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL + CH3_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL NA 17 1 read-write - CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL + CH3_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL NA 18 1 read-write - CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL + CH3_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL NA 19 1 read-write - CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL + CH3_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL NA 20 1 read-write - CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL + CH3_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL NA 21 1 read-write - CH4_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL + CH3_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL NA 25 1 read-only - CH4_ENABLE_CH_LOCK_CLEARED_INTSIGNAL + CH3_ENABLE_CH_LOCK_CLEARED_INTSIGNAL NA 27 1 read-write - CH4_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL + CH3_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL NA 28 1 read-write - CH4_ENABLE_CH_SUSPENDED_INTSIGNAL + CH3_ENABLE_CH_SUSPENDED_INTSIGNAL NA 29 1 read-write - CH4_ENABLE_CH_DISABLED_INTSIGNAL + CH3_ENABLE_CH_DISABLED_INTSIGNAL NA 30 1 read-write - CH4_ENABLE_CH_ABORTED_INTSIGNAL + CH3_ENABLE_CH_ABORTED_INTSIGNAL NA 31 1 @@ -27665,35 +27886,35 @@ - CH4_INTSIGNAL_ENABLE1 + CH3_INTSIGNAL_ENABLE1 NA - 0x494 + 0x394 0x20 0x0000000F - CH4_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL + CH3_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL NA 0 1 read-only - CH4_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL + CH3_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL NA 1 1 read-only - CH4_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL + CH3_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL NA 2 1 read-only - CH4_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL + CH3_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL NA 3 1 @@ -27702,188 +27923,188 @@ - CH4_INTCLEAR0 + CH3_INTCLEAR0 NA - 0x498 + 0x398 0x20 - CH4_CLEAR_BLOCK_TFR_DONE_INTSTAT + CH3_CLEAR_BLOCK_TFR_DONE_INTSTAT NA 0 1 write-only - CH4_CLEAR_DMA_TFR_DONE_INTSTAT + CH3_CLEAR_DMA_TFR_DONE_INTSTAT NA 1 1 write-only - CH4_CLEAR_SRC_TRANSCOMP_INTSTAT + CH3_CLEAR_SRC_TRANSCOMP_INTSTAT NA 3 1 write-only - CH4_CLEAR_DST_TRANSCOMP_INTSTAT + CH3_CLEAR_DST_TRANSCOMP_INTSTAT NA 4 1 write-only - CH4_CLEAR_SRC_DEC_ERR_INTSTAT + CH3_CLEAR_SRC_DEC_ERR_INTSTAT NA 5 1 write-only - CH4_CLEAR_DST_DEC_ERR_INTSTAT + CH3_CLEAR_DST_DEC_ERR_INTSTAT NA 6 1 write-only - CH4_CLEAR_SRC_SLV_ERR_INTSTAT + CH3_CLEAR_SRC_SLV_ERR_INTSTAT NA 7 1 write-only - CH4_CLEAR_DST_SLV_ERR_INTSTAT + CH3_CLEAR_DST_SLV_ERR_INTSTAT NA 8 1 write-only - CH4_CLEAR_LLI_RD_DEC_ERR_INTSTAT + CH3_CLEAR_LLI_RD_DEC_ERR_INTSTAT NA 9 1 write-only - CH4_CLEAR_LLI_WR_DEC_ERR_INTSTAT + CH3_CLEAR_LLI_WR_DEC_ERR_INTSTAT NA 10 1 write-only - CH4_CLEAR_LLI_RD_SLV_ERR_INTSTAT + CH3_CLEAR_LLI_RD_SLV_ERR_INTSTAT NA 11 1 write-only - CH4_CLEAR_LLI_WR_SLV_ERR_INTSTAT + CH3_CLEAR_LLI_WR_SLV_ERR_INTSTAT NA 12 1 write-only - CH4_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT + CH3_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT NA 13 1 write-only - CH4_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT + CH3_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT NA 14 1 write-only - CH4_CLEAR_SLVIF_DEC_ERR_INTSTAT + CH3_CLEAR_SLVIF_DEC_ERR_INTSTAT NA 16 1 write-only - CH4_CLEAR_SLVIF_WR2RO_ERR_INTSTAT + CH3_CLEAR_SLVIF_WR2RO_ERR_INTSTAT NA 17 1 write-only - CH4_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT + CH3_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT NA 18 1 write-only - CH4_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT + CH3_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT NA 19 1 write-only - CH4_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT + CH3_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT NA 20 1 write-only - CH4_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT + CH3_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT NA 21 1 write-only - CH4_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT + CH3_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT NA 25 1 write-only - CH4_CLEAR_CH_LOCK_CLEARED_INTSTAT + CH3_CLEAR_CH_LOCK_CLEARED_INTSTAT NA 27 1 write-only - CH4_CLEAR_CH_SRC_SUSPENDED_INTSTAT + CH3_CLEAR_CH_SRC_SUSPENDED_INTSTAT NA 28 1 write-only - CH4_CLEAR_CH_SUSPENDED_INTSTAT + CH3_CLEAR_CH_SUSPENDED_INTSTAT NA 29 1 write-only - CH4_CLEAR_CH_DISABLED_INTSTAT + CH3_CLEAR_CH_DISABLED_INTSTAT NA 30 1 write-only - CH4_CLEAR_CH_ABORTED_INTSTAT + CH3_CLEAR_CH_ABORTED_INTSTAT NA 31 1 @@ -27892,34 +28113,34 @@ - CH4_INTCLEAR1 + CH3_INTCLEAR1 NA - 0x49C + 0x39C 0x20 - CH4_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT + CH3_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT NA 0 1 write-only - CH4_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT + CH3_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT NA 1 1 write-only - CH4_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT + CH3_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT NA 2 1 write-only - CH4_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT + CH3_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT NA 3 1 @@ -27927,2976 +28148,3077 @@ - - - - DS - Digital Signature - DS - 0x50094000 - - 0x0 - 0xA5C - registers - - - - 512 - 0x1 - Y_MEM[%s] - memory that stores Y - 0x0 - 0x8 - - - 512 - 0x1 - M_MEM[%s] - memory that stores M - 0x200 - 0x8 - - 512 - 0x1 - RB_MEM[%s] - memory that stores Rb + CH4_SAR0 + NA 0x400 - 0x8 - - - 48 - 0x1 - BOX_MEM[%s] - memory that stores BOX - 0x600 - 0x8 - - - 16 - 0x1 - IV_MEM[%s] - memory that stores IV - 0x630 - 0x8 - - - 512 - 0x1 - X_MEM[%s] - memory that stores X - 0x800 - 0x8 - - - 512 - 0x1 - Z_MEM[%s] - memory that stores Z - 0xA00 - 0x8 - - - SET_START - DS start control register - 0xE00 0x20 - SET_START - set this bit to start DS operation. + CH4_SAR0 + NA 0 - 1 - write-only + 32 + read-write - SET_CONTINUE - DS continue control register - 0xE04 + CH4_SAR1 + NA + 0x404 0x20 - SET_CONTINUE - set this bit to continue DS operation. + CH4_SAR1 + NA 0 - 1 - write-only + 32 + read-write - SET_FINISH - DS finish control register - 0xE08 + CH4_DAR0 + NA + 0x408 0x20 - SET_FINISH - Set this bit to finish DS process. + CH4_DAR0 + NA 0 - 1 - write-only + 32 + read-write - QUERY_BUSY - DS query busy register - 0xE0C + CH4_DAR1 + NA + 0x40C 0x20 - QUERY_BUSY - digital signature state. 1'b0: idle, 1'b1: busy + CH4_DAR1 + NA 0 - 1 - read-only + 32 + read-write - QUERY_KEY_WRONG - DS query key-wrong counter register - 0xE10 + CH4_BLOCK_TS0 + NA + 0x410 0x20 - QUERY_KEY_WRONG - digital signature key wrong counter + CH4_BLOCK_TS + NA 0 - 4 - read-only + 22 + read-write - QUERY_CHECK - DS query check result register - 0xE14 + CH4_CTL0 + NA + 0x418 0x20 + 0x00001200 - MD_ERROR - MD checkout result. 1'b0: MD check pass, 1'b1: MD check fail + CH4_SMS + NA 0 1 - read-only + read-write - PADDING_BAD - padding checkout result. 1'b0: a good padding, 1'b1: a bad padding - 1 + CH4_DMS + NA + 2 1 - read-only - - - - - DATE - DS version control register - 0xE20 - 0x20 - 0x20200618 - - - DATE - ds version information - 0 - 30 read-write - - - - - - MIPI_DSI_BRIDGE - MIPI Camera Interface Bridge - DSI_BRG - 0x500A0800 - - 0x0 - 0x94 - registers - - - DSI_BRIDGE - 86 - - - - CLK_EN - dsi bridge clk control register - 0x0 - 0x20 - - CLK_EN - this bit configures force_on of dsi_bridge register clock gate - 0 + CH4_SINC + NA + 4 1 read-write - - - - EN - dsi bridge en register - 0x4 - 0x20 - - DSI_EN - this bit configures module enable of dsi_bridge. 0: disable, 1: enable - 0 + CH4_DINC + NA + 6 1 read-write - - - - DMA_REQ_CFG - dsi bridge dma burst len register - 0x8 - 0x20 - 0x00000080 - - DMA_BURST_LEN - this field configures the num of 64-bit in one dma burst transfer, valid only when dsi_bridge as flow controller - 0 - 12 + CH4_SRC_TR_WIDTH + NA + 8 + 3 read-write - - - - RAW_NUM_CFG - dsi bridge raw number control register - 0xC - 0x20 - 0x00038400 - - RAW_NUM_TOTAL - this field configures number of total pix bits/64 - 0 - 22 + CH4_DST_TR_WIDTH + NA + 11 + 3 read-write - UNALIGN_64BIT_EN - this field configures whether the total pix bits is a multiple of 64bits. 0: align to 64-bit, 1: unalign to 64-bit - 22 - 1 + CH4_SRC_MSIZE + NA + 14 + 4 read-write - RAW_NUM_TOTAL_SET - this bit configures enable of reload reg_raw_num_total to internal cnt. 0: disable, 1: enable. valid only when dsi_bridge as flow controller - 31 - 1 - write-only + CH4_DST_MSIZE + NA + 18 + 4 + read-write - - - - RAW_BUF_CREDIT_CTL - dsi bridge credit register - 0x10 - 0x20 - 0x03200400 - - CREDIT_THRD - this field configures the threshold whether dsi_bridge fifo can receive one more 64-bit, valid only when dsi_bridge as flow controller - 0 - 15 + CH4_AR_CACHE + NA + 22 + 4 read-write - CREDIT_BURST_THRD - this field configures the threshold whether dsi_bridge fifo can receive one more dma burst, valid only when dsi_bridge as flow controller - 16 - 15 + CH4_AW_CACHE + NA + 26 + 4 read-write - CREDIT_RESET - this bit configures internal credit cnt clear, 0: non, 1: reset. valid only when dsi_bridge as flow controller - 31 + CH4_NONPOSTED_LASTWRITE_EN + NA + 30 1 read-write - FIFO_FLOW_STATUS - dsi bridge raw buffer depth register - 0x14 - 0x20 - - - RAW_BUF_DEPTH - this field configures the depth of dsi_bridge fifo depth - 0 - 14 - read-only - - - - - PIXEL_TYPE - dsi bridge dpi type control register - 0x18 + CH4_CTL1 + NA + 0x41C 0x20 - RAW_TYPE - this field configures the pixel type. 0: rgb888, 1:rgb666, 2:rgb565 + CH4_AR_PROT + NA 0 - 4 + 3 read-write - DPI_CONFIG - this field configures the pixel arrange type of dpi interface - 4 - 2 + CH4_AW_PROT + NA + 3 + 3 read-write - DATA_IN_TYPE - input data type, 0: rgb, 1: yuv + CH4_ARLEN_EN + NA 6 1 read-write - - - - DMA_BLOCK_INTERVAL - dsi bridge dma block interval control register - 0x1C - 0x20 - 0x30002409 - - DMA_BLOCK_SLOT - this field configures the max block_slot_cnt - 0 - 10 + CH4_ARLEN + NA + 7 + 8 read-write - DMA_BLOCK_INTERVAL - this field configures the max block_interval_cnt, block_interval_cnt increased by 1 when block_slot_cnt if full - 10 - 18 + CH4_AWLEN_EN + NA + 15 + 1 read-write - RAW_NUM_TOTAL_AUTO_RELOAD - this bit configures enable of auto reload reg_raw_num_total, 0: disable, 1: enable - 28 - 1 + CH4_AWLEN + NA + 16 + 8 read-write - EN - this bit configures enable of interval between dma block transfer, 0: disable, 1: enable - 29 + CH4_SRC_STAT_EN + NA + 24 1 read-write - - - - DMA_REQ_INTERVAL - dsi bridge dma req interval control register - 0x20 - 0x20 - 0x00000001 - - DMA_REQ_INTERVAL - this field configures the interval between dma req events - 0 - 16 + CH4_DST_STAT_EN + NA + 25 + 1 read-write - - - - DPI_LCD_CTL - dsi bridge dpi signal control register - 0x24 - 0x20 - - DPISHUTDN - this bit configures dpishutdn signal in dpi interface - 0 + CH4_IOC_BLKTFR + NA + 26 1 read-write - DPICOLORM - this bit configures dpicolorm signal in dpi interface - 1 + CH4_SHADOWREG_OR_LLI_LAST + NA + 30 1 read-write - DPIUPDATECFG - this bit configures dpiupdatecfg signal in dpi interface - 2 + CH4_SHADOWREG_OR_LLI_VALID + NA + 31 1 read-write - DPI_RSV_DPI_DATA - dsi bridge dpi reserved data register - 0x28 + CH4_CFG0 + NA + 0x420 0x20 - 0x00003FFF - DPI_RSV_DATA - this field controls the pixel data sent to dsi_host when dsi_bridge fifo underflow + CH4_SRC_MULTBLK_TYPE + NA 0 - 30 + 2 read-write - - - - DPI_V_CFG0 - dsi bridge dpi v config register 0 - 0x30 - 0x20 - 0x01E0020D - - VTOTAL - this field configures the total length of one frame (by line) for dpi output, must meet: reg_vtotal > reg_vdisp+reg_vsync+reg_vbank - 0 - 12 + CH4_DST_MULTBLK_TYPE + NA + 2 + 2 read-write - VDISP - this field configures the length of valid line (by line) for dpi output - 16 - 12 - read-write + CH4_RD_UID + NA + 18 + 4 + read-only + + + CH4_WR_UID + NA + 25 + 4 + read-only - DPI_V_CFG1 - dsi bridge dpi v config register 1 - 0x34 + CH4_CFG1 + NA + 0x424 0x20 - 0x00020021 + 0x0000001B - VBANK - this field configures the length between vsync and valid line (by line) for dpi output + CH4_TT_FC + NA 0 - 12 + 3 read-write - VSYNC - this field configures the length of vsync (by line) for dpi output - 16 - 12 + CH4_HS_SEL_SRC + NA + 3 + 1 read-write - - - - DPI_H_CFG0 - dsi bridge dpi h config register 0 - 0x38 - 0x20 - 0x02800320 - - HTOTAL - this field configures the total length of one line (by pixel num) for dpi output, must meet: reg_htotal > reg_hdisp+reg_hsync+reg_hbank - 0 - 12 + CH4_HS_SEL_DST + NA + 4 + 1 read-write - HDISP - this field configures the length of valid pixel data (by pixel num) for dpi output - 16 - 12 + CH4_SRC_HWHS_POL + NA + 5 + 1 + read-only + + + CH4_DST_HWHS_POL + NA + 6 + 1 + read-only + + + CH4_SRC_PER + NA + 7 + 2 read-write - - - - DPI_H_CFG1 - dsi bridge dpi h config register 1 - 0x3C - 0x20 - 0x00600030 - - HBANK - this field configures the length between hsync and pixel data valid (by pixel num) for dpi output - 0 - 12 + CH4_DST_PER + NA + 12 + 2 read-write - HSYNC - this field configures the length of hsync (by pixel num) for dpi output - 16 - 12 + CH4_CH_PRIOR + NA + 17 + 3 read-write - - - - DPI_MISC_CONFIG - dsi_bridge dpi misc config register - 0x40 - 0x20 - 0x000019D0 - - DPI_EN - this bit configures enable of dpi output, 0: disable, 1: enable - 0 + CH4_LOCK_CH + NA + 20 1 + read-only + + + CH4_LOCK_CH_L + NA + 21 + 2 + read-only + + + CH4_SRC_OSR_LMT + NA + 23 + 4 read-write - FIFO_UNDERRUN_DISCARD_VCNT - this field configures the underrun interrupt musk, when underrun occurs and line cnt is less then this field - 4 - 12 + CH4_DST_OSR_LMT + NA + 27 + 4 read-write - DPI_CONFIG_UPDATE - dsi_bridge dpi config update register - 0x44 + CH4_LLP0 + NA + 0x428 0x20 - DPI_CONFIG_UPDATE - write 1 to this bit to update dpi config register MIPI_DSI_BRG_DPI_* + CH4_LMS + NA 0 1 - write-only + read-write - - - - INT_ENA - dsi_bridge interrupt enable register - 0x50 - 0x20 - - UNDERRUN_INT_ENA - write 1 to enables dpi_underrun_int_st field of MIPI_DSI_BRG_INT_ST_REG controlled by dpi_underrun interrupt signal - 0 - 1 + CH4_LOC0 + NA + 6 + 26 read-write - INT_CLR - dsi_bridge interrupt clear register - 0x54 + CH4_LLP1 + NA + 0x42C 0x20 - UNDERRUN_INT_CLR - write 1 to this bit to clear dpi_underrun_int_raw field of MIPI_DSI_BRG_INT_RAW_REG + CH4_LOC1 + NA 0 - 1 - write-only + 32 + read-write - INT_RAW - dsi_bridge raw interrupt register - 0x58 + CH4_STATUS0 + NA + 0x430 0x20 - UNDERRUN_INT_RAW - the raw interrupt status of dpi_underrun + CH4_CMPLTD_BLK_TFR_SIZE + NA 0 - 1 - read-write + 22 + read-only - INT_ST - dsi_bridge masked interrupt register - 0x5C + CH4_STATUS1 + NA + 0x434 0x20 - UNDERRUN_INT_ST - the masked interrupt status of dpi_underrun + CH4_DATA_LEFT_IN_FIFO + NA 0 - 1 + 15 read-only - HOST_BIST_CTL - dsi_bridge host bist control register - 0x60 + CH4_SWHSSRC0 + NA + 0x438 0x20 - BISTOK - bistok + CH4_SWHS_REQ_SRC + NA 0 1 - read-only + read-write - BISTON - biston + CH4_SWHS_REQ_SRC_WE + NA 1 1 - read-write + write-only - - - - HOST_TRIGGER_REV - dsi_bridge host trigger reverse control register - 0x64 - 0x20 - - TX_TRIGGER_REV_EN - tx_trigger reverse. 0: disable, 1: enable - 0 + CH4_SWHS_SGLREQ_SRC + NA + 2 1 read-write - RX_TRIGGER_REV_EN - rx_trigger reverse. 0: disable, 1: enable - 1 + CH4_SWHS_SGLREQ_SRC_WE + NA + 3 1 - read-write + write-only - - - - BLK_RAW_NUM_CFG - dsi_bridge block raw number control register - 0x68 - 0x20 - 0x00038400 - - BLK_RAW_NUM_TOTAL - this field configures number of total block pix bits/64 - 0 - 22 + CH4_SWHS_LST_SRC + NA + 4 + 1 read-write - BLK_RAW_NUM_TOTAL_SET - write 1 to reload reg_blk_raw_num_total to internal cnt - 31 + CH4_SWHS_LST_SRC_WE + NA + 5 1 write-only - DMA_FRAME_INTERVAL - dsi_bridge dam frame interval control register - 0x6C + CH4_SWHSDST0 + NA + 0x440 0x20 - 0x20002409 - DMA_FRAME_SLOT - this field configures the max frame_slot_cnt + CH4_SWHS_REQ_DST + NA 0 - 10 + 1 read-write - DMA_FRAME_INTERVAL - this field configures the max frame_interval_cnt, frame_interval_cnt increased by 1 when frame_slot_cnt if full - 10 - 18 - read-write + CH4_SWHS_REQ_DST_WE + NA + 1 + 1 + write-only - DMA_MULTIBLK_EN - this bit configures enable multi-blk transfer, 0: disable, 1: enable - 28 + CH4_SWHS_SGLREQ_DST + NA + 2 1 read-write - EN - this bit configures enable interval between frame transfer, 0: disable, 1: enable - 29 + CH4_SWHS_SGLREQ_DST_WE + NA + 3 + 1 + write-only + + + CH4_SWHS_LST_DST + NA + 4 1 read-write + + CH4_SWHS_LST_DST_WE + NA + 5 + 1 + write-only + - MEM_AUX_CTRL - dsi_bridge mem aux control register - 0x70 + CH4_BLK_TFR_RESUMEREQ0 + NA + 0x448 0x20 - 0x00001320 - DSI_MEM_AUX_CTRL - this field configures dsi_bridge fifo memory aux ctrl + CH4_BLK_TFR_RESUMEREQ + NA 0 - 14 - read-write + 1 + write-only - RDN_ECO_CS - dsi_bridge rdn eco cs register - 0x74 + CH4_AXI_ID0 + NA + 0x450 0x20 - RDN_ECO_EN - rdn_eco_en + CH4_AXI_READ_ID_SUFFIX + NA 0 1 read-write - RDN_ECO_RESULT - rdn_eco_result - 1 + CH4_AXI_WRITE_ID_SUFFIX + NA + 16 1 - read-only + read-write - RDN_ECO_LOW - dsi_bridge rdn eco all low register - 0x78 + CH4_AXI_QOS0 + NA + 0x458 0x20 - RDN_ECO_LOW - rdn_eco_low + CH4_AXI_AWQOS + NA 0 - 32 + 4 + read-write + + + CH4_AXI_ARQOS + NA + 4 + 4 read-write - RDN_ECO_HIGH - dsi_bridge rdn eco all high register - 0x7C + CH4_SSTAT0 + NA + 0x460 0x20 - 0xFFFFFFFF - RDN_ECO_HIGH - rdn_eco_high + CH4_SSTAT + NA 0 32 - read-write + read-only - HOST_CTRL - dsi_bridge host control register - 0x80 + CH4_DSTAT0 + NA + 0x468 0x20 - 0x00000001 - DSI_CFG_REF_CLK_EN - this bit configures the clk enable refclk and cfg_clk of dsi_host. 0: disable, 1: enable + CH4_DSTAT + NA 0 - 1 - read-write + 32 + read-only - MEM_CLK_CTRL - dsi_bridge mem force on control register - 0x84 + CH4_SSTATAR0 + NA + 0x470 0x20 - DSI_BRIDGE_MEM_CLK_FORCE_ON - this bit configures the clock force on of dsi_bridge fifo memory. 0: disable, 1: force on + CH4_SSTATAR0 + NA 0 - 1 - read-write - - - DSI_MEM_CLK_FORCE_ON - this bit configures the clock force on of dpi fifo memory. 0: disable, 1: force on - 1 - 1 + 32 read-write - DMA_FLOW_CTRL - dsi_bridge dma flow controller register - 0x88 + CH4_SSTATAR1 + NA + 0x474 0x20 - 0x00000011 - DSI_DMA_FLOW_CONTROLLER - this bit configures the flow controller, 0: dmac as flow controller, 1:dsi_bridge as flow controller + CH4_SSTATAR1 + NA 0 - 1 + 32 read-write + + + + CH4_DSTATAR0 + NA + 0x478 + 0x20 + - DMA_FLOW_MULTIBLK_NUM - this field configures the num of blocks when multi-blk is enable and dmac as flow controller - 4 - 4 + CH4_DSTATAR0 + NA + 0 + 32 read-write - RAW_BUF_ALMOST_EMPTY_THRD - dsi_bridge buffer empty threshold register - 0x8C + CH4_DSTATAR1 + NA + 0x47C 0x20 - 0x00000200 - DSI_RAW_BUF_ALMOST_EMPTY_THRD - this field configures the fifo almost empty threshold, is valid only when dmac as flow controller + CH4_DSTATAR1 + NA 0 - 11 + 32 read-write - YUV_CFG - dsi_bridge yuv format config register - 0x90 + CH4_INTSTATUS_ENABLE0 + NA + 0x480 0x20 + 0xFA3F7FFB - PROTOCAL - this bit configures yuv protoocl, 0: bt.601, 1: bt.709 + CH4_ENABLE_BLOCK_TFR_DONE_INTSTAT + NA 0 1 read-write - YUV_PIX_ENDIAN - this bit configures yuv pixel endian, 0: y0u0y1v1y2u2y3v3, 1: y3u3y2v2y1u1y0v0 + CH4_ENABLE_DMA_TFR_DONE_INTSTAT + NA 1 1 read-write - YUV422_FORMAT - this field configures yuv422 store format, 0: yuyv, 1: yvyu, 2: uyvy, 3: vyuy - 2 - 2 - read-write - - - - - PHY_LP_LOOPBACK_CTRL - dsi phy lp_loopback test ctrl - 0x94 - 0x20 - - - PHY_LP_TXDATAESC_1 - txdataesc_1 ctrl when enable dsi phy lp_loopback_test - 0 - 8 + CH4_ENABLE_SRC_TRANSCOMP_INTSTAT + NA + 3 + 1 read-write - PHY_LP_TXREQUESTESC_1 - txrequestesc_1 ctrl when enable dsi phy lp_loopback_test - 8 + CH4_ENABLE_DST_TRANSCOMP_INTSTAT + NA + 4 1 read-write - PHY_LP_TXVALIDESC_1 - txvalidesc_1 ctrl when enable dsi phy lp_loopback_test - 9 + CH4_ENABLE_SRC_DEC_ERR_INTSTAT + NA + 5 1 read-write - PHY_LP_TXLPDTESC_1 - txlpdtesc_1 ctrl when enable dsi phy lp_loopback_test - 10 + CH4_ENABLE_DST_DEC_ERR_INTSTAT + NA + 6 1 read-write - PHY_LP_BASEDIR_1 - basedir_1 ctrl when enable dsi phy lp_loopback_test - 11 + CH4_ENABLE_SRC_SLV_ERR_INTSTAT + NA + 7 1 read-write - PHY_LP_TXDATAESC_0 - txdataesc_0 ctrl when enable dsi phy lp_loopback_test - 16 - 8 + CH4_ENABLE_DST_SLV_ERR_INTSTAT + NA + 8 + 1 read-write - PHY_LP_TXREQUESTESC_0 - txrequestesc_0 ctrl when enable dsi phy lp_loopback_test - 24 + CH4_ENABLE_LLI_RD_DEC_ERR_INTSTAT + NA + 9 1 read-write - PHY_LP_TXVALIDESC_0 - txvalidesc_0 ctrl when enable dsi phy lp_loopback_test - 25 + CH4_ENABLE_LLI_WR_DEC_ERR_INTSTAT + NA + 10 1 read-write - PHY_LP_TXLPDTESC_0 - txlpdtesc_0 ctrl when enable dsi phy lp_loopback_test - 26 + CH4_ENABLE_LLI_RD_SLV_ERR_INTSTAT + NA + 11 1 read-write - PHY_LP_BASEDIR_0 - basedir_0 ctrl when enable dsi phy lp_loopback_test - 27 + CH4_ENABLE_LLI_WR_SLV_ERR_INTSTAT + NA + 12 1 read-write - PHY_LP_LOOPBACK_CHECK - dsi phy lp_loopback test start check - 28 + CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT + NA + 13 1 - write-only + read-write - PHY_LP_LOOPBACK_CHECK_DONE - dsi phy lp_loopback test check done - 29 + CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT + NA + 14 1 - read-only + read-write - PHY_LP_LOOPBACK_EN - dsi phy lp_loopback ctrl en - 30 + CH4_ENABLE_SLVIF_DEC_ERR_INTSTAT + NA + 16 1 read-write - PHY_LP_LOOPBACK_OK - result of dsi phy lp_loopback test - 31 + CH4_ENABLE_SLVIF_WR2RO_ERR_INTSTAT + NA + 17 1 - read-only - - - - - PHY_HS_LOOPBACK_CTRL - dsi phy hp_loopback test ctrl - 0x98 - 0x20 - 0x00000200 - - - PHY_HS_TXDATAHS_1 - txdatahs_1 ctrl when enable dsi phy hs_loopback_test - 0 - 8 read-write - PHY_HS_TXREQUESTDATAHS_1 - txrequestdatahs_1 ctrl when enable dsi phy hs_loopback_test - 8 + CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT + NA + 18 1 read-write - PHY_HS_BASEDIR_1 - basedir_1 ctrl when enable dsi phy hs_loopback_test - 9 + CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT + NA + 19 1 read-write - PHY_HS_TXDATAHS_0 - txdatahs_0 ctrl when enable dsi phy hs_loopback_test - 16 - 8 + CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT + NA + 20 + 1 read-write - PHY_HS_TXREQUESTDATAHS_0 - txrequestdatahs_0 ctrl when enable dsi phy hs_loopback_test - 24 + CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT + NA + 21 1 read-write - PHY_HS_BASEDIR_0 - basedir_0 ctrl when enable dsi phy hs_loopback_test + CH4_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT + NA 25 1 - read-write + read-only - PHY_HS_TXREQUESTHSCLK - txrequesthsclk when enable dsi phy hs_loopback_test + CH4_ENABLE_CH_LOCK_CLEARED_INTSTAT + NA 27 1 read-write - PHY_HS_LOOPBACK_CHECK - dsi phy hs_loopback test start check + CH4_ENABLE_CH_SRC_SUSPENDED_INTSTAT + NA 28 1 - write-only + read-write - PHY_HS_LOOPBACK_CHECK_DONE - dsi phy hs_loopback test check done + CH4_ENABLE_CH_SUSPENDED_INTSTAT + NA 29 1 - read-only + read-write - PHY_HS_LOOPBACK_EN - dsi phy hs_loopback ctrl en + CH4_ENABLE_CH_DISABLED_INTSTAT + NA 30 1 read-write - PHY_HS_LOOPBACK_OK - result of dsi phy hs_loopback test + CH4_ENABLE_CH_ABORTED_INTSTAT + NA 31 1 - read-only + read-write - PHY_LOOPBACK_CNT - loopback test cnt - 0x9C + CH4_INTSTATUS_ENABLE1 + NA + 0x484 0x20 - 0x00400040 + 0x0000000F - PHY_HS_CHECK_CNT_TH - hs_loopback test check cnt + CH4_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT + NA 0 - 8 - read-write + 1 + read-only - PHY_LP_CHECK_CNT_TH - lp_loopback test check cnt - 16 - 8 - read-write + CH4_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT + NA + 1 + 1 + read-only - - - - - - MIPI_DSI_HOST - MIPI Display Interface Host - DSI_HOST - 0x500A0000 - - 0x0 - 0x128 - registers - - - DSI - 88 - - - - VERSION - NA - 0x0 - 0x20 - 0x3134312A - - VERSION + CH4_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT NA - 0 - 32 + 2 + 1 read-only - - - - PWR_UP - NA - 0x4 - 0x20 - - SHUTDOWNZ + CH4_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT NA - 0 + 3 1 - read-write + read-only - CLKMGR_CFG + CH4_INTSTATUS0 NA - 0x8 + 0x488 0x20 - TX_ESC_CLK_DIVISION + CH4_BLOCK_TFR_DONE_INTSTAT NA 0 - 8 - read-write + 1 + read-only - TO_CLK_DIVISION + CH4_DMA_TFR_DONE_INTSTAT NA - 8 - 8 - read-write + 1 + 1 + read-only - - - - DPI_VCID - NA - 0xC - 0x20 - - DPI_VCID + CH4_SRC_TRANSCOMP_INTSTAT NA - 0 - 2 - read-write + 3 + 1 + read-only - - - - DPI_COLOR_CODING - NA - 0x10 - 0x20 - - DPI_COLOR_CODING + CH4_DST_TRANSCOMP_INTSTAT NA - 0 - 4 - read-write + 4 + 1 + read-only - LOOSELY18_EN + CH4_SRC_DEC_ERR_INTSTAT + NA + 5 + 1 + read-only + + + CH4_DST_DEC_ERR_INTSTAT + NA + 6 + 1 + read-only + + + CH4_SRC_SLV_ERR_INTSTAT + NA + 7 + 1 + read-only + + + CH4_DST_SLV_ERR_INTSTAT NA 8 1 - read-write + read-only - - - - DPI_CFG_POL - NA - 0x14 - 0x20 - - DATAEN_ACTIVE_LOW + CH4_LLI_RD_DEC_ERR_INTSTAT NA - 0 + 9 1 - read-write + read-only - VSYNC_ACTIVE_LOW + CH4_LLI_WR_DEC_ERR_INTSTAT NA - 1 + 10 1 - read-write + read-only - HSYNC_ACTIVE_LOW + CH4_LLI_RD_SLV_ERR_INTSTAT NA - 2 + 11 1 - read-write + read-only - SHUTD_ACTIVE_LOW + CH4_LLI_WR_SLV_ERR_INTSTAT NA - 3 + 12 1 - read-write + read-only - COLORM_ACTIVE_LOW + CH4_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT NA - 4 + 13 1 - read-write + read-only - - - - DPI_LP_CMD_TIM - NA - 0x18 - 0x20 - - INVACT_LPCMD_TIME + CH4_SLVIF_MULTIBLKTYPE_ERR_INTSTAT NA - 0 - 8 - read-write + 14 + 1 + read-only - OUTVACT_LPCMD_TIME + CH4_SLVIF_DEC_ERR_INTSTAT NA 16 - 8 - read-write + 1 + read-only - - - - DBI_VCID - NA - 0x1C - 0x20 - - DBI_VCID + CH4_SLVIF_WR2RO_ERR_INTSTAT NA - 0 - 2 - read-write + 17 + 1 + read-only - - - - DBI_CFG - NA - 0x20 - 0x20 - - IN_DBI_CONF + CH4_SLVIF_RD2RWO_ERR_INTSTAT NA - 0 - 4 - read-write + 18 + 1 + read-only - OUT_DBI_CONF + CH4_SLVIF_WRONCHEN_ERR_INTSTAT NA - 8 - 4 - read-write + 19 + 1 + read-only - LUT_SIZE_CONF + CH4_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT NA - 16 - 2 - read-write + 20 + 1 + read-only - - - - DBI_PARTITIONING_EN - NA - 0x24 - 0x20 - - PARTITIONING_EN + CH4_SLVIF_WRONHOLD_ERR_INTSTAT NA - 0 + 21 1 - read-write + read-only - - - - DBI_CMDSIZE - NA - 0x28 - 0x20 - - WR_CMD_SIZE + CH4_SLVIF_WRPARITY_ERR_INTSTAT NA - 0 - 16 - read-write + 25 + 1 + read-only - ALLOWED_CMD_SIZE + CH4_CH_LOCK_CLEARED_INTSTAT NA - 16 - 16 - read-write + 27 + 1 + read-only + + + CH4_CH_SRC_SUSPENDED_INTSTAT + NA + 28 + 1 + read-only + + + CH4_CH_SUSPENDED_INTSTAT + NA + 29 + 1 + read-only + + + CH4_CH_DISABLED_INTSTAT + NA + 30 + 1 + read-only + + + CH4_CH_ABORTED_INTSTAT + NA + 31 + 1 + read-only - PCKHDL_CFG + CH4_INTSTATUS1 NA - 0x2C + 0x48C 0x20 - EOTP_TX_EN + CH4_ECC_PROT_CHMEM_CORRERR_INTSTAT NA 0 1 - read-write + read-only - EOTP_RX_EN + CH4_ECC_PROT_CHMEM_UNCORRERR_INTSTAT NA 1 1 - read-write + read-only - BTA_EN + CH4_ECC_PROT_UIDMEM_CORRERR_INTSTAT NA 2 1 - read-write + read-only - ECC_RX_EN + CH4_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT NA 3 1 - read-write + read-only + + + + CH4_INTSIGNAL_ENABLE0 + NA + 0x490 + 0x20 + 0xFA3F7FFB + - CRC_RX_EN + CH4_ENABLE_BLOCK_TFR_DONE_INTSIGNAL NA - 4 + 0 1 read-write - EOTP_TX_LP_EN + CH4_ENABLE_DMA_TFR_DONE_INTSIGNAL NA - 5 + 1 1 read-write - - - - GEN_VCID - NA - 0x30 - 0x20 - - RX + CH4_ENABLE_SRC_TRANSCOMP_INTSIGNAL NA - 0 - 2 + 3 + 1 read-write - TEAR_AUTO + CH4_ENABLE_DST_TRANSCOMP_INTSIGNAL NA - 8 - 2 + 4 + 1 read-write - TX_AUTO + CH4_ENABLE_SRC_DEC_ERR_INTSIGNAL NA - 16 - 2 + 5 + 1 read-write - - - - MODE_CFG - NA - 0x34 - 0x20 - 0x00000001 - - CMD_VIDEO_MODE + CH4_ENABLE_DST_DEC_ERR_INTSIGNAL NA - 0 + 6 1 read-write - - - - VID_MODE_CFG - NA - 0x38 - 0x20 - - VID_MODE_TYPE + CH4_ENABLE_SRC_SLV_ERR_INTSIGNAL NA - 0 - 2 + 7 + 1 read-write - LP_VSA_EN + CH4_ENABLE_DST_SLV_ERR_INTSIGNAL NA 8 1 read-write - LP_VBP_EN + CH4_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL NA 9 1 read-write - LP_VFP_EN + CH4_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL NA 10 1 read-write - LP_VACT_EN + CH4_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL NA 11 1 read-write - LP_HBP_EN + CH4_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL NA 12 1 read-write - LP_HFP_EN + CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL NA 13 1 read-write - FRAME_BTA_ACK_EN + CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL NA 14 1 read-write - LP_CMD_EN + CH4_ENABLE_SLVIF_DEC_ERR_INTSIGNAL NA - 15 + 16 1 read-write - VPG_EN + CH4_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL NA - 16 + 17 1 read-write - VPG_MODE + CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL NA - 20 + 18 1 read-write - VPG_ORIENTATION + CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL NA - 24 + 19 1 read-write - - - - VID_PKT_SIZE - NA - 0x3C - 0x20 - - VID_PKT_SIZE + CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL NA - 0 - 14 + 20 + 1 read-write - - - - VID_NUM_CHUNKS - NA - 0x40 - 0x20 - - VID_NUM_CHUNKS + CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL NA - 0 - 13 + 21 + 1 read-write - - - - VID_NULL_SIZE - NA - 0x44 - 0x20 - - VID_NULL_SIZE + CH4_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL NA - 0 - 13 - read-write + 25 + 1 + read-only - - - - VID_HSA_TIME - NA - 0x48 - 0x20 - - VID_HSA_TIME + CH4_ENABLE_CH_LOCK_CLEARED_INTSIGNAL NA - 0 - 12 + 27 + 1 read-write - - - - VID_HBP_TIME - NA - 0x4C - 0x20 - - VID_HBP_TIME + CH4_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL NA - 0 - 12 + 28 + 1 read-write - - - - VID_HLINE_TIME - NA - 0x50 - 0x20 - - VID_HLINE_TIME + CH4_ENABLE_CH_SUSPENDED_INTSIGNAL NA - 0 - 15 + 29 + 1 read-write - - - - VID_VSA_LINES - NA - 0x54 - 0x20 - - VSA_LINES + CH4_ENABLE_CH_DISABLED_INTSIGNAL NA - 0 - 10 + 30 + 1 read-write - - - - VID_VBP_LINES - NA - 0x58 - 0x20 - - VBP_LINES + CH4_ENABLE_CH_ABORTED_INTSIGNAL NA - 0 - 10 + 31 + 1 read-write - VID_VFP_LINES + CH4_INTSIGNAL_ENABLE1 NA - 0x5C + 0x494 0x20 + 0x0000000F - VFP_LINES + CH4_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL NA 0 - 10 - read-write + 1 + read-only - - - - VID_VACTIVE_LINES - NA - 0x60 - 0x20 - - V_ACTIVE_LINES + CH4_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL NA - 0 - 14 - read-write + 1 + 1 + read-only - - - - EDPI_CMD_SIZE - NA - 0x64 - 0x20 - - EDPI_ALLOWED_CMD_SIZE + CH4_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL NA - 0 - 16 - read-write + 2 + 1 + read-only + + + CH4_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL + NA + 3 + 1 + read-only - CMD_MODE_CFG + CH4_INTCLEAR0 NA - 0x68 + 0x498 0x20 - TEAR_FX_EN + CH4_CLEAR_BLOCK_TFR_DONE_INTSTAT NA 0 1 - read-write + write-only - ACK_RQST_EN + CH4_CLEAR_DMA_TFR_DONE_INTSTAT NA 1 1 - read-write + write-only - GEN_SW_0P_TX + CH4_CLEAR_SRC_TRANSCOMP_INTSTAT + NA + 3 + 1 + write-only + + + CH4_CLEAR_DST_TRANSCOMP_INTSTAT + NA + 4 + 1 + write-only + + + CH4_CLEAR_SRC_DEC_ERR_INTSTAT + NA + 5 + 1 + write-only + + + CH4_CLEAR_DST_DEC_ERR_INTSTAT + NA + 6 + 1 + write-only + + + CH4_CLEAR_SRC_SLV_ERR_INTSTAT + NA + 7 + 1 + write-only + + + CH4_CLEAR_DST_SLV_ERR_INTSTAT NA 8 1 - read-write + write-only - GEN_SW_1P_TX + CH4_CLEAR_LLI_RD_DEC_ERR_INTSTAT NA 9 1 - read-write + write-only - GEN_SW_2P_TX + CH4_CLEAR_LLI_WR_DEC_ERR_INTSTAT NA 10 1 - read-write + write-only - GEN_SR_0P_TX + CH4_CLEAR_LLI_RD_SLV_ERR_INTSTAT NA 11 1 - read-write + write-only - GEN_SR_1P_TX + CH4_CLEAR_LLI_WR_SLV_ERR_INTSTAT NA 12 1 - read-write + write-only - GEN_SR_2P_TX + CH4_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT NA 13 1 - read-write + write-only - GEN_LW_TX + CH4_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT NA 14 1 - read-write + write-only - DCS_SW_0P_TX + CH4_CLEAR_SLVIF_DEC_ERR_INTSTAT NA 16 1 - read-write + write-only - DCS_SW_1P_TX + CH4_CLEAR_SLVIF_WR2RO_ERR_INTSTAT NA 17 1 - read-write + write-only - DCS_SR_0P_TX + CH4_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT NA 18 1 - read-write + write-only - DCS_LW_TX + CH4_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT NA 19 1 - read-write + write-only - MAX_RD_PKT_SIZE + CH4_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT NA - 24 + 20 1 - read-write - - - - - GEN_HDR - NA - 0x6C - 0x20 - - - GEN_DT - NA - 0 - 6 - read-write + write-only - GEN_VC + CH4_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT NA - 6 - 2 - read-write + 21 + 1 + write-only - GEN_WC_LSBYTE + CH4_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT NA - 8 - 8 - read-write + 25 + 1 + write-only - GEN_WC_MSBYTE + CH4_CLEAR_CH_LOCK_CLEARED_INTSTAT NA - 16 - 8 - read-write + 27 + 1 + write-only - - - - GEN_PLD_DATA - NA - 0x70 - 0x20 - - GEN_PLD_B1 + CH4_CLEAR_CH_SRC_SUSPENDED_INTSTAT NA - 0 - 8 - read-write + 28 + 1 + write-only - GEN_PLD_B2 + CH4_CLEAR_CH_SUSPENDED_INTSTAT NA - 8 - 8 - read-write + 29 + 1 + write-only - GEN_PLD_B3 + CH4_CLEAR_CH_DISABLED_INTSTAT NA - 16 - 8 - read-write + 30 + 1 + write-only - GEN_PLD_B4 + CH4_CLEAR_CH_ABORTED_INTSTAT NA - 24 - 8 - read-write + 31 + 1 + write-only - CMD_PKT_STATUS + CH4_INTCLEAR1 NA - 0x74 + 0x49C 0x20 - 0x00050015 - GEN_CMD_EMPTY + CH4_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT NA 0 1 - read-only + write-only - GEN_CMD_FULL + CH4_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT NA 1 1 - read-only + write-only - GEN_PLD_W_EMPTY + CH4_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT NA 2 1 - read-only + write-only - GEN_PLD_W_FULL + CH4_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT NA 3 1 - read-only + write-only + + + + + + DS + Digital Signature + DS + 0x50094000 + + 0x0 + 0xA5C + registers + + + + 128 + 0x4 + Y_MEM[%s] + memory that stores Y + 0x0 + 0x20 + + + 128 + 0x4 + M_MEM[%s] + memory that stores M + 0x200 + 0x20 + + + 128 + 0x4 + RB_MEM[%s] + memory that stores Rb + 0x400 + 0x20 + + + 12 + 0x4 + BOX_MEM[%s] + memory that stores BOX + 0x600 + 0x20 + + + 4 + 0x4 + IV_MEM[%s] + memory that stores IV + 0x630 + 0x20 + + + 128 + 0x4 + X_MEM[%s] + memory that stores X + 0x800 + 0x20 + + + 128 + 0x4 + Z_MEM[%s] + memory that stores Z + 0xA00 + 0x20 + + + SET_START + DS start control register + 0xE00 + 0x20 + - GEN_PLD_R_EMPTY - NA - 4 + SET_START + set this bit to start DS operation. + 0 1 - read-only + write-only + + + + SET_CONTINUE + DS continue control register + 0xE04 + 0x20 + - GEN_PLD_R_FULL - NA - 5 + SET_CONTINUE + set this bit to continue DS operation. + 0 1 - read-only + write-only + + + + SET_FINISH + DS finish control register + 0xE08 + 0x20 + - GEN_RD_CMD_BUSY - NA - 6 + SET_FINISH + Set this bit to finish DS process. + 0 1 - read-only + write-only + + + + QUERY_BUSY + DS query busy register + 0xE0C + 0x20 + - GEN_BUFF_CMD_EMPTY - NA - 16 + QUERY_BUSY + digital signature state. 1'b0: idle, 1'b1: busy + 0 1 read-only + + + + QUERY_KEY_WRONG + DS query key-wrong counter register + 0xE10 + 0x20 + - GEN_BUFF_CMD_FULL - NA - 17 - 1 + QUERY_KEY_WRONG + digital signature key wrong counter + 0 + 4 read-only + + + + QUERY_CHECK + DS query check result register + 0xE14 + 0x20 + - GEN_BUFF_PLD_EMPTY - NA - 18 + MD_ERROR + MD checkout result. 1'b0: MD check pass, 1'b1: MD check fail + 0 1 read-only - GEN_BUFF_PLD_FULL - NA - 19 + PADDING_BAD + padding checkout result. 1'b0: a good padding, 1'b1: a bad padding + 1 1 read-only - TO_CNT_CFG - NA - 0x78 + DATE + DS version control register + 0xE20 0x20 + 0x20200618 - LPRX_TO_CNT - NA + DATE + ds version information 0 - 16 - read-write - - - HSTX_TO_CNT - NA - 16 - 16 + 30 read-write + + + + MIPI_DSI_BRIDGE + MIPI Camera Interface Bridge + DSI_BRG + 0x500A0800 + + 0x0 + 0x94 + registers + + + DSI_BRIDGE + 86 + + - HS_RD_TO_CNT - NA - 0x7C + CLK_EN + dsi bridge clk control register + 0x0 0x20 - HS_RD_TO_CNT - NA + CLK_EN + this bit configures force_on of dsi_bridge register clock gate 0 - 16 + 1 read-write - LP_RD_TO_CNT - NA - 0x80 + EN + dsi bridge en register + 0x4 0x20 - LP_RD_TO_CNT - NA + DSI_EN + this bit configures module enable of dsi_bridge. 0: disable, 1: enable 0 - 16 + 1 read-write - HS_WR_TO_CNT - NA - 0x84 + DMA_REQ_CFG + dsi bridge dma burst len register + 0x8 0x20 + 0x00000080 - HS_WR_TO_CNT - NA + DMA_BURST_LEN + this field configures the num of 64-bit in one dma burst transfer, valid only when dsi_bridge as flow controller 0 - 16 + 12 read-write - LP_WR_TO_CNT - NA - 0x88 + RAW_NUM_CFG + dsi bridge raw number control register + 0xC 0x20 + 0x00038400 - LP_WR_TO_CNT - NA + RAW_NUM_TOTAL + this field configures number of total pix bits/64 0 - 16 + 22 read-write - - - - BTA_TO_CNT - NA - 0x8C - 0x20 - - BTA_TO_CNT - NA + UNALIGN_64BIT_EN + this field configures whether the total pix bits is a multiple of 64bits. 0: align to 64-bit, 1: unalign to 64-bit + 22 + 1 + read-write + + + RAW_NUM_TOTAL_SET + this bit configures enable of reload reg_raw_num_total to internal cnt. 0: disable, 1: enable. valid only when dsi_bridge as flow controller + 31 + 1 + write-only + + + + + RAW_BUF_CREDIT_CTL + dsi bridge credit register + 0x10 + 0x20 + 0x03200400 + + + CREDIT_THRD + this field configures the threshold whether dsi_bridge fifo can receive one more 64-bit, valid only when dsi_bridge as flow controller 0 - 16 + 15 + read-write + + + CREDIT_BURST_THRD + this field configures the threshold whether dsi_bridge fifo can receive one more dma burst, valid only when dsi_bridge as flow controller + 16 + 15 + read-write + + + CREDIT_RESET + this bit configures internal credit cnt clear, 0: non, 1: reset. valid only when dsi_bridge as flow controller + 31 + 1 read-write - SDF_3D - NA - 0x90 + FIFO_FLOW_STATUS + dsi bridge raw buffer depth register + 0x14 0x20 - MODE_3D - NA + RAW_BUF_DEPTH + this field configures the depth of dsi_bridge fifo depth 0 - 2 + 14 + read-only + + + + + PIXEL_TYPE + dsi bridge dpi type control register + 0x18 + 0x20 + + + RAW_TYPE + this field configures the pixel type. 0: rgb888, 1:rgb666, 2:rgb565 + 0 + 4 read-write - FORMAT_3D - NA - 2 + DPI_CONFIG + this field configures the pixel arrange type of dpi interface + 4 2 read-write - SECOND_VSYNC - NA - 4 + DATA_IN_TYPE + input data type, 0: rgb, 1: yuv + 6 1 read-write + + + + DMA_BLOCK_INTERVAL + dsi bridge dma block interval control register + 0x1C + 0x20 + 0x30002409 + - RIGHT_FIRST - NA - 5 + DMA_BLOCK_SLOT + this field configures the max block_slot_cnt + 0 + 10 + read-write + + + DMA_BLOCK_INTERVAL + this field configures the max block_interval_cnt, block_interval_cnt increased by 1 when block_slot_cnt if full + 10 + 18 + read-write + + + RAW_NUM_TOTAL_AUTO_RELOAD + this bit configures enable of auto reload reg_raw_num_total, 0: disable, 1: enable + 28 1 read-write - SEND_3D_CFG - NA - 16 + EN + this bit configures enable of interval between dma block transfer, 0: disable, 1: enable + 29 1 read-write - LPCLK_CTRL - NA - 0x94 + DMA_REQ_INTERVAL + dsi bridge dma req interval control register + 0x20 0x20 + 0x00000001 - PHY_TXREQUESTCLKHS - NA + DMA_REQ_INTERVAL + this field configures the interval between dma req events + 0 + 16 + read-write + + + + + DPI_LCD_CTL + dsi bridge dpi signal control register + 0x24 + 0x20 + + + DPISHUTDN + this bit configures dpishutdn signal in dpi interface 0 1 read-write - AUTO_CLKLANE_CTRL - NA + DPICOLORM + this bit configures dpicolorm signal in dpi interface 1 1 read-write + + DPIUPDATECFG + this bit configures dpiupdatecfg signal in dpi interface + 2 + 1 + read-write + - PHY_TMR_LPCLK_CFG - NA - 0x98 + DPI_RSV_DPI_DATA + dsi bridge dpi reserved data register + 0x28 + 0x20 + 0x00003FFF + + + DPI_RSV_DATA + this field controls the pixel data sent to dsi_host when dsi_bridge fifo underflow + 0 + 30 + read-write + + + + + DPI_V_CFG0 + dsi bridge dpi v config register 0 + 0x30 0x20 + 0x01E0020D - PHY_CLKLP2HS_TIME - NA + VTOTAL + this field configures the total length of one frame (by line) for dpi output, must meet: reg_vtotal > reg_vdisp+reg_vsync+reg_vbank 0 - 10 + 12 read-write - PHY_CLKHS2LP_TIME - NA + VDISP + this field configures the length of valid line (by line) for dpi output 16 - 10 + 12 read-write - PHY_TMR_CFG - NA - 0x9C + DPI_V_CFG1 + dsi bridge dpi v config register 1 + 0x34 0x20 + 0x00020021 - PHY_LP2HS_TIME - NA + VBANK + this field configures the length between vsync and valid line (by line) for dpi output 0 - 10 + 12 read-write - PHY_HS2LP_TIME - NA + VSYNC + this field configures the length of vsync (by line) for dpi output 16 - 10 + 12 read-write - PHY_RSTZ - NA - 0xA0 + DPI_H_CFG0 + dsi bridge dpi h config register 0 + 0x38 0x20 + 0x02800320 - PHY_SHUTDOWNZ - NA + HTOTAL + this field configures the total length of one line (by pixel num) for dpi output, must meet: reg_htotal > reg_hdisp+reg_hsync+reg_hbank 0 - 1 + 12 read-write - PHY_RSTZ - NA - 1 - 1 + HDISP + this field configures the length of valid pixel data (by pixel num) for dpi output + 16 + 12 read-write + + + + DPI_H_CFG1 + dsi bridge dpi h config register 1 + 0x3C + 0x20 + 0x00600030 + - PHY_ENABLECLK - NA - 2 - 1 + HBANK + this field configures the length between hsync and pixel data valid (by pixel num) for dpi output + 0 + 12 read-write - PHY_FORCEPLL - NA - 3 - 1 + HSYNC + this field configures the length of hsync (by pixel num) for dpi output + 16 + 12 read-write - PHY_IF_CFG - NA - 0xA4 + DPI_MISC_CONFIG + dsi_bridge dpi misc config register + 0x40 0x20 - 0x00000001 + 0x000019D0 - N_LANES - NA + DPI_EN + this bit configures enable of dpi output, 0: disable, 1: enable 0 - 2 + 1 read-write - PHY_STOP_WAIT_TIME - NA - 8 - 8 + FIFO_UNDERRUN_DISCARD_VCNT + this field configures the underrun interrupt musk, when underrun occurs and line cnt is less then this field + 4 + 12 read-write - PHY_ULPS_CTRL - NA - 0xA8 + DPI_CONFIG_UPDATE + dsi_bridge dpi config update register + 0x44 0x20 - PHY_TXREQULPSCLK - NA + DPI_CONFIG_UPDATE + write 1 to this bit to update dpi config register MIPI_DSI_BRG_DPI_* 0 1 - read-write + write-only + + + + INT_ENA + dsi_bridge interrupt enable register + 0x50 + 0x20 + - PHY_TXEXITULPSCLK - NA - 1 + UNDERRUN_INT_ENA + write 1 to enables dpi_underrun_int_st field of MIPI_DSI_BRG_INT_ST_REG controlled by dpi_underrun interrupt signal + 0 1 read-write + + + + INT_CLR + dsi_bridge interrupt clear register + 0x54 + 0x20 + - PHY_TXREQULPSLAN - NA - 2 + UNDERRUN_INT_CLR + write 1 to this bit to clear dpi_underrun_int_raw field of MIPI_DSI_BRG_INT_RAW_REG + 0 1 - read-write + write-only + + + + INT_RAW + dsi_bridge raw interrupt register + 0x58 + 0x20 + - PHY_TXEXITULPSLAN - NA - 3 + UNDERRUN_INT_RAW + the raw interrupt status of dpi_underrun + 0 1 read-write - PHY_TX_TRIGGERS - NA - 0xAC + INT_ST + dsi_bridge masked interrupt register + 0x5C 0x20 - PHY_TX_TRIGGERS - NA + UNDERRUN_INT_ST + the masked interrupt status of dpi_underrun 0 - 4 - read-write + 1 + read-only - PHY_STATUS - NA - 0xB0 + HOST_BIST_CTL + dsi_bridge host bist control register + 0x60 0x20 - 0x00000140 - PHY_LOCK - NA + BISTOK + bistok 0 1 read-only - PHY_DIRECTION - NA + BISTON + biston 1 1 - read-only + read-write + + + + HOST_TRIGGER_REV + dsi_bridge host trigger reverse control register + 0x64 + 0x20 + - PHY_STOPSTATECLKLANE - NA - 2 + TX_TRIGGER_REV_EN + tx_trigger reverse. 0: disable, 1: enable + 0 1 - read-only + read-write - PHY_ULPSACTIVENOTCLK - NA - 3 + RX_TRIGGER_REV_EN + rx_trigger reverse. 0: disable, 1: enable + 1 1 - read-only + read-write + + + + BLK_RAW_NUM_CFG + dsi_bridge block raw number control register + 0x68 + 0x20 + 0x00038400 + - PHY_STOPSTATE0LANE - NA - 4 - 1 - read-only + BLK_RAW_NUM_TOTAL + this field configures number of total block pix bits/64 + 0 + 22 + read-write - PHY_ULPSACTIVENOT0LANE - NA - 5 + BLK_RAW_NUM_TOTAL_SET + write 1 to reload reg_blk_raw_num_total to internal cnt + 31 1 - read-only + write-only + + + + + DMA_FRAME_INTERVAL + dsi_bridge dam frame interval control register + 0x6C + 0x20 + 0x20002409 + + + DMA_FRAME_SLOT + this field configures the max frame_slot_cnt + 0 + 10 + read-write - PHY_RXULPSESC0LANE - NA - 6 - 1 - read-only + DMA_FRAME_INTERVAL + this field configures the max frame_interval_cnt, frame_interval_cnt increased by 1 when frame_slot_cnt if full + 10 + 18 + read-write - PHY_STOPSTATE1LANE - NA - 7 + DMA_MULTIBLK_EN + this bit configures enable multi-blk transfer, 0: disable, 1: enable + 28 1 - read-only + read-write - PHY_ULPSACTIVENOT1LANE - NA - 8 + EN + this bit configures enable interval between frame transfer, 0: disable, 1: enable + 29 1 - read-only + read-write - PHY_TST_CTRL0 - NA - 0xB4 + MEM_AUX_CTRL + dsi_bridge mem aux control register + 0x70 0x20 - 0x00000001 + 0x00001320 - PHY_TESTCLR - NA + DSI_MEM_AUX_CTRL + this field configures dsi_bridge fifo memory aux ctrl + 0 + 14 + read-write + + + + + RDN_ECO_CS + dsi_bridge rdn eco cs register + 0x74 + 0x20 + + + RDN_ECO_EN + rdn_eco_en 0 1 read-write - PHY_TESTCLK - NA + RDN_ECO_RESULT + rdn_eco_result 1 1 - read-write + read-only - PHY_TST_CTRL1 - NA - 0xB8 + RDN_ECO_LOW + dsi_bridge rdn eco all low register + 0x78 0x20 - PHY_TESTDIN - NA + RDN_ECO_LOW + rdn_eco_low 0 - 8 + 32 read-write + + + + RDN_ECO_HIGH + dsi_bridge rdn eco all high register + 0x7C + 0x20 + 0xFFFFFFFF + - PHT_TESTDOUT - NA - 8 - 8 - read-only + RDN_ECO_HIGH + rdn_eco_high + 0 + 32 + read-write + + + + HOST_CTRL + dsi_bridge host control register + 0x80 + 0x20 + 0x00000001 + - PHY_TESTEN - NA - 16 + DSI_CFG_REF_CLK_EN + this bit configures the clk enable refclk and cfg_clk of dsi_host. 0: disable, 1: enable + 0 1 read-write - INT_ST0 - NA - 0xBC + MEM_CLK_CTRL + dsi_bridge mem force on control register + 0x84 0x20 - ACK_WITH_ERR_0 - NA + DSI_BRIDGE_MEM_CLK_FORCE_ON + this bit configures the clock force on of dsi_bridge fifo memory. 0: disable, 1: force on 0 1 - read-only + read-write - ACK_WITH_ERR_1 - NA + DSI_MEM_CLK_FORCE_ON + this bit configures the clock force on of dpi fifo memory. 0: disable, 1: force on 1 1 - read-only + read-write + + + + DMA_FLOW_CTRL + dsi_bridge dma flow controller register + 0x88 + 0x20 + 0x00000011 + - ACK_WITH_ERR_2 - NA - 2 + DSI_DMA_FLOW_CONTROLLER + this bit configures the flow controller, 0: dmac as flow controller, 1:dsi_bridge as flow controller + 0 1 - read-only + read-write - ACK_WITH_ERR_3 - NA - 3 - 1 - read-only + DMA_FLOW_MULTIBLK_NUM + this field configures the num of blocks when multi-blk is enable and dmac as flow controller + 4 + 4 + read-write + + + + RAW_BUF_ALMOST_EMPTY_THRD + dsi_bridge buffer empty threshold register + 0x8C + 0x20 + 0x00000200 + - ACK_WITH_ERR_4 - NA - 4 - 1 - read-only + DSI_RAW_BUF_ALMOST_EMPTY_THRD + this field configures the fifo almost empty threshold, is valid only when dmac as flow controller + 0 + 11 + read-write + + + + YUV_CFG + dsi_bridge yuv format config register + 0x90 + 0x20 + - ACK_WITH_ERR_5 - NA - 5 + PROTOCAL + this bit configures yuv protoocl, 0: bt.601, 1: bt.709 + 0 1 - read-only + read-write - ACK_WITH_ERR_6 - NA - 6 + YUV_PIX_ENDIAN + this bit configures yuv pixel endian, 0: y0u0y1v1y2u2y3v3, 1: y3u3y2v2y1u1y0v0 + 1 1 - read-only + read-write - ACK_WITH_ERR_7 - NA - 7 - 1 - read-only + YUV422_FORMAT + this field configures yuv422 store format, 0: yuyv, 1: yvyu, 2: uyvy, 3: vyuy + 2 + 2 + read-write + + + + + PHY_LP_LOOPBACK_CTRL + dsi phy lp_loopback test ctrl + 0x94 + 0x20 + + + PHY_LP_TXDATAESC_1 + txdataesc_1 ctrl when enable dsi phy lp_loopback_test + 0 + 8 + read-write - ACK_WITH_ERR_8 - NA + PHY_LP_TXREQUESTESC_1 + txrequestesc_1 ctrl when enable dsi phy lp_loopback_test 8 1 - read-only + read-write - ACK_WITH_ERR_9 - NA + PHY_LP_TXVALIDESC_1 + txvalidesc_1 ctrl when enable dsi phy lp_loopback_test 9 1 - read-only + read-write - ACK_WITH_ERR_10 - NA + PHY_LP_TXLPDTESC_1 + txlpdtesc_1 ctrl when enable dsi phy lp_loopback_test 10 1 - read-only + read-write - ACK_WITH_ERR_11 - NA + PHY_LP_BASEDIR_1 + basedir_1 ctrl when enable dsi phy lp_loopback_test 11 1 - read-only + read-write - ACK_WITH_ERR_12 - NA - 12 - 1 - read-only + PHY_LP_TXDATAESC_0 + txdataesc_0 ctrl when enable dsi phy lp_loopback_test + 16 + 8 + read-write - ACK_WITH_ERR_13 - NA - 13 + PHY_LP_TXREQUESTESC_0 + txrequestesc_0 ctrl when enable dsi phy lp_loopback_test + 24 1 - read-only + read-write - ACK_WITH_ERR_14 - NA - 14 + PHY_LP_TXVALIDESC_0 + txvalidesc_0 ctrl when enable dsi phy lp_loopback_test + 25 1 - read-only + read-write - ACK_WITH_ERR_15 - NA - 15 + PHY_LP_TXLPDTESC_0 + txlpdtesc_0 ctrl when enable dsi phy lp_loopback_test + 26 1 - read-only + read-write - DPHY_ERRORS_0 - NA - 16 + PHY_LP_BASEDIR_0 + basedir_0 ctrl when enable dsi phy lp_loopback_test + 27 1 - read-only + read-write - DPHY_ERRORS_1 - NA - 17 + PHY_LP_LOOPBACK_CHECK + dsi phy lp_loopback test start check + 28 1 - read-only + write-only - DPHY_ERRORS_2 - NA - 18 + PHY_LP_LOOPBACK_CHECK_DONE + dsi phy lp_loopback test check done + 29 1 read-only - DPHY_ERRORS_3 - NA - 19 + PHY_LP_LOOPBACK_EN + dsi phy lp_loopback ctrl en + 30 1 - read-only + read-write - DPHY_ERRORS_4 - NA - 20 + PHY_LP_LOOPBACK_OK + result of dsi phy lp_loopback test + 31 1 read-only - INT_ST1 - NA - 0xC0 + PHY_HS_LOOPBACK_CTRL + dsi phy hp_loopback test ctrl + 0x98 0x20 + 0x00000200 - TO_HS_TX - NA + PHY_HS_TXDATAHS_1 + txdatahs_1 ctrl when enable dsi phy hs_loopback_test 0 - 1 - read-only + 8 + read-write - TO_LP_RX - NA - 1 + PHY_HS_TXREQUESTDATAHS_1 + txrequestdatahs_1 ctrl when enable dsi phy hs_loopback_test + 8 1 - read-only + read-write - ECC_SINGLE_ERR - NA - 2 + PHY_HS_BASEDIR_1 + basedir_1 ctrl when enable dsi phy hs_loopback_test + 9 1 - read-only + read-write - ECC_MILTI_ERR - NA - 3 - 1 - read-only + PHY_HS_TXDATAHS_0 + txdatahs_0 ctrl when enable dsi phy hs_loopback_test + 16 + 8 + read-write - CRC_ERR - NA - 4 + PHY_HS_TXREQUESTDATAHS_0 + txrequestdatahs_0 ctrl when enable dsi phy hs_loopback_test + 24 1 - read-only + read-write - PKT_SIZE_ERR - NA - 5 + PHY_HS_BASEDIR_0 + basedir_0 ctrl when enable dsi phy hs_loopback_test + 25 1 - read-only + read-write - EOPT_ERR - NA - 6 + PHY_HS_TXREQUESTHSCLK + txrequesthsclk when enable dsi phy hs_loopback_test + 27 1 - read-only + read-write - DPI_PLD_WR_ERR - NA - 7 + PHY_HS_LOOPBACK_CHECK + dsi phy hs_loopback test start check + 28 1 - read-only + write-only - GEN_CMD_WR_ERR - NA - 8 + PHY_HS_LOOPBACK_CHECK_DONE + dsi phy hs_loopback test check done + 29 1 read-only - GEN_PLD_WR_ERR - NA - 9 + PHY_HS_LOOPBACK_EN + dsi phy hs_loopback ctrl en + 30 1 - read-only + read-write - GEN_PLD_SEND_ERR - NA - 10 + PHY_HS_LOOPBACK_OK + result of dsi phy hs_loopback test + 31 1 read-only + + + + PHY_LOOPBACK_CNT + loopback test cnt + 0x9C + 0x20 + 0x00400040 + - GEN_PLD_RD_ERR - NA - 11 - 1 - read-only + PHY_HS_CHECK_CNT_TH + hs_loopback test check cnt + 0 + 8 + read-write - GEN_PLD_RECEV_ERR - NA - 12 - 1 - read-only + PHY_LP_CHECK_CNT_TH + lp_loopback test check cnt + 16 + 8 + read-write + + + + + + MIPI_DSI_HOST + MIPI Display Interface Host + DSI_HOST + 0x500A0000 + + 0x0 + 0x128 + registers + + + DSI + 88 + + + + VERSION + NA + 0x0 + 0x20 + 0x3134312A + - DPI_BUFF_PLD_UNDER + VERSION NA - 19 - 1 + 0 + 32 read-only - INT_MSK0 + PWR_UP NA - 0xC4 + 0x4 0x20 - MASK_ACK_WITH_ERR_0 + SHUTDOWNZ NA 0 1 read-write + + + + CLKMGR_CFG + NA + 0x8 + 0x20 + - MASK_ACK_WITH_ERR_1 + TX_ESC_CLK_DIVISION NA - 1 - 1 + 0 + 8 read-write - MASK_ACK_WITH_ERR_2 + TO_CLK_DIVISION NA - 2 - 1 + 8 + 8 read-write + + + + DPI_VCID + NA + 0xC + 0x20 + - MASK_ACK_WITH_ERR_3 + DPI_VCID NA - 3 - 1 + 0 + 2 read-write + + + + DPI_COLOR_CODING + NA + 0x10 + 0x20 + - MASK_ACK_WITH_ERR_4 + DPI_COLOR_CODING NA - 4 - 1 + 0 + 4 read-write - MASK_ACK_WITH_ERR_5 + LOOSELY18_EN NA - 5 + 8 1 read-write + + + + DPI_CFG_POL + NA + 0x14 + 0x20 + - MASK_ACK_WITH_ERR_6 + DATAEN_ACTIVE_LOW NA - 6 + 0 1 read-write - MASK_ACK_WITH_ERR_7 + VSYNC_ACTIVE_LOW NA - 7 + 1 1 read-write - MASK_ACK_WITH_ERR_8 + HSYNC_ACTIVE_LOW NA - 8 + 2 1 read-write - MASK_ACK_WITH_ERR_9 + SHUTD_ACTIVE_LOW NA - 9 + 3 1 read-write - MASK_ACK_WITH_ERR_10 + COLORM_ACTIVE_LOW NA - 10 + 4 1 read-write + + + + DPI_LP_CMD_TIM + NA + 0x18 + 0x20 + - MASK_ACK_WITH_ERR_11 + INVACT_LPCMD_TIME NA - 11 - 1 + 0 + 8 read-write - MASK_ACK_WITH_ERR_12 + OUTVACT_LPCMD_TIME NA - 12 - 1 + 16 + 8 read-write + + + + DBI_VCID + NA + 0x1C + 0x20 + - MASK_ACK_WITH_ERR_13 + DBI_VCID NA - 13 - 1 + 0 + 2 read-write + + + + DBI_CFG + NA + 0x20 + 0x20 + - MASK_ACK_WITH_ERR_14 + IN_DBI_CONF NA - 14 - 1 + 0 + 4 read-write - MASK_ACK_WITH_ERR_15 + OUT_DBI_CONF NA - 15 - 1 + 8 + 4 read-write - MASK_DPHY_ERRORS_0 + LUT_SIZE_CONF NA 16 - 1 - read-write - - - MASK_DPHY_ERRORS_1 - NA - 17 - 1 + 2 read-write + + + + DBI_PARTITIONING_EN + NA + 0x24 + 0x20 + - MASK_DPHY_ERRORS_2 + PARTITIONING_EN NA - 18 + 0 1 read-write + + + + DBI_CMDSIZE + NA + 0x28 + 0x20 + - MASK_DPHY_ERRORS_3 + WR_CMD_SIZE NA - 19 - 1 + 0 + 16 read-write - MASK_DPHY_ERRORS_4 + ALLOWED_CMD_SIZE NA - 20 - 1 + 16 + 16 read-write - INT_MSK1 + PCKHDL_CFG NA - 0xC8 + 0x2C 0x20 - MASK_TO_HS_TX + EOTP_TX_EN NA 0 1 read-write - MASK_TO_LP_RX + EOTP_RX_EN NA 1 1 read-write - MASK_ECC_SINGLE_ERR + BTA_EN NA 2 1 read-write - MASK_ECC_MILTI_ERR + ECC_RX_EN NA 3 1 read-write - MASK_CRC_ERR + CRC_RX_EN NA 4 1 read-write - MASK_PKT_SIZE_ERR + EOTP_TX_LP_EN NA 5 1 read-write + + + + GEN_VCID + NA + 0x30 + 0x20 + - MASK_EOPT_ERR - NA - 6 - 1 - read-write - - - MASK_DPI_PLD_WR_ERR + RX NA - 7 - 1 + 0 + 2 read-write - MASK_GEN_CMD_WR_ERR + TEAR_AUTO NA 8 - 1 - read-write - - - MASK_GEN_PLD_WR_ERR - NA - 9 - 1 - read-write - - - MASK_GEN_PLD_SEND_ERR - NA - 10 - 1 - read-write - - - MASK_GEN_PLD_RD_ERR - NA - 11 - 1 - read-write - - - MASK_GEN_PLD_RECEV_ERR - NA - 12 - 1 + 2 read-write - MASK_DPI_BUFF_PLD_UNDER + TX_AUTO NA - 19 - 1 + 16 + 2 read-write - PHY_CAL + MODE_CFG NA - 0xCC + 0x34 0x20 + 0x00000001 - TXSKEWCALHS + CMD_VIDEO_MODE NA 0 1 @@ -30905,3181 +31227,2978 @@ - INT_FORCE0 + VID_MODE_CFG NA - 0xD8 + 0x38 0x20 - FORCE_ACK_WITH_ERR_0 + VID_MODE_TYPE NA 0 - 1 + 2 read-write - FORCE_ACK_WITH_ERR_1 + LP_VSA_EN NA - 1 + 8 1 read-write - FORCE_ACK_WITH_ERR_2 + LP_VBP_EN NA - 2 + 9 1 read-write - FORCE_ACK_WITH_ERR_3 + LP_VFP_EN NA - 3 + 10 1 read-write - FORCE_ACK_WITH_ERR_4 + LP_VACT_EN NA - 4 + 11 1 read-write - FORCE_ACK_WITH_ERR_5 + LP_HBP_EN NA - 5 + 12 1 read-write - FORCE_ACK_WITH_ERR_6 + LP_HFP_EN NA - 6 + 13 1 read-write - FORCE_ACK_WITH_ERR_7 + FRAME_BTA_ACK_EN NA - 7 + 14 1 read-write - FORCE_ACK_WITH_ERR_8 + LP_CMD_EN NA - 8 + 15 1 read-write - FORCE_ACK_WITH_ERR_9 + VPG_EN NA - 9 + 16 1 read-write - FORCE_ACK_WITH_ERR_10 + VPG_MODE NA - 10 + 20 1 read-write - FORCE_ACK_WITH_ERR_11 + VPG_ORIENTATION NA - 11 + 24 1 read-write + + + + VID_PKT_SIZE + NA + 0x3C + 0x20 + - FORCE_ACK_WITH_ERR_12 + VID_PKT_SIZE NA - 12 - 1 + 0 + 14 read-write + + + + VID_NUM_CHUNKS + NA + 0x40 + 0x20 + - FORCE_ACK_WITH_ERR_13 + VID_NUM_CHUNKS NA - 13 - 1 + 0 + 13 read-write + + + + VID_NULL_SIZE + NA + 0x44 + 0x20 + - FORCE_ACK_WITH_ERR_14 + VID_NULL_SIZE NA - 14 - 1 + 0 + 13 read-write + + + + VID_HSA_TIME + NA + 0x48 + 0x20 + - FORCE_ACK_WITH_ERR_15 + VID_HSA_TIME NA - 15 - 1 + 0 + 12 read-write + + + + VID_HBP_TIME + NA + 0x4C + 0x20 + - FORCE_DPHY_ERRORS_0 + VID_HBP_TIME NA - 16 - 1 + 0 + 12 read-write + + + + VID_HLINE_TIME + NA + 0x50 + 0x20 + - FORCE_DPHY_ERRORS_1 + VID_HLINE_TIME NA - 17 - 1 + 0 + 15 read-write + + + + VID_VSA_LINES + NA + 0x54 + 0x20 + - FORCE_DPHY_ERRORS_2 + VSA_LINES NA - 18 - 1 + 0 + 10 read-write + + + + VID_VBP_LINES + NA + 0x58 + 0x20 + - FORCE_DPHY_ERRORS_3 + VBP_LINES NA - 19 - 1 + 0 + 10 read-write + + + + VID_VFP_LINES + NA + 0x5C + 0x20 + - FORCE_DPHY_ERRORS_4 + VFP_LINES NA - 20 - 1 + 0 + 10 read-write - INT_FORCE1 + VID_VACTIVE_LINES NA - 0xDC + 0x60 0x20 - FORCE_TO_HS_TX + V_ACTIVE_LINES NA 0 - 1 + 14 read-write + + + + EDPI_CMD_SIZE + NA + 0x64 + 0x20 + - FORCE_TO_LP_RX + EDPI_ALLOWED_CMD_SIZE NA - 1 - 1 + 0 + 16 read-write + + + + CMD_MODE_CFG + NA + 0x68 + 0x20 + - FORCE_ECC_SINGLE_ERR + TEAR_FX_EN NA - 2 + 0 1 read-write - FORCE_ECC_MILTI_ERR + ACK_RQST_EN NA - 3 + 1 1 read-write - FORCE_CRC_ERR + GEN_SW_0P_TX NA - 4 + 8 1 read-write - FORCE_PKT_SIZE_ERR + GEN_SW_1P_TX NA - 5 + 9 1 read-write - FORCE_EOPT_ERR + GEN_SW_2P_TX NA - 6 + 10 1 read-write - FORCE_DPI_PLD_WR_ERR + GEN_SR_0P_TX NA - 7 + 11 1 read-write - FORCE_GEN_CMD_WR_ERR + GEN_SR_1P_TX NA - 8 + 12 1 read-write - FORCE_GEN_PLD_WR_ERR + GEN_SR_2P_TX NA - 9 + 13 1 read-write - FORCE_GEN_PLD_SEND_ERR + GEN_LW_TX NA - 10 + 14 1 read-write - FORCE_GEN_PLD_RD_ERR + DCS_SW_0P_TX NA - 11 + 16 1 read-write - FORCE_GEN_PLD_RECEV_ERR + DCS_SW_1P_TX NA - 12 + 17 1 read-write - FORCE_DPI_BUFF_PLD_UNDER + DCS_SR_0P_TX NA - 19 + 18 1 read-write - - - - DSC_PARAMETER - NA - 0xF0 - 0x20 - - COMPRESSION_MODE + DCS_LW_TX NA - 0 + 19 1 read-write - COMPRESS_ALGO - NA - 8 - 2 - read-write - - - PPS_SEL + MAX_RD_PKT_SIZE NA - 16 - 2 + 24 + 1 read-write - PHY_TMR_RD_CFG + GEN_HDR NA - 0xF4 + 0x6C 0x20 - MAX_RD_TIME + GEN_DT NA 0 - 15 + 6 read-write - - - - VID_SHADOW_CTRL - NA - 0x100 - 0x20 - - VID_SHADOW_EN + GEN_VC NA - 0 - 1 + 6 + 2 read-write - VID_SHADOW_REQ + GEN_WC_LSBYTE NA 8 - 1 + 8 read-write - VID_SHADOW_PIN_REQ + GEN_WC_MSBYTE NA 16 - 1 + 8 read-write - DPI_VCID_ACT - NA - 0x10C - 0x20 - - - DPI_VCID_ACT - NA - 0 - 2 - read-only - - - - - DPI_COLOR_CODING_ACT + GEN_PLD_DATA NA - 0x110 + 0x70 0x20 - DPI_COLOR_CODING_ACT + GEN_PLD_B1 NA 0 - 4 - read-only + 8 + read-write - LOOSELY18_EN_ACT + GEN_PLD_B2 NA 8 - 1 - read-only + 8 + read-write - - - - DPI_LP_CMD_TIM_ACT - NA - 0x118 - 0x20 - - INVACT_LPCMD_TIME_ACT + GEN_PLD_B3 NA - 0 + 16 8 - read-only + read-write - OUTVACT_LPCMD_TIME_ACT + GEN_PLD_B4 NA - 16 + 24 8 - read-only + read-write - EDPI_TE_HW_CFG + CMD_PKT_STATUS NA - 0x11C + 0x74 0x20 + 0x00050015 - HW_TEAR_EFFECT_ON + GEN_CMD_EMPTY NA 0 1 - read-write + read-only - HW_TEAR_EFFECT_GEN + GEN_CMD_FULL NA 1 1 - read-write - - - HW_SET_SCAN_LINE - NA - 4 - 1 - read-write - - - SCAN_LINE_PARAMETER - NA - 16 - 16 - read-write - - - - - VID_MODE_CFG_ACT - NA - 0x138 - 0x20 - - - VID_MODE_TYPE_ACT - NA - 0 - 2 read-only - LP_VSA_EN_ACT + GEN_PLD_W_EMPTY NA 2 1 read-only - LP_VBP_EN_ACT + GEN_PLD_W_FULL NA 3 1 read-only - LP_VFP_EN_ACT + GEN_PLD_R_EMPTY NA 4 1 read-only - LP_VACT_EN_ACT + GEN_PLD_R_FULL NA 5 1 read-only - LP_HBP_EN_ACT + GEN_RD_CMD_BUSY NA 6 1 read-only - LP_HFP_EN_ACT + GEN_BUFF_CMD_EMPTY NA - 7 + 16 1 read-only - FRAME_BTA_ACK_EN_ACT + GEN_BUFF_CMD_FULL NA - 8 + 17 1 read-only - LP_CMD_EN_ACT + GEN_BUFF_PLD_EMPTY NA - 9 + 18 + 1 + read-only + + + GEN_BUFF_PLD_FULL + NA + 19 1 read-only - VID_PKT_SIZE_ACT + TO_CNT_CFG NA - 0x13C + 0x78 0x20 - VID_PKT_SIZE_ACT + LPRX_TO_CNT NA 0 - 14 - read-only + 16 + read-write + + + HSTX_TO_CNT + NA + 16 + 16 + read-write - VID_NUM_CHUNKS_ACT + HS_RD_TO_CNT NA - 0x140 + 0x7C 0x20 - VID_NUM_CHUNKS_ACT + HS_RD_TO_CNT NA 0 - 13 - read-only + 16 + read-write - VID_NULL_SIZE_ACT + LP_RD_TO_CNT NA - 0x144 + 0x80 0x20 - VID_NULL_SIZE_ACT + LP_RD_TO_CNT NA 0 - 13 - read-only + 16 + read-write - VID_HSA_TIME_ACT + HS_WR_TO_CNT NA - 0x148 + 0x84 0x20 - VID_HSA_TIME_ACT + HS_WR_TO_CNT NA 0 - 12 - read-only + 16 + read-write - VID_HBP_TIME_ACT + LP_WR_TO_CNT NA - 0x14C + 0x88 0x20 - VID_HBP_TIME_ACT + LP_WR_TO_CNT NA 0 - 12 - read-only + 16 + read-write - VID_HLINE_TIME_ACT + BTA_TO_CNT NA - 0x150 + 0x8C 0x20 - VID_HLINE_TIME_ACT + BTA_TO_CNT NA 0 - 15 - read-only + 16 + read-write - VID_VSA_LINES_ACT + SDF_3D NA - 0x154 + 0x90 0x20 - VSA_LINES_ACT + MODE_3D NA 0 - 10 - read-only + 2 + read-write + + + FORMAT_3D + NA + 2 + 2 + read-write + + + SECOND_VSYNC + NA + 4 + 1 + read-write + + + RIGHT_FIRST + NA + 5 + 1 + read-write + + + SEND_3D_CFG + NA + 16 + 1 + read-write - VID_VBP_LINES_ACT + LPCLK_CTRL NA - 0x158 + 0x94 0x20 - VBP_LINES_ACT + PHY_TXREQUESTCLKHS NA 0 - 10 - read-only + 1 + read-write + + + AUTO_CLKLANE_CTRL + NA + 1 + 1 + read-write - VID_VFP_LINES_ACT + PHY_TMR_LPCLK_CFG NA - 0x15C + 0x98 0x20 - VFP_LINES_ACT + PHY_CLKLP2HS_TIME NA 0 10 - read-only + read-write + + + PHY_CLKHS2LP_TIME + NA + 16 + 10 + read-write - VID_VACTIVE_LINES_ACT + PHY_TMR_CFG NA - 0x160 + 0x9C 0x20 - V_ACTIVE_LINES_ACT + PHY_LP2HS_TIME NA 0 - 14 - read-only + 10 + read-write + + + PHY_HS2LP_TIME + NA + 16 + 10 + read-write - VID_PKT_STATUS + PHY_RSTZ NA - 0x168 + 0xA0 0x20 - 0x00010005 - DPI_CMD_W_EMPTY + PHY_SHUTDOWNZ NA 0 1 - read-only + read-write - DPI_CMD_W_FULL + PHY_RSTZ NA 1 1 - read-only + read-write - DPI_PLD_W_EMPTY + PHY_ENABLECLK NA 2 1 - read-only + read-write - DPI_PLD_W_FULL + PHY_FORCEPLL NA 3 1 - read-only + read-write + + + + PHY_IF_CFG + NA + 0xA4 + 0x20 + 0x00000001 + - DPI_BUFF_PLD_EMPTY + N_LANES NA - 16 + 0 + 2 + read-write + + + PHY_STOP_WAIT_TIME + NA + 8 + 8 + read-write + + + + + PHY_ULPS_CTRL + NA + 0xA8 + 0x20 + + + PHY_TXREQULPSCLK + NA + 0 1 - read-only + read-write - DPI_BUFF_PLD_FULL + PHY_TXEXITULPSCLK NA - 17 + 1 1 - read-only + read-write + + + PHY_TXREQULPSLAN + NA + 2 + 1 + read-write + + + PHY_TXEXITULPSLAN + NA + 3 + 1 + read-write - SDF_3D_ACT + PHY_TX_TRIGGERS NA - 0x190 + 0xAC 0x20 - MODE_3D_ACT + PHY_TX_TRIGGERS NA 0 - 2 + 4 + read-write + + + + + PHY_STATUS + NA + 0xB0 + 0x20 + 0x00000140 + + + PHY_LOCK + NA + 0 + 1 read-only - FORMAT_3D_ACT + PHY_DIRECTION + NA + 1 + 1 + read-only + + + PHY_STOPSTATECLKLANE NA 2 - 2 + 1 read-only - SECOND_VSYNC_ACT + PHY_ULPSACTIVENOTCLK + NA + 3 + 1 + read-only + + + PHY_STOPSTATE0LANE NA 4 1 read-only - RIGHT_FIRST_ACT + PHY_ULPSACTIVENOT0LANE NA 5 1 read-only - SEND_3D_CFG_ACT + PHY_RXULPSESC0LANE NA - 16 + 6 1 read-only - - - - - - ECC - ECC (ECC Hardware Accelerator) - ECC - 0x50093000 - - 0x0 - 0x78 - registers - - - ECC - 71 - - - - MULT_INT_RAW - ECC interrupt raw register, valid in level. - 0xC - 0x20 - - CALC_DONE_INT_RAW - The raw interrupt status bit for the ecc_calc_done_int interrupt - 0 + PHY_STOPSTATE1LANE + NA + 7 1 read-only - - - - MULT_INT_ST - ECC interrupt status register. - 0x10 - 0x20 - - CALC_DONE_INT_ST - The masked interrupt status bit for the ecc_calc_done_int interrupt - 0 + PHY_ULPSACTIVENOT1LANE + NA + 8 1 read-only - MULT_INT_ENA - ECC interrupt enable register. - 0x14 + PHY_TST_CTRL0 + NA + 0xB4 0x20 + 0x00000001 - CALC_DONE_INT_ENA - The interrupt enable bit for the ecc_calc_done_int interrupt + PHY_TESTCLR + NA 0 1 read-write + + PHY_TESTCLK + NA + 1 + 1 + read-write + - MULT_INT_CLR - ECC interrupt clear register. - 0x18 + PHY_TST_CTRL1 + NA + 0xB8 0x20 - CALC_DONE_INT_CLR - Set this bit to clear the ecc_calc_done_int interrupt + PHY_TESTDIN + NA 0 + 8 + read-write + + + PHT_TESTDOUT + NA + 8 + 8 + read-only + + + PHY_TESTEN + NA + 16 1 - write-only + read-write - MULT_CONF - ECC configure register - 0x1C + INT_ST0 + NA + 0xBC 0x20 - START - Write 1 to start caculation of ECC Accelerator. This bit will be self-cleared after the caculatrion is done. + ACK_WITH_ERR_0 + NA 0 1 - read-write + read-only - RESET - Write 1 to reset ECC Accelerator. + ACK_WITH_ERR_1 + NA 1 1 - write-only + read-only - KEY_LENGTH - The key length mode bit of ECC Accelerator. 0: P-192. 1: P-256. + ACK_WITH_ERR_2 + NA 2 1 - read-write + read-only - MOD_BASE - The mod base of mod operation, only valid in work_mode 8-11. 0: n(order of curve). 1: p(mod base of curve) + ACK_WITH_ERR_3 + NA 3 1 - read-write + read-only - WORK_MODE - The work mode bits of ECC Accelerator. 0: Point Mult Mode. 1: Reserved. 2: Point verification mode. 3: Point Verif+mult mode. 4: Jacobian Point Mult Mode. 5: Point Add Mode. 6: Jacobian Point Verification Mode. 7: Point Verif + Jacobian Mult Mode. 8: mod addition. 9. mod substraction. 10: mod multiplication. 11: mod division. + ACK_WITH_ERR_4 + NA 4 - 4 - read-write + 1 + read-only - SECURITY_MODE - Reserved - 8 + ACK_WITH_ERR_5 + NA + 5 1 - read-write + read-only - VERIFICATION_RESULT - The verification result bit of ECC Accelerator, only valid when calculation is done. - 29 + ACK_WITH_ERR_6 + NA + 6 1 read-only - CLK_EN - Write 1 to force on register clock gate. - 30 + ACK_WITH_ERR_7 + NA + 7 1 - read-write + read-only - MEM_CLOCK_GATE_FORCE_ON - ECC memory clock gate force on register - 31 + ACK_WITH_ERR_8 + NA + 8 1 - read-write + read-only - - - - MULT_DATE - Version control register - 0xFC - 0x20 - 0x02305040 - - DATE - ECC mult version control register - 0 - 28 - read-write - - - - - 32 - 0x1 - K_MEM[%s] - The memory that stores k. - 0x100 - 0x8 - - - 32 - 0x1 - PX_MEM[%s] - The memory that stores Px. - 0x120 - 0x8 - - - 32 - 0x1 - PY_MEM[%s] - The memory that stores Py. - 0x140 - 0x8 - - - - - ECDSA - ECDSA (Elliptic Curve Digital Signature Algorithm) Accelerator - ECDSA - 0x50096000 - - 0x0 - 0xF8 - registers - - - - CONF - ECDSA configure register - 0x4 - 0x20 - - - WORK_MODE - The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature Generate Mode. 2: Export Public Key Mode. 3: invalid. - 0 - 2 - read-write - - - ECC_CURVE - The ecc curve select bit of ECDSA Accelerator. 0: P-192. 1: P-256. - 2 - 1 - read-write - - - SOFTWARE_SET_K - The source of k select bit. 0: k is automatically generated by hardware. 1: k is written by software. - 3 + ACK_WITH_ERR_9 + NA + 9 1 - read-write + read-only - SOFTWARE_SET_Z - The source of z select bit. 0: z is generated from SHA result. 1: z is written by software. - 4 + ACK_WITH_ERR_10 + NA + 10 1 - read-write + read-only - DETERMINISTIC_K - The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by deterministic derivation algorithm. - 5 + ACK_WITH_ERR_11 + NA + 11 1 - read-write - - - DETERMINISTIC_LOOP - The (loop number - 1) value in the deterministic derivation algorithm to derive k. - 6 - 16 - read-write + read-only - - - - CLK - ECDSA clock gate register - 0x8 - 0x20 - - GATE_FORCE_ON - Write 1 to force on register clock gate. - 0 + ACK_WITH_ERR_12 + NA + 12 1 - read-write + read-only - - - - INT_RAW - ECDSA interrupt raw register, valid in level. - 0xC - 0x20 - - CALC_DONE_INT_RAW - The raw interrupt status bit for the ecdsa_calc_done_int interrupt - 0 + ACK_WITH_ERR_13 + NA + 13 1 read-only - SHA_RELEASE_INT_RAW - The raw interrupt status bit for the ecdsa_sha_release_int interrupt - 1 + ACK_WITH_ERR_14 + NA + 14 1 read-only - - - - INT_ST - ECDSA interrupt status register. - 0x10 - 0x20 - - CALC_DONE_INT_ST - The masked interrupt status bit for the ecdsa_calc_done_int interrupt - 0 + ACK_WITH_ERR_15 + NA + 15 1 read-only - SHA_RELEASE_INT_ST - The masked interrupt status bit for the ecdsa_sha_release_int interrupt - 1 + DPHY_ERRORS_0 + NA + 16 1 read-only - - - - INT_ENA - ECDSA interrupt enable register. - 0x14 - 0x20 - - CALC_DONE_INT_ENA - The interrupt enable bit for the ecdsa_calc_done_int interrupt - 0 + DPHY_ERRORS_1 + NA + 17 1 - read-write + read-only - SHA_RELEASE_INT_ENA - The interrupt enable bit for the ecdsa_sha_release_int interrupt - 1 + DPHY_ERRORS_2 + NA + 18 1 - read-write + read-only - - - - INT_CLR - ECDSA interrupt clear register. - 0x18 - 0x20 - - CALC_DONE_INT_CLR - Set this bit to clear the ecdsa_calc_done_int interrupt - 0 + DPHY_ERRORS_3 + NA + 19 1 - write-only + read-only - SHA_RELEASE_INT_CLR - Set this bit to clear the ecdsa_sha_release_int interrupt - 1 + DPHY_ERRORS_4 + NA + 20 1 - write-only + read-only - START - ECDSA start register - 0x1C + INT_ST1 + NA + 0xC0 0x20 - START - Write 1 to start caculation of ECDSA Accelerator. This bit will be self-cleared after configuration. + TO_HS_TX + NA 0 1 - write-only + read-only - LOAD_DONE - Write 1 to input load done signal of ECDSA Accelerator. This bit will be self-cleared after configuration. + TO_LP_RX + NA 1 1 - write-only + read-only - GET_DONE - Write 1 to input get done signal of ECDSA Accelerator. This bit will be self-cleared after configuration. + ECC_SINGLE_ERR + NA 2 1 - write-only - - - - - STATE - ECDSA status register - 0x20 - 0x20 - - - BUSY - The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY state. - 0 - 2 read-only - - - - RESULT - ECDSA result register - 0x24 - 0x20 - - OPERATION_RESULT - The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is done. - 0 + ECC_MILTI_ERR + NA + 3 1 read-only - K_VALUE_WARNING - The k value warning bit of ECDSA Accelerator, valid when k value is bigger than the curve order, then actually taken k = k mod n. - 1 + CRC_ERR + NA + 4 1 read-only - - - - DATE - Version control register - 0xFC - 0x20 - 0x02304070 - - DATE - ECDSA version control register - 0 - 28 - read-write + PKT_SIZE_ERR + NA + 5 + 1 + read-only - - - - SHA_MODE - ECDSA control SHA register - 0x200 - 0x20 - - SHA_MODE - The work mode bits of SHA Calculator in ECDSA Accelerator. 1: SHA-224. 2: SHA-256. Others: invalid. - 0 - 3 - read-write + EOPT_ERR + NA + 6 + 1 + read-only - - - - SHA_START - ECDSA control SHA register - 0x210 - 0x20 - - SHA_START - Write 1 to start the first caculation of SHA Calculator in ECDSA Accelerator. This bit will be self-cleared after configuration. - 0 + DPI_PLD_WR_ERR + NA + 7 1 - write-only + read-only - - - - SHA_CONTINUE - ECDSA control SHA register - 0x214 - 0x20 - - SHA_CONTINUE - Write 1 to start the latter caculation of SHA Calculator in ECDSA Accelerator. This bit will be self-cleared after configuration. - 0 + GEN_CMD_WR_ERR + NA + 8 1 - write-only + read-only - - - - SHA_BUSY - ECDSA status register - 0x218 - 0x20 - - SHA_BUSY - The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in calculation. 0: SHA is idle. - 0 + GEN_PLD_WR_ERR + NA + 9 1 read-only - - - - 32 - 0x1 - MESSAGE_MEM[%s] - The memory that stores message. - 0x280 - 0x8 - - - 32 - 0x1 - R_MEM[%s] - The memory that stores r. - 0xA00 - 0x8 - - - 32 - 0x1 - S_MEM[%s] - The memory that stores s. - 0xA20 - 0x8 - - - 32 - 0x1 - Z_MEM[%s] - The memory that stores software written z. - 0xA40 - 0x8 - - - 32 - 0x1 - QAX_MEM[%s] - The memory that stores x coordinates of QA or software written k. - 0xA60 - 0x8 - - - 32 - 0x1 - QAY_MEM[%s] - The memory that stores y coordinates of QA. - 0xA80 - 0x8 - - - - - EFUSE - eFuse Controller - EFUSE - 0x5012D000 - - 0x0 - 0x3D8 - registers - - - - PGM_DATA0 - Register 0 that stores data to be programmed. - 0x0 - 0x20 - - PGM_DATA_0 - Configures the 0th 32-bit data to be programmed. - 0 - 32 - read-write + GEN_PLD_SEND_ERR + NA + 10 + 1 + read-only - - - - PGM_DATA1 - Register 1 that stores data to be programmed. - 0x4 - 0x20 - - PGM_DATA_1 - Configures the 1st 32-bit data to be programmed. - 0 - 32 - read-write + GEN_PLD_RD_ERR + NA + 11 + 1 + read-only - - - - PGM_DATA2 - Register 2 that stores data to be programmed. - 0x8 - 0x20 - - PGM_DATA_2 - Configures the 2nd 32-bit data to be programmed. - 0 - 32 - read-write + GEN_PLD_RECEV_ERR + NA + 12 + 1 + read-only - - - - PGM_DATA3 - Register 3 that stores data to be programmed. - 0xC - 0x20 - - PGM_DATA_3 - Configures the 3rd 32-bit data to be programmed. - 0 - 32 - read-write + DPI_BUFF_PLD_UNDER + NA + 19 + 1 + read-only - PGM_DATA4 - Register 4 that stores data to be programmed. - 0x10 + INT_MSK0 + NA + 0xC4 0x20 - PGM_DATA_4 - Configures the 4th 32-bit data to be programmed. + MASK_ACK_WITH_ERR_0 + NA 0 - 32 + 1 read-write - - - - PGM_DATA5 - Register 5 that stores data to be programmed. - 0x14 - 0x20 - - PGM_DATA_5 - Configures the 5th 32-bit data to be programmed. - 0 - 32 + MASK_ACK_WITH_ERR_1 + NA + 1 + 1 read-write - - - - PGM_DATA6 - Register 6 that stores data to be programmed. - 0x18 - 0x20 - - PGM_DATA_6 - Configures the 6th 32-bit data to be programmed. - 0 - 32 + MASK_ACK_WITH_ERR_2 + NA + 2 + 1 read-write - - - - PGM_DATA7 - Register 7 that stores data to be programmed. - 0x1C - 0x20 - - PGM_DATA_7 - Configures the 7th 32-bit data to be programmed. - 0 - 32 + MASK_ACK_WITH_ERR_3 + NA + 3 + 1 read-write - - - - PGM_CHECK_VALUE0 - Register 0 that stores the RS code to be programmed. - 0x20 - 0x20 - - PGM_RS_DATA_0 - Configures the 0th 32-bit RS code to be programmed. - 0 - 32 + MASK_ACK_WITH_ERR_4 + NA + 4 + 1 read-write - - - - PGM_CHECK_VALUE1 - Register 1 that stores the RS code to be programmed. - 0x24 - 0x20 - - PGM_RS_DATA_1 - Configures the 1st 32-bit RS code to be programmed. - 0 - 32 + MASK_ACK_WITH_ERR_5 + NA + 5 + 1 read-write - - - - PGM_CHECK_VALUE2 - Register 2 that stores the RS code to be programmed. - 0x28 - 0x20 - - PGM_RS_DATA_2 - Configures the 2nd 32-bit RS code to be programmed. - 0 - 32 + MASK_ACK_WITH_ERR_6 + NA + 6 + 1 read-write - - - - RD_WR_DIS - BLOCK0 data register 0. - 0x2C - 0x20 - - - WR_DIS - Represents whether programming of individual eFuse memory bit is disabled or enabled. 1: Disabled. 0 Enabled. - 0 - 32 - read-only - - - - - RD_REPEAT_DATA0 - BLOCK0 data register 1. - 0x30 - 0x20 - - - RD_DIS - Represents whether reading of individual eFuse block(block4~block10) is disabled or enabled. 1: disabled. 0: enabled. - 0 - 7 - read-only - - USB_DEVICE_EXCHG_PINS - Enable usb device exchange pins of D+ and D-. + MASK_ACK_WITH_ERR_7 + NA 7 1 - read-only + read-write - USB_OTG11_EXCHG_PINS - Enable usb otg11 exchange pins of D+ and D-. + MASK_ACK_WITH_ERR_8 + NA 8 1 - read-only + read-write - DIS_USB_JTAG - Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled. + MASK_ACK_WITH_ERR_9 + NA 9 1 - read-only + read-write - POWERGLITCH_EN - Represents whether power glitch function is enabled. 1: enabled. 0: disabled. + MASK_ACK_WITH_ERR_10 + NA 10 1 - read-only + read-write - DIS_USB_SERIAL_JTAG - Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled. + MASK_ACK_WITH_ERR_11 + NA 11 1 - read-only + read-write - DIS_FORCE_DOWNLOAD - Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled. 0: enabled. + MASK_ACK_WITH_ERR_12 + NA 12 1 - read-only + read-write - SPI_DOWNLOAD_MSPI_DIS - Set this bit to disable accessing MSPI flash/MSPI ram by SYS AXI matrix during boot_mode_download. + MASK_ACK_WITH_ERR_13 + NA 13 1 - read-only + read-write - DIS_TWAI - Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled. + MASK_ACK_WITH_ERR_14 + NA 14 1 - read-only + read-write - JTAG_SEL_ENABLE - Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. 1: enabled. 0: disabled. + MASK_ACK_WITH_ERR_15 + NA 15 1 - read-only + read-write - SOFT_DIS_JTAG - Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: enabled. + MASK_DPHY_ERRORS_0 + NA 16 - 3 - read-only - - - DIS_PAD_JTAG - Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled. - 19 1 - read-only + read-write - DIS_DOWNLOAD_MANUAL_ENCRYPT - Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled. - 20 + MASK_DPHY_ERRORS_1 + NA + 17 1 - read-only - - - USB_DEVICE_DREFH - USB intphy of usb device signle-end input high threshold, 1.76V to 2V. Step by 80mV - 21 - 2 - read-only + read-write - USB_OTG11_DREFH - USB intphy of usb otg11 signle-end input high threshold, 1.76V to 2V. Step by 80mV - 23 - 2 - read-only + MASK_DPHY_ERRORS_2 + NA + 18 + 1 + read-write - USB_PHY_SEL - TBD - 25 + MASK_DPHY_ERRORS_3 + NA + 19 1 - read-only + read-write - KM_HUK_GEN_STATE_LOW - Set this bit to control validation of HUK generate mode. Odd of 1 is invalid, even of 1 is valid. - 26 - 6 - read-only + MASK_DPHY_ERRORS_4 + NA + 20 + 1 + read-write - RD_REPEAT_DATA1 - BLOCK0 data register 2. - 0x34 + INT_MSK1 + NA + 0xC8 0x20 - KM_HUK_GEN_STATE_HIGH - Set this bit to control validation of HUK generate mode. Odd of 1 is invalid, even of 1 is valid. + MASK_TO_HS_TX + NA 0 - 3 - read-only + 1 + read-write - KM_RND_SWITCH_CYCLE - Set bits to control key manager random number switch cycle. 0: control by register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles. - 3 - 2 - read-only + MASK_TO_LP_RX + NA + 1 + 1 + read-write - KM_DEPLOY_ONLY_ONCE - Set each bit to control whether corresponding key can only be deployed once. 1 is true, 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds. - 5 - 4 - read-only + MASK_ECC_SINGLE_ERR + NA + 2 + 1 + read-write - FORCE_USE_KEY_MANAGER_KEY - Set each bit to control whether corresponding key must come from key manager.. 1 is true, 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds. - 9 - 4 - read-only + MASK_ECC_MILTI_ERR + NA + 3 + 1 + read-write - FORCE_DISABLE_SW_INIT_KEY - Set this bit to disable software written init key, and force use efuse_init_key. - 13 + MASK_CRC_ERR + NA + 4 1 - read-only + read-write - XTS_KEY_LENGTH_256 - Set this bit to configure flash encryption use xts-128 key, else use xts-256 key. - 14 + MASK_PKT_SIZE_ERR + NA + 5 1 - read-only + read-write - WDT_DELAY_SEL - Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected. 0: not selected. - 16 - 2 - read-only + MASK_EOPT_ERR + NA + 6 + 1 + read-write - SPI_BOOT_CRYPT_CNT - Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number of 1: enabled. Even number of 1: disabled. - 18 - 3 - read-only + MASK_DPI_PLD_WR_ERR + NA + 7 + 1 + read-write - SECURE_BOOT_KEY_REVOKE0 - Represents whether revoking first secure boot key is enabled or disabled. 1: enabled. 0: disabled. - 21 + MASK_GEN_CMD_WR_ERR + NA + 8 1 - read-only + read-write - SECURE_BOOT_KEY_REVOKE1 - Represents whether revoking second secure boot key is enabled or disabled. 1: enabled. 0: disabled. - 22 + MASK_GEN_PLD_WR_ERR + NA + 9 1 - read-only + read-write - SECURE_BOOT_KEY_REVOKE2 - Represents whether revoking third secure boot key is enabled or disabled. 1: enabled. 0: disabled. - 23 + MASK_GEN_PLD_SEND_ERR + NA + 10 1 - read-only + read-write - KEY_PURPOSE_0 - Represents the purpose of Key0. - 24 - 4 - read-only + MASK_GEN_PLD_RD_ERR + NA + 11 + 1 + read-write - KEY_PURPOSE_1 - Represents the purpose of Key1. - 28 - 4 - read-only + MASK_GEN_PLD_RECEV_ERR + NA + 12 + 1 + read-write + + + MASK_DPI_BUFF_PLD_UNDER + NA + 19 + 1 + read-write - RD_REPEAT_DATA2 - BLOCK0 data register 3. - 0x38 + PHY_CAL + NA + 0xCC 0x20 - 0x00080000 - KEY_PURPOSE_2 - Represents the purpose of Key2. + TXSKEWCALHS + NA 0 - 4 - read-only + 1 + read-write + + + + INT_FORCE0 + NA + 0xD8 + 0x20 + - KEY_PURPOSE_3 - Represents the purpose of Key3. - 4 - 4 - read-only + FORCE_ACK_WITH_ERR_0 + NA + 0 + 1 + read-write - KEY_PURPOSE_4 - Represents the purpose of Key4. - 8 - 4 - read-only + FORCE_ACK_WITH_ERR_1 + NA + 1 + 1 + read-write - KEY_PURPOSE_5 - Represents the purpose of Key5. - 12 - 4 - read-only + FORCE_ACK_WITH_ERR_2 + NA + 2 + 1 + read-write - SEC_DPA_LEVEL - Represents the spa secure level by configuring the clock random divide mode. - 16 - 2 - read-only + FORCE_ACK_WITH_ERR_3 + NA + 3 + 1 + read-write - ECDSA_ENABLE_SOFT_K - Represents whether hardware random number k is forced used in ESDCA. 1: force used. 0: not force used. - 18 + FORCE_ACK_WITH_ERR_4 + NA + 4 1 - read-only + read-write - CRYPT_DPA_ENABLE - Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled. - 19 + FORCE_ACK_WITH_ERR_5 + NA + 5 1 - read-only + read-write - SECURE_BOOT_EN - Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled. - 20 + FORCE_ACK_WITH_ERR_6 + NA + 6 1 - read-only + read-write - SECURE_BOOT_AGGRESSIVE_REVOKE - Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled. - 21 + FORCE_ACK_WITH_ERR_7 + NA + 7 1 - read-only + read-write - FLASH_TYPE - The type of interfaced flash. 0: four data lines, 1: eight data lines. - 23 + FORCE_ACK_WITH_ERR_8 + NA + 8 1 - read-only + read-write - FLASH_PAGE_SIZE - Set flash page size. - 24 - 2 - read-only + FORCE_ACK_WITH_ERR_9 + NA + 9 + 1 + read-write - FLASH_ECC_EN - Set this bit to enable ecc for flash boot. - 26 + FORCE_ACK_WITH_ERR_10 + NA + 10 1 - read-only + read-write - DIS_USB_OTG_DOWNLOAD_MODE - Set this bit to disable download via USB-OTG. - 27 + FORCE_ACK_WITH_ERR_11 + NA + 11 1 - read-only + read-write - FLASH_TPUW - Represents the flash waiting time after power-up, in unit of ms. When the value less than 15, the waiting time is the programmed value. Otherwise, the waiting time is 2 times the programmed value. - 28 - 4 - read-only + FORCE_ACK_WITH_ERR_12 + NA + 12 + 1 + read-write - - - - RD_REPEAT_DATA3 - BLOCK0 data register 4. - 0x3C - 0x20 - - DIS_DOWNLOAD_MODE - Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled. - 0 + FORCE_ACK_WITH_ERR_13 + NA + 13 1 - read-only + read-write - DIS_DIRECT_BOOT - Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled. - 1 + FORCE_ACK_WITH_ERR_14 + NA + 14 1 - read-only + read-write - DIS_USB_SERIAL_JTAG_ROM_PRINT - Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled. - 2 + FORCE_ACK_WITH_ERR_15 + NA + 15 1 - read-only + read-write - LOCK_KM_KEY - TBD - 3 + FORCE_DPHY_ERRORS_0 + NA + 16 1 - read-only + read-write - DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE - Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: disabled. 0: enabled. - 4 + FORCE_DPHY_ERRORS_1 + NA + 17 1 - read-only + read-write - ENABLE_SECURITY_DOWNLOAD - Represents whether security download is enabled or disabled. 1: enabled. 0: disabled. - 5 + FORCE_DPHY_ERRORS_2 + NA + 18 1 - read-only + read-write - UART_PRINT_CONTROL - Represents the type of UART printing. 00: force enable printing. 01: enable printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset at high level. 11: force disable printing. - 6 - 2 - read-only + FORCE_DPHY_ERRORS_3 + NA + 19 + 1 + read-write - FORCE_SEND_RESUME - Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced. 0:not forced. - 8 + FORCE_DPHY_ERRORS_4 + NA + 20 1 - read-only + read-write + + + + INT_FORCE1 + NA + 0xDC + 0x20 + - SECURE_VERSION - Represents the version used by ESP-IDF anti-rollback feature. - 9 - 16 - read-only + FORCE_TO_HS_TX + NA + 0 + 1 + read-write - SECURE_BOOT_DISABLE_FAST_WAKE - Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled. - 25 + FORCE_TO_LP_RX + NA + 1 1 - read-only + read-write - HYS_EN_PAD - Represents whether the hysteresis function of corresponding PAD is enabled. 1: enabled. 0:disabled. - 26 + FORCE_ECC_SINGLE_ERR + NA + 2 1 - read-only + read-write - DCDC_VSET - Set the dcdc voltage default. - 27 - 5 - read-only + FORCE_ECC_MILTI_ERR + NA + 3 + 1 + read-write - - - - RD_REPEAT_DATA4 - BLOCK0 data register 5. - 0x40 - 0x20 - - _0PXA_TIEH_SEL_0 - TBD - 0 - 2 - read-only + FORCE_CRC_ERR + NA + 4 + 1 + read-write - _0PXA_TIEH_SEL_1 - TBD. - 2 - 2 - read-only + FORCE_PKT_SIZE_ERR + NA + 5 + 1 + read-write - _0PXA_TIEH_SEL_2 - TBD. - 4 - 2 - read-only + FORCE_EOPT_ERR + NA + 6 + 1 + read-write - _0PXA_TIEH_SEL_3 - TBD. - 6 - 2 - read-only + FORCE_DPI_PLD_WR_ERR + NA + 7 + 1 + read-write - KM_DISABLE_DEPLOY_MODE - TBD. + FORCE_GEN_CMD_WR_ERR + NA 8 - 4 - read-only + 1 + read-write - USB_DEVICE_DREFL - Represents the usb device single-end input low threhold, 0.8 V to 1.04 V with step of 80 mV. - 12 - 2 - read-only + FORCE_GEN_PLD_WR_ERR + NA + 9 + 1 + read-write - USB_OTG11_DREFL - Represents the usb otg11 single-end input low threhold, 0.8 V to 1.04 V with step of 80 mV. - 14 - 2 - read-only + FORCE_GEN_PLD_SEND_ERR + NA + 10 + 1 + read-write - HP_PWR_SRC_SEL - HP system power source select. 0:LDO. 1: DCDC. - 18 + FORCE_GEN_PLD_RD_ERR + NA + 11 1 - read-only + read-write - DCDC_VSET_EN - Select dcdc vset use efuse_dcdc_vset. - 19 + FORCE_GEN_PLD_RECEV_ERR + NA + 12 1 - read-only + read-write - DIS_WDT - Set this bit to disable watch dog. - 20 + FORCE_DPI_BUFF_PLD_UNDER + NA + 19 1 - read-only + read-write + + + + DSC_PARAMETER + NA + 0xF0 + 0x20 + - DIS_SWD - Set this bit to disable super-watchdog. - 21 + COMPRESSION_MODE + NA + 0 1 - read-only + read-write + + + COMPRESS_ALGO + NA + 8 + 2 + read-write + + + PPS_SEL + NA + 16 + 2 + read-write - RD_MAC_SYS_0 - BLOCK1 data register $n. - 0x44 + PHY_TMR_RD_CFG + NA + 0xF4 0x20 - MAC_0 - Stores the low 32 bits of MAC address. + MAX_RD_TIME + NA 0 - 32 - read-only + 15 + read-write - RD_MAC_SYS_1 - BLOCK1 data register $n. - 0x48 + VID_SHADOW_CTRL + NA + 0x100 0x20 - MAC_1 - Stores the high 16 bits of MAC address. + VID_SHADOW_EN + NA 0 - 16 - read-only + 1 + read-write - MAC_EXT - Stores the extended bits of MAC address. + VID_SHADOW_REQ + NA + 8 + 1 + read-write + + + VID_SHADOW_PIN_REQ + NA 16 - 16 - read-only + 1 + read-write - RD_MAC_SYS_2 - BLOCK1 data register $n. - 0x4C + DPI_VCID_ACT + NA + 0x10C 0x20 - MAC_RESERVED_1 - Reserved. + DPI_VCID_ACT + NA 0 - 14 - read-only - - - MAC_RESERVED_0 - Reserved. - 14 - 18 + 2 read-only - RD_MAC_SYS_3 - BLOCK1 data register $n. - 0x50 + DPI_COLOR_CODING_ACT + NA + 0x110 0x20 - MAC_RESERVED_2 - Reserved. + DPI_COLOR_CODING_ACT + NA 0 - 18 + 4 read-only - SYS_DATA_PART0_0 - Stores the first 14 bits of the zeroth part of system data. - 18 - 14 + LOOSELY18_EN_ACT + NA + 8 + 1 read-only - RD_MAC_SYS_4 - BLOCK1 data register $n. - 0x54 + DPI_LP_CMD_TIM_ACT + NA + 0x118 0x20 - SYS_DATA_PART0_1 - Stores the first 32 bits of the zeroth part of system data. + INVACT_LPCMD_TIME_ACT + NA 0 - 32 + 8 + read-only + + + OUTVACT_LPCMD_TIME_ACT + NA + 16 + 8 read-only - RD_MAC_SYS_5 - BLOCK1 data register $n. - 0x58 + EDPI_TE_HW_CFG + NA + 0x11C 0x20 - SYS_DATA_PART0_2 - Stores the second 32 bits of the zeroth part of system data. + HW_TEAR_EFFECT_ON + NA 0 - 32 - read-only + 1 + read-write + + + HW_TEAR_EFFECT_GEN + NA + 1 + 1 + read-write + + + HW_SET_SCAN_LINE + NA + 4 + 1 + read-write + + + SCAN_LINE_PARAMETER + NA + 16 + 16 + read-write - RD_SYS_PART1_DATA0 - Register $n of BLOCK2 (system). - 0x5C + VID_MODE_CFG_ACT + NA + 0x138 0x20 - SYS_DATA_PART1_0 - Stores the zeroth 32 bits of the first part of system data. + VID_MODE_TYPE_ACT + NA 0 - 32 + 2 + read-only + + + LP_VSA_EN_ACT + NA + 2 + 1 + read-only + + + LP_VBP_EN_ACT + NA + 3 + 1 + read-only + + + LP_VFP_EN_ACT + NA + 4 + 1 + read-only + + + LP_VACT_EN_ACT + NA + 5 + 1 + read-only + + + LP_HBP_EN_ACT + NA + 6 + 1 + read-only + + + LP_HFP_EN_ACT + NA + 7 + 1 + read-only + + + FRAME_BTA_ACK_EN_ACT + NA + 8 + 1 + read-only + + + LP_CMD_EN_ACT + NA + 9 + 1 read-only - RD_SYS_PART1_DATA1 - Register $n of BLOCK2 (system). - 0x60 + VID_PKT_SIZE_ACT + NA + 0x13C 0x20 - SYS_DATA_PART1_1 - Stores the first 32 bits of the first part of system data. + VID_PKT_SIZE_ACT + NA 0 - 32 + 14 read-only - RD_SYS_PART1_DATA2 - Register $n of BLOCK2 (system). - 0x64 + VID_NUM_CHUNKS_ACT + NA + 0x140 0x20 - SYS_DATA_PART1_2 - Stores the second 32 bits of the first part of system data. + VID_NUM_CHUNKS_ACT + NA 0 - 32 + 13 read-only - RD_SYS_PART1_DATA3 - Register $n of BLOCK2 (system). - 0x68 + VID_NULL_SIZE_ACT + NA + 0x144 0x20 - SYS_DATA_PART1_3 - Stores the third 32 bits of the first part of system data. + VID_NULL_SIZE_ACT + NA 0 - 32 + 13 read-only - RD_SYS_PART1_DATA4 - Register $n of BLOCK2 (system). - 0x6C + VID_HSA_TIME_ACT + NA + 0x148 0x20 - SYS_DATA_PART1_4 - Stores the fourth 32 bits of the first part of system data. + VID_HSA_TIME_ACT + NA 0 - 32 + 12 read-only - RD_SYS_PART1_DATA5 - Register $n of BLOCK2 (system). - 0x70 + VID_HBP_TIME_ACT + NA + 0x14C 0x20 - SYS_DATA_PART1_5 - Stores the fifth 32 bits of the first part of system data. + VID_HBP_TIME_ACT + NA 0 - 32 + 12 read-only - RD_SYS_PART1_DATA6 - Register $n of BLOCK2 (system). - 0x74 + VID_HLINE_TIME_ACT + NA + 0x150 0x20 - SYS_DATA_PART1_6 - Stores the sixth 32 bits of the first part of system data. + VID_HLINE_TIME_ACT + NA 0 - 32 + 15 read-only - RD_SYS_PART1_DATA7 - Register $n of BLOCK2 (system). - 0x78 + VID_VSA_LINES_ACT + NA + 0x154 0x20 - SYS_DATA_PART1_7 - Stores the seventh 32 bits of the first part of system data. + VSA_LINES_ACT + NA 0 - 32 + 10 read-only - RD_USR_DATA0 - Register $n of BLOCK3 (user). - 0x7C + VID_VBP_LINES_ACT + NA + 0x158 0x20 - USR_DATA0 - Stores the zeroth 32 bits of BLOCK3 (user). + VBP_LINES_ACT + NA 0 - 32 + 10 read-only - RD_USR_DATA1 - Register $n of BLOCK3 (user). - 0x80 + VID_VFP_LINES_ACT + NA + 0x15C 0x20 - USR_DATA1 - Stores the first 32 bits of BLOCK3 (user). + VFP_LINES_ACT + NA 0 - 32 + 10 read-only - RD_USR_DATA2 - Register $n of BLOCK3 (user). - 0x84 + VID_VACTIVE_LINES_ACT + NA + 0x160 0x20 - USR_DATA2 - Stores the second 32 bits of BLOCK3 (user). + V_ACTIVE_LINES_ACT + NA 0 - 32 + 14 read-only - RD_USR_DATA3 - Register $n of BLOCK3 (user). - 0x88 + VID_PKT_STATUS + NA + 0x168 0x20 + 0x00010005 - USR_DATA3 - Stores the third 32 bits of BLOCK3 (user). + DPI_CMD_W_EMPTY + NA 0 - 32 + 1 + read-only + + + DPI_CMD_W_FULL + NA + 1 + 1 + read-only + + + DPI_PLD_W_EMPTY + NA + 2 + 1 + read-only + + + DPI_PLD_W_FULL + NA + 3 + 1 + read-only + + + DPI_BUFF_PLD_EMPTY + NA + 16 + 1 + read-only + + + DPI_BUFF_PLD_FULL + NA + 17 + 1 read-only - RD_USR_DATA4 - Register $n of BLOCK3 (user). - 0x8C + SDF_3D_ACT + NA + 0x190 0x20 - USR_DATA4 - Stores the fourth 32 bits of BLOCK3 (user). + MODE_3D_ACT + NA 0 - 32 + 2 + read-only + + + FORMAT_3D_ACT + NA + 2 + 2 + read-only + + + SECOND_VSYNC_ACT + NA + 4 + 1 + read-only + + + RIGHT_FIRST_ACT + NA + 5 + 1 + read-only + + + SEND_3D_CFG_ACT + NA + 16 + 1 read-only + + + + ECC + ECC (ECC Hardware Accelerator) + ECC + 0x50093000 + + 0x0 + 0x78 + registers + + + ECC + 71 + + - RD_USR_DATA5 - Register $n of BLOCK3 (user). - 0x90 + MULT_INT_RAW + ECC interrupt raw register, valid in level. + 0xC 0x20 - USR_DATA5 - Stores the fifth 32 bits of BLOCK3 (user). + CALC_DONE_INT_RAW + The raw interrupt status bit for the ecc_calc_done_int interrupt 0 - 32 + 1 read-only - RD_USR_DATA6 - Register $n of BLOCK3 (user). - 0x94 + MULT_INT_ST + ECC interrupt status register. + 0x10 0x20 - USR_DATA6 - Stores the sixth 32 bits of BLOCK3 (user). + CALC_DONE_INT_ST + The masked interrupt status bit for the ecc_calc_done_int interrupt 0 - 32 + 1 read-only - RD_USR_DATA7 - Register $n of BLOCK3 (user). - 0x98 + MULT_INT_ENA + ECC interrupt enable register. + 0x14 0x20 - USR_DATA7 - Stores the seventh 32 bits of BLOCK3 (user). + CALC_DONE_INT_ENA + The interrupt enable bit for the ecc_calc_done_int interrupt 0 - 32 - read-only + 1 + read-write - RD_KEY0_DATA0 - Register $n of BLOCK4 (KEY0). - 0x9C + MULT_INT_CLR + ECC interrupt clear register. + 0x18 0x20 - KEY0_DATA0 - Stores the zeroth 32 bits of KEY0. + CALC_DONE_INT_CLR + Set this bit to clear the ecc_calc_done_int interrupt 0 - 32 - read-only + 1 + write-only - RD_KEY0_DATA1 - Register $n of BLOCK4 (KEY0). - 0xA0 + MULT_CONF + ECC configure register + 0x1C 0x20 - KEY0_DATA1 - Stores the first 32 bits of KEY0. + START + Write 1 to start caculation of ECC Accelerator. This bit will be self-cleared after the caculatrion is done. 0 - 32 + 1 + read-write + + + RESET + Write 1 to reset ECC Accelerator. + 1 + 1 + write-only + + + KEY_LENGTH + The key length mode bit of ECC Accelerator. 0: P-192. 1: P-256. + 2 + 1 + read-write + + + MOD_BASE + The mod base of mod operation, only valid in work_mode 8-11. 0: n(order of curve). 1: p(mod base of curve) + 3 + 1 + read-write + + + WORK_MODE + The work mode bits of ECC Accelerator. 0: Point Mult Mode. 1: Reserved. 2: Point verification mode. 3: Point Verif+mult mode. 4: Jacobian Point Mult Mode. 5: Point Add Mode. 6: Jacobian Point Verification Mode. 7: Point Verif + Jacobian Mult Mode. 8: mod addition. 9. mod substraction. 10: mod multiplication. 11: mod division. + 4 + 4 + read-write + + + SECURITY_MODE + Reserved + 8 + 1 + read-write + + + VERIFICATION_RESULT + The verification result bit of ECC Accelerator, only valid when calculation is done. + 29 + 1 read-only + + CLK_EN + Write 1 to force on register clock gate. + 30 + 1 + read-write + + + MEM_CLOCK_GATE_FORCE_ON + ECC memory clock gate force on register + 31 + 1 + read-write + - RD_KEY0_DATA2 - Register $n of BLOCK4 (KEY0). - 0xA4 + MULT_DATE + Version control register + 0xFC 0x20 + 0x02305040 - KEY0_DATA2 - Stores the second 32 bits of KEY0. + DATE + ECC mult version control register 0 - 32 - read-only + 28 + read-write - RD_KEY0_DATA3 - Register $n of BLOCK4 (KEY0). - 0xA8 + 8 + 0x4 + K_MEM[%s] + The memory that stores k. + 0x100 + 0x20 + + + 8 + 0x4 + PX_MEM[%s] + The memory that stores Px. + 0x120 + 0x20 + + + 8 + 0x4 + PY_MEM[%s] + The memory that stores Py. + 0x140 + 0x20 + + + + + ECDSA + ECDSA (Elliptic Curve Digital Signature Algorithm) Accelerator + ECDSA + 0x50096000 + + 0x0 + 0xF8 + registers + + + + CONF + ECDSA configure register + 0x4 0x20 - KEY0_DATA3 - Stores the third 32 bits of KEY0. + WORK_MODE + The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature Generate Mode. 2: Export Public Key Mode. 3: invalid. 0 - 32 - read-only + 2 + read-write + + + ECC_CURVE + The ecc curve select bit of ECDSA Accelerator. 0: P-192. 1: P-256. + 2 + 1 + read-write + + + SOFTWARE_SET_K + The source of k select bit. 0: k is automatically generated by hardware. 1: k is written by software. + 3 + 1 + read-write + + + SOFTWARE_SET_Z + The source of z select bit. 0: z is generated from SHA result. 1: z is written by software. + 4 + 1 + read-write + + + DETERMINISTIC_K + The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by deterministic derivation algorithm. + 5 + 1 + read-write + + + DETERMINISTIC_LOOP + The (loop number - 1) value in the deterministic derivation algorithm to derive k. + 6 + 16 + read-write - RD_KEY0_DATA4 - Register $n of BLOCK4 (KEY0). - 0xAC + CLK + ECDSA clock gate register + 0x8 0x20 - KEY0_DATA4 - Stores the fourth 32 bits of KEY0. + GATE_FORCE_ON + Write 1 to force on register clock gate. 0 - 32 - read-only + 1 + read-write - RD_KEY0_DATA5 - Register $n of BLOCK4 (KEY0). - 0xB0 + INT_RAW + ECDSA interrupt raw register, valid in level. + 0xC 0x20 - KEY0_DATA5 - Stores the fifth 32 bits of KEY0. + CALC_DONE_INT_RAW + The raw interrupt status bit for the ecdsa_calc_done_int interrupt 0 - 32 + 1 + read-only + + + SHA_RELEASE_INT_RAW + The raw interrupt status bit for the ecdsa_sha_release_int interrupt + 1 + 1 read-only - RD_KEY0_DATA6 - Register $n of BLOCK4 (KEY0). - 0xB4 + INT_ST + ECDSA interrupt status register. + 0x10 0x20 - KEY0_DATA6 - Stores the sixth 32 bits of KEY0. + CALC_DONE_INT_ST + The masked interrupt status bit for the ecdsa_calc_done_int interrupt 0 - 32 + 1 + read-only + + + SHA_RELEASE_INT_ST + The masked interrupt status bit for the ecdsa_sha_release_int interrupt + 1 + 1 read-only - RD_KEY0_DATA7 - Register $n of BLOCK4 (KEY0). - 0xB8 + INT_ENA + ECDSA interrupt enable register. + 0x14 0x20 - KEY0_DATA7 - Stores the seventh 32 bits of KEY0. + CALC_DONE_INT_ENA + The interrupt enable bit for the ecdsa_calc_done_int interrupt 0 - 32 - read-only + 1 + read-write + + + SHA_RELEASE_INT_ENA + The interrupt enable bit for the ecdsa_sha_release_int interrupt + 1 + 1 + read-write - RD_KEY1_DATA0 - Register $n of BLOCK5 (KEY1). - 0xBC + INT_CLR + ECDSA interrupt clear register. + 0x18 0x20 - KEY1_DATA0 - Stores the zeroth 32 bits of KEY1. + CALC_DONE_INT_CLR + Set this bit to clear the ecdsa_calc_done_int interrupt 0 - 32 - read-only + 1 + write-only + + + SHA_RELEASE_INT_CLR + Set this bit to clear the ecdsa_sha_release_int interrupt + 1 + 1 + write-only - RD_KEY1_DATA1 - Register $n of BLOCK5 (KEY1). - 0xC0 + START + ECDSA start register + 0x1C 0x20 - KEY1_DATA1 - Stores the first 32 bits of KEY1. + START + Write 1 to start caculation of ECDSA Accelerator. This bit will be self-cleared after configuration. 0 - 32 - read-only + 1 + write-only + + + LOAD_DONE + Write 1 to input load done signal of ECDSA Accelerator. This bit will be self-cleared after configuration. + 1 + 1 + write-only + + + GET_DONE + Write 1 to input get done signal of ECDSA Accelerator. This bit will be self-cleared after configuration. + 2 + 1 + write-only - RD_KEY1_DATA2 - Register $n of BLOCK5 (KEY1). - 0xC4 + STATE + ECDSA status register + 0x20 0x20 - KEY1_DATA2 - Stores the second 32 bits of KEY1. + BUSY + The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY state. 0 - 32 + 2 read-only - RD_KEY1_DATA3 - Register $n of BLOCK5 (KEY1). - 0xC8 + RESULT + ECDSA result register + 0x24 0x20 - KEY1_DATA3 - Stores the third 32 bits of KEY1. + OPERATION_RESULT + The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is done. 0 - 32 + 1 + read-only + + + K_VALUE_WARNING + The k value warning bit of ECDSA Accelerator, valid when k value is bigger than the curve order, then actually taken k = k mod n. + 1 + 1 read-only - RD_KEY1_DATA4 - Register $n of BLOCK5 (KEY1). - 0xCC + DATE + Version control register + 0xFC 0x20 + 0x02304070 - KEY1_DATA4 - Stores the fourth 32 bits of KEY1. + DATE + ECDSA version control register 0 - 32 - read-only + 28 + read-write - RD_KEY1_DATA5 - Register $n of BLOCK5 (KEY1). - 0xD0 + SHA_MODE + ECDSA control SHA register + 0x200 0x20 - KEY1_DATA5 - Stores the fifth 32 bits of KEY1. + SHA_MODE + The work mode bits of SHA Calculator in ECDSA Accelerator. 1: SHA-224. 2: SHA-256. Others: invalid. 0 - 32 - read-only + 3 + read-write - RD_KEY1_DATA6 - Register $n of BLOCK5 (KEY1). - 0xD4 + SHA_START + ECDSA control SHA register + 0x210 0x20 - KEY1_DATA6 - Stores the sixth 32 bits of KEY1. + SHA_START + Write 1 to start the first caculation of SHA Calculator in ECDSA Accelerator. This bit will be self-cleared after configuration. 0 - 32 - read-only - - - - - RD_KEY1_DATA7 - Register $n of BLOCK5 (KEY1). - 0xD8 - 0x20 - - - KEY1_DATA7 - Stores the seventh 32 bits of KEY1. - 0 - 32 - read-only - - - - - RD_KEY2_DATA0 - Register $n of BLOCK6 (KEY2). - 0xDC - 0x20 - - - KEY2_DATA0 - Stores the zeroth 32 bits of KEY2. - 0 - 32 - read-only - - - - - RD_KEY2_DATA1 - Register $n of BLOCK6 (KEY2). - 0xE0 - 0x20 - - - KEY2_DATA1 - Stores the first 32 bits of KEY2. - 0 - 32 - read-only - - - - - RD_KEY2_DATA2 - Register $n of BLOCK6 (KEY2). - 0xE4 - 0x20 - - - KEY2_DATA2 - Stores the second 32 bits of KEY2. - 0 - 32 - read-only - - - - - RD_KEY2_DATA3 - Register $n of BLOCK6 (KEY2). - 0xE8 - 0x20 - - - KEY2_DATA3 - Stores the third 32 bits of KEY2. - 0 - 32 - read-only - - - - - RD_KEY2_DATA4 - Register $n of BLOCK6 (KEY2). - 0xEC - 0x20 - - - KEY2_DATA4 - Stores the fourth 32 bits of KEY2. - 0 - 32 - read-only - - - - - RD_KEY2_DATA5 - Register $n of BLOCK6 (KEY2). - 0xF0 - 0x20 - - - KEY2_DATA5 - Stores the fifth 32 bits of KEY2. - 0 - 32 - read-only - - - - - RD_KEY2_DATA6 - Register $n of BLOCK6 (KEY2). - 0xF4 - 0x20 - - - KEY2_DATA6 - Stores the sixth 32 bits of KEY2. - 0 - 32 - read-only - - - - - RD_KEY2_DATA7 - Register $n of BLOCK6 (KEY2). - 0xF8 - 0x20 - - - KEY2_DATA7 - Stores the seventh 32 bits of KEY2. - 0 - 32 - read-only - - - - - RD_KEY3_DATA0 - Register $n of BLOCK7 (KEY3). - 0xFC - 0x20 - - - KEY3_DATA0 - Stores the zeroth 32 bits of KEY3. - 0 - 32 - read-only - - - - - RD_KEY3_DATA1 - Register $n of BLOCK7 (KEY3). - 0x100 - 0x20 - - - KEY3_DATA1 - Stores the first 32 bits of KEY3. - 0 - 32 - read-only - - - - - RD_KEY3_DATA2 - Register $n of BLOCK7 (KEY3). - 0x104 - 0x20 - - - KEY3_DATA2 - Stores the second 32 bits of KEY3. - 0 - 32 - read-only - - - - - RD_KEY3_DATA3 - Register $n of BLOCK7 (KEY3). - 0x108 - 0x20 - - - KEY3_DATA3 - Stores the third 32 bits of KEY3. - 0 - 32 - read-only - - - - - RD_KEY3_DATA4 - Register $n of BLOCK7 (KEY3). - 0x10C - 0x20 - - - KEY3_DATA4 - Stores the fourth 32 bits of KEY3. - 0 - 32 - read-only - - - - - RD_KEY3_DATA5 - Register $n of BLOCK7 (KEY3). - 0x110 - 0x20 - - - KEY3_DATA5 - Stores the fifth 32 bits of KEY3. - 0 - 32 - read-only - - - - - RD_KEY3_DATA6 - Register $n of BLOCK7 (KEY3). - 0x114 - 0x20 - - - KEY3_DATA6 - Stores the sixth 32 bits of KEY3. - 0 - 32 - read-only - - - - - RD_KEY3_DATA7 - Register $n of BLOCK7 (KEY3). - 0x118 - 0x20 - - - KEY3_DATA7 - Stores the seventh 32 bits of KEY3. - 0 - 32 - read-only - - - - - RD_KEY4_DATA0 - Register $n of BLOCK8 (KEY4). - 0x11C - 0x20 - - - KEY4_DATA0 - Stores the zeroth 32 bits of KEY4. - 0 - 32 - read-only - - - - - RD_KEY4_DATA1 - Register $n of BLOCK8 (KEY4). - 0x120 - 0x20 - - - KEY4_DATA1 - Stores the first 32 bits of KEY4. - 0 - 32 - read-only - - - - - RD_KEY4_DATA2 - Register $n of BLOCK8 (KEY4). - 0x124 - 0x20 - - - KEY4_DATA2 - Stores the second 32 bits of KEY4. - 0 - 32 - read-only - - - - - RD_KEY4_DATA3 - Register $n of BLOCK8 (KEY4). - 0x128 - 0x20 - - - KEY4_DATA3 - Stores the third 32 bits of KEY4. - 0 - 32 - read-only + 1 + write-only - RD_KEY4_DATA4 - Register $n of BLOCK8 (KEY4). - 0x12C + SHA_CONTINUE + ECDSA control SHA register + 0x214 0x20 - KEY4_DATA4 - Stores the fourth 32 bits of KEY4. + SHA_CONTINUE + Write 1 to start the latter caculation of SHA Calculator in ECDSA Accelerator. This bit will be self-cleared after configuration. 0 - 32 - read-only + 1 + write-only - RD_KEY4_DATA5 - Register $n of BLOCK8 (KEY4). - 0x130 + SHA_BUSY + ECDSA status register + 0x218 0x20 - KEY4_DATA5 - Stores the fifth 32 bits of KEY4. + SHA_BUSY + The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in calculation. 0: SHA is idle. 0 - 32 + 1 read-only - RD_KEY4_DATA6 - Register $n of BLOCK8 (KEY4). - 0x134 + 8 + 0x4 + MESSAGE_MEM[%s] + The memory that stores message. + 0x280 0x20 - - - KEY4_DATA6 - Stores the sixth 32 bits of KEY4. - 0 - 32 - read-only - - - RD_KEY4_DATA7 - Register $n of BLOCK8 (KEY4). - 0x138 + 8 + 0x4 + R_MEM[%s] + The memory that stores r. + 0xA00 0x20 - - - KEY4_DATA7 - Stores the seventh 32 bits of KEY4. - 0 - 32 - read-only - - - RD_KEY5_DATA0 - Register $n of BLOCK9 (KEY5). - 0x13C + 8 + 0x4 + S_MEM[%s] + The memory that stores s. + 0xA20 0x20 - - - KEY5_DATA0 - Stores the zeroth 32 bits of KEY5. - 0 - 32 - read-only - - - RD_KEY5_DATA1 - Register $n of BLOCK9 (KEY5). - 0x140 + 8 + 0x4 + Z_MEM[%s] + The memory that stores software written z. + 0xA40 0x20 - - - KEY5_DATA1 - Stores the first 32 bits of KEY5. - 0 - 32 - read-only - - - RD_KEY5_DATA2 - Register $n of BLOCK9 (KEY5). - 0x144 + 8 + 0x4 + QAX_MEM[%s] + The memory that stores x coordinates of QA or software written k. + 0xA60 0x20 - - - KEY5_DATA2 - Stores the second 32 bits of KEY5. - 0 - 32 - read-only - - - RD_KEY5_DATA3 - Register $n of BLOCK9 (KEY5). - 0x148 + 8 + 0x4 + QAY_MEM[%s] + The memory that stores y coordinates of QA. + 0xA80 0x20 - - - KEY5_DATA3 - Stores the third 32 bits of KEY5. - 0 - 32 - read-only - - + + + + EFUSE + eFuse Controller + EFUSE + 0x5012D000 + + 0x0 + 0x3D8 + registers + + - RD_KEY5_DATA4 - Register $n of BLOCK9 (KEY5). - 0x14C + PGM_DATA0 + Register 0 that stores data to be programmed. + 0x0 0x20 - KEY5_DATA4 - Stores the fourth 32 bits of KEY5. + PGM_DATA_0 + Configures the 0th 32-bit data to be programmed. 0 32 - read-only + read-write - RD_KEY5_DATA5 - Register $n of BLOCK9 (KEY5). - 0x150 + PGM_DATA1 + Register 1 that stores data to be programmed. + 0x4 0x20 - KEY5_DATA5 - Stores the fifth 32 bits of KEY5. + PGM_DATA_1 + Configures the 1st 32-bit data to be programmed. 0 32 - read-only + read-write - RD_KEY5_DATA6 - Register $n of BLOCK9 (KEY5). - 0x154 + PGM_DATA2 + Register 2 that stores data to be programmed. + 0x8 0x20 - KEY5_DATA6 - Stores the sixth 32 bits of KEY5. + PGM_DATA_2 + Configures the 2nd 32-bit data to be programmed. 0 32 - read-only + read-write - RD_KEY5_DATA7 - Register $n of BLOCK9 (KEY5). - 0x158 + PGM_DATA3 + Register 3 that stores data to be programmed. + 0xC 0x20 - KEY5_DATA7 - Stores the seventh 32 bits of KEY5. + PGM_DATA_3 + Configures the 3rd 32-bit data to be programmed. 0 32 - read-only + read-write - RD_SYS_PART2_DATA0 - Register $n of BLOCK10 (system). - 0x15C + PGM_DATA4 + Register 4 that stores data to be programmed. + 0x10 0x20 - SYS_DATA_PART2_0 - Stores the 0th 32 bits of the 2nd part of system data. + PGM_DATA_4 + Configures the 4th 32-bit data to be programmed. 0 32 - read-only + read-write - RD_SYS_PART2_DATA1 - Register $n of BLOCK9 (KEY5). - 0x160 + PGM_DATA5 + Register 5 that stores data to be programmed. + 0x14 0x20 - SYS_DATA_PART2_1 - Stores the 0th 32 bits of the 2nd part of system data. + PGM_DATA_5 + Configures the 5th 32-bit data to be programmed. 0 32 - read-only + read-write - RD_SYS_PART2_DATA2 - Register $n of BLOCK10 (system). - 0x164 + PGM_DATA6 + Register 6 that stores data to be programmed. + 0x18 0x20 - SYS_DATA_PART2_2 - Stores the 0th 32 bits of the 2nd part of system data. + PGM_DATA_6 + Configures the 6th 32-bit data to be programmed. 0 32 - read-only + read-write - RD_SYS_PART2_DATA3 - Register $n of BLOCK10 (system). - 0x168 + PGM_DATA7 + Register 7 that stores data to be programmed. + 0x1C 0x20 - SYS_DATA_PART2_3 - Stores the 0th 32 bits of the 2nd part of system data. + PGM_DATA_7 + Configures the 7th 32-bit data to be programmed. 0 32 - read-only + read-write - RD_SYS_PART2_DATA4 - Register $n of BLOCK10 (system). - 0x16C + PGM_CHECK_VALUE0 + Register 0 that stores the RS code to be programmed. + 0x20 0x20 - SYS_DATA_PART2_4 - Stores the 0th 32 bits of the 2nd part of system data. + PGM_RS_DATA_0 + Configures the 0th 32-bit RS code to be programmed. 0 32 - read-only + read-write - RD_SYS_PART2_DATA5 - Register $n of BLOCK10 (system). - 0x170 + PGM_CHECK_VALUE1 + Register 1 that stores the RS code to be programmed. + 0x24 0x20 - SYS_DATA_PART2_5 - Stores the 0th 32 bits of the 2nd part of system data. + PGM_RS_DATA_1 + Configures the 1st 32-bit RS code to be programmed. 0 32 - read-only + read-write - RD_SYS_PART2_DATA6 - Register $n of BLOCK10 (system). - 0x174 + PGM_CHECK_VALUE2 + Register 2 that stores the RS code to be programmed. + 0x28 0x20 - SYS_DATA_PART2_6 - Stores the 0th 32 bits of the 2nd part of system data. + PGM_RS_DATA_2 + Configures the 2nd 32-bit RS code to be programmed. 0 32 - read-only + read-write - RD_SYS_PART2_DATA7 - Register $n of BLOCK10 (system). - 0x178 + RD_WR_DIS + BLOCK0 data register 0. + 0x2C 0x20 - SYS_DATA_PART2_7 - Stores the 0th 32 bits of the 2nd part of system data. + WR_DIS + Represents whether programming of individual eFuse memory bit is disabled or enabled. 1: Disabled. 0 Enabled. 0 32 read-only @@ -34087,126 +34206,126 @@ - RD_REPEAT_ERR0 - Programming error record register 0 of BLOCK0. - 0x17C + RD_REPEAT_DATA0 + BLOCK0 data register 1. + 0x30 0x20 - RD_DIS_ERR - Indicates a programming error of RD_DIS. + RD_DIS + Represents whether reading of individual eFuse block(block4~block10) is disabled or enabled. 1: disabled. 0: enabled. 0 7 read-only - DIS_USB_DEVICE_EXCHG_PINS_ERR - Indicates a programming error of DIS_USB_DEVICE_EXCHG_PINS. + USB_DEVICE_EXCHG_PINS + Enable usb device exchange pins of D+ and D-. 7 1 read-only - DIS_USB_OTG11_EXCHG_PINS_ERR - Indicates a programming error of DIS_USB_OTG11_EXCHG_PINS. + USB_OTG11_EXCHG_PINS + Enable usb otg11 exchange pins of D+ and D-. 8 1 read-only - DIS_USB_JTAG_ERR - Indicates a programming error of DIS_USB_JTAG. + DIS_USB_JTAG + Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled. 9 1 read-only - POWERGLITCH_EN_ERR - Indicates a programming error of POWERGLITCH_EN. + POWERGLITCH_EN + Represents whether power glitch function is enabled. 1: enabled. 0: disabled. 10 1 read-only - DIS_USB_SERIAL_JTAG_ERR - Indicates a programming error of DIS_USB_SERIAL_JTAG. + DIS_USB_SERIAL_JTAG + Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled. 11 1 read-only - DIS_FORCE_DOWNLOAD_ERR - Indicates a programming error of DIS_FORCE_DOWNLOAD. + DIS_FORCE_DOWNLOAD + Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled. 0: enabled. 12 1 read-only - SPI_DOWNLOAD_MSPI_DIS_ERR - Indicates a programming error of SPI_DOWNLOAD_MSPI_DIS. + SPI_DOWNLOAD_MSPI_DIS + Set this bit to disable accessing MSPI flash/MSPI ram by SYS AXI matrix during boot_mode_download. 13 1 read-only - DIS_TWAI_ERR - Indicates a programming error of DIS_TWAI. + DIS_TWAI + Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled. 14 1 read-only - JTAG_SEL_ENABLE_ERR - Indicates a programming error of JTAG_SEL_ENABLE. + JTAG_SEL_ENABLE + Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. 1: enabled. 0: disabled. 15 1 read-only - SOFT_DIS_JTAG_ERR - Indicates a programming error of SOFT_DIS_JTAG. + SOFT_DIS_JTAG + Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: enabled. 16 3 read-only - DIS_PAD_JTAG_ERR - Indicates a programming error of DIS_PAD_JTAG. + DIS_PAD_JTAG + Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled. 19 1 read-only - DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR - Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT. + DIS_DOWNLOAD_MANUAL_ENCRYPT + Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled. 20 1 read-only - USB_DEVICE_DREFH_ERR - Indicates a programming error of USB_DEVICE_DREFH. + USB_DEVICE_DREFH + USB intphy of usb device signle-end input high threshold, 1.76V to 2V. Step by 80mV 21 2 read-only - USB_OTG11_DREFH_ERR - Indicates a programming error of USB_OTG11_DREFH. + USB_OTG11_DREFH + USB intphy of usb otg11 signle-end input high threshold, 1.76V to 2V. Step by 80mV 23 2 read-only - USB_PHY_SEL_ERR - Indicates a programming error of USB_PHY_SEL. + USB_PHY_SEL + TBD 25 1 read-only - HUK_GEN_STATE_LOW_ERR - Indicates a programming error of HUK_GEN_STATE_LOW. + KM_HUK_GEN_STATE_LOW + Set this bit to control validation of HUK generate mode. Odd of 1 is invalid, even of 1 is valid. 26 6 read-only @@ -34214,98 +34333,98 @@ - RD_REPEAT_ERR1 - Programming error record register 1 of BLOCK0. - 0x180 + RD_REPEAT_DATA1 + BLOCK0 data register 2. + 0x34 0x20 - KM_HUK_GEN_STATE_HIGH_ERR - Indicates a programming error of HUK_GEN_STATE_HIGH. + KM_HUK_GEN_STATE_HIGH + Set this bit to control validation of HUK generate mode. Odd of 1 is invalid, even of 1 is valid. 0 3 read-only - KM_RND_SWITCH_CYCLE_ERR - Indicates a programming error of KM_RND_SWITCH_CYCLE. + KM_RND_SWITCH_CYCLE + Set bits to control key manager random number switch cycle. 0: control by register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles. 3 2 read-only - KM_DEPLOY_ONLY_ONCE_ERR - Indicates a programming error of KM_DEPLOY_ONLY_ONCE. + KM_DEPLOY_ONLY_ONCE + Set each bit to control whether corresponding key can only be deployed once. 1 is true, 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds. 5 4 read-only - FORCE_USE_KEY_MANAGER_KEY_ERR - Indicates a programming error of FORCE_USE_KEY_MANAGER_KEY. + FORCE_USE_KEY_MANAGER_KEY + Set each bit to control whether corresponding key must come from key manager.. 1 is true, 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds. 9 4 read-only - FORCE_DISABLE_SW_INIT_KEY_ERR - Indicates a programming error of FORCE_DISABLE_SW_INIT_KEY. + FORCE_DISABLE_SW_INIT_KEY + Set this bit to disable software written init key, and force use efuse_init_key. 13 1 read-only - XTS_KEY_LENGTH_256_ERR - Indicates a programming error of XTS_KEY_LENGTH_256. + XTS_KEY_LENGTH_256 + Set this bit to configure flash encryption use xts-128 key, else use xts-256 key. 14 1 read-only - WDT_DELAY_SEL_ERR - Indicates a programming error of WDT_DELAY_SEL. + WDT_DELAY_SEL + Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected. 0: not selected. 16 2 read-only - SPI_BOOT_CRYPT_CNT_ERR - Indicates a programming error of SPI_BOOT_CRYPT_CNT. + SPI_BOOT_CRYPT_CNT + Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number of 1: enabled. Even number of 1: disabled. 18 3 read-only - SECURE_BOOT_KEY_REVOKE0_ERR - Indicates a programming error of SECURE_BOOT_KEY_REVOKE0. + SECURE_BOOT_KEY_REVOKE0 + Represents whether revoking first secure boot key is enabled or disabled. 1: enabled. 0: disabled. 21 1 read-only - SECURE_BOOT_KEY_REVOKE1_ERR - Indicates a programming error of SECURE_BOOT_KEY_REVOKE1. + SECURE_BOOT_KEY_REVOKE1 + Represents whether revoking second secure boot key is enabled or disabled. 1: enabled. 0: disabled. 22 1 read-only - SECURE_BOOT_KEY_REVOKE2_ERR - Indicates a programming error of SECURE_BOOT_KEY_REVOKE2. + SECURE_BOOT_KEY_REVOKE2 + Represents whether revoking third secure boot key is enabled or disabled. 1: enabled. 0: disabled. 23 1 read-only - KEY_PURPOSE_0_ERR - Indicates a programming error of KEY_PURPOSE_0. + KEY_PURPOSE_0 + Represents the purpose of Key0. 24 4 read-only - KEY_PURPOSE_1_ERR - Indicates a programming error of KEY_PURPOSE_1. + KEY_PURPOSE_1 + Represents the purpose of Key1. 28 4 read-only @@ -34313,105 +34432,106 @@ - RD_REPEAT_ERR2 - Programming error record register 2 of BLOCK0. - 0x184 + RD_REPEAT_DATA2 + BLOCK0 data register 3. + 0x38 0x20 + 0x00080000 - KEY_PURPOSE_2_ERR - Indicates a programming error of KEY_PURPOSE_2. + KEY_PURPOSE_2 + Represents the purpose of Key2. 0 4 read-only - KEY_PURPOSE_3_ERR - Indicates a programming error of KEY_PURPOSE_3. + KEY_PURPOSE_3 + Represents the purpose of Key3. 4 4 read-only - KEY_PURPOSE_4_ERR - Indicates a programming error of KEY_PURPOSE_4. + KEY_PURPOSE_4 + Represents the purpose of Key4. 8 4 read-only - KEY_PURPOSE_5_ERR - Indicates a programming error of KEY_PURPOSE_5. + KEY_PURPOSE_5 + Represents the purpose of Key5. 12 4 read-only - SEC_DPA_LEVEL_ERR - Indicates a programming error of SEC_DPA_LEVEL. + SEC_DPA_LEVEL + Represents the spa secure level by configuring the clock random divide mode. 16 2 read-only - ECDSA_ENABLE_SOFT_K_ERR - Indicates a programming error of ECDSA_FORCE_USE_HARDWARE_K. + ECDSA_ENABLE_SOFT_K + Represents whether hardware random number k is forced used in ESDCA. 1: force used. 0: not force used. 18 1 read-only - CRYPT_DPA_ENABLE_ERR - Indicates a programming error of CRYPT_DPA_ENABLE. + CRYPT_DPA_ENABLE + Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled. 19 1 read-only - SECURE_BOOT_EN_ERR - Indicates a programming error of SECURE_BOOT_EN. + SECURE_BOOT_EN + Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled. 20 1 read-only - SECURE_BOOT_AGGRESSIVE_REVOKE_ERR - Indicates a programming error of SECURE_BOOT_AGGRESSIVE_REVOKE. + SECURE_BOOT_AGGRESSIVE_REVOKE + Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled. 21 1 read-only - FLASH_TYPE_ERR - Indicates a programming error of FLASH_TYPE. + FLASH_TYPE + The type of interfaced flash. 0: four data lines, 1: eight data lines. 23 1 read-only - FLASH_PAGE_SIZE_ERR - Indicates a programming error of FLASH_PAGE_SIZE. + FLASH_PAGE_SIZE + Set flash page size. 24 2 read-only - FLASH_ECC_EN_ERR - Indicates a programming error of FLASH_ECC_EN. + FLASH_ECC_EN + Set this bit to enable ecc for flash boot. 26 1 read-only - DIS_USB_OTG_DOWNLOAD_MODE_ERR - Indicates a programming error of DIS_USB_OTG_DOWNLOAD_MODE. + DIS_USB_OTG_DOWNLOAD_MODE + Set this bit to disable download via USB-OTG. 27 1 read-only - FLASH_TPUW_ERR - Indicates a programming error of FLASH_TPUW. + FLASH_TPUW + Represents the flash waiting time after power-up, in unit of ms. When the value less than 15, the waiting time is the programmed value. Otherwise, the waiting time is 2 times the programmed value. 28 4 read-only @@ -34419,91 +34539,91 @@ - RD_REPEAT_ERR3 - Programming error record register 3 of BLOCK0. - 0x188 + RD_REPEAT_DATA3 + BLOCK0 data register 4. + 0x3C 0x20 - DIS_DOWNLOAD_MODE_ERR - Indicates a programming error of DIS_DOWNLOAD_MODE. + DIS_DOWNLOAD_MODE + Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled. 0 1 read-only - DIS_DIRECT_BOOT_ERR - Indicates a programming error of DIS_DIRECT_BOOT. + DIS_DIRECT_BOOT + Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled. 1 1 read-only - DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR - Indicates a programming error of DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR. + DIS_USB_SERIAL_JTAG_ROM_PRINT + Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled. 2 1 read-only - LOCK_KM_KEY_ERR + LOCK_KM_KEY TBD 3 1 read-only - DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR - Indicates a programming error of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE. + DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE + Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: disabled. 0: enabled. 4 1 read-only - ENABLE_SECURITY_DOWNLOAD_ERR - Indicates a programming error of ENABLE_SECURITY_DOWNLOAD. + ENABLE_SECURITY_DOWNLOAD + Represents whether security download is enabled or disabled. 1: enabled. 0: disabled. 5 1 read-only - UART_PRINT_CONTROL_ERR - Indicates a programming error of UART_PRINT_CONTROL. + UART_PRINT_CONTROL + Represents the type of UART printing. 00: force enable printing. 01: enable printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset at high level. 11: force disable printing. 6 2 read-only - FORCE_SEND_RESUME_ERR - Indicates a programming error of FORCE_SEND_RESUME. + FORCE_SEND_RESUME + Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced. 0:not forced. 8 1 read-only - SECURE_VERSION_ERR - Indicates a programming error of SECURE VERSION. + SECURE_VERSION + Represents the version used by ESP-IDF anti-rollback feature. 9 16 read-only - SECURE_BOOT_DISABLE_FAST_WAKE_ERR - Indicates a programming error of SECURE_BOOT_DISABLE_FAST_WAKE. + SECURE_BOOT_DISABLE_FAST_WAKE + Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled. 25 1 read-only - HYS_EN_PAD_ERR - Indicates a programming error of HYS_EN_PAD. + HYS_EN_PAD + Represents whether the hysteresis function of corresponding PAD is enabled. 1: enabled. 0:disabled. 26 1 read-only - DCDC_VSET_ERR - Indicates a programming error of DCDC_VSET. + DCDC_VSET + Set the dcdc voltage default. 27 5 read-only @@ -34511,84 +34631,84 @@ - RD_REPEAT_ERR4 - Programming error record register 4 of BLOCK0. - 0x18C + RD_REPEAT_DATA4 + BLOCK0 data register 5. + 0x40 0x20 - _0PXA_TIEH_SEL_0_ERR - Indicates a programming error of 0PXA_TIEH_SEL_0. + _0PXA_TIEH_SEL_0 + TBD 0 2 read-only - _0PXA_TIEH_SEL_1_ERR - Indicates a programming error of 0PXA_TIEH_SEL_1. + _0PXA_TIEH_SEL_1 + TBD. 2 2 read-only - _0PXA_TIEH_SEL_2_ERR - Indicates a programming error of 0PXA_TIEH_SEL_2. + _0PXA_TIEH_SEL_2 + TBD. 4 2 read-only - _0PXA_TIEH_SEL_3_ERR - Indicates a programming error of 0PXA_TIEH_SEL_3. + _0PXA_TIEH_SEL_3 + TBD. 6 2 read-only - KM_DISABLE_DEPLOY_MODE_ERR + KM_DISABLE_DEPLOY_MODE TBD. 8 4 read-only - USB_DEVICE_DREFL_ERR - Indicates a programming error of USB_DEVICE_DREFL. + USB_DEVICE_DREFL + Represents the usb device single-end input low threhold, 0.8 V to 1.04 V with step of 80 mV. 12 2 read-only - USB_OTG11_DREFL_ERR - Indicates a programming error of USB_OTG11_DREFL. + USB_OTG11_DREFL + Represents the usb otg11 single-end input low threhold, 0.8 V to 1.04 V with step of 80 mV. 14 2 read-only - HP_PWR_SRC_SEL_ERR - Indicates a programming error of HP_PWR_SRC_SEL. + HP_PWR_SRC_SEL + HP system power source select. 0:LDO. 1: DCDC. 18 1 read-only - DCDC_VSET_EN_ERR - Indicates a programming error of DCDC_VSET_EN. + DCDC_VSET_EN + Select dcdc vset use efuse_dcdc_vset. 19 1 read-only - DIS_WDT_ERR - Indicates a programming error of DIS_WDT. + DIS_WDT + Set this bit to disable watch dog. 20 1 read-only - DIS_SWD_ERR - Indicates a programming error of DIS_SWD. + DIS_SWD + Set this bit to disable super-watchdog. 21 1 read-only @@ -34596,596 +34716,365 @@ - RD_RS_ERR0 - Programming error record register 0 of BLOCK1-10. - 0x1C0 + RD_MAC_SYS_0 + BLOCK1 data register $n. + 0x44 0x20 - MAC_SYS_ERR_NUM - The value of this signal means the number of error bytes. + MAC_0 + Stores the low 32 bits of MAC address. 0 - 3 + 32 read-only + + + + RD_MAC_SYS_1 + BLOCK1 data register $n. + 0x48 + 0x20 + - MAC_SYS_FAIL - 0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that programming user data failed and the number of error bytes is over 6. - 3 - 1 + MAC_1 + Stores the high 16 bits of MAC address. + 0 + 16 read-only - SYS_PART1_ERR_NUM - The value of this signal means the number of error bytes. - 4 - 3 + MAC_EXT + Stores the extended bits of MAC address. + 16 + 16 read-only + + + + RD_MAC_SYS_2 + BLOCK1 data register $n. + 0x4C + 0x20 + - SYS_PART1_FAIL - 0: Means no failure and that the data of system part1 is reliable 1: Means that programming user data failed and the number of error bytes is over 6. - 7 - 1 + MAC_RESERVED_1 + Reserved. + 0 + 14 read-only - USR_DATA_ERR_NUM - The value of this signal means the number of error bytes. - 8 - 3 + MAC_RESERVED_0 + Reserved. + 14 + 18 read-only + + + + RD_MAC_SYS_3 + BLOCK1 data register $n. + 0x50 + 0x20 + - USR_DATA_FAIL - 0: Means no failure and that the user data is reliable 1: Means that programming user data failed and the number of error bytes is over 6. - 11 - 1 + MAC_RESERVED_2 + Reserved. + 0 + 18 read-only - KEY0_ERR_NUM - The value of this signal means the number of error bytes. - 12 - 3 + SYS_DATA_PART0_0 + Stores the first 14 bits of the zeroth part of system data. + 18 + 14 read-only + + + + RD_MAC_SYS_4 + BLOCK1 data register $n. + 0x54 + 0x20 + - KEY0_FAIL - 0: Means no failure and that the data of key0 is reliable 1: Means that programming key0 failed and the number of error bytes is over 6. - 15 - 1 + SYS_DATA_PART0_1 + Stores the first 32 bits of the zeroth part of system data. + 0 + 32 read-only + + + + RD_MAC_SYS_5 + BLOCK1 data register $n. + 0x58 + 0x20 + - KEY1_ERR_NUM - The value of this signal means the number of error bytes. - 16 - 3 + SYS_DATA_PART0_2 + Stores the second 32 bits of the zeroth part of system data. + 0 + 32 read-only + + + + RD_SYS_PART1_DATA0 + Register $n of BLOCK2 (system). + 0x5C + 0x20 + - KEY1_FAIL - 0: Means no failure and that the data of key1 is reliable 1: Means that programming key1 failed and the number of error bytes is over 6. - 19 - 1 - read-only - - - KEY2_ERR_NUM - The value of this signal means the number of error bytes. - 20 - 3 - read-only - - - KEY2_FAIL - 0: Means no failure and that the data of key2 is reliable 1: Means that programming key2 failed and the number of error bytes is over 6. - 23 - 1 - read-only - - - KEY3_ERR_NUM - The value of this signal means the number of error bytes. - 24 - 3 - read-only - - - KEY3_FAIL - 0: Means no failure and that the data of key3 is reliable 1: Means that programming key3 failed and the number of error bytes is over 6. - 27 - 1 - read-only - - - KEY4_ERR_NUM - The value of this signal means the number of error bytes. - 28 - 3 - read-only - - - KEY4_FAIL - 0: Means no failure and that the data of key4 is reliable 1: Means that programming key4 failed and the number of error bytes is over 6. - 31 - 1 + SYS_DATA_PART1_0 + Stores the zeroth 32 bits of the first part of system data. + 0 + 32 read-only - RD_RS_ERR1 - Programming error record register 1 of BLOCK1-10. - 0x1C4 + RD_SYS_PART1_DATA1 + Register $n of BLOCK2 (system). + 0x60 0x20 - KEY5_ERR_NUM - The value of this signal means the number of error bytes. + SYS_DATA_PART1_1 + Stores the first 32 bits of the first part of system data. 0 - 3 - read-only - - - KEY5_FAIL - 0: Means no failure and that the data of key5 is reliable 1: Means that programming key5 failed and the number of error bytes is over 6. - 3 - 1 - read-only - - - SYS_PART2_ERR_NUM - The value of this signal means the number of error bytes. - 4 - 3 - read-only - - - SYS_PART2_FAIL - 0: Means no failure and that the data of system part2 is reliable 1: Means that programming user data failed and the number of error bytes is over 6. - 7 - 1 + 32 read-only - CLK - eFuse clcok configuration register. - 0x1C8 + RD_SYS_PART1_DATA2 + Register $n of BLOCK2 (system). + 0x64 0x20 - MEM_FORCE_PD - Set this bit to force eFuse SRAM into power-saving mode. + SYS_DATA_PART1_2 + Stores the second 32 bits of the first part of system data. 0 - 1 - read-write - - - MEM_CLK_FORCE_ON - Set this bit and force to activate clock signal of eFuse SRAM. - 1 - 1 - read-write - - - MEM_FORCE_PU - Set this bit to force eFuse SRAM into working mode. - 2 - 1 - read-write - - - EN - Set this bit to force enable eFuse register configuration clock signal. - 16 - 1 - read-write + 32 + read-only - CONF - eFuse operation mode configuraiton register - 0x1CC + RD_SYS_PART1_DATA3 + Register $n of BLOCK2 (system). + 0x68 0x20 - OP_CODE - 0x5A5A: programming operation command 0x5AA5: read operation command. + SYS_DATA_PART1_3 + Stores the third 32 bits of the first part of system data. 0 - 16 - read-write - - - CFG_ECDSA_BLK - Configures which block to use for ECDSA key output. - 16 - 4 - read-write + 32 + read-only - STATUS - eFuse status register. - 0x1D0 + RD_SYS_PART1_DATA4 + Register $n of BLOCK2 (system). + 0x6C 0x20 - STATE - Indicates the state of the eFuse state machine. + SYS_DATA_PART1_4 + Stores the fourth 32 bits of the first part of system data. 0 - 4 - read-only - - - OTP_LOAD_SW - The value of OTP_LOAD_SW. - 4 - 1 - read-only - - - OTP_VDDQ_C_SYNC2 - The value of OTP_VDDQ_C_SYNC2. - 5 - 1 - read-only - - - OTP_STROBE_SW - The value of OTP_STROBE_SW. - 6 - 1 - read-only - - - OTP_CSB_SW - The value of OTP_CSB_SW. - 7 - 1 - read-only - - - OTP_PGENB_SW - The value of OTP_PGENB_SW. - 8 - 1 - read-only - - - OTP_VDDQ_IS_SW - The value of OTP_VDDQ_IS_SW. - 9 - 1 - read-only - - - BLK0_VALID_BIT_CNT - Indicates the number of block valid bit. - 10 - 10 - read-only - - - CUR_ECDSA_BLK - Indicates which block is used for ECDSA key output. - 20 - 4 + 32 read-only - CMD - eFuse command register. - 0x1D4 + RD_SYS_PART1_DATA5 + Register $n of BLOCK2 (system). + 0x70 0x20 - READ_CMD - Set this bit to send read command. + SYS_DATA_PART1_5 + Stores the fifth 32 bits of the first part of system data. 0 - 1 - read-write - - - PGM_CMD - Set this bit to send programming command. - 1 - 1 - read-write - - - BLK_NUM - The serial number of the block to be programmed. Value 0-10 corresponds to block number 0-10, respectively. - 2 - 4 - read-write + 32 + read-only - INT_RAW - eFuse raw interrupt register. - 0x1D8 + RD_SYS_PART1_DATA6 + Register $n of BLOCK2 (system). + 0x74 0x20 - READ_DONE_INT_RAW - The raw bit signal for read_done interrupt. + SYS_DATA_PART1_6 + Stores the sixth 32 bits of the first part of system data. 0 - 1 - read-only - - - PGM_DONE_INT_RAW - The raw bit signal for pgm_done interrupt. - 1 - 1 + 32 read-only - INT_ST - eFuse interrupt status register. - 0x1DC + RD_SYS_PART1_DATA7 + Register $n of BLOCK2 (system). + 0x78 0x20 - READ_DONE_INT_ST - The status signal for read_done interrupt. + SYS_DATA_PART1_7 + Stores the seventh 32 bits of the first part of system data. 0 - 1 - read-only - - - PGM_DONE_INT_ST - The status signal for pgm_done interrupt. - 1 - 1 + 32 read-only - INT_ENA - eFuse interrupt enable register. - 0x1E0 + RD_USR_DATA0 + Register $n of BLOCK3 (user). + 0x7C 0x20 - READ_DONE_INT_ENA - The enable signal for read_done interrupt. + USR_DATA0 + Stores the zeroth 32 bits of BLOCK3 (user). 0 - 1 - read-write - - - PGM_DONE_INT_ENA - The enable signal for pgm_done interrupt. - 1 - 1 - read-write + 32 + read-only - INT_CLR - eFuse interrupt clear register. - 0x1E4 + RD_USR_DATA1 + Register $n of BLOCK3 (user). + 0x80 0x20 - READ_DONE_INT_CLR - The clear signal for read_done interrupt. + USR_DATA1 + Stores the first 32 bits of BLOCK3 (user). 0 - 1 - write-only - - - PGM_DONE_INT_CLR - The clear signal for pgm_done interrupt. - 1 - 1 - write-only + 32 + read-only - DAC_CONF - Controls the eFuse programming voltage. - 0x1E8 + RD_USR_DATA2 + Register $n of BLOCK3 (user). + 0x84 0x20 - 0x0001FE17 - DAC_CLK_DIV - Controls the division factor of the rising clock of the programming voltage. + USR_DATA2 + Stores the second 32 bits of BLOCK3 (user). 0 - 8 - read-write - - - DAC_CLK_PAD_SEL - Don't care. - 8 - 1 - read-write - - - DAC_NUM - Controls the rising period of the programming voltage. - 9 - 8 - read-write - - - OE_CLR - Reduces the power supply of the programming voltage. - 17 - 1 - read-write + 32 + read-only - RD_TIM_CONF - Configures read timing parameters. - 0x1EC + RD_USR_DATA3 + Register $n of BLOCK3 (user). + 0x88 0x20 - 0x0F010201 - THR_A - Configures the read hold time. + USR_DATA3 + Stores the third 32 bits of BLOCK3 (user). 0 - 8 - read-write - - - TRD - Configures the read time. - 8 - 8 - read-write - - - TSUR_A - Configures the read setup time. - 16 - 8 - read-write - - - READ_INIT_NUM - Configures the waiting time of reading eFuse memory. - 24 - 8 - read-write + 32 + read-only - WR_TIM_CONF1 - Configurarion register 1 of eFuse programming timing parameters. - 0x1F0 + RD_USR_DATA4 + Register $n of BLOCK3 (user). + 0x8C 0x20 - 0x01266701 - TSUP_A - Configures the programming setup time. + USR_DATA4 + Stores the fourth 32 bits of BLOCK3 (user). 0 - 8 - read-write - - - PWR_ON_NUM - Configures the power up time for VDDQ. - 8 - 16 - read-write - - - THP_A - Configures the programming hold time. - 24 - 8 - read-write + 32 + read-only - WR_TIM_CONF2 - Configurarion register 2 of eFuse programming timing parameters. - 0x1F4 + RD_USR_DATA5 + Register $n of BLOCK3 (user). + 0x90 0x20 - 0x00A00140 - PWR_OFF_NUM - Configures the power outage time for VDDQ. + USR_DATA5 + Stores the fifth 32 bits of BLOCK3 (user). 0 - 16 - read-write - - - TPGM - Configures the active programming time. - 16 - 16 - read-write + 32 + read-only - WR_TIM_CONF0_RS_BYPASS - Configurarion register0 of eFuse programming time parameters and rs bypass operation. - 0x1F8 + RD_USR_DATA6 + Register $n of BLOCK3 (user). + 0x94 0x20 - 0x00002000 - BYPASS_RS_CORRECTION - Set this bit to bypass reed solomon correction step. + USR_DATA6 + Stores the sixth 32 bits of BLOCK3 (user). 0 - 1 - read-write - - - BYPASS_RS_BLK_NUM - Configures block number of programming twice operation. - 1 - 11 - read-write - - - UPDATE - Set this bit to update multi-bit register signals. - 12 - 1 - write-only - - - TPGM_INACTIVE - Configures the inactive programming time. - 13 - 8 - read-write + 32 + read-only - DATE - eFuse version register. - 0x1FC + RD_USR_DATA7 + Register $n of BLOCK3 (user). + 0x98 0x20 - 0x02305050 - DATE - Stores eFuse version. + USR_DATA7 + Stores the seventh 32 bits of BLOCK3 (user). 0 - 28 - read-write + 32 + read-only - APB2OTP_WR_DIS - eFuse apb2otp block0 data register1. - 0x800 + RD_KEY0_DATA0 + Register $n of BLOCK4 (KEY0). + 0x9C 0x20 - APB2OTP_BLOCK0_WR_DIS - Otp block0 write disable data. + KEY0_DATA0 + Stores the zeroth 32 bits of KEY0. 0 32 read-only @@ -35193,14 +35082,14 @@ - APB2OTP_BLK0_BACKUP1_W1 - eFuse apb2otp block0 data register2. - 0x804 + RD_KEY0_DATA1 + Register $n of BLOCK4 (KEY0). + 0xA0 0x20 - APB2OTP_BLOCK0_BACKUP1_W1 - Otp block0 backup1 word1 data. + KEY0_DATA1 + Stores the first 32 bits of KEY0. 0 32 read-only @@ -35208,14 +35097,14 @@ - APB2OTP_BLK0_BACKUP1_W2 - eFuse apb2otp block0 data register3. - 0x808 + RD_KEY0_DATA2 + Register $n of BLOCK4 (KEY0). + 0xA4 0x20 - APB2OTP_BLOCK0_BACKUP1_W2 - Otp block0 backup1 word2 data. + KEY0_DATA2 + Stores the second 32 bits of KEY0. 0 32 read-only @@ -35223,14 +35112,14 @@ - APB2OTP_BLK0_BACKUP1_W3 - eFuse apb2otp block0 data register4. - 0x80C + RD_KEY0_DATA3 + Register $n of BLOCK4 (KEY0). + 0xA8 0x20 - APB2OTP_BLOCK0_BACKUP1_W3 - Otp block0 backup1 word3 data. + KEY0_DATA3 + Stores the third 32 bits of KEY0. 0 32 read-only @@ -35238,14 +35127,14 @@ - APB2OTP_BLK0_BACKUP1_W4 - eFuse apb2otp block0 data register5. - 0x810 + RD_KEY0_DATA4 + Register $n of BLOCK4 (KEY0). + 0xAC 0x20 - APB2OTP_BLOCK0_BACKUP1_W4 - Otp block0 backup1 word4 data. + KEY0_DATA4 + Stores the fourth 32 bits of KEY0. 0 32 read-only @@ -35253,14 +35142,14 @@ - APB2OTP_BLK0_BACKUP1_W5 - eFuse apb2otp block0 data register6. - 0x814 + RD_KEY0_DATA5 + Register $n of BLOCK4 (KEY0). + 0xB0 0x20 - APB2OTP_BLOCK0_BACKUP1_W5 - Otp block0 backup1 word5 data. + KEY0_DATA5 + Stores the fifth 32 bits of KEY0. 0 32 read-only @@ -35268,14 +35157,14 @@ - APB2OTP_BLK0_BACKUP2_W1 - eFuse apb2otp block0 data register7. - 0x818 + RD_KEY0_DATA6 + Register $n of BLOCK4 (KEY0). + 0xB4 0x20 - APB2OTP_BLOCK0_BACKUP2_W1 - Otp block0 backup2 word1 data. + KEY0_DATA6 + Stores the sixth 32 bits of KEY0. 0 32 read-only @@ -35283,14 +35172,14 @@ - APB2OTP_BLK0_BACKUP2_W2 - eFuse apb2otp block0 data register8. - 0x81C + RD_KEY0_DATA7 + Register $n of BLOCK4 (KEY0). + 0xB8 0x20 - APB2OTP_BLOCK0_BACKUP2_W2 - Otp block0 backup2 word2 data. + KEY0_DATA7 + Stores the seventh 32 bits of KEY0. 0 32 read-only @@ -35298,14 +35187,14 @@ - APB2OTP_BLK0_BACKUP2_W3 - eFuse apb2otp block0 data register9. - 0x820 + RD_KEY1_DATA0 + Register $n of BLOCK5 (KEY1). + 0xBC 0x20 - APB2OTP_BLOCK0_BACKUP2_W3 - Otp block0 backup2 word3 data. + KEY1_DATA0 + Stores the zeroth 32 bits of KEY1. 0 32 read-only @@ -35313,14 +35202,14 @@ - APB2OTP_BLK0_BACKUP2_W4 - eFuse apb2otp block0 data register10. - 0x824 + RD_KEY1_DATA1 + Register $n of BLOCK5 (KEY1). + 0xC0 0x20 - APB2OTP_BLOCK0_BACKUP2_W4 - Otp block0 backup2 word4 data. + KEY1_DATA1 + Stores the first 32 bits of KEY1. 0 32 read-only @@ -35328,14 +35217,14 @@ - APB2OTP_BLK0_BACKUP2_W5 - eFuse apb2otp block0 data register11. - 0x828 + RD_KEY1_DATA2 + Register $n of BLOCK5 (KEY1). + 0xC4 0x20 - APB2OTP_BLOCK0_BACKUP2_W5 - Otp block0 backup2 word5 data. + KEY1_DATA2 + Stores the second 32 bits of KEY1. 0 32 read-only @@ -35343,14 +35232,14 @@ - APB2OTP_BLK0_BACKUP3_W1 - eFuse apb2otp block0 data register12. - 0x82C + RD_KEY1_DATA3 + Register $n of BLOCK5 (KEY1). + 0xC8 0x20 - APB2OTP_BLOCK0_BACKUP3_W1 - Otp block0 backup3 word1 data. + KEY1_DATA3 + Stores the third 32 bits of KEY1. 0 32 read-only @@ -35358,14 +35247,14 @@ - APB2OTP_BLK0_BACKUP3_W2 - eFuse apb2otp block0 data register13. - 0x830 + RD_KEY1_DATA4 + Register $n of BLOCK5 (KEY1). + 0xCC 0x20 - APB2OTP_BLOCK0_BACKUP3_W2 - Otp block0 backup3 word2 data. + KEY1_DATA4 + Stores the fourth 32 bits of KEY1. 0 32 read-only @@ -35373,14 +35262,14 @@ - APB2OTP_BLK0_BACKUP3_W3 - eFuse apb2otp block0 data register14. - 0x834 + RD_KEY1_DATA5 + Register $n of BLOCK5 (KEY1). + 0xD0 0x20 - APB2OTP_BLOCK0_BACKUP3_W3 - Otp block0 backup3 word3 data. + KEY1_DATA5 + Stores the fifth 32 bits of KEY1. 0 32 read-only @@ -35388,14 +35277,14 @@ - APB2OTP_BLK0_BACKUP3_W4 - eFuse apb2otp block0 data register15. - 0x838 + RD_KEY1_DATA6 + Register $n of BLOCK5 (KEY1). + 0xD4 0x20 - APB2OTP_BLOCK0_BACKUP3_W4 - Otp block0 backup3 word4 data. + KEY1_DATA6 + Stores the sixth 32 bits of KEY1. 0 32 read-only @@ -35403,14 +35292,14 @@ - APB2OTP_BLK0_BACKUP3_W5 - eFuse apb2otp block0 data register16. - 0x83C + RD_KEY1_DATA7 + Register $n of BLOCK5 (KEY1). + 0xD8 0x20 - APB2OTP_BLOCK0_BACKUP3_W5 - Otp block0 backup3 word5 data. + KEY1_DATA7 + Stores the seventh 32 bits of KEY1. 0 32 read-only @@ -35418,14 +35307,14 @@ - APB2OTP_BLK0_BACKUP4_W1 - eFuse apb2otp block0 data register17. - 0x840 + RD_KEY2_DATA0 + Register $n of BLOCK6 (KEY2). + 0xDC 0x20 - APB2OTP_BLOCK0_BACKUP4_W1 - Otp block0 backup4 word1 data. + KEY2_DATA0 + Stores the zeroth 32 bits of KEY2. 0 32 read-only @@ -35433,14 +35322,14 @@ - APB2OTP_BLK0_BACKUP4_W2 - eFuse apb2otp block0 data register18. - 0x844 + RD_KEY2_DATA1 + Register $n of BLOCK6 (KEY2). + 0xE0 0x20 - APB2OTP_BLOCK0_BACKUP4_W2 - Otp block0 backup4 word2 data. + KEY2_DATA1 + Stores the first 32 bits of KEY2. 0 32 read-only @@ -35448,14 +35337,14 @@ - APB2OTP_BLK0_BACKUP4_W3 - eFuse apb2otp block0 data register19. - 0x848 + RD_KEY2_DATA2 + Register $n of BLOCK6 (KEY2). + 0xE4 0x20 - APB2OTP_BLOCK0_BACKUP4_W3 - Otp block0 backup4 word3 data. + KEY2_DATA2 + Stores the second 32 bits of KEY2. 0 32 read-only @@ -35463,14 +35352,14 @@ - APB2OTP_BLK0_BACKUP4_W4 - eFuse apb2otp block0 data register20. - 0x84C + RD_KEY2_DATA3 + Register $n of BLOCK6 (KEY2). + 0xE8 0x20 - APB2OTP_BLOCK0_BACKUP4_W4 - Otp block0 backup4 word4 data. + KEY2_DATA3 + Stores the third 32 bits of KEY2. 0 32 read-only @@ -35478,14 +35367,14 @@ - APB2OTP_BLK0_BACKUP4_W5 - eFuse apb2otp block0 data register21. - 0x850 + RD_KEY2_DATA4 + Register $n of BLOCK6 (KEY2). + 0xEC 0x20 - APB2OTP_BLOCK0_BACKUP4_W5 - Otp block0 backup4 word5 data. + KEY2_DATA4 + Stores the fourth 32 bits of KEY2. 0 32 read-only @@ -35493,14 +35382,14 @@ - APB2OTP_BLK1_W1 - eFuse apb2otp block1 data register1. - 0x854 + RD_KEY2_DATA5 + Register $n of BLOCK6 (KEY2). + 0xF0 0x20 - APB2OTP_BLOCK1_W1 - Otp block1 word1 data. + KEY2_DATA5 + Stores the fifth 32 bits of KEY2. 0 32 read-only @@ -35508,14 +35397,14 @@ - APB2OTP_BLK1_W2 - eFuse apb2otp block1 data register2. - 0x858 + RD_KEY2_DATA6 + Register $n of BLOCK6 (KEY2). + 0xF4 0x20 - APB2OTP_BLOCK1_W2 - Otp block1 word2 data. + KEY2_DATA6 + Stores the sixth 32 bits of KEY2. 0 32 read-only @@ -35523,14 +35412,14 @@ - APB2OTP_BLK1_W3 - eFuse apb2otp block1 data register3. - 0x85C + RD_KEY2_DATA7 + Register $n of BLOCK6 (KEY2). + 0xF8 0x20 - APB2OTP_BLOCK1_W3 - Otp block1 word3 data. + KEY2_DATA7 + Stores the seventh 32 bits of KEY2. 0 32 read-only @@ -35538,14 +35427,14 @@ - APB2OTP_BLK1_W4 - eFuse apb2otp block1 data register4. - 0x860 + RD_KEY3_DATA0 + Register $n of BLOCK7 (KEY3). + 0xFC 0x20 - APB2OTP_BLOCK1_W4 - Otp block1 word4 data. + KEY3_DATA0 + Stores the zeroth 32 bits of KEY3. 0 32 read-only @@ -35553,14 +35442,14 @@ - APB2OTP_BLK1_W5 - eFuse apb2otp block1 data register5. - 0x864 + RD_KEY3_DATA1 + Register $n of BLOCK7 (KEY3). + 0x100 0x20 - APB2OTP_BLOCK1_W5 - Otp block1 word5 data. + KEY3_DATA1 + Stores the first 32 bits of KEY3. 0 32 read-only @@ -35568,14 +35457,14 @@ - APB2OTP_BLK1_W6 - eFuse apb2otp block1 data register6. - 0x868 + RD_KEY3_DATA2 + Register $n of BLOCK7 (KEY3). + 0x104 0x20 - APB2OTP_BLOCK1_W6 - Otp block1 word6 data. + KEY3_DATA2 + Stores the second 32 bits of KEY3. 0 32 read-only @@ -35583,14 +35472,14 @@ - APB2OTP_BLK1_W7 - eFuse apb2otp block1 data register7. - 0x86C + RD_KEY3_DATA3 + Register $n of BLOCK7 (KEY3). + 0x108 0x20 - APB2OTP_BLOCK1_W7 - Otp block1 word7 data. + KEY3_DATA3 + Stores the third 32 bits of KEY3. 0 32 read-only @@ -35598,14 +35487,14 @@ - APB2OTP_BLK1_W8 - eFuse apb2otp block1 data register8. - 0x870 + RD_KEY3_DATA4 + Register $n of BLOCK7 (KEY3). + 0x10C 0x20 - APB2OTP_BLOCK1_W8 - Otp block1 word8 data. + KEY3_DATA4 + Stores the fourth 32 bits of KEY3. 0 32 read-only @@ -35613,14 +35502,14 @@ - APB2OTP_BLK1_W9 - eFuse apb2otp block1 data register9. - 0x874 + RD_KEY3_DATA5 + Register $n of BLOCK7 (KEY3). + 0x110 0x20 - APB2OTP_BLOCK1_W9 - Otp block1 word9 data. + KEY3_DATA5 + Stores the fifth 32 bits of KEY3. 0 32 read-only @@ -35628,14 +35517,14 @@ - APB2OTP_BLK2_W1 - eFuse apb2otp block2 data register1. - 0x878 + RD_KEY3_DATA6 + Register $n of BLOCK7 (KEY3). + 0x114 0x20 - APB2OTP_BLOCK2_W1 - Otp block2 word1 data. + KEY3_DATA6 + Stores the sixth 32 bits of KEY3. 0 32 read-only @@ -35643,14 +35532,14 @@ - APB2OTP_BLK2_W2 - eFuse apb2otp block2 data register2. - 0x87C + RD_KEY3_DATA7 + Register $n of BLOCK7 (KEY3). + 0x118 0x20 - APB2OTP_BLOCK2_W2 - Otp block2 word2 data. + KEY3_DATA7 + Stores the seventh 32 bits of KEY3. 0 32 read-only @@ -35658,14 +35547,14 @@ - APB2OTP_BLK2_W3 - eFuse apb2otp block2 data register3. - 0x880 + RD_KEY4_DATA0 + Register $n of BLOCK8 (KEY4). + 0x11C 0x20 - APB2OTP_BLOCK2_W3 - Otp block2 word3 data. + KEY4_DATA0 + Stores the zeroth 32 bits of KEY4. 0 32 read-only @@ -35673,14 +35562,14 @@ - APB2OTP_BLK2_W4 - eFuse apb2otp block2 data register4. - 0x884 + RD_KEY4_DATA1 + Register $n of BLOCK8 (KEY4). + 0x120 0x20 - APB2OTP_BLOCK2_W4 - Otp block2 word4 data. + KEY4_DATA1 + Stores the first 32 bits of KEY4. 0 32 read-only @@ -35688,14 +35577,14 @@ - APB2OTP_BLK2_W5 - eFuse apb2otp block2 data register5. - 0x888 + RD_KEY4_DATA2 + Register $n of BLOCK8 (KEY4). + 0x124 0x20 - APB2OTP_BLOCK2_W5 - Otp block2 word5 data. + KEY4_DATA2 + Stores the second 32 bits of KEY4. 0 32 read-only @@ -35703,14 +35592,14 @@ - APB2OTP_BLK2_W6 - eFuse apb2otp block2 data register6. - 0x88C + RD_KEY4_DATA3 + Register $n of BLOCK8 (KEY4). + 0x128 0x20 - APB2OTP_BLOCK2_W6 - Otp block2 word6 data. + KEY4_DATA3 + Stores the third 32 bits of KEY4. 0 32 read-only @@ -35718,14 +35607,14 @@ - APB2OTP_BLK2_W7 - eFuse apb2otp block2 data register7. - 0x890 + RD_KEY4_DATA4 + Register $n of BLOCK8 (KEY4). + 0x12C 0x20 - APB2OTP_BLOCK2_W7 - Otp block2 word7 data. + KEY4_DATA4 + Stores the fourth 32 bits of KEY4. 0 32 read-only @@ -35733,14 +35622,14 @@ - APB2OTP_BLK2_W8 - eFuse apb2otp block2 data register8. - 0x894 + RD_KEY4_DATA5 + Register $n of BLOCK8 (KEY4). + 0x130 0x20 - APB2OTP_BLOCK2_W8 - Otp block2 word8 data. + KEY4_DATA5 + Stores the fifth 32 bits of KEY4. 0 32 read-only @@ -35748,14 +35637,14 @@ - APB2OTP_BLK2_W9 - eFuse apb2otp block2 data register9. - 0x898 + RD_KEY4_DATA6 + Register $n of BLOCK8 (KEY4). + 0x134 0x20 - APB2OTP_BLOCK2_W9 - Otp block2 word9 data. + KEY4_DATA6 + Stores the sixth 32 bits of KEY4. 0 32 read-only @@ -35763,14 +35652,14 @@ - APB2OTP_BLK2_W10 - eFuse apb2otp block2 data register10. - 0x89C + RD_KEY4_DATA7 + Register $n of BLOCK8 (KEY4). + 0x138 0x20 - APB2OTP_BLOCK2_W10 - Otp block2 word10 data. + KEY4_DATA7 + Stores the seventh 32 bits of KEY4. 0 32 read-only @@ -35778,14 +35667,14 @@ - APB2OTP_BLK2_W11 - eFuse apb2otp block2 data register11. - 0x8A0 + RD_KEY5_DATA0 + Register $n of BLOCK9 (KEY5). + 0x13C 0x20 - APB2OTP_BLOCK2_W11 - Otp block2 word11 data. + KEY5_DATA0 + Stores the zeroth 32 bits of KEY5. 0 32 read-only @@ -35793,14 +35682,14 @@ - APB2OTP_BLK3_W1 - eFuse apb2otp block3 data register1. - 0x8A4 + RD_KEY5_DATA1 + Register $n of BLOCK9 (KEY5). + 0x140 0x20 - APB2OTP_BLOCK3_W1 - Otp block3 word1 data. + KEY5_DATA1 + Stores the first 32 bits of KEY5. 0 32 read-only @@ -35808,14 +35697,14 @@ - APB2OTP_BLK3_W2 - eFuse apb2otp block3 data register2. - 0x8A8 + RD_KEY5_DATA2 + Register $n of BLOCK9 (KEY5). + 0x144 0x20 - APB2OTP_BLOCK3_W2 - Otp block3 word2 data. + KEY5_DATA2 + Stores the second 32 bits of KEY5. 0 32 read-only @@ -35823,14 +35712,14 @@ - APB2OTP_BLK3_W3 - eFuse apb2otp block3 data register3. - 0x8AC + RD_KEY5_DATA3 + Register $n of BLOCK9 (KEY5). + 0x148 0x20 - APB2OTP_BLOCK3_W3 - Otp block3 word3 data. + KEY5_DATA3 + Stores the third 32 bits of KEY5. 0 32 read-only @@ -35838,14 +35727,14 @@ - APB2OTP_BLK3_W4 - eFuse apb2otp block3 data register4. - 0x8B0 + RD_KEY5_DATA4 + Register $n of BLOCK9 (KEY5). + 0x14C 0x20 - APB2OTP_BLOCK3_W4 - Otp block3 word4 data. + KEY5_DATA4 + Stores the fourth 32 bits of KEY5. 0 32 read-only @@ -35853,14 +35742,14 @@ - APB2OTP_BLK3_W5 - eFuse apb2otp block3 data register5. - 0x8B4 + RD_KEY5_DATA5 + Register $n of BLOCK9 (KEY5). + 0x150 0x20 - APB2OTP_BLOCK3_W5 - Otp block3 word5 data. + KEY5_DATA5 + Stores the fifth 32 bits of KEY5. 0 32 read-only @@ -35868,14 +35757,14 @@ - APB2OTP_BLK3_W6 - eFuse apb2otp block3 data register6. - 0x8B8 + RD_KEY5_DATA6 + Register $n of BLOCK9 (KEY5). + 0x154 0x20 - APB2OTP_BLOCK3_W6 - Otp block3 word6 data. + KEY5_DATA6 + Stores the sixth 32 bits of KEY5. 0 32 read-only @@ -35883,14 +35772,14 @@ - APB2OTP_BLK3_W7 - eFuse apb2otp block3 data register7. - 0x8BC + RD_KEY5_DATA7 + Register $n of BLOCK9 (KEY5). + 0x158 0x20 - APB2OTP_BLOCK3_W7 - Otp block3 word7 data. + KEY5_DATA7 + Stores the seventh 32 bits of KEY5. 0 32 read-only @@ -35898,14 +35787,14 @@ - APB2OTP_BLK3_W8 - eFuse apb2otp block3 data register8. - 0x8C0 + RD_SYS_PART2_DATA0 + Register $n of BLOCK10 (system). + 0x15C 0x20 - APB2OTP_BLOCK3_W8 - Otp block3 word8 data. + SYS_DATA_PART2_0 + Stores the 0th 32 bits of the 2nd part of system data. 0 32 read-only @@ -35913,14 +35802,14 @@ - APB2OTP_BLK3_W9 - eFuse apb2otp block3 data register9. - 0x8C4 + RD_SYS_PART2_DATA1 + Register $n of BLOCK9 (KEY5). + 0x160 0x20 - APB2OTP_BLOCK3_W9 - Otp block3 word9 data. + SYS_DATA_PART2_1 + Stores the 0th 32 bits of the 2nd part of system data. 0 32 read-only @@ -35928,14 +35817,14 @@ - APB2OTP_BLK3_W10 - eFuse apb2otp block3 data register10. - 0x8C8 + RD_SYS_PART2_DATA2 + Register $n of BLOCK10 (system). + 0x164 0x20 - APB2OTP_BLOCK3_W10 - Otp block3 word10 data. + SYS_DATA_PART2_2 + Stores the 0th 32 bits of the 2nd part of system data. 0 32 read-only @@ -35943,14 +35832,14 @@ - APB2OTP_BLK3_W11 - eFuse apb2otp block3 data register11. - 0x8CC + RD_SYS_PART2_DATA3 + Register $n of BLOCK10 (system). + 0x168 0x20 - APB2OTP_BLOCK3_W11 - Otp block3 word11 data. + SYS_DATA_PART2_3 + Stores the 0th 32 bits of the 2nd part of system data. 0 32 read-only @@ -35958,14 +35847,14 @@ - APB2OTP_BLK4_W1 - eFuse apb2otp block4 data register1. - 0x8D0 + RD_SYS_PART2_DATA4 + Register $n of BLOCK10 (system). + 0x16C 0x20 - APB2OTP_BLOCK4_W1 - Otp block4 word1 data. + SYS_DATA_PART2_4 + Stores the 0th 32 bits of the 2nd part of system data. 0 32 read-only @@ -35973,14 +35862,14 @@ - APB2OTP_BLK4_W2 - eFuse apb2otp block4 data register2. - 0x8D4 + RD_SYS_PART2_DATA5 + Register $n of BLOCK10 (system). + 0x170 0x20 - APB2OTP_BLOCK4_W2 - Otp block4 word2 data. + SYS_DATA_PART2_5 + Stores the 0th 32 bits of the 2nd part of system data. 0 32 read-only @@ -35988,14 +35877,14 @@ - APB2OTP_BLK4_W3 - eFuse apb2otp block4 data register3. - 0x8D8 + RD_SYS_PART2_DATA6 + Register $n of BLOCK10 (system). + 0x174 0x20 - APB2OTP_BLOCK4_W3 - Otp block4 word3 data. + SYS_DATA_PART2_6 + Stores the 0th 32 bits of the 2nd part of system data. 0 32 read-only @@ -36003,14 +35892,14 @@ - APB2OTP_BLK4_W4 - eFuse apb2otp block4 data register4. - 0x8DC + RD_SYS_PART2_DATA7 + Register $n of BLOCK10 (system). + 0x178 0x20 - APB2OTP_BLOCK4_W4 - Otp block4 word4 data. + SYS_DATA_PART2_7 + Stores the 0th 32 bits of the 2nd part of system data. 0 32 read-only @@ -36018,1367 +35907,1225 @@ - APB2OTP_BLK4_W5 - eFuse apb2otp block4 data register5. - 0x8E0 + RD_REPEAT_ERR0 + Programming error record register 0 of BLOCK0. + 0x17C 0x20 - APB2OTP_BLOCK4_W5 - Otp block4 word5 data. + RD_DIS_ERR + Indicates a programming error of RD_DIS. 0 - 32 + 7 read-only - - - - APB2OTP_BLK4_W6 - eFuse apb2otp block4 data register6. - 0x8E4 - 0x20 - - APB2OTP_BLOCK4_W6 - Otp block4 word6 data. - 0 - 32 + DIS_USB_DEVICE_EXCHG_PINS_ERR + Indicates a programming error of DIS_USB_DEVICE_EXCHG_PINS. + 7 + 1 read-only - - - - APB2OTP_BLK4_W7 - eFuse apb2otp block4 data register7. - 0x8E8 - 0x20 - - APB2OTP_BLOCK4_W7 - Otp block4 word7 data. - 0 - 32 + DIS_USB_OTG11_EXCHG_PINS_ERR + Indicates a programming error of DIS_USB_OTG11_EXCHG_PINS. + 8 + 1 read-only - - - - APB2OTP_BLK4_W8 - eFuse apb2otp block4 data register8. - 0x8EC - 0x20 - - APB2OTP_BLOCK4_W8 - Otp block4 word8 data. - 0 - 32 + DIS_USB_JTAG_ERR + Indicates a programming error of DIS_USB_JTAG. + 9 + 1 read-only - - - - APB2OTP_BLK4_W9 - eFuse apb2otp block4 data register9. - 0x8F0 - 0x20 - - APB2OTP_BLOCK4_W9 - Otp block4 word9 data. - 0 - 32 + POWERGLITCH_EN_ERR + Indicates a programming error of POWERGLITCH_EN. + 10 + 1 read-only - - - - APB2OTP_BLK4_W10 - eFuse apb2otp block4 data registe10. - 0x8F4 - 0x20 - - APB2OTP_BLOCK4_W10 - Otp block4 word10 data. - 0 - 32 + DIS_USB_SERIAL_JTAG_ERR + Indicates a programming error of DIS_USB_SERIAL_JTAG. + 11 + 1 read-only - - - - APB2OTP_BLK4_W11 - eFuse apb2otp block4 data register11. - 0x8F8 - 0x20 - - APB2OTP_BLOCK4_W11 - Otp block4 word11 data. - 0 - 32 + DIS_FORCE_DOWNLOAD_ERR + Indicates a programming error of DIS_FORCE_DOWNLOAD. + 12 + 1 read-only - - - - APB2OTP_BLK5_W1 - eFuse apb2otp block5 data register1. - 0x8FC - 0x20 - - APB2OTP_BLOCK5_W1 - Otp block5 word1 data. - 0 - 32 + SPI_DOWNLOAD_MSPI_DIS_ERR + Indicates a programming error of SPI_DOWNLOAD_MSPI_DIS. + 13 + 1 read-only - - - - APB2OTP_BLK5_W2 - eFuse apb2otp block5 data register2. - 0x900 - 0x20 - - APB2OTP_BLOCK5_W2 - Otp block5 word2 data. - 0 - 32 + DIS_TWAI_ERR + Indicates a programming error of DIS_TWAI. + 14 + 1 read-only - - - - APB2OTP_BLK5_W3 - eFuse apb2otp block5 data register3. - 0x904 - 0x20 - - APB2OTP_BLOCK5_W3 - Otp block5 word3 data. - 0 - 32 + JTAG_SEL_ENABLE_ERR + Indicates a programming error of JTAG_SEL_ENABLE. + 15 + 1 read-only - - - - APB2OTP_BLK5_W4 - eFuse apb2otp block5 data register4. - 0x908 - 0x20 - - APB2OTP_BLOCK5_W4 - Otp block5 word4 data. - 0 - 32 + SOFT_DIS_JTAG_ERR + Indicates a programming error of SOFT_DIS_JTAG. + 16 + 3 read-only - - - - APB2OTP_BLK5_W5 - eFuse apb2otp block5 data register5. - 0x90C - 0x20 - - APB2OTP_BLOCK5_W5 - Otp block5 word5 data. - 0 - 32 + DIS_PAD_JTAG_ERR + Indicates a programming error of DIS_PAD_JTAG. + 19 + 1 read-only - - - - APB2OTP_BLK5_W6 - eFuse apb2otp block5 data register6. - 0x910 - 0x20 - - APB2OTP_BLOCK5_W6 - Otp block5 word6 data. - 0 - 32 + DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR + Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT. + 20 + 1 read-only - - - - APB2OTP_BLK5_W7 - eFuse apb2otp block5 data register7. - 0x914 - 0x20 - - APB2OTP_BLOCK5_W7 - Otp block5 word7 data. - 0 - 32 + USB_DEVICE_DREFH_ERR + Indicates a programming error of USB_DEVICE_DREFH. + 21 + 2 read-only - - - - APB2OTP_BLK5_W8 - eFuse apb2otp block5 data register8. - 0x918 - 0x20 - - APB2OTP_BLOCK5_W8 - Otp block5 word8 data. - 0 - 32 + USB_OTG11_DREFH_ERR + Indicates a programming error of USB_OTG11_DREFH. + 23 + 2 read-only - - - - APB2OTP_BLK5_W9 - eFuse apb2otp block5 data register9. - 0x91C - 0x20 - - APB2OTP_BLOCK5_W9 - Otp block5 word9 data. - 0 - 32 + USB_PHY_SEL_ERR + Indicates a programming error of USB_PHY_SEL. + 25 + 1 read-only - - - - APB2OTP_BLK5_W10 - eFuse apb2otp block5 data register10. - 0x920 - 0x20 - - APB2OTP_BLOCK5_W10 - Otp block5 word10 data. - 0 - 32 + HUK_GEN_STATE_LOW_ERR + Indicates a programming error of HUK_GEN_STATE_LOW. + 26 + 6 read-only - APB2OTP_BLK5_W11 - eFuse apb2otp block5 data register11. - 0x924 + RD_REPEAT_ERR1 + Programming error record register 1 of BLOCK0. + 0x180 0x20 - APB2OTP_BLOCK5_W11 - Otp block5 word11 data. + KM_HUK_GEN_STATE_HIGH_ERR + Indicates a programming error of HUK_GEN_STATE_HIGH. 0 - 32 + 3 read-only - - - - APB2OTP_BLK6_W1 - eFuse apb2otp block6 data register1. - 0x928 - 0x20 - - APB2OTP_BLOCK6_W1 - Otp block6 word1 data. - 0 - 32 + KM_RND_SWITCH_CYCLE_ERR + Indicates a programming error of KM_RND_SWITCH_CYCLE. + 3 + 2 read-only - - - - APB2OTP_BLK6_W2 - eFuse apb2otp block6 data register2. - 0x92C - 0x20 - - APB2OTP_BLOCK6_W2 - Otp block6 word2 data. - 0 - 32 + KM_DEPLOY_ONLY_ONCE_ERR + Indicates a programming error of KM_DEPLOY_ONLY_ONCE. + 5 + 4 read-only - - - - APB2OTP_BLK6_W3 - eFuse apb2otp block6 data register3. - 0x930 - 0x20 - - APB2OTP_BLOCK6_W3 - Otp block6 word3 data. - 0 - 32 + FORCE_USE_KEY_MANAGER_KEY_ERR + Indicates a programming error of FORCE_USE_KEY_MANAGER_KEY. + 9 + 4 read-only - - - - APB2OTP_BLK6_W4 - eFuse apb2otp block6 data register4. - 0x934 - 0x20 - - APB2OTP_BLOCK6_W4 - Otp block6 word4 data. - 0 - 32 + FORCE_DISABLE_SW_INIT_KEY_ERR + Indicates a programming error of FORCE_DISABLE_SW_INIT_KEY. + 13 + 1 read-only - - - - APB2OTP_BLK6_W5 - eFuse apb2otp block6 data register5. - 0x938 - 0x20 - - APB2OTP_BLOCK6_W5 - Otp block6 word5 data. - 0 - 32 + XTS_KEY_LENGTH_256_ERR + Indicates a programming error of XTS_KEY_LENGTH_256. + 14 + 1 read-only - - - - APB2OTP_BLK6_W6 - eFuse apb2otp block6 data register6. - 0x93C - 0x20 - - APB2OTP_BLOCK6_W6 - Otp block6 word6 data. - 0 - 32 + WDT_DELAY_SEL_ERR + Indicates a programming error of WDT_DELAY_SEL. + 16 + 2 read-only - - - - APB2OTP_BLK6_W7 - eFuse apb2otp block6 data register7. - 0x940 - 0x20 - - APB2OTP_BLOCK6_W7 - Otp block6 word7 data. - 0 - 32 + SPI_BOOT_CRYPT_CNT_ERR + Indicates a programming error of SPI_BOOT_CRYPT_CNT. + 18 + 3 read-only - - - - APB2OTP_BLK6_W8 - eFuse apb2otp block6 data register8. - 0x944 - 0x20 - - APB2OTP_BLOCK6_W8 - Otp block6 word8 data. - 0 - 32 + SECURE_BOOT_KEY_REVOKE0_ERR + Indicates a programming error of SECURE_BOOT_KEY_REVOKE0. + 21 + 1 read-only - - - - APB2OTP_BLK6_W9 - eFuse apb2otp block6 data register9. - 0x948 - 0x20 - - APB2OTP_BLOCK6_W9 - Otp block6 word9 data. - 0 - 32 + SECURE_BOOT_KEY_REVOKE1_ERR + Indicates a programming error of SECURE_BOOT_KEY_REVOKE1. + 22 + 1 read-only - - - - APB2OTP_BLK6_W10 - eFuse apb2otp block6 data register10. - 0x94C - 0x20 - - APB2OTP_BLOCK6_W10 - Otp block6 word10 data. - 0 - 32 + SECURE_BOOT_KEY_REVOKE2_ERR + Indicates a programming error of SECURE_BOOT_KEY_REVOKE2. + 23 + 1 read-only - - - - APB2OTP_BLK6_W11 - eFuse apb2otp block6 data register11. - 0x950 - 0x20 - - APB2OTP_BLOCK6_W11 - Otp block6 word11 data. - 0 - 32 + KEY_PURPOSE_0_ERR + Indicates a programming error of KEY_PURPOSE_0. + 24 + 4 read-only - - - - APB2OTP_BLK7_W1 - eFuse apb2otp block7 data register1. - 0x954 - 0x20 - - APB2OTP_BLOCK7_W1 - Otp block7 word1 data. - 0 - 32 + KEY_PURPOSE_1_ERR + Indicates a programming error of KEY_PURPOSE_1. + 28 + 4 read-only - APB2OTP_BLK7_W2 - eFuse apb2otp block7 data register2. - 0x958 + RD_REPEAT_ERR2 + Programming error record register 2 of BLOCK0. + 0x184 0x20 - APB2OTP_BLOCK7_W2 - Otp block7 word2 data. + KEY_PURPOSE_2_ERR + Indicates a programming error of KEY_PURPOSE_2. 0 - 32 + 4 read-only - - - - APB2OTP_BLK7_W3 - eFuse apb2otp block7 data register3. - 0x95C - 0x20 - - APB2OTP_BLOCK7_W3 - Otp block7 word3 data. - 0 - 32 + KEY_PURPOSE_3_ERR + Indicates a programming error of KEY_PURPOSE_3. + 4 + 4 read-only - - - - APB2OTP_BLK7_W4 - eFuse apb2otp block7 data register4. - 0x960 - 0x20 - - APB2OTP_BLOCK7_W4 - Otp block7 word4 data. - 0 - 32 + KEY_PURPOSE_4_ERR + Indicates a programming error of KEY_PURPOSE_4. + 8 + 4 read-only - - - - APB2OTP_BLK7_W5 - eFuse apb2otp block7 data register5. - 0x964 - 0x20 - - APB2OTP_BLOCK7_W5 - Otp block7 word5 data. - 0 - 32 + KEY_PURPOSE_5_ERR + Indicates a programming error of KEY_PURPOSE_5. + 12 + 4 read-only - - - - APB2OTP_BLK7_W6 - eFuse apb2otp block7 data register6. - 0x968 - 0x20 - - APB2OTP_BLOCK7_W6 - Otp block7 word6 data. - 0 - 32 + SEC_DPA_LEVEL_ERR + Indicates a programming error of SEC_DPA_LEVEL. + 16 + 2 read-only - - - - APB2OTP_BLK7_W7 - eFuse apb2otp block7 data register7. - 0x96C - 0x20 - - APB2OTP_BLOCK7_W7 - Otp block7 word7 data. - 0 - 32 + ECDSA_ENABLE_SOFT_K_ERR + Indicates a programming error of ECDSA_FORCE_USE_HARDWARE_K. + 18 + 1 read-only - - - - APB2OTP_BLK7_W8 - eFuse apb2otp block7 data register8. - 0x970 - 0x20 - - APB2OTP_BLOCK7_W8 - Otp block7 word8 data. - 0 - 32 + CRYPT_DPA_ENABLE_ERR + Indicates a programming error of CRYPT_DPA_ENABLE. + 19 + 1 read-only - - - - APB2OTP_BLK7_W9 - eFuse apb2otp block7 data register9. - 0x974 - 0x20 - - APB2OTP_BLOCK7_W9 - Otp block7 word9 data. - 0 - 32 + SECURE_BOOT_EN_ERR + Indicates a programming error of SECURE_BOOT_EN. + 20 + 1 read-only - - - - APB2OTP_BLK7_W10 - eFuse apb2otp block7 data register10. - 0x978 - 0x20 - - APB2OTP_BLOCK7_W10 - Otp block7 word10 data. - 0 - 32 + SECURE_BOOT_AGGRESSIVE_REVOKE_ERR + Indicates a programming error of SECURE_BOOT_AGGRESSIVE_REVOKE. + 21 + 1 read-only - - - - APB2OTP_BLK7_W11 - eFuse apb2otp block7 data register11. - 0x97C - 0x20 - - APB2OTP_BLOCK7_W11 - Otp block7 word11 data. - 0 - 32 + FLASH_TYPE_ERR + Indicates a programming error of FLASH_TYPE. + 23 + 1 read-only - - - - APB2OTP_BLK8_W1 - eFuse apb2otp block8 data register1. - 0x980 - 0x20 - - APB2OTP_BLOCK8_W1 - Otp block8 word1 data. - 0 - 32 + FLASH_PAGE_SIZE_ERR + Indicates a programming error of FLASH_PAGE_SIZE. + 24 + 2 read-only - - - - APB2OTP_BLK8_W2 - eFuse apb2otp block8 data register2. - 0x984 - 0x20 - - APB2OTP_BLOCK8_W2 - Otp block8 word2 data. - 0 - 32 + FLASH_ECC_EN_ERR + Indicates a programming error of FLASH_ECC_EN. + 26 + 1 read-only - - - - APB2OTP_BLK8_W3 - eFuse apb2otp block8 data register3. - 0x988 - 0x20 - - APB2OTP_BLOCK8_W3 - Otp block8 word3 data. - 0 - 32 + DIS_USB_OTG_DOWNLOAD_MODE_ERR + Indicates a programming error of DIS_USB_OTG_DOWNLOAD_MODE. + 27 + 1 read-only - - - - APB2OTP_BLK8_W4 - eFuse apb2otp block8 data register4. - 0x98C - 0x20 - - APB2OTP_BLOCK8_W4 - Otp block8 word4 data. - 0 - 32 + FLASH_TPUW_ERR + Indicates a programming error of FLASH_TPUW. + 28 + 4 read-only - APB2OTP_BLK8_W5 - eFuse apb2otp block8 data register5. - 0x990 + RD_REPEAT_ERR3 + Programming error record register 3 of BLOCK0. + 0x188 0x20 - APB2OTP_BLOCK8_W5 - Otp block8 word5 data. + DIS_DOWNLOAD_MODE_ERR + Indicates a programming error of DIS_DOWNLOAD_MODE. 0 - 32 + 1 read-only - - - - APB2OTP_BLK8_W6 - eFuse apb2otp block8 data register6. - 0x994 - 0x20 - - APB2OTP_BLOCK8_W6 - Otp block8 word6 data. - 0 - 32 + DIS_DIRECT_BOOT_ERR + Indicates a programming error of DIS_DIRECT_BOOT. + 1 + 1 read-only - - - - APB2OTP_BLK8_W7 - eFuse apb2otp block8 data register7. - 0x998 - 0x20 - - APB2OTP_BLOCK8_W7 - Otp block8 word7 data. - 0 - 32 + DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR + Indicates a programming error of DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR. + 2 + 1 read-only - - - - APB2OTP_BLK8_W8 - eFuse apb2otp block8 data register8. - 0x99C - 0x20 - - APB2OTP_BLOCK8_W8 - Otp block8 word8 data. - 0 - 32 + LOCK_KM_KEY_ERR + TBD + 3 + 1 read-only - - - - APB2OTP_BLK8_W9 - eFuse apb2otp block8 data register9. - 0x9A0 - 0x20 - - APB2OTP_BLOCK8_W9 - Otp block8 word9 data. - 0 - 32 + DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR + Indicates a programming error of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE. + 4 + 1 read-only - - - - APB2OTP_BLK8_W10 - eFuse apb2otp block8 data register10. - 0x9A4 - 0x20 - - APB2OTP_BLOCK8_W10 - Otp block8 word10 data. - 0 - 32 + ENABLE_SECURITY_DOWNLOAD_ERR + Indicates a programming error of ENABLE_SECURITY_DOWNLOAD. + 5 + 1 read-only - - - - APB2OTP_BLK8_W11 - eFuse apb2otp block8 data register11. - 0x9A8 - 0x20 - - APB2OTP_BLOCK8_W11 - Otp block8 word11 data. - 0 - 32 + UART_PRINT_CONTROL_ERR + Indicates a programming error of UART_PRINT_CONTROL. + 6 + 2 read-only - - - - APB2OTP_BLK9_W1 - eFuse apb2otp block9 data register1. - 0x9AC - 0x20 - - APB2OTP_BLOCK9_W1 - Otp block9 word1 data. - 0 - 32 + FORCE_SEND_RESUME_ERR + Indicates a programming error of FORCE_SEND_RESUME. + 8 + 1 read-only - - - - APB2OTP_BLK9_W2 - eFuse apb2otp block9 data register2. - 0x9B0 - 0x20 - - APB2OTP_BLOCK9_W2 - Otp block9 word2 data. - 0 - 32 + SECURE_VERSION_ERR + Indicates a programming error of SECURE VERSION. + 9 + 16 read-only - - - - APB2OTP_BLK9_W3 - eFuse apb2otp block9 data register3. - 0x9B4 - 0x20 - - APB2OTP_BLOCK9_W3 - Otp block9 word3 data. - 0 - 32 + SECURE_BOOT_DISABLE_FAST_WAKE_ERR + Indicates a programming error of SECURE_BOOT_DISABLE_FAST_WAKE. + 25 + 1 read-only - - - - APB2OTP_BLK9_W4 - eFuse apb2otp block9 data register4. - 0x9B8 - 0x20 - - APB2OTP_BLOCK9_W4 - Otp block9 word4 data. - 0 - 32 + HYS_EN_PAD_ERR + Indicates a programming error of HYS_EN_PAD. + 26 + 1 read-only - - - - APB2OTP_BLK9_W5 - eFuse apb2otp block9 data register5. - 0x9BC - 0x20 - - APB2OTP_BLOCK9_W5 - Otp block9 word5 data. - 0 - 32 + DCDC_VSET_ERR + Indicates a programming error of DCDC_VSET. + 27 + 5 read-only - APB2OTP_BLK9_W6 - eFuse apb2otp block9 data register6. - 0x9C0 + RD_REPEAT_ERR4 + Programming error record register 4 of BLOCK0. + 0x18C 0x20 - APB2OTP_BLOCK9_W6 - Otp block9 word6 data. + _0PXA_TIEH_SEL_0_ERR + Indicates a programming error of 0PXA_TIEH_SEL_0. 0 - 32 + 2 read-only - - - - APB2OTP_BLK9_W7 - eFuse apb2otp block9 data register7. - 0x9C4 - 0x20 - - APB2OTP_BLOCK9_W7 - Otp block9 word7 data. - 0 - 32 + _0PXA_TIEH_SEL_1_ERR + Indicates a programming error of 0PXA_TIEH_SEL_1. + 2 + 2 read-only - - - - APB2OTP_BLK9_W8 - eFuse apb2otp block9 data register8. - 0x9C8 - 0x20 - - APB2OTP_BLOCK9_W8 - Otp block9 word8 data. - 0 - 32 + _0PXA_TIEH_SEL_2_ERR + Indicates a programming error of 0PXA_TIEH_SEL_2. + 4 + 2 read-only - - - - APB2OTP_BLK9_W9 - eFuse apb2otp block9 data register9. - 0x9CC - 0x20 - - APB2OTP_BLOCK9_W9 - Otp block9 word9 data. - 0 - 32 + _0PXA_TIEH_SEL_3_ERR + Indicates a programming error of 0PXA_TIEH_SEL_3. + 6 + 2 read-only - - - - APB2OTP_BLK9_W10 - eFuse apb2otp block9 data register10. - 0x9D0 - 0x20 - - APB2OTP_BLOCK9_W10 - Otp block9 word10 data. - 0 - 32 + KM_DISABLE_DEPLOY_MODE_ERR + TBD. + 8 + 4 read-only - - - - APB2OTP_BLK9_W11 - eFuse apb2otp block9 data register11. - 0x9D4 - 0x20 - - APB2OTP_BLOCK9_W11 - Otp block9 word11 data. - 0 - 32 + USB_DEVICE_DREFL_ERR + Indicates a programming error of USB_DEVICE_DREFL. + 12 + 2 read-only - - - - APB2OTP_BLK10_W1 - eFuse apb2otp block10 data register1. - 0x9D8 - 0x20 - - APB2OTP_BLOCK10_W1 - Otp block10 word1 data. - 0 - 32 + USB_OTG11_DREFL_ERR + Indicates a programming error of USB_OTG11_DREFL. + 14 + 2 read-only - - - - APB2OTP_BLK10_W2 - eFuse apb2otp block10 data register2. - 0x9DC - 0x20 - - APB2OTP_BLOCK10_W2 - Otp block10 word2 data. - 0 - 32 + HP_PWR_SRC_SEL_ERR + Indicates a programming error of HP_PWR_SRC_SEL. + 18 + 1 + read-only + + + DCDC_VSET_EN_ERR + Indicates a programming error of DCDC_VSET_EN. + 19 + 1 + read-only + + + DIS_WDT_ERR + Indicates a programming error of DIS_WDT. + 20 + 1 + read-only + + + DIS_SWD_ERR + Indicates a programming error of DIS_SWD. + 21 + 1 read-only - APB2OTP_BLK10_W3 - eFuse apb2otp block10 data register3. - 0x9E0 + RD_RS_ERR0 + Programming error record register 0 of BLOCK1-10. + 0x1C0 0x20 - APB2OTP_BLOCK10_W3 - Otp block10 word3 data. + MAC_SYS_ERR_NUM + The value of this signal means the number of error bytes. 0 - 32 + 3 + read-only + + + MAC_SYS_FAIL + 0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that programming user data failed and the number of error bytes is over 6. + 3 + 1 + read-only + + + SYS_PART1_ERR_NUM + The value of this signal means the number of error bytes. + 4 + 3 + read-only + + + SYS_PART1_FAIL + 0: Means no failure and that the data of system part1 is reliable 1: Means that programming user data failed and the number of error bytes is over 6. + 7 + 1 + read-only + + + USR_DATA_ERR_NUM + The value of this signal means the number of error bytes. + 8 + 3 + read-only + + + USR_DATA_FAIL + 0: Means no failure and that the user data is reliable 1: Means that programming user data failed and the number of error bytes is over 6. + 11 + 1 + read-only + + + KEY0_ERR_NUM + The value of this signal means the number of error bytes. + 12 + 3 + read-only + + + KEY0_FAIL + 0: Means no failure and that the data of key0 is reliable 1: Means that programming key0 failed and the number of error bytes is over 6. + 15 + 1 + read-only + + + KEY1_ERR_NUM + The value of this signal means the number of error bytes. + 16 + 3 + read-only + + + KEY1_FAIL + 0: Means no failure and that the data of key1 is reliable 1: Means that programming key1 failed and the number of error bytes is over 6. + 19 + 1 + read-only + + + KEY2_ERR_NUM + The value of this signal means the number of error bytes. + 20 + 3 + read-only + + + KEY2_FAIL + 0: Means no failure and that the data of key2 is reliable 1: Means that programming key2 failed and the number of error bytes is over 6. + 23 + 1 + read-only + + + KEY3_ERR_NUM + The value of this signal means the number of error bytes. + 24 + 3 + read-only + + + KEY3_FAIL + 0: Means no failure and that the data of key3 is reliable 1: Means that programming key3 failed and the number of error bytes is over 6. + 27 + 1 + read-only + + + KEY4_ERR_NUM + The value of this signal means the number of error bytes. + 28 + 3 + read-only + + + KEY4_FAIL + 0: Means no failure and that the data of key4 is reliable 1: Means that programming key4 failed and the number of error bytes is over 6. + 31 + 1 read-only - APB2OTP_BLK10_W4 - eFuse apb2otp block10 data register4. - 0x9E4 + RD_RS_ERR1 + Programming error record register 1 of BLOCK1-10. + 0x1C4 0x20 - APB2OTP_BLOCK10_W4 - Otp block10 word4 data. + KEY5_ERR_NUM + The value of this signal means the number of error bytes. 0 - 32 + 3 + read-only + + + KEY5_FAIL + 0: Means no failure and that the data of key5 is reliable 1: Means that programming key5 failed and the number of error bytes is over 6. + 3 + 1 + read-only + + + SYS_PART2_ERR_NUM + The value of this signal means the number of error bytes. + 4 + 3 + read-only + + + SYS_PART2_FAIL + 0: Means no failure and that the data of system part2 is reliable 1: Means that programming user data failed and the number of error bytes is over 6. + 7 + 1 read-only - APB2OTP_BLK10_W5 - eFuse apb2otp block10 data register5. - 0x9E8 + CLK + eFuse clcok configuration register. + 0x1C8 0x20 - APB2OTP_BLOCK10_W5 - Otp block10 word5 data. + MEM_FORCE_PD + Set this bit to force eFuse SRAM into power-saving mode. 0 - 32 - read-only + 1 + read-write + + + MEM_CLK_FORCE_ON + Set this bit and force to activate clock signal of eFuse SRAM. + 1 + 1 + read-write + + + MEM_FORCE_PU + Set this bit to force eFuse SRAM into working mode. + 2 + 1 + read-write + + + EN + Set this bit to force enable eFuse register configuration clock signal. + 16 + 1 + read-write - APB2OTP_BLK10_W6 - eFuse apb2otp block10 data register6. - 0x9EC + CONF + eFuse operation mode configuraiton register + 0x1CC 0x20 - APB2OTP_BLOCK10_W6 - Otp block10 word6 data. + OP_CODE + 0x5A5A: programming operation command 0x5AA5: read operation command. 0 - 32 - read-only + 16 + read-write + + + CFG_ECDSA_BLK + Configures which block to use for ECDSA key output. + 16 + 4 + read-write - APB2OTP_BLK10_W7 - eFuse apb2otp block10 data register7. - 0x9F0 + STATUS + eFuse status register. + 0x1D0 0x20 - APB2OTP_BLOCK10_W7 - Otp block10 word7 data. + STATE + Indicates the state of the eFuse state machine. 0 - 32 + 4 + read-only + + + OTP_LOAD_SW + The value of OTP_LOAD_SW. + 4 + 1 + read-only + + + OTP_VDDQ_C_SYNC2 + The value of OTP_VDDQ_C_SYNC2. + 5 + 1 + read-only + + + OTP_STROBE_SW + The value of OTP_STROBE_SW. + 6 + 1 + read-only + + + OTP_CSB_SW + The value of OTP_CSB_SW. + 7 + 1 + read-only + + + OTP_PGENB_SW + The value of OTP_PGENB_SW. + 8 + 1 + read-only + + + OTP_VDDQ_IS_SW + The value of OTP_VDDQ_IS_SW. + 9 + 1 + read-only + + + BLK0_VALID_BIT_CNT + Indicates the number of block valid bit. + 10 + 10 + read-only + + + CUR_ECDSA_BLK + Indicates which block is used for ECDSA key output. + 20 + 4 read-only - APB2OTP_BLK10_W8 - eFuse apb2otp block10 data register8. - 0x9F4 + CMD + eFuse command register. + 0x1D4 0x20 - APB2OTP_BLOCK10_W8 - Otp block10 word8 data. + READ_CMD + Set this bit to send read command. 0 - 32 - read-only + 1 + read-write + + + PGM_CMD + Set this bit to send programming command. + 1 + 1 + read-write + + + BLK_NUM + The serial number of the block to be programmed. Value 0-10 corresponds to block number 0-10, respectively. + 2 + 4 + read-write - APB2OTP_BLK10_W9 - eFuse apb2otp block10 data register9. - 0x9F8 + INT_RAW + eFuse raw interrupt register. + 0x1D8 0x20 - APB2OTP_BLOCK10_W9 - Otp block10 word9 data. + READ_DONE_INT_RAW + The raw bit signal for read_done interrupt. 0 - 32 + 1 + read-only + + + PGM_DONE_INT_RAW + The raw bit signal for pgm_done interrupt. + 1 + 1 read-only - APB2OTP_BLK10_W10 - eFuse apb2otp block10 data register10. - 0x9FC + INT_ST + eFuse interrupt status register. + 0x1DC 0x20 - APB2OTP_BLOCK19_W10 - Otp block10 word10 data. + READ_DONE_INT_ST + The status signal for read_done interrupt. 0 - 32 + 1 + read-only + + + PGM_DONE_INT_ST + The status signal for pgm_done interrupt. + 1 + 1 read-only - APB2OTP_BLK10_W11 - eFuse apb2otp block10 data register11. - 0xA00 + INT_ENA + eFuse interrupt enable register. + 0x1E0 0x20 - APB2OTP_BLOCK10_W11 - Otp block10 word11 data. + READ_DONE_INT_ENA + The enable signal for read_done interrupt. 0 - 32 - read-only + 1 + read-write + + + PGM_DONE_INT_ENA + The enable signal for pgm_done interrupt. + 1 + 1 + read-write - APB2OTP_EN - eFuse apb2otp enable configuration register. - 0xA08 + INT_CLR + eFuse interrupt clear register. + 0x1E4 0x20 - APB2OTP_APB2OTP_EN - Apb2otp mode enable signal. + READ_DONE_INT_CLR + The clear signal for read_done interrupt. 0 1 - read-write + write-only + + + PGM_DONE_INT_CLR + The clear signal for pgm_done interrupt. + 1 + 1 + write-only - - - - GPIO - General Purpose Input/Output - GPIO - 0x500E0000 - - 0x0 - 0x5F8 - registers - - - GPIO_INT0 - 74 - - - GPIO_INT1 - 75 - - - GPIO_INT2 - 76 - - - GPIO_INT3 - 77 - - - GPIO_PAD_COMP - 78 - - - BT_SELECT - GPIO bit select register - 0x0 + DAC_CONF + Controls the eFuse programming voltage. + 0x1E8 0x20 + 0x0001FE17 - BT_SEL - GPIO bit select register + DAC_CLK_DIV + Controls the division factor of the rising clock of the programming voltage. 0 - 32 + 8 + read-write + + + DAC_CLK_PAD_SEL + Don't care. + 8 + 1 + read-write + + + DAC_NUM + Controls the rising period of the programming voltage. + 9 + 8 + read-write + + + OE_CLR + Reduces the power supply of the programming voltage. + 17 + 1 read-write - OUT - GPIO output register for GPIO0-31 - 0x4 + RD_TIM_CONF + Configures read timing parameters. + 0x1EC 0x20 + 0x0F010201 - DATA_ORIG - GPIO output register for GPIO0-31 + THR_A + Configures the read hold time. 0 - 32 + 8 + read-write + + + TRD + Configures the read time. + 8 + 8 + read-write + + + TSUR_A + Configures the read setup time. + 16 + 8 + read-write + + + READ_INIT_NUM + Configures the waiting time of reading eFuse memory. + 24 + 8 read-write - OUT_W1TS - GPIO output set register for GPIO0-31 - 0x8 + WR_TIM_CONF1 + Configurarion register 1 of eFuse programming timing parameters. + 0x1F0 0x20 + 0x01266701 - OUT_W1TS - GPIO output set register for GPIO0-31 + TSUP_A + Configures the programming setup time. 0 - 32 - write-only + 8 + read-write + + + PWR_ON_NUM + Configures the power up time for VDDQ. + 8 + 16 + read-write + + + THP_A + Configures the programming hold time. + 24 + 8 + read-write - OUT_W1TC - GPIO output clear register for GPIO0-31 - 0xC + WR_TIM_CONF2 + Configurarion register 2 of eFuse programming timing parameters. + 0x1F4 0x20 + 0x00A00140 - OUT_W1TC - GPIO output clear register for GPIO0-31 + PWR_OFF_NUM + Configures the power outage time for VDDQ. 0 - 32 - write-only + 16 + read-write + + + TPGM + Configures the active programming time. + 16 + 16 + read-write - OUT1 - GPIO output register for GPIO32-56 - 0x10 + WR_TIM_CONF0_RS_BYPASS + Configurarion register0 of eFuse programming time parameters and rs bypass operation. + 0x1F8 0x20 + 0x00002000 - DATA_ORIG - GPIO output register for GPIO32-56 + BYPASS_RS_CORRECTION + Set this bit to bypass reed solomon correction step. 0 - 25 + 1 + read-write + + + BYPASS_RS_BLK_NUM + Configures block number of programming twice operation. + 1 + 11 + read-write + + + UPDATE + Set this bit to update multi-bit register signals. + 12 + 1 + write-only + + + TPGM_INACTIVE + Configures the inactive programming time. + 13 + 8 read-write - OUT1_W1TS - GPIO output set register for GPIO32-56 - 0x14 + DATE + eFuse version register. + 0x1FC 0x20 + 0x02305050 - OUT1_W1TS - GPIO output set register for GPIO32-56 + DATE + Stores eFuse version. 0 - 25 - write-only + 28 + read-write - OUT1_W1TC - GPIO output clear register for GPIO32-56 - 0x18 + APB2OTP_WR_DIS + eFuse apb2otp block0 data register1. + 0x800 0x20 - OUT1_W1TC - GPIO output clear register for GPIO32-56 + APB2OTP_BLOCK0_WR_DIS + Otp block0 write disable data. 0 - 25 - write-only + 32 + read-only - ENABLE - GPIO output enable register for GPIO0-31 - 0x20 + APB2OTP_BLK0_BACKUP1_W1 + eFuse apb2otp block0 data register2. + 0x804 0x20 - DATA - GPIO output enable register for GPIO0-31 + APB2OTP_BLOCK0_BACKUP1_W1 + Otp block0 backup1 word1 data. 0 32 - read-write + read-only - ENABLE_W1TS - GPIO output enable set register for GPIO0-31 - 0x24 + APB2OTP_BLK0_BACKUP1_W2 + eFuse apb2otp block0 data register3. + 0x808 0x20 - ENABLE_W1TS - GPIO output enable set register for GPIO0-31 + APB2OTP_BLOCK0_BACKUP1_W2 + Otp block0 backup1 word2 data. 0 32 - write-only + read-only - ENABLE_W1TC - GPIO output enable clear register for GPIO0-31 - 0x28 + APB2OTP_BLK0_BACKUP1_W3 + eFuse apb2otp block0 data register4. + 0x80C 0x20 - ENABLE_W1TC - GPIO output enable clear register for GPIO0-31 + APB2OTP_BLOCK0_BACKUP1_W3 + Otp block0 backup1 word3 data. 0 32 - write-only + read-only - ENABLE1 - GPIO output enable register for GPIO32-56 - 0x2C + APB2OTP_BLK0_BACKUP1_W4 + eFuse apb2otp block0 data register5. + 0x810 0x20 - DATA - GPIO output enable register for GPIO32-56 + APB2OTP_BLOCK0_BACKUP1_W4 + Otp block0 backup1 word4 data. 0 - 25 - read-write + 32 + read-only - ENABLE1_W1TS - GPIO output enable set register for GPIO32-56 - 0x30 + APB2OTP_BLK0_BACKUP1_W5 + eFuse apb2otp block0 data register6. + 0x814 0x20 - ENABLE1_W1TS - GPIO output enable set register for GPIO32-56 + APB2OTP_BLOCK0_BACKUP1_W5 + Otp block0 backup1 word5 data. 0 - 25 - write-only + 32 + read-only - ENABLE1_W1TC - GPIO output enable clear register for GPIO32-56 - 0x34 + APB2OTP_BLK0_BACKUP2_W1 + eFuse apb2otp block0 data register7. + 0x818 0x20 - ENABLE1_W1TC - GPIO output enable clear register for GPIO32-56 + APB2OTP_BLOCK0_BACKUP2_W1 + Otp block0 backup2 word1 data. 0 - 25 - write-only + 32 + read-only - STRAP - pad strapping register - 0x38 + APB2OTP_BLK0_BACKUP2_W2 + eFuse apb2otp block0 data register8. + 0x81C 0x20 - STRAPPING - pad strapping register + APB2OTP_BLOCK0_BACKUP2_W2 + Otp block0 backup2 word2 data. 0 - 16 + 32 read-only - IN - GPIO input register for GPIO0-31 - 0x3C + APB2OTP_BLK0_BACKUP2_W3 + eFuse apb2otp block0 data register9. + 0x820 0x20 - DATA_NEXT - GPIO input register for GPIO0-31 + APB2OTP_BLOCK0_BACKUP2_W3 + Otp block0 backup2 word3 data. 0 32 read-only @@ -37386,119 +37133,119 @@ - IN1 - GPIO input register for GPIO32-56 - 0x40 + APB2OTP_BLK0_BACKUP2_W4 + eFuse apb2otp block0 data register10. + 0x824 0x20 - DATA_NEXT - GPIO input register for GPIO32-56 + APB2OTP_BLOCK0_BACKUP2_W4 + Otp block0 backup2 word4 data. 0 - 25 + 32 read-only - STATUS - GPIO interrupt status register for GPIO0-31 - 0x44 + APB2OTP_BLK0_BACKUP2_W5 + eFuse apb2otp block0 data register11. + 0x828 0x20 - INTERRUPT - GPIO interrupt status register for GPIO0-31 + APB2OTP_BLOCK0_BACKUP2_W5 + Otp block0 backup2 word5 data. 0 32 - read-write + read-only - STATUS_W1TS - GPIO interrupt status set register for GPIO0-31 - 0x48 + APB2OTP_BLK0_BACKUP3_W1 + eFuse apb2otp block0 data register12. + 0x82C 0x20 - STATUS_W1TS - GPIO interrupt status set register for GPIO0-31 + APB2OTP_BLOCK0_BACKUP3_W1 + Otp block0 backup3 word1 data. 0 32 - write-only + read-only - STATUS_W1TC - GPIO interrupt status clear register for GPIO0-31 - 0x4C + APB2OTP_BLK0_BACKUP3_W2 + eFuse apb2otp block0 data register13. + 0x830 0x20 - STATUS_W1TC - GPIO interrupt status clear register for GPIO0-31 + APB2OTP_BLOCK0_BACKUP3_W2 + Otp block0 backup3 word2 data. 0 32 - write-only + read-only - STATUS1 - GPIO interrupt status register for GPIO32-56 - 0x50 + APB2OTP_BLK0_BACKUP3_W3 + eFuse apb2otp block0 data register14. + 0x834 0x20 - INTERRUPT - GPIO interrupt status register for GPIO32-56 + APB2OTP_BLOCK0_BACKUP3_W3 + Otp block0 backup3 word3 data. 0 - 25 - read-write + 32 + read-only - STATUS1_W1TS - GPIO interrupt status set register for GPIO32-56 - 0x54 + APB2OTP_BLK0_BACKUP3_W4 + eFuse apb2otp block0 data register15. + 0x838 0x20 - STATUS1_W1TS - GPIO interrupt status set register for GPIO32-56 + APB2OTP_BLOCK0_BACKUP3_W4 + Otp block0 backup3 word4 data. 0 - 25 - write-only + 32 + read-only - STATUS1_W1TC - GPIO interrupt status clear register for GPIO32-56 - 0x58 + APB2OTP_BLK0_BACKUP3_W5 + eFuse apb2otp block0 data register16. + 0x83C 0x20 - STATUS1_W1TC - GPIO interrupt status clear register for GPIO32-56 + APB2OTP_BLOCK0_BACKUP3_W5 + Otp block0 backup3 word5 data. 0 - 25 - write-only + 32 + read-only - INTR_0 - GPIO interrupt 0 status register for GPIO0-31 - 0x5C + APB2OTP_BLK0_BACKUP4_W1 + eFuse apb2otp block0 data register17. + 0x840 0x20 - INT_0 - GPIO interrupt 0 status register for GPIO0-31 + APB2OTP_BLOCK0_BACKUP4_W1 + Otp block0 backup4 word1 data. 0 32 read-only @@ -37506,29 +37253,29 @@ - INTR1_0 - GPIO interrupt 0 status register for GPIO32-56 - 0x60 + APB2OTP_BLK0_BACKUP4_W2 + eFuse apb2otp block0 data register18. + 0x844 0x20 - INT1_0 - GPIO interrupt 0 status register for GPIO32-56 + APB2OTP_BLOCK0_BACKUP4_W2 + Otp block0 backup4 word2 data. 0 - 25 + 32 read-only - INTR_1 - GPIO interrupt 1 status register for GPIO0-31 - 0x64 + APB2OTP_BLK0_BACKUP4_W3 + eFuse apb2otp block0 data register19. + 0x848 0x20 - INT_1 - GPIO interrupt 1 status register for GPIO0-31 + APB2OTP_BLOCK0_BACKUP4_W3 + Otp block0 backup4 word3 data. 0 32 read-only @@ -37536,29 +37283,29 @@ - INTR1_1 - GPIO interrupt 1 status register for GPIO32-56 - 0x68 + APB2OTP_BLK0_BACKUP4_W4 + eFuse apb2otp block0 data register20. + 0x84C 0x20 - INT1_1 - GPIO interrupt 1 status register for GPIO32-56 + APB2OTP_BLOCK0_BACKUP4_W4 + Otp block0 backup4 word4 data. 0 - 25 + 32 read-only - STATUS_NEXT - GPIO interrupt source register for GPIO0-31 - 0x6C + APB2OTP_BLK0_BACKUP4_W5 + eFuse apb2otp block0 data register21. + 0x850 0x20 - STATUS_INTERRUPT_NEXT - GPIO interrupt source register for GPIO0-31 + APB2OTP_BLOCK0_BACKUP4_W5 + Otp block0 backup4 word5 data. 0 32 read-only @@ -37566,4213 +37313,2325 @@ - STATUS_NEXT1 - GPIO interrupt source register for GPIO32-56 - 0x70 + APB2OTP_BLK1_W1 + eFuse apb2otp block1 data register1. + 0x854 0x20 - STATUS_INTERRUPT_NEXT1 - GPIO interrupt source register for GPIO32-56 + APB2OTP_BLOCK1_W1 + Otp block1 word1 data. 0 - 25 + 32 read-only - 57 - 0x4 - PIN%s - GPIO pin configuration register - 0x74 + APB2OTP_BLK1_W2 + eFuse apb2otp block1 data register2. + 0x858 0x20 - SYNC2_BYPASS - set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge. + APB2OTP_BLOCK1_W2 + Otp block1 word2 data. 0 - 2 - read-write - - - PAD_DRIVER - set this bit to select pad driver. 1:open-drain. 0:normal. - 2 - 1 - read-write - - - SYNC1_BYPASS - set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge. - 3 - 2 - read-write - - - INT_TYPE - set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid at high level - 7 - 3 - read-write - - - WAKEUP_ENABLE - set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - 10 - 1 - read-write - - - CONFIG - reserved - 11 - 2 - read-write - - - INT_ENA - set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) interrupt. - 13 - 5 - read-write + 32 + read-only - FUNC1_IN_SEL_CFG - GPIO input function configuration register - 0x15C + APB2OTP_BLK1_W3 + eFuse apb2otp block1 data register3. + 0x85C 0x20 - 0x0000003F - FUNC1_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK1_W3 + Otp block1 word3 data. 0 - 6 - read-write - - - FUNC1_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG1_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC2_IN_SEL_CFG - GPIO input function configuration register - 0x160 + APB2OTP_BLK1_W4 + eFuse apb2otp block1 data register4. + 0x860 0x20 - 0x0000003F - FUNC2_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK1_W4 + Otp block1 word4 data. 0 - 6 - read-write - - - FUNC2_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG2_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC3_IN_SEL_CFG - GPIO input function configuration register - 0x164 + APB2OTP_BLK1_W5 + eFuse apb2otp block1 data register5. + 0x864 0x20 - 0x0000003F - FUNC3_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK1_W5 + Otp block1 word5 data. 0 - 6 - read-write - - - FUNC3_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG3_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC4_IN_SEL_CFG - GPIO input function configuration register - 0x168 + APB2OTP_BLK1_W6 + eFuse apb2otp block1 data register6. + 0x868 0x20 - 0x0000003F - FUNC4_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK1_W6 + Otp block1 word6 data. 0 - 6 - read-write - - - FUNC4_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG4_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC5_IN_SEL_CFG - GPIO input function configuration register - 0x16C + APB2OTP_BLK1_W7 + eFuse apb2otp block1 data register7. + 0x86C 0x20 - 0x0000003F - FUNC5_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK1_W7 + Otp block1 word7 data. 0 - 6 - read-write - - - FUNC5_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG5_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC6_IN_SEL_CFG - GPIO input function configuration register - 0x170 + APB2OTP_BLK1_W8 + eFuse apb2otp block1 data register8. + 0x870 0x20 - 0x0000003F - FUNC6_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK1_W8 + Otp block1 word8 data. 0 - 6 - read-write - - - FUNC6_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG6_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC7_IN_SEL_CFG - GPIO input function configuration register - 0x174 + APB2OTP_BLK1_W9 + eFuse apb2otp block1 data register9. + 0x874 0x20 - 0x0000003F - FUNC7_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK1_W9 + Otp block1 word9 data. 0 - 6 - read-write - - - FUNC7_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG7_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC8_IN_SEL_CFG - GPIO input function configuration register - 0x178 + APB2OTP_BLK2_W1 + eFuse apb2otp block2 data register1. + 0x878 0x20 - 0x0000003F - FUNC8_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK2_W1 + Otp block2 word1 data. 0 - 6 - read-write - - - FUNC8_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG8_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC9_IN_SEL_CFG - GPIO input function configuration register - 0x17C + APB2OTP_BLK2_W2 + eFuse apb2otp block2 data register2. + 0x87C 0x20 - 0x0000003F - FUNC9_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK2_W2 + Otp block2 word2 data. 0 - 6 - read-write - - - FUNC9_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG9_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC10_IN_SEL_CFG - GPIO input function configuration register - 0x180 + APB2OTP_BLK2_W3 + eFuse apb2otp block2 data register3. + 0x880 0x20 - 0x0000003E - FUNC10_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK2_W3 + Otp block2 word3 data. 0 - 6 - read-write - - - FUNC10_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG10_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC11_IN_SEL_CFG - GPIO input function configuration register - 0x184 + APB2OTP_BLK2_W4 + eFuse apb2otp block2 data register4. + 0x884 0x20 - 0x0000003E - FUNC11_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK2_W4 + Otp block2 word4 data. 0 - 6 - read-write - - - FUNC11_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG11_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC12_IN_SEL_CFG - GPIO input function configuration register - 0x188 + APB2OTP_BLK2_W5 + eFuse apb2otp block2 data register5. + 0x888 0x20 - 0x0000003E - FUNC12_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK2_W5 + Otp block2 word5 data. 0 - 6 - read-write - - - FUNC12_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG12_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC13_IN_SEL_CFG - GPIO input function configuration register - 0x18C + APB2OTP_BLK2_W6 + eFuse apb2otp block2 data register6. + 0x88C 0x20 - 0x0000003E - FUNC13_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK2_W6 + Otp block2 word6 data. 0 - 6 - read-write - - - FUNC13_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG13_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC14_IN_SEL_CFG - GPIO input function configuration register - 0x190 + APB2OTP_BLK2_W7 + eFuse apb2otp block2 data register7. + 0x890 0x20 - 0x0000003E - FUNC14_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK2_W7 + Otp block2 word7 data. 0 - 6 - read-write - - - FUNC14_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG14_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC15_IN_SEL_CFG - GPIO input function configuration register - 0x194 + APB2OTP_BLK2_W8 + eFuse apb2otp block2 data register8. + 0x894 0x20 - 0x0000003E - FUNC15_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK2_W8 + Otp block2 word8 data. 0 - 6 - read-write - - - FUNC15_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG15_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC16_IN_SEL_CFG - GPIO input function configuration register - 0x198 + APB2OTP_BLK2_W9 + eFuse apb2otp block2 data register9. + 0x898 0x20 - 0x0000003E - FUNC16_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK2_W9 + Otp block2 word9 data. 0 - 6 - read-write - - - FUNC16_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG16_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC17_IN_SEL_CFG - GPIO input function configuration register - 0x19C + APB2OTP_BLK2_W10 + eFuse apb2otp block2 data register10. + 0x89C 0x20 - 0x0000003E - FUNC17_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK2_W10 + Otp block2 word10 data. 0 - 6 - read-write - - - FUNC17_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG17_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC18_IN_SEL_CFG - GPIO input function configuration register - 0x1A0 + APB2OTP_BLK2_W11 + eFuse apb2otp block2 data register11. + 0x8A0 0x20 - 0x0000003E - FUNC18_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK2_W11 + Otp block2 word11 data. 0 - 6 - read-write - - - FUNC18_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG18_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC19_IN_SEL_CFG - GPIO input function configuration register - 0x1A4 + APB2OTP_BLK3_W1 + eFuse apb2otp block3 data register1. + 0x8A4 0x20 - 0x0000003E - FUNC19_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK3_W1 + Otp block3 word1 data. 0 - 6 - read-write - - - FUNC19_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG19_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC20_IN_SEL_CFG - GPIO input function configuration register - 0x1A8 + APB2OTP_BLK3_W2 + eFuse apb2otp block3 data register2. + 0x8A8 0x20 - 0x0000003E - FUNC20_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK3_W2 + Otp block3 word2 data. 0 - 6 - read-write - - - FUNC20_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG20_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC21_IN_SEL_CFG - GPIO input function configuration register - 0x1AC + APB2OTP_BLK3_W3 + eFuse apb2otp block3 data register3. + 0x8AC 0x20 - 0x0000003E - FUNC21_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK3_W3 + Otp block3 word3 data. 0 - 6 - read-write - - - FUNC21_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG21_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC22_IN_SEL_CFG - GPIO input function configuration register - 0x1B0 + APB2OTP_BLK3_W4 + eFuse apb2otp block3 data register4. + 0x8B0 0x20 - 0x0000003E - FUNC22_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK3_W4 + Otp block3 word4 data. 0 - 6 - read-write - - - FUNC22_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG22_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC23_IN_SEL_CFG - GPIO input function configuration register - 0x1B4 + APB2OTP_BLK3_W5 + eFuse apb2otp block3 data register5. + 0x8B4 0x20 - 0x0000003E - FUNC23_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK3_W5 + Otp block3 word5 data. 0 - 6 - read-write - - - FUNC23_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG23_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC24_IN_SEL_CFG - GPIO input function configuration register - 0x1B8 + APB2OTP_BLK3_W6 + eFuse apb2otp block3 data register6. + 0x8B8 0x20 - 0x0000003E - FUNC24_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK3_W6 + Otp block3 word6 data. 0 - 6 - read-write - - - FUNC24_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG24_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC25_IN_SEL_CFG - GPIO input function configuration register - 0x1BC + APB2OTP_BLK3_W7 + eFuse apb2otp block3 data register7. + 0x8BC 0x20 - 0x0000003E - FUNC25_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK3_W7 + Otp block3 word7 data. 0 - 6 - read-write - - - FUNC25_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG25_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC26_IN_SEL_CFG - GPIO input function configuration register - 0x1C0 + APB2OTP_BLK3_W8 + eFuse apb2otp block3 data register8. + 0x8C0 0x20 - 0x0000003E - FUNC26_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK3_W8 + Otp block3 word8 data. 0 - 6 - read-write - - - FUNC26_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG26_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC27_IN_SEL_CFG - GPIO input function configuration register - 0x1C4 + APB2OTP_BLK3_W9 + eFuse apb2otp block3 data register9. + 0x8C4 0x20 - 0x0000003E - FUNC27_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK3_W9 + Otp block3 word9 data. 0 - 6 - read-write - - - FUNC27_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG27_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC28_IN_SEL_CFG - GPIO input function configuration register - 0x1C8 + APB2OTP_BLK3_W10 + eFuse apb2otp block3 data register10. + 0x8C8 0x20 - 0x0000003E - FUNC28_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK3_W10 + Otp block3 word10 data. 0 - 6 - read-write - - - FUNC28_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG28_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC29_IN_SEL_CFG - GPIO input function configuration register - 0x1CC + APB2OTP_BLK3_W11 + eFuse apb2otp block3 data register11. + 0x8CC 0x20 - 0x0000003E - FUNC29_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK3_W11 + Otp block3 word11 data. 0 - 6 - read-write - - - FUNC29_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG29_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC30_IN_SEL_CFG - GPIO input function configuration register - 0x1D0 + APB2OTP_BLK4_W1 + eFuse apb2otp block4 data register1. + 0x8D0 0x20 - 0x0000003E - FUNC30_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK4_W1 + Otp block4 word1 data. 0 - 6 - read-write - - - FUNC30_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG30_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC31_IN_SEL_CFG - GPIO input function configuration register - 0x1D4 + APB2OTP_BLK4_W2 + eFuse apb2otp block4 data register2. + 0x8D4 0x20 - 0x0000003E - FUNC31_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK4_W2 + Otp block4 word2 data. 0 - 6 - read-write - - - FUNC31_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG31_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC32_IN_SEL_CFG - GPIO input function configuration register - 0x1D8 + APB2OTP_BLK4_W3 + eFuse apb2otp block4 data register3. + 0x8D8 0x20 - 0x0000003E - FUNC32_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK4_W3 + Otp block4 word3 data. 0 - 6 - read-write - - - FUNC32_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG32_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC33_IN_SEL_CFG - GPIO input function configuration register - 0x1DC + APB2OTP_BLK4_W4 + eFuse apb2otp block4 data register4. + 0x8DC 0x20 - 0x0000003E - FUNC33_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK4_W4 + Otp block4 word4 data. 0 - 6 - read-write - - - FUNC33_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG33_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC34_IN_SEL_CFG - GPIO input function configuration register - 0x1E0 + APB2OTP_BLK4_W5 + eFuse apb2otp block4 data register5. + 0x8E0 0x20 - 0x0000003E - FUNC34_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK4_W5 + Otp block4 word5 data. 0 - 6 - read-write - - - FUNC34_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG34_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC35_IN_SEL_CFG - GPIO input function configuration register - 0x1E4 + APB2OTP_BLK4_W6 + eFuse apb2otp block4 data register6. + 0x8E4 0x20 - 0x0000003E - FUNC35_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK4_W6 + Otp block4 word6 data. 0 - 6 - read-write - - - FUNC35_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG35_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC36_IN_SEL_CFG - GPIO input function configuration register - 0x1E8 + APB2OTP_BLK4_W7 + eFuse apb2otp block4 data register7. + 0x8E8 0x20 - 0x0000003E - FUNC36_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK4_W7 + Otp block4 word7 data. 0 - 6 - read-write - - - FUNC36_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG36_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC37_IN_SEL_CFG - GPIO input function configuration register - 0x1EC + APB2OTP_BLK4_W8 + eFuse apb2otp block4 data register8. + 0x8EC 0x20 - 0x0000003E - FUNC37_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK4_W8 + Otp block4 word8 data. 0 - 6 - read-write - - - FUNC37_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG37_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC38_IN_SEL_CFG - GPIO input function configuration register - 0x1F0 + APB2OTP_BLK4_W9 + eFuse apb2otp block4 data register9. + 0x8F0 0x20 - 0x0000003E - FUNC38_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK4_W9 + Otp block4 word9 data. 0 - 6 - read-write - - - FUNC38_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG38_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC39_IN_SEL_CFG - GPIO input function configuration register - 0x1F4 + APB2OTP_BLK4_W10 + eFuse apb2otp block4 data registe10. + 0x8F4 0x20 - 0x0000003E - FUNC39_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK4_W10 + Otp block4 word10 data. 0 - 6 - read-write - - - FUNC39_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG39_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC40_IN_SEL_CFG - GPIO input function configuration register - 0x1F8 + APB2OTP_BLK4_W11 + eFuse apb2otp block4 data register11. + 0x8F8 0x20 - 0x0000003E - FUNC40_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK4_W11 + Otp block4 word11 data. 0 - 6 - read-write - - - FUNC40_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG40_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC41_IN_SEL_CFG - GPIO input function configuration register - 0x1FC + APB2OTP_BLK5_W1 + eFuse apb2otp block5 data register1. + 0x8FC 0x20 - 0x0000003E - FUNC41_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK5_W1 + Otp block5 word1 data. 0 - 6 - read-write - - - FUNC41_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG41_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC42_IN_SEL_CFG - GPIO input function configuration register - 0x200 + APB2OTP_BLK5_W2 + eFuse apb2otp block5 data register2. + 0x900 0x20 - 0x0000003E - FUNC42_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK5_W2 + Otp block5 word2 data. 0 - 6 - read-write - - - FUNC42_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG42_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC43_IN_SEL_CFG - GPIO input function configuration register - 0x204 + APB2OTP_BLK5_W3 + eFuse apb2otp block5 data register3. + 0x904 0x20 - 0x0000003E - FUNC43_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK5_W3 + Otp block5 word3 data. 0 - 6 - read-write - - - FUNC43_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG43_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC44_IN_SEL_CFG - GPIO input function configuration register - 0x208 + APB2OTP_BLK5_W4 + eFuse apb2otp block5 data register4. + 0x908 0x20 - 0x0000003E - FUNC44_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK5_W4 + Otp block5 word4 data. 0 - 6 - read-write - - - FUNC44_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG44_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC45_IN_SEL_CFG - GPIO input function configuration register - 0x20C + APB2OTP_BLK5_W5 + eFuse apb2otp block5 data register5. + 0x90C 0x20 - 0x0000003E - FUNC45_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK5_W5 + Otp block5 word5 data. 0 - 6 - read-write - - - FUNC45_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG45_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC47_IN_SEL_CFG - GPIO input function configuration register - 0x214 + APB2OTP_BLK5_W6 + eFuse apb2otp block5 data register6. + 0x910 0x20 - 0x0000003E - FUNC47_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK5_W6 + Otp block5 word6 data. 0 - 6 - read-write - - - FUNC47_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG47_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC48_IN_SEL_CFG - GPIO input function configuration register - 0x218 + APB2OTP_BLK5_W7 + eFuse apb2otp block5 data register7. + 0x914 0x20 - 0x0000003E - FUNC48_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK5_W7 + Otp block5 word7 data. 0 - 6 - read-write - - - FUNC48_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG48_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC49_IN_SEL_CFG - GPIO input function configuration register - 0x21C + APB2OTP_BLK5_W8 + eFuse apb2otp block5 data register8. + 0x918 0x20 - 0x0000003E - FUNC49_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK5_W8 + Otp block5 word8 data. 0 - 6 - read-write - - - FUNC49_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG49_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC50_IN_SEL_CFG - GPIO input function configuration register - 0x220 + APB2OTP_BLK5_W9 + eFuse apb2otp block5 data register9. + 0x91C 0x20 - 0x0000003E - FUNC50_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK5_W9 + Otp block5 word9 data. 0 - 6 - read-write - - - FUNC50_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG50_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC51_IN_SEL_CFG - GPIO input function configuration register - 0x224 + APB2OTP_BLK5_W10 + eFuse apb2otp block5 data register10. + 0x920 0x20 - 0x0000003E - FUNC51_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK5_W10 + Otp block5 word10 data. 0 - 6 - read-write - - - FUNC51_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG51_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC52_IN_SEL_CFG - GPIO input function configuration register - 0x228 + APB2OTP_BLK5_W11 + eFuse apb2otp block5 data register11. + 0x924 0x20 - 0x0000003E - FUNC52_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK5_W11 + Otp block5 word11 data. 0 - 6 - read-write - - - FUNC52_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG52_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC53_IN_SEL_CFG - GPIO input function configuration register - 0x22C + APB2OTP_BLK6_W1 + eFuse apb2otp block6 data register1. + 0x928 0x20 - 0x0000003E - FUNC53_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK6_W1 + Otp block6 word1 data. 0 - 6 - read-write - - - FUNC53_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG53_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC54_IN_SEL_CFG - GPIO input function configuration register - 0x230 + APB2OTP_BLK6_W2 + eFuse apb2otp block6 data register2. + 0x92C 0x20 - 0x0000003E - FUNC54_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK6_W2 + Otp block6 word2 data. 0 - 6 - read-write - - - FUNC54_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG54_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC55_IN_SEL_CFG - GPIO input function configuration register - 0x234 + APB2OTP_BLK6_W3 + eFuse apb2otp block6 data register3. + 0x930 0x20 - 0x0000003E - FUNC55_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK6_W3 + Otp block6 word3 data. 0 - 6 - read-write - - - FUNC55_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG55_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC56_IN_SEL_CFG - GPIO input function configuration register - 0x238 + APB2OTP_BLK6_W4 + eFuse apb2otp block6 data register4. + 0x934 0x20 - 0x0000003E - FUNC56_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK6_W4 + Otp block6 word4 data. 0 - 6 - read-write - - - FUNC56_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG56_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC57_IN_SEL_CFG - GPIO input function configuration register - 0x23C + APB2OTP_BLK6_W5 + eFuse apb2otp block6 data register5. + 0x938 0x20 - 0x0000003E - FUNC57_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK6_W5 + Otp block6 word5 data. 0 - 6 - read-write - - - FUNC57_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG57_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC58_IN_SEL_CFG - GPIO input function configuration register - 0x240 + APB2OTP_BLK6_W6 + eFuse apb2otp block6 data register6. + 0x93C 0x20 - 0x0000003E - FUNC58_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK6_W6 + Otp block6 word6 data. 0 - 6 - read-write - - - FUNC58_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG58_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC59_IN_SEL_CFG - GPIO input function configuration register - 0x244 + APB2OTP_BLK6_W7 + eFuse apb2otp block6 data register7. + 0x940 0x20 - 0x0000003E - FUNC59_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK6_W7 + Otp block6 word7 data. 0 - 6 - read-write - - - FUNC59_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG59_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC60_IN_SEL_CFG - GPIO input function configuration register - 0x248 + APB2OTP_BLK6_W8 + eFuse apb2otp block6 data register8. + 0x944 0x20 - 0x0000003E - FUNC60_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK6_W8 + Otp block6 word8 data. 0 - 6 - read-write - - - FUNC60_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG60_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC61_IN_SEL_CFG - GPIO input function configuration register - 0x24C + APB2OTP_BLK6_W9 + eFuse apb2otp block6 data register9. + 0x948 0x20 - 0x0000003E - FUNC61_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK6_W9 + Otp block6 word9 data. 0 - 6 - read-write - - - FUNC61_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG61_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC62_IN_SEL_CFG - GPIO input function configuration register - 0x250 + APB2OTP_BLK6_W10 + eFuse apb2otp block6 data register10. + 0x94C 0x20 - 0x0000003E - FUNC62_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK6_W10 + Otp block6 word10 data. 0 - 6 - read-write - - - FUNC62_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG62_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC63_IN_SEL_CFG - GPIO input function configuration register - 0x254 + APB2OTP_BLK6_W11 + eFuse apb2otp block6 data register11. + 0x950 0x20 - 0x0000003E - FUNC63_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK6_W11 + Otp block6 word11 data. 0 - 6 - read-write - - - FUNC63_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG63_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC64_IN_SEL_CFG - GPIO input function configuration register - 0x258 + APB2OTP_BLK7_W1 + eFuse apb2otp block7 data register1. + 0x954 0x20 - 0x0000003E - FUNC64_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK7_W1 + Otp block7 word1 data. 0 - 6 - read-write - - - FUNC64_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG64_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC65_IN_SEL_CFG - GPIO input function configuration register - 0x25C + APB2OTP_BLK7_W2 + eFuse apb2otp block7 data register2. + 0x958 0x20 - 0x0000003E - FUNC65_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK7_W2 + Otp block7 word2 data. 0 - 6 - read-write - - - FUNC65_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG65_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC66_IN_SEL_CFG - GPIO input function configuration register - 0x260 + APB2OTP_BLK7_W3 + eFuse apb2otp block7 data register3. + 0x95C 0x20 - 0x0000003E - FUNC66_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK7_W3 + Otp block7 word3 data. 0 - 6 - read-write - - - FUNC66_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG66_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC68_IN_SEL_CFG - GPIO input function configuration register - 0x268 + APB2OTP_BLK7_W4 + eFuse apb2otp block7 data register4. + 0x960 0x20 - 0x0000003F - FUNC68_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK7_W4 + Otp block7 word4 data. 0 - 6 - read-write - - - FUNC68_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG68_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC69_IN_SEL_CFG - GPIO input function configuration register - 0x26C + APB2OTP_BLK7_W5 + eFuse apb2otp block7 data register5. + 0x964 0x20 - 0x0000003F - FUNC69_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK7_W5 + Otp block7 word5 data. 0 - 6 - read-write - - - FUNC69_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG69_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC70_IN_SEL_CFG - GPIO input function configuration register - 0x270 + APB2OTP_BLK7_W6 + eFuse apb2otp block7 data register6. + 0x968 0x20 - 0x0000003F - FUNC70_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK7_W6 + Otp block7 word6 data. 0 - 6 - read-write - - - FUNC70_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG70_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC71_IN_SEL_CFG - GPIO input function configuration register - 0x274 + APB2OTP_BLK7_W7 + eFuse apb2otp block7 data register7. + 0x96C 0x20 - 0x0000003F - FUNC71_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK7_W7 + Otp block7 word7 data. 0 - 6 - read-write - - - FUNC71_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG71_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC74_IN_SEL_CFG - GPIO input function configuration register - 0x280 + APB2OTP_BLK7_W8 + eFuse apb2otp block7 data register8. + 0x970 0x20 - 0x0000003E - FUNC74_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK7_W8 + Otp block7 word8 data. 0 - 6 - read-write - - - FUNC74_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG74_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC75_IN_SEL_CFG - GPIO input function configuration register - 0x284 + APB2OTP_BLK7_W9 + eFuse apb2otp block7 data register9. + 0x974 0x20 - 0x0000003E - FUNC75_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK7_W9 + Otp block7 word9 data. 0 - 6 - read-write - - - FUNC75_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG75_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC76_IN_SEL_CFG - GPIO input function configuration register - 0x288 + APB2OTP_BLK7_W10 + eFuse apb2otp block7 data register10. + 0x978 0x20 - 0x0000003E - FUNC76_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK7_W10 + Otp block7 word10 data. 0 - 6 - read-write - - - FUNC76_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG76_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC77_IN_SEL_CFG - GPIO input function configuration register - 0x28C + APB2OTP_BLK7_W11 + eFuse apb2otp block7 data register11. + 0x97C 0x20 - 0x0000003E - FUNC77_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK7_W11 + Otp block7 word11 data. 0 - 6 - read-write - - - FUNC77_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG77_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC78_IN_SEL_CFG - GPIO input function configuration register - 0x290 + APB2OTP_BLK8_W1 + eFuse apb2otp block8 data register1. + 0x980 0x20 - 0x0000003E - FUNC78_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK8_W1 + Otp block8 word1 data. 0 - 6 - read-write - - - FUNC78_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG78_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC80_IN_SEL_CFG - GPIO input function configuration register - 0x298 + APB2OTP_BLK8_W2 + eFuse apb2otp block8 data register2. + 0x984 0x20 - 0x0000003F - FUNC80_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK8_W2 + Otp block8 word2 data. 0 - 6 - read-write - - - FUNC80_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG80_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC83_IN_SEL_CFG - GPIO input function configuration register - 0x2A4 + APB2OTP_BLK8_W3 + eFuse apb2otp block8 data register3. + 0x988 0x20 - 0x0000003F - FUNC83_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK8_W3 + Otp block8 word3 data. 0 - 6 - read-write - - - FUNC83_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG83_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC86_IN_SEL_CFG - GPIO input function configuration register - 0x2B0 + APB2OTP_BLK8_W4 + eFuse apb2otp block8 data register4. + 0x98C 0x20 - 0x0000003F - FUNC86_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK8_W4 + Otp block8 word4 data. 0 - 6 - read-write - - - FUNC86_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG86_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC89_IN_SEL_CFG - GPIO input function configuration register - 0x2BC + APB2OTP_BLK8_W5 + eFuse apb2otp block8 data register5. + 0x990 0x20 - 0x0000003E - FUNC89_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK8_W5 + Otp block8 word5 data. 0 - 6 - read-write - - - FUNC89_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG89_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC90_IN_SEL_CFG - GPIO input function configuration register - 0x2C0 + APB2OTP_BLK8_W6 + eFuse apb2otp block8 data register6. + 0x994 0x20 - 0x0000003E - FUNC90_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK8_W6 + Otp block8 word6 data. 0 - 6 - read-write - - - FUNC90_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG90_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC91_IN_SEL_CFG - GPIO input function configuration register - 0x2C4 + APB2OTP_BLK8_W7 + eFuse apb2otp block8 data register7. + 0x998 0x20 - 0x0000003E - FUNC91_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK8_W7 + Otp block8 word7 data. 0 - 6 - read-write - - - FUNC91_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG91_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC92_IN_SEL_CFG - GPIO input function configuration register - 0x2C8 + APB2OTP_BLK8_W8 + eFuse apb2otp block8 data register8. + 0x99C 0x20 - 0x0000003E - FUNC92_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK8_W8 + Otp block8 word8 data. 0 - 6 - read-write - - - FUNC92_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG92_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC93_IN_SEL_CFG - GPIO input function configuration register - 0x2CC + APB2OTP_BLK8_W9 + eFuse apb2otp block8 data register9. + 0x9A0 0x20 - 0x0000003E - FUNC93_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK8_W9 + Otp block8 word9 data. 0 - 6 - read-write - - - FUNC93_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG93_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC94_IN_SEL_CFG - GPIO input function configuration register - 0x2D0 + APB2OTP_BLK8_W10 + eFuse apb2otp block8 data register10. + 0x9A4 0x20 - 0x0000003E - FUNC94_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK8_W10 + Otp block8 word10 data. 0 - 6 - read-write - - - FUNC94_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG94_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC95_IN_SEL_CFG - GPIO input function configuration register - 0x2D4 + APB2OTP_BLK8_W11 + eFuse apb2otp block8 data register11. + 0x9A8 0x20 - 0x0000003E - FUNC95_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK8_W11 + Otp block8 word11 data. 0 - 6 - read-write - - - FUNC95_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG95_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC96_IN_SEL_CFG - GPIO input function configuration register - 0x2D8 + APB2OTP_BLK9_W1 + eFuse apb2otp block9 data register1. + 0x9AC 0x20 - 0x0000003E - FUNC96_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK9_W1 + Otp block9 word1 data. 0 - 6 - read-write - - - FUNC96_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG96_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC97_IN_SEL_CFG - GPIO input function configuration register - 0x2DC - 0x20 - 0x0000003E + APB2OTP_BLK9_W2 + eFuse apb2otp block9 data register2. + 0x9B0 + 0x20 - FUNC97_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK9_W2 + Otp block9 word2 data. 0 - 6 - read-write - - - FUNC97_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG97_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC98_IN_SEL_CFG - GPIO input function configuration register - 0x2E0 + APB2OTP_BLK9_W3 + eFuse apb2otp block9 data register3. + 0x9B4 0x20 - 0x0000003E - FUNC98_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK9_W3 + Otp block9 word3 data. 0 - 6 - read-write - - - FUNC98_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG98_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC99_IN_SEL_CFG - GPIO input function configuration register - 0x2E4 + APB2OTP_BLK9_W4 + eFuse apb2otp block9 data register4. + 0x9B8 0x20 - 0x0000003E - FUNC99_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK9_W4 + Otp block9 word4 data. 0 - 6 - read-write - - - FUNC99_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG99_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC100_IN_SEL_CFG - GPIO input function configuration register - 0x2E8 + APB2OTP_BLK9_W5 + eFuse apb2otp block9 data register5. + 0x9BC 0x20 - 0x0000003E - FUNC100_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK9_W5 + Otp block9 word5 data. 0 - 6 - read-write - - - FUNC100_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG100_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC101_IN_SEL_CFG - GPIO input function configuration register - 0x2EC + APB2OTP_BLK9_W6 + eFuse apb2otp block9 data register6. + 0x9C0 0x20 - 0x0000003E - FUNC101_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK9_W6 + Otp block9 word6 data. 0 - 6 - read-write - - - FUNC101_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG101_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC102_IN_SEL_CFG - GPIO input function configuration register - 0x2F0 + APB2OTP_BLK9_W7 + eFuse apb2otp block9 data register7. + 0x9C4 0x20 - 0x0000003E - FUNC102_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK9_W7 + Otp block9 word7 data. 0 - 6 - read-write - - - FUNC102_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG102_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC103_IN_SEL_CFG - GPIO input function configuration register - 0x2F4 + APB2OTP_BLK9_W8 + eFuse apb2otp block9 data register8. + 0x9C8 0x20 - 0x0000003E - FUNC103_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK9_W8 + Otp block9 word8 data. 0 - 6 - read-write - - - FUNC103_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG103_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC104_IN_SEL_CFG - GPIO input function configuration register - 0x2F8 + APB2OTP_BLK9_W9 + eFuse apb2otp block9 data register9. + 0x9CC 0x20 - 0x0000003E - FUNC104_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK9_W9 + Otp block9 word9 data. 0 - 6 - read-write - - - FUNC104_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG104_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC105_IN_SEL_CFG - GPIO input function configuration register - 0x2FC + APB2OTP_BLK9_W10 + eFuse apb2otp block9 data register10. + 0x9D0 0x20 - 0x0000003E - FUNC105_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK9_W10 + Otp block9 word10 data. 0 - 6 - read-write - - - FUNC105_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG105_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC106_IN_SEL_CFG - GPIO input function configuration register - 0x300 + APB2OTP_BLK9_W11 + eFuse apb2otp block9 data register11. + 0x9D4 0x20 - 0x0000003E - FUNC106_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK9_W11 + Otp block9 word11 data. 0 - 6 - read-write - - - FUNC106_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG106_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC107_IN_SEL_CFG - GPIO input function configuration register - 0x304 + APB2OTP_BLK10_W1 + eFuse apb2otp block10 data register1. + 0x9D8 0x20 - 0x0000003E - FUNC107_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK10_W1 + Otp block10 word1 data. 0 - 6 - read-write - - - FUNC107_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG107_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC108_IN_SEL_CFG - GPIO input function configuration register - 0x308 + APB2OTP_BLK10_W2 + eFuse apb2otp block10 data register2. + 0x9DC 0x20 - 0x0000003E - FUNC108_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK10_W2 + Otp block10 word2 data. 0 - 6 - read-write - - - FUNC108_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG108_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC109_IN_SEL_CFG - GPIO input function configuration register - 0x30C + APB2OTP_BLK10_W3 + eFuse apb2otp block10 data register3. + 0x9E0 0x20 - 0x0000003E - FUNC109_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK10_W3 + Otp block10 word3 data. 0 - 6 - read-write - - - FUNC109_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG109_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC110_IN_SEL_CFG - GPIO input function configuration register - 0x310 + APB2OTP_BLK10_W4 + eFuse apb2otp block10 data register4. + 0x9E4 0x20 - 0x0000003E - FUNC110_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK10_W4 + Otp block10 word4 data. 0 - 6 - read-write - - - FUNC110_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG110_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC111_IN_SEL_CFG - GPIO input function configuration register - 0x314 + APB2OTP_BLK10_W5 + eFuse apb2otp block10 data register5. + 0x9E8 0x20 - 0x0000003E - FUNC111_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK10_W5 + Otp block10 word5 data. 0 - 6 - read-write - - - FUNC111_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG111_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC112_IN_SEL_CFG - GPIO input function configuration register - 0x318 + APB2OTP_BLK10_W6 + eFuse apb2otp block10 data register6. + 0x9EC 0x20 - 0x0000003E - FUNC112_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK10_W6 + Otp block10 word6 data. 0 - 6 - read-write - - - FUNC112_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG112_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC113_IN_SEL_CFG - GPIO input function configuration register - 0x31C + APB2OTP_BLK10_W7 + eFuse apb2otp block10 data register7. + 0x9F0 0x20 - 0x0000003E - FUNC113_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK10_W7 + Otp block10 word7 data. 0 - 6 - read-write - - - FUNC113_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG113_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC114_IN_SEL_CFG - GPIO input function configuration register - 0x320 + APB2OTP_BLK10_W8 + eFuse apb2otp block10 data register8. + 0x9F4 0x20 - 0x0000003E - FUNC114_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK10_W8 + Otp block10 word8 data. 0 - 6 - read-write - - - FUNC114_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG114_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC117_IN_SEL_CFG - GPIO input function configuration register - 0x32C + APB2OTP_BLK10_W9 + eFuse apb2otp block10 data register9. + 0x9F8 0x20 - 0x0000003E - FUNC117_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK10_W9 + Otp block10 word9 data. 0 - 6 - read-write - - - FUNC117_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG117_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC118_IN_SEL_CFG - GPIO input function configuration register - 0x330 + APB2OTP_BLK10_W10 + eFuse apb2otp block10 data register10. + 0x9FC 0x20 - 0x0000003E - FUNC118_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK19_W10 + Otp block10 word10 data. 0 - 6 - read-write - - - FUNC118_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG118_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC126_IN_SEL_CFG - GPIO input function configuration register - 0x350 + APB2OTP_BLK10_W11 + eFuse apb2otp block10 data register11. + 0xA00 0x20 - 0x0000003E - FUNC126_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_BLOCK10_W11 + Otp block10 word11 data. 0 - 6 - read-write - - - FUNC126_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG126_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC127_IN_SEL_CFG - GPIO input function configuration register - 0x354 + APB2OTP_EN + eFuse apb2otp enable configuration register. + 0xA08 0x20 - 0x0000003E - FUNC127_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + APB2OTP_APB2OTP_EN + Apb2otp mode enable signal. 0 - 6 - read-write - - - FUNC127_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG127_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 1 read-write + + + + GPIO + General Purpose Input/Output + GPIO + 0x500E0000 + + 0x0 + 0x5F8 + registers + + + GPIO_INT0 + 74 + + + GPIO_INT1 + 75 + + + GPIO_INT2 + 76 + + + GPIO_INT3 + 77 + + + GPIO_PAD_COMP + 78 + + - FUNC128_IN_SEL_CFG - GPIO input function configuration register - 0x358 + BT_SELECT + GPIO bit select register + 0x0 0x20 - 0x0000003F - FUNC128_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + BT_SEL + GPIO bit select register 0 - 6 - read-write - - - FUNC128_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG128_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 + 32 read-write - FUNC129_IN_SEL_CFG - GPIO input function configuration register - 0x35C + OUT + GPIO output register for GPIO0-31 + 0x4 0x20 - 0x0000003F - FUNC129_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + DATA_ORIG + GPIO output register for GPIO0-31 0 - 6 - read-write - - - FUNC129_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG129_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 + 32 read-write - FUNC130_IN_SEL_CFG - GPIO input function configuration register - 0x360 + OUT_W1TS + GPIO output set register for GPIO0-31 + 0x8 0x20 - 0x0000003E - FUNC130_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + OUT_W1TS + GPIO output set register for GPIO0-31 0 - 6 - read-write - - - FUNC130_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG130_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + write-only - FUNC131_IN_SEL_CFG - GPIO input function configuration register - 0x364 + OUT_W1TC + GPIO output clear register for GPIO0-31 + 0xC 0x20 - 0x0000003E - FUNC131_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + OUT_W1TC + GPIO output clear register for GPIO0-31 0 - 6 - read-write - - - FUNC131_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG131_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + write-only - FUNC132_IN_SEL_CFG - GPIO input function configuration register - 0x368 + OUT1 + GPIO output register for GPIO32-56 + 0x10 0x20 - 0x0000003E - FUNC132_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + DATA_ORIG + GPIO output register for GPIO32-56 0 - 6 - read-write - - - FUNC132_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG132_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 + 25 read-write - FUNC133_IN_SEL_CFG - GPIO input function configuration register - 0x36C + OUT1_W1TS + GPIO output set register for GPIO32-56 + 0x14 0x20 - 0x0000003E - FUNC133_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + OUT1_W1TS + GPIO output set register for GPIO32-56 0 - 6 - read-write - - - FUNC133_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG133_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 25 + write-only - FUNC134_IN_SEL_CFG - GPIO input function configuration register - 0x370 + OUT1_W1TC + GPIO output clear register for GPIO32-56 + 0x18 0x20 - 0x0000003F - FUNC134_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + OUT1_W1TC + GPIO output clear register for GPIO32-56 0 - 6 - read-write - - - FUNC134_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG134_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 25 + write-only - FUNC135_IN_SEL_CFG - GPIO input function configuration register - 0x374 + ENABLE + GPIO output enable register for GPIO0-31 + 0x20 0x20 - 0x0000003F - FUNC135_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + DATA + GPIO output enable register for GPIO0-31 0 - 6 - read-write - - - FUNC135_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG135_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 + 32 read-write - FUNC136_IN_SEL_CFG - GPIO input function configuration register - 0x378 + ENABLE_W1TS + GPIO output enable set register for GPIO0-31 + 0x24 0x20 - 0x0000003F - FUNC136_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + ENABLE_W1TS + GPIO output enable set register for GPIO0-31 0 - 6 - read-write - - - FUNC136_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG136_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + write-only - FUNC137_IN_SEL_CFG - GPIO input function configuration register - 0x37C + ENABLE_W1TC + GPIO output enable clear register for GPIO0-31 + 0x28 0x20 - 0x0000003F - FUNC137_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + ENABLE_W1TC + GPIO output enable clear register for GPIO0-31 0 - 6 - read-write - - - FUNC137_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG137_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + write-only - FUNC138_IN_SEL_CFG - GPIO input function configuration register - 0x380 + ENABLE1 + GPIO output enable register for GPIO32-56 + 0x2C 0x20 - 0x0000003E - FUNC138_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + DATA + GPIO output enable register for GPIO32-56 0 - 6 - read-write - - - FUNC138_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG138_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 + 25 read-write - FUNC139_IN_SEL_CFG - GPIO input function configuration register - 0x384 + ENABLE1_W1TS + GPIO output enable set register for GPIO32-56 + 0x30 0x20 - 0x0000003E - FUNC139_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + ENABLE1_W1TS + GPIO output enable set register for GPIO32-56 0 - 6 - read-write - - - FUNC139_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG139_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 25 + write-only - FUNC140_IN_SEL_CFG - GPIO input function configuration register - 0x388 + ENABLE1_W1TC + GPIO output enable clear register for GPIO32-56 + 0x34 0x20 - 0x0000003E - FUNC140_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + ENABLE1_W1TC + GPIO output enable clear register for GPIO32-56 0 - 6 - read-write - - - FUNC140_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG140_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 25 + write-only - FUNC141_IN_SEL_CFG - GPIO input function configuration register - 0x38C + STRAP + pad strapping register + 0x38 0x20 - 0x0000003E - FUNC141_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + STRAPPING + pad strapping register 0 - 6 - read-write - - - FUNC141_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG141_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 16 + read-only - FUNC142_IN_SEL_CFG - GPIO input function configuration register - 0x390 + IN + GPIO input register for GPIO0-31 + 0x3C 0x20 - 0x0000003E - FUNC142_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + DATA_NEXT + GPIO input register for GPIO0-31 0 - 6 - read-write - - - FUNC142_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG142_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC143_IN_SEL_CFG - GPIO input function configuration register - 0x394 + IN1 + GPIO input register for GPIO32-56 + 0x40 0x20 - 0x0000003E - FUNC143_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + DATA_NEXT + GPIO input register for GPIO32-56 0 - 6 - read-write - - - FUNC143_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG143_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 25 + read-only - FUNC144_IN_SEL_CFG - GPIO input function configuration register - 0x398 + STATUS + GPIO interrupt status register for GPIO0-31 + 0x44 0x20 - 0x0000003E - FUNC144_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + INTERRUPT + GPIO interrupt status register for GPIO0-31 0 - 6 - read-write - - - FUNC144_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG144_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 + 32 read-write - FUNC145_IN_SEL_CFG - GPIO input function configuration register - 0x39C + STATUS_W1TS + GPIO interrupt status set register for GPIO0-31 + 0x48 0x20 - 0x0000003E - FUNC145_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + STATUS_W1TS + GPIO interrupt status set register for GPIO0-31 0 - 6 - read-write - - - FUNC145_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG145_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + write-only - FUNC146_IN_SEL_CFG - GPIO input function configuration register - 0x3A0 + STATUS_W1TC + GPIO interrupt status clear register for GPIO0-31 + 0x4C 0x20 - 0x0000003E - FUNC146_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + STATUS_W1TC + GPIO interrupt status clear register for GPIO0-31 0 - 6 - read-write - - - FUNC146_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG146_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + write-only - FUNC147_IN_SEL_CFG - GPIO input function configuration register - 0x3A4 + STATUS1 + GPIO interrupt status register for GPIO32-56 + 0x50 0x20 - 0x0000003E - FUNC147_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + INTERRUPT + GPIO interrupt status register for GPIO32-56 0 - 6 - read-write - - - FUNC147_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG147_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 + 25 read-write - FUNC148_IN_SEL_CFG - GPIO input function configuration register - 0x3A8 + STATUS1_W1TS + GPIO interrupt status set register for GPIO32-56 + 0x54 0x20 - 0x0000003E - FUNC148_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + STATUS1_W1TS + GPIO interrupt status set register for GPIO32-56 0 - 6 - read-write - - - FUNC148_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write + 25 + write-only + + + + STATUS1_W1TC + GPIO interrupt status clear register for GPIO32-56 + 0x58 + 0x20 + - SIG148_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + STATUS1_W1TC + GPIO interrupt status clear register for GPIO32-56 + 0 + 25 + write-only - FUNC149_IN_SEL_CFG - GPIO input function configuration register - 0x3AC + INTR_0 + GPIO interrupt 0 status register for GPIO0-31 + 0x5C 0x20 - 0x0000003E - FUNC149_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + INT_0 + GPIO interrupt 0 status register for GPIO0-31 0 - 6 - read-write + 32 + read-only + + + + INTR1_0 + GPIO interrupt 0 status register for GPIO32-56 + 0x60 + 0x20 + - FUNC149_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write + INT1_0 + GPIO interrupt 0 status register for GPIO32-56 + 0 + 25 + read-only + + + + INTR_1 + GPIO interrupt 1 status register for GPIO0-31 + 0x64 + 0x20 + - SIG149_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + INT_1 + GPIO interrupt 1 status register for GPIO0-31 + 0 + 32 + read-only - FUNC150_IN_SEL_CFG - GPIO input function configuration register - 0x3B0 + INTR1_1 + GPIO interrupt 1 status register for GPIO32-56 + 0x68 0x20 - 0x0000003E - FUNC150_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + INT1_1 + GPIO interrupt 1 status register for GPIO32-56 0 - 6 - read-write + 25 + read-only + + + + STATUS_NEXT + GPIO interrupt source register for GPIO0-31 + 0x6C + 0x20 + - FUNC150_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write + STATUS_INTERRUPT_NEXT + GPIO interrupt source register for GPIO0-31 + 0 + 32 + read-only + + + + STATUS_NEXT1 + GPIO interrupt source register for GPIO32-56 + 0x70 + 0x20 + - SIG150_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + STATUS_INTERRUPT_NEXT1 + GPIO interrupt source register for GPIO32-56 + 0 + 25 + read-only - FUNC151_IN_SEL_CFG - GPIO input function configuration register - 0x3B4 + 57 + 0x4 + PIN%s + GPIO pin configuration register + 0x74 0x20 - 0x0000003E - FUNC151_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + SYNC2_BYPASS + set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge. 0 - 6 + 2 read-write - FUNC151_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + PAD_DRIVER + set this bit to select pad driver. 1:open-drain. 0:normal. + 2 1 read-write - SIG151_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 + SYNC1_BYPASS + set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge. + 3 + 2 read-write - - - - FUNC152_IN_SEL_CFG - GPIO input function configuration register - 0x3B8 - 0x20 - 0x0000003E - - FUNC152_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. - 0 - 6 + INT_TYPE + set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid at high level + 7 + 3 read-write - FUNC152_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + WAKEUP_ENABLE + set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + 10 1 read-write - SIG152_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 + CONFIG + reserved + 11 + 2 + read-write + + + INT_ENA + set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) interrupt. + 13 + 5 read-write - FUNC153_IN_SEL_CFG - GPIO input function configuration register - 0x3BC + 57 + 0x4 + FUNC%s_OUT_SEL_CFG + GPIO output function select register + 0x558 0x20 - 0x0000003E + 0x00000100 - FUNC153_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + OUT_SEL + The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. 0 - 6 + 9 read-write - FUNC153_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + INV_SEL + set this bit to invert output signal.1:invert.0:not invert. + 9 1 read-write - SIG153_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + OEN_SEL + set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output enable signal.0:use peripheral output enable signal. + 10 + 1 + read-write + + + OEN_INV_SEL + set this bit to invert output enable signal.1:invert.0:not invert. + 11 1 read-write - FUNC154_IN_SEL_CFG - GPIO input function configuration register - 0x3C0 + INTR_2 + GPIO interrupt 2 status register for GPIO0-31 + 0x63C 0x20 - 0x0000003E - FUNC154_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + INT_2 + GPIO interrupt 2 status register for GPIO0-31 0 - 6 - read-write - - - FUNC154_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write + 32 + read-only + + + + INTR1_2 + GPIO interrupt 2 status register for GPIO32-56 + 0x640 + 0x20 + - SIG154_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + INT1_2 + GPIO interrupt 2 status register for GPIO32-56 + 0 + 25 + read-only - FUNC155_IN_SEL_CFG - GPIO input function configuration register - 0x3C4 + INTR_3 + GPIO interrupt 3 status register for GPIO0-31 + 0x644 0x20 - 0x0000003E - FUNC155_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + INT_3 + GPIO interrupt 3 status register for GPIO0-31 0 - 6 - read-write + 32 + read-only + + + + INTR1_3 + GPIO interrupt 3 status register for GPIO32-56 + 0x648 + 0x20 + - FUNC155_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write + INT1_3 + GPIO interrupt 3 status register for GPIO32-56 + 0 + 25 + read-only + + + + CLOCK_GATE + GPIO clock gate register + 0x64C + 0x20 + 0x00000001 + - SIG155_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + CLK_EN + set this bit to enable GPIO clock gate + 0 1 read-write - FUNC156_IN_SEL_CFG - GPIO input function configuration register - 0x3C8 + INT_RAW + analog comparator interrupt raw + 0x700 0x20 - 0x0000003E - FUNC156_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + COMP0_NEG_INT_RAW + analog comparator pos edge interrupt raw 0 - 6 - read-write - - - FUNC156_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 1 read-write - SIG156_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + COMP0_POS_INT_RAW + analog comparator neg edge interrupt raw + 1 1 read-write - - - - FUNC158_IN_SEL_CFG - GPIO input function configuration register - 0x3D0 - 0x20 - 0x0000003E - - FUNC158_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. - 0 - 6 + COMP0_ALL_INT_RAW + analog comparator neg or pos edge interrupt raw + 2 + 1 read-write - FUNC158_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + COMP1_NEG_INT_RAW + analog comparator pos edge interrupt raw + 3 1 read-write - SIG158_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + COMP1_POS_INT_RAW + analog comparator neg edge interrupt raw + 4 1 read-write - - - - FUNC159_IN_SEL_CFG - GPIO input function configuration register - 0x3D4 - 0x20 - 0x0000003E - - FUNC159_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. - 0 - 6 + COMP1_ALL_INT_RAW + analog comparator neg or pos edge interrupt raw + 5 + 1 read-write - FUNC159_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. + BISTOK_INT_RAW + pad bistok interrupt raw 6 1 read-write - SIG159_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + BISTFAIL_INT_RAW + pad bistfail interrupt raw 7 1 read-write @@ -41780,149 +39639,128 @@ - FUNC160_IN_SEL_CFG - GPIO input function configuration register - 0x3D8 + INT_ST + analog comparator interrupt status + 0x704 0x20 - 0x0000003E - FUNC160_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + COMP0_NEG_INT_ST + analog comparator pos edge interrupt status 0 - 6 - read-write + 1 + read-only - FUNC160_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + COMP0_POS_INT_ST + analog comparator neg edge interrupt status + 1 1 - read-write + read-only - SIG160_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + COMP0_ALL_INT_ST + analog comparator neg or pos edge interrupt status + 2 1 - read-write + read-only - - - - FUNC161_IN_SEL_CFG - GPIO input function configuration register - 0x3DC - 0x20 - 0x0000003E - - FUNC161_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. - 0 - 6 - read-write + COMP1_NEG_INT_ST + analog comparator pos edge interrupt status + 3 + 1 + read-only - FUNC161_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. + COMP1_POS_INT_ST + analog comparator neg edge interrupt status + 4 + 1 + read-only + + + COMP1_ALL_INT_ST + analog comparator neg or pos edge interrupt status + 5 + 1 + read-only + + + BISTOK_INT_ST + pad bistok interrupt status 6 1 - read-write + read-only - SIG161_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + BISTFAIL_INT_ST + pad bistfail interrupt status 7 1 - read-write + read-only - FUNC162_IN_SEL_CFG - GPIO input function configuration register - 0x3E0 + INT_ENA + analog comparator interrupt enable + 0x708 0x20 - 0x0000003E + 0x000000FF - FUNC162_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + COMP0_NEG_INT_ENA + analog comparator pos edge interrupt enable 0 - 6 - read-write - - - FUNC162_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 1 read-write - SIG162_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + COMP0_POS_INT_ENA + analog comparator neg edge interrupt enable + 1 1 read-write - - - - FUNC163_IN_SEL_CFG - GPIO input function configuration register - 0x3E4 - 0x20 - 0x0000003E - - FUNC163_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. - 0 - 6 + COMP0_ALL_INT_ENA + analog comparator neg or pos edge interrupt enable + 2 + 1 read-write - FUNC163_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + COMP1_NEG_INT_ENA + analog comparator pos edge interrupt enable + 3 1 read-write - SIG163_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + COMP1_POS_INT_ENA + analog comparator neg edge interrupt enable + 4 1 read-write - - - - FUNC164_IN_SEL_CFG - GPIO input function configuration register - 0x3E8 - 0x20 - 0x0000003E - - FUNC164_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. - 0 - 6 + COMP1_ALL_INT_ENA + analog comparator neg or pos edge interrupt enable + 5 + 1 read-write - FUNC164_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. + BISTOK_INT_ENA + pad bistok interrupt enable 6 1 read-write - SIG164_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + BISTFAIL_INT_ENA + pad bistfail interrupt enable 7 1 read-write @@ -41930,329 +39768,348 @@ - FUNC165_IN_SEL_CFG - GPIO input function configuration register - 0x3EC + INT_CLR + analog comparator interrupt clear + 0x70C 0x20 - 0x0000003E - FUNC165_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + COMP0_NEG_INT_CLR + analog comparator pos edge interrupt clear 0 - 6 - read-write + 1 + write-only - FUNC165_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + COMP0_POS_INT_CLR + analog comparator neg edge interrupt clear + 1 1 - read-write + write-only - SIG165_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + COMP0_ALL_INT_CLR + analog comparator neg or pos edge interrupt clear + 2 1 - read-write + write-only - - - - FUNC166_IN_SEL_CFG - GPIO input function configuration register - 0x3F0 - 0x20 - 0x0000003E - - FUNC166_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. - 0 - 6 - read-write + COMP1_NEG_INT_CLR + analog comparator pos edge interrupt clear + 3 + 1 + write-only - FUNC166_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. + COMP1_POS_INT_CLR + analog comparator neg edge interrupt clear + 4 + 1 + write-only + + + COMP1_ALL_INT_CLR + analog comparator neg or pos edge interrupt clear + 5 + 1 + write-only + + + BISTOK_INT_CLR + pad bistok interrupt enable 6 1 - read-write + write-only - SIG166_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + BISTFAIL_INT_CLR + pad bistfail interrupt enable 7 1 - read-write + write-only - FUNC167_IN_SEL_CFG - GPIO input function configuration register - 0x3F4 + ZERO_DET0_FILTER_CNT + GPIO analog comparator zero detect filter count + 0x710 0x20 - 0x0000003E + 0xFFFFFFFF - FUNC167_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + ZERO_DET0_FILTER_CNT + GPIO analog comparator zero detect filter count 0 - 6 - read-write - - - FUNC167_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG167_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 + 32 read-write - FUNC168_IN_SEL_CFG - GPIO input function configuration register - 0x3F8 + ZERO_DET1_FILTER_CNT + GPIO analog comparator zero detect filter count + 0x714 0x20 - 0x0000003E + 0xFFFFFFFF - FUNC168_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + ZERO_DET1_FILTER_CNT + GPIO analog comparator zero detect filter count 0 - 6 + 32 read-write + + + + SEND_SEQ + High speed sdio pad bist send sequence + 0x718 + 0x20 + 0x12345678 + - FUNC168_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 + SEND_SEQ + High speed sdio pad bist send sequence + 0 + 32 read-write + + + + RECIVE_SEQ + High speed sdio pad bist recive sequence + 0x71C + 0x20 + - SIG168_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + RECIVE_SEQ + High speed sdio pad bist recive sequence + 0 + 32 + read-only - FUNC169_IN_SEL_CFG - GPIO input function configuration register - 0x3FC + BISTIN_SEL + High speed sdio pad bist in pad sel + 0x720 0x20 - 0x0000003E + 0x0000000F - FUNC169_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + BISTIN_SEL + High speed sdio pad bist in pad sel 0:pad39, 1: pad40... 0 - 6 + 4 read-write + + + + BIST_CTRL + High speed sdio pad bist control + 0x724 + 0x20 + 0x00000001 + - FUNC169_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + BIST_PAD_OE + High speed sdio pad bist out pad oe + 0 1 read-write - SIG169_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + BIST_START + High speed sdio pad bist start + 1 1 - read-write + write-only - FUNC170_IN_SEL_CFG - GPIO input function configuration register - 0x400 + DATE + GPIO version register + 0x7FC 0x20 - 0x0000003E + 0x00230403 - FUNC170_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + DATE + version register 0 - 6 - read-write - - - FUNC170_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG170_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 + 28 read-write - FUNC171_IN_SEL_CFG + 254 + 0x4 + 1-254 + FUNC%s_IN_SEL_CFG GPIO input function configuration register - 0x404 + 0x15C 0x20 - 0x0000003E + read-write - FUNC171_IN_SEL + IN_SEL set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. 0 6 - read-write - FUNC171_IN_INV_SEL + IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 - read-write - SIG171_IN_SEL + SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 - read-write + + + + GPIO_SD + Sigma-Delta Modulation + GPIOSD + 0x500E0F00 + + 0x0 + 0xA4 + registers + + - FUNC172_IN_SEL_CFG - GPIO input function configuration register - 0x408 + 8 + 0x4 + SIGMADELTA%s + Duty Cycle Configure Register of SDM%s + 0x0 0x20 - 0x0000003E + 0x0000FF00 - FUNC172_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + SD_IN + This field is used to configure the duty cycle of sigma delta modulation output. 0 - 6 - read-write - - - FUNC172_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 + 8 read-write - SIG172_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 + SD_PRESCALE + This field is used to set a divider value to divide APB clock. + 8 + 8 read-write - FUNC173_IN_SEL_CFG - GPIO input function configuration register - 0x40C + CLOCK_GATE + Clock Gating Configure Register + 0x20 0x20 - 0x0000003E - FUNC173_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + CLK_EN + Clock enable bit of configuration registers for sigma delta modulation. 0 - 6 + 1 read-write + + + + SIGMADELTA_MISC + MISC Register + 0x24 + 0x20 + - FUNC173_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + FUNCTION_CLK_EN + Clock enable bit of sigma delta modulation. + 30 1 read-write - SIG173_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + SPI_SWAP + Reserved. + 31 1 read-write - FUNC174_IN_SEL_CFG - GPIO input function configuration register - 0x410 + 8 + 0x4 + GLITCH_FILTER_CH%s + Glitch Filter Configure Register of Channel%s + 0x30 0x20 - 0x0000003E - FUNC174_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + FILTER_CH0_EN + Glitch Filter channel enable bit. 0 - 6 + 1 read-write - FUNC174_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 + FILTER_CH0_INPUT_IO_NUM + Glitch Filter input io number. + 1 + 6 read-write - SIG174_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + FILTER_CH0_WINDOW_THRES + Glitch Filter window threshold. 7 - 1 + 6 + read-write + + + FILTER_CH0_WINDOW_WIDTH + Glitch Filter window width. + 13 + 6 read-write - FUNC175_IN_SEL_CFG - GPIO input function configuration register - 0x414 + 8 + 0x4 + ETM_EVENT_CH%s_CFG + Etm Config register of Channel%s + 0x60 0x20 - 0x0000003E - FUNC175_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + ETM_CH0_EVENT_SEL + Etm event channel select gpio. 0 6 read-write - FUNC175_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG175_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + ETM_CH0_EVENT_EN + Etm event send enable bit. 7 1 read-write @@ -42260,2279 +40117,2437 @@ - FUNC176_IN_SEL_CFG - GPIO input function configuration register - 0x418 + ETM_TASK_P0_CFG + Etm Configure Register to decide which GPIO been chosen + 0xA0 0x20 - 0x0000003E - FUNC176_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + ETM_TASK_GPIO0_EN + Enable bit of GPIO response etm task. 0 - 6 + 1 read-write - FUNC176_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 + ETM_TASK_GPIO0_SEL + GPIO choose a etm task channel. + 1 + 3 read-write - SIG176_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + ETM_TASK_GPIO1_EN + Enable bit of GPIO response etm task. + 8 1 read-write - - - - FUNC177_IN_SEL_CFG - GPIO input function configuration register - 0x41C - 0x20 - 0x0000003E - - FUNC177_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. - 0 - 6 + ETM_TASK_GPIO1_SEL + GPIO choose a etm task channel. + 9 + 3 read-write - FUNC177_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + ETM_TASK_GPIO2_EN + Enable bit of GPIO response etm task. + 16 1 read-write - SIG177_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + ETM_TASK_GPIO2_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + ETM_TASK_GPIO3_EN + Enable bit of GPIO response etm task. + 24 1 read-write + + ETM_TASK_GPIO3_SEL + GPIO choose a etm task channel. + 25 + 3 + read-write + - FUNC178_IN_SEL_CFG - GPIO input function configuration register - 0x420 + ETM_TASK_P1_CFG + Etm Configure Register to decide which GPIO been chosen + 0xA4 0x20 - 0x0000003E - FUNC178_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + ETM_TASK_GPIO4_EN + Enable bit of GPIO response etm task. 0 - 6 + 1 read-write - FUNC178_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 + ETM_TASK_GPIO4_SEL + GPIO choose a etm task channel. + 1 + 3 read-write - SIG178_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + ETM_TASK_GPIO5_EN + Enable bit of GPIO response etm task. + 8 1 read-write - - - - FUNC179_IN_SEL_CFG - GPIO input function configuration register - 0x424 - 0x20 - 0x0000003E - - FUNC179_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. - 0 - 6 + ETM_TASK_GPIO5_SEL + GPIO choose a etm task channel. + 9 + 3 read-write - FUNC179_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + ETM_TASK_GPIO6_EN + Enable bit of GPIO response etm task. + 16 1 read-write - SIG179_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + ETM_TASK_GPIO6_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + ETM_TASK_GPIO7_EN + Enable bit of GPIO response etm task. + 24 1 read-write + + ETM_TASK_GPIO7_SEL + GPIO choose a etm task channel. + 25 + 3 + read-write + - FUNC180_IN_SEL_CFG - GPIO input function configuration register - 0x428 + ETM_TASK_P2_CFG + Etm Configure Register to decide which GPIO been chosen + 0xA8 0x20 - 0x0000003E - FUNC180_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + ETM_TASK_GPIO8_EN + Enable bit of GPIO response etm task. 0 - 6 + 1 read-write - FUNC180_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 + ETM_TASK_GPIO8_SEL + GPIO choose a etm task channel. + 1 + 3 read-write - SIG180_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + ETM_TASK_GPIO9_EN + Enable bit of GPIO response etm task. + 8 1 read-write - - - - FUNC181_IN_SEL_CFG - GPIO input function configuration register - 0x42C - 0x20 - 0x0000003E - - FUNC181_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. - 0 - 6 + ETM_TASK_GPIO9_SEL + GPIO choose a etm task channel. + 9 + 3 read-write - FUNC181_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + ETM_TASK_GPIO10_EN + Enable bit of GPIO response etm task. + 16 1 read-write - SIG181_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC182_IN_SEL_CFG - GPIO input function configuration register - 0x430 - 0x20 - 0x0000003E - - - FUNC182_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. - 0 - 6 + ETM_TASK_GPIO10_SEL + GPIO choose a etm task channel. + 17 + 3 read-write - FUNC182_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + ETM_TASK_GPIO11_EN + Enable bit of GPIO response etm task. + 24 1 read-write - SIG182_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 + ETM_TASK_GPIO11_SEL + GPIO choose a etm task channel. + 25 + 3 read-write - FUNC183_IN_SEL_CFG - GPIO input function configuration register - 0x434 + ETM_TASK_P3_CFG + Etm Configure Register to decide which GPIO been chosen + 0xAC 0x20 - 0x0000003E - FUNC183_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + ETM_TASK_GPIO12_EN + Enable bit of GPIO response etm task. 0 - 6 - read-write - - - FUNC183_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 1 read-write - SIG183_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 + ETM_TASK_GPIO12_SEL + GPIO choose a etm task channel. + 1 + 3 read-write - - - - FUNC184_IN_SEL_CFG - GPIO input function configuration register - 0x438 - 0x20 - 0x0000003E - - FUNC184_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. - 0 - 6 + ETM_TASK_GPIO13_EN + Enable bit of GPIO response etm task. + 8 + 1 read-write - FUNC184_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 + ETM_TASK_GPIO13_SEL + GPIO choose a etm task channel. + 9 + 3 read-write - SIG184_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + ETM_TASK_GPIO14_EN + Enable bit of GPIO response etm task. + 16 1 read-write - - - - FUNC185_IN_SEL_CFG - GPIO input function configuration register - 0x43C - 0x20 - 0x0000003E - - FUNC185_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. - 0 - 6 + ETM_TASK_GPIO14_SEL + GPIO choose a etm task channel. + 17 + 3 read-write - FUNC185_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + ETM_TASK_GPIO15_EN + Enable bit of GPIO response etm task. + 24 1 read-write - SIG185_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 + ETM_TASK_GPIO15_SEL + GPIO choose a etm task channel. + 25 + 3 read-write - FUNC186_IN_SEL_CFG - GPIO input function configuration register - 0x440 + ETM_TASK_P4_CFG + Etm Configure Register to decide which GPIO been chosen + 0xB0 0x20 - 0x0000003E - FUNC186_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + ETM_TASK_GPIO16_EN + Enable bit of GPIO response etm task. 0 - 6 + 1 read-write - FUNC186_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 + ETM_TASK_GPIO16_SEL + GPIO choose a etm task channel. + 1 + 3 read-write - SIG186_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + ETM_TASK_GPIO17_EN + Enable bit of GPIO response etm task. + 8 1 read-write - - - - FUNC187_IN_SEL_CFG - GPIO input function configuration register - 0x444 - 0x20 - 0x0000003E - - FUNC187_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. - 0 - 6 + ETM_TASK_GPIO17_SEL + GPIO choose a etm task channel. + 9 + 3 read-write - FUNC187_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + ETM_TASK_GPIO18_EN + Enable bit of GPIO response etm task. + 16 1 read-write - SIG187_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + ETM_TASK_GPIO18_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + ETM_TASK_GPIO19_EN + Enable bit of GPIO response etm task. + 24 1 read-write + + ETM_TASK_GPIO19_SEL + GPIO choose a etm task channel. + 25 + 3 + read-write + - FUNC188_IN_SEL_CFG - GPIO input function configuration register - 0x448 + ETM_TASK_P5_CFG + Etm Configure Register to decide which GPIO been chosen + 0xB4 0x20 - 0x0000003E - FUNC188_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + ETM_TASK_GPIO20_EN + Enable bit of GPIO response etm task. 0 - 6 + 1 read-write - FUNC188_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 + ETM_TASK_GPIO20_SEL + GPIO choose a etm task channel. + 1 + 3 read-write - SIG188_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + ETM_TASK_GPIO21_EN + Enable bit of GPIO response etm task. + 8 1 read-write - - - - FUNC189_IN_SEL_CFG - GPIO input function configuration register - 0x44C - 0x20 - 0x0000003E - - FUNC189_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. - 0 - 6 + ETM_TASK_GPIO21_SEL + GPIO choose a etm task channel. + 9 + 3 read-write - FUNC189_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + ETM_TASK_GPIO22_EN + Enable bit of GPIO response etm task. + 16 1 read-write - SIG189_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + ETM_TASK_GPIO22_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + ETM_TASK_GPIO23_EN + Enable bit of GPIO response etm task. + 24 1 read-write + + ETM_TASK_GPIO23_SEL + GPIO choose a etm task channel. + 25 + 3 + read-write + - FUNC190_IN_SEL_CFG - GPIO input function configuration register - 0x450 + ETM_TASK_P6_CFG + Etm Configure Register to decide which GPIO been chosen + 0xB8 0x20 - 0x0000003E - FUNC190_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + ETM_TASK_GPIO24_EN + Enable bit of GPIO response etm task. 0 - 6 + 1 read-write - FUNC190_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 + ETM_TASK_GPIO24_SEL + GPIO choose a etm task channel. + 1 + 3 read-write - SIG190_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + ETM_TASK_GPIO25_EN + Enable bit of GPIO response etm task. + 8 1 read-write - - - - FUNC191_IN_SEL_CFG - GPIO input function configuration register - 0x454 - 0x20 - 0x0000003E - - FUNC191_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. - 0 - 6 + ETM_TASK_GPIO25_SEL + GPIO choose a etm task channel. + 9 + 3 read-write - FUNC191_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + ETM_TASK_GPIO26_EN + Enable bit of GPIO response etm task. + 16 1 read-write - SIG191_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + ETM_TASK_GPIO26_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + ETM_TASK_GPIO27_EN + Enable bit of GPIO response etm task. + 24 1 read-write + + ETM_TASK_GPIO27_SEL + GPIO choose a etm task channel. + 25 + 3 + read-write + - FUNC192_IN_SEL_CFG - GPIO input function configuration register - 0x458 + ETM_TASK_P7_CFG + Etm Configure Register to decide which GPIO been chosen + 0xBC 0x20 - 0x0000003E - FUNC192_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + ETM_TASK_GPIO28_EN + Enable bit of GPIO response etm task. 0 - 6 + 1 read-write - FUNC192_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 + ETM_TASK_GPIO28_SEL + GPIO choose a etm task channel. + 1 + 3 read-write - SIG192_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + ETM_TASK_GPIO29_EN + Enable bit of GPIO response etm task. + 8 1 read-write - - - - FUNC193_IN_SEL_CFG - GPIO input function configuration register - 0x45C - 0x20 - 0x0000003E - - FUNC193_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. - 0 - 6 + ETM_TASK_GPIO29_SEL + GPIO choose a etm task channel. + 9 + 3 read-write - FUNC193_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + ETM_TASK_GPIO30_EN + Enable bit of GPIO response etm task. + 16 1 read-write - SIG193_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + ETM_TASK_GPIO30_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + ETM_TASK_GPIO31_EN + Enable bit of GPIO response etm task. + 24 1 read-write + + ETM_TASK_GPIO31_SEL + GPIO choose a etm task channel. + 25 + 3 + read-write + - FUNC194_IN_SEL_CFG - GPIO input function configuration register - 0x460 + ETM_TASK_P8_CFG + Etm Configure Register to decide which GPIO been chosen + 0xC0 0x20 - 0x0000003E - FUNC194_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + ETM_TASK_GPIO32_EN + Enable bit of GPIO response etm task. 0 - 6 + 1 read-write - FUNC194_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 + ETM_TASK_GPIO32_SEL + GPIO choose a etm task channel. + 1 + 3 read-write - SIG194_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + ETM_TASK_GPIO33_EN + Enable bit of GPIO response etm task. + 8 1 read-write - - - - FUNC195_IN_SEL_CFG - GPIO input function configuration register - 0x464 - 0x20 - 0x0000003E - - FUNC195_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. - 0 - 6 + ETM_TASK_GPIO33_SEL + GPIO choose a etm task channel. + 9 + 3 read-write - FUNC195_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + ETM_TASK_GPIO34_EN + Enable bit of GPIO response etm task. + 16 1 read-write - SIG195_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + ETM_TASK_GPIO34_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + ETM_TASK_GPIO35_EN + Enable bit of GPIO response etm task. + 24 1 read-write + + ETM_TASK_GPIO35_SEL + GPIO choose a etm task channel. + 25 + 3 + read-write + - FUNC196_IN_SEL_CFG - GPIO input function configuration register - 0x468 + ETM_TASK_P9_CFG + Etm Configure Register to decide which GPIO been chosen + 0xC4 0x20 - 0x0000003E - FUNC196_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + ETM_TASK_GPIO36_EN + Enable bit of GPIO response etm task. 0 - 6 + 1 read-write - FUNC196_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 + ETM_TASK_GPIO36_SEL + GPIO choose a etm task channel. + 1 + 3 read-write - SIG196_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + ETM_TASK_GPIO37_EN + Enable bit of GPIO response etm task. + 8 1 read-write - - - - FUNC197_IN_SEL_CFG - GPIO input function configuration register - 0x46C - 0x20 - 0x0000003E - - FUNC197_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. - 0 - 6 + ETM_TASK_GPIO37_SEL + GPIO choose a etm task channel. + 9 + 3 read-write - FUNC197_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + ETM_TASK_GPIO38_EN + Enable bit of GPIO response etm task. + 16 1 read-write - SIG197_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + ETM_TASK_GPIO38_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + ETM_TASK_GPIO39_EN + Enable bit of GPIO response etm task. + 24 1 read-write + + ETM_TASK_GPIO39_SEL + GPIO choose a etm task channel. + 25 + 3 + read-write + - FUNC198_IN_SEL_CFG - GPIO input function configuration register - 0x470 + ETM_TASK_P10_CFG + Etm Configure Register to decide which GPIO been chosen + 0xC8 0x20 - 0x0000003E - FUNC198_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + ETM_TASK_GPIO40_EN + Enable bit of GPIO response etm task. 0 - 6 + 1 read-write - FUNC198_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 + ETM_TASK_GPIO40_SEL + GPIO choose a etm task channel. + 1 + 3 read-write - SIG198_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + ETM_TASK_GPIO41_EN + Enable bit of GPIO response etm task. + 8 1 read-write - - - - FUNC199_IN_SEL_CFG - GPIO input function configuration register - 0x474 - 0x20 - 0x0000003E - - FUNC199_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. - 0 - 6 + ETM_TASK_GPIO41_SEL + GPIO choose a etm task channel. + 9 + 3 read-write - FUNC199_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + ETM_TASK_GPIO42_EN + Enable bit of GPIO response etm task. + 16 1 read-write - SIG199_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + ETM_TASK_GPIO42_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + ETM_TASK_GPIO43_EN + Enable bit of GPIO response etm task. + 24 1 read-write + + ETM_TASK_GPIO43_SEL + GPIO choose a etm task channel. + 25 + 3 + read-write + - FUNC200_IN_SEL_CFG - GPIO input function configuration register - 0x478 + ETM_TASK_P11_CFG + Etm Configure Register to decide which GPIO been chosen + 0xCC 0x20 - 0x0000003E - FUNC200_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + ETM_TASK_GPIO44_EN + Enable bit of GPIO response etm task. 0 - 6 + 1 read-write - FUNC200_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 + ETM_TASK_GPIO44_SEL + GPIO choose a etm task channel. + 1 + 3 read-write - SIG200_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + ETM_TASK_GPIO45_EN + Enable bit of GPIO response etm task. + 8 1 read-write - - - - FUNC201_IN_SEL_CFG - GPIO input function configuration register - 0x47C - 0x20 - 0x0000003E - - FUNC201_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. - 0 - 6 + ETM_TASK_GPIO45_SEL + GPIO choose a etm task channel. + 9 + 3 read-write - FUNC201_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + ETM_TASK_GPIO46_EN + Enable bit of GPIO response etm task. + 16 1 read-write - SIG201_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + ETM_TASK_GPIO46_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + ETM_TASK_GPIO47_EN + Enable bit of GPIO response etm task. + 24 1 read-write + + ETM_TASK_GPIO47_SEL + GPIO choose a etm task channel. + 25 + 3 + read-write + - FUNC202_IN_SEL_CFG - GPIO input function configuration register - 0x480 + ETM_TASK_P12_CFG + Etm Configure Register to decide which GPIO been chosen + 0xD0 0x20 - 0x0000003E - FUNC202_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + ETM_TASK_GPIO48_EN + Enable bit of GPIO response etm task. 0 - 6 + 1 read-write - FUNC202_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 + ETM_TASK_GPIO48_SEL + GPIO choose a etm task channel. + 1 + 3 read-write - SIG202_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + ETM_TASK_GPIO49_EN + Enable bit of GPIO response etm task. + 8 1 read-write - - - - FUNC203_IN_SEL_CFG - GPIO input function configuration register - 0x484 - 0x20 - 0x0000003E - - FUNC203_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. - 0 - 6 + ETM_TASK_GPIO49_SEL + GPIO choose a etm task channel. + 9 + 3 read-write - FUNC203_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + ETM_TASK_GPIO50_EN + Enable bit of GPIO response etm task. + 16 1 read-write - SIG203_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + ETM_TASK_GPIO50_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + ETM_TASK_GPIO51_EN + Enable bit of GPIO response etm task. + 24 1 read-write + + ETM_TASK_GPIO51_SEL + GPIO choose a etm task channel. + 25 + 3 + read-write + - FUNC214_IN_SEL_CFG - GPIO input function configuration register - 0x4B0 + ETM_TASK_P13_CFG + Etm Configure Register to decide which GPIO been chosen + 0xD4 0x20 - 0x0000003E - FUNC214_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + ETM_TASK_GPIO52_EN + Enable bit of GPIO response etm task. 0 - 6 + 1 read-write - FUNC214_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 + ETM_TASK_GPIO52_SEL + GPIO choose a etm task channel. + 1 + 3 read-write - SIG214_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + ETM_TASK_GPIO53_EN + Enable bit of GPIO response etm task. + 8 1 read-write - - - - FUNC215_IN_SEL_CFG - GPIO input function configuration register - 0x4B4 - 0x20 - 0x0000003E - - FUNC215_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. - 0 - 6 + ETM_TASK_GPIO53_SEL + GPIO choose a etm task channel. + 9 + 3 read-write - FUNC215_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + ETM_TASK_GPIO54_EN + Enable bit of GPIO response etm task. + 16 1 read-write - SIG215_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 + ETM_TASK_GPIO54_SEL + GPIO choose a etm task channel. + 17 + 3 read-write - FUNC216_IN_SEL_CFG - GPIO input function configuration register - 0x4B8 + VERSION + Version Control Register + 0xFC 0x20 - 0x0000003E + 0x02203050 - FUNC216_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + GPIO_SD_DATE + Version control register. 0 - 6 - read-write - - - FUNC216_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG216_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 + 28 read-write + + + + H264 + H264 Encoder (Core) + H264 + 0x50084000 + + 0x0 + 0xF4 + registers + + + H264_REG + 126 + + - FUNC217_IN_SEL_CFG - GPIO input function configuration register - 0x4BC + SYS_CTRL + H264 system level control register. + 0x0 0x20 - 0x0000003E - FUNC217_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + FRAME_START + Configures whether or not to start encoding one frame.\\0: Invalid. No effect\\1: Start encoding one frame 0 - 6 - read-write + 1 + write-only - FUNC217_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + DMA_MOVE_START + Configures whether or not to start moving reference data from external mem.\\0: Invalid. No effect\\1: H264 start moving two MB lines of reference frame from external mem to internal mem + 1 1 - read-write + write-only - SIG217_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + FRAME_MODE + Configures H264 running mode. When field H264_DUAL_STREAM_MODE is set to 1, this field must be set to 1 too.\\0: GOP mode. Before every GOP first frame start, need reconfig reference frame DMA\\1: Frame mode. Before every frame start, need reconfig reference frame DMA + 2 1 read-write + + SYS_RST_PULSE + Configures whether or not to reset H264 ip.\\0: Invalid. No effect\\1: Reset H264 ip + 3 + 1 + write-only + - FUNC218_IN_SEL_CFG - GPIO input function configuration register - 0x4C0 + GOP_CONF + GOP related configuration register. + 0x4 0x20 - 0x0000003E - FUNC218_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + DUAL_STREAM_MODE + Configures whether or not to enable dual stream mode. When this field is set to 1, H264_FRAME_MODE field must be set to 1 too.\\0: Normal mode\\1: Dual stream mode 0 - 6 - read-write - - - FUNC218_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 1 read-write - SIG218_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 + GOP_NUM + Configures the frame number of one GOP.\\0: The frame number of one GOP is infinite\\Others: Actual frame number of one GOP + 1 + 8 read-write - FUNC219_IN_SEL_CFG - GPIO input function configuration register - 0x4C4 + A_SYS_MB_RES + Video A horizontal and vertical MB resolution register. + 0x8 0x20 - 0x0000003E - FUNC219_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + A_SYS_TOTAL_MB_Y + Configures video A vertical MB resolution. 0 - 6 - read-write - - - FUNC219_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 + 7 read-write - SIG219_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + A_SYS_TOTAL_MB_X + Configures video A horizontal MB resolution. 7 - 1 + 7 read-write - FUNC220_IN_SEL_CFG - GPIO input function configuration register - 0x4C8 + A_SYS_CONF + Video A system level configuration register. + 0xC 0x20 - 0x0000003E + 0x00000203 - FUNC220_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + A_DB_TMP_READY_TRIGGER_MB_NUM + Configures when to trigger video A H264_DB_TMP_READY_INT. When the (MB number of written db temp+1) is greater than this filed in first MB line, trigger H264_DB_TMP_READY_INT. Min is 3. 0 - 6 + 7 read-write - FUNC220_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 + A_REC_READY_TRIGGER_MB_LINES + Configures when to trigger video A H264_REC_READY_INT. When the MB line number of generated reconstruct pixel is greater than this filed, trigger H264_REC_READY_INT. Min is 4. + 7 + 7 read-write - SIG220_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 + A_INTRA_COST_CMP_OFFSET + Configures video A intra cost offset when I MB compared with P MB. + 14 + 16 read-write - FUNC221_IN_SEL_CFG - GPIO input function configuration register - 0x4CC + A_DECI_SCORE + Video A luma and chroma MB decimate score Register. + 0x10 0x20 - 0x0000003E - FUNC221_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + A_C_DECI_SCORE + Configures video A chroma MB decimate score. When chroma score is smaller than it, chroma decimate will be enable. 0 - 6 - read-write - - - FUNC221_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 + 10 read-write - SIG221_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 + A_L_DECI_SCORE + Configures video A luma MB decimate score. When luma score is smaller than it, luma decimate will be enable. + 10 + 10 read-write - FUNC222_IN_SEL_CFG - GPIO input function configuration register - 0x4D0 + A_DECI_SCORE_OFFSET + Video A luma and chroma MB decimate score offset Register. + 0x14 0x20 - 0x0000003E - FUNC222_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + A_I16X16_DECI_SCORE_OFFSET + Configures video A i16x16 MB decimate score offset. This offset will be added to i16x16 MB score. 0 6 read-write - FUNC222_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. + A_I_CHROMA_DECI_SCORE_OFFSET + Configures video A I chroma MB decimate score offset. This offset will be added to I chroma MB score. 6 - 1 + 6 read-write - SIG222_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 + A_P16X16_DECI_SCORE_OFFSET + Configures video A p16x16 MB decimate score offset. This offset will be added to p16x16 MB score. + 12 + 6 + read-write + + + A_P_CHROMA_DECI_SCORE_OFFSET + Configures video A p chroma MB decimate score offset. This offset will be added to p chroma MB score. + 18 + 6 read-write - FUNC223_IN_SEL_CFG - GPIO input function configuration register - 0x4D4 + A_RC_CONF0 + Video A rate control configuration register0. + 0x18 0x20 - 0x0000003E - FUNC223_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + A_QP + Configures video A frame level initial luma QP value. 0 6 read-write - FUNC223_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. + A_RATE_CTRL_U + Configures video A parameter U value. U = int((float) u << 8). 6 - 1 + 16 read-write - SIG223_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + A_MB_RATE_CTRL_EN + Configures video A whether or not to open macro block rate ctrl.\\1:Open the macro block rate ctrl\\1:Close the macro block rate ctrl. + 22 1 read-write - FUNC224_IN_SEL_CFG - GPIO input function configuration register - 0x4D8 + A_RC_CONF1 + Video A rate control configuration register1. + 0x1C 0x20 - 0x0000003E - FUNC224_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + A_CHROMA_DC_QP_DELTA + Configures video A chroma DC QP offset based on Chroma QP. Chroma DC QP = Chroma QP(after map) + reg_chroma_dc_qp_delta. 0 - 6 + 3 read-write - FUNC224_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 + A_CHROMA_QP_DELTA + Configures video A chroma QP offset based on luma QP. Chroma QP(before map) = Luma QP + reg_chroma_qp_delta. + 3 + 4 read-write - SIG224_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + A_QP_MIN + Configures video A allowed luma QP min value. 7 - 1 + 6 read-write - - - - FUNC225_IN_SEL_CFG - GPIO input function configuration register - 0x4DC - 0x20 - 0x0000003E - - FUNC225_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. - 0 + A_QP_MAX + Configures video A allowed luma QP max value. + 13 6 read-write - FUNC225_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 + A_MAD_FRAME_PRED + Configures vdieo A frame level predicted MB MAD value. + 19 + 12 read-write + + + + A_DB_BYPASS + Video A Deblocking bypass register + 0x20 + 0x20 + - SIG225_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + A_BYPASS_DB_FILTER + Configures whether or not to bypass video A deblcoking filter. \\0: Open the deblock filter\\1: Close the deblock filter + 0 1 read-write - FUNC226_IN_SEL_CFG - GPIO input function configuration register - 0x4E0 + A_ROI_REGION0 + Video A H264 ROI region0 range configure register. + 0x24 0x20 - 0x0000003E - FUNC226_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + X + Configures the horizontal start macroblocks of region 0 in Video A. 0 - 6 - read-write - - - FUNC226_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 + 7 read-write - SIG226_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + Y + Configures the vertical start macroblocks of region 0 in Video A. 7 - 1 + 7 read-write - - - - FUNC227_IN_SEL_CFG - GPIO input function configuration register - 0x4E4 - 0x20 - 0x0000003E - - FUNC227_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. - 0 - 6 + X_LEN + Configures the number of macroblocks in horizontal direction of the region 0 in Video A. + 14 + 7 read-write - FUNC227_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 + Y_LEN + Configures the number of macroblocks in vertical direction of the region 0 in Video A. + 21 + 7 read-write - SIG227_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + EN + Configures whether or not to open Video A ROI of region 0 .\\0:Close ROI\\1:Open ROI. + 28 1 read-write - FUNC228_IN_SEL_CFG - GPIO input function configuration register - 0x4E8 + A_ROI_REGION1 + Video A H264 ROI region1 range configure register. + 0x28 0x20 - 0x0000003E - FUNC228_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + X + Configures the horizontal start macroblocks of region 1 in Video A. 0 - 6 - read-write - - - FUNC228_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 + 7 read-write - SIG228_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + Y + Configures the vertical start macroblocks of region 1 in Video A. 7 - 1 + 7 read-write - - - - FUNC229_IN_SEL_CFG - GPIO input function configuration register - 0x4EC - 0x20 - 0x0000003E - - FUNC229_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. - 0 - 6 + X_LEN + Configures the number of macroblocks in horizontal direction of the region 1 in Video A. + 14 + 7 read-write - FUNC229_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 + Y_LEN + Configures the number of macroblocks in vertical direction of the region 1 in Video A. + 21 + 7 read-write - SIG229_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + EN + Configures whether or not to open Video A ROI of region 1 .\\0:Close ROI\\1:Open ROI. + 28 1 read-write - FUNC230_IN_SEL_CFG - GPIO input function configuration register - 0x4F0 + A_ROI_REGION2 + Video A H264 ROI region2 range configure register. + 0x2C 0x20 - 0x0000003E - FUNC230_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + X + Configures the horizontal start macroblocks of region 2 in Video A. 0 - 6 + 7 read-write - FUNC230_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 + Y + Configures the vertical start macroblocks of region 2 in Video A. + 7 + 7 read-write - SIG230_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + X_LEN + Configures the number of macroblocks in horizontal direction of the region 2 in Video A. + 14 + 7 + read-write + + + Y_LEN + Configures the number of macroblocks in vertical direction of the region 2 in Video A. + 21 + 7 + read-write + + + EN + Configures whether or not to open Video A ROI of region 2 .\\0:Close ROI\\1:Open ROI. + 28 1 read-write - FUNC231_IN_SEL_CFG - GPIO input function configuration register - 0x4F4 + A_ROI_REGION3 + Video A H264 ROI region3 range configure register. + 0x30 0x20 - 0x0000003E - FUNC231_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + X + Configures the horizontal start macroblocks of region 3 in Video A. 0 - 6 + 7 read-write - FUNC231_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 + Y + Configures the vertical start macroblocks of region 3 in Video A. + 7 + 7 read-write - SIG231_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + X_LEN + Configures the number of macroblocks in horizontal direction of the region 3 in video A. + 14 + 7 + read-write + + + Y_LEN + Configures the number of macroblocks in vertical direction of the region 3 in video A. + 21 + 7 + read-write + + + EN + Configures whether or not to open Video A ROI of region 3 .\\0:Close ROI\\1:Open ROI. + 28 1 read-write - FUNC232_IN_SEL_CFG - GPIO input function configuration register - 0x4F8 + A_ROI_REGION4 + Video A H264 ROI region4 range configure register. + 0x34 0x20 - 0x0000003E - FUNC232_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + X + Configures the horizontal start macroblocks of region 4 in Video A. 0 - 6 + 7 read-write - FUNC232_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 + Y + Configures the vertical start macroblocks of region 4 in Video A. + 7 + 7 read-write - SIG232_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + X_LEN + Configures the number of macroblocks in horizontal direction of the region 4 in video A. + 14 + 7 + read-write + + + Y_LEN + Configures the number of macroblocks in vertical direction of the region 4 in video A. + 21 + 7 + read-write + + + EN + Configures whether or not to open Video A ROI of region 4 .\\0:Close ROI\\1:Open ROI. + 28 1 read-write - FUNC233_IN_SEL_CFG - GPIO input function configuration register - 0x4FC + A_ROI_REGION5 + Video A H264 ROI region5 range configure register. + 0x38 0x20 - 0x0000003E - FUNC233_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + X + Configures the horizontial start macroblocks of region 5 video A. 0 - 6 + 7 read-write - FUNC233_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 + Y + Configures the vertical start macroblocks of region 5 video A. + 7 + 7 read-write - SIG233_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + X_LEN + Configures the number of macroblocks in horizontal direction of the region 5 video A. + 14 + 7 + read-write + + + Y_LEN + Configures the number of macroblocks in vertical direction of the region 5 in video A. + 21 + 7 + read-write + + + EN + Configures whether or not to open Video A ROI of region 5 .\\0:Close ROI\\1:Open ROI. + 28 1 read-write - FUNC234_IN_SEL_CFG - GPIO input function configuration register - 0x500 + A_ROI_REGION6 + Video A H264 ROI region6 range configure register. + 0x3C 0x20 - 0x0000003E - FUNC234_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + X + Configures the horizontial start macroblocks of region 6 video A. 0 - 6 + 7 read-write - FUNC234_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 + Y + Configures the vertical start macroblocks of region 6 in video A. + 7 + 7 read-write - SIG234_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + X_LEN + Configures the number of macroblocks in horizontal direction of the region 6 in video A. + 14 + 7 + read-write + + + Y_LEN + Configures the number of macroblocks in vertical direction of the region 6 in video A. + 21 + 7 + read-write + + + EN + Configures whether or not to open Video A ROI of region 6 .\\0:Close ROI\\1:Open ROI. + 28 1 read-write - FUNC235_IN_SEL_CFG - GPIO input function configuration register - 0x504 + A_ROI_REGION7 + Video A H264 ROI region7 range configure register. + 0x40 0x20 - 0x0000003E - FUNC235_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + X + Configures the horizontal start macroblocks of region 7 in video A. 0 - 6 + 7 read-write - FUNC235_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 + Y + Configures the vertical start macroblocks of region 7 in video A. + 7 + 7 read-write - SIG235_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + X_LEN + Configures the number of macroblocks in horizontal direction of the region 7 in video A. + 14 + 7 + read-write + + + Y_LEN + Configures the number of macroblocks in vertical direction of the region 7 in video A. + 21 + 7 + read-write + + + EN + Configures whether or not to open Video A ROI of region 7 .\\0:Close ROI\\1:Open ROI. + 28 1 read-write - FUNC236_IN_SEL_CFG - GPIO input function configuration register - 0x508 + A_ROI_REGION0_3_QP + Video A H264 ROI region0, region1,region2,region3 QP register. + 0x44 0x20 - 0x0000003E - FUNC236_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + A_ROI_REGION0_QP + Configure H264 ROI region0 qp in video A,fixed qp or delta qp. 0 - 6 + 7 read-write - FUNC236_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 + A_ROI_REGION1_QP + Configure H264 ROI region1 qp in video A,fixed qp or delta qp. + 7 + 7 read-write - SIG236_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 + A_ROI_REGION2_QP + Configure H264 ROI region2 qp in video A,fixed qp or delta qp. + 14 + 7 + read-write + + + A_ROI_REGION3_QP + Configure H264 ROI region3 qp in video A,fixed qp or delta qp. + 21 + 7 read-write - FUNC237_IN_SEL_CFG - GPIO input function configuration register - 0x50C + A_ROI_REGION4_7_QP + Video A H264 ROI region4, region5,region6,region7 QP register. + 0x48 0x20 - 0x0000003E - FUNC237_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + A_ROI_REGION4_QP + Configure H264 ROI region4 qp in video A,fixed qp or delta qp. 0 - 6 + 7 read-write - FUNC237_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 + A_ROI_REGION5_QP + Configure H264 ROI region5 qp in video A,fixed qp or delta qp. + 7 + 7 read-write - SIG237_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 + A_ROI_REGION6_QP + Configure H264 ROI region6 qp in video A,fixed qp or delta qp. + 14 + 7 + read-write + + + A_ROI_REGION7_QP + Configure H264 ROI region7 qp in video A,fixed qp or delta qp. + 21 + 7 read-write - FUNC238_IN_SEL_CFG - GPIO input function configuration register - 0x510 + A_NO_ROI_REGION_QP_OFFSET + Video A H264 no roi region QP register. + 0x4C 0x20 - 0x0000003E - FUNC238_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + A_NO_ROI_REGION_QP + Configure H264 no region qp in video A, delta qp. 0 - 6 + 7 read-write + + + + A_ROI_CONFIG + Video A H264 ROI configure register. + 0x50 + 0x20 + - FUNC238_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + A_ROI_EN + Configure whether or not to enable ROI in video A.\\0:not enable ROI\\1:enable ROI. + 0 1 read-write - SIG238_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + A_ROI_MODE + Configure the mode of ROI in video A.\\0:fixed qp\\1:delta qp. + 1 1 read-write - FUNC239_IN_SEL_CFG - GPIO input function configuration register - 0x514 + B_SYS_MB_RES + Video B horizontal and vertical MB resolution register. + 0x54 0x20 - 0x0000003E - FUNC239_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + B_SYS_TOTAL_MB_Y + Configures video B vertical MB resolution. 0 - 6 - read-write - - - FUNC239_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 + 7 read-write - SIG239_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + B_SYS_TOTAL_MB_X + Configures video B horizontal MB resolution. 7 - 1 + 7 read-write - FUNC240_IN_SEL_CFG - GPIO input function configuration register - 0x518 + B_SYS_CONF + Video B system level configuration register. + 0x58 0x20 - 0x0000003E + 0x00000203 - FUNC240_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + B_DB_TMP_READY_TRIGGER_MB_NUM + Configures when to trigger video B H264_DB_TMP_READY_INT. When the (MB number of written db temp+1) is greater than this filed in first MB line, trigger H264_DB_TMP_READY_INT. Min is 3. 0 - 6 + 7 read-write - FUNC240_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 + B_REC_READY_TRIGGER_MB_LINES + Configures when to trigger video B H264_REC_READY_INT. When the MB line number of generated reconstruct pixel is greater than this filed, trigger H264_REC_READY_INT. Min is 4. + 7 + 7 read-write - SIG240_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 + B_INTRA_COST_CMP_OFFSET + Configures video B intra cost offset when I MB compared with P MB. + 14 + 16 read-write - FUNC241_IN_SEL_CFG - GPIO input function configuration register - 0x51C + B_DECI_SCORE + Video B luma and chroma MB decimate score Register. + 0x5C 0x20 - 0x0000003E - FUNC241_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + B_C_DECI_SCORE + Configures video B chroma MB decimate score. When chroma score is smaller than it, chroma decimate will be enable. 0 - 6 - read-write - - - FUNC241_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 + 10 read-write - SIG241_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 + B_L_DECI_SCORE + Configures video B luma MB decimate score. When luma score is smaller than it, luma decimate will be enable. + 10 + 10 read-write - FUNC242_IN_SEL_CFG - GPIO input function configuration register - 0x520 + B_DECI_SCORE_OFFSET + Video B luma and chroma MB decimate score offset Register. + 0x60 0x20 - 0x0000003E - FUNC242_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + B_I16X16_DECI_SCORE_OFFSET + Configures video B i16x16 MB decimate score offset. This offset will be added to i16x16 MB score. 0 6 read-write - FUNC242_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. + B_I_CHROMA_DECI_SCORE_OFFSET + Configures video B I chroma MB decimate score offset. This offset will be added to I chroma MB score. 6 - 1 + 6 read-write - SIG242_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 + B_P16X16_DECI_SCORE_OFFSET + Configures video B p16x16 MB decimate score offset. This offset will be added to p16x16 MB score. + 12 + 6 + read-write + + + B_P_CHROMA_DECI_SCORE_OFFSET + Configures video B p chroma MB decimate score offset. This offset will be added to p chroma MB score. + 18 + 6 read-write - FUNC243_IN_SEL_CFG - GPIO input function configuration register - 0x524 + B_RC_CONF0 + Video B rate control configuration register0. + 0x64 0x20 - 0x0000003E - FUNC243_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + B_QP + Configures video B frame level initial luma QP value. 0 6 read-write - FUNC243_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. + B_RATE_CTRL_U + Configures video B parameter U value. U = int((float) u << 8). 6 - 1 + 16 read-write - SIG243_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + B_MB_RATE_CTRL_EN + Configures video A whether or not to open macro block rate ctrl.\\1:Open the macro block rate ctrl\\1:Close the macro block rate ctrl. + 22 1 read-write - FUNC244_IN_SEL_CFG - GPIO input function configuration register - 0x528 + B_RC_CONF1 + Video B rate control configuration register1. + 0x68 0x20 - 0x0000003E - FUNC244_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + B_CHROMA_DC_QP_DELTA + Configures video B chroma DC QP offset based on Chroma QP. Chroma DC QP = Chroma QP(after map) + reg_chroma_dc_qp_delta. 0 - 6 + 3 read-write - FUNC244_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 + B_CHROMA_QP_DELTA + Configures video B chroma QP offset based on luma QP. Chroma QP(before map) = Luma QP + reg_chroma_qp_delta. + 3 + 4 read-write - SIG244_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + B_QP_MIN + Configures video B allowed luma QP min value. 7 - 1 + 6 read-write - - - - FUNC245_IN_SEL_CFG - GPIO input function configuration register - 0x52C - 0x20 - 0x0000003E - - FUNC245_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. - 0 + B_QP_MAX + Configures video B allowed luma QP max value. + 13 6 read-write - FUNC245_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 + B_MAD_FRAME_PRED + Configures vdieo B frame level predicted MB MAD value. + 19 + 12 read-write + + + + B_DB_BYPASS + Video B Deblocking bypass register + 0x6C + 0x20 + - SIG245_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + B_BYPASS_DB_FILTER + Configures whether or not to bypass video B deblcoking filter. \\0: Open the deblock filter\\1: Close the deblock filter + 0 1 read-write - FUNC246_IN_SEL_CFG - GPIO input function configuration register - 0x530 + B_ROI_REGION0 + Video B H264 ROI region0 range configure register. + 0x70 0x20 - 0x0000003E - FUNC246_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + X + Configures the horizontal start macroblocks of region 0 in Video B. 0 - 6 + 7 read-write - FUNC246_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 + Y + Configures the vertical start macroblocks of region 0 in Video B. + 7 + 7 read-write - SIG246_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + X_LEN + Configures the number of macroblocks in horizontal direction of the region 0 in Video B. + 14 + 7 + read-write + + + Y_LEN + Configures the number of macroblocks in vertical direction of the region 0 in Video B. + 21 + 7 + read-write + + + EN + Configures whether or not to open Video B ROI of region 0 .\\0:Close ROI\\1:Open ROI. + 28 1 read-write - FUNC247_IN_SEL_CFG - GPIO input function configuration register - 0x534 + B_ROI_REGION1 + Video B H264 ROI region1 range configure register. + 0x74 0x20 - 0x0000003E - FUNC247_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + X + Configures the horizontal start macroblocks of region 1 in Video B. 0 - 6 + 7 read-write - FUNC247_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 + Y + Configures the vertical start macroblocks of region 1 in Video B. + 7 + 7 read-write - SIG247_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + X_LEN + Configures the number of macroblocks in horizontal direction of the region 1 in Video B. + 14 + 7 + read-write + + + Y_LEN + Configures the number of macroblocks in vertical direction of the region 1 in Video B. + 21 + 7 + read-write + + + EN + Configures whether or not to open Video B ROI of region 1 .\\0:Close ROI\\1:Open ROI. + 28 1 read-write - FUNC248_IN_SEL_CFG - GPIO input function configuration register - 0x538 + B_ROI_REGION2 + Video B H264 ROI region2 range configure register. + 0x78 0x20 - 0x0000003E - FUNC248_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + X + Configures the horizontal start macroblocks of region 2 in Video B. 0 - 6 + 7 read-write - FUNC248_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 + Y + Configures the vertical start macroblocks of region 2 in Video B. + 7 + 7 read-write - SIG248_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + X_LEN + Configures the number of macroblocks in horizontal direction of the region 2 in Video B. + 14 + 7 + read-write + + + Y_LEN + Configures the number of macroblocks in vertical direction of the region 2 in Video B. + 21 + 7 + read-write + + + EN + Configures whether or not to open Video B ROI of region 2 .\\0:Close ROI\\1:Open ROI. + 28 1 read-write - FUNC249_IN_SEL_CFG - GPIO input function configuration register - 0x53C + B_ROI_REGION3 + Video B H264 ROI region3 range configure register. + 0x7C 0x20 - 0x0000003E - FUNC249_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + X + Configures the horizontal start macroblocks of region 3 in Video B. 0 - 6 + 7 read-write - FUNC249_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 + Y + Configures the vertical start macroblocks of region 3 in Video B. + 7 + 7 read-write - SIG249_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + X_LEN + Configures the number of macroblocks in horizontal direction of the region 3 in video B. + 14 + 7 + read-write + + + Y_LEN + Configures the number of macroblocks in vertical direction of the region 3 in video B. + 21 + 7 + read-write + + + EN + Configures whether or not to open Video B ROI of region 3 .\\0:Close ROI\\1:Open ROI. + 28 1 read-write - FUNC250_IN_SEL_CFG - GPIO input function configuration register - 0x540 + B_ROI_REGION4 + Video B H264 ROI region4 range configure register. + 0x80 0x20 - 0x0000003E - FUNC250_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + X + Configures the horizontal start macroblocks of region 4 in Video B. 0 - 6 + 7 read-write - FUNC250_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 + Y + Configures the vertical start macroblocks of region 4 in Video B. + 7 + 7 read-write - SIG250_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + X_LEN + Configures the number of macroblocks in horizontal direction of the region 4 in video B. + 14 + 7 + read-write + + + Y_LEN + Configures the number of macroblocks in vertical direction of the region 4 in video B. + 21 + 7 + read-write + + + EN + Configures whether or not to open Video B ROI of region 4 .\\0:Close ROI\\1:Open ROI. + 28 1 read-write - FUNC251_IN_SEL_CFG - GPIO input function configuration register - 0x544 + B_ROI_REGION5 + Video B H264 ROI region5 range configure register. + 0x84 0x20 - 0x0000003E - FUNC251_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + X + Configures the horizontial start macroblocks of region 5 video B. 0 - 6 + 7 read-write - FUNC251_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 + Y + Configures the vertical start macroblocks of region 5 video B. + 7 + 7 read-write - SIG251_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + X_LEN + Configures the number of macroblocks in horizontal direction of the region 5 video B. + 14 + 7 + read-write + + + Y_LEN + Configures the number of macroblocks in vertical direction of the region 5 in video B. + 21 + 7 + read-write + + + EN + Configures whether or not to open Video B ROI of region 5 .\\0:Close ROI\\1:Open ROI. + 28 1 read-write - FUNC252_IN_SEL_CFG - GPIO input function configuration register - 0x548 + B_ROI_REGION6 + Video B H264 ROI region6 range configure register. + 0x88 0x20 - 0x0000003E - FUNC252_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + X + Configures the horizontial start macroblocks of region 6 video B. 0 - 6 + 7 read-write - FUNC252_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 + Y + Configures the vertical start macroblocks of region 6 in video B. + 7 + 7 read-write - SIG252_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + X_LEN + Configures the number of macroblocks in horizontal direction of the region 6 in video B. + 14 + 7 + read-write + + + Y_LEN + Configures the number of macroblocks in vertical direction of the region 6 in video B. + 21 + 7 + read-write + + + EN + Configures whether or not to open Video B ROI of region 6 .\\0:Close ROI\\1:Open ROI. + 28 1 read-write - FUNC253_IN_SEL_CFG - GPIO input function configuration register - 0x54C + B_ROI_REGION7 + Video B H264 ROI region7 range configure register. + 0x8C 0x20 - 0x0000003E - FUNC253_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + X + Configures the horizontal start macroblocks of region 7 in video B. 0 - 6 + 7 read-write - FUNC253_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 + Y + Configures the vertical start macroblocks of region 7 in video B. + 7 + 7 read-write - SIG253_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + X_LEN + Configures the number of macroblocks in horizontal direction of the region 7 in video B. + 14 + 7 + read-write + + + Y_LEN + Configures the number of macroblocks in vertical direction of the region 7 in video B. + 21 + 7 + read-write + + + EN + Configures whether or not to open Video B ROI of region 7 .\\0:Close ROI\\1:Open ROI. + 28 1 read-write - FUNC254_IN_SEL_CFG - GPIO input function configuration register - 0x550 + B_ROI_REGION0_3_QP + Video B H264 ROI region0, region1,region2,region3 QP register. + 0x90 0x20 - 0x0000003E - FUNC254_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + B_ROI_REGION0_QP + Configure H264 ROI region0 qp in video B,fixed qp or delta qp. 0 - 6 + 7 read-write - FUNC254_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 + B_ROI_REGION1_QP + Configure H264 ROI region1 qp in video B,fixed qp or delta qp. + 7 + 7 read-write - SIG254_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 + B_ROI_REGION2_QP + Configure H264 ROI region2 qp in video B,fixed qp or delta qp. + 14 + 7 + read-write + + + B_ROI_REGION3_QP + Configure H264 ROI region3 qp in video B,fixed qp or delta qp. + 21 + 7 read-write - FUNC255_IN_SEL_CFG - GPIO input function configuration register - 0x554 + B_ROI_REGION4_7_QP + Video B H264 ROI region4, region5,region6,region7 QP register. + 0x94 0x20 - 0x0000003E - FUNC255_IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + B_ROI_REGION4_QP + Configure H264 ROI region4 qp in video B,fixed qp or delta qp. 0 - 6 + 7 read-write - FUNC255_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 + B_ROI_REGION5_QP + Configure H264 ROI region5 qp in video B,fixed qp or delta qp. + 7 + 7 read-write - SIG255_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 + B_ROI_REGION6_QP + Configure H264 ROI region6 qp in video B,fixed qp or delta qp. + 14 + 7 + read-write + + + B_ROI_REGION7_QP + Configure H264 ROI region7 qp in video B,fixed qp or delta qp. + 21 + 7 read-write - 57 - 0x4 - FUNC%s_OUT_SEL_CFG - GPIO output function select register - 0x558 + B_NO_ROI_REGION_QP_OFFSET + Video B H264 no roi region QP register. + 0x98 0x20 - 0x00000100 - FUNC_OUT_SEL - The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. + B_NO_ROI_REGION_QP + Configure H264 no region qp in video B, delta qp. 0 - 9 - read-write - - - FUNC_OUT_INV_SEL - set this bit to invert output signal.1:invert.0:not invert. - 9 - 1 + 7 read-write + + + + B_ROI_CONFIG + Video B H264 ROI configure register. + 0x9C + 0x20 + - FUNC_OEN_SEL - set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output enable signal.0:use peripheral output enable signal. - 10 + B_ROI_EN + Configure whether or not to enable ROI in video B.\\0:not enable ROI\\1:enable ROI. + 0 1 read-write - FUNC_OEN_INV_SEL - set this bit to invert output enable signal.1:invert.0:not invert. - 11 + B_ROI_MODE + Configure the mode of ROI in video B.\\0:fixed qp\\1:delta qp. + 1 1 read-write - INTR_2 - GPIO interrupt 2 status register for GPIO0-31 - 0x63C + RC_STATUS0 + Rate control status register0. + 0xA0 0x20 - INT_2 - GPIO interrupt 2 status register for GPIO0-31 + FRAME_MAD_SUM + Represents all MB actual MAD sum value of one frame. 0 - 32 + 21 read-only - INTR1_2 - GPIO interrupt 2 status register for GPIO32-56 - 0x640 + RC_STATUS1 + Rate control status register1. + 0xA4 0x20 - INT1_2 - GPIO interrupt 2 status register for GPIO32-56 + FRAME_ENC_BITS + Represents all MB actual encoding bits sum value of one frame. 0 - 25 + 27 read-only - INTR_3 - GPIO interrupt 3 status register for GPIO0-31 - 0x644 + RC_STATUS2 + Rate control status register2. + 0xA8 0x20 - INT_3 - GPIO interrupt 3 status register for GPIO0-31 + FRAME_QP_SUM + Represents all MB actual luma QP sum value of one frame. 0 - 32 + 19 read-only - INTR1_3 - GPIO interrupt 3 status register for GPIO32-56 - 0x648 + SLICE_HEADER_REMAIN + Frame Slice Header remain bit register. + 0xAC 0x20 - INT1_3 - GPIO interrupt 3 status register for GPIO32-56 + SLICE_REMAIN_BITLENGTH + Configures Slice Header remain bit number 0 - 25 - read-only + 3 + read-write + + + SLICE_REMAIN_BIT + Configures Slice Header remain bit + 3 + 8 + read-write - CLOCK_GATE - GPIO clock gate register - 0x64C + SLICE_HEADER_BYTE_LENGTH + Frame Slice Header byte length register. + 0xB0 0x20 - 0x00000001 - CLK_EN - set this bit to enable GPIO clock gate + SLICE_BYTE_LENGTH + Configures Slice Header byte number 0 - 1 + 4 read-write - INT_RAW - analog comparator interrupt raw - 0x700 + BS_THRESHOLD + Bitstream buffer overflow threshold register + 0xB4 0x20 + 0x00000030 - COMP0_NEG_INT_RAW - analog comparator pos edge interrupt raw + BS_BUFFER_THRESHOLD + Configures bitstream buffer overflow threshold. This value should be bigger than the encode bytes of one 4x4 submb. 0 - 1 - read-write - - - COMP0_POS_INT_RAW - analog comparator neg edge interrupt raw - 1 - 1 + 7 read-write + + + + SLICE_HEADER_BYTE0 + Frame Slice Header byte low 32 bit register. + 0xB8 + 0x20 + - COMP0_ALL_INT_RAW - analog comparator neg or pos edge interrupt raw - 2 - 1 + SLICE_BYTE_LSB + Configures Slice Header low 32 bit + 0 + 32 read-write + + + + SLICE_HEADER_BYTE1 + Frame Slice Header byte high 32 bit register. + 0xBC + 0x20 + - COMP1_NEG_INT_RAW - analog comparator pos edge interrupt raw - 3 - 1 + SLICE_BYTE_MSB + Configures Slice Header high 32 bit + 0 + 32 read-write + + + + INT_RAW + Interrupt raw status register + 0xC0 + 0x20 + - COMP1_POS_INT_RAW - analog comparator neg edge interrupt raw - 4 + DB_TMP_READY_INT_RAW + Raw status bit: The raw interrupt status of H264_DB_TMP_READY_INT. Triggered when H264 written enough db tmp pixel. + 0 1 read-write - COMP1_ALL_INT_RAW - analog comparator neg or pos edge interrupt raw - 5 + REC_READY_INT_RAW + Raw status bit: The raw interrupt status of H264_REC_READY_INT. Triggered when H264 encoding enough reconstruct pixel. + 1 1 read-write - BISTOK_INT_RAW - pad bistok interrupt raw - 6 + FRAME_DONE_INT_RAW + Raw status bit: The raw interrupt status of H264_FRAME_DONE_INT. Triggered when H264 encoding one frame done. + 2 1 read-write - BISTFAIL_INT_RAW - pad bistfail interrupt raw - 7 + DMA_MOVE_2MB_LINE_DONE_INT_RAW + Raw status bit: The raw interrupt status of H264_DMA_MOVE_2MB_LINE_DONE_INT. Triggered when H264 move two MB lines of reference frame from external mem to internal mem done. + 3 1 read-write @@ -44540,3703 +42555,3795 @@ INT_ST - analog comparator interrupt status - 0x704 + Interrupt masked status register + 0xC4 0x20 - COMP0_NEG_INT_ST - analog comparator pos edge interrupt status + DB_TMP_READY_INT_ST + The masked interrupt status of H264_DB_TMP_READY_INT. Valid only when the H264_DB_TMP_READY_INT_ENA is set to 1. 0 1 read-only - COMP0_POS_INT_ST - analog comparator neg edge interrupt status + REC_READY_INT_ST + The masked interrupt status of H264_REC_READY_INT. Valid only when the H264_REC_READY_INT_ENA is set to 1. 1 1 read-only - COMP0_ALL_INT_ST - analog comparator neg or pos edge interrupt status + FRAME_DONE_INT_ST + The masked interrupt status of H264_FRAME_DONE_INT. Valid only when the H264_FRAME_DONE_INT_ENA is set to 1. 2 1 read-only - COMP1_NEG_INT_ST - analog comparator pos edge interrupt status + DMA_MOVE_2MB_LINE_DONE_INT_ST + Masked status bit: The masked interrupt status of H264_DMA_MOVE_2MB_LINE_DONE_INT. Valid only when the H264_DMA_MOVE_2MB_LINE_DONE_INT_ENA is set to 1. 3 1 read-only - - COMP1_POS_INT_ST - analog comparator neg edge interrupt status - 4 - 1 - read-only - - - COMP1_ALL_INT_ST - analog comparator neg or pos edge interrupt status - 5 - 1 - read-only - - - BISTOK_INT_ST - pad bistok interrupt status - 6 - 1 - read-only - - - BISTFAIL_INT_ST - pad bistfail interrupt status - 7 - 1 - read-only - INT_ENA - analog comparator interrupt enable - 0x708 + Interrupt enable register + 0xC8 0x20 - 0x000000FF - COMP0_NEG_INT_ENA - analog comparator pos edge interrupt enable + DB_TMP_READY_INT_ENA + Write 1 to enable H264_DB_TMP_READY_INT. 0 1 read-write - COMP0_POS_INT_ENA - analog comparator neg edge interrupt enable + REC_READY_INT_ENA + Write 1 to enable H264_REC_READY_INT. 1 1 read-write - COMP0_ALL_INT_ENA - analog comparator neg or pos edge interrupt enable + FRAME_DONE_INT_ENA + Write 1 to enable H264_FRAME_DONE_INT. 2 1 read-write - COMP1_NEG_INT_ENA - analog comparator pos edge interrupt enable + DMA_MOVE_2MB_LINE_DONE_INT_ENA + Enable bit: Write 1 to enable H264_DMA_MOVE_2MB_LINE_DONE_INT. 3 1 read-write - - COMP1_POS_INT_ENA - analog comparator neg edge interrupt enable - 4 - 1 - read-write - - - COMP1_ALL_INT_ENA - analog comparator neg or pos edge interrupt enable - 5 - 1 - read-write - - - BISTOK_INT_ENA - pad bistok interrupt enable - 6 - 1 - read-write - - - BISTFAIL_INT_ENA - pad bistfail interrupt enable - 7 - 1 - read-write - INT_CLR - analog comparator interrupt clear - 0x70C + Interrupt clear register + 0xCC 0x20 - COMP0_NEG_INT_CLR - analog comparator pos edge interrupt clear + DB_TMP_READY_INT_CLR + Write 1 to clear H264_DB_TMP_READY_INT. 0 1 write-only - COMP0_POS_INT_CLR - analog comparator neg edge interrupt clear + REC_READY_INT_CLR + Write 1 to clear H264_REC_READY_INT. 1 1 write-only - COMP0_ALL_INT_CLR - analog comparator neg or pos edge interrupt clear + FRAME_DONE_INT_CLR + Write 1 to clear H264_FRAME_DONE_INT. 2 1 write-only - COMP1_NEG_INT_CLR - analog comparator pos edge interrupt clear + DMA_MOVE_2MB_LINE_DONE_INT_CLR + Clear bit: Write 1 to clear H264_DMA_MOVE_2MB_LINE_DONE_INT. 3 1 write-only - - COMP1_POS_INT_CLR - analog comparator neg edge interrupt clear - 4 - 1 - write-only - - - COMP1_ALL_INT_CLR - analog comparator neg or pos edge interrupt clear - 5 - 1 - write-only - - - BISTOK_INT_CLR - pad bistok interrupt enable - 6 - 1 - write-only - - - BISTFAIL_INT_CLR - pad bistfail interrupt enable - 7 - 1 - write-only - - ZERO_DET0_FILTER_CNT - GPIO analog comparator zero detect filter count - 0x710 + CONF + General configuration register. + 0xD0 0x20 - 0xFFFFFFFF - ZERO_DET0_FILTER_CNT - GPIO analog comparator zero detect filter count + CLK_EN + Configures whether or not to open register clock gate.\\0: Open the clock gate only when application writes registers\\1: Force open the clock gate for register 0 - 32 + 1 read-write - - - - ZERO_DET1_FILTER_CNT - GPIO analog comparator zero detect filter count - 0x714 - 0x20 - 0xFFFFFFFF - - ZERO_DET1_FILTER_CNT - GPIO analog comparator zero detect filter count - 0 - 32 + REC_RAM_CLK_EN2 + Configures whether or not to open the clock gate for rec ram2.\\0: Open the clock gate only when application writes or reads rec ram2\\1: Force open the clock gate for rec ram2 + 1 + 1 read-write - - - - SEND_SEQ - High speed sdio pad bist send sequence - 0x718 - 0x20 - 0x12345678 - - SEND_SEQ - High speed sdio pad bist send sequence - 0 - 32 + REC_RAM_CLK_EN1 + Configures whether or not to open the clock gate for rec ram1.\\0: Open the clock gate only when application writes or reads rec ram1\\1: Force open the clock gate for rec ram1 + 2 + 1 read-write - - - - RECIVE_SEQ - High speed sdio pad bist recive sequence - 0x71C - 0x20 - - - RECIVE_SEQ - High speed sdio pad bist recive sequence - 0 - 32 - read-only - - - - - BISTIN_SEL - High speed sdio pad bist in pad sel - 0x720 - 0x20 - 0x0000000F - - BISTIN_SEL - High speed sdio pad bist in pad sel 0:pad39, 1: pad40... - 0 - 4 + QUANT_RAM_CLK_EN2 + Configures whether or not to open the clock gate for quant ram2.\\0: Open the clock gate only when application writes or reads quant ram2\\1: Force open the clock gate for quant ram2 + 3 + 1 read-write - - - - BIST_CTRL - High speed sdio pad bist control - 0x724 - 0x20 - 0x00000001 - - BIST_PAD_OE - High speed sdio pad bist out pad oe - 0 + QUANT_RAM_CLK_EN1 + Configures whether or not to open the clock gate for quant ram1.\\0: Open the clock gate only when application writes or reads quant ram1\\1: Force open the clock gate for quant ram1 + 4 1 read-write - BIST_START - High speed sdio pad bist start - 1 + PRE_RAM_CLK_EN + Configures whether or not to open the clock gate for pre ram.\\0: Open the clock gate only when application writes or reads pre ram\\1: Force open the clock gate for pre ram + 5 1 - write-only + read-write - - - - DATE - GPIO version register - 0x7FC - 0x20 - 0x00230403 - - DATE - version register - 0 - 28 + MVD_RAM_CLK_EN + Configures whether or not to open the clock gate for mvd ram.\\0: Open the clock gate only when application writes or reads mvd ram\\1: Force open the clock gate for mvd ram + 6 + 1 read-write - - - - - - GPIO_SD - Sigma-Delta Modulation - GPIOSD - 0x500E0F00 - - 0x0 - 0xA4 - registers - - - - 8 - 0x4 - SIGMADELTA%s - Duty Cycle Configure Register of SDM%s - 0x0 - 0x20 - 0x0000FF00 - - SD_IN - This field is used to configure the duty cycle of sigma delta modulation output. - 0 - 8 + MC_RAM_CLK_EN + Configures whether or not to open the clock gate for mc ram.\\0: Open the clock gate only when application writes or reads mc ram\\1: Force open the clock gate for mc ram + 7 + 1 read-write - SD_PRESCALE - This field is used to set a divider value to divide APB clock. + REF_RAM_CLK_EN + Configures whether or not to open the clock gate for ref ram.\\0: Open the clock gate only when application writes or reads ref ram\\1: Force open the clock gate for ref ram 8 - 8 + 1 read-write - - - - CLOCK_GATE - Clock Gating Configure Register - 0x20 - 0x20 - - CLK_EN - Clock enable bit of configuration registers for sigma delta modulation. - 0 + I4X4_REF_RAM_CLK_EN + Configures whether or not to open the clock gate for i4x4_mode ram.\\0: Open the clock gate only when application writes or reads i4x4_mode ram\\1: Force open the clock gate for i4x4_mode ram + 9 1 read-write - - - - SIGMADELTA_MISC - MISC Register - 0x24 - 0x20 - - FUNCTION_CLK_EN - Clock enable bit of sigma delta modulation. - 30 + IME_RAM_CLK_EN + Configures whether or not to open the clock gate for ime ram.\\0: Open the clock gate only when application writes or reads ime ram\\1: Force open the clock gate for ime ram + 10 1 read-write - SPI_SWAP - Reserved. - 31 + FME_RAM_CLK_EN + Configures whether or not to open the clock gate for fme ram.\\0: Open the clock gate only when application writes or readsfme ram\\1: Force open the clock gate for fme ram + 11 1 read-write - - - - 8 - 0x4 - GLITCH_FILTER_CH%s - Glitch Filter Configure Register of Channel%s - 0x30 - 0x20 - - FILTER_CH0_EN - Glitch Filter channel enable bit. - 0 + FETCH_RAM_CLK_EN + Configures whether or not to open the clock gate for fetch ram.\\0: Open the clock gate only when application writes or reads fetch ram\\1: Force open the clock gate for fetch ram + 12 1 read-write - FILTER_CH0_INPUT_IO_NUM - Glitch Filter input io number. - 1 - 6 + DB_RAM_CLK_EN + Configures whether or not to open the clock gate for db ram.\\0: Open the clock gate only when application writes or reads db ram\\1: Force open the clock gate for db ram + 13 + 1 read-write - FILTER_CH0_WINDOW_THRES - Glitch Filter window threshold. - 7 - 6 + CUR_MB_RAM_CLK_EN + Configures whether or not to open the clock gate for cur_mb ram.\\0: Open the clock gate only when application writes or reads cur_mb ram\\1: Force open the clock gate for cur_mb ram + 14 + 1 read-write - FILTER_CH0_WINDOW_WIDTH - Glitch Filter window width. - 13 - 6 + CAVLC_RAM_CLK_EN + Configures whether or not to open the clock gate for cavlc ram.\\0: Open the clock gate only when application writes or reads cavlc ram\\1: Force open the clock gate for cavlc ram + 15 + 1 read-write - - - - 8 - 0x4 - ETM_EVENT_CH%s_CFG - Etm Config register of Channel%s - 0x60 - 0x20 - - ETM_CH0_EVENT_SEL - Etm event channel select gpio. - 0 - 6 + IME_CLK_EN + Configures whether or not to open the clock gate for ime.\\0: Open the clock gate only when ime work\\1: Force open the clock gate for ime + 16 + 1 read-write - ETM_CH0_EVENT_EN - Etm event send enable bit. - 7 + FME_CLK_EN + Configures whether or not to open the clock gate for fme.\\0: Open the clock gate only when fme work\\1: Force open the clock gate for fme + 17 1 read-write - - - - ETM_TASK_P0_CFG - Etm Configure Register to decide which GPIO been chosen - 0xA0 - 0x20 - - ETM_TASK_GPIO0_EN - Enable bit of GPIO response etm task. - 0 + MC_CLK_EN + Configures whether or not to open the clock gate for mc.\\0: Open the clock gate only when mc work\\1: Force open the clock gate for mc + 18 1 read-write - ETM_TASK_GPIO0_SEL - GPIO choose a etm task channel. - 1 - 3 + INTERPOLATOR_CLK_EN + Configures whether or not to open the clock gate for interpolator.\\0: Open the clock gate only when interpolator work\\1: Force open the clock gate for interpolator + 19 + 1 read-write - ETM_TASK_GPIO1_EN - Enable bit of GPIO response etm task. - 8 + DB_CLK_EN + Configures whether or not to open the clock gate for deblocking filter.\\0: Open the clock gate only when deblocking filter work\\1: Force open the clock gate for deblocking filter + 20 1 read-write - ETM_TASK_GPIO1_SEL - GPIO choose a etm task channel. - 9 - 3 + CLAVLC_CLK_EN + Configures whether or not to open the clock gate for cavlc.\\0: Open the clock gate only when cavlc work\\1: Force open the clock gate for cavlc + 21 + 1 read-write - ETM_TASK_GPIO2_EN - Enable bit of GPIO response etm task. - 16 + INTRA_CLK_EN + Configures whether or not to open the clock gate for intra.\\0: Open the clock gate only when intra work\\1: Force open the clock gate for intra + 22 1 read-write - ETM_TASK_GPIO2_SEL - GPIO choose a etm task channel. - 17 - 3 + DECI_CLK_EN + Configures whether or not to open the clock gate for decimate.\\0: Open the clock gate only when decimate work\\1: Force open the clock gate for decimate + 23 + 1 read-write - ETM_TASK_GPIO3_EN - Enable bit of GPIO response etm task. + BS_CLK_EN + Configures whether or not to open the clock gate for bs buffer.\\0: Open the clock gate only when bs buffer work\\1: Force open the clock gate for bs buffer 24 1 read-write - ETM_TASK_GPIO3_SEL - GPIO choose a etm task channel. + MV_MERGE_CLK_EN + Configures whether or not to open the clock gate for mv merge.\\0: Open the clock gate only when mv merge work\\1: Force open the clock gate for mv merge 25 - 3 + 1 read-write - ETM_TASK_P1_CFG - Etm Configure Register to decide which GPIO been chosen - 0xA4 + MV_MERGE_CONFIG + Mv merge configuration register. + 0xD4 0x20 - ETM_TASK_GPIO4_EN - Enable bit of GPIO response etm task. + MV_MERGE_TYPE + Configure mv merge type.\\0: merge p16x16 mv\\1: merge min mv\\2: merge max mv\\3: not valid. 0 - 1 - read-write - - - ETM_TASK_GPIO4_SEL - GPIO choose a etm task channel. - 1 - 3 + 2 read-write - ETM_TASK_GPIO5_EN - Enable bit of GPIO response etm task. - 8 + INT_MV_OUT_EN + Configure mv merge output integer part not zero mv or all part not zero mv.\\0: output all part not zero mv\\1: output integer part not zero mv. + 2 1 read-write - ETM_TASK_GPIO5_SEL - GPIO choose a etm task channel. - 9 - 3 - read-write - - - ETM_TASK_GPIO6_EN - Enable bit of GPIO response etm task. - 16 + A_MV_MERGE_EN + Configure whether or not to enable video A mv merge.\\0: disable\\1: enable. + 3 1 read-write - ETM_TASK_GPIO6_SEL - GPIO choose a etm task channel. - 17 - 3 - read-write - - - ETM_TASK_GPIO7_EN - Enable bit of GPIO response etm task. - 24 + B_MV_MERGE_EN + Configure whether or not to enable video B mv merge.\\0: disable\\1: enable. + 4 1 read-write - ETM_TASK_GPIO7_SEL - GPIO choose a etm task channel. - 25 - 3 - read-write + MB_VALID_NUM + Represents the valid mb number of mv merge output. + 5 + 13 + read-only - ETM_TASK_P2_CFG - Etm Configure Register to decide which GPIO been chosen - 0xA8 + DEBUG_DMA_SEL + Debug H264 DMA select register + 0xD8 0x20 - ETM_TASK_GPIO8_EN - Enable bit of GPIO response etm task. + DBG_DMA_SEL + Every bit represents a dma in h264 0 - 1 - read-write - - - ETM_TASK_GPIO8_SEL - GPIO choose a etm task channel. - 1 - 3 + 8 read-write + + + + SYS_STATUS + System status register. + 0xDC + 0x20 + - ETM_TASK_GPIO9_EN - Enable bit of GPIO response etm task. - 8 - 1 - read-write + FRAME_NUM + Represents current frame number. + 0 + 9 + read-only - ETM_TASK_GPIO9_SEL - GPIO choose a etm task channel. + DUAL_STREAM_SEL + Represents which register group is used for cur frame.\\0: Register group A is used\\1: Register group B is used. 9 - 3 - read-write - - - ETM_TASK_GPIO10_EN - Enable bit of GPIO response etm task. - 16 1 - read-write - - - ETM_TASK_GPIO10_SEL - GPIO choose a etm task channel. - 17 - 3 - read-write + read-only - ETM_TASK_GPIO11_EN - Enable bit of GPIO response etm task. - 24 + INTRA_FLAG + Represents the type of current encoding frame.\\0: P frame\\1: I frame. + 10 1 - read-write + read-only + + + + FRAME_CODE_LENGTH + Frame code byte length register. + 0xE0 + 0x20 + - ETM_TASK_GPIO11_SEL - GPIO choose a etm task channel. - 25 - 3 - read-write + FRAME_CODE_LENGTH + Represents current frame code byte length. + 0 + 24 + read-only - ETM_TASK_P3_CFG - Etm Configure Register to decide which GPIO been chosen - 0xAC + DEBUG_INFO0 + Debug information register0. + 0xE4 0x20 - ETM_TASK_GPIO12_EN - Enable bit of GPIO response etm task. + TOP_CTRL_INTER_DEBUG_STATE + Represents top_ctrl_inter module FSM info. 0 - 1 - read-write + 4 + read-only - ETM_TASK_GPIO12_SEL - GPIO choose a etm task channel. - 1 + TOP_CTRL_INTRA_DEBUG_STATE + Represents top_ctrl_intra module FSM info. + 4 3 - read-write + read-only - ETM_TASK_GPIO13_EN - Enable bit of GPIO response etm task. - 8 - 1 - read-write + P_I_CMP_DEBUG_STATE + Represents p_i_cmp module FSM info. + 7 + 3 + read-only - ETM_TASK_GPIO13_SEL - GPIO choose a etm task channel. - 9 + MVD_DEBUG_STATE + Represents mvd module FSM info. + 10 3 - read-write + read-only - ETM_TASK_GPIO14_EN - Enable bit of GPIO response etm task. - 16 + MC_CHROMA_IP_DEBUG_STATE + Represents mc_chroma_ip module FSM info. + 13 1 - read-write + read-only - ETM_TASK_GPIO14_SEL - GPIO choose a etm task channel. - 17 - 3 - read-write + INTRA_16X16_CHROMA_CTRL_DEBUG_STATE + Represents intra_16x16_chroma_ctrl module FSM info. + 14 + 4 + read-only - ETM_TASK_GPIO15_EN - Enable bit of GPIO response etm task. - 24 - 1 - read-write + INTRA_4X4_CTRL_DEBUG_STATE + Represents intra_4x4_ctrl module FSM info. + 18 + 4 + read-only - ETM_TASK_GPIO15_SEL - GPIO choose a etm task channel. + INTRA_TOP_CTRL_DEBUG_STATE + Represents intra_top_ctrl module FSM info. + 22 + 3 + read-only + + + IME_CTRL_DEBUG_STATE + Represents ime_ctrl module FSM info. 25 3 - read-write + read-only - ETM_TASK_P4_CFG - Etm Configure Register to decide which GPIO been chosen - 0xB0 + DEBUG_INFO1 + Debug information register1. + 0xE8 0x20 - ETM_TASK_GPIO16_EN - Enable bit of GPIO response etm task. + FME_CTRL_DEBUG_STATE + Represents fme_ctrl module FSM info. 0 - 1 - read-write - - - ETM_TASK_GPIO16_SEL - GPIO choose a etm task channel. - 1 3 - read-write + read-only - ETM_TASK_GPIO17_EN - Enable bit of GPIO response etm task. - 8 - 1 - read-write + DECI_CALC_DEBUG_STATE + Represents deci_calc module's FSM info. DEV use only. + 3 + 2 + read-only - ETM_TASK_GPIO17_SEL - GPIO choose a etm task channel. - 9 + DB_DEBUG_STATE + Represents db module FSM info. + 5 3 - read-write + read-only - ETM_TASK_GPIO18_EN - Enable bit of GPIO response etm task. - 16 - 1 - read-write + CAVLC_ENC_DEBUG_STATE + Represents cavlc module enc FSM info. + 8 + 4 + read-only - ETM_TASK_GPIO18_SEL - GPIO choose a etm task channel. - 17 - 3 - read-write + CAVLC_SCAN_DEBUG_STATE + Represents cavlc module scan FSM info. + 12 + 4 + read-only - ETM_TASK_GPIO19_EN - Enable bit of GPIO response etm task. - 24 - 1 - read-write + CAVLC_CTRL_DEBUG_STATE + Represents cavlc module ctrl FSM info. + 16 + 2 + read-only - ETM_TASK_GPIO19_SEL - GPIO choose a etm task channel. - 25 - 3 - read-write + BS_BUFFER_DEBUG_STATE + Represents bs buffer overflow info. + 18 + 1 + read-only - ETM_TASK_P5_CFG - Etm Configure Register to decide which GPIO been chosen - 0xB4 + DEBUG_INFO2 + Debug information register2. + 0xEC 0x20 - ETM_TASK_GPIO20_EN - Enable bit of GPIO response etm task. + P_RC_DONE_DEBUG_FLAG + Represents p rate ctrl done status.\\0: not done\\1: done. 0 1 - read-write + read-only - ETM_TASK_GPIO20_SEL - GPIO choose a etm task channel. + P_P_I_CMP_DONE_DEBUG_FLAG + Represents p p_i_cmp done status.\\0: not done\\1: done. 1 - 3 - read-write - - - ETM_TASK_GPIO21_EN - Enable bit of GPIO response etm task. - 8 1 - read-write - - - ETM_TASK_GPIO21_SEL - GPIO choose a etm task channel. - 9 - 3 - read-write + read-only - ETM_TASK_GPIO22_EN - Enable bit of GPIO response etm task. - 16 + P_MV_MERGE_DONE_DEBUG_FLAG + Represents p mv merge done status.\\0: not done\\1: done. + 2 1 - read-write + read-only - ETM_TASK_GPIO22_SEL - GPIO choose a etm task channel. - 17 - 3 - read-write + P_MOVE_ORI_DONE_DEBUG_FLAG + Represents p move origin done status.\\0: not done\\1: done. + 3 + 1 + read-only - ETM_TASK_GPIO23_EN - Enable bit of GPIO response etm task. - 24 + P_MC_DONE_DEBUG_FLAG + Represents p mc done status.\\0: not done\\1: done. + 4 1 - read-write + read-only - ETM_TASK_GPIO23_SEL - GPIO choose a etm task channel. - 25 - 3 - read-write + P_IME_DONE_DEBUG_FLAG + Represents p ime done status.\\0: not done\\1: done. + 5 + 1 + read-only - - - - ETM_TASK_P6_CFG - Etm Configure Register to decide which GPIO been chosen - 0xB8 - 0x20 - - ETM_TASK_GPIO24_EN - Enable bit of GPIO response etm task. - 0 + P_GET_ORI_DONE_DEBUG_FLAG + Represents p get origin done status.\\0: not done\\1: done. + 6 1 - read-write + read-only - ETM_TASK_GPIO24_SEL - GPIO choose a etm task channel. - 1 - 3 - read-write + P_FME_DONE_DEBUG_FLAG + Represents p fme done status.\\0: not done\\1: done. + 7 + 1 + read-only - ETM_TASK_GPIO25_EN - Enable bit of GPIO response etm task. + P_FETCH_DONE_DEBUG_FLAG + Represents p fetch done status.\\0: not done\\1: done. 8 1 - read-write + read-only - ETM_TASK_GPIO25_SEL - GPIO choose a etm task channel. + P_DB_DONE_DEBUG_FLAG + Represents p deblocking done status.\\0: not done\\1: done. 9 - 3 - read-write - - - ETM_TASK_GPIO26_EN - Enable bit of GPIO response etm task. - 16 1 - read-write - - - ETM_TASK_GPIO26_SEL - GPIO choose a etm task channel. - 17 - 3 - read-write + read-only - ETM_TASK_GPIO27_EN - Enable bit of GPIO response etm task. - 24 + P_BS_BUF_DONE_DEBUG_FLAG + Represents p bitstream buffer done status.\\0: not done\\1: done. + 10 1 - read-write + read-only - ETM_TASK_GPIO27_SEL - GPIO choose a etm task channel. - 25 - 3 - read-write + REF_MOVE_2MB_LINE_DONE_DEBUG_FLAG + Represents dma move 2 ref mb line done status.\\0: not done\\1: done. + 11 + 1 + read-only - - - - ETM_TASK_P7_CFG - Etm Configure Register to decide which GPIO been chosen - 0xBC - 0x20 - - ETM_TASK_GPIO28_EN - Enable bit of GPIO response etm task. - 0 + I_P_I_CMP_DONE_DEBUG_FLAG + Represents I p_i_cmp done status.\\0: not done\\1: done. + 12 1 - read-write + read-only - ETM_TASK_GPIO28_SEL - GPIO choose a etm task channel. - 1 - 3 - read-write + I_MOVE_ORI_DONE_DEBUG_FLAG + Represents I move origin done status.\\0: not done\\1: done. + 13 + 1 + read-only - ETM_TASK_GPIO29_EN - Enable bit of GPIO response etm task. - 8 + I_GET_ORI_DONE_DEBUG_FLAG + Represents I get origin done status.\\0: not done\\1: done. + 14 1 - read-write + read-only - ETM_TASK_GPIO29_SEL - GPIO choose a etm task channel. - 9 - 3 - read-write + I_EC_DONE_DEBUG_FLAG + Represents I encoder done status.\\0: not done\\1: done. + 15 + 1 + read-only - ETM_TASK_GPIO30_EN - Enable bit of GPIO response etm task. + I_DB_DONE_DEBUG_FLAG + Represents I deblocking done status.\\0: not done\\1: done. 16 1 - read-write + read-only - ETM_TASK_GPIO30_SEL - GPIO choose a etm task channel. + I_BS_BUF_DONE_DEBUG_FLAG + Represents I bitstream buffer done status.\\0: not done\\1: done. 17 - 3 - read-write - - - ETM_TASK_GPIO31_EN - Enable bit of GPIO response etm task. - 24 1 - read-write - - - ETM_TASK_GPIO31_SEL - GPIO choose a etm task channel. - 25 - 3 - read-write + read-only - ETM_TASK_P8_CFG - Etm Configure Register to decide which GPIO been chosen - 0xC0 + DATE + Version control register + 0xF0 0x20 + 0x02304240 - ETM_TASK_GPIO32_EN - Enable bit of GPIO response etm task. + LEDC_DATE + Configures the version. + 0 + 28 + read-write + + + + + + + H264_DMA + H264 Encoder (DMA) + H264_DMA + 0x500A7000 + + 0x0 + 0x3DC + registers + + + H264_DMA2D_OUT_CH0 + 115 + + + H264_DMA2D_OUT_CH1 + 116 + + + H264_DMA2D_OUT_CH2 + 117 + + + H264_DMA2D_OUT_CH3 + 118 + + + H264_DMA2D_OUT_CH4 + 119 + + + H264_DMA2D_IN_CH0 + 120 + + + H264_DMA2D_IN_CH1 + 121 + + + H264_DMA2D_IN_CH2 + 122 + + + H264_DMA2D_IN_CH3 + 123 + + + H264_DMA2D_IN_CH4 + 124 + + + H264_DMA2D_IN_CH5 + 125 + + + + OUT_CONF0_CH0 + TX CH0 config0 register + 0x0 + 0x20 + 0x00000002 + + + OUT_AUTO_WRBACK_CH0 + Set this bit to enable automatic outlink-writeback when all the data pointed by outlink descriptor has been received. 0 1 read-write - ETM_TASK_GPIO32_SEL - GPIO choose a etm task channel. + OUT_EOF_MODE_CH0 + EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is generated when data need to read has been popped from FIFO in DMA 1 - 3 + 1 read-write - ETM_TASK_GPIO33_EN - Enable bit of GPIO response etm task. - 8 + OUTDSCR_BURST_EN_CH0 + Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM. + 2 1 read-write - ETM_TASK_GPIO33_SEL - GPIO choose a etm task channel. - 9 - 3 + OUT_ECC_AES_EN_CH0 + When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned. + 3 + 1 read-write - ETM_TASK_GPIO34_EN - Enable bit of GPIO response etm task. - 16 + OUT_CHECK_OWNER_CH0 + Set this bit to enable checking the owner attribute of the link descriptor. + 4 1 read-write - ETM_TASK_GPIO34_SEL - GPIO choose a etm task channel. - 17 + OUT_MEM_BURST_LENGTH_CH0 + Block size of Tx channel 0. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes + 6 3 read-write - ETM_TASK_GPIO35_EN - Enable bit of GPIO response etm task. + OUT_PAGE_BOUND_EN_CH0 + Set this bit to 1 to make sure AXI read data don't cross the address boundary which define by mem_burst_length + 12 + 1 + read-write + + + OUT_REORDER_EN_CH0 + Enable TX channel 0 macro block reorder when set to 1, only channel0 have this selection + 16 + 1 + read-write + + + OUT_RST_CH0 + Write 1 then write 0 to this bit to reset TX channel 24 1 read-write - ETM_TASK_GPIO35_SEL - GPIO choose a etm task channel. + OUT_CMD_DISABLE_CH0 + Write 1 before reset and write 0 after reset 25 - 3 + 1 + read-write + + + OUT_ARB_WEIGHT_OPT_DIS_CH0 + Set this bit to 1 to disable arbiter optimum weight function. + 26 + 1 read-write - ETM_TASK_P9_CFG - Etm Configure Register to decide which GPIO been chosen - 0xC4 + OUT_INT_RAW_CH0 + TX CH0 interrupt raw register + 0x4 0x20 - ETM_TASK_GPIO36_EN - Enable bit of GPIO response etm task. + OUT_DONE_CH0_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0. 0 1 read-write - ETM_TASK_GPIO36_SEL - GPIO choose a etm task channel. + OUT_EOF_CH0_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. 1 - 3 + 1 read-write - ETM_TASK_GPIO37_EN - Enable bit of GPIO response etm task. - 8 + OUT_DSCR_ERR_CH0_INT_RAW + The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0. + 2 1 read-write - ETM_TASK_GPIO37_SEL - GPIO choose a etm task channel. - 9 - 3 + OUT_TOTAL_EOF_CH0_INT_RAW + The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0. + 3 + 1 read-write - ETM_TASK_GPIO38_EN - Enable bit of GPIO response etm task. - 16 + OUTFIFO_OVF_L1_CH0_INT_RAW + The raw interrupt bit turns to high level when fifo is overflow. + 4 1 read-write - ETM_TASK_GPIO38_SEL - GPIO choose a etm task channel. - 17 - 3 + OUTFIFO_UDF_L1_CH0_INT_RAW + The raw interrupt bit turns to high level when fifo is underflow. + 5 + 1 read-write - ETM_TASK_GPIO39_EN - Enable bit of GPIO response etm task. - 24 + OUTFIFO_OVF_L2_CH0_INT_RAW + The raw interrupt bit turns to high level when fifo is overflow. + 6 1 read-write - ETM_TASK_GPIO39_SEL - GPIO choose a etm task channel. - 25 - 3 + OUTFIFO_UDF_L2_CH0_INT_RAW + The raw interrupt bit turns to high level when fifo is underflow. + 7 + 1 + read-write + + + OUT_DSCR_TASK_OVF_CH0_INT_RAW + The raw interrupt bit turns to high level when dscr ready task fifo is overflow. + 8 + 1 read-write - ETM_TASK_P10_CFG - Etm Configure Register to decide which GPIO been chosen - 0xC8 + OUT_INT_ENA_CH0 + TX CH0 interrupt ena register + 0x8 0x20 - ETM_TASK_GPIO40_EN - Enable bit of GPIO response etm task. + OUT_DONE_CH0_INT_ENA + The interrupt enable bit for the OUT_DONE_CH_INT interrupt. 0 1 read-write - ETM_TASK_GPIO40_SEL - GPIO choose a etm task channel. + OUT_EOF_CH0_INT_ENA + The interrupt enable bit for the OUT_EOF_CH_INT interrupt. 1 - 3 + 1 read-write - ETM_TASK_GPIO41_EN - Enable bit of GPIO response etm task. - 8 + OUT_DSCR_ERR_CH0_INT_ENA + The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + 2 1 read-write - ETM_TASK_GPIO41_SEL - GPIO choose a etm task channel. - 9 - 3 + OUT_TOTAL_EOF_CH0_INT_ENA + The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 read-write - ETM_TASK_GPIO42_EN - Enable bit of GPIO response etm task. - 16 + OUTFIFO_OVF_L1_CH0_INT_ENA + The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 1 read-write - ETM_TASK_GPIO42_SEL - GPIO choose a etm task channel. - 17 - 3 + OUTFIFO_UDF_L1_CH0_INT_ENA + The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 read-write - ETM_TASK_GPIO43_EN - Enable bit of GPIO response etm task. - 24 + OUTFIFO_OVF_L2_CH0_INT_ENA + The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. + 6 1 read-write - ETM_TASK_GPIO43_SEL - GPIO choose a etm task channel. - 25 - 3 + OUTFIFO_UDF_L2_CH0_INT_ENA + The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + read-write + + + OUT_DSCR_TASK_OVF_CH0_INT_ENA + The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. + 8 + 1 read-write - ETM_TASK_P11_CFG - Etm Configure Register to decide which GPIO been chosen - 0xCC + OUT_INT_ST_CH0 + TX CH0 interrupt st register + 0xC 0x20 - ETM_TASK_GPIO44_EN - Enable bit of GPIO response etm task. + OUT_DONE_CH0_INT_ST + The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. 0 1 - read-write + read-only - ETM_TASK_GPIO44_SEL - GPIO choose a etm task channel. + OUT_EOF_CH0_INT_ST + The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. 1 - 3 - read-write + 1 + read-only - ETM_TASK_GPIO45_EN - Enable bit of GPIO response etm task. - 8 + OUT_DSCR_ERR_CH0_INT_ST + The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + 2 1 - read-write + read-only - ETM_TASK_GPIO45_SEL - GPIO choose a etm task channel. - 9 - 3 - read-write + OUT_TOTAL_EOF_CH0_INT_ST + The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + read-only - ETM_TASK_GPIO46_EN - Enable bit of GPIO response etm task. - 16 + OUTFIFO_OVF_L1_CH0_INT_ST + The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 1 - read-write + read-only - ETM_TASK_GPIO46_SEL - GPIO choose a etm task channel. - 17 - 3 - read-write + OUTFIFO_UDF_L1_CH0_INT_ST + The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-only - ETM_TASK_GPIO47_EN - Enable bit of GPIO response etm task. - 24 + OUTFIFO_OVF_L2_CH0_INT_ST + The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. + 6 1 - read-write + read-only - ETM_TASK_GPIO47_SEL - GPIO choose a etm task channel. - 25 - 3 - read-write + OUTFIFO_UDF_L2_CH0_INT_ST + The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + read-only + + + OUT_DSCR_TASK_OVF_CH0_INT_ST + The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. + 8 + 1 + read-only - ETM_TASK_P12_CFG - Etm Configure Register to decide which GPIO been chosen - 0xD0 + OUT_INT_CLR_CH0 + TX CH0 interrupt clr register + 0x10 0x20 - ETM_TASK_GPIO48_EN - Enable bit of GPIO response etm task. + OUT_DONE_CH0_INT_CLR + Set this bit to clear the OUT_DONE_CH_INT interrupt. 0 1 - read-write + write-only - ETM_TASK_GPIO48_SEL - GPIO choose a etm task channel. + OUT_EOF_CH0_INT_CLR + Set this bit to clear the OUT_EOF_CH_INT interrupt. 1 - 3 - read-write + 1 + write-only - ETM_TASK_GPIO49_EN - Enable bit of GPIO response etm task. - 8 + OUT_DSCR_ERR_CH0_INT_CLR + Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + 2 1 - read-write + write-only - ETM_TASK_GPIO49_SEL - GPIO choose a etm task channel. - 9 - 3 - read-write + OUT_TOTAL_EOF_CH0_INT_CLR + Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + write-only - ETM_TASK_GPIO50_EN - Enable bit of GPIO response etm task. - 16 + OUTFIFO_OVF_L1_CH0_INT_CLR + Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 1 - read-write + write-only - ETM_TASK_GPIO50_SEL - GPIO choose a etm task channel. - 17 - 3 - read-write + OUTFIFO_UDF_L1_CH0_INT_CLR + Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + write-only - ETM_TASK_GPIO51_EN - Enable bit of GPIO response etm task. - 24 + OUTFIFO_OVF_L2_CH0_INT_CLR + Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. + 6 1 - read-write + write-only - ETM_TASK_GPIO51_SEL - GPIO choose a etm task channel. - 25 - 3 - read-write + OUTFIFO_UDF_L2_CH0_INT_CLR + Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + write-only + + + OUT_DSCR_TASK_OVF_CH0_INT_CLR + Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt. + 8 + 1 + write-only - ETM_TASK_P13_CFG - Etm Configure Register to decide which GPIO been chosen - 0xD4 + OUTFIFO_STATUS_CH0 + TX CH0 outfifo status register + 0x14 0x20 + 0x00020082 - ETM_TASK_GPIO52_EN - Enable bit of GPIO response etm task. + OUTFIFO_FULL_L2_CH0 + Tx FIFO full signal for Tx channel 0. 0 1 - read-write + read-only - ETM_TASK_GPIO52_SEL - GPIO choose a etm task channel. + OUTFIFO_EMPTY_L2_CH0 + Tx FIFO empty signal for Tx channel 0. 1 - 3 - read-write + 1 + read-only - ETM_TASK_GPIO53_EN - Enable bit of GPIO response etm task. - 8 + OUTFIFO_CNT_L2_CH0 + The register stores the byte number of the data in Tx FIFO for Tx channel 0. + 2 + 4 + read-only + + + OUTFIFO_FULL_L1_CH0 + Tx FIFO full signal for Tx channel 0. + 6 1 - read-write + read-only - ETM_TASK_GPIO53_SEL - GPIO choose a etm task channel. - 9 - 3 - read-write + OUTFIFO_EMPTY_L1_CH0 + Tx FIFO empty signal for Tx channel 0. + 7 + 1 + read-only - ETM_TASK_GPIO54_EN - Enable bit of GPIO response etm task. + OUTFIFO_CNT_L1_CH0 + The register stores the byte number of the data in Tx FIFO for Tx channel 0. + 8 + 5 + read-only + + + OUTFIFO_FULL_L3_CH0 + Tx FIFO full signal for Tx channel 0. 16 1 - read-write + read-only - ETM_TASK_GPIO54_SEL - GPIO choose a etm task channel. + OUTFIFO_EMPTY_L3_CH0 + Tx FIFO empty signal for Tx channel 0. 17 - 3 - read-write + 1 + read-only + + + OUTFIFO_CNT_L3_CH0 + The register stores the 8byte number of the data in Tx FIFO for Tx channel 0. + 18 + 2 + read-only - VERSION - Version Control Register - 0xFC + OUT_PUSH_CH0 + TX CH0 outfifo push register + 0x18 0x20 - 0x02203050 - GPIO_SD_DATE - Version control register. + OUTFIFO_WDATA_CH0 + This register stores the data that need to be pushed into DMA Tx FIFO. 0 - 28 + 10 + read-write + + + OUTFIFO_PUSH_CH0 + Set this bit to push data into DMA Tx FIFO. + 10 + 1 read-write - - - - H264 - H264 Encoder (Core) - H264 - 0x50084000 - - 0x0 - 0xF4 - registers - - - H264_REG - 126 - - - SYS_CTRL - H264 system level control register. - 0x0 + OUT_LINK_CONF_CH0 + TX CH0 out_link dscr ctrl register + 0x1C 0x20 + 0x00800000 - FRAME_START - Configures whether or not to start encoding one frame.\\0: Invalid. No effect\\1: Start encoding one frame - 0 + OUTLINK_STOP_CH0 + Set this bit to stop dealing with the outlink descriptors. + 20 1 - write-only + read-write - DMA_MOVE_START - Configures whether or not to start moving reference data from external mem.\\0: Invalid. No effect\\1: H264 start moving two MB lines of reference frame from external mem to internal mem - 1 + OUTLINK_START_CH0 + Set this bit to start dealing with the outlink descriptors. + 21 1 - write-only + read-write - FRAME_MODE - Configures H264 running mode. When field H264_DUAL_STREAM_MODE is set to 1, this field must be set to 1 too.\\0: GOP mode. Before every GOP first frame start, need reconfig reference frame DMA\\1: Frame mode. Before every frame start, need reconfig reference frame DMA - 2 + OUTLINK_RESTART_CH0 + Set this bit to restart a new outlink from the last address. + 22 1 read-write - SYS_RST_PULSE - Configures whether or not to reset H264 ip.\\0: Invalid. No effect\\1: Reset H264 ip - 3 + OUTLINK_PARK_CH0 + 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working. + 23 1 - write-only + read-only - GOP_CONF - GOP related configuration register. - 0x4 + OUT_LINK_ADDR_CH0 + TX CH0 out_link dscr addr register + 0x20 0x20 - DUAL_STREAM_MODE - Configures whether or not to enable dual stream mode. When this field is set to 1, H264_FRAME_MODE field must be set to 1 too.\\0: Normal mode\\1: Dual stream mode + OUTLINK_ADDR_CH0 + This register stores the first outlink descriptor's address. 0 - 1 + 32 read-write + + + + OUT_STATE_CH0 + TX CH0 state register + 0x24 + 0x20 + 0x01000000 + - GOP_NUM - Configures the frame number of one GOP.\\0: The frame number of one GOP is infinite\\Others: Actual frame number of one GOP - 1 - 8 - read-write + OUTLINK_DSCR_ADDR_CH0 + This register stores the current outlink descriptor's address. + 0 + 18 + read-only + + + OUT_DSCR_STATE_CH0 + This register stores the current descriptor state machine state. + 18 + 2 + read-only + + + OUT_STATE_CH0 + This register stores the current control module state machine state. + 20 + 4 + read-only + + + OUT_RESET_AVAIL_CH0 + This register indicate that if the channel reset is safety. + 24 + 1 + read-only - A_SYS_MB_RES - Video A horizontal and vertical MB resolution register. - 0x8 + OUT_EOF_DES_ADDR_CH0 + TX CH0 eof des addr register + 0x28 0x20 - A_SYS_TOTAL_MB_Y - Configures video A vertical MB resolution. + OUT_EOF_DES_ADDR_CH0 + This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1. 0 - 7 - read-write + 32 + read-only + + + + OUT_DSCR_CH0 + TX CH0 next dscr addr register + 0x2C + 0x20 + - A_SYS_TOTAL_MB_X - Configures video A horizontal MB resolution. - 7 - 7 - read-write + OUTLINK_DSCR_CH0 + The address of the next outlink descriptor address y. + 0 + 32 + read-only - A_SYS_CONF - Video A system level configuration register. - 0xC + OUT_DSCR_BF0_CH0 + TX CH0 last dscr addr register + 0x30 0x20 - 0x00000203 - A_DB_TMP_READY_TRIGGER_MB_NUM - Configures when to trigger video A H264_DB_TMP_READY_INT. When the (MB number of written db temp+1) is greater than this filed in first MB line, trigger H264_DB_TMP_READY_INT. Min is 3. + OUTLINK_DSCR_BF0_CH0 + The address of the last outlink descriptor's next address y-1. 0 - 7 - read-write + 32 + read-only + + + + OUT_DSCR_BF1_CH0 + TX CH0 second-to-last dscr addr register + 0x34 + 0x20 + - A_REC_READY_TRIGGER_MB_LINES - Configures when to trigger video A H264_REC_READY_INT. When the MB line number of generated reconstruct pixel is greater than this filed, trigger H264_REC_READY_INT. Min is 4. - 7 - 7 + OUTLINK_DSCR_BF1_CH0 + The address of the second-to-last outlink descriptor's next address y-2. + 0 + 32 + read-only + + + + + OUT_ARB_CH0 + TX CH0 arb register + 0x3C + 0x20 + 0x00000011 + + + OUT_ARB_TOKEN_NUM_CH0 + Set the max number of token count of arbiter + 0 + 4 read-write - A_INTRA_COST_CMP_OFFSET - Configures video A intra cost offset when I MB compared with P MB. - 14 - 16 + EXTER_OUT_ARB_PRIORITY_CH0 + Set the priority of channel + 4 + 2 read-write - A_DECI_SCORE - Video A luma and chroma MB decimate score Register. - 0x10 + OUT_RO_STATUS_CH0 + TX CH0 reorder status register + 0x40 0x20 + 0x00000800 - A_C_DECI_SCORE - Configures video A chroma MB decimate score. When chroma score is smaller than it, chroma decimate will be enable. + OUTFIFO_RO_CNT_CH0 + The register stores the 8byte number of the data in reorder Tx FIFO for channel 0. 0 - 10 - read-write + 2 + read-only - A_L_DECI_SCORE - Configures video A luma MB decimate score. When luma score is smaller than it, luma decimate will be enable. + OUT_RO_WR_STATE_CH0 + The register stores the state of read ram of reorder + 6 + 2 + read-only + + + OUT_RO_RD_STATE_CH0 + The register stores the state of write ram of reorder + 8 + 2 + read-only + + + OUT_PIXEL_BYTE_CH0 + the number of bytes contained in a pixel at TX channel 0: 1byte 1: 1.5bytes 2 : 2bytes 3: 2.5bytes 4: 3bytes 5: 4bytes 10 - 10 - read-write + 4 + read-only + + + OUT_BURST_BLOCK_NUM_CH0 + the number of macro blocks contained in a burst of data at TX channel + 14 + 4 + read-only - A_DECI_SCORE_OFFSET - Video A luma and chroma MB decimate score offset Register. - 0x14 + OUT_RO_PD_CONF_CH0 + TX CH0 reorder power config register + 0x44 0x20 + 0x00000020 - A_I16X16_DECI_SCORE_OFFSET - Configures video A i16x16 MB decimate score offset. This offset will be added to i16x16 MB score. - 0 - 6 + OUT_RO_RAM_FORCE_PD_CH0 + dma reorder ram power down + 4 + 1 read-write - A_I_CHROMA_DECI_SCORE_OFFSET - Configures video A I chroma MB decimate score offset. This offset will be added to I chroma MB score. - 6 - 6 + OUT_RO_RAM_FORCE_PU_CH0 + dma reorder ram power up + 5 + 1 read-write - A_P16X16_DECI_SCORE_OFFSET - Configures video A p16x16 MB decimate score offset. This offset will be added to p16x16 MB score. - 12 - 6 + OUT_RO_RAM_CLK_FO_CH0 + 1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA. 0: A gate-clock will be used when accessing the RAM in DMA. + 6 + 1 read-write + + + + OUT_MODE_ENABLE_CH0 + tx CH0 mode enable register + 0x50 + 0x20 + - A_P_CHROMA_DECI_SCORE_OFFSET - Configures video A p chroma MB decimate score offset. This offset will be added to p chroma MB score. - 18 - 6 + OUT_TEST_MODE_ENABLE_CH0 + tx CH0 test mode enable.0 : H264_DMA work in normal mode.1 : H264_DMA work in test mode + 0 + 1 read-write - A_RC_CONF0 - Video A rate control configuration register0. - 0x18 + OUT_MODE_YUV_CH0 + tx CH0 test mode yuv value register + 0x54 0x20 - A_QP - Configures video A frame level initial luma QP value. + OUT_TEST_Y_VALUE_CH0 + tx CH0 test mode y value 0 - 6 + 8 read-write - A_RATE_CTRL_U - Configures video A parameter U value. U = int((float) u << 8). - 6 - 16 + OUT_TEST_U_VALUE_CH0 + tx CH0 test mode u value + 8 + 8 read-write - A_MB_RATE_CTRL_EN - Configures video A whether or not to open macro block rate ctrl.\\1:Open the macro block rate ctrl\\1:Close the macro block rate ctrl. - 22 - 1 + OUT_TEST_V_VALUE_CH0 + tx CH0 test mode v value + 16 + 8 read-write - A_RC_CONF1 - Video A rate control configuration register1. - 0x1C + OUT_ETM_CONF_CH0 + TX CH0 ETM config register + 0x68 0x20 + 0x00000004 - A_CHROMA_DC_QP_DELTA - Configures video A chroma DC QP offset based on Chroma QP. Chroma DC QP = Chroma QP(after map) + reg_chroma_dc_qp_delta. + OUT_ETM_EN_CH0 + Set this bit to 1 to enable ETM task function 0 - 3 + 1 read-write - A_CHROMA_QP_DELTA - Configures video A chroma QP offset based on luma QP. Chroma QP(before map) = Luma QP + reg_chroma_qp_delta. - 3 - 4 + OUT_ETM_LOOP_EN_CH0 + when this bit is 1, dscr can be processed after receiving a task + 1 + 1 read-write - A_QP_MIN - Configures video A allowed luma QP min value. - 7 - 6 + OUT_DSCR_TASK_MAK_CH0 + ETM dscr_ready maximum cache numbers + 2 + 2 read-write + + + + OUT_BUF_LEN_CH0 + tx CH0 buf len register + 0x70 + 0x20 + - A_QP_MAX - Configures video A allowed luma QP max value. - 13 - 6 - read-write + OUT_CMDFIFO_BUF_LEN_HB_CH0 + only for debug + 0 + 13 + read-only + + + + OUT_FIFO_BCNT_CH0 + tx CH0 fifo byte cnt register + 0x74 + 0x20 + - A_MAD_FRAME_PRED - Configures vdieo A frame level predicted MB MAD value. - 19 - 12 - read-write + OUT_CMDFIFO_OUTFIFO_BCNT_CH0 + only for debug + 0 + 10 + read-only - A_DB_BYPASS - Video A Deblocking bypass register - 0x20 + OUT_PUSH_BYTECNT_CH0 + tx CH0 push byte cnt register + 0x78 0x20 + 0x000000FF - A_BYPASS_DB_FILTER - Configures whether or not to bypass video A deblcoking filter. \\0: Open the deblock filter\\1: Close the deblock filter + OUT_CMDFIFO_PUSH_BYTECNT_CH0 + only for debug 0 - 1 - read-write + 8 + read-only - A_ROI_REGION0 - Video A H264 ROI region0 range configure register. - 0x24 + OUT_XADDR_CH0 + tx CH0 xaddr register + 0x7C 0x20 - X - Configures the horizontal start macroblocks of region 0 in Video A. + OUT_CMDFIFO_XADDR_CH0 + only for debug 0 - 7 + 32 + read-only + + + + + OUT_CONF0_CH1 + TX CH1 config0 register + 0x100 + 0x20 + 0x00000002 + + + OUT_AUTO_WRBACK_CH1 + Set this bit to enable automatic outlink-writeback when all the data pointed by outlink descriptor has been received. + 0 + 1 read-write - Y - Configures the vertical start macroblocks of region 0 in Video A. - 7 - 7 + OUT_EOF_MODE_CH1 + EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is generated when data need to read has been popped from FIFO in DMA + 1 + 1 read-write - X_LEN - Configures the number of macroblocks in horizontal direction of the region 0 in Video A. - 14 - 7 + OUTDSCR_BURST_EN_CH1 + Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM. + 2 + 1 read-write - Y_LEN - Configures the number of macroblocks in vertical direction of the region 0 in Video A. - 21 - 7 + OUT_ECC_AES_EN_CH1 + When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned. + 3 + 1 read-write - EN - Configures whether or not to open Video A ROI of region 0 .\\0:Close ROI\\1:Open ROI. - 28 + OUT_CHECK_OWNER_CH1 + Set this bit to enable checking the owner attribute of the link descriptor. + 4 1 read-write - - - - A_ROI_REGION1 - Video A H264 ROI region1 range configure register. - 0x28 - 0x20 - - X - Configures the horizontal start macroblocks of region 1 in Video A. - 0 - 7 + OUT_MEM_BURST_LENGTH_CH1 + Block size of Tx channel 1. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 64 bytes + 6 + 3 read-write - Y - Configures the vertical start macroblocks of region 1 in Video A. - 7 - 7 + OUT_PAGE_BOUND_EN_CH1 + Set this bit to 1 to make sure AXI read data don't cross the address boundary which define by mem_burst_length + 12 + 1 read-write - X_LEN - Configures the number of macroblocks in horizontal direction of the region 1 in Video A. - 14 - 7 + OUT_RST_CH1 + Write 1 then write 0 to this bit to reset TX channel + 24 + 1 read-write - Y_LEN - Configures the number of macroblocks in vertical direction of the region 1 in Video A. - 21 - 7 + OUT_CMD_DISABLE_CH1 + Write 1 before reset and write 0 after reset + 25 + 1 read-write - EN - Configures whether or not to open Video A ROI of region 1 .\\0:Close ROI\\1:Open ROI. - 28 + OUT_ARB_WEIGHT_OPT_DIS_CH1 + Set this bit to 1 to disable arbiter optimum weight function. + 26 1 read-write - A_ROI_REGION2 - Video A H264 ROI region2 range configure register. - 0x2C + OUT_INT_RAW_CH1 + TX CH1 interrupt raw register + 0x104 0x20 - X - Configures the horizontal start macroblocks of region 2 in Video A. + OUT_DONE_CH1_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0. 0 - 7 - read-write - - - Y - Configures the vertical start macroblocks of region 2 in Video A. - 7 - 7 + 1 read-write - X_LEN - Configures the number of macroblocks in horizontal direction of the region 2 in Video A. - 14 - 7 + OUT_EOF_CH1_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. + 1 + 1 read-write - Y_LEN - Configures the number of macroblocks in vertical direction of the region 2 in Video A. - 21 - 7 + OUT_DSCR_ERR_CH1_INT_RAW + The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0. + 2 + 1 read-write - EN - Configures whether or not to open Video A ROI of region 2 .\\0:Close ROI\\1:Open ROI. - 28 + OUT_TOTAL_EOF_CH1_INT_RAW + The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0. + 3 1 read-write - - - - A_ROI_REGION3 - Video A H264 ROI region3 range configure register. - 0x30 - 0x20 - - X - Configures the horizontal start macroblocks of region 3 in Video A. - 0 - 7 + OUTFIFO_OVF_L1_CH1_INT_RAW + The raw interrupt bit turns to high level when fifo is overflow. + 4 + 1 read-write - Y - Configures the vertical start macroblocks of region 3 in Video A. - 7 - 7 + OUTFIFO_UDF_L1_CH1_INT_RAW + The raw interrupt bit turns to high level when fifo is underflow. + 5 + 1 read-write - X_LEN - Configures the number of macroblocks in horizontal direction of the region 3 in video A. - 14 - 7 + OUTFIFO_OVF_L2_CH1_INT_RAW + The raw interrupt bit turns to high level when fifo is overflow. + 6 + 1 read-write - Y_LEN - Configures the number of macroblocks in vertical direction of the region 3 in video A. - 21 - 7 + OUTFIFO_UDF_L2_CH1_INT_RAW + The raw interrupt bit turns to high level when fifo is underflow. + 7 + 1 read-write - EN - Configures whether or not to open Video A ROI of region 3 .\\0:Close ROI\\1:Open ROI. - 28 + OUT_DSCR_TASK_OVF_CH1_INT_RAW + The raw interrupt bit turns to high level when dscr ready task fifo is overflow. + 8 1 read-write - A_ROI_REGION4 - Video A H264 ROI region4 range configure register. - 0x34 + OUT_INT_ENA_CH1 + TX CH1 interrupt ena register + 0x108 0x20 - X - Configures the horizontal start macroblocks of region 4 in Video A. + OUT_DONE_CH1_INT_ENA + The interrupt enable bit for the OUT_DONE_CH_INT interrupt. 0 - 7 - read-write - - - Y - Configures the vertical start macroblocks of region 4 in Video A. - 7 - 7 + 1 read-write - X_LEN - Configures the number of macroblocks in horizontal direction of the region 4 in video A. - 14 - 7 + OUT_EOF_CH1_INT_ENA + The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + 1 + 1 read-write - Y_LEN - Configures the number of macroblocks in vertical direction of the region 4 in video A. - 21 - 7 + OUT_DSCR_ERR_CH1_INT_ENA + The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 read-write - EN - Configures whether or not to open Video A ROI of region 4 .\\0:Close ROI\\1:Open ROI. - 28 + OUT_TOTAL_EOF_CH1_INT_ENA + The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + 3 1 read-write - - - - A_ROI_REGION5 - Video A H264 ROI region5 range configure register. - 0x38 - 0x20 - - X - Configures the horizontial start macroblocks of region 5 video A. - 0 - 7 + OUTFIFO_OVF_L1_CH1_INT_ENA + The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 read-write - Y - Configures the vertical start macroblocks of region 5 video A. - 7 - 7 + OUTFIFO_UDF_L1_CH1_INT_ENA + The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 read-write - X_LEN - Configures the number of macroblocks in horizontal direction of the region 5 video A. - 14 - 7 + OUTFIFO_OVF_L2_CH1_INT_ENA + The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 read-write - Y_LEN - Configures the number of macroblocks in vertical direction of the region 5 in video A. - 21 - 7 + OUTFIFO_UDF_L2_CH1_INT_ENA + The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 read-write - EN - Configures whether or not to open Video A ROI of region 5 .\\0:Close ROI\\1:Open ROI. - 28 + OUT_DSCR_TASK_OVF_CH1_INT_ENA + The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. + 8 1 read-write - A_ROI_REGION6 - Video A H264 ROI region6 range configure register. - 0x3C + OUT_INT_ST_CH1 + TX CH1 interrupt st register + 0x10C 0x20 - X - Configures the horizontial start macroblocks of region 6 video A. + OUT_DONE_CH1_INT_ST + The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. 0 - 7 - read-write + 1 + read-only - Y - Configures the vertical start macroblocks of region 6 in video A. - 7 - 7 - read-write + OUT_EOF_CH1_INT_ST + The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + 1 + 1 + read-only - X_LEN - Configures the number of macroblocks in horizontal direction of the region 6 in video A. - 14 - 7 - read-write + OUT_DSCR_ERR_CH1_INT_ST + The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + read-only - Y_LEN - Configures the number of macroblocks in vertical direction of the region 6 in video A. - 21 - 7 - read-write + OUT_TOTAL_EOF_CH1_INT_ST + The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + read-only - EN - Configures whether or not to open Video A ROI of region 6 .\\0:Close ROI\\1:Open ROI. - 28 + OUTFIFO_OVF_L1_CH1_INT_ST + The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 1 - read-write + read-only + + + OUTFIFO_UDF_L1_CH1_INT_ST + The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-only + + + OUTFIFO_OVF_L2_CH1_INT_ST + The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + read-only + + + OUTFIFO_UDF_L2_CH1_INT_ST + The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + read-only + + + OUT_DSCR_TASK_OVF_CH1_INT_ST + The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. + 8 + 1 + read-only - A_ROI_REGION7 - Video A H264 ROI region7 range configure register. - 0x40 + OUT_INT_CLR_CH1 + TX CH1 interrupt clr register + 0x110 0x20 - X - Configures the horizontal start macroblocks of region 7 in video A. + OUT_DONE_CH1_INT_CLR + Set this bit to clear the OUT_DONE_CH_INT interrupt. 0 - 7 - read-write + 1 + write-only - Y - Configures the vertical start macroblocks of region 7 in video A. - 7 - 7 - read-write + OUT_EOF_CH1_INT_CLR + Set this bit to clear the OUT_EOF_CH_INT interrupt. + 1 + 1 + write-only - X_LEN - Configures the number of macroblocks in horizontal direction of the region 7 in video A. - 14 - 7 - read-write + OUT_DSCR_ERR_CH1_INT_CLR + Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + write-only - Y_LEN - Configures the number of macroblocks in vertical direction of the region 7 in video A. - 21 - 7 - read-write + OUT_TOTAL_EOF_CH1_INT_CLR + Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + write-only - EN - Configures whether or not to open Video A ROI of region 7 .\\0:Close ROI\\1:Open ROI. - 28 + OUTFIFO_OVF_L1_CH1_INT_CLR + Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 1 - read-write + write-only + + + OUTFIFO_UDF_L1_CH1_INT_CLR + Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + write-only + + + OUTFIFO_OVF_L2_CH1_INT_CLR + Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + write-only + + + OUTFIFO_UDF_L2_CH1_INT_CLR + Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + write-only + + + OUT_DSCR_TASK_OVF_CH1_INT_CLR + Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt. + 8 + 1 + write-only - A_ROI_REGION0_3_QP - Video A H264 ROI region0, region1,region2,region3 QP register. - 0x44 + OUTFIFO_STATUS_CH1 + TX CH1 outfifo status register + 0x114 0x20 + 0x00020082 - A_ROI_REGION0_QP - Configure H264 ROI region0 qp in video A,fixed qp or delta qp. + OUTFIFO_FULL_L2_CH1 + Tx FIFO full signal for Tx channel 1. 0 - 7 - read-write + 1 + read-only - A_ROI_REGION1_QP - Configure H264 ROI region1 qp in video A,fixed qp or delta qp. + OUTFIFO_EMPTY_L2_CH1 + Tx FIFO empty signal for Tx channel 1. + 1 + 1 + read-only + + + OUTFIFO_CNT_L2_CH1 + The register stores the byte number of the data in Tx FIFO for Tx channel 1. + 2 + 4 + read-only + + + OUTFIFO_FULL_L1_CH1 + Tx FIFO full signal for Tx channel 1. + 6 + 1 + read-only + + + OUTFIFO_EMPTY_L1_CH1 + Tx FIFO empty signal for Tx channel 1. 7 - 7 - read-write + 1 + read-only - A_ROI_REGION2_QP - Configure H264 ROI region2 qp in video A,fixed qp or delta qp. - 14 - 7 - read-write + OUTFIFO_CNT_L1_CH1 + The register stores the byte number of the data in Tx FIFO for Tx channel 1. + 8 + 5 + read-only - A_ROI_REGION3_QP - Configure H264 ROI region3 qp in video A,fixed qp or delta qp. - 21 - 7 - read-write + OUTFIFO_FULL_L3_CH1 + Tx FIFO full signal for Tx channel 1. + 16 + 1 + read-only + + + OUTFIFO_EMPTY_L3_CH1 + Tx FIFO empty signal for Tx channel 1. + 17 + 1 + read-only + + + OUTFIFO_CNT_L3_CH1 + The register stores the byte number of the data in Tx FIFO for Tx channel 1. + 18 + 2 + read-only - A_ROI_REGION4_7_QP - Video A H264 ROI region4, region5,region6,region7 QP register. - 0x48 + OUT_PUSH_CH1 + TX CH1 outfifo push register + 0x118 0x20 - A_ROI_REGION4_QP - Configure H264 ROI region4 qp in video A,fixed qp or delta qp. + OUTFIFO_WDATA_CH1 + This register stores the data that need to be pushed into DMA Tx FIFO. 0 - 7 + 10 read-write - A_ROI_REGION5_QP - Configure H264 ROI region5 qp in video A,fixed qp or delta qp. - 7 - 7 + OUTFIFO_PUSH_CH1 + Set this bit to push data into DMA Tx FIFO. + 10 + 1 read-write + + + + OUT_LINK_CONF_CH1 + TX CH1 out_link dscr ctrl register + 0x11C + 0x20 + 0x00800000 + - A_ROI_REGION6_QP - Configure H264 ROI region6 qp in video A,fixed qp or delta qp. - 14 - 7 + OUTLINK_STOP_CH1 + Set this bit to stop dealing with the outlink descriptors. + 20 + 1 read-write - A_ROI_REGION7_QP - Configure H264 ROI region7 qp in video A,fixed qp or delta qp. + OUTLINK_START_CH1 + Set this bit to start dealing with the outlink descriptors. 21 - 7 + 1 + read-write + + + OUTLINK_RESTART_CH1 + Set this bit to restart a new outlink from the last address. + 22 + 1 read-write + + OUTLINK_PARK_CH1 + 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working. + 23 + 1 + read-only + - A_NO_ROI_REGION_QP_OFFSET - Video A H264 no roi region QP register. - 0x4C + OUT_LINK_ADDR_CH1 + TX CH1 out_link dscr addr register + 0x120 0x20 - A_NO_ROI_REGION_QP - Configure H264 no region qp in video A, delta qp. + OUTLINK_ADDR_CH1 + This register stores the first outlink descriptor's address. 0 - 7 + 32 read-write - A_ROI_CONFIG - Video A H264 ROI configure register. - 0x50 + OUT_STATE_CH1 + TX CH1 state register + 0x124 0x20 + 0x01000000 - A_ROI_EN - Configure whether or not to enable ROI in video A.\\0:not enable ROI\\1:enable ROI. + OUTLINK_DSCR_ADDR_CH1 + This register stores the current outlink descriptor's address. 0 - 1 - read-write + 18 + read-only - A_ROI_MODE - Configure the mode of ROI in video A.\\0:fixed qp\\1:delta qp. - 1 + OUT_DSCR_STATE_CH1 + This register stores the current descriptor state machine state. + 18 + 2 + read-only + + + OUT_STATE_CH1 + This register stores the current control module state machine state. + 20 + 4 + read-only + + + OUT_RESET_AVAIL_CH1 + This register indicate that if the channel reset is safety. + 24 1 - read-write + read-only - B_SYS_MB_RES - Video B horizontal and vertical MB resolution register. - 0x54 + OUT_EOF_DES_ADDR_CH1 + TX CH1 eof des addr register + 0x128 0x20 - B_SYS_TOTAL_MB_Y - Configures video B vertical MB resolution. + OUT_EOF_DES_ADDR_CH1 + This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1. 0 - 7 - read-write - - - B_SYS_TOTAL_MB_X - Configures video B horizontal MB resolution. - 7 - 7 - read-write + 32 + read-only - B_SYS_CONF - Video B system level configuration register. - 0x58 + OUT_DSCR_CH1 + TX CH1 next dscr addr register + 0x12C 0x20 - 0x00000203 - B_DB_TMP_READY_TRIGGER_MB_NUM - Configures when to trigger video B H264_DB_TMP_READY_INT. When the (MB number of written db temp+1) is greater than this filed in first MB line, trigger H264_DB_TMP_READY_INT. Min is 3. + OUTLINK_DSCR_CH1 + The address of the next outlink descriptor address y. 0 - 7 - read-write - - - B_REC_READY_TRIGGER_MB_LINES - Configures when to trigger video B H264_REC_READY_INT. When the MB line number of generated reconstruct pixel is greater than this filed, trigger H264_REC_READY_INT. Min is 4. - 7 - 7 - read-write - - - B_INTRA_COST_CMP_OFFSET - Configures video B intra cost offset when I MB compared with P MB. - 14 - 16 - read-write + 32 + read-only - B_DECI_SCORE - Video B luma and chroma MB decimate score Register. - 0x5C + OUT_DSCR_BF0_CH1 + TX CH1 last dscr addr register + 0x130 0x20 - B_C_DECI_SCORE - Configures video B chroma MB decimate score. When chroma score is smaller than it, chroma decimate will be enable. + OUTLINK_DSCR_BF0_CH1 + The address of the last outlink descriptor's next address y-1. 0 - 10 - read-write + 32 + read-only + + + + OUT_DSCR_BF1_CH1 + TX CH1 second-to-last dscr addr register + 0x134 + 0x20 + - B_L_DECI_SCORE - Configures video B luma MB decimate score. When luma score is smaller than it, luma decimate will be enable. - 10 - 10 - read-write + OUTLINK_DSCR_BF1_CH1 + The address of the second-to-last outlink descriptor's next address y-2. + 0 + 32 + read-only - B_DECI_SCORE_OFFSET - Video B luma and chroma MB decimate score offset Register. - 0x60 + OUT_ARB_CH1 + TX CH1 arb register + 0x13C 0x20 + 0x00000041 - B_I16X16_DECI_SCORE_OFFSET - Configures video B i16x16 MB decimate score offset. This offset will be added to i16x16 MB score. + OUT_ARB_TOKEN_NUM_CH1 + Set the max number of token count of arbiter 0 - 6 + 4 read-write - B_I_CHROMA_DECI_SCORE_OFFSET - Configures video B I chroma MB decimate score offset. This offset will be added to I chroma MB score. + INTER_OUT_ARB_PRIORITY_CH1 + Set the priority of channel 6 - 6 - read-write - - - B_P16X16_DECI_SCORE_OFFSET - Configures video B p16x16 MB decimate score offset. This offset will be added to p16x16 MB score. - 12 - 6 - read-write - - - B_P_CHROMA_DECI_SCORE_OFFSET - Configures video B p chroma MB decimate score offset. This offset will be added to p chroma MB score. - 18 - 6 + 1 read-write - B_RC_CONF0 - Video B rate control configuration register0. - 0x64 + OUT_ETM_CONF_CH1 + TX CH1 ETM config register + 0x168 0x20 + 0x00000004 - B_QP - Configures video B frame level initial luma QP value. + OUT_ETM_EN_CH1 + Set this bit to 1 to enable ETM task function 0 - 6 + 1 read-write - B_RATE_CTRL_U - Configures video B parameter U value. U = int((float) u << 8). - 6 - 16 + OUT_ETM_LOOP_EN_CH1 + when this bit is 1, dscr can be processed after receiving a task + 1 + 1 read-write - B_MB_RATE_CTRL_EN - Configures video A whether or not to open macro block rate ctrl.\\1:Open the macro block rate ctrl\\1:Close the macro block rate ctrl. - 22 - 1 + OUT_DSCR_TASK_MAK_CH1 + ETM dscr_ready maximum cache numbers + 2 + 2 read-write - B_RC_CONF1 - Video B rate control configuration register1. - 0x68 + OUT_BUF_LEN_CH1 + tx CH1 buf len register + 0x170 0x20 - B_CHROMA_DC_QP_DELTA - Configures video B chroma DC QP offset based on Chroma QP. Chroma DC QP = Chroma QP(after map) + reg_chroma_dc_qp_delta. + OUT_CMDFIFO_BUF_LEN_HB_CH1 + only for debug 0 - 3 - read-write - - - B_CHROMA_QP_DELTA - Configures video B chroma QP offset based on luma QP. Chroma QP(before map) = Luma QP + reg_chroma_qp_delta. - 3 - 4 - read-write - - - B_QP_MIN - Configures video B allowed luma QP min value. - 7 - 6 - read-write + 13 + read-only + + + + OUT_FIFO_BCNT_CH1 + tx CH1 fifo byte cnt register + 0x174 + 0x20 + - B_QP_MAX - Configures video B allowed luma QP max value. - 13 - 6 - read-write + OUT_CMDFIFO_OUTFIFO_BCNT_CH1 + only for debug + 0 + 10 + read-only + + + + OUT_PUSH_BYTECNT_CH1 + tx CH1 push byte cnt register + 0x178 + 0x20 + 0x000000FF + - B_MAD_FRAME_PRED - Configures vdieo B frame level predicted MB MAD value. - 19 - 12 - read-write + OUT_CMDFIFO_PUSH_BYTECNT_CH1 + only for debug + 0 + 8 + read-only - B_DB_BYPASS - Video B Deblocking bypass register - 0x6C + OUT_XADDR_CH1 + tx CH1 xaddr register + 0x17C 0x20 - B_BYPASS_DB_FILTER - Configures whether or not to bypass video B deblcoking filter. \\0: Open the deblock filter\\1: Close the deblock filter + OUT_CMDFIFO_XADDR_CH1 + only for debug 0 - 1 - read-write + 32 + read-only - B_ROI_REGION0 - Video B H264 ROI region0 range configure register. - 0x70 + OUT_CONF0_CH2 + TX CH2 config0 register + 0x200 0x20 + 0x00000002 - X - Configures the horizontal start macroblocks of region 0 in Video B. + OUT_AUTO_WRBACK_CH2 + Set this bit to enable automatic outlink-writeback when all the data pointed by outlink descriptor has been received. 0 - 7 + 1 read-write - Y - Configures the vertical start macroblocks of region 0 in Video B. - 7 - 7 + OUT_EOF_MODE_CH2 + EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is generated when data need to read has been popped from FIFO in DMA + 1 + 1 read-write - X_LEN - Configures the number of macroblocks in horizontal direction of the region 0 in Video B. - 14 - 7 + OUTDSCR_BURST_EN_CH2 + Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM. + 2 + 1 read-write - Y_LEN - Configures the number of macroblocks in vertical direction of the region 0 in Video B. - 21 - 7 + OUT_ECC_AES_EN_CH2 + When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned. + 3 + 1 read-write - EN - Configures whether or not to open Video B ROI of region 0 .\\0:Close ROI\\1:Open ROI. - 28 + OUT_CHECK_OWNER_CH2 + Set this bit to enable checking the owner attribute of the link descriptor. + 4 1 read-write - - - - B_ROI_REGION1 - Video B H264 ROI region1 range configure register. - 0x74 - 0x20 - - X - Configures the horizontal start macroblocks of region 1 in Video B. - 0 - 7 + OUT_MEM_BURST_LENGTH_CH2 + Block size of Tx channel 2. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes + 6 + 3 read-write - Y - Configures the vertical start macroblocks of region 1 in Video B. - 7 - 7 + OUT_PAGE_BOUND_EN_CH2 + Set this bit to 1 to make sure AXI read data don't cross the address boundary which define by mem_burst_length + 12 + 1 read-write - X_LEN - Configures the number of macroblocks in horizontal direction of the region 1 in Video B. - 14 - 7 + OUT_RST_CH2 + Write 1 then write 0 to this bit to reset TX channel + 24 + 1 read-write - Y_LEN - Configures the number of macroblocks in vertical direction of the region 1 in Video B. - 21 - 7 + OUT_CMD_DISABLE_CH2 + Write 1 before reset and write 0 after reset + 25 + 1 read-write - EN - Configures whether or not to open Video B ROI of region 1 .\\0:Close ROI\\1:Open ROI. - 28 + OUT_ARB_WEIGHT_OPT_DIS_CH2 + Set this bit to 1 to disable arbiter optimum weight function. + 26 1 read-write - B_ROI_REGION2 - Video B H264 ROI region2 range configure register. - 0x78 + OUT_INT_RAW_CH2 + TX CH2 interrupt raw register + 0x204 0x20 - X - Configures the horizontal start macroblocks of region 2 in Video B. + OUT_DONE_CH2_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0. 0 - 7 - read-write - - - Y - Configures the vertical start macroblocks of region 2 in Video B. - 7 - 7 + 1 read-write - X_LEN - Configures the number of macroblocks in horizontal direction of the region 2 in Video B. - 14 - 7 + OUT_EOF_CH2_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. + 1 + 1 read-write - Y_LEN - Configures the number of macroblocks in vertical direction of the region 2 in Video B. - 21 - 7 + OUT_DSCR_ERR_CH2_INT_RAW + The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0. + 2 + 1 read-write - EN - Configures whether or not to open Video B ROI of region 2 .\\0:Close ROI\\1:Open ROI. - 28 + OUT_TOTAL_EOF_CH2_INT_RAW + The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0. + 3 1 read-write - - - - B_ROI_REGION3 - Video B H264 ROI region3 range configure register. - 0x7C - 0x20 - - X - Configures the horizontal start macroblocks of region 3 in Video B. - 0 - 7 + OUTFIFO_OVF_L1_CH2_INT_RAW + The raw interrupt bit turns to high level when fifo is overflow. + 4 + 1 read-write - Y - Configures the vertical start macroblocks of region 3 in Video B. - 7 - 7 + OUTFIFO_UDF_L1_CH2_INT_RAW + The raw interrupt bit turns to high level when fifo is underflow. + 5 + 1 read-write - X_LEN - Configures the number of macroblocks in horizontal direction of the region 3 in video B. - 14 - 7 + OUTFIFO_OVF_L2_CH2_INT_RAW + The raw interrupt bit turns to high level when fifo is overflow. + 6 + 1 read-write - Y_LEN - Configures the number of macroblocks in vertical direction of the region 3 in video B. - 21 - 7 + OUTFIFO_UDF_L2_CH2_INT_RAW + The raw interrupt bit turns to high level when fifo is underflow. + 7 + 1 read-write - EN - Configures whether or not to open Video B ROI of region 3 .\\0:Close ROI\\1:Open ROI. - 28 + OUT_DSCR_TASK_OVF_CH2_INT_RAW + The raw interrupt bit turns to high level when dscr ready task fifo is overflow. + 8 1 read-write - B_ROI_REGION4 - Video B H264 ROI region4 range configure register. - 0x80 + OUT_INT_ENA_CH2 + TX CH2 interrupt ena register + 0x208 0x20 - X - Configures the horizontal start macroblocks of region 4 in Video B. + OUT_DONE_CH2_INT_ENA + The interrupt enable bit for the OUT_DONE_CH_INT interrupt. 0 - 7 - read-write - - - Y - Configures the vertical start macroblocks of region 4 in Video B. - 7 - 7 + 1 read-write - X_LEN - Configures the number of macroblocks in horizontal direction of the region 4 in video B. - 14 - 7 + OUT_EOF_CH2_INT_ENA + The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + 1 + 1 read-write - Y_LEN - Configures the number of macroblocks in vertical direction of the region 4 in video B. - 21 - 7 + OUT_DSCR_ERR_CH2_INT_ENA + The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 read-write - EN - Configures whether or not to open Video B ROI of region 4 .\\0:Close ROI\\1:Open ROI. - 28 + OUT_TOTAL_EOF_CH2_INT_ENA + The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + 3 1 read-write - - - - B_ROI_REGION5 - Video B H264 ROI region5 range configure register. - 0x84 - 0x20 - - X - Configures the horizontial start macroblocks of region 5 video B. - 0 - 7 + OUTFIFO_OVF_L1_CH2_INT_ENA + The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 read-write - Y - Configures the vertical start macroblocks of region 5 video B. - 7 - 7 + OUTFIFO_UDF_L1_CH2_INT_ENA + The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 read-write - X_LEN - Configures the number of macroblocks in horizontal direction of the region 5 video B. - 14 - 7 + OUTFIFO_OVF_L2_CH2_INT_ENA + The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 read-write - Y_LEN - Configures the number of macroblocks in vertical direction of the region 5 in video B. - 21 - 7 + OUTFIFO_UDF_L2_CH2_INT_ENA + The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 read-write - EN - Configures whether or not to open Video B ROI of region 5 .\\0:Close ROI\\1:Open ROI. - 28 + OUT_DSCR_TASK_OVF_CH2_INT_ENA + The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. + 8 1 read-write - B_ROI_REGION6 - Video B H264 ROI region6 range configure register. - 0x88 + OUT_INT_ST_CH2 + TX CH2 interrupt st register + 0x20C 0x20 - X - Configures the horizontial start macroblocks of region 6 video B. + OUT_DONE_CH2_INT_ST + The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. 0 - 7 - read-write - - - Y - Configures the vertical start macroblocks of region 6 in video B. - 7 - 7 - read-write + 1 + read-only - X_LEN - Configures the number of macroblocks in horizontal direction of the region 6 in video B. - 14 - 7 - read-write + OUT_EOF_CH2_INT_ST + The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + 1 + 1 + read-only - Y_LEN - Configures the number of macroblocks in vertical direction of the region 6 in video B. - 21 - 7 - read-write + OUT_DSCR_ERR_CH2_INT_ST + The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + read-only - EN - Configures whether or not to open Video B ROI of region 6 .\\0:Close ROI\\1:Open ROI. - 28 + OUT_TOTAL_EOF_CH2_INT_ST + The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + 3 1 - read-write + read-only - - - - B_ROI_REGION7 - Video B H264 ROI region7 range configure register. - 0x8C - 0x20 - - X - Configures the horizontal start macroblocks of region 7 in video B. - 0 - 7 - read-write + OUTFIFO_OVF_L1_CH2_INT_ST + The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-only - Y - Configures the vertical start macroblocks of region 7 in video B. - 7 - 7 - read-write + OUTFIFO_UDF_L1_CH2_INT_ST + The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-only - X_LEN - Configures the number of macroblocks in horizontal direction of the region 7 in video B. - 14 - 7 - read-write + OUTFIFO_OVF_L2_CH2_INT_ST + The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + read-only - Y_LEN - Configures the number of macroblocks in vertical direction of the region 7 in video B. - 21 - 7 - read-write + OUTFIFO_UDF_L2_CH2_INT_ST + The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + read-only - EN - Configures whether or not to open Video B ROI of region 7 .\\0:Close ROI\\1:Open ROI. - 28 + OUT_DSCR_TASK_OVF_CH2_INT_ST + The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. + 8 1 - read-write + read-only - B_ROI_REGION0_3_QP - Video B H264 ROI region0, region1,region2,region3 QP register. - 0x90 + OUT_INT_CLR_CH2 + TX CH2 interrupt clr register + 0x210 0x20 - B_ROI_REGION0_QP - Configure H264 ROI region0 qp in video B,fixed qp or delta qp. + OUT_DONE_CH2_INT_CLR + Set this bit to clear the OUT_DONE_CH_INT interrupt. 0 - 7 - read-write + 1 + write-only - B_ROI_REGION1_QP - Configure H264 ROI region1 qp in video B,fixed qp or delta qp. - 7 - 7 - read-write + OUT_EOF_CH2_INT_CLR + Set this bit to clear the OUT_EOF_CH_INT interrupt. + 1 + 1 + write-only - B_ROI_REGION2_QP - Configure H264 ROI region2 qp in video B,fixed qp or delta qp. - 14 - 7 - read-write + OUT_DSCR_ERR_CH2_INT_CLR + Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + write-only - B_ROI_REGION3_QP - Configure H264 ROI region3 qp in video B,fixed qp or delta qp. - 21 - 7 - read-write + OUT_TOTAL_EOF_CH2_INT_CLR + Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + write-only + + + OUTFIFO_OVF_L1_CH2_INT_CLR + Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + write-only + + + OUTFIFO_UDF_L1_CH2_INT_CLR + Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + write-only + + + OUTFIFO_OVF_L2_CH2_INT_CLR + Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + write-only + + + OUTFIFO_UDF_L2_CH2_INT_CLR + Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + write-only + + + OUT_DSCR_TASK_OVF_CH2_INT_CLR + Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt. + 8 + 1 + write-only - B_ROI_REGION4_7_QP - Video B H264 ROI region4, region5,region6,region7 QP register. - 0x94 + OUTFIFO_STATUS_CH2 + TX CH2 outfifo status register + 0x214 0x20 + 0x00020082 - B_ROI_REGION4_QP - Configure H264 ROI region4 qp in video B,fixed qp or delta qp. + OUTFIFO_FULL_L2_CH2 + Tx FIFO full signal for Tx channel 2. 0 - 7 - read-write + 1 + read-only - B_ROI_REGION5_QP - Configure H264 ROI region5 qp in video B,fixed qp or delta qp. + OUTFIFO_EMPTY_L2_CH2 + Tx FIFO empty signal for Tx channel 2. + 1 + 1 + read-only + + + OUTFIFO_CNT_L2_CH2 + The register stores the byte number of the data in Tx FIFO for Tx channel 2. + 2 + 4 + read-only + + + OUTFIFO_FULL_L1_CH2 + Tx FIFO full signal for Tx channel 2. + 6 + 1 + read-only + + + OUTFIFO_EMPTY_L1_CH2 + Tx FIFO empty signal for Tx channel 2. 7 - 7 - read-write + 1 + read-only - B_ROI_REGION6_QP - Configure H264 ROI region6 qp in video B,fixed qp or delta qp. - 14 - 7 - read-write + OUTFIFO_CNT_L1_CH2 + The register stores the byte number of the data in Tx FIFO for Tx channel 2. + 8 + 5 + read-only - B_ROI_REGION7_QP - Configure H264 ROI region7 qp in video B,fixed qp or delta qp. - 21 - 7 - read-write + OUTFIFO_FULL_L3_CH2 + Tx FIFO full signal for Tx channel 2. + 16 + 1 + read-only + + + OUTFIFO_EMPTY_L3_CH2 + Tx FIFO empty signal for Tx channel 2. + 17 + 1 + read-only + + + OUTFIFO_CNT_L3_CH2 + The register stores the byte number of the data in Tx FIFO for Tx channel 2. + 18 + 2 + read-only - B_NO_ROI_REGION_QP_OFFSET - Video B H264 no roi region QP register. - 0x98 + OUT_PUSH_CH2 + TX CH2 outfifo push register + 0x218 0x20 - B_NO_ROI_REGION_QP - Configure H264 no region qp in video B, delta qp. + OUTFIFO_WDATA_CH2 + This register stores the data that need to be pushed into DMA Tx FIFO. 0 - 7 + 10 + read-write + + + OUTFIFO_PUSH_CH2 + Set this bit to push data into DMA Tx FIFO. + 10 + 1 read-write - B_ROI_CONFIG - Video B H264 ROI configure register. - 0x9C + OUT_LINK_CONF_CH2 + TX CH2 out_link dscr ctrl register + 0x21C 0x20 + 0x00800000 - B_ROI_EN - Configure whether or not to enable ROI in video B.\\0:not enable ROI\\1:enable ROI. - 0 + OUTLINK_STOP_CH2 + Set this bit to stop dealing with the outlink descriptors. + 20 1 read-write - B_ROI_MODE - Configure the mode of ROI in video B.\\0:fixed qp\\1:delta qp. - 1 + OUTLINK_START_CH2 + Set this bit to start dealing with the outlink descriptors. + 21 1 read-write - - - - RC_STATUS0 - Rate control status register0. - 0xA0 - 0x20 - - FRAME_MAD_SUM - Represents all MB actual MAD sum value of one frame. - 0 - 21 + OUTLINK_RESTART_CH2 + Set this bit to restart a new outlink from the last address. + 22 + 1 + read-write + + + OUTLINK_PARK_CH2 + 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working. + 23 + 1 read-only - RC_STATUS1 - Rate control status register1. - 0xA4 + OUT_LINK_ADDR_CH2 + TX CH2 out_link dscr addr register + 0x220 0x20 - FRAME_ENC_BITS - Represents all MB actual encoding bits sum value of one frame. + OUTLINK_ADDR_CH2 + This register stores the first outlink descriptor's address. 0 - 27 - read-only + 32 + read-write - RC_STATUS2 - Rate control status register2. - 0xA8 + OUT_STATE_CH2 + TX CH2 state register + 0x224 0x20 + 0x01000000 - FRAME_QP_SUM - Represents all MB actual luma QP sum value of one frame. + OUTLINK_DSCR_ADDR_CH2 + This register stores the current outlink descriptor's address. 0 - 19 + 18 + read-only + + + OUT_DSCR_STATE_CH2 + This register stores the current descriptor state machine state. + 18 + 2 + read-only + + + OUT_STATE_CH2 + This register stores the current control module state machine state. + 20 + 4 + read-only + + + OUT_RESET_AVAIL_CH2 + This register indicate that if the channel reset is safety. + 24 + 1 read-only - SLICE_HEADER_REMAIN - Frame Slice Header remain bit register. - 0xAC + OUT_EOF_DES_ADDR_CH2 + TX CH2 eof des addr register + 0x228 0x20 - SLICE_REMAIN_BITLENGTH - Configures Slice Header remain bit number + OUT_EOF_DES_ADDR_CH2 + This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. 0 - 3 - read-write - - - SLICE_REMAIN_BIT - Configures Slice Header remain bit - 3 - 8 - read-write + 32 + read-only - SLICE_HEADER_BYTE_LENGTH - Frame Slice Header byte length register. - 0xB0 + OUT_DSCR_CH2 + TX CH2 next dscr addr register + 0x22C 0x20 - SLICE_BYTE_LENGTH - Configures Slice Header byte number + OUTLINK_DSCR_CH2 + The address of the next outlink descriptor address y. 0 - 4 - read-write + 32 + read-only - BS_THRESHOLD - Bitstream buffer overflow threshold register - 0xB4 + OUT_DSCR_BF0_CH2 + TX CH2 last dscr addr register + 0x230 0x20 - 0x00000030 - BS_BUFFER_THRESHOLD - Configures bitstream buffer overflow threshold. This value should be bigger than the encode bytes of one 4x4 submb. + OUTLINK_DSCR_BF0_CH2 + The address of the last outlink descriptor's next address y-1. 0 - 7 - read-write + 32 + read-only - SLICE_HEADER_BYTE0 - Frame Slice Header byte low 32 bit register. - 0xB8 + OUT_DSCR_BF1_CH2 + TX CH2 second-to-last dscr addr register + 0x234 0x20 - SLICE_BYTE_LSB - Configures Slice Header low 32 bit + OUTLINK_DSCR_BF1_CH2 + The address of the second-to-last outlink descriptor's next address y-2. 0 32 - read-write + read-only - SLICE_HEADER_BYTE1 - Frame Slice Header byte high 32 bit register. - 0xBC + OUT_ARB_CH2 + TX CH2 arb register + 0x23C 0x20 + 0x00000041 - SLICE_BYTE_MSB - Configures Slice Header high 32 bit + OUT_ARB_TOKEN_NUM_CH2 + Set the max number of token count of arbiter 0 - 32 + 4 + read-write + + + INTER_OUT_ARB_PRIORITY_CH2 + Set the priority of channel + 6 + 1 read-write - INT_RAW - Interrupt raw status register - 0xC0 + OUT_ETM_CONF_CH2 + TX CH2 ETM config register + 0x268 0x20 + 0x00000004 - DB_TMP_READY_INT_RAW - Raw status bit: The raw interrupt status of H264_DB_TMP_READY_INT. Triggered when H264 written enough db tmp pixel. + OUT_ETM_EN_CH2 + Set this bit to 1 to enable ETM task function 0 1 read-write - REC_READY_INT_RAW - Raw status bit: The raw interrupt status of H264_REC_READY_INT. Triggered when H264 encoding enough reconstruct pixel. + OUT_ETM_LOOP_EN_CH2 + when this bit is 1, dscr can be processed after receiving a task 1 1 read-write - FRAME_DONE_INT_RAW - Raw status bit: The raw interrupt status of H264_FRAME_DONE_INT. Triggered when H264 encoding one frame done. + OUT_DSCR_TASK_MAK_CH2 + ETM dscr_ready maximum cache numbers 2 - 1 - read-write - - - DMA_MOVE_2MB_LINE_DONE_INT_RAW - Raw status bit: The raw interrupt status of H264_DMA_MOVE_2MB_LINE_DONE_INT. Triggered when H264 move two MB lines of reference frame from external mem to internal mem done. - 3 - 1 + 2 read-write - INT_ST - Interrupt masked status register - 0xC4 + OUT_BUF_LEN_CH2 + tx CH2 buf len register + 0x270 0x20 - DB_TMP_READY_INT_ST - The masked interrupt status of H264_DB_TMP_READY_INT. Valid only when the H264_DB_TMP_READY_INT_ENA is set to 1. + OUT_CMDFIFO_BUF_LEN_HB_CH2 + only for debug 0 - 1 + 13 read-only + + + + OUT_FIFO_BCNT_CH2 + tx CH2 fifo byte cnt register + 0x274 + 0x20 + - REC_READY_INT_ST - The masked interrupt status of H264_REC_READY_INT. Valid only when the H264_REC_READY_INT_ENA is set to 1. - 1 - 1 + OUT_CMDFIFO_OUTFIFO_BCNT_CH2 + only for debug + 0 + 10 read-only + + + + OUT_PUSH_BYTECNT_CH2 + tx CH2 push byte cnt register + 0x278 + 0x20 + 0x000000FF + - FRAME_DONE_INT_ST - The masked interrupt status of H264_FRAME_DONE_INT. Valid only when the H264_FRAME_DONE_INT_ENA is set to 1. - 2 - 1 + OUT_CMDFIFO_PUSH_BYTECNT_CH2 + only for debug + 0 + 8 read-only + + + + OUT_XADDR_CH2 + tx CH2 xaddr register + 0x27C + 0x20 + - DMA_MOVE_2MB_LINE_DONE_INT_ST - Masked status bit: The masked interrupt status of H264_DMA_MOVE_2MB_LINE_DONE_INT. Valid only when the H264_DMA_MOVE_2MB_LINE_DONE_INT_ENA is set to 1. - 3 - 1 + OUT_CMDFIFO_XADDR_CH2 + only for debug + 0 + 32 read-only - INT_ENA - Interrupt enable register - 0xC8 + OUT_CONF0_CH3 + TX CH3 config0 register + 0x300 0x20 + 0x00000002 - DB_TMP_READY_INT_ENA - Write 1 to enable H264_DB_TMP_READY_INT. + OUT_AUTO_WRBACK_CH3 + Set this bit to enable automatic outlink-writeback when all the data pointed by outlink descriptor has been received. 0 1 read-write - REC_READY_INT_ENA - Write 1 to enable H264_REC_READY_INT. + OUT_EOF_MODE_CH3 + EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is generated when data need to read has been popped from FIFO in DMA 1 1 read-write - FRAME_DONE_INT_ENA - Write 1 to enable H264_FRAME_DONE_INT. + OUTDSCR_BURST_EN_CH3 + Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM. 2 1 read-write - DMA_MOVE_2MB_LINE_DONE_INT_ENA - Enable bit: Write 1 to enable H264_DMA_MOVE_2MB_LINE_DONE_INT. + OUT_ECC_AES_EN_CH3 + When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned. 3 1 read-write - - - - INT_CLR - Interrupt clear register - 0xCC - 0x20 - - DB_TMP_READY_INT_CLR - Write 1 to clear H264_DB_TMP_READY_INT. - 0 + OUT_CHECK_OWNER_CH3 + Set this bit to enable checking the owner attribute of the link descriptor. + 4 1 - write-only + read-write - REC_READY_INT_CLR - Write 1 to clear H264_REC_READY_INT. - 1 - 1 - write-only + OUT_MEM_BURST_LENGTH_CH3 + Block size of Tx channel 3. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes + 6 + 3 + read-write - FRAME_DONE_INT_CLR - Write 1 to clear H264_FRAME_DONE_INT. - 2 + OUT_PAGE_BOUND_EN_CH3 + Set this bit to 1 to make sure AXI read data don't cross the address boundary which define by mem_burst_length + 12 1 - write-only + read-write - DMA_MOVE_2MB_LINE_DONE_INT_CLR - Clear bit: Write 1 to clear H264_DMA_MOVE_2MB_LINE_DONE_INT. - 3 + OUT_ARB_WEIGHT_OPT_DIS_CH3 + Set this bit to 1 to disable arbiter optimum weight function. + 26 1 - write-only + read-write - CONF - General configuration register. - 0xD0 + OUT_INT_RAW_CH3 + TX CH3 interrupt raw register + 0x304 0x20 - CLK_EN - Configures whether or not to open register clock gate.\\0: Open the clock gate only when application writes registers\\1: Force open the clock gate for register + OUT_DONE_CH3_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0. 0 1 read-write - REC_RAM_CLK_EN2 - Configures whether or not to open the clock gate for rec ram2.\\0: Open the clock gate only when application writes or reads rec ram2\\1: Force open the clock gate for rec ram2 + OUT_EOF_CH3_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. 1 1 read-write - REC_RAM_CLK_EN1 - Configures whether or not to open the clock gate for rec ram1.\\0: Open the clock gate only when application writes or reads rec ram1\\1: Force open the clock gate for rec ram1 + OUT_DSCR_ERR_CH3_INT_RAW + The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0. 2 1 read-write - QUANT_RAM_CLK_EN2 - Configures whether or not to open the clock gate for quant ram2.\\0: Open the clock gate only when application writes or reads quant ram2\\1: Force open the clock gate for quant ram2 + OUT_TOTAL_EOF_CH3_INT_RAW + The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0. 3 1 read-write - QUANT_RAM_CLK_EN1 - Configures whether or not to open the clock gate for quant ram1.\\0: Open the clock gate only when application writes or reads quant ram1\\1: Force open the clock gate for quant ram1 + OUTFIFO_OVF_L1_CH3_INT_RAW + The raw interrupt bit turns to high level when fifo is overflow. 4 1 read-write - PRE_RAM_CLK_EN - Configures whether or not to open the clock gate for pre ram.\\0: Open the clock gate only when application writes or reads pre ram\\1: Force open the clock gate for pre ram + OUTFIFO_UDF_L1_CH3_INT_RAW + The raw interrupt bit turns to high level when fifo is underflow. 5 1 read-write - MVD_RAM_CLK_EN - Configures whether or not to open the clock gate for mvd ram.\\0: Open the clock gate only when application writes or reads mvd ram\\1: Force open the clock gate for mvd ram + OUTFIFO_OVF_L2_CH3_INT_RAW + The raw interrupt bit turns to high level when fifo is overflow. 6 1 read-write - MC_RAM_CLK_EN - Configures whether or not to open the clock gate for mc ram.\\0: Open the clock gate only when application writes or reads mc ram\\1: Force open the clock gate for mc ram + OUTFIFO_UDF_L2_CH3_INT_RAW + The raw interrupt bit turns to high level when fifo is underflow. 7 1 read-write - REF_RAM_CLK_EN - Configures whether or not to open the clock gate for ref ram.\\0: Open the clock gate only when application writes or reads ref ram\\1: Force open the clock gate for ref ram + OUT_DSCR_TASK_OVF_CH3_INT_RAW + The raw interrupt bit turns to high level when dscr ready task fifo is overflow. 8 1 read-write + + + + OUT_INT_ENA_CH3 + TX CH3 interrupt ena register + 0x308 + 0x20 + - I4X4_REF_RAM_CLK_EN - Configures whether or not to open the clock gate for i4x4_mode ram.\\0: Open the clock gate only when application writes or reads i4x4_mode ram\\1: Force open the clock gate for i4x4_mode ram - 9 + OUT_DONE_CH3_INT_ENA + The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + 0 1 read-write - IME_RAM_CLK_EN - Configures whether or not to open the clock gate for ime ram.\\0: Open the clock gate only when application writes or reads ime ram\\1: Force open the clock gate for ime ram - 10 + OUT_EOF_CH3_INT_ENA + The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + 1 1 read-write - FME_RAM_CLK_EN - Configures whether or not to open the clock gate for fme ram.\\0: Open the clock gate only when application writes or readsfme ram\\1: Force open the clock gate for fme ram - 11 + OUT_DSCR_ERR_CH3_INT_ENA + The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + 2 1 read-write - FETCH_RAM_CLK_EN - Configures whether or not to open the clock gate for fetch ram.\\0: Open the clock gate only when application writes or reads fetch ram\\1: Force open the clock gate for fetch ram - 12 + OUT_TOTAL_EOF_CH3_INT_ENA + The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + 3 1 read-write - DB_RAM_CLK_EN - Configures whether or not to open the clock gate for db ram.\\0: Open the clock gate only when application writes or reads db ram\\1: Force open the clock gate for db ram - 13 + OUTFIFO_OVF_L1_CH3_INT_ENA + The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 1 read-write - CUR_MB_RAM_CLK_EN - Configures whether or not to open the clock gate for cur_mb ram.\\0: Open the clock gate only when application writes or reads cur_mb ram\\1: Force open the clock gate for cur_mb ram - 14 + OUTFIFO_UDF_L1_CH3_INT_ENA + The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 1 read-write - CAVLC_RAM_CLK_EN - Configures whether or not to open the clock gate for cavlc ram.\\0: Open the clock gate only when application writes or reads cavlc ram\\1: Force open the clock gate for cavlc ram - 15 + OUTFIFO_OVF_L2_CH3_INT_ENA + The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. + 6 1 read-write - IME_CLK_EN - Configures whether or not to open the clock gate for ime.\\0: Open the clock gate only when ime work\\1: Force open the clock gate for ime - 16 + OUTFIFO_UDF_L2_CH3_INT_ENA + The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. + 7 1 read-write - FME_CLK_EN - Configures whether or not to open the clock gate for fme.\\0: Open the clock gate only when fme work\\1: Force open the clock gate for fme - 17 + OUT_DSCR_TASK_OVF_CH3_INT_ENA + The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. + 8 1 read-write + + + + OUT_INT_ST_CH3 + TX CH3 interrupt st register + 0x30C + 0x20 + - MC_CLK_EN - Configures whether or not to open the clock gate for mc.\\0: Open the clock gate only when mc work\\1: Force open the clock gate for mc - 18 + OUT_DONE_CH3_INT_ST + The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + 0 1 - read-write + read-only - INTERPOLATOR_CLK_EN - Configures whether or not to open the clock gate for interpolator.\\0: Open the clock gate only when interpolator work\\1: Force open the clock gate for interpolator - 19 + OUT_EOF_CH3_INT_ST + The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + 1 1 - read-write + read-only - DB_CLK_EN - Configures whether or not to open the clock gate for deblocking filter.\\0: Open the clock gate only when deblocking filter work\\1: Force open the clock gate for deblocking filter - 20 + OUT_DSCR_ERR_CH3_INT_ST + The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + 2 1 - read-write + read-only - CLAVLC_CLK_EN - Configures whether or not to open the clock gate for cavlc.\\0: Open the clock gate only when cavlc work\\1: Force open the clock gate for cavlc - 21 + OUT_TOTAL_EOF_CH3_INT_ST + The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + 3 1 - read-write + read-only - INTRA_CLK_EN - Configures whether or not to open the clock gate for intra.\\0: Open the clock gate only when intra work\\1: Force open the clock gate for intra - 22 + OUTFIFO_OVF_L1_CH3_INT_ST + The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 1 - read-write + read-only - DECI_CLK_EN - Configures whether or not to open the clock gate for decimate.\\0: Open the clock gate only when decimate work\\1: Force open the clock gate for decimate - 23 + OUTFIFO_UDF_L1_CH3_INT_ST + The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 1 - read-write + read-only - BS_CLK_EN - Configures whether or not to open the clock gate for bs buffer.\\0: Open the clock gate only when bs buffer work\\1: Force open the clock gate for bs buffer - 24 + OUTFIFO_OVF_L2_CH3_INT_ST + The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. + 6 1 - read-write + read-only - MV_MERGE_CLK_EN - Configures whether or not to open the clock gate for mv merge.\\0: Open the clock gate only when mv merge work\\1: Force open the clock gate for mv merge - 25 + OUTFIFO_UDF_L2_CH3_INT_ST + The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. + 7 1 - read-write + read-only + + + OUT_DSCR_TASK_OVF_CH3_INT_ST + The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. + 8 + 1 + read-only - MV_MERGE_CONFIG - Mv merge configuration register. - 0xD4 + OUT_INT_CLR_CH3 + TX CH3 interrupt clr register + 0x310 0x20 - MV_MERGE_TYPE - Configure mv merge type.\\0: merge p16x16 mv\\1: merge min mv\\2: merge max mv\\3: not valid. + OUT_DONE_CH3_INT_CLR + Set this bit to clear the OUT_DONE_CH_INT interrupt. 0 - 2 - read-write + 1 + write-only - INT_MV_OUT_EN - Configure mv merge output integer part not zero mv or all part not zero mv.\\0: output all part not zero mv\\1: output integer part not zero mv. + OUT_EOF_CH3_INT_CLR + Set this bit to clear the OUT_EOF_CH_INT interrupt. + 1 + 1 + write-only + + + OUT_DSCR_ERR_CH3_INT_CLR + Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. 2 1 - read-write + write-only - A_MV_MERGE_EN - Configure whether or not to enable video A mv merge.\\0: disable\\1: enable. + OUT_TOTAL_EOF_CH3_INT_CLR + Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. 3 1 - read-write + write-only - B_MV_MERGE_EN - Configure whether or not to enable video B mv merge.\\0: disable\\1: enable. + OUTFIFO_OVF_L1_CH3_INT_CLR + Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. 4 1 - read-write + write-only - MB_VALID_NUM - Represents the valid mb number of mv merge output. + OUTFIFO_UDF_L1_CH3_INT_CLR + Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. 5 - 13 - read-only - - - - - DEBUG_DMA_SEL - Debug H264 DMA select register - 0xD8 - 0x20 - - - DBG_DMA_SEL - Every bit represents a dma in h264 - 0 - 8 - read-write + 1 + write-only - - - - SYS_STATUS - System status register. - 0xDC - 0x20 - - FRAME_NUM - Represents current frame number. - 0 - 9 - read-only + OUTFIFO_OVF_L2_CH3_INT_CLR + Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + write-only - DUAL_STREAM_SEL - Represents which register group is used for cur frame.\\0: Register group A is used\\1: Register group B is used. - 9 + OUTFIFO_UDF_L2_CH3_INT_CLR + Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. + 7 1 - read-only + write-only - INTRA_FLAG - Represents the type of current encoding frame.\\0: P frame\\1: I frame. - 10 + OUT_DSCR_TASK_OVF_CH3_INT_CLR + Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt. + 8 1 - read-only + write-only - FRAME_CODE_LENGTH - Frame code byte length register. - 0xE0 + OUTFIFO_STATUS_CH3 + TX CH3 outfifo status register + 0x314 0x20 + 0x00020082 - FRAME_CODE_LENGTH - Represents current frame code byte length. + OUTFIFO_FULL_L2_CH3 + Tx FIFO full signal for Tx channel 2. 0 - 24 + 1 read-only - - - - DEBUG_INFO0 - Debug information register0. - 0xE4 - 0x20 - - TOP_CTRL_INTER_DEBUG_STATE - Represents top_ctrl_inter module FSM info. - 0 + OUTFIFO_EMPTY_L2_CH3 + Tx FIFO empty signal for Tx channel 2. + 1 + 1 + read-only + + + OUTFIFO_CNT_L2_CH3 + The register stores the byte number of the data in Tx FIFO for Tx channel 2. + 2 4 read-only - TOP_CTRL_INTRA_DEBUG_STATE - Represents top_ctrl_intra module FSM info. - 4 - 3 + OUTFIFO_FULL_L1_CH3 + Tx FIFO full signal for Tx channel 2. + 6 + 1 read-only - P_I_CMP_DEBUG_STATE - Represents p_i_cmp module FSM info. + OUTFIFO_EMPTY_L1_CH3 + Tx FIFO empty signal for Tx channel 2. 7 - 3 + 1 read-only - MVD_DEBUG_STATE - Represents mvd module FSM info. - 10 - 3 + OUTFIFO_CNT_L1_CH3 + The register stores the byte number of the data in Tx FIFO for Tx channel 2. + 8 + 5 read-only - MC_CHROMA_IP_DEBUG_STATE - Represents mc_chroma_ip module FSM info. - 13 + OUTFIFO_FULL_L3_CH3 + Tx FIFO full signal for Tx channel 2. + 16 1 read-only - INTRA_16X16_CHROMA_CTRL_DEBUG_STATE - Represents intra_16x16_chroma_ctrl module FSM info. - 14 - 4 + OUTFIFO_EMPTY_L3_CH3 + Tx FIFO empty signal for Tx channel 2. + 17 + 1 read-only - INTRA_4X4_CTRL_DEBUG_STATE - Represents intra_4x4_ctrl module FSM info. + OUTFIFO_CNT_L3_CH3 + The register stores the byte number of the data in Tx FIFO for Tx channel 2. 18 - 4 + 2 read-only + + + + OUT_PUSH_CH3 + TX CH3 outfifo push register + 0x318 + 0x20 + - INTRA_TOP_CTRL_DEBUG_STATE - Represents intra_top_ctrl module FSM info. - 22 - 3 - read-only + OUTFIFO_WDATA_CH3 + This register stores the data that need to be pushed into DMA Tx FIFO. + 0 + 10 + read-write - IME_CTRL_DEBUG_STATE - Represents ime_ctrl module FSM info. - 25 - 3 - read-only + OUTFIFO_PUSH_CH3 + Set this bit to push data into DMA Tx FIFO. + 10 + 1 + read-write - DEBUG_INFO1 - Debug information register1. - 0xE8 + OUT_LINK_CONF_CH3 + TX CH3 out_link dscr ctrl register + 0x31C 0x20 + 0x00800000 - FME_CTRL_DEBUG_STATE - Represents fme_ctrl module FSM info. - 0 - 3 - read-only + OUTLINK_STOP_CH3 + Set this bit to stop dealing with the outlink descriptors. + 20 + 1 + read-write - DECI_CALC_DEBUG_STATE - Represents deci_calc module's FSM info. DEV use only. - 3 - 2 - read-only + OUTLINK_START_CH3 + Set this bit to start dealing with the outlink descriptors. + 21 + 1 + read-write - DB_DEBUG_STATE - Represents db module FSM info. - 5 - 3 - read-only + OUTLINK_RESTART_CH3 + Set this bit to restart a new outlink from the last address. + 22 + 1 + read-write - CAVLC_ENC_DEBUG_STATE - Represents cavlc module enc FSM info. - 8 - 4 + OUTLINK_PARK_CH3 + 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working. + 23 + 1 read-only + + + + OUT_LINK_ADDR_CH3 + TX CH3 out_link dscr addr register + 0x320 + 0x20 + - CAVLC_SCAN_DEBUG_STATE - Represents cavlc module scan FSM info. - 12 - 4 - read-only - - - CAVLC_CTRL_DEBUG_STATE - Represents cavlc module ctrl FSM info. - 16 - 2 - read-only - - - BS_BUFFER_DEBUG_STATE - Represents bs buffer overflow info. - 18 - 1 - read-only + OUTLINK_ADDR_CH3 + This register stores the first outlink descriptor's address. + 0 + 32 + read-write - DEBUG_INFO2 - Debug information register2. - 0xEC + OUT_STATE_CH3 + TX CH3 state register + 0x324 0x20 - P_RC_DONE_DEBUG_FLAG - Represents p rate ctrl done status.\\0: not done\\1: done. + OUTLINK_DSCR_ADDR_CH3 + This register stores the current outlink descriptor's address. 0 - 1 - read-only - - - P_P_I_CMP_DONE_DEBUG_FLAG - Represents p p_i_cmp done status.\\0: not done\\1: done. - 1 - 1 - read-only - - - P_MV_MERGE_DONE_DEBUG_FLAG - Represents p mv merge done status.\\0: not done\\1: done. - 2 - 1 + 18 read-only - P_MOVE_ORI_DONE_DEBUG_FLAG - Represents p move origin done status.\\0: not done\\1: done. - 3 - 1 + OUT_DSCR_STATE_CH3 + This register stores the current descriptor state machine state. + 18 + 2 read-only - P_MC_DONE_DEBUG_FLAG - Represents p mc done status.\\0: not done\\1: done. - 4 - 1 + OUT_STATE_CH3 + This register stores the current control module state machine state. + 20 + 4 read-only + + + + OUT_EOF_DES_ADDR_CH3 + TX CH3 eof des addr register + 0x328 + 0x20 + - P_IME_DONE_DEBUG_FLAG - Represents p ime done status.\\0: not done\\1: done. - 5 - 1 + OUT_EOF_DES_ADDR_CH3 + This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. + 0 + 32 read-only + + + + OUT_DSCR_CH3 + TX CH3 next dscr addr register + 0x32C + 0x20 + - P_GET_ORI_DONE_DEBUG_FLAG - Represents p get origin done status.\\0: not done\\1: done. - 6 - 1 + OUTLINK_DSCR_CH3 + The address of the next outlink descriptor address y. + 0 + 32 read-only + + + + OUT_DSCR_BF0_CH3 + TX CH3 last dscr addr register + 0x330 + 0x20 + - P_FME_DONE_DEBUG_FLAG - Represents p fme done status.\\0: not done\\1: done. - 7 - 1 + OUTLINK_DSCR_BF0_CH3 + The address of the last outlink descriptor's next address y-1. + 0 + 32 read-only + + + + OUT_DSCR_BF1_CH3 + TX CH3 second-to-last dscr addr register + 0x334 + 0x20 + - P_FETCH_DONE_DEBUG_FLAG - Represents p fetch done status.\\0: not done\\1: done. - 8 - 1 + OUTLINK_DSCR_BF1_CH3 + The address of the second-to-last outlink descriptor's next address y-2. + 0 + 32 read-only + + + + OUT_ARB_CH3 + TX CH3 arb register + 0x33C + 0x20 + 0x00000011 + - P_DB_DONE_DEBUG_FLAG - Represents p deblocking done status.\\0: not done\\1: done. - 9 - 1 - read-only + OUT_ARB_TOKEN_NUM_CH3 + Set the max number of token count of arbiter + 0 + 4 + read-write - P_BS_BUF_DONE_DEBUG_FLAG - Represents p bitstream buffer done status.\\0: not done\\1: done. - 10 - 1 - read-only + EXTER_OUT_ARB_PRIORITY_CH3 + Set the priority of channel + 4 + 2 + read-write + + + + OUT_ETM_CONF_CH3 + TX CH3 ETM config register + 0x368 + 0x20 + 0x00000004 + - REF_MOVE_2MB_LINE_DONE_DEBUG_FLAG - Represents dma move 2 ref mb line done status.\\0: not done\\1: done. - 11 + OUT_ETM_EN_CH3 + Set this bit to 1 to enable ETM task function + 0 1 - read-only + read-write - I_P_I_CMP_DONE_DEBUG_FLAG - Represents I p_i_cmp done status.\\0: not done\\1: done. - 12 + OUT_ETM_LOOP_EN_CH3 + when this bit is 1, dscr can be processed after receiving a task + 1 1 - read-only + read-write - I_MOVE_ORI_DONE_DEBUG_FLAG - Represents I move origin done status.\\0: not done\\1: done. - 13 - 1 - read-only + OUT_DSCR_TASK_MAK_CH3 + ETM dscr_ready maximum cache numbers + 2 + 2 + read-write + + + + OUT_BUF_LEN_CH3 + tx CH3 buf len register + 0x370 + 0x20 + - I_GET_ORI_DONE_DEBUG_FLAG - Represents I get origin done status.\\0: not done\\1: done. - 14 - 1 + OUT_CMDFIFO_BUF_LEN_HB_CH3 + only for debug + 0 + 13 read-only + + + + OUT_FIFO_BCNT_CH3 + tx CH3 fifo byte cnt register + 0x374 + 0x20 + - I_EC_DONE_DEBUG_FLAG - Represents I encoder done status.\\0: not done\\1: done. - 15 - 1 + OUT_CMDFIFO_OUTFIFO_BCNT_CH3 + only for debug + 0 + 10 read-only + + + + OUT_PUSH_BYTECNT_CH3 + tx CH3 push byte cnt register + 0x378 + 0x20 + 0x0000003F + - I_DB_DONE_DEBUG_FLAG - Represents I deblocking done status.\\0: not done\\1: done. - 16 - 1 + OUT_CMDFIFO_PUSH_BYTECNT_CH3 + only for debug + 0 + 8 read-only + + + + OUT_XADDR_CH3 + tx CH3 xaddr register + 0x37C + 0x20 + - I_BS_BUF_DONE_DEBUG_FLAG - Represents I bitstream buffer done status.\\0: not done\\1: done. - 17 - 1 + OUT_CMDFIFO_XADDR_CH3 + only for debug + 0 + 32 read-only - DATE - Version control register - 0xF0 + OUT_BLOCK_BUF_LEN_CH3 + tx CH3 block buf len register + 0x380 0x20 - 0x02304240 - LEDC_DATE - Configures the version. + OUT_BLOCK_BUF_LEN_CH3 + only for debug 0 28 - read-write + read-only - - - - H264_DMA - H264 Encoder (DMA) - H264_DMA - 0x500A7000 - - 0x0 - 0x3DC - registers - - - H264_DMA2D_OUT_CH0 - 115 - - - H264_DMA2D_OUT_CH1 - 116 - - - H264_DMA2D_OUT_CH2 - 117 - - - H264_DMA2D_OUT_CH3 - 118 - - - H264_DMA2D_OUT_CH4 - 119 - - - H264_DMA2D_IN_CH0 - 120 - - - H264_DMA2D_IN_CH1 - 121 - - - H264_DMA2D_IN_CH2 - 122 - - - H264_DMA2D_IN_CH3 - 123 - - - H264_DMA2D_IN_CH4 - 124 - - - H264_DMA2D_IN_CH5 - 125 - - - OUT_CONF0_CH0 - TX CH0 config0 register - 0x0 + OUT_CONF0_CH4 + TX CH4 config0 register + 0x400 0x20 0x00000002 - OUT_AUTO_WRBACK_CH0 + OUT_AUTO_WRBACK_CH4 Set this bit to enable automatic outlink-writeback when all the data pointed by outlink descriptor has been received. 0 1 read-write - OUT_EOF_MODE_CH0 + OUT_EOF_MODE_CH4 EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is generated when data need to read has been popped from FIFO in DMA 1 1 read-write - OUTDSCR_BURST_EN_CH0 + OUTDSCR_BURST_EN_CH4 Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM. 2 1 read-write - OUT_ECC_AES_EN_CH0 + OUT_ECC_AES_EN_CH4 When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned. 3 1 read-write - OUT_CHECK_OWNER_CH0 + OUT_CHECK_OWNER_CH4 Set this bit to enable checking the owner attribute of the link descriptor. 4 1 read-write - OUT_MEM_BURST_LENGTH_CH0 - Block size of Tx channel 0. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes + OUT_MEM_BURST_LENGTH_CH4 + Block size of Tx channel 4. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes 6 3 read-write - OUT_PAGE_BOUND_EN_CH0 + OUT_PAGE_BOUND_EN_CH4 Set this bit to 1 to make sure AXI read data don't cross the address boundary which define by mem_burst_length 12 1 read-write - OUT_REORDER_EN_CH0 - Enable TX channel 0 macro block reorder when set to 1, only channel0 have this selection - 16 - 1 - read-write - - - OUT_RST_CH0 - Write 1 then write 0 to this bit to reset TX channel - 24 - 1 - read-write - - - OUT_CMD_DISABLE_CH0 - Write 1 before reset and write 0 after reset - 25 - 1 - read-write - - - OUT_ARB_WEIGHT_OPT_DIS_CH0 + OUT_ARB_WEIGHT_OPT_DIS_CH4 Set this bit to 1 to disable arbiter optimum weight function. 26 1 @@ -48245,69 +46352,69 @@ - OUT_INT_RAW_CH0 - TX CH0 interrupt raw register - 0x4 + OUT_INT_RAW_CH4 + TX CH4 interrupt raw register + 0x404 0x20 - OUT_DONE_CH0_INT_RAW + OUT_DONE_CH4_INT_RAW The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0. 0 1 read-write - OUT_EOF_CH0_INT_RAW + OUT_EOF_CH4_INT_RAW The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. 1 1 read-write - OUT_DSCR_ERR_CH0_INT_RAW + OUT_DSCR_ERR_CH4_INT_RAW The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0. 2 1 read-write - OUT_TOTAL_EOF_CH0_INT_RAW + OUT_TOTAL_EOF_CH4_INT_RAW The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0. 3 1 read-write - OUTFIFO_OVF_L1_CH0_INT_RAW + OUTFIFO_OVF_L1_CH4_INT_RAW The raw interrupt bit turns to high level when fifo is overflow. 4 1 read-write - OUTFIFO_UDF_L1_CH0_INT_RAW + OUTFIFO_UDF_L1_CH4_INT_RAW The raw interrupt bit turns to high level when fifo is underflow. 5 1 read-write - OUTFIFO_OVF_L2_CH0_INT_RAW + OUTFIFO_OVF_L2_CH4_INT_RAW The raw interrupt bit turns to high level when fifo is overflow. 6 1 read-write - OUTFIFO_UDF_L2_CH0_INT_RAW + OUTFIFO_UDF_L2_CH4_INT_RAW The raw interrupt bit turns to high level when fifo is underflow. 7 1 read-write - OUT_DSCR_TASK_OVF_CH0_INT_RAW + OUT_DSCR_TASK_OVF_CH4_INT_RAW The raw interrupt bit turns to high level when dscr ready task fifo is overflow. 8 1 @@ -48316,69 +46423,69 @@ - OUT_INT_ENA_CH0 - TX CH0 interrupt ena register - 0x8 + OUT_INT_ENA_CH4 + TX CH4 interrupt ena register + 0x408 0x20 - OUT_DONE_CH0_INT_ENA + OUT_DONE_CH4_INT_ENA The interrupt enable bit for the OUT_DONE_CH_INT interrupt. 0 1 read-write - OUT_EOF_CH0_INT_ENA + OUT_EOF_CH4_INT_ENA The interrupt enable bit for the OUT_EOF_CH_INT interrupt. 1 1 read-write - OUT_DSCR_ERR_CH0_INT_ENA + OUT_DSCR_ERR_CH4_INT_ENA The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. 2 1 read-write - OUT_TOTAL_EOF_CH0_INT_ENA + OUT_TOTAL_EOF_CH4_INT_ENA The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. 3 1 read-write - OUTFIFO_OVF_L1_CH0_INT_ENA + OUTFIFO_OVF_L1_CH4_INT_ENA The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. 4 1 read-write - OUTFIFO_UDF_L1_CH0_INT_ENA + OUTFIFO_UDF_L1_CH4_INT_ENA The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. 5 1 read-write - OUTFIFO_OVF_L2_CH0_INT_ENA + OUTFIFO_OVF_L2_CH4_INT_ENA The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. 6 1 read-write - OUTFIFO_UDF_L2_CH0_INT_ENA + OUTFIFO_UDF_L2_CH4_INT_ENA The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. 7 1 read-write - OUT_DSCR_TASK_OVF_CH0_INT_ENA + OUT_DSCR_TASK_OVF_CH4_INT_ENA The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. 8 1 @@ -48387,69 +46494,69 @@ - OUT_INT_ST_CH0 - TX CH0 interrupt st register - 0xC + OUT_INT_ST_CH4 + TX CH4 interrupt st register + 0x40C 0x20 - OUT_DONE_CH0_INT_ST + OUT_DONE_CH4_INT_ST The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. 0 1 read-only - OUT_EOF_CH0_INT_ST + OUT_EOF_CH4_INT_ST The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. 1 1 read-only - OUT_DSCR_ERR_CH0_INT_ST + OUT_DSCR_ERR_CH4_INT_ST The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. 2 1 read-only - OUT_TOTAL_EOF_CH0_INT_ST + OUT_TOTAL_EOF_CH4_INT_ST The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. 3 1 read-only - OUTFIFO_OVF_L1_CH0_INT_ST + OUTFIFO_OVF_L1_CH4_INT_ST The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. 4 1 read-only - OUTFIFO_UDF_L1_CH0_INT_ST + OUTFIFO_UDF_L1_CH4_INT_ST The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. 5 1 read-only - OUTFIFO_OVF_L2_CH0_INT_ST + OUTFIFO_OVF_L2_CH4_INT_ST The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. 6 1 read-only - OUTFIFO_UDF_L2_CH0_INT_ST + OUTFIFO_UDF_L2_CH4_INT_ST The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. 7 1 read-only - OUT_DSCR_TASK_OVF_CH0_INT_ST + OUT_DSCR_TASK_OVF_CH4_INT_ST The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. 8 1 @@ -48458,69 +46565,69 @@ - OUT_INT_CLR_CH0 - TX CH0 interrupt clr register - 0x10 + OUT_INT_CLR_CH4 + TX CH4 interrupt clr register + 0x410 0x20 - OUT_DONE_CH0_INT_CLR + OUT_DONE_CH4_INT_CLR Set this bit to clear the OUT_DONE_CH_INT interrupt. 0 1 write-only - OUT_EOF_CH0_INT_CLR + OUT_EOF_CH4_INT_CLR Set this bit to clear the OUT_EOF_CH_INT interrupt. 1 1 write-only - OUT_DSCR_ERR_CH0_INT_CLR + OUT_DSCR_ERR_CH4_INT_CLR Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. 2 1 write-only - OUT_TOTAL_EOF_CH0_INT_CLR + OUT_TOTAL_EOF_CH4_INT_CLR Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. 3 1 write-only - OUTFIFO_OVF_L1_CH0_INT_CLR + OUTFIFO_OVF_L1_CH4_INT_CLR Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. 4 1 write-only - OUTFIFO_UDF_L1_CH0_INT_CLR + OUTFIFO_UDF_L1_CH4_INT_CLR Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. 5 1 write-only - OUTFIFO_OVF_L2_CH0_INT_CLR + OUTFIFO_OVF_L2_CH4_INT_CLR Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. 6 1 write-only - OUTFIFO_UDF_L2_CH0_INT_CLR + OUTFIFO_UDF_L2_CH4_INT_CLR Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. 7 1 write-only - OUT_DSCR_TASK_OVF_CH0_INT_CLR + OUT_DSCR_TASK_OVF_CH4_INT_CLR Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt. 8 1 @@ -48529,71 +46636,71 @@ - OUTFIFO_STATUS_CH0 - TX CH0 outfifo status register - 0x14 + OUTFIFO_STATUS_CH4 + TX CH4 outfifo status register + 0x414 0x20 0x00020082 - OUTFIFO_FULL_L2_CH0 - Tx FIFO full signal for Tx channel 0. + OUTFIFO_FULL_L2_CH4 + Tx FIFO full signal for Tx channel 2. 0 1 read-only - OUTFIFO_EMPTY_L2_CH0 - Tx FIFO empty signal for Tx channel 0. + OUTFIFO_EMPTY_L2_CH4 + Tx FIFO empty signal for Tx channel 2. 1 1 read-only - OUTFIFO_CNT_L2_CH0 - The register stores the byte number of the data in Tx FIFO for Tx channel 0. + OUTFIFO_CNT_L2_CH4 + The register stores the byte number of the data in Tx FIFO for Tx channel 2. 2 4 read-only - OUTFIFO_FULL_L1_CH0 - Tx FIFO full signal for Tx channel 0. + OUTFIFO_FULL_L1_CH4 + Tx FIFO full signal for Tx channel 2. 6 1 read-only - OUTFIFO_EMPTY_L1_CH0 - Tx FIFO empty signal for Tx channel 0. + OUTFIFO_EMPTY_L1_CH4 + Tx FIFO empty signal for Tx channel 2. 7 1 read-only - OUTFIFO_CNT_L1_CH0 - The register stores the byte number of the data in Tx FIFO for Tx channel 0. + OUTFIFO_CNT_L1_CH4 + The register stores the byte number of the data in Tx FIFO for Tx channel 2. 8 5 read-only - OUTFIFO_FULL_L3_CH0 - Tx FIFO full signal for Tx channel 0. + OUTFIFO_FULL_L3_CH4 + Tx FIFO full signal for Tx channel 2. 16 1 read-only - OUTFIFO_EMPTY_L3_CH0 - Tx FIFO empty signal for Tx channel 0. + OUTFIFO_EMPTY_L3_CH4 + Tx FIFO empty signal for Tx channel 2. 17 1 read-only - OUTFIFO_CNT_L3_CH0 - The register stores the 8byte number of the data in Tx FIFO for Tx channel 0. + OUTFIFO_CNT_L3_CH4 + The register stores the byte number of the data in Tx FIFO for Tx channel 2. 18 2 read-only @@ -48601,20 +46708,20 @@ - OUT_PUSH_CH0 - TX CH0 outfifo push register - 0x18 + OUT_PUSH_CH4 + TX CH4 outfifo push register + 0x418 0x20 - OUTFIFO_WDATA_CH0 + OUTFIFO_WDATA_CH4 This register stores the data that need to be pushed into DMA Tx FIFO. 0 10 read-write - OUTFIFO_PUSH_CH0 + OUTFIFO_PUSH_CH4 Set this bit to push data into DMA Tx FIFO. 10 1 @@ -48623,35 +46730,35 @@ - OUT_LINK_CONF_CH0 - TX CH0 out_link dscr ctrl register - 0x1C + OUT_LINK_CONF_CH4 + TX CH4 out_link dscr ctrl register + 0x41C 0x20 0x00800000 - OUTLINK_STOP_CH0 + OUTLINK_STOP_CH4 Set this bit to stop dealing with the outlink descriptors. 20 1 read-write - OUTLINK_START_CH0 + OUTLINK_START_CH4 Set this bit to start dealing with the outlink descriptors. 21 1 read-write - OUTLINK_RESTART_CH0 + OUTLINK_RESTART_CH4 Set this bit to restart a new outlink from the last address. 22 1 read-write - OUTLINK_PARK_CH0 + OUTLINK_PARK_CH4 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working. 23 1 @@ -48660,13 +46767,13 @@ - OUT_LINK_ADDR_CH0 - TX CH0 out_link dscr addr register - 0x20 + OUT_LINK_ADDR_CH4 + TX CH4 out_link dscr addr register + 0x420 0x20 - OUTLINK_ADDR_CH0 + OUTLINK_ADDR_CH4 This register stores the first outlink descriptor's address. 0 32 @@ -48675,51 +46782,43 @@ - OUT_STATE_CH0 - TX CH0 state register - 0x24 + OUT_STATE_CH4 + TX CH4 state register + 0x424 0x20 - 0x01000000 - OUTLINK_DSCR_ADDR_CH0 + OUTLINK_DSCR_ADDR_CH4 This register stores the current outlink descriptor's address. 0 18 read-only - OUT_DSCR_STATE_CH0 + OUT_DSCR_STATE_CH4 This register stores the current descriptor state machine state. 18 2 read-only - OUT_STATE_CH0 + OUT_STATE_CH4 This register stores the current control module state machine state. 20 4 read-only - - OUT_RESET_AVAIL_CH0 - This register indicate that if the channel reset is safety. - 24 - 1 - read-only - - OUT_EOF_DES_ADDR_CH0 - TX CH0 eof des addr register - 0x28 + OUT_EOF_DES_ADDR_CH4 + TX CH4 eof des addr register + 0x428 0x20 - OUT_EOF_DES_ADDR_CH0 - This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1. + OUT_EOF_DES_ADDR_CH4 + This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. 0 32 read-only @@ -48727,13 +46826,13 @@ - OUT_DSCR_CH0 - TX CH0 next dscr addr register - 0x2C + OUT_DSCR_CH4 + TX CH4 next dscr addr register + 0x42C 0x20 - OUTLINK_DSCR_CH0 + OUTLINK_DSCR_CH4 The address of the next outlink descriptor address y. 0 32 @@ -48742,13 +46841,13 @@ - OUT_DSCR_BF0_CH0 - TX CH0 last dscr addr register - 0x30 + OUT_DSCR_BF0_CH4 + TX CH4 last dscr addr register + 0x430 0x20 - OUTLINK_DSCR_BF0_CH0 + OUTLINK_DSCR_BF0_CH4 The address of the last outlink descriptor's next address y-1. 0 32 @@ -48757,13 +46856,13 @@ - OUT_DSCR_BF1_CH0 - TX CH0 second-to-last dscr addr register - 0x34 + OUT_DSCR_BF1_CH4 + TX CH4 second-to-last dscr addr register + 0x434 0x20 - OUTLINK_DSCR_BF1_CH0 + OUTLINK_DSCR_BF1_CH4 The address of the second-to-last outlink descriptor's next address y-2. 0 32 @@ -48772,21 +46871,21 @@ - OUT_ARB_CH0 - TX CH0 arb register - 0x3C + OUT_ARB_CH4 + TX CH4 arb register + 0x43C 0x20 0x00000011 - OUT_ARB_TOKEN_NUM_CH0 + OUT_ARB_TOKEN_NUM_CH4 Set the max number of token count of arbiter 0 4 read-write - EXTER_OUT_ARB_PRIORITY_CH0 + EXTER_OUT_ARB_PRIORITY_CH4 Set the priority of channel 4 2 @@ -48795,146 +46894,28 @@ - OUT_RO_STATUS_CH0 - TX CH0 reorder status register - 0x40 - 0x20 - 0x00000800 - - - OUTFIFO_RO_CNT_CH0 - The register stores the 8byte number of the data in reorder Tx FIFO for channel 0. - 0 - 2 - read-only - - - OUT_RO_WR_STATE_CH0 - The register stores the state of read ram of reorder - 6 - 2 - read-only - - - OUT_RO_RD_STATE_CH0 - The register stores the state of write ram of reorder - 8 - 2 - read-only - - - OUT_PIXEL_BYTE_CH0 - the number of bytes contained in a pixel at TX channel 0: 1byte 1: 1.5bytes 2 : 2bytes 3: 2.5bytes 4: 3bytes 5: 4bytes - 10 - 4 - read-only - - - OUT_BURST_BLOCK_NUM_CH0 - the number of macro blocks contained in a burst of data at TX channel - 14 - 4 - read-only - - - - - OUT_RO_PD_CONF_CH0 - TX CH0 reorder power config register - 0x44 - 0x20 - 0x00000020 - - - OUT_RO_RAM_FORCE_PD_CH0 - dma reorder ram power down - 4 - 1 - read-write - - - OUT_RO_RAM_FORCE_PU_CH0 - dma reorder ram power up - 5 - 1 - read-write - - - OUT_RO_RAM_CLK_FO_CH0 - 1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA. 0: A gate-clock will be used when accessing the RAM in DMA. - 6 - 1 - read-write - - - - - OUT_MODE_ENABLE_CH0 - tx CH0 mode enable register - 0x50 - 0x20 - - - OUT_TEST_MODE_ENABLE_CH0 - tx CH0 test mode enable.0 : H264_DMA work in normal mode.1 : H264_DMA work in test mode - 0 - 1 - read-write - - - - - OUT_MODE_YUV_CH0 - tx CH0 test mode yuv value register - 0x54 - 0x20 - - - OUT_TEST_Y_VALUE_CH0 - tx CH0 test mode y value - 0 - 8 - read-write - - - OUT_TEST_U_VALUE_CH0 - tx CH0 test mode u value - 8 - 8 - read-write - - - OUT_TEST_V_VALUE_CH0 - tx CH0 test mode v value - 16 - 8 - read-write - - - - - OUT_ETM_CONF_CH0 - TX CH0 ETM config register - 0x68 + OUT_ETM_CONF_CH4 + TX CH4 ETM config register + 0x468 0x20 0x00000004 - OUT_ETM_EN_CH0 + OUT_ETM_EN_CH4 Set this bit to 1 to enable ETM task function 0 1 read-write - OUT_ETM_LOOP_EN_CH0 + OUT_ETM_LOOP_EN_CH4 when this bit is 1, dscr can be processed after receiving a task 1 1 read-write - OUT_DSCR_TASK_MAK_CH0 + OUT_DSCR_TASK_MAK_CH4 ETM dscr_ready maximum cache numbers 2 2 @@ -48943,13 +46924,13 @@ - OUT_BUF_LEN_CH0 - tx CH0 buf len register - 0x70 + OUT_BUF_LEN_CH4 + tx CH4 buf len register + 0x470 0x20 - OUT_CMDFIFO_BUF_LEN_HB_CH0 + OUT_CMDFIFO_BUF_LEN_HB_CH4 only for debug 0 13 @@ -48958,13 +46939,13 @@ - OUT_FIFO_BCNT_CH0 - tx CH0 fifo byte cnt register - 0x74 + OUT_FIFO_BCNT_CH4 + tx CH4 fifo byte cnt register + 0x474 0x20 - OUT_CMDFIFO_OUTFIFO_BCNT_CH0 + OUT_CMDFIFO_OUTFIFO_BCNT_CH4 only for debug 0 10 @@ -48973,14 +46954,14 @@ - OUT_PUSH_BYTECNT_CH0 - tx CH0 push byte cnt register - 0x78 + OUT_PUSH_BYTECNT_CH4 + tx CH4 push byte cnt register + 0x478 0x20 - 0x000000FF + 0x0000003F - OUT_CMDFIFO_PUSH_BYTECNT_CH0 + OUT_CMDFIFO_PUSH_BYTECNT_CH4 only for debug 0 8 @@ -48989,13 +46970,13 @@ - OUT_XADDR_CH0 - tx CH0 xaddr register - 0x7C + OUT_XADDR_CH4 + tx CH4 xaddr register + 0x47C 0x20 - OUT_CMDFIFO_XADDR_CH0 + OUT_CMDFIFO_XADDR_CH4 only for debug 0 32 @@ -49004,77 +46985,77 @@ - OUT_CONF0_CH1 - TX CH1 config0 register - 0x100 + OUT_BLOCK_BUF_LEN_CH4 + tx CH4 block buf len register + 0x480 0x20 - 0x00000002 - OUT_AUTO_WRBACK_CH1 - Set this bit to enable automatic outlink-writeback when all the data pointed by outlink descriptor has been received. + OUT_BLOCK_BUF_LEN_CH4 + only for debug 0 - 1 - read-write - - - OUT_EOF_MODE_CH1 - EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is generated when data need to read has been popped from FIFO in DMA - 1 - 1 - read-write + 28 + read-only + + + + IN_CONF0_CH0 + RX CH0 config0 register + 0x500 + 0x20 + - OUTDSCR_BURST_EN_CH1 - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM. + INDSCR_BURST_EN_CH0 + Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor when accessing SRAM. 2 1 read-write - OUT_ECC_AES_EN_CH1 + IN_ECC_AES_EN_CH0 When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned. 3 1 read-write - OUT_CHECK_OWNER_CH1 + IN_CHECK_OWNER_CH0 Set this bit to enable checking the owner attribute of the link descriptor. 4 1 read-write - OUT_MEM_BURST_LENGTH_CH1 - Block size of Tx channel 1. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 64 bytes + IN_MEM_BURST_LENGTH_CH0 + Block size of Rx channel 0. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes 6 3 read-write - OUT_PAGE_BOUND_EN_CH1 - Set this bit to 1 to make sure AXI read data don't cross the address boundary which define by mem_burst_length + IN_PAGE_BOUND_EN_CH0 + Set this bit to 1 to make sure AXI write data don't cross the address boundary which define by mem_burst_length 12 1 read-write - OUT_RST_CH1 - Write 1 then write 0 to this bit to reset TX channel + IN_RST_CH0 + Write 1 then write 0 to this bit to reset Rx channel 24 1 read-write - OUT_CMD_DISABLE_CH1 + IN_CMD_DISABLE_CH0 Write 1 before reset and write 0 after reset 25 1 read-write - OUT_ARB_WEIGHT_OPT_DIS_CH1 + IN_ARB_WEIGHT_OPT_DIS_CH0 Set this bit to 1 to disable arbiter optimum weight function. 26 1 @@ -49083,355 +47064,383 @@ - OUT_INT_RAW_CH1 - TX CH1 interrupt raw register - 0x104 + IN_INT_RAW_CH0 + RX CH0 interrupt raw register + 0x504 0x20 - OUT_DONE_CH1_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0. + IN_DONE_CH0_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been transmitted to peripherals for Rx channel 0. 0 1 read-write - OUT_EOF_CH1_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. + IN_SUC_EOF_CH0_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0. 1 1 read-write - OUT_DSCR_ERR_CH1_INT_RAW - The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0. + IN_ERR_EOF_CH0_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and data error is detected 2 1 read-write - OUT_TOTAL_EOF_CH1_INT_RAW - The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0. + IN_DSCR_ERR_CH0_INT_RAW + The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0. 3 1 read-write - OUTFIFO_OVF_L1_CH1_INT_RAW - The raw interrupt bit turns to high level when fifo is overflow. + INFIFO_OVF_L1_CH0_INT_RAW + The raw interrupt bit turns to high level when fifo of Rx channel is overflow. 4 1 read-write - OUTFIFO_UDF_L1_CH1_INT_RAW - The raw interrupt bit turns to high level when fifo is underflow. + INFIFO_UDF_L1_CH0_INT_RAW + The raw interrupt bit turns to high level when fifo of Rx channel is underflow. 5 1 read-write - OUTFIFO_OVF_L2_CH1_INT_RAW - The raw interrupt bit turns to high level when fifo is overflow. + INFIFO_OVF_L2_CH0_INT_RAW + The raw interrupt bit turns to high level when fifo of Rx channel is overflow. 6 1 read-write - OUTFIFO_UDF_L2_CH1_INT_RAW - The raw interrupt bit turns to high level when fifo is underflow. + INFIFO_UDF_L2_CH0_INT_RAW + The raw interrupt bit turns to high level when fifo of Rx channel is underflow. 7 1 read-write - OUT_DSCR_TASK_OVF_CH1_INT_RAW - The raw interrupt bit turns to high level when dscr ready task fifo is overflow. + IN_DSCR_EMPTY_CH0_INT_RAW + The raw interrupt bit turns to high level when the last descriptor is done but fifo also remain data. 8 1 read-write + + IN_DSCR_TASK_OVF_CH0_INT_RAW + The raw interrupt bit turns to high level when dscr ready task fifo is overflow. + 9 + 1 + read-write + - OUT_INT_ENA_CH1 - TX CH1 interrupt ena register - 0x108 + IN_INT_ENA_CH0 + RX CH0 interrupt ena register + 0x508 0x20 - OUT_DONE_CH1_INT_ENA - The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + IN_DONE_CH0_INT_ENA + The interrupt enable bit for the IN_DONE_CH_INT interrupt. 0 1 read-write - OUT_EOF_CH1_INT_ENA - The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + IN_SUC_EOF_CH0_INT_ENA + The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. 1 1 read-write - OUT_DSCR_ERR_CH1_INT_ENA - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + IN_ERR_EOF_CH0_INT_ENA + The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. 2 1 read-write - OUT_TOTAL_EOF_CH1_INT_ENA - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + IN_DSCR_ERR_CH0_INT_ENA + The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. 3 1 read-write - OUTFIFO_OVF_L1_CH1_INT_ENA - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + INFIFO_OVF_L1_CH0_INT_ENA + The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. 4 1 read-write - OUTFIFO_UDF_L1_CH1_INT_ENA - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + INFIFO_UDF_L1_CH0_INT_ENA + The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. 5 1 read-write - OUTFIFO_OVF_L2_CH1_INT_ENA - The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. + INFIFO_OVF_L2_CH0_INT_ENA + The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. 6 1 read-write - OUTFIFO_UDF_L2_CH1_INT_ENA - The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. + INFIFO_UDF_L2_CH0_INT_ENA + The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. 7 1 read-write - OUT_DSCR_TASK_OVF_CH1_INT_ENA - The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. + IN_DSCR_EMPTY_CH0_INT_ENA + The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. 8 1 read-write + + IN_DSCR_TASK_OVF_CH0_INT_ENA + The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. + 9 + 1 + read-write + - OUT_INT_ST_CH1 - TX CH1 interrupt st register - 0x10C + IN_INT_ST_CH0 + RX CH0 interrupt st register + 0x50C 0x20 - OUT_DONE_CH1_INT_ST - The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + IN_DONE_CH0_INT_ST + The raw interrupt status bit for the IN_DONE_CH_INT interrupt. 0 1 read-only - OUT_EOF_CH1_INT_ST - The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + IN_SUC_EOF_CH0_INT_ST + The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. 1 1 read-only - OUT_DSCR_ERR_CH1_INT_ST - The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + IN_ERR_EOF_CH0_INT_ST + The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. 2 1 read-only - OUT_TOTAL_EOF_CH1_INT_ST - The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + IN_DSCR_ERR_CH0_INT_ST + The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. 3 1 read-only - OUTFIFO_OVF_L1_CH1_INT_ST - The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + INFIFO_OVF_L1_CH0_INT_ST + The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. 4 1 read-only - OUTFIFO_UDF_L1_CH1_INT_ST - The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + INFIFO_UDF_L1_CH0_INT_ST + The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. 5 1 read-only - OUTFIFO_OVF_L2_CH1_INT_ST - The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. + INFIFO_OVF_L2_CH0_INT_ST + The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. 6 1 read-only - OUTFIFO_UDF_L2_CH1_INT_ST - The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. + INFIFO_UDF_L2_CH0_INT_ST + The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. 7 1 read-only - OUT_DSCR_TASK_OVF_CH1_INT_ST - The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. + IN_DSCR_EMPTY_CH0_INT_ST + The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. 8 1 read-only + + IN_DSCR_TASK_OVF_CH0_INT_ST + The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. + 9 + 1 + read-only + - OUT_INT_CLR_CH1 - TX CH1 interrupt clr register - 0x110 + IN_INT_CLR_CH0 + RX CH0 interrupt clr register + 0x510 0x20 - OUT_DONE_CH1_INT_CLR - Set this bit to clear the OUT_DONE_CH_INT interrupt. + IN_DONE_CH0_INT_CLR + Set this bit to clear the IN_DONE_CH_INT interrupt. 0 1 write-only - OUT_EOF_CH1_INT_CLR - Set this bit to clear the OUT_EOF_CH_INT interrupt. + IN_SUC_EOF_CH0_INT_CLR + Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. 1 1 write-only - OUT_DSCR_ERR_CH1_INT_CLR - Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + IN_ERR_EOF_CH0_INT_CLR + Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. 2 1 write-only - OUT_TOTAL_EOF_CH1_INT_CLR - Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + IN_DSCR_ERR_CH0_INT_CLR + Set this bit to clear the INDSCR_ERR_CH_INT interrupt. 3 1 write-only - OUTFIFO_OVF_L1_CH1_INT_CLR - Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + INFIFO_OVF_L1_CH0_INT_CLR + Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. 4 1 write-only - OUTFIFO_UDF_L1_CH1_INT_CLR - Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + INFIFO_UDF_L1_CH0_INT_CLR + Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. 5 1 write-only - OUTFIFO_OVF_L2_CH1_INT_CLR - Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. + INFIFO_OVF_L2_CH0_INT_CLR + Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. 6 1 write-only - OUTFIFO_UDF_L2_CH1_INT_CLR - Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. + INFIFO_UDF_L2_CH0_INT_CLR + Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. 7 1 write-only - OUT_DSCR_TASK_OVF_CH1_INT_CLR - Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt. + IN_DSCR_EMPTY_CH0_INT_CLR + Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. 8 1 write-only + + IN_DSCR_TASK_OVF_CH0_INT_CLR + Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt. + 9 + 1 + write-only + - OUTFIFO_STATUS_CH1 - TX CH1 outfifo status register - 0x114 - 0x20 + INFIFO_STATUS_CH0 + RX CH0 INFIFO status register + 0x514 + 0x20 0x00020082 - OUTFIFO_FULL_L2_CH1 - Tx FIFO full signal for Tx channel 1. + INFIFO_FULL_L2_CH0 + Rx FIFO full signal for Rx channel. 0 1 read-only - OUTFIFO_EMPTY_L2_CH1 - Tx FIFO empty signal for Tx channel 1. + INFIFO_EMPTY_L2_CH0 + Rx FIFO empty signal for Rx channel. 1 1 read-only - OUTFIFO_CNT_L2_CH1 - The register stores the byte number of the data in Tx FIFO for Tx channel 1. + INFIFO_CNT_L2_CH0 + The register stores the byte number of the data in Rx FIFO for Rx channel. 2 4 read-only - OUTFIFO_FULL_L1_CH1 - Tx FIFO full signal for Tx channel 1. + INFIFO_FULL_L1_CH0 + Tx FIFO full signal for Tx channel 0. 6 1 read-only - OUTFIFO_EMPTY_L1_CH1 - Tx FIFO empty signal for Tx channel 1. + INFIFO_EMPTY_L1_CH0 + Tx FIFO empty signal for Tx channel 0. 7 1 read-only - OUTFIFO_CNT_L1_CH1 - The register stores the byte number of the data in Tx FIFO for Tx channel 1. + INFIFO_CNT_L1_CH0 + The register stores the byte number of the data in Tx FIFO for Tx channel 0. 8 5 read-only - OUTFIFO_FULL_L3_CH1 - Tx FIFO full signal for Tx channel 1. + INFIFO_FULL_L3_CH0 + Tx FIFO full signal for Tx channel 0. 16 1 read-only - OUTFIFO_EMPTY_L3_CH1 - Tx FIFO empty signal for Tx channel 1. + INFIFO_EMPTY_L3_CH0 + Tx FIFO empty signal for Tx channel 0. 17 1 read-only - OUTFIFO_CNT_L3_CH1 - The register stores the byte number of the data in Tx FIFO for Tx channel 1. + INFIFO_CNT_L3_CH0 + The register stores the 8byte number of the data in Tx FIFO for Tx channel 0. 18 2 read-only @@ -49439,73 +47448,81 @@ - OUT_PUSH_CH1 - TX CH1 outfifo push register - 0x118 + IN_POP_CH0 + RX CH0 INFIFO pop register + 0x518 0x20 + 0x00000400 - OUTFIFO_WDATA_CH1 - This register stores the data that need to be pushed into DMA Tx FIFO. + INFIFO_RDATA_CH0 + This register stores the data popping from DMA Rx FIFO. 0 - 10 - read-write + 11 + read-only - OUTFIFO_PUSH_CH1 - Set this bit to push data into DMA Tx FIFO. - 10 + INFIFO_POP_CH0 + Set this bit to pop data from DMA Rx FIFO. + 11 1 read-write - OUT_LINK_CONF_CH1 - TX CH1 out_link dscr ctrl register - 0x11C + IN_LINK_CONF_CH0 + RX CH0 in_link dscr ctrl register + 0x51C 0x20 - 0x00800000 + 0x01100000 - OUTLINK_STOP_CH1 - Set this bit to stop dealing with the outlink descriptors. + INLINK_AUTO_RET_CH0 + Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data. 20 1 read-write - OUTLINK_START_CH1 - Set this bit to start dealing with the outlink descriptors. + INLINK_STOP_CH0 + Set this bit to stop dealing with the inlink descriptors. 21 1 read-write - OUTLINK_RESTART_CH1 - Set this bit to restart a new outlink from the last address. + INLINK_START_CH0 + Set this bit to start dealing with the inlink descriptors. 22 1 read-write - OUTLINK_PARK_CH1 - 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working. + INLINK_RESTART_CH0 + Set this bit to mount a new inlink descriptor. 23 1 + read-write + + + INLINK_PARK_CH0 + 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working. + 24 + 1 read-only - OUT_LINK_ADDR_CH1 - TX CH1 out_link dscr addr register - 0x120 + IN_LINK_ADDR_CH0 + RX CH0 in_link dscr addr register + 0x520 0x20 - OUTLINK_ADDR_CH1 - This register stores the first outlink descriptor's address. + INLINK_ADDR_CH0 + This register stores the first inlink descriptor's address. 0 32 read-write @@ -49513,51 +47530,51 @@ - OUT_STATE_CH1 - TX CH1 state register - 0x124 + IN_STATE_CH0 + RX CH0 state register + 0x524 0x20 - 0x01000000 + 0x00800000 - OUTLINK_DSCR_ADDR_CH1 - This register stores the current outlink descriptor's address. + INLINK_DSCR_ADDR_CH0 + This register stores the current inlink descriptor's address. 0 18 read-only - OUT_DSCR_STATE_CH1 + IN_DSCR_STATE_CH0 This register stores the current descriptor state machine state. 18 2 read-only - OUT_STATE_CH1 + IN_STATE_CH0 This register stores the current control module state machine state. 20 - 4 + 3 read-only - OUT_RESET_AVAIL_CH1 + IN_RESET_AVAIL_CH0 This register indicate that if the channel reset is safety. - 24 + 23 1 read-only - OUT_EOF_DES_ADDR_CH1 - TX CH1 eof des addr register - 0x128 + IN_SUC_EOF_DES_ADDR_CH0 + RX CH0 eof des addr register + 0x528 0x20 - OUT_EOF_DES_ADDR_CH1 - This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1. + IN_SUC_EOF_DES_ADDR_CH0 + This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. 0 32 read-only @@ -49565,14 +47582,14 @@ - OUT_DSCR_CH1 - TX CH1 next dscr addr register - 0x12C + IN_ERR_EOF_DES_ADDR_CH0 + RX CH0 err eof des addr register + 0x52C 0x20 - OUTLINK_DSCR_CH1 - The address of the next outlink descriptor address y. + IN_ERR_EOF_DES_ADDR_CH0 + This register stores the address of the inlink descriptor when there are some errors in current receiving data. 0 32 read-only @@ -49580,14 +47597,14 @@ - OUT_DSCR_BF0_CH1 - TX CH1 last dscr addr register - 0x130 + IN_DSCR_CH0 + RX CH0 next dscr addr register + 0x530 0x20 - OUTLINK_DSCR_BF0_CH1 - The address of the last outlink descriptor's next address y-1. + INLINK_DSCR_CH0 + The address of the next inlink descriptor address x. 0 32 read-only @@ -49595,14 +47612,14 @@ - OUT_DSCR_BF1_CH1 - TX CH1 second-to-last dscr addr register - 0x134 + IN_DSCR_BF0_CH0 + RX CH0 last dscr addr register + 0x534 0x20 - OUTLINK_DSCR_BF1_CH1 - The address of the second-to-last outlink descriptor's next address y-2. + INLINK_DSCR_BF0_CH0 + The address of the last inlink descriptor's next address x-1. 0 32 read-only @@ -49610,51 +47627,88 @@ - OUT_ARB_CH1 - TX CH1 arb register - 0x13C + IN_DSCR_BF1_CH0 + RX CH0 second-to-last dscr addr register + 0x538 0x20 - 0x00000041 - OUT_ARB_TOKEN_NUM_CH1 + INLINK_DSCR_BF1_CH0 + The address of the second-to-last inlink descriptor's next address x-2. + 0 + 32 + read-only + + + + + IN_ARB_CH0 + RX CH0 arb register + 0x540 + 0x20 + 0x00000051 + + + IN_ARB_TOKEN_NUM_CH0 Set the max number of token count of arbiter 0 4 read-write - INTER_OUT_ARB_PRIORITY_CH1 + EXTER_IN_ARB_PRIORITY_CH0 + Set the priority of channel + 4 + 2 + read-write + + + INTER_IN_ARB_PRIORITY_CH0 Set the priority of channel 6 + 3 + read-write + + + + + IN_RO_PD_CONF_CH0 + RX CH0 reorder power config register + 0x548 + 0x20 + + + IN_RO_RAM_CLK_FO_CH0 + 1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA. 0: A gate-clock will be used when accessing the RAM in DMA. + 6 1 read-write - OUT_ETM_CONF_CH1 - TX CH1 ETM config register - 0x168 + IN_ETM_CONF_CH0 + RX CH0 ETM config register + 0x56C 0x20 0x00000004 - OUT_ETM_EN_CH1 + IN_ETM_EN_CH0 Set this bit to 1 to enable ETM task function 0 1 read-write - OUT_ETM_LOOP_EN_CH1 + IN_ETM_LOOP_EN_CH0 when this bit is 1, dscr can be processed after receiving a task 1 1 read-write - OUT_DSCR_TASK_MAK_CH1 + IN_DSCR_TASK_MAK_CH0 ETM dscr_ready maximum cache numbers 2 2 @@ -49663,138 +47717,123 @@ - OUT_BUF_LEN_CH1 - tx CH1 buf len register - 0x170 + IN_FIFO_CNT_CH0 + rx CH0 fifo cnt register + 0x580 0x20 - OUT_CMDFIFO_BUF_LEN_HB_CH1 + IN_CMDFIFO_INFIFO_CNT_CH0 only for debug 0 - 13 + 10 read-only - OUT_FIFO_BCNT_CH1 - tx CH1 fifo byte cnt register - 0x174 + IN_POP_DATA_CNT_CH0 + rx CH0 pop data cnt register + 0x584 0x20 + 0x00000007 - OUT_CMDFIFO_OUTFIFO_BCNT_CH1 + IN_CMDFIFO_POP_DATA_CNT_CH0 only for debug 0 - 10 + 8 read-only - OUT_PUSH_BYTECNT_CH1 - tx CH1 push byte cnt register - 0x178 + IN_XADDR_CH0 + rx CH0 xaddr register + 0x588 0x20 - 0x000000FF - OUT_CMDFIFO_PUSH_BYTECNT_CH1 + IN_CMDFIFO_XADDR_CH0 only for debug 0 - 8 + 32 read-only - OUT_XADDR_CH1 - tx CH1 xaddr register - 0x17C + IN_BUF_HB_RCV_CH0 + rx CH0 buf len hb rcv register + 0x58C 0x20 - OUT_CMDFIFO_XADDR_CH1 + IN_CMDFIFO_BUF_HB_RCV_CH0 only for debug 0 - 32 + 29 read-only - OUT_CONF0_CH2 - TX CH2 config0 register - 0x200 + IN_CONF0_CH1 + RX CH1 config0 register + 0x600 0x20 - 0x00000002 - OUT_AUTO_WRBACK_CH2 - Set this bit to enable automatic outlink-writeback when all the data pointed by outlink descriptor has been received. - 0 - 1 - read-write - - - OUT_EOF_MODE_CH2 - EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is generated when data need to read has been popped from FIFO in DMA - 1 - 1 - read-write - - - OUTDSCR_BURST_EN_CH2 - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM. + INDSCR_BURST_EN_CH1 + Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor when accessing SRAM. 2 1 read-write - OUT_ECC_AES_EN_CH2 + IN_ECC_AES_EN_CH1 When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned. 3 1 read-write - OUT_CHECK_OWNER_CH2 + IN_CHECK_OWNER_CH1 Set this bit to enable checking the owner attribute of the link descriptor. 4 1 read-write - OUT_MEM_BURST_LENGTH_CH2 - Block size of Tx channel 2. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes + IN_MEM_BURST_LENGTH_CH1 + Block size of Rx channel 1. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes 6 3 read-write - OUT_PAGE_BOUND_EN_CH2 - Set this bit to 1 to make sure AXI read data don't cross the address boundary which define by mem_burst_length + IN_PAGE_BOUND_EN_CH1 + Set this bit to 1 to make sure AXI write data don't cross the address boundary which define by mem_burst_length 12 1 read-write - OUT_RST_CH2 - Write 1 then write 0 to this bit to reset TX channel + IN_RST_CH1 + Write 1 then write 0 to this bit to reset Rx channel 24 1 read-write - OUT_CMD_DISABLE_CH2 + IN_CMD_DISABLE_CH1 Write 1 before reset and write 0 after reset 25 1 read-write - OUT_ARB_WEIGHT_OPT_DIS_CH2 + IN_ARB_WEIGHT_OPT_DIS_CH1 Set this bit to 1 to disable arbiter optimum weight function. 26 1 @@ -49803,355 +47842,383 @@ - OUT_INT_RAW_CH2 - TX CH2 interrupt raw register - 0x204 + IN_INT_RAW_CH1 + RX CH1 interrupt raw register + 0x604 0x20 - OUT_DONE_CH2_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0. + IN_DONE_CH1_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been transmitted to peripherals for Rx channel 1. 0 1 read-write - OUT_EOF_CH2_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. + IN_SUC_EOF_CH1_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1. 1 1 read-write - OUT_DSCR_ERR_CH2_INT_RAW - The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0. + IN_ERR_EOF_CH1_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and data error is detected 2 1 read-write - OUT_TOTAL_EOF_CH2_INT_RAW - The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0. + IN_DSCR_ERR_CH1_INT_RAW + The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 1. 3 1 read-write - OUTFIFO_OVF_L1_CH2_INT_RAW - The raw interrupt bit turns to high level when fifo is overflow. + INFIFO_OVF_L1_CH1_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is overflow. 4 1 read-write - OUTFIFO_UDF_L1_CH2_INT_RAW - The raw interrupt bit turns to high level when fifo is underflow. + INFIFO_UDF_L1_CH1_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is underflow. 5 1 read-write - OUTFIFO_OVF_L2_CH2_INT_RAW - The raw interrupt bit turns to high level when fifo is overflow. + INFIFO_OVF_L2_CH1_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is overflow. 6 1 read-write - OUTFIFO_UDF_L2_CH2_INT_RAW - The raw interrupt bit turns to high level when fifo is underflow. + INFIFO_UDF_L2_CH1_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is underflow. 7 1 read-write - OUT_DSCR_TASK_OVF_CH2_INT_RAW - The raw interrupt bit turns to high level when dscr ready task fifo is overflow. + IN_DSCR_EMPTY_CH1_INT_RAW + The raw interrupt bit turns to high level when the last descriptor is done but fifo also remain data. 8 1 read-write + + IN_DSCR_TASK_OVF_CH1_INT_RAW + The raw interrupt bit turns to high level when dscr ready task fifo is overflow. + 9 + 1 + read-write + - OUT_INT_ENA_CH2 - TX CH2 interrupt ena register - 0x208 + IN_INT_ENA_CH1 + RX CH1 interrupt ena register + 0x608 0x20 - OUT_DONE_CH2_INT_ENA - The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + IN_DONE_CH1_INT_ENA + The interrupt enable bit for the IN_DONE_CH_INT interrupt. 0 1 read-write - OUT_EOF_CH2_INT_ENA - The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + IN_SUC_EOF_CH1_INT_ENA + The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. 1 1 read-write - OUT_DSCR_ERR_CH2_INT_ENA - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + IN_ERR_EOF_CH1_INT_ENA + The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. 2 1 read-write - OUT_TOTAL_EOF_CH2_INT_ENA - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + IN_DSCR_ERR_CH1_INT_ENA + The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. 3 1 read-write - OUTFIFO_OVF_L1_CH2_INT_ENA - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + INFIFO_OVF_L1_CH1_INT_ENA + The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. 4 1 read-write - OUTFIFO_UDF_L1_CH2_INT_ENA - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + INFIFO_UDF_L1_CH1_INT_ENA + The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. 5 1 read-write - OUTFIFO_OVF_L2_CH2_INT_ENA - The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. + INFIFO_OVF_L2_CH1_INT_ENA + The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. 6 1 read-write - OUTFIFO_UDF_L2_CH2_INT_ENA - The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. + INFIFO_UDF_L2_CH1_INT_ENA + The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. 7 1 read-write - OUT_DSCR_TASK_OVF_CH2_INT_ENA - The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. + IN_DSCR_EMPTY_CH1_INT_ENA + The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. 8 1 read-write + + IN_DSCR_TASK_OVF_CH1_INT_ENA + The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. + 9 + 1 + read-write + - OUT_INT_ST_CH2 - TX CH2 interrupt st register - 0x20C + IN_INT_ST_CH1 + RX CH1 interrupt st register + 0x60C 0x20 - OUT_DONE_CH2_INT_ST - The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + IN_DONE_CH1_INT_ST + The raw interrupt status bit for the IN_DONE_CH_INT interrupt. 0 1 read-only - OUT_EOF_CH2_INT_ST - The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + IN_SUC_EOF_CH1_INT_ST + The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. 1 1 read-only - OUT_DSCR_ERR_CH2_INT_ST - The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + IN_ERR_EOF_CH1_INT_ST + The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. 2 1 read-only - OUT_TOTAL_EOF_CH2_INT_ST - The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + IN_DSCR_ERR_CH1_INT_ST + The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. 3 1 read-only - OUTFIFO_OVF_L1_CH2_INT_ST - The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + INFIFO_OVF_L1_CH1_INT_ST + The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. 4 1 read-only - OUTFIFO_UDF_L1_CH2_INT_ST - The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + INFIFO_UDF_L1_CH1_INT_ST + The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. 5 1 read-only - OUTFIFO_OVF_L2_CH2_INT_ST - The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. + INFIFO_OVF_L2_CH1_INT_ST + The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. 6 1 read-only - OUTFIFO_UDF_L2_CH2_INT_ST - The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. + INFIFO_UDF_L2_CH1_INT_ST + The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. 7 1 read-only - OUT_DSCR_TASK_OVF_CH2_INT_ST - The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. + IN_DSCR_EMPTY_CH1_INT_ST + The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. 8 1 read-only + + IN_DSCR_TASK_OVF_CH1_INT_ST + The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. + 9 + 1 + read-only + - OUT_INT_CLR_CH2 - TX CH2 interrupt clr register - 0x210 + IN_INT_CLR_CH1 + RX CH1 interrupt clr register + 0x610 0x20 - OUT_DONE_CH2_INT_CLR - Set this bit to clear the OUT_DONE_CH_INT interrupt. + IN_DONE_CH1_INT_CLR + Set this bit to clear the IN_DONE_CH_INT interrupt. 0 1 write-only - OUT_EOF_CH2_INT_CLR - Set this bit to clear the OUT_EOF_CH_INT interrupt. + IN_SUC_EOF_CH1_INT_CLR + Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. 1 1 write-only - OUT_DSCR_ERR_CH2_INT_CLR - Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + IN_ERR_EOF_CH1_INT_CLR + Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. 2 1 write-only - OUT_TOTAL_EOF_CH2_INT_CLR - Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + IN_DSCR_ERR_CH1_INT_CLR + Set this bit to clear the INDSCR_ERR_CH_INT interrupt. 3 1 write-only - OUTFIFO_OVF_L1_CH2_INT_CLR - Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + INFIFO_OVF_L1_CH1_INT_CLR + Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. 4 1 write-only - OUTFIFO_UDF_L1_CH2_INT_CLR - Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + INFIFO_UDF_L1_CH1_INT_CLR + Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. 5 1 write-only - OUTFIFO_OVF_L2_CH2_INT_CLR - Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. + INFIFO_OVF_L2_CH1_INT_CLR + Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. 6 1 write-only - OUTFIFO_UDF_L2_CH2_INT_CLR - Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. + INFIFO_UDF_L2_CH1_INT_CLR + Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. 7 1 write-only - OUT_DSCR_TASK_OVF_CH2_INT_CLR - Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt. + IN_DSCR_EMPTY_CH1_INT_CLR + Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. 8 1 write-only + + IN_DSCR_TASK_OVF_CH1_INT_CLR + Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt. + 9 + 1 + write-only + - OUTFIFO_STATUS_CH2 - TX CH2 outfifo status register - 0x214 + INFIFO_STATUS_CH1 + RX CH1 INFIFO status register + 0x614 0x20 0x00020082 - OUTFIFO_FULL_L2_CH2 - Tx FIFO full signal for Tx channel 2. + INFIFO_FULL_L2_CH1 + Rx FIFO full signal for Rx channel. 0 1 read-only - OUTFIFO_EMPTY_L2_CH2 - Tx FIFO empty signal for Tx channel 2. + INFIFO_EMPTY_L2_CH1 + Rx FIFO empty signal for Rx channel. 1 1 read-only - OUTFIFO_CNT_L2_CH2 - The register stores the byte number of the data in Tx FIFO for Tx channel 2. + INFIFO_CNT_L2_CH1 + The register stores the byte number of the data in Rx FIFO for Rx channel. 2 4 read-only - OUTFIFO_FULL_L1_CH2 - Tx FIFO full signal for Tx channel 2. + INFIFO_FULL_L1_CH1 + Tx FIFO full signal for Tx channel 1. 6 1 read-only - OUTFIFO_EMPTY_L1_CH2 - Tx FIFO empty signal for Tx channel 2. + INFIFO_EMPTY_L1_CH1 + Tx FIFO empty signal for Tx channel 1. 7 1 read-only - OUTFIFO_CNT_L1_CH2 - The register stores the byte number of the data in Tx FIFO for Tx channel 2. + INFIFO_CNT_L1_CH1 + The register stores the byte number of the data in Tx FIFO for Tx channel 1. 8 5 read-only - OUTFIFO_FULL_L3_CH2 - Tx FIFO full signal for Tx channel 2. + INFIFO_FULL_L3_CH1 + Tx FIFO full signal for Tx channel 1. 16 1 read-only - OUTFIFO_EMPTY_L3_CH2 - Tx FIFO empty signal for Tx channel 2. + INFIFO_EMPTY_L3_CH1 + Tx FIFO empty signal for Tx channel 1. 17 1 read-only - OUTFIFO_CNT_L3_CH2 - The register stores the byte number of the data in Tx FIFO for Tx channel 2. + INFIFO_CNT_L3_CH1 + The register stores the byte number of the data in Tx FIFO for Tx channel 1. 18 2 read-only @@ -50159,73 +48226,81 @@ - OUT_PUSH_CH2 - TX CH2 outfifo push register - 0x218 + IN_POP_CH1 + RX CH1 INFIFO pop register + 0x618 0x20 + 0x00000400 - OUTFIFO_WDATA_CH2 - This register stores the data that need to be pushed into DMA Tx FIFO. + INFIFO_RDATA_CH1 + This register stores the data popping from DMA Rx FIFO. 0 - 10 - read-write + 11 + read-only - OUTFIFO_PUSH_CH2 - Set this bit to push data into DMA Tx FIFO. - 10 + INFIFO_POP_CH1 + Set this bit to pop data from DMA Rx FIFO. + 11 1 read-write - OUT_LINK_CONF_CH2 - TX CH2 out_link dscr ctrl register - 0x21C + IN_LINK_CONF_CH1 + RX CH1 in_link dscr ctrl register + 0x61C 0x20 - 0x00800000 + 0x01100000 - OUTLINK_STOP_CH2 - Set this bit to stop dealing with the outlink descriptors. + INLINK_AUTO_RET_CH1 + Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data. 20 1 read-write - OUTLINK_START_CH2 - Set this bit to start dealing with the outlink descriptors. + INLINK_STOP_CH1 + Set this bit to stop dealing with the inlink descriptors. 21 1 read-write - OUTLINK_RESTART_CH2 - Set this bit to restart a new outlink from the last address. + INLINK_START_CH1 + Set this bit to start dealing with the inlink descriptors. 22 1 read-write - OUTLINK_PARK_CH2 - 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working. + INLINK_RESTART_CH1 + Set this bit to mount a new inlink descriptor. 23 1 + read-write + + + INLINK_PARK_CH1 + 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working. + 24 + 1 read-only - OUT_LINK_ADDR_CH2 - TX CH2 out_link dscr addr register - 0x220 + IN_LINK_ADDR_CH1 + RX CH1 in_link dscr addr register + 0x620 0x20 - OUTLINK_ADDR_CH2 - This register stores the first outlink descriptor's address. + INLINK_ADDR_CH1 + This register stores the first inlink descriptor's address. 0 32 read-write @@ -50233,50 +48308,50 @@ - OUT_STATE_CH2 - TX CH2 state register - 0x224 + IN_STATE_CH1 + RX CH1 state register + 0x624 0x20 - 0x01000000 + 0x00800000 - OUTLINK_DSCR_ADDR_CH2 - This register stores the current outlink descriptor's address. + INLINK_DSCR_ADDR_CH1 + This register stores the current inlink descriptor's address. 0 18 read-only - OUT_DSCR_STATE_CH2 + IN_DSCR_STATE_CH1 This register stores the current descriptor state machine state. 18 2 read-only - OUT_STATE_CH2 + IN_STATE_CH1 This register stores the current control module state machine state. 20 - 4 + 3 read-only - OUT_RESET_AVAIL_CH2 + IN_RESET_AVAIL_CH1 This register indicate that if the channel reset is safety. - 24 + 23 1 read-only - OUT_EOF_DES_ADDR_CH2 - TX CH2 eof des addr register - 0x228 + IN_SUC_EOF_DES_ADDR_CH1 + RX CH1 eof des addr register + 0x628 0x20 - OUT_EOF_DES_ADDR_CH2 + IN_SUC_EOF_DES_ADDR_CH1 This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. 0 32 @@ -50285,14 +48360,14 @@ - OUT_DSCR_CH2 - TX CH2 next dscr addr register - 0x22C + IN_ERR_EOF_DES_ADDR_CH1 + RX CH1 err eof des addr register + 0x62C 0x20 - OUTLINK_DSCR_CH2 - The address of the next outlink descriptor address y. + IN_ERR_EOF_DES_ADDR_CH1 + This register stores the address of the inlink descriptor when there are some errors in current receiving data. 0 32 read-only @@ -50300,14 +48375,14 @@ - OUT_DSCR_BF0_CH2 - TX CH2 last dscr addr register - 0x230 + IN_DSCR_CH1 + RX CH1 next dscr addr register + 0x630 0x20 - OUTLINK_DSCR_BF0_CH2 - The address of the last outlink descriptor's next address y-1. + INLINK_DSCR_CH1 + The address of the next inlink descriptor address x. 0 32 read-only @@ -50315,14 +48390,14 @@ - OUT_DSCR_BF1_CH2 - TX CH2 second-to-last dscr addr register - 0x234 + IN_DSCR_BF0_CH1 + RX CH1 last dscr addr register + 0x634 0x20 - OUTLINK_DSCR_BF1_CH2 - The address of the second-to-last outlink descriptor's next address y-2. + INLINK_DSCR_BF0_CH1 + The address of the last inlink descriptor's next address x-1. 0 32 read-only @@ -50330,51 +48405,73 @@ - OUT_ARB_CH2 - TX CH2 arb register - 0x23C + IN_DSCR_BF1_CH1 + RX CH1 second-to-last dscr addr register + 0x638 0x20 - 0x00000041 - OUT_ARB_TOKEN_NUM_CH2 + INLINK_DSCR_BF1_CH1 + The address of the second-to-last inlink descriptor's next address x-2. + 0 + 32 + read-only + + + + + IN_ARB_CH1 + RX CH1 arb register + 0x640 + 0x20 + 0x00000051 + + + IN_ARB_TOKEN_NUM_CH1 Set the max number of token count of arbiter 0 4 read-write - INTER_OUT_ARB_PRIORITY_CH2 + EXTER_IN_ARB_PRIORITY_CH1 + Set the priority of channel + 4 + 2 + read-write + + + INTER_IN_ARB_PRIORITY_CH1 Set the priority of channel 6 - 1 + 3 read-write - OUT_ETM_CONF_CH2 - TX CH2 ETM config register - 0x268 + IN_ETM_CONF_CH1 + RX CH1 ETM config register + 0x648 0x20 0x00000004 - OUT_ETM_EN_CH2 + IN_ETM_EN_CH1 Set this bit to 1 to enable ETM task function 0 1 read-write - OUT_ETM_LOOP_EN_CH2 + IN_ETM_LOOP_EN_CH1 when this bit is 1, dscr can be processed after receiving a task 1 1 read-write - OUT_DSCR_TASK_MAK_CH2 + IN_DSCR_TASK_MAK_CH1 ETM dscr_ready maximum cache numbers 2 2 @@ -50383,124 +48480,123 @@ - OUT_BUF_LEN_CH2 - tx CH2 buf len register - 0x270 + IN_FIFO_CNT_CH1 + rx CH1 fifo cnt register + 0x680 0x20 - OUT_CMDFIFO_BUF_LEN_HB_CH2 + IN_CMDFIFO_INFIFO_CNT_CH1 only for debug 0 - 13 + 10 read-only - OUT_FIFO_BCNT_CH2 - tx CH2 fifo byte cnt register - 0x274 + IN_POP_DATA_CNT_CH1 + rx CH1 pop data cnt register + 0x684 0x20 + 0x00000007 - OUT_CMDFIFO_OUTFIFO_BCNT_CH2 + IN_CMDFIFO_POP_DATA_CNT_CH1 only for debug 0 - 10 + 8 read-only - OUT_PUSH_BYTECNT_CH2 - tx CH2 push byte cnt register - 0x278 + IN_XADDR_CH1 + rx CH1 xaddr register + 0x688 0x20 - 0x000000FF - OUT_CMDFIFO_PUSH_BYTECNT_CH2 + IN_CMDFIFO_XADDR_CH1 only for debug 0 - 8 + 32 read-only - OUT_XADDR_CH2 - tx CH2 xaddr register - 0x27C + IN_BUF_HB_RCV_CH1 + rx CH1 buf len hb rcv register + 0x68C 0x20 - OUT_CMDFIFO_XADDR_CH2 + IN_CMDFIFO_BUF_HB_RCV_CH1 only for debug 0 - 32 + 29 read-only - OUT_CONF0_CH3 - TX CH3 config0 register - 0x300 + IN_CONF0_CH2 + RX CH2 config0 register + 0x700 0x20 - 0x00000002 - OUT_AUTO_WRBACK_CH3 - Set this bit to enable automatic outlink-writeback when all the data pointed by outlink descriptor has been received. - 0 - 1 - read-write - - - OUT_EOF_MODE_CH3 - EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is generated when data need to read has been popped from FIFO in DMA - 1 - 1 - read-write - - - OUTDSCR_BURST_EN_CH3 - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM. + INDSCR_BURST_EN_CH2 + Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor when accessing SRAM. 2 1 read-write - OUT_ECC_AES_EN_CH3 + IN_ECC_AES_EN_CH2 When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned. 3 1 read-write - OUT_CHECK_OWNER_CH3 + IN_CHECK_OWNER_CH2 Set this bit to enable checking the owner attribute of the link descriptor. 4 1 read-write - OUT_MEM_BURST_LENGTH_CH3 - Block size of Tx channel 3. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes + IN_MEM_BURST_LENGTH_CH2 + Block size of Rx channel 2. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes 6 3 read-write - OUT_PAGE_BOUND_EN_CH3 - Set this bit to 1 to make sure AXI read data don't cross the address boundary which define by mem_burst_length + IN_PAGE_BOUND_EN_CH2 + Set this bit to 1 to make sure AXI write data don't cross the address boundary which define by mem_burst_length 12 1 read-write - OUT_ARB_WEIGHT_OPT_DIS_CH3 + IN_RST_CH2 + Write 1 then write 0 to this bit to reset Rx channel + 24 + 1 + read-write + + + IN_CMD_DISABLE_CH2 + Write 1 before reset and write 0 after reset + 25 + 1 + read-write + + + IN_ARB_WEIGHT_OPT_DIS_CH2 Set this bit to 1 to disable arbiter optimum weight function. 26 1 @@ -50509,355 +48605,383 @@ - OUT_INT_RAW_CH3 - TX CH3 interrupt raw register - 0x304 + IN_INT_RAW_CH2 + RX CH2 interrupt raw register + 0x704 0x20 - OUT_DONE_CH3_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0. + IN_DONE_CH2_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been transmitted to peripherals for Rx channel 1. 0 1 read-write - OUT_EOF_CH3_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. + IN_SUC_EOF_CH2_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1. 1 1 read-write - OUT_DSCR_ERR_CH3_INT_RAW - The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0. + IN_ERR_EOF_CH2_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and data error is detected 2 1 read-write - OUT_TOTAL_EOF_CH3_INT_RAW - The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0. + IN_DSCR_ERR_CH2_INT_RAW + The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 1. 3 1 read-write - OUTFIFO_OVF_L1_CH3_INT_RAW - The raw interrupt bit turns to high level when fifo is overflow. + INFIFO_OVF_L1_CH2_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is overflow. 4 1 read-write - OUTFIFO_UDF_L1_CH3_INT_RAW - The raw interrupt bit turns to high level when fifo is underflow. + INFIFO_UDF_L1_CH2_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is underflow. 5 1 read-write - OUTFIFO_OVF_L2_CH3_INT_RAW - The raw interrupt bit turns to high level when fifo is overflow. + INFIFO_OVF_L2_CH2_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is overflow. 6 1 read-write - OUTFIFO_UDF_L2_CH3_INT_RAW - The raw interrupt bit turns to high level when fifo is underflow. + INFIFO_UDF_L2_CH2_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is underflow. 7 1 read-write - OUT_DSCR_TASK_OVF_CH3_INT_RAW - The raw interrupt bit turns to high level when dscr ready task fifo is overflow. + IN_DSCR_EMPTY_CH2_INT_RAW + The raw interrupt bit turns to high level when the last descriptor is done but fifo also remain data. 8 1 read-write + + IN_DSCR_TASK_OVF_CH2_INT_RAW + The raw interrupt bit turns to high level when dscr ready task fifo is overflow. + 9 + 1 + read-write + - OUT_INT_ENA_CH3 - TX CH3 interrupt ena register - 0x308 + IN_INT_ENA_CH2 + RX CH2 interrupt ena register + 0x708 0x20 - OUT_DONE_CH3_INT_ENA - The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + IN_DONE_CH2_INT_ENA + The interrupt enable bit for the IN_DONE_CH_INT interrupt. 0 1 read-write - OUT_EOF_CH3_INT_ENA - The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + IN_SUC_EOF_CH2_INT_ENA + The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. 1 1 read-write - OUT_DSCR_ERR_CH3_INT_ENA - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + IN_ERR_EOF_CH2_INT_ENA + The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. 2 1 read-write - OUT_TOTAL_EOF_CH3_INT_ENA - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + IN_DSCR_ERR_CH2_INT_ENA + The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. 3 1 read-write - OUTFIFO_OVF_L1_CH3_INT_ENA - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + INFIFO_OVF_L1_CH2_INT_ENA + The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. 4 1 read-write - OUTFIFO_UDF_L1_CH3_INT_ENA - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + INFIFO_UDF_L1_CH2_INT_ENA + The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. 5 1 read-write - OUTFIFO_OVF_L2_CH3_INT_ENA - The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. + INFIFO_OVF_L2_CH2_INT_ENA + The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. 6 1 read-write - OUTFIFO_UDF_L2_CH3_INT_ENA - The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. + INFIFO_UDF_L2_CH2_INT_ENA + The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. 7 1 read-write - OUT_DSCR_TASK_OVF_CH3_INT_ENA - The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. + IN_DSCR_EMPTY_CH2_INT_ENA + The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. 8 1 read-write + + IN_DSCR_TASK_OVF_CH2_INT_ENA + The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. + 9 + 1 + read-write + - OUT_INT_ST_CH3 - TX CH3 interrupt st register - 0x30C + IN_INT_ST_CH2 + RX CH2 interrupt st register + 0x70C 0x20 - OUT_DONE_CH3_INT_ST - The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + IN_DONE_CH2_INT_ST + The raw interrupt status bit for the IN_DONE_CH_INT interrupt. 0 1 read-only - OUT_EOF_CH3_INT_ST - The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + IN_SUC_EOF_CH2_INT_ST + The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. 1 1 read-only - OUT_DSCR_ERR_CH3_INT_ST - The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + IN_ERR_EOF_CH2_INT_ST + The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. 2 1 read-only - OUT_TOTAL_EOF_CH3_INT_ST - The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + IN_DSCR_ERR_CH2_INT_ST + The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. 3 1 read-only - OUTFIFO_OVF_L1_CH3_INT_ST - The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + INFIFO_OVF_L1_CH2_INT_ST + The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. 4 1 read-only - OUTFIFO_UDF_L1_CH3_INT_ST - The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + INFIFO_UDF_L1_CH2_INT_ST + The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. 5 1 read-only - OUTFIFO_OVF_L2_CH3_INT_ST - The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. + INFIFO_OVF_L2_CH2_INT_ST + The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. 6 1 read-only - OUTFIFO_UDF_L2_CH3_INT_ST - The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. + INFIFO_UDF_L2_CH2_INT_ST + The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. 7 1 read-only - OUT_DSCR_TASK_OVF_CH3_INT_ST - The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. + IN_DSCR_EMPTY_CH2_INT_ST + The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. 8 1 read-only + + IN_DSCR_TASK_OVF_CH2_INT_ST + The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. + 9 + 1 + read-only + - OUT_INT_CLR_CH3 - TX CH3 interrupt clr register - 0x310 + IN_INT_CLR_CH2 + RX CH2 interrupt clr register + 0x710 0x20 - OUT_DONE_CH3_INT_CLR - Set this bit to clear the OUT_DONE_CH_INT interrupt. + IN_DONE_CH2_INT_CLR + Set this bit to clear the IN_DONE_CH_INT interrupt. 0 1 write-only - OUT_EOF_CH3_INT_CLR - Set this bit to clear the OUT_EOF_CH_INT interrupt. + IN_SUC_EOF_CH2_INT_CLR + Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. 1 1 write-only - OUT_DSCR_ERR_CH3_INT_CLR - Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + IN_ERR_EOF_CH2_INT_CLR + Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. 2 1 write-only - OUT_TOTAL_EOF_CH3_INT_CLR - Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + IN_DSCR_ERR_CH2_INT_CLR + Set this bit to clear the INDSCR_ERR_CH_INT interrupt. 3 1 write-only - OUTFIFO_OVF_L1_CH3_INT_CLR - Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + INFIFO_OVF_L1_CH2_INT_CLR + Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. 4 1 write-only - OUTFIFO_UDF_L1_CH3_INT_CLR - Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + INFIFO_UDF_L1_CH2_INT_CLR + Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. 5 1 write-only - OUTFIFO_OVF_L2_CH3_INT_CLR - Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. + INFIFO_OVF_L2_CH2_INT_CLR + Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. 6 1 write-only - OUTFIFO_UDF_L2_CH3_INT_CLR - Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. + INFIFO_UDF_L2_CH2_INT_CLR + Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. 7 1 write-only - OUT_DSCR_TASK_OVF_CH3_INT_CLR - Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt. + IN_DSCR_EMPTY_CH2_INT_CLR + Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. 8 1 write-only + + IN_DSCR_TASK_OVF_CH2_INT_CLR + Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt. + 9 + 1 + write-only + - OUTFIFO_STATUS_CH3 - TX CH3 outfifo status register - 0x314 + INFIFO_STATUS_CH2 + RX CH2 INFIFO status register + 0x714 0x20 0x00020082 - OUTFIFO_FULL_L2_CH3 - Tx FIFO full signal for Tx channel 2. + INFIFO_FULL_L2_CH2 + Rx FIFO full signal for Rx channel. 0 1 read-only - OUTFIFO_EMPTY_L2_CH3 - Tx FIFO empty signal for Tx channel 2. - 1 + INFIFO_EMPTY_L2_CH2 + Rx FIFO empty signal for Rx channel. + 1 1 read-only - OUTFIFO_CNT_L2_CH3 - The register stores the byte number of the data in Tx FIFO for Tx channel 2. + INFIFO_CNT_L2_CH2 + The register stores the byte number of the data in Rx FIFO for Rx channel. 2 4 read-only - OUTFIFO_FULL_L1_CH3 - Tx FIFO full signal for Tx channel 2. + INFIFO_FULL_L1_CH2 + Tx FIFO full signal for Tx channel 1. 6 1 read-only - OUTFIFO_EMPTY_L1_CH3 - Tx FIFO empty signal for Tx channel 2. + INFIFO_EMPTY_L1_CH2 + Tx FIFO empty signal for Tx channel 1. 7 1 read-only - OUTFIFO_CNT_L1_CH3 - The register stores the byte number of the data in Tx FIFO for Tx channel 2. + INFIFO_CNT_L1_CH2 + The register stores the byte number of the data in Tx FIFO for Tx channel 1. 8 5 read-only - OUTFIFO_FULL_L3_CH3 - Tx FIFO full signal for Tx channel 2. + INFIFO_FULL_L3_CH2 + Tx FIFO full signal for Tx channel 1. 16 1 read-only - OUTFIFO_EMPTY_L3_CH3 - Tx FIFO empty signal for Tx channel 2. + INFIFO_EMPTY_L3_CH2 + Tx FIFO empty signal for Tx channel 1. 17 1 read-only - OUTFIFO_CNT_L3_CH3 - The register stores the byte number of the data in Tx FIFO for Tx channel 2. + INFIFO_CNT_L3_CH2 + The register stores the byte number of the data in Tx FIFO for Tx channel 1. 18 2 read-only @@ -50865,73 +48989,81 @@ - OUT_PUSH_CH3 - TX CH3 outfifo push register - 0x318 + IN_POP_CH2 + RX CH2 INFIFO pop register + 0x718 0x20 + 0x00000400 - OUTFIFO_WDATA_CH3 - This register stores the data that need to be pushed into DMA Tx FIFO. + INFIFO_RDATA_CH2 + This register stores the data popping from DMA Rx FIFO. 0 - 10 - read-write + 11 + read-only - OUTFIFO_PUSH_CH3 - Set this bit to push data into DMA Tx FIFO. - 10 + INFIFO_POP_CH2 + Set this bit to pop data from DMA Rx FIFO. + 11 1 read-write - OUT_LINK_CONF_CH3 - TX CH3 out_link dscr ctrl register - 0x31C + IN_LINK_CONF_CH2 + RX CH2 in_link dscr ctrl register + 0x71C 0x20 - 0x00800000 + 0x01100000 - OUTLINK_STOP_CH3 - Set this bit to stop dealing with the outlink descriptors. + INLINK_AUTO_RET_CH2 + Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data. 20 1 read-write - OUTLINK_START_CH3 - Set this bit to start dealing with the outlink descriptors. + INLINK_STOP_CH2 + Set this bit to stop dealing with the inlink descriptors. 21 1 read-write - OUTLINK_RESTART_CH3 - Set this bit to restart a new outlink from the last address. + INLINK_START_CH2 + Set this bit to start dealing with the inlink descriptors. 22 1 read-write - OUTLINK_PARK_CH3 - 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working. + INLINK_RESTART_CH2 + Set this bit to mount a new inlink descriptor. 23 1 + read-write + + + INLINK_PARK_CH2 + 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working. + 24 + 1 read-only - OUT_LINK_ADDR_CH3 - TX CH3 out_link dscr addr register - 0x320 + IN_LINK_ADDR_CH2 + RX CH2 in_link dscr addr register + 0x720 0x20 - OUTLINK_ADDR_CH3 - This register stores the first outlink descriptor's address. + INLINK_ADDR_CH2 + This register stores the first inlink descriptor's address. 0 32 read-write @@ -50939,42 +49071,50 @@ - OUT_STATE_CH3 - TX CH3 state register - 0x324 + IN_STATE_CH2 + RX CH2 state register + 0x724 0x20 + 0x00800000 - OUTLINK_DSCR_ADDR_CH3 - This register stores the current outlink descriptor's address. + INLINK_DSCR_ADDR_CH2 + This register stores the current inlink descriptor's address. 0 18 read-only - OUT_DSCR_STATE_CH3 + IN_DSCR_STATE_CH2 This register stores the current descriptor state machine state. 18 2 read-only - OUT_STATE_CH3 + IN_STATE_CH2 This register stores the current control module state machine state. 20 - 4 + 3 + read-only + + + IN_RESET_AVAIL_CH2 + This register indicate that if the channel reset is safety. + 23 + 1 read-only - OUT_EOF_DES_ADDR_CH3 - TX CH3 eof des addr register - 0x328 + IN_SUC_EOF_DES_ADDR_CH2 + RX CH2 eof des addr register + 0x728 0x20 - OUT_EOF_DES_ADDR_CH3 + IN_SUC_EOF_DES_ADDR_CH2 This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. 0 32 @@ -50983,14 +49123,14 @@ - OUT_DSCR_CH3 - TX CH3 next dscr addr register - 0x32C + IN_ERR_EOF_DES_ADDR_CH2 + RX CH2 err eof des addr register + 0x72C 0x20 - OUTLINK_DSCR_CH3 - The address of the next outlink descriptor address y. + IN_ERR_EOF_DES_ADDR_CH2 + This register stores the address of the inlink descriptor when there are some errors in current receiving data. 0 32 read-only @@ -50998,14 +49138,14 @@ - OUT_DSCR_BF0_CH3 - TX CH3 last dscr addr register - 0x330 + IN_DSCR_CH2 + RX CH2 next dscr addr register + 0x730 0x20 - OUTLINK_DSCR_BF0_CH3 - The address of the last outlink descriptor's next address y-1. + INLINK_DSCR_CH2 + The address of the next inlink descriptor address x. 0 32 read-only @@ -51013,14 +49153,14 @@ - OUT_DSCR_BF1_CH3 - TX CH3 second-to-last dscr addr register - 0x334 + IN_DSCR_BF0_CH2 + RX CH2 last dscr addr register + 0x734 0x20 - OUTLINK_DSCR_BF1_CH3 - The address of the second-to-last outlink descriptor's next address y-2. + INLINK_DSCR_BF0_CH2 + The address of the last inlink descriptor's next address x-1. 0 32 read-only @@ -51028,51 +49168,66 @@ - OUT_ARB_CH3 - TX CH3 arb register - 0x33C + IN_DSCR_BF1_CH2 + RX CH2 second-to-last dscr addr register + 0x738 0x20 - 0x00000011 - OUT_ARB_TOKEN_NUM_CH3 + INLINK_DSCR_BF1_CH2 + The address of the second-to-last inlink descriptor's next address x-2. + 0 + 32 + read-only + + + + + IN_ARB_CH2 + RX CH2 arb register + 0x740 + 0x20 + 0x00000041 + + + IN_ARB_TOKEN_NUM_CH2 Set the max number of token count of arbiter 0 4 read-write - EXTER_OUT_ARB_PRIORITY_CH3 + INTER_IN_ARB_PRIORITY_CH2 Set the priority of channel - 4 - 2 + 6 + 3 read-write - OUT_ETM_CONF_CH3 - TX CH3 ETM config register - 0x368 + IN_ETM_CONF_CH2 + RX CH2 ETM config register + 0x748 0x20 0x00000004 - OUT_ETM_EN_CH3 + IN_ETM_EN_CH2 Set this bit to 1 to enable ETM task function 0 1 read-write - OUT_ETM_LOOP_EN_CH3 + IN_ETM_LOOP_EN_CH2 when this bit is 1, dscr can be processed after receiving a task 1 1 read-write - OUT_DSCR_TASK_MAK_CH3 + IN_DSCR_TASK_MAK_CH2 ETM dscr_ready maximum cache numbers 2 2 @@ -51081,28 +49236,13 @@ - OUT_BUF_LEN_CH3 - tx CH3 buf len register - 0x370 - 0x20 - - - OUT_CMDFIFO_BUF_LEN_HB_CH3 - only for debug - 0 - 13 - read-only - - - - - OUT_FIFO_BCNT_CH3 - tx CH3 fifo byte cnt register - 0x374 + IN_FIFO_CNT_CH2 + rx CH2 fifo cnt register + 0x780 0x20 - OUT_CMDFIFO_OUTFIFO_BCNT_CH3 + IN_CMDFIFO_INFIFO_CNT_CH2 only for debug 0 10 @@ -51111,14 +49251,14 @@ - OUT_PUSH_BYTECNT_CH3 - tx CH3 push byte cnt register - 0x378 + IN_POP_DATA_CNT_CH2 + rx CH2 pop data cnt register + 0x784 0x20 - 0x0000003F + 0x00000007 - OUT_CMDFIFO_PUSH_BYTECNT_CH3 + IN_CMDFIFO_POP_DATA_CNT_CH2 only for debug 0 8 @@ -51127,13 +49267,13 @@ - OUT_XADDR_CH3 - tx CH3 xaddr register - 0x37C + IN_XADDR_CH2 + rx CH2 xaddr register + 0x788 0x20 - OUT_CMDFIFO_XADDR_CH3 + IN_CMDFIFO_XADDR_CH2 only for debug 0 32 @@ -51142,78 +49282,77 @@ - OUT_BLOCK_BUF_LEN_CH3 - tx CH3 block buf len register - 0x380 + IN_BUF_HB_RCV_CH2 + rx CH2 buf len hb rcv register + 0x78C 0x20 - OUT_BLOCK_BUF_LEN_CH3 + IN_CMDFIFO_BUF_HB_RCV_CH2 only for debug 0 - 28 + 29 read-only - OUT_CONF0_CH4 - TX CH4 config0 register - 0x400 + IN_CONF0_CH3 + RX CH3 config0 register + 0x800 0x20 - 0x00000002 - OUT_AUTO_WRBACK_CH4 - Set this bit to enable automatic outlink-writeback when all the data pointed by outlink descriptor has been received. - 0 - 1 - read-write - - - OUT_EOF_MODE_CH4 - EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is generated when data need to read has been popped from FIFO in DMA - 1 - 1 - read-write - - - OUTDSCR_BURST_EN_CH4 - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM. + INDSCR_BURST_EN_CH3 + Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor when accessing SRAM. 2 1 read-write - OUT_ECC_AES_EN_CH4 + IN_ECC_AES_EN_CH3 When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned. 3 1 read-write - OUT_CHECK_OWNER_CH4 + IN_CHECK_OWNER_CH3 Set this bit to enable checking the owner attribute of the link descriptor. 4 1 read-write - OUT_MEM_BURST_LENGTH_CH4 - Block size of Tx channel 4. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes + IN_MEM_BURST_LENGTH_CH3 + Block size of Rx channel 1. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes 6 3 read-write - OUT_PAGE_BOUND_EN_CH4 - Set this bit to 1 to make sure AXI read data don't cross the address boundary which define by mem_burst_length + IN_PAGE_BOUND_EN_CH3 + Set this bit to 1 to make sure AXI write data don't cross the address boundary which define by mem_burst_length 12 1 read-write - OUT_ARB_WEIGHT_OPT_DIS_CH4 + IN_RST_CH3 + Write 1 then write 0 to this bit to reset Rx channel + 24 + 1 + read-write + + + IN_CMD_DISABLE_CH3 + Write 1 before reset and write 0 after reset + 25 + 1 + read-write + + + IN_ARB_WEIGHT_OPT_DIS_CH3 Set this bit to 1 to disable arbiter optimum weight function. 26 1 @@ -51222,355 +49361,383 @@ - OUT_INT_RAW_CH4 - TX CH4 interrupt raw register - 0x404 + IN_INT_RAW_CH3 + RX CH3 interrupt raw register + 0x804 0x20 - OUT_DONE_CH4_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0. + IN_DONE_CH3_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been transmitted to peripherals for Rx channel 1. 0 1 read-write - OUT_EOF_CH4_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. + IN_SUC_EOF_CH3_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1. 1 1 read-write - OUT_DSCR_ERR_CH4_INT_RAW - The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0. + IN_ERR_EOF_CH3_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and data error is detected 2 1 read-write - OUT_TOTAL_EOF_CH4_INT_RAW - The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0. + IN_DSCR_ERR_CH3_INT_RAW + The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 1. 3 1 read-write - OUTFIFO_OVF_L1_CH4_INT_RAW - The raw interrupt bit turns to high level when fifo is overflow. + INFIFO_OVF_L1_CH3_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is overflow. 4 1 read-write - OUTFIFO_UDF_L1_CH4_INT_RAW - The raw interrupt bit turns to high level when fifo is underflow. + INFIFO_UDF_L1_CH3_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is underflow. 5 1 read-write - OUTFIFO_OVF_L2_CH4_INT_RAW - The raw interrupt bit turns to high level when fifo is overflow. + INFIFO_OVF_L2_CH3_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is overflow. 6 1 read-write - OUTFIFO_UDF_L2_CH4_INT_RAW - The raw interrupt bit turns to high level when fifo is underflow. + INFIFO_UDF_L2_CH3_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is underflow. 7 1 read-write - OUT_DSCR_TASK_OVF_CH4_INT_RAW - The raw interrupt bit turns to high level when dscr ready task fifo is overflow. + IN_DSCR_EMPTY_CH3_INT_RAW + The raw interrupt bit turns to high level when the last descriptor is done but fifo also remain data. 8 1 read-write + + IN_DSCR_TASK_OVF_CH3_INT_RAW + The raw interrupt bit turns to high level when dscr ready task fifo is overflow. + 9 + 1 + read-write + - OUT_INT_ENA_CH4 - TX CH4 interrupt ena register - 0x408 + IN_INT_ENA_CH3 + RX CH3 interrupt ena register + 0x808 0x20 - OUT_DONE_CH4_INT_ENA - The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + IN_DONE_CH3_INT_ENA + The interrupt enable bit for the IN_DONE_CH_INT interrupt. 0 1 read-write - OUT_EOF_CH4_INT_ENA - The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + IN_SUC_EOF_CH3_INT_ENA + The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. 1 1 read-write - OUT_DSCR_ERR_CH4_INT_ENA - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + IN_ERR_EOF_CH3_INT_ENA + The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. 2 1 read-write - OUT_TOTAL_EOF_CH4_INT_ENA - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + IN_DSCR_ERR_CH3_INT_ENA + The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. 3 1 read-write - OUTFIFO_OVF_L1_CH4_INT_ENA - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + INFIFO_OVF_L1_CH3_INT_ENA + The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. 4 1 read-write - OUTFIFO_UDF_L1_CH4_INT_ENA - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + INFIFO_UDF_L1_CH3_INT_ENA + The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. 5 1 read-write - OUTFIFO_OVF_L2_CH4_INT_ENA - The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. + INFIFO_OVF_L2_CH3_INT_ENA + The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. 6 1 read-write - OUTFIFO_UDF_L2_CH4_INT_ENA - The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. + INFIFO_UDF_L2_CH3_INT_ENA + The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. 7 1 read-write - OUT_DSCR_TASK_OVF_CH4_INT_ENA - The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. + IN_DSCR_EMPTY_CH3_INT_ENA + The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. 8 1 read-write + + IN_DSCR_TASK_OVF_CH3_INT_ENA + The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. + 9 + 1 + read-write + - OUT_INT_ST_CH4 - TX CH4 interrupt st register - 0x40C + IN_INT_ST_CH3 + RX CH3 interrupt st register + 0x80C 0x20 - OUT_DONE_CH4_INT_ST - The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + IN_DONE_CH3_INT_ST + The raw interrupt status bit for the IN_DONE_CH_INT interrupt. 0 1 read-only - OUT_EOF_CH4_INT_ST - The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + IN_SUC_EOF_CH3_INT_ST + The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. 1 1 read-only - OUT_DSCR_ERR_CH4_INT_ST - The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + IN_ERR_EOF_CH3_INT_ST + The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. 2 1 read-only - OUT_TOTAL_EOF_CH4_INT_ST - The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + IN_DSCR_ERR_CH3_INT_ST + The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. 3 1 read-only - OUTFIFO_OVF_L1_CH4_INT_ST - The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + INFIFO_OVF_L1_CH3_INT_ST + The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. 4 1 read-only - OUTFIFO_UDF_L1_CH4_INT_ST - The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + INFIFO_UDF_L1_CH3_INT_ST + The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. 5 1 read-only - OUTFIFO_OVF_L2_CH4_INT_ST - The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. + INFIFO_OVF_L2_CH3_INT_ST + The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. 6 1 read-only - OUTFIFO_UDF_L2_CH4_INT_ST - The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. + INFIFO_UDF_L2_CH3_INT_ST + The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. 7 1 read-only - OUT_DSCR_TASK_OVF_CH4_INT_ST - The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. + IN_DSCR_EMPTY_CH3_INT_ST + The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. 8 1 read-only + + IN_DSCR_TASK_OVF_CH3_INT_ST + The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. + 9 + 1 + read-only + - OUT_INT_CLR_CH4 - TX CH4 interrupt clr register - 0x410 + IN_INT_CLR_CH3 + RX CH3 interrupt clr register + 0x810 0x20 - OUT_DONE_CH4_INT_CLR - Set this bit to clear the OUT_DONE_CH_INT interrupt. + IN_DONE_CH3_INT_CLR + Set this bit to clear the IN_DONE_CH_INT interrupt. 0 1 write-only - OUT_EOF_CH4_INT_CLR - Set this bit to clear the OUT_EOF_CH_INT interrupt. + IN_SUC_EOF_CH3_INT_CLR + Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. 1 1 write-only - OUT_DSCR_ERR_CH4_INT_CLR - Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + IN_ERR_EOF_CH3_INT_CLR + Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. 2 1 write-only - OUT_TOTAL_EOF_CH4_INT_CLR - Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + IN_DSCR_ERR_CH3_INT_CLR + Set this bit to clear the INDSCR_ERR_CH_INT interrupt. 3 1 write-only - OUTFIFO_OVF_L1_CH4_INT_CLR - Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + INFIFO_OVF_L1_CH3_INT_CLR + Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. 4 1 write-only - OUTFIFO_UDF_L1_CH4_INT_CLR - Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + INFIFO_UDF_L1_CH3_INT_CLR + Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. 5 1 write-only - OUTFIFO_OVF_L2_CH4_INT_CLR - Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. + INFIFO_OVF_L2_CH3_INT_CLR + Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. 6 1 write-only - OUTFIFO_UDF_L2_CH4_INT_CLR - Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. + INFIFO_UDF_L2_CH3_INT_CLR + Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. 7 1 write-only - OUT_DSCR_TASK_OVF_CH4_INT_CLR - Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt. + IN_DSCR_EMPTY_CH3_INT_CLR + Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. 8 1 write-only + + IN_DSCR_TASK_OVF_CH3_INT_CLR + Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt. + 9 + 1 + write-only + - OUTFIFO_STATUS_CH4 - TX CH4 outfifo status register - 0x414 + INFIFO_STATUS_CH3 + RX CH3 INFIFO status register + 0x814 0x20 0x00020082 - OUTFIFO_FULL_L2_CH4 - Tx FIFO full signal for Tx channel 2. + INFIFO_FULL_L2_CH3 + Rx FIFO full signal for Rx channel. 0 1 read-only - OUTFIFO_EMPTY_L2_CH4 - Tx FIFO empty signal for Tx channel 2. + INFIFO_EMPTY_L2_CH3 + Rx FIFO empty signal for Rx channel. 1 1 read-only - OUTFIFO_CNT_L2_CH4 - The register stores the byte number of the data in Tx FIFO for Tx channel 2. + INFIFO_CNT_L2_CH3 + The register stores the byte number of the data in Rx FIFO for Rx channel. 2 4 read-only - OUTFIFO_FULL_L1_CH4 - Tx FIFO full signal for Tx channel 2. + INFIFO_FULL_L1_CH3 + Tx FIFO full signal for Tx channel 1. 6 1 read-only - OUTFIFO_EMPTY_L1_CH4 - Tx FIFO empty signal for Tx channel 2. + INFIFO_EMPTY_L1_CH3 + Tx FIFO empty signal for Tx channel 1. 7 1 read-only - OUTFIFO_CNT_L1_CH4 - The register stores the byte number of the data in Tx FIFO for Tx channel 2. + INFIFO_CNT_L1_CH3 + The register stores the byte number of the data in Tx FIFO for Tx channel 1. 8 5 read-only - OUTFIFO_FULL_L3_CH4 - Tx FIFO full signal for Tx channel 2. + INFIFO_FULL_L3_CH3 + Tx FIFO full signal for Tx channel 1. 16 1 read-only - OUTFIFO_EMPTY_L3_CH4 - Tx FIFO empty signal for Tx channel 2. + INFIFO_EMPTY_L3_CH3 + Tx FIFO empty signal for Tx channel 1. 17 1 read-only - OUTFIFO_CNT_L3_CH4 - The register stores the byte number of the data in Tx FIFO for Tx channel 2. + INFIFO_CNT_L3_CH3 + The register stores the byte number of the data in Tx FIFO for Tx channel 1. 18 2 read-only @@ -51578,73 +49745,81 @@ - OUT_PUSH_CH4 - TX CH4 outfifo push register - 0x418 + IN_POP_CH3 + RX CH3 INFIFO pop register + 0x818 0x20 + 0x00000400 - OUTFIFO_WDATA_CH4 - This register stores the data that need to be pushed into DMA Tx FIFO. + INFIFO_RDATA_CH3 + This register stores the data popping from DMA Rx FIFO. 0 - 10 - read-write + 11 + read-only - OUTFIFO_PUSH_CH4 - Set this bit to push data into DMA Tx FIFO. - 10 + INFIFO_POP_CH3 + Set this bit to pop data from DMA Rx FIFO. + 11 1 read-write - OUT_LINK_CONF_CH4 - TX CH4 out_link dscr ctrl register - 0x41C + IN_LINK_CONF_CH3 + RX CH3 in_link dscr ctrl register + 0x81C 0x20 - 0x00800000 + 0x01100000 - OUTLINK_STOP_CH4 - Set this bit to stop dealing with the outlink descriptors. + INLINK_AUTO_RET_CH3 + Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data. 20 1 read-write - OUTLINK_START_CH4 - Set this bit to start dealing with the outlink descriptors. + INLINK_STOP_CH3 + Set this bit to stop dealing with the inlink descriptors. 21 1 read-write - OUTLINK_RESTART_CH4 - Set this bit to restart a new outlink from the last address. + INLINK_START_CH3 + Set this bit to start dealing with the inlink descriptors. 22 1 read-write - OUTLINK_PARK_CH4 - 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working. + INLINK_RESTART_CH3 + Set this bit to mount a new inlink descriptor. 23 1 + read-write + + + INLINK_PARK_CH3 + 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working. + 24 + 1 read-only - OUT_LINK_ADDR_CH4 - TX CH4 out_link dscr addr register - 0x420 + IN_LINK_ADDR_CH3 + RX CH3 in_link dscr addr register + 0x820 0x20 - OUTLINK_ADDR_CH4 - This register stores the first outlink descriptor's address. + INLINK_ADDR_CH3 + This register stores the first inlink descriptor's address. 0 32 read-write @@ -51652,42 +49827,50 @@ - OUT_STATE_CH4 - TX CH4 state register - 0x424 + IN_STATE_CH3 + RX CH3 state register + 0x824 0x20 + 0x00800000 - OUTLINK_DSCR_ADDR_CH4 - This register stores the current outlink descriptor's address. + INLINK_DSCR_ADDR_CH3 + This register stores the current inlink descriptor's address. 0 18 read-only - OUT_DSCR_STATE_CH4 + IN_DSCR_STATE_CH3 This register stores the current descriptor state machine state. 18 2 read-only - OUT_STATE_CH4 + IN_STATE_CH3 This register stores the current control module state machine state. 20 - 4 + 3 + read-only + + + IN_RESET_AVAIL_CH3 + This register indicate that if the channel reset is safety. + 23 + 1 read-only - OUT_EOF_DES_ADDR_CH4 - TX CH4 eof des addr register - 0x428 + IN_SUC_EOF_DES_ADDR_CH3 + RX CH3 eof des addr register + 0x828 0x20 - OUT_EOF_DES_ADDR_CH4 + IN_SUC_EOF_DES_ADDR_CH3 This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. 0 32 @@ -51696,14 +49879,14 @@ - OUT_DSCR_CH4 - TX CH4 next dscr addr register - 0x42C + IN_ERR_EOF_DES_ADDR_CH3 + RX CH3 err eof des addr register + 0x82C 0x20 - OUTLINK_DSCR_CH4 - The address of the next outlink descriptor address y. + IN_ERR_EOF_DES_ADDR_CH3 + This register stores the address of the inlink descriptor when there are some errors in current receiving data. 0 32 read-only @@ -51711,14 +49894,14 @@ - OUT_DSCR_BF0_CH4 - TX CH4 last dscr addr register - 0x430 + IN_DSCR_CH3 + RX CH3 next dscr addr register + 0x830 0x20 - OUTLINK_DSCR_BF0_CH4 - The address of the last outlink descriptor's next address y-1. + INLINK_DSCR_CH3 + The address of the next inlink descriptor address x. 0 32 read-only @@ -51726,14 +49909,14 @@ - OUT_DSCR_BF1_CH4 - TX CH4 second-to-last dscr addr register - 0x434 + IN_DSCR_BF0_CH3 + RX CH3 last dscr addr register + 0x834 0x20 - OUTLINK_DSCR_BF1_CH4 - The address of the second-to-last outlink descriptor's next address y-2. + INLINK_DSCR_BF0_CH3 + The address of the last inlink descriptor's next address x-1. 0 32 read-only @@ -51741,51 +49924,66 @@ - OUT_ARB_CH4 - TX CH4 arb register - 0x43C + IN_DSCR_BF1_CH3 + RX CH3 second-to-last dscr addr register + 0x838 0x20 - 0x00000011 - OUT_ARB_TOKEN_NUM_CH4 + INLINK_DSCR_BF1_CH3 + The address of the second-to-last inlink descriptor's next address x-2. + 0 + 32 + read-only + + + + + IN_ARB_CH3 + RX CH3 arb register + 0x840 + 0x20 + 0x00000041 + + + IN_ARB_TOKEN_NUM_CH3 Set the max number of token count of arbiter 0 4 read-write - EXTER_OUT_ARB_PRIORITY_CH4 + INTER_IN_ARB_PRIORITY_CH3 Set the priority of channel - 4 - 2 + 6 + 3 read-write - OUT_ETM_CONF_CH4 - TX CH4 ETM config register - 0x468 + IN_ETM_CONF_CH3 + RX CH3 ETM config register + 0x848 0x20 0x00000004 - OUT_ETM_EN_CH4 + IN_ETM_EN_CH3 Set this bit to 1 to enable ETM task function 0 1 read-write - OUT_ETM_LOOP_EN_CH4 + IN_ETM_LOOP_EN_CH3 when this bit is 1, dscr can be processed after receiving a task 1 1 read-write - OUT_DSCR_TASK_MAK_CH4 + IN_DSCR_TASK_MAK_CH3 ETM dscr_ready maximum cache numbers 2 2 @@ -51794,28 +49992,13 @@ - OUT_BUF_LEN_CH4 - tx CH4 buf len register - 0x470 - 0x20 - - - OUT_CMDFIFO_BUF_LEN_HB_CH4 - only for debug - 0 - 13 - read-only - - - - - OUT_FIFO_BCNT_CH4 - tx CH4 fifo byte cnt register - 0x474 + IN_FIFO_CNT_CH3 + rx CH3 fifo cnt register + 0x880 0x20 - OUT_CMDFIFO_OUTFIFO_BCNT_CH4 + IN_CMDFIFO_INFIFO_CNT_CH3 only for debug 0 10 @@ -51824,14 +50007,14 @@ - OUT_PUSH_BYTECNT_CH4 - tx CH4 push byte cnt register - 0x478 + IN_POP_DATA_CNT_CH3 + rx CH3 pop data cnt register + 0x884 0x20 - 0x0000003F + 0x00000007 - OUT_CMDFIFO_PUSH_BYTECNT_CH4 + IN_CMDFIFO_POP_DATA_CNT_CH3 only for debug 0 8 @@ -51840,13 +50023,13 @@ - OUT_XADDR_CH4 - tx CH4 xaddr register - 0x47C + IN_XADDR_CH3 + rx CH3 xaddr register + 0x888 0x20 - OUT_CMDFIFO_XADDR_CH4 + IN_CMDFIFO_XADDR_CH3 only for debug 0 32 @@ -51855,77 +50038,77 @@ - OUT_BLOCK_BUF_LEN_CH4 - tx CH4 block buf len register - 0x480 + IN_BUF_HB_RCV_CH3 + rx CH3 buf len hb rcv register + 0x88C 0x20 - OUT_BLOCK_BUF_LEN_CH4 + IN_CMDFIFO_BUF_HB_RCV_CH3 only for debug 0 - 28 + 29 read-only - IN_CONF0_CH0 - RX CH0 config0 register - 0x500 + IN_CONF0_CH4 + RX CH4 config0 register + 0x900 0x20 - INDSCR_BURST_EN_CH0 + INDSCR_BURST_EN_CH4 Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor when accessing SRAM. 2 1 read-write - IN_ECC_AES_EN_CH0 + IN_ECC_AES_EN_CH4 When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned. 3 1 read-write - IN_CHECK_OWNER_CH0 + IN_CHECK_OWNER_CH4 Set this bit to enable checking the owner attribute of the link descriptor. 4 1 read-write - IN_MEM_BURST_LENGTH_CH0 - Block size of Rx channel 0. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes + IN_MEM_BURST_LENGTH_CH4 + Block size of Rx channel 1. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes 6 3 read-write - IN_PAGE_BOUND_EN_CH0 + IN_PAGE_BOUND_EN_CH4 Set this bit to 1 to make sure AXI write data don't cross the address boundary which define by mem_burst_length 12 1 read-write - IN_RST_CH0 + IN_RST_CH4 Write 1 then write 0 to this bit to reset Rx channel 24 1 read-write - IN_CMD_DISABLE_CH0 + IN_CMD_DISABLE_CH4 Write 1 before reset and write 0 after reset 25 1 read-write - IN_ARB_WEIGHT_OPT_DIS_CH0 + IN_ARB_WEIGHT_OPT_DIS_CH4 Set this bit to 1 to disable arbiter optimum weight function. 26 1 @@ -51934,76 +50117,76 @@ - IN_INT_RAW_CH0 - RX CH0 interrupt raw register - 0x504 + IN_INT_RAW_CH4 + RX CH4 interrupt raw register + 0x904 0x20 - IN_DONE_CH0_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been transmitted to peripherals for Rx channel 0. + IN_DONE_CH4_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been transmitted to peripherals for Rx channel 1. 0 1 read-write - IN_SUC_EOF_CH0_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0. + IN_SUC_EOF_CH4_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1. 1 1 read-write - IN_ERR_EOF_CH0_INT_RAW + IN_ERR_EOF_CH4_INT_RAW The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and data error is detected 2 1 read-write - IN_DSCR_ERR_CH0_INT_RAW - The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0. + IN_DSCR_ERR_CH4_INT_RAW + The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 1. 3 1 read-write - INFIFO_OVF_L1_CH0_INT_RAW - The raw interrupt bit turns to high level when fifo of Rx channel is overflow. + INFIFO_OVF_L1_CH4_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is overflow. 4 1 read-write - INFIFO_UDF_L1_CH0_INT_RAW - The raw interrupt bit turns to high level when fifo of Rx channel is underflow. + INFIFO_UDF_L1_CH4_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is underflow. 5 1 read-write - INFIFO_OVF_L2_CH0_INT_RAW - The raw interrupt bit turns to high level when fifo of Rx channel is overflow. + INFIFO_OVF_L2_CH4_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is overflow. 6 1 read-write - INFIFO_UDF_L2_CH0_INT_RAW - The raw interrupt bit turns to high level when fifo of Rx channel is underflow. + INFIFO_UDF_L2_CH4_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is underflow. 7 1 read-write - IN_DSCR_EMPTY_CH0_INT_RAW + IN_DSCR_EMPTY_CH4_INT_RAW The raw interrupt bit turns to high level when the last descriptor is done but fifo also remain data. 8 1 read-write - IN_DSCR_TASK_OVF_CH0_INT_RAW + IN_DSCR_TASK_OVF_CH4_INT_RAW The raw interrupt bit turns to high level when dscr ready task fifo is overflow. 9 1 @@ -52012,76 +50195,76 @@ - IN_INT_ENA_CH0 - RX CH0 interrupt ena register - 0x508 + IN_INT_ENA_CH4 + RX CH4 interrupt ena register + 0x908 0x20 - IN_DONE_CH0_INT_ENA + IN_DONE_CH4_INT_ENA The interrupt enable bit for the IN_DONE_CH_INT interrupt. 0 1 read-write - IN_SUC_EOF_CH0_INT_ENA + IN_SUC_EOF_CH4_INT_ENA The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. 1 1 read-write - IN_ERR_EOF_CH0_INT_ENA + IN_ERR_EOF_CH4_INT_ENA The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. 2 1 read-write - IN_DSCR_ERR_CH0_INT_ENA + IN_DSCR_ERR_CH4_INT_ENA The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. 3 1 read-write - INFIFO_OVF_L1_CH0_INT_ENA + INFIFO_OVF_L1_CH4_INT_ENA The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. 4 1 read-write - INFIFO_UDF_L1_CH0_INT_ENA + INFIFO_UDF_L1_CH4_INT_ENA The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. 5 1 read-write - INFIFO_OVF_L2_CH0_INT_ENA + INFIFO_OVF_L2_CH4_INT_ENA The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. 6 1 read-write - INFIFO_UDF_L2_CH0_INT_ENA + INFIFO_UDF_L2_CH4_INT_ENA The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. 7 1 read-write - IN_DSCR_EMPTY_CH0_INT_ENA + IN_DSCR_EMPTY_CH4_INT_ENA The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. 8 1 read-write - IN_DSCR_TASK_OVF_CH0_INT_ENA + IN_DSCR_TASK_OVF_CH4_INT_ENA The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. 9 1 @@ -52090,76 +50273,76 @@ - IN_INT_ST_CH0 - RX CH0 interrupt st register - 0x50C + IN_INT_ST_CH4 + RX CH4 interrupt st register + 0x90C 0x20 - IN_DONE_CH0_INT_ST + IN_DONE_CH4_INT_ST The raw interrupt status bit for the IN_DONE_CH_INT interrupt. 0 1 read-only - IN_SUC_EOF_CH0_INT_ST + IN_SUC_EOF_CH4_INT_ST The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. 1 1 read-only - IN_ERR_EOF_CH0_INT_ST + IN_ERR_EOF_CH4_INT_ST The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. 2 1 read-only - IN_DSCR_ERR_CH0_INT_ST + IN_DSCR_ERR_CH4_INT_ST The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. 3 1 read-only - INFIFO_OVF_L1_CH0_INT_ST + INFIFO_OVF_L1_CH4_INT_ST The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. 4 1 read-only - INFIFO_UDF_L1_CH0_INT_ST + INFIFO_UDF_L1_CH4_INT_ST The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. 5 1 read-only - INFIFO_OVF_L2_CH0_INT_ST + INFIFO_OVF_L2_CH4_INT_ST The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. 6 1 read-only - INFIFO_UDF_L2_CH0_INT_ST + INFIFO_UDF_L2_CH4_INT_ST The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. 7 1 read-only - IN_DSCR_EMPTY_CH0_INT_ST + IN_DSCR_EMPTY_CH4_INT_ST The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. 8 1 read-only - IN_DSCR_TASK_OVF_CH0_INT_ST + IN_DSCR_TASK_OVF_CH4_INT_ST The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. 9 1 @@ -52168,76 +50351,76 @@ - IN_INT_CLR_CH0 - RX CH0 interrupt clr register - 0x510 + IN_INT_CLR_CH4 + RX CH4 interrupt clr register + 0x910 0x20 - IN_DONE_CH0_INT_CLR + IN_DONE_CH4_INT_CLR Set this bit to clear the IN_DONE_CH_INT interrupt. 0 1 write-only - IN_SUC_EOF_CH0_INT_CLR + IN_SUC_EOF_CH4_INT_CLR Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. 1 1 write-only - IN_ERR_EOF_CH0_INT_CLR + IN_ERR_EOF_CH4_INT_CLR Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. 2 1 write-only - IN_DSCR_ERR_CH0_INT_CLR + IN_DSCR_ERR_CH4_INT_CLR Set this bit to clear the INDSCR_ERR_CH_INT interrupt. 3 1 write-only - INFIFO_OVF_L1_CH0_INT_CLR + INFIFO_OVF_L1_CH4_INT_CLR Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. 4 1 write-only - INFIFO_UDF_L1_CH0_INT_CLR + INFIFO_UDF_L1_CH4_INT_CLR Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. 5 1 write-only - INFIFO_OVF_L2_CH0_INT_CLR + INFIFO_OVF_L2_CH4_INT_CLR Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. 6 1 write-only - INFIFO_UDF_L2_CH0_INT_CLR + INFIFO_UDF_L2_CH4_INT_CLR Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. 7 1 write-only - IN_DSCR_EMPTY_CH0_INT_CLR + IN_DSCR_EMPTY_CH4_INT_CLR Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. 8 1 write-only - IN_DSCR_TASK_OVF_CH0_INT_CLR + IN_DSCR_TASK_OVF_CH4_INT_CLR Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt. 9 1 @@ -52246,71 +50429,71 @@ - INFIFO_STATUS_CH0 - RX CH0 INFIFO status register - 0x514 + INFIFO_STATUS_CH4 + RX CH4 INFIFO status register + 0x914 0x20 0x00020082 - INFIFO_FULL_L2_CH0 + INFIFO_FULL_L2_CH4 Rx FIFO full signal for Rx channel. 0 1 read-only - INFIFO_EMPTY_L2_CH0 + INFIFO_EMPTY_L2_CH4 Rx FIFO empty signal for Rx channel. 1 1 read-only - INFIFO_CNT_L2_CH0 + INFIFO_CNT_L2_CH4 The register stores the byte number of the data in Rx FIFO for Rx channel. 2 4 read-only - INFIFO_FULL_L1_CH0 - Tx FIFO full signal for Tx channel 0. + INFIFO_FULL_L1_CH4 + Tx FIFO full signal for Tx channel 1. 6 1 read-only - INFIFO_EMPTY_L1_CH0 - Tx FIFO empty signal for Tx channel 0. + INFIFO_EMPTY_L1_CH4 + Tx FIFO empty signal for Tx channel 1. 7 1 read-only - INFIFO_CNT_L1_CH0 - The register stores the byte number of the data in Tx FIFO for Tx channel 0. + INFIFO_CNT_L1_CH4 + The register stores the byte number of the data in Tx FIFO for Tx channel 1. 8 5 read-only - INFIFO_FULL_L3_CH0 - Tx FIFO full signal for Tx channel 0. + INFIFO_FULL_L3_CH4 + Tx FIFO full signal for Tx channel 1. 16 1 read-only - INFIFO_EMPTY_L3_CH0 - Tx FIFO empty signal for Tx channel 0. + INFIFO_EMPTY_L3_CH4 + Tx FIFO empty signal for Tx channel 1. 17 1 read-only - INFIFO_CNT_L3_CH0 - The register stores the 8byte number of the data in Tx FIFO for Tx channel 0. + INFIFO_CNT_L3_CH4 + The register stores the byte number of the data in Tx FIFO for Tx channel 1. 18 2 read-only @@ -52318,21 +50501,21 @@ - IN_POP_CH0 - RX CH0 INFIFO pop register - 0x518 + IN_POP_CH4 + RX CH4 INFIFO pop register + 0x918 0x20 0x00000400 - INFIFO_RDATA_CH0 + INFIFO_RDATA_CH4 This register stores the data popping from DMA Rx FIFO. 0 11 read-only - INFIFO_POP_CH0 + INFIFO_POP_CH4 Set this bit to pop data from DMA Rx FIFO. 11 1 @@ -52341,42 +50524,42 @@ - IN_LINK_CONF_CH0 - RX CH0 in_link dscr ctrl register - 0x51C + IN_LINK_CONF_CH4 + RX CH4 in_link dscr ctrl register + 0x91C 0x20 0x01100000 - INLINK_AUTO_RET_CH0 + INLINK_AUTO_RET_CH4 Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data. 20 1 read-write - INLINK_STOP_CH0 + INLINK_STOP_CH4 Set this bit to stop dealing with the inlink descriptors. 21 1 read-write - INLINK_START_CH0 + INLINK_START_CH4 Set this bit to start dealing with the inlink descriptors. 22 1 read-write - INLINK_RESTART_CH0 + INLINK_RESTART_CH4 Set this bit to mount a new inlink descriptor. 23 1 read-write - INLINK_PARK_CH0 + INLINK_PARK_CH4 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working. 24 1 @@ -52385,13 +50568,13 @@ - IN_LINK_ADDR_CH0 - RX CH0 in_link dscr addr register - 0x520 + IN_LINK_ADDR_CH4 + RX CH4 in_link dscr addr register + 0x920 0x20 - INLINK_ADDR_CH0 + INLINK_ADDR_CH4 This register stores the first inlink descriptor's address. 0 32 @@ -52400,35 +50583,35 @@ - IN_STATE_CH0 - RX CH0 state register - 0x524 + IN_STATE_CH4 + RX CH4 state register + 0x924 0x20 0x00800000 - INLINK_DSCR_ADDR_CH0 + INLINK_DSCR_ADDR_CH4 This register stores the current inlink descriptor's address. 0 18 read-only - IN_DSCR_STATE_CH0 + IN_DSCR_STATE_CH4 This register stores the current descriptor state machine state. 18 2 read-only - IN_STATE_CH0 + IN_STATE_CH4 This register stores the current control module state machine state. 20 3 read-only - IN_RESET_AVAIL_CH0 + IN_RESET_AVAIL_CH4 This register indicate that if the channel reset is safety. 23 1 @@ -52437,13 +50620,13 @@ - IN_SUC_EOF_DES_ADDR_CH0 - RX CH0 eof des addr register - 0x528 + IN_SUC_EOF_DES_ADDR_CH4 + RX CH4 eof des addr register + 0x928 0x20 - IN_SUC_EOF_DES_ADDR_CH0 + IN_SUC_EOF_DES_ADDR_CH4 This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. 0 32 @@ -52452,13 +50635,13 @@ - IN_ERR_EOF_DES_ADDR_CH0 - RX CH0 err eof des addr register - 0x52C + IN_ERR_EOF_DES_ADDR_CH4 + RX CH4 err eof des addr register + 0x92C 0x20 - IN_ERR_EOF_DES_ADDR_CH0 + IN_ERR_EOF_DES_ADDR_CH4 This register stores the address of the inlink descriptor when there are some errors in current receiving data. 0 32 @@ -52467,13 +50650,13 @@ - IN_DSCR_CH0 - RX CH0 next dscr addr register - 0x530 + IN_DSCR_CH4 + RX CH4 next dscr addr register + 0x930 0x20 - INLINK_DSCR_CH0 + INLINK_DSCR_CH4 The address of the next inlink descriptor address x. 0 32 @@ -52482,13 +50665,13 @@ - IN_DSCR_BF0_CH0 - RX CH0 last dscr addr register - 0x534 + IN_DSCR_BF0_CH4 + RX CH4 last dscr addr register + 0x934 0x20 - INLINK_DSCR_BF0_CH0 + INLINK_DSCR_BF0_CH4 The address of the last inlink descriptor's next address x-1. 0 32 @@ -52497,13 +50680,13 @@ - IN_DSCR_BF1_CH0 - RX CH0 second-to-last dscr addr register - 0x538 + IN_DSCR_BF1_CH4 + RX CH4 second-to-last dscr addr register + 0x938 0x20 - INLINK_DSCR_BF1_CH0 + INLINK_DSCR_BF1_CH4 The address of the second-to-last inlink descriptor's next address x-2. 0 32 @@ -52512,28 +50695,28 @@ - IN_ARB_CH0 - RX CH0 arb register - 0x540 + IN_ARB_CH4 + RX CH4 arb register + 0x940 0x20 0x00000051 - IN_ARB_TOKEN_NUM_CH0 + IN_ARB_TOKEN_NUM_CH4 Set the max number of token count of arbiter 0 4 read-write - EXTER_IN_ARB_PRIORITY_CH0 + EXTER_IN_ARB_PRIORITY_CH4 Set the priority of channel 4 2 read-write - INTER_IN_ARB_PRIORITY_CH0 + INTER_IN_ARB_PRIORITY_CH4 Set the priority of channel 6 3 @@ -52542,43 +50725,28 @@ - IN_RO_PD_CONF_CH0 - RX CH0 reorder power config register - 0x548 - 0x20 - - - IN_RO_RAM_CLK_FO_CH0 - 1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA. 0: A gate-clock will be used when accessing the RAM in DMA. - 6 - 1 - read-write - - - - - IN_ETM_CONF_CH0 - RX CH0 ETM config register - 0x56C + IN_ETM_CONF_CH4 + RX CH4 ETM config register + 0x948 0x20 0x00000004 - IN_ETM_EN_CH0 + IN_ETM_EN_CH4 Set this bit to 1 to enable ETM task function 0 1 read-write - IN_ETM_LOOP_EN_CH0 + IN_ETM_LOOP_EN_CH4 when this bit is 1, dscr can be processed after receiving a task 1 1 read-write - IN_DSCR_TASK_MAK_CH0 + IN_DSCR_TASK_MAK_CH4 ETM dscr_ready maximum cache numbers 2 2 @@ -52587,13 +50755,13 @@ - IN_FIFO_CNT_CH0 - rx CH0 fifo cnt register - 0x580 + IN_FIFO_CNT_CH4 + rx CH4 fifo cnt register + 0x980 0x20 - IN_CMDFIFO_INFIFO_CNT_CH0 + IN_CMDFIFO_INFIFO_CNT_CH4 only for debug 0 10 @@ -52602,14 +50770,14 @@ - IN_POP_DATA_CNT_CH0 - rx CH0 pop data cnt register - 0x584 + IN_POP_DATA_CNT_CH4 + rx CH4 pop data cnt register + 0x984 0x20 0x00000007 - IN_CMDFIFO_POP_DATA_CNT_CH0 + IN_CMDFIFO_POP_DATA_CNT_CH4 only for debug 0 8 @@ -52618,13 +50786,13 @@ - IN_XADDR_CH0 - rx CH0 xaddr register - 0x588 + IN_XADDR_CH4 + rx CH4 xaddr register + 0x988 0x20 - IN_CMDFIFO_XADDR_CH0 + IN_CMDFIFO_XADDR_CH4 only for debug 0 32 @@ -52633,13 +50801,13 @@ - IN_BUF_HB_RCV_CH0 - rx CH0 buf len hb rcv register - 0x58C + IN_BUF_HB_RCV_CH4 + rx CH4 buf len hb rcv register + 0x98C 0x20 - IN_CMDFIFO_BUF_HB_RCV_CH0 + IN_CMDFIFO_BUF_HB_RCV_CH4 only for debug 0 29 @@ -52648,469 +50816,327 @@ - IN_CONF0_CH1 - RX CH1 config0 register - 0x600 + IN_CONF0_CH5 + RX CH5 config0 register + 0xA00 0x20 - INDSCR_BURST_EN_CH1 - Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor when accessing SRAM. - 2 - 1 - read-write - - - IN_ECC_AES_EN_CH1 + IN_ECC_AES_EN_CH5 When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned. 3 1 read-write - IN_CHECK_OWNER_CH1 - Set this bit to enable checking the owner attribute of the link descriptor. - 4 - 1 - read-write - - - IN_MEM_BURST_LENGTH_CH1 + IN_MEM_BURST_LENGTH_CH5 Block size of Rx channel 1. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes 6 3 read-write - IN_PAGE_BOUND_EN_CH1 + IN_PAGE_BOUND_EN_CH5 Set this bit to 1 to make sure AXI write data don't cross the address boundary which define by mem_burst_length 12 1 read-write - IN_RST_CH1 + IN_RST_CH5 Write 1 then write 0 to this bit to reset Rx channel 24 1 read-write - IN_CMD_DISABLE_CH1 + IN_CMD_DISABLE_CH5 Write 1 before reset and write 0 after reset 25 1 read-write + + + + IN_CONF1_CH5 + RX CH5 config1 register + 0xA04 + 0x20 + - IN_ARB_WEIGHT_OPT_DIS_CH1 - Set this bit to 1 to disable arbiter optimum weight function. - 26 - 1 + BLOCK_START_ADDR_CH5 + RX Channel 5 destination start address + 0 + 32 read-write - IN_INT_RAW_CH1 - RX CH1 interrupt raw register - 0x604 + IN_CONF2_CH5 + RX CH5 config2 register + 0xA08 0x20 + 0x3C007800 - IN_DONE_CH1_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been transmitted to peripherals for Rx channel 1. + BLOCK_ROW_LENGTH_12LINE_CH5 + The number of bytes contained in a row block 12line in RX channel 5 0 - 1 + 16 read-write - IN_SUC_EOF_CH1_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1. - 1 - 1 + BLOCK_ROW_LENGTH_4LINE_CH5 + The number of bytes contained in a row block 4line in RX channel 5 + 16 + 16 read-write + + + + IN_CONF3_CH5 + RX CH5 config3 register + 0xA0C + 0x20 + 0x00200100 + - IN_ERR_EOF_CH1_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and data error is detected - 2 - 1 + BLOCK_LENGTH_12LINE_CH5 + The number of bytes contained in a block 12line + 0 + 14 read-write - IN_DSCR_ERR_CH1_INT_RAW - The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 1. - 3 - 1 + BLOCK_LENGTH_4LINE_CH5 + The number of bytes contained in a block 4line + 14 + 14 read-write + + + + IN_INT_RAW_CH5 + RX CH5 interrupt raw register + 0xA10 + 0x20 + - INFIFO_OVF_L1_CH1_INT_RAW - This raw interrupt bit turns to high level when fifo of Rx channel is overflow. - 4 + IN_DONE_CH5_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been transmitted to peripherals for Rx channel 1. + 0 1 read-write - INFIFO_UDF_L1_CH1_INT_RAW - This raw interrupt bit turns to high level when fifo of Rx channel is underflow. - 5 + IN_SUC_EOF_CH5_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1. + 1 1 read-write - INFIFO_OVF_L2_CH1_INT_RAW + INFIFO_OVF_L1_CH5_INT_RAW This raw interrupt bit turns to high level when fifo of Rx channel is overflow. - 6 + 2 1 read-write - INFIFO_UDF_L2_CH1_INT_RAW + INFIFO_UDF_L1_CH5_INT_RAW This raw interrupt bit turns to high level when fifo of Rx channel is underflow. - 7 - 1 - read-write - - - IN_DSCR_EMPTY_CH1_INT_RAW - The raw interrupt bit turns to high level when the last descriptor is done but fifo also remain data. - 8 + 3 1 read-write - IN_DSCR_TASK_OVF_CH1_INT_RAW - The raw interrupt bit turns to high level when dscr ready task fifo is overflow. - 9 + FETCH_MB_COL_CNT_OVF_CH5_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is underflow. + 4 1 read-write - IN_INT_ENA_CH1 - RX CH1 interrupt ena register - 0x608 + IN_INT_ENA_CH5 + RX CH5 interrupt ena register + 0xA14 0x20 - IN_DONE_CH1_INT_ENA + IN_DONE_CH5_INT_ENA The interrupt enable bit for the IN_DONE_CH_INT interrupt. 0 1 read-write - IN_SUC_EOF_CH1_INT_ENA + IN_SUC_EOF_CH5_INT_ENA The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. 1 1 read-write - IN_ERR_EOF_CH1_INT_ENA - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + INFIFO_OVF_L1_CH5_INT_ENA + The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. 2 1 read-write - IN_DSCR_ERR_CH1_INT_ENA - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + INFIFO_UDF_L1_CH5_INT_ENA + The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. 3 1 read-write - INFIFO_OVF_L1_CH1_INT_ENA - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. - 4 - 1 - read-write - - - INFIFO_UDF_L1_CH1_INT_ENA + FETCH_MB_COL_CNT_OVF_CH5_INT_ENA The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. - 5 - 1 - read-write - - - INFIFO_OVF_L2_CH1_INT_ENA - The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. - 6 - 1 - read-write - - - INFIFO_UDF_L2_CH1_INT_ENA - The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. - 7 - 1 - read-write - - - IN_DSCR_EMPTY_CH1_INT_ENA - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. - 8 - 1 - read-write - - - IN_DSCR_TASK_OVF_CH1_INT_ENA - The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. - 9 + 4 1 read-write - IN_INT_ST_CH1 - RX CH1 interrupt st register - 0x60C + IN_INT_ST_CH5 + RX CH5 interrupt st register + 0xA18 0x20 - IN_DONE_CH1_INT_ST + IN_DONE_CH5_INT_ST The raw interrupt status bit for the IN_DONE_CH_INT interrupt. 0 1 read-only - IN_SUC_EOF_CH1_INT_ST + IN_SUC_EOF_CH5_INT_ST The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. 1 1 read-only - IN_ERR_EOF_CH1_INT_ST - The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + INFIFO_OVF_L1_CH5_INT_ST + The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. 2 1 read-only - IN_DSCR_ERR_CH1_INT_ST - The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + INFIFO_UDF_L1_CH5_INT_ST + The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. 3 1 read-only - INFIFO_OVF_L1_CH1_INT_ST - The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. - 4 - 1 - read-only - - - INFIFO_UDF_L1_CH1_INT_ST + FETCH_MB_COL_CNT_OVF_CH5_INT_ST The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. - 5 - 1 - read-only - - - INFIFO_OVF_L2_CH1_INT_ST - The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. - 6 - 1 - read-only - - - INFIFO_UDF_L2_CH1_INT_ST - The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. - 7 - 1 - read-only - - - IN_DSCR_EMPTY_CH1_INT_ST - The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. - 8 - 1 - read-only - - - IN_DSCR_TASK_OVF_CH1_INT_ST - The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. - 9 + 4 1 read-only - IN_INT_CLR_CH1 - RX CH1 interrupt clr register - 0x610 + IN_INT_CLR_CH5 + RX CH5 interrupt clr register + 0xA1C 0x20 - IN_DONE_CH1_INT_CLR + IN_DONE_CH5_INT_CLR Set this bit to clear the IN_DONE_CH_INT interrupt. 0 1 write-only - IN_SUC_EOF_CH1_INT_CLR + IN_SUC_EOF_CH5_INT_CLR Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. 1 1 write-only - IN_ERR_EOF_CH1_INT_CLR - Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + INFIFO_OVF_L1_CH5_INT_CLR + Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. 2 1 write-only - IN_DSCR_ERR_CH1_INT_CLR - Set this bit to clear the INDSCR_ERR_CH_INT interrupt. + INFIFO_UDF_L1_CH5_INT_CLR + Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. 3 1 write-only - INFIFO_OVF_L1_CH1_INT_CLR - Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. - 4 - 1 - write-only - - - INFIFO_UDF_L1_CH1_INT_CLR + FETCH_MB_COL_CNT_OVF_CH5_INT_CLR Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. - 5 - 1 - write-only - - - INFIFO_OVF_L2_CH1_INT_CLR - Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. - 6 - 1 - write-only - - - INFIFO_UDF_L2_CH1_INT_CLR - Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. - 7 - 1 - write-only - - - IN_DSCR_EMPTY_CH1_INT_CLR - Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. - 8 - 1 - write-only - - - IN_DSCR_TASK_OVF_CH1_INT_CLR - Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt. - 9 + 4 1 write-only - INFIFO_STATUS_CH1 - RX CH1 INFIFO status register - 0x614 + INFIFO_STATUS_CH5 + RX CH5 INFIFO status register + 0xA20 0x20 - 0x00020082 + 0x00000002 - INFIFO_FULL_L2_CH1 - Rx FIFO full signal for Rx channel. - 0 - 1 - read-only - - - INFIFO_EMPTY_L2_CH1 - Rx FIFO empty signal for Rx channel. - 1 - 1 - read-only - - - INFIFO_CNT_L2_CH1 - The register stores the byte number of the data in Rx FIFO for Rx channel. - 2 - 4 - read-only - - - INFIFO_FULL_L1_CH1 + INFIFO_FULL_L1_CH5 Tx FIFO full signal for Tx channel 1. - 6 + 0 1 read-only - INFIFO_EMPTY_L1_CH1 + INFIFO_EMPTY_L1_CH5 Tx FIFO empty signal for Tx channel 1. - 7 + 1 1 read-only - INFIFO_CNT_L1_CH1 + INFIFO_CNT_L1_CH5 The register stores the byte number of the data in Tx FIFO for Tx channel 1. - 8 + 2 5 read-only - - INFIFO_FULL_L3_CH1 - Tx FIFO full signal for Tx channel 1. - 16 - 1 - read-only - - - INFIFO_EMPTY_L3_CH1 - Tx FIFO empty signal for Tx channel 1. - 17 - 1 - read-only - - - INFIFO_CNT_L3_CH1 - The register stores the byte number of the data in Tx FIFO for Tx channel 1. - 18 - 2 - read-only - - IN_POP_CH1 - RX CH1 INFIFO pop register - 0x618 + IN_POP_CH5 + RX CH5 INFIFO pop register + 0xA24 0x20 0x00000400 - INFIFO_RDATA_CH1 + INFIFO_RDATA_CH5 This register stores the data popping from DMA Rx FIFO. 0 11 read-only - INFIFO_POP_CH1 + INFIFO_POP_CH5 Set this bit to pop data from DMA Rx FIFO. 11 1 @@ -53119,140 +51145,91 @@ - IN_LINK_CONF_CH1 - RX CH1 in_link dscr ctrl register - 0x61C + IN_STATE_CH5 + RX CH5 state register + 0xA28 0x20 - 0x01100000 + 0x00000008 - INLINK_AUTO_RET_CH1 - Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data. - 20 - 1 - read-write - - - INLINK_STOP_CH1 - Set this bit to stop dealing with the inlink descriptors. - 21 - 1 - read-write - - - INLINK_START_CH1 - Set this bit to start dealing with the inlink descriptors. - 22 - 1 - read-write - - - INLINK_RESTART_CH1 - Set this bit to mount a new inlink descriptor. - 23 - 1 - read-write + IN_STATE_CH5 + This register stores the current control module state machine state. + 0 + 3 + read-only - INLINK_PARK_CH1 - 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working. - 24 + IN_RESET_AVAIL_CH5 + This register indicate that if the channel reset is safety. + 3 1 read-only - IN_LINK_ADDR_CH1 - RX CH1 in_link dscr addr register - 0x620 + IN_ARB_CH5 + RX CH5 arb register + 0xA40 0x20 + 0x00000041 - INLINK_ADDR_CH1 - This register stores the first inlink descriptor's address. + IN_ARB_TOKEN_NUM_CH5 + Set the max number of token count of arbiter 0 - 32 + 4 read-write - - - - IN_STATE_CH1 - RX CH1 state register - 0x624 - 0x20 - 0x00800000 - - - INLINK_DSCR_ADDR_CH1 - This register stores the current inlink descriptor's address. - 0 - 18 - read-only - - - IN_DSCR_STATE_CH1 - This register stores the current descriptor state machine state. - 18 - 2 - read-only - - IN_STATE_CH1 - This register stores the current control module state machine state. - 20 + INTER_IN_ARB_PRIORITY_CH5 + Set the priority of channel + 6 3 - read-only - - - IN_RESET_AVAIL_CH1 - This register indicate that if the channel reset is safety. - 23 - 1 - read-only + read-write - IN_SUC_EOF_DES_ADDR_CH1 - RX CH1 eof des addr register - 0x628 + IN_FIFO_CNT_CH5 + rx CH5 fifo cnt register + 0xA80 0x20 - IN_SUC_EOF_DES_ADDR_CH1 - This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. + IN_CMDFIFO_INFIFO_CNT_CH5 + only for debug 0 - 32 + 10 read-only - IN_ERR_EOF_DES_ADDR_CH1 - RX CH1 err eof des addr register - 0x62C + IN_POP_DATA_CNT_CH5 + rx CH5 pop data cnt register + 0xA84 0x20 + 0x000000FF - IN_ERR_EOF_DES_ADDR_CH1 - This register stores the address of the inlink descriptor when there are some errors in current receiving data. + IN_CMDFIFO_POP_DATA_CNT_CH5 + only for debug 0 - 32 + 8 read-only - IN_DSCR_CH1 - RX CH1 next dscr addr register - 0x630 + IN_XADDR_CH5 + rx CH5 xaddr register + 0xA88 0x20 - INLINK_DSCR_CH1 - The address of the next inlink descriptor address x. + IN_CMDFIFO_XADDR_CH5 + only for debug 0 32 read-only @@ -53260,777 +51237,1140 @@ - IN_DSCR_BF0_CH1 - RX CH1 last dscr addr register - 0x634 + IN_BUF_HB_RCV_CH5 + rx CH5 buf len hb rcv register + 0xA8C 0x20 - INLINK_DSCR_BF0_CH1 - The address of the last inlink descriptor's next address x-1. + IN_CMDFIFO_BUF_HB_RCV_CH5 + only for debug 0 - 32 + 29 read-only - IN_DSCR_BF1_CH1 - RX CH1 second-to-last dscr addr register - 0x638 + INTER_AXI_ERR + inter memory axi err register + 0xB00 0x20 - INLINK_DSCR_BF1_CH1 - The address of the second-to-last inlink descriptor's next address x-2. + INTER_RID_ERR_CNT + AXI read id err cnt 0 - 32 + 4 + read-only + + + INTER_RRESP_ERR_CNT + AXI read resp err cnt + 4 + 4 + read-only + + + INTER_WRESP_ERR_CNT + AXI write resp err cnt + 8 + 4 + read-only + + + INTER_RD_FIFO_CNT + AXI read cmd fifo remain cmd count + 12 + 3 + read-only + + + INTER_RD_BAK_FIFO_CNT + AXI read backup cmd fifo remain cmd count + 15 + 4 + read-only + + + INTER_WR_FIFO_CNT + AXI write cmd fifo remain cmd count + 19 + 3 + read-only + + + INTER_WR_BAK_FIFO_CNT + AXI write backup cmd fifo remain cmd count + 22 + 4 read-only - IN_ARB_CH1 - RX CH1 arb register - 0x640 + EXTER_AXI_ERR + exter memory axi err register + 0xB04 0x20 - 0x00000051 - IN_ARB_TOKEN_NUM_CH1 - Set the max number of token count of arbiter + EXTER_RID_ERR_CNT + AXI read id err cnt 0 4 - read-write + read-only - EXTER_IN_ARB_PRIORITY_CH1 - Set the priority of channel + EXTER_RRESP_ERR_CNT + AXI read resp err cnt 4 - 2 - read-write + 4 + read-only - INTER_IN_ARB_PRIORITY_CH1 - Set the priority of channel - 6 + EXTER_WRESP_ERR_CNT + AXI write resp err cnt + 8 + 4 + read-only + + + EXTER_RD_FIFO_CNT + AXI read cmd fifo remain cmd count + 12 3 - read-write + read-only + + + EXTER_RD_BAK_FIFO_CNT + AXI read backup cmd fifo remain cmd count + 15 + 4 + read-only + + + EXTER_WR_FIFO_CNT + AXI write cmd fifo remain cmd count + 19 + 3 + read-only + + + EXTER_WR_BAK_FIFO_CNT + AXI write backup cmd fifo remain cmd count + 22 + 4 + read-only - IN_ETM_CONF_CH1 - RX CH1 ETM config register - 0x648 + RST_CONF + axi reset config register + 0xB08 0x20 - 0x00000004 - IN_ETM_EN_CH1 - Set this bit to 1 to enable ETM task function + INTER_AXIM_RD_RST + Write 1 then write 0 to this bit to reset axi master read data FIFO. 0 1 read-write - IN_ETM_LOOP_EN_CH1 - when this bit is 1, dscr can be processed after receiving a task + INTER_AXIM_WR_RST + Write 1 then write 0 to this bit to reset axi master write data FIFO. 1 1 read-write - IN_DSCR_TASK_MAK_CH1 - ETM dscr_ready maximum cache numbers + EXTER_AXIM_RD_RST + Write 1 then write 0 to this bit to reset axi master read data FIFO. 2 - 2 + 1 + read-write + + + EXTER_AXIM_WR_RST + Write 1 then write 0 to this bit to reset axi master write data FIFO. + 3 + 1 + read-write + + + CLK_EN + 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers. + 4 + 1 read-write - IN_FIFO_CNT_CH1 - rx CH1 fifo cnt register - 0x680 + INTER_MEM_START_ADDR0 + Start address of inter memory range0 register + 0xB0C 0x20 + 0x30100000 - IN_CMDFIFO_INFIFO_CNT_CH1 - only for debug + ACCESS_INTER_MEM_START_ADDR0 + The start address of accessible address space. 0 - 10 - read-only + 32 + read-write - IN_POP_DATA_CNT_CH1 - rx CH1 pop data cnt register - 0x684 + INTER_MEM_END_ADDR0 + end address of inter memory range0 register + 0xB10 0x20 - 0x00000007 + 0x8FFFFFFF - IN_CMDFIFO_POP_DATA_CNT_CH1 - only for debug + ACCESS_INTER_MEM_END_ADDR0 + The end address of accessible address space. The access address beyond this range would lead to descriptor error. 0 - 8 - read-only + 32 + read-write - IN_XADDR_CH1 - rx CH1 xaddr register - 0x688 + INTER_MEM_START_ADDR1 + Start address of inter memory range1 register + 0xB14 0x20 + 0x30100000 - IN_CMDFIFO_XADDR_CH1 - only for debug + ACCESS_INTER_MEM_START_ADDR1 + The start address of accessible address space. 0 32 - read-only + read-write - IN_BUF_HB_RCV_CH1 - rx CH1 buf len hb rcv register - 0x68C + INTER_MEM_END_ADDR1 + end address of inter memory range1 register + 0xB18 0x20 + 0x8FFFFFFF - IN_CMDFIFO_BUF_HB_RCV_CH1 - only for debug + ACCESS_INTER_MEM_END_ADDR1 + The end address of accessible address space. The access address beyond this range would lead to descriptor error. 0 - 29 - read-only + 32 + read-write - IN_CONF0_CH2 - RX CH2 config0 register - 0x700 + EXTER_MEM_START_ADDR0 + Start address of exter memory range0 register + 0xB20 0x20 + 0x30100000 - INDSCR_BURST_EN_CH2 - Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor when accessing SRAM. - 2 - 1 - read-write - - - IN_ECC_AES_EN_CH2 - When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned. - 3 - 1 - read-write - - - IN_CHECK_OWNER_CH2 - Set this bit to enable checking the owner attribute of the link descriptor. - 4 - 1 + ACCESS_EXTER_MEM_START_ADDR0 + The start address of accessible address space. + 0 + 32 read-write + + + + EXTER_MEM_END_ADDR0 + end address of exter memory range0 register + 0xB24 + 0x20 + 0x8FFFFFFF + - IN_MEM_BURST_LENGTH_CH2 - Block size of Rx channel 2. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes - 6 - 3 + ACCESS_EXTER_MEM_END_ADDR0 + The end address of accessible address space. The access address beyond this range would lead to descriptor error. + 0 + 32 read-write + + + + EXTER_MEM_START_ADDR1 + Start address of exter memory range1 register + 0xB28 + 0x20 + 0x30100000 + - IN_PAGE_BOUND_EN_CH2 - Set this bit to 1 to make sure AXI write data don't cross the address boundary which define by mem_burst_length - 12 - 1 + ACCESS_EXTER_MEM_START_ADDR1 + The start address of accessible address space. + 0 + 32 read-write + + + + EXTER_MEM_END_ADDR1 + end address of exter memory range1 register + 0xB2C + 0x20 + 0x8FFFFFFF + - IN_RST_CH2 - Write 1 then write 0 to this bit to reset Rx channel - 24 - 1 + ACCESS_EXTER_MEM_END_ADDR1 + The end address of accessible address space. The access address beyond this range would lead to descriptor error. + 0 + 32 read-write + + + + OUT_ARB_CONFIG + reserved + 0xB30 + 0x20 + - IN_CMD_DISABLE_CH2 - Write 1 before reset and write 0 after reset - 25 - 1 + OUT_ARB_TIMEOUT_NUM + Set the max number of timeout count of arbiter + 0 + 16 read-write - IN_ARB_WEIGHT_OPT_DIS_CH2 - Set this bit to 1 to disable arbiter optimum weight function. - 26 + OUT_WEIGHT_EN + reserved + 16 1 read-write - IN_INT_RAW_CH2 - RX CH2 interrupt raw register - 0x704 + IN_ARB_CONFIG + reserved + 0xB34 0x20 - IN_DONE_CH2_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been transmitted to peripherals for Rx channel 1. + IN_ARB_TIMEOUT_NUM + Set the max number of timeout count of arbiter 0 - 1 - read-write - - - IN_SUC_EOF_CH2_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1. - 1 - 1 + 16 read-write - IN_ERR_EOF_CH2_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and data error is detected - 2 + IN_WEIGHT_EN + reserved + 16 1 read-write + + + + DATE + reserved + 0xB3C + 0x20 + 0x20230403 + - IN_DSCR_ERR_CH2_INT_RAW - The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 1. - 3 - 1 + DATE + register version. + 0 + 32 read-write + + + + COUNTER_RST + counter reset register + 0xB50 + 0x20 + - INFIFO_OVF_L1_CH2_INT_RAW - This raw interrupt bit turns to high level when fifo of Rx channel is overflow. - 4 + RX_CH0_EXTER_COUNTER_RST + Write 1 then write 0 to this bit to reset rx ch0 counter. + 0 1 read-write - INFIFO_UDF_L1_CH2_INT_RAW - This raw interrupt bit turns to high level when fifo of Rx channel is underflow. - 5 + RX_CH1_EXTER_COUNTER_RST + Write 1 then write 0 to this bit to reset rx ch1 counter. + 1 1 read-write - INFIFO_OVF_L2_CH2_INT_RAW - This raw interrupt bit turns to high level when fifo of Rx channel is overflow. - 6 + RX_CH2_INTER_COUNTER_RST + Write 1 then write 0 to this bit to reset rx ch2 counter. + 2 1 read-write - INFIFO_UDF_L2_CH2_INT_RAW - This raw interrupt bit turns to high level when fifo of Rx channel is underflow. - 7 + RX_CH5_INTER_COUNTER_RST + Write 1 then write 0 to this bit to reset rx ch5 counter. + 3 1 read-write + + + + RX_CH0_COUNTER + rx ch0 counter register + 0xB54 + 0x20 + - IN_DSCR_EMPTY_CH2_INT_RAW - The raw interrupt bit turns to high level when the last descriptor is done but fifo also remain data. - 8 - 1 - read-write + RX_CH0_CNT + rx ch0 counter register + 0 + 23 + read-only + + + + RX_CH1_COUNTER + rx ch1 counter register + 0xB58 + 0x20 + - IN_DSCR_TASK_OVF_CH2_INT_RAW - The raw interrupt bit turns to high level when dscr ready task fifo is overflow. - 9 - 1 - read-write + RX_CH1_CNT + rx ch1 counter register + 0 + 21 + read-only - IN_INT_ENA_CH2 - RX CH2 interrupt ena register - 0x708 + RX_CH2_COUNTER + rx ch2 counter register + 0xB5C 0x20 - IN_DONE_CH2_INT_ENA - The interrupt enable bit for the IN_DONE_CH_INT interrupt. + RX_CH2_CNT + rx ch2 counter register 0 - 1 - read-write - - - IN_SUC_EOF_CH2_INT_ENA - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. - 1 - 1 - read-write - - - IN_ERR_EOF_CH2_INT_ENA - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. - 2 - 1 - read-write - - - IN_DSCR_ERR_CH2_INT_ENA - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. - 3 - 1 - read-write - - - INFIFO_OVF_L1_CH2_INT_ENA - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. - 4 - 1 - read-write - - - INFIFO_UDF_L1_CH2_INT_ENA - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. - 5 - 1 - read-write + 11 + read-only + + + + RX_CH5_COUNTER + rx ch5 counter register + 0xB60 + 0x20 + - INFIFO_OVF_L2_CH2_INT_ENA - The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. - 6 - 1 - read-write + RX_CH5_CNT + rx ch5 counter register + 0 + 17 + read-only + + + + + + HMAC + HMAC (Hash-based Message Authentication Code) Accelerator + HMAC + 0x50095000 + + 0x0 + 0xA4 + registers + + + + SET_START + Process control register 0. + 0x40 + 0x20 + - INFIFO_UDF_L2_CH2_INT_ENA - The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. - 7 + SET_START + Start hmac operation. + 0 1 - read-write + write-only + + + + SET_PARA_PURPOSE + Configure purpose. + 0x44 + 0x20 + - IN_DSCR_EMPTY_CH2_INT_ENA - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. - 8 - 1 - read-write + PURPOSE_SET + Set hmac parameter purpose. + 0 + 4 + write-only + + + + SET_PARA_KEY + Configure key. + 0x48 + 0x20 + - IN_DSCR_TASK_OVF_CH2_INT_ENA - The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. - 9 - 1 - read-write + KEY_SET + Set hmac parameter key. + 0 + 3 + write-only - IN_INT_ST_CH2 - RX CH2 interrupt st register - 0x70C + SET_PARA_FINISH + Finish initial configuration. + 0x4C 0x20 - IN_DONE_CH2_INT_ST - The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + SET_PARA_END + Finish hmac configuration. 0 1 - read-only + write-only + + + + SET_MESSAGE_ONE + Process control register 1. + 0x50 + 0x20 + - IN_SUC_EOF_CH2_INT_ST - The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. - 1 + SET_TEXT_ONE + Call SHA to calculate one message block. + 0 1 - read-only + write-only + + + + SET_MESSAGE_ING + Process control register 2. + 0x54 + 0x20 + - IN_ERR_EOF_CH2_INT_ST - The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. - 2 + SET_TEXT_ING + Continue typical hmac. + 0 1 - read-only + write-only + + + + SET_MESSAGE_END + Process control register 3. + 0x58 + 0x20 + - IN_DSCR_ERR_CH2_INT_ST - The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. - 3 + SET_TEXT_END + Start hardware padding. + 0 1 - read-only + write-only + + + + SET_RESULT_FINISH + Process control register 4. + 0x5C + 0x20 + - INFIFO_OVF_L1_CH2_INT_ST - The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. - 4 + SET_RESULT_END + After read result from upstream, then let hmac back to idle. + 0 1 - read-only + write-only + + + + SET_INVALIDATE_JTAG + Invalidate register 0. + 0x60 + 0x20 + - INFIFO_UDF_L1_CH2_INT_ST - The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. - 5 + SET_INVALIDATE_JTAG + Clear result from hmac downstream JTAG. + 0 1 - read-only + write-only + + + + SET_INVALIDATE_DS + Invalidate register 1. + 0x64 + 0x20 + - INFIFO_OVF_L2_CH2_INT_ST - The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. - 6 + SET_INVALIDATE_DS + Clear result from hmac downstream DS. + 0 1 - read-only + write-only + + + + QUERY_ERROR + Error register. + 0x68 + 0x20 + - INFIFO_UDF_L2_CH2_INT_ST - The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. - 7 + QUERY_CHECK + Hmac configuration state. 0: key are agree with purpose. 1: error + 0 1 read-only + + + + QUERY_BUSY + Busy register. + 0x6C + 0x20 + - IN_DSCR_EMPTY_CH2_INT_ST - The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. - 8 + BUSY_STATE + Hmac state. 1'b0: idle. 1'b1: busy + 0 1 read-only + + + + 16 + 0x4 + WR_MESSAGE_MEM[%s] + Message block memory. + 0x80 + 0x20 + + + 8 + 0x4 + RD_RESULT_MEM[%s] + Result from upstream. + 0xC0 + 0x20 + + + SET_MESSAGE_PAD + Process control register 5. + 0xF0 + 0x20 + - IN_DSCR_TASK_OVF_CH2_INT_ST - The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. - 9 + SET_TEXT_PAD + Start software padding. + 0 1 - read-only + write-only - IN_INT_CLR_CH2 - RX CH2 interrupt clr register - 0x710 + ONE_BLOCK + Process control register 6. + 0xF4 0x20 - IN_DONE_CH2_INT_CLR - Set this bit to clear the IN_DONE_CH_INT interrupt. + SET_ONE_BLOCK + Don't have to do padding. 0 1 write-only + + + + SOFT_JTAG_CTRL + Jtag register 0. + 0xF8 + 0x20 + - IN_SUC_EOF_CH2_INT_CLR - Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. - 1 + SOFT_JTAG_CTRL + Turn on JTAG verification. + 0 1 write-only + + + + WR_JTAG + Jtag register 1. + 0xFC + 0x20 + - IN_ERR_EOF_CH2_INT_CLR - Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. - 2 - 1 + WR_JTAG + 32-bit of key to be compared. + 0 + 32 write-only + + + + DATE + Date register. + 0x1FC + 0x20 + 0x20200618 + - IN_DSCR_ERR_CH2_INT_CLR - Set this bit to clear the INDSCR_ERR_CH_INT interrupt. - 3 - 1 - write-only + DATE + Hmac date information/ hmac version information. + 0 + 30 + read-write + + + + + + HP_SYS + High-Power System + HP_SYS + 0x500E5000 + + 0x0 + 0x16C + registers + + + HP_SYS + 110 + + + + VER_DATE + NA + 0x0 + 0x20 + 0x20230519 + - INFIFO_OVF_L1_CH2_INT_CLR - Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. - 4 - 1 - write-only + REG_VER_DATE + NA + 0 + 32 + read-write + + + + CLK_EN + NA + 0x4 + 0x20 + - INFIFO_UDF_L1_CH2_INT_CLR - Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. - 5 + REG_CLK_EN + NA + 0 1 - write-only + read-write + + + + CPU_INTR_FROM_CPU_0 + NA + 0x10 + 0x20 + - INFIFO_OVF_L2_CH2_INT_CLR - Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. - 6 + CPU_INTR_FROM_CPU_0 + set 1 will triger a interrupt + 0 1 - write-only + read-write + + + + CPU_INTR_FROM_CPU_1 + NA + 0x14 + 0x20 + - INFIFO_UDF_L2_CH2_INT_CLR - Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. - 7 + CPU_INTR_FROM_CPU_1 + set 1 will triger a interrupt + 0 1 - write-only + read-write + + + + CPU_INTR_FROM_CPU_2 + NA + 0x18 + 0x20 + - IN_DSCR_EMPTY_CH2_INT_CLR - Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. - 8 + CPU_INTR_FROM_CPU_2 + set 1 will triger a interrupt + 0 1 - write-only + read-write + + + + CPU_INTR_FROM_CPU_3 + NA + 0x1C + 0x20 + - IN_DSCR_TASK_OVF_CH2_INT_CLR - Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt. - 9 + CPU_INTR_FROM_CPU_3 + set 1 will triger a interrupt + 0 1 - write-only + read-write - INFIFO_STATUS_CH2 - RX CH2 INFIFO status register - 0x714 + CACHE_CLK_CONFIG + NA + 0x20 0x20 - 0x00020082 + 0x00000033 - INFIFO_FULL_L2_CH2 - Rx FIFO full signal for Rx channel. + REG_L2_CACHE_CLK_ON + l2 cahce clk enable 0 1 - read-only + read-write - INFIFO_EMPTY_L2_CH2 - Rx FIFO empty signal for Rx channel. + REG_L1_D_CACHE_CLK_ON + l1 dcahce clk enable 1 1 - read-only - - - INFIFO_CNT_L2_CH2 - The register stores the byte number of the data in Rx FIFO for Rx channel. - 2 - 4 - read-only + read-write - INFIFO_FULL_L1_CH2 - Tx FIFO full signal for Tx channel 1. - 6 + REG_L1_I1_CACHE_CLK_ON + l1 icahce1 clk enable + 4 1 - read-only + read-write - INFIFO_EMPTY_L1_CH2 - Tx FIFO empty signal for Tx channel 1. - 7 + REG_L1_I0_CACHE_CLK_ON + l1 icahce0 clk enable + 5 1 - read-only - - - INFIFO_CNT_L1_CH2 - The register stores the byte number of the data in Tx FIFO for Tx channel 1. - 8 - 5 - read-only + read-write + + + + CACHE_RESET_CONFIG + NA + 0x24 + 0x20 + - INFIFO_FULL_L3_CH2 - Tx FIFO full signal for Tx channel 1. - 16 + REG_L1_D_CACHE_RESET + set 1 to reset l1 dcahce + 1 1 - read-only + read-write - INFIFO_EMPTY_L3_CH2 - Tx FIFO empty signal for Tx channel 1. - 17 + REG_L1_I1_CACHE_RESET + set 1 to reset l1 icahce1 + 4 1 - read-only + read-write - INFIFO_CNT_L3_CH2 - The register stores the byte number of the data in Tx FIFO for Tx channel 1. - 18 - 2 - read-only + REG_L1_I0_CACHE_RESET + set 1 to reset l1 icahce0 + 5 + 1 + read-write - IN_POP_CH2 - RX CH2 INFIFO pop register - 0x718 + DMA_ADDR_CTRL + NA + 0x2C 0x20 - 0x00000400 - INFIFO_RDATA_CH2 - This register stores the data popping from DMA Rx FIFO. + REG_SYS_DMA_ADDR_SEL + 0 means dma access extmem use 8xxx_xxxx else use 4xxx_xxxx 0 - 11 - read-only - - - INFIFO_POP_CH2 - Set this bit to pop data from DMA Rx FIFO. - 11 1 read-write - IN_LINK_CONF_CH2 - RX CH2 in_link dscr ctrl register - 0x71C + TCM_RAM_WRR_CONFIG + NA + 0x34 0x20 - 0x01100000 + 0x826ED93F - INLINK_AUTO_RET_CH2 - Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data. - 20 - 1 + REG_TCM_RAM_IBUS0_WT + weight value of ibus0 + 0 + 3 read-write - INLINK_STOP_CH2 - Set this bit to stop dealing with the inlink descriptors. - 21 - 1 + REG_TCM_RAM_IBUS1_WT + weight value of ibus1 + 3 + 3 read-write - INLINK_START_CH2 - Set this bit to start dealing with the inlink descriptors. - 22 - 1 + REG_TCM_RAM_IBUS2_WT + weight value of ibus2 + 6 + 3 read-write - INLINK_RESTART_CH2 - Set this bit to mount a new inlink descriptor. - 23 - 1 + REG_TCM_RAM_IBUS3_WT + weight value of ibus3 + 9 + 3 read-write - INLINK_PARK_CH2 - 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working. + REG_TCM_RAM_DBUS0_WT + weight value of dbus0 + 12 + 3 + read-write + + + REG_TCM_RAM_DBUS1_WT + weight value of dbus1 + 15 + 3 + read-write + + + REG_TCM_RAM_DBUS2_WT + weight value of dbus2 + 18 + 3 + read-write + + + REG_TCM_RAM_DBUS3_WT + weight value of dbus3 + 21 + 3 + read-write + + + REG_TCM_RAM_DMA_WT + weight value of dma 24 + 3 + read-write + + + REG_TCM_RAM_WRR_HIGH + enable weighted round robin arbitration + 31 1 - read-only + read-write - IN_LINK_ADDR_CH2 - RX CH2 in_link dscr addr register - 0x720 + TCM_SW_PARITY_BWE_MASK + NA + 0x38 0x20 - INLINK_ADDR_CH2 - This register stores the first inlink descriptor's address. + REG_TCM_SW_PARITY_BWE_MASK_CTRL + Set 1 to mask tcm bwe parity code bit 0 - 32 + 1 read-write - IN_STATE_CH2 - RX CH2 state register - 0x724 + TCM_RAM_PWR_CTRL0 + NA + 0x3C 0x20 - 0x00800000 - INLINK_DSCR_ADDR_CH2 - This register stores the current inlink descriptor's address. + REG_HP_TCM_CLK_FORCE_ON + hp_tcm clk gatig force on 0 - 18 - read-only - - - IN_DSCR_STATE_CH2 - This register stores the current descriptor state machine state. - 18 - 2 - read-only - - - IN_STATE_CH2 - This register stores the current control module state machine state. - 20 - 3 - read-only - - - IN_RESET_AVAIL_CH2 - This register indicate that if the channel reset is safety. - 23 1 - read-only + read-write - IN_SUC_EOF_DES_ADDR_CH2 - RX CH2 eof des addr register - 0x728 + L2_ROM_PWR_CTRL0 + NA + 0x40 0x20 - IN_SUC_EOF_DES_ADDR_CH2 - This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. + REG_L2_ROM_CLK_FORCE_ON + l2_rom clk gating force on 0 - 32 - read-only + 1 + read-write - IN_ERR_EOF_DES_ADDR_CH2 - RX CH2 err eof des addr register - 0x72C + PROBEA_CTRL + NA + 0x50 0x20 - IN_ERR_EOF_DES_ADDR_CH2 - This register stores the address of the inlink descriptor when there are some errors in current receiving data. + REG_PROBE_A_MOD_SEL + Tihs field is used to selec probe_group from probe_group0 to probe_group15 for module's probe_out[31:0] in a mode 0 - 32 - read-only + 16 + read-write + + + REG_PROBE_A_TOP_SEL + Tihs field is used to selec module's probe_out[31:0] as probe out in a mode + 16 + 8 + read-write + + + REG_PROBE_L_SEL + Tihs field is used to selec probe_out[31:16] + 24 + 2 + read-write + + + REG_PROBE_H_SEL + Tihs field is used to selec probe_out[31:16] + 26 + 2 + read-write + + + REG_PROBE_GLOBAL_EN + Set this bit to enable global debug probe in hp system. + 28 + 1 + read-write - IN_DSCR_CH2 - RX CH2 next dscr addr register - 0x730 + PROBEB_CTRL + NA + 0x54 0x20 - INLINK_DSCR_CH2 - The address of the next inlink descriptor address x. + REG_PROBE_B_MOD_SEL + Tihs field is used to selec probe_group from probe_group0 to probe_group15 for module's probe_out[31:0] in b mode. 0 - 32 - read-only + 16 + read-write + + + REG_PROBE_B_TOP_SEL + Tihs field is used to select module's probe_out[31:0] as probe_out in b mode + 16 + 8 + read-write + + + REG_PROBE_B_EN + Set this bit to enable b mode for debug probe. 1: b mode, 0: a mode. + 24 + 1 + read-write - IN_DSCR_BF0_CH2 - RX CH2 last dscr addr register - 0x734 + PROBE_OUT + NA + 0x5C 0x20 - INLINK_DSCR_BF0_CH2 - The address of the last inlink descriptor's next address x-1. + REG_PROBE_TOP_OUT + NA 0 32 read-only @@ -54038,869 +52378,984 @@ - IN_DSCR_BF1_CH2 - RX CH2 second-to-last dscr addr register - 0x738 + L2_MEM_RAM_PWR_CTRL0 + NA + 0x60 0x20 - INLINK_DSCR_BF1_CH2 - The address of the second-to-last inlink descriptor's next address x-2. + REG_L2_MEM_CLK_FORCE_ON + l2ram clk_gating force on 0 - 32 - read-only + 1 + read-write - IN_ARB_CH2 - RX CH2 arb register - 0x740 + CPU_CORESTALLED_ST + NA + 0x64 0x20 - 0x00000041 - IN_ARB_TOKEN_NUM_CH2 - Set the max number of token count of arbiter + REG_CORE0_CORESTALLED_ST + hp core0 corestalled status 0 - 4 - read-write + 1 + read-only - INTER_IN_ARB_PRIORITY_CH2 - Set the priority of channel - 6 - 3 - read-write + REG_CORE1_CORESTALLED_ST + hp core1 corestalled status + 1 + 1 + read-only - IN_ETM_CONF_CH2 - RX CH2 ETM config register - 0x748 + CRYPTO_CTRL + NA + 0x70 0x20 - 0x00000004 - IN_ETM_EN_CH2 - Set this bit to 1 to enable ETM task function + REG_ENABLE_SPI_MANUAL_ENCRYPT + NA 0 1 read-write - IN_ETM_LOOP_EN_CH2 - when this bit is 1, dscr can be processed after receiving a task + REG_ENABLE_DOWNLOAD_DB_ENCRYPT + NA 1 1 read-write - IN_DSCR_TASK_MAK_CH2 - ETM dscr_ready maximum cache numbers + REG_ENABLE_DOWNLOAD_G0CB_DECRYPT + NA 2 - 2 + 1 + read-write + + + REG_ENABLE_DOWNLOAD_MANUAL_ENCRYPT + NA + 3 + 1 read-write - IN_FIFO_CNT_CH2 - rx CH2 fifo cnt register - 0x780 + GPIO_O_HOLD_CTRL0 + NA + 0x74 0x20 - IN_CMDFIFO_INFIFO_CNT_CH2 - only for debug + REG_GPIO_0_HOLD_LOW + hold control for gpio47~16 0 - 10 - read-only + 32 + read-write - IN_POP_DATA_CNT_CH2 - rx CH2 pop data cnt register - 0x784 + GPIO_O_HOLD_CTRL1 + NA + 0x78 0x20 - 0x00000007 - IN_CMDFIFO_POP_DATA_CNT_CH2 - only for debug + REG_GPIO_0_HOLD_HIGH + hold control for gpio56~48 0 - 8 - read-only + 9 + read-write - IN_XADDR_CH2 - rx CH2 xaddr register - 0x788 + RDN_ECO_CS + NA + 0x7C 0x20 - IN_CMDFIFO_XADDR_CH2 - only for debug + REG_HP_SYS_RDN_ECO_EN + NA 0 - 32 + 1 + read-write + + + REG_HP_SYS_RDN_ECO_RESULT + NA + 1 + 1 read-only - IN_BUF_HB_RCV_CH2 - rx CH2 buf len hb rcv register - 0x78C + CACHE_APB_POSTW_EN + NA + 0x80 0x20 - IN_CMDFIFO_BUF_HB_RCV_CH2 - only for debug + REG_CACHE_APB_POSTW_EN + cache apb register interface post write enable, 1 will speed up write, but will take some time to update value to register 0 - 29 - read-only + 1 + read-write - IN_CONF0_CH3 - RX CH3 config0 register - 0x800 + L2_MEM_SUBSIZE + NA + 0x84 0x20 - INDSCR_BURST_EN_CH3 - Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor when accessing SRAM. - 2 - 1 - read-write - - - IN_ECC_AES_EN_CH3 - When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned. - 3 - 1 - read-write - - - IN_CHECK_OWNER_CH3 - Set this bit to enable checking the owner attribute of the link descriptor. - 4 - 1 - read-write - - - IN_MEM_BURST_LENGTH_CH3 - Block size of Rx channel 1. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes - 6 - 3 - read-write - - - IN_PAGE_BOUND_EN_CH3 - Set this bit to 1 to make sure AXI write data don't cross the address boundary which define by mem_burst_length - 12 - 1 + REG_L2_MEM_SUB_BLKSIZE + l2mem sub block size 00=>32 01=>64 10=>128 11=>256 + 0 + 2 read-write + + + + L2_MEM_INT_RAW + NA + 0x9C + 0x20 + - IN_RST_CH3 - Write 1 then write 0 to this bit to reset Rx channel - 24 + REG_L2_MEM_ECC_ERR_INT_RAW + intr triggered when two bit error detected and corrected from ecc + 0 1 read-write - IN_CMD_DISABLE_CH3 - Write 1 before reset and write 0 after reset - 25 + REG_L2_MEM_EXCEED_ADDR_INT_RAW + intr triggered when access addr exceeds 0xff9ffff at bypass mode or exceeds 0xff80000 at l2cache 128kb mode or exceeds 0xff60000 at l2cache 256kb mode + 1 1 read-write - IN_ARB_WEIGHT_OPT_DIS_CH3 - Set this bit to 1 to disable arbiter optimum weight function. - 26 + REG_L2_MEM_ERR_RESP_INT_RAW + intr triggered when err response occurs + 2 1 read-write - IN_INT_RAW_CH3 - RX CH3 interrupt raw register - 0x804 + L2_MEM_INT_ST + NA + 0xA0 0x20 - IN_DONE_CH3_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been transmitted to peripherals for Rx channel 1. + REG_L2_MEM_ECC_ERR_INT_ST + NA 0 1 - read-write + read-only - IN_SUC_EOF_CH3_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1. + REG_L2_MEM_EXCEED_ADDR_INT_ST + NA 1 1 - read-write + read-only - IN_ERR_EOF_CH3_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and data error is detected + REG_L2_MEM_ERR_RESP_INT_ST + NA 2 1 - read-write - - - IN_DSCR_ERR_CH3_INT_RAW - The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 1. - 3 - 1 - read-write + read-only + + + + L2_MEM_INT_ENA + NA + 0xA4 + 0x20 + - INFIFO_OVF_L1_CH3_INT_RAW - This raw interrupt bit turns to high level when fifo of Rx channel is overflow. - 4 + REG_L2_MEM_ECC_ERR_INT_ENA + NA + 0 1 read-write - INFIFO_UDF_L1_CH3_INT_RAW - This raw interrupt bit turns to high level when fifo of Rx channel is underflow. - 5 + REG_L2_MEM_EXCEED_ADDR_INT_ENA + NA + 1 1 read-write - INFIFO_OVF_L2_CH3_INT_RAW - This raw interrupt bit turns to high level when fifo of Rx channel is overflow. - 6 + REG_L2_MEM_ERR_RESP_INT_ENA + NA + 2 1 read-write + + + + L2_MEM_INT_CLR + NA + 0xA8 + 0x20 + - INFIFO_UDF_L2_CH3_INT_RAW - This raw interrupt bit turns to high level when fifo of Rx channel is underflow. - 7 + REG_L2_MEM_ECC_ERR_INT_CLR + NA + 0 1 - read-write + write-only - IN_DSCR_EMPTY_CH3_INT_RAW - The raw interrupt bit turns to high level when the last descriptor is done but fifo also remain data. - 8 + REG_L2_MEM_EXCEED_ADDR_INT_CLR + NA + 1 1 - read-write + write-only - IN_DSCR_TASK_OVF_CH3_INT_RAW - The raw interrupt bit turns to high level when dscr ready task fifo is overflow. - 9 + REG_L2_MEM_ERR_RESP_INT_CLR + NA + 2 1 - read-write + write-only - IN_INT_ENA_CH3 - RX CH3 interrupt ena register - 0x808 + L2_MEM_L2_RAM_ECC + NA + 0xAC 0x20 - IN_DONE_CH3_INT_ENA - The interrupt enable bit for the IN_DONE_CH_INT interrupt. + REG_L2_RAM_UNIT0_ECC_EN + NA 0 1 read-write - IN_SUC_EOF_CH3_INT_ENA - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + REG_L2_RAM_UNIT1_ECC_EN + NA 1 1 read-write - IN_ERR_EOF_CH3_INT_ENA - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + REG_L2_RAM_UNIT2_ECC_EN + NA 2 1 read-write - IN_DSCR_ERR_CH3_INT_ENA - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + REG_L2_RAM_UNIT3_ECC_EN + NA 3 1 read-write - INFIFO_OVF_L1_CH3_INT_ENA - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + REG_L2_RAM_UNIT4_ECC_EN + NA 4 1 read-write - INFIFO_UDF_L1_CH3_INT_ENA - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + REG_L2_RAM_UNIT5_ECC_EN + NA 5 1 read-write + + + + L2_MEM_INT_RECORD0 + NA + 0xB0 + 0x20 + - INFIFO_OVF_L2_CH3_INT_ENA - The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. - 6 - 1 - read-write + REG_L2_MEM_EXCEED_ADDR_INT_ADDR + NA + 0 + 21 + read-only - INFIFO_UDF_L2_CH3_INT_ENA - The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. - 7 - 1 - read-write - - - IN_DSCR_EMPTY_CH3_INT_ENA - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. - 8 + REG_L2_MEM_EXCEED_ADDR_INT_WE + NA + 21 1 - read-write + read-only - IN_DSCR_TASK_OVF_CH3_INT_ENA - The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. - 9 - 1 - read-write + REG_L2_MEM_EXCEED_ADDR_INT_MASTER + NA + 22 + 3 + read-only - IN_INT_ST_CH3 - RX CH3 interrupt st register - 0x80C + L2_MEM_INT_RECORD1 + NA + 0xB4 0x20 - IN_DONE_CH3_INT_ST - The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + REG_L2_MEM_ECC_ERR_INT_ADDR + NA 0 - 1 - read-only - - - IN_SUC_EOF_CH3_INT_ST - The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. - 1 - 1 - read-only - - - IN_ERR_EOF_CH3_INT_ST - The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. - 2 - 1 + 15 read-only - IN_DSCR_ERR_CH3_INT_ST - The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. - 3 + REG_L2_MEM_ECC_ONE_BIT_ERR + NA + 15 1 read-only - INFIFO_OVF_L1_CH3_INT_ST - The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. - 4 + REG_L2_MEM_ECC_TWO_BIT_ERR + NA + 16 1 read-only - INFIFO_UDF_L1_CH3_INT_ST - The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. - 5 - 1 + REG_L2_MEM_ECC_ERR_BIT + NA + 17 + 9 read-only - INFIFO_OVF_L2_CH3_INT_ST - The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. - 6 + REG_L2_CACHE_ERR_BANK + NA + 26 1 read-only + + + + L2_MEM_L2_CACHE_ECC + NA + 0xC4 + 0x20 + - INFIFO_UDF_L2_CH3_INT_ST - The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. - 7 + REG_L2_CACHE_ECC_EN + NA + 0 1 - read-only + read-write + + + + L1CACHE_BUS0_ID + NA + 0xC8 + 0x20 + - IN_DSCR_EMPTY_CH3_INT_ST - The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. - 8 - 1 - read-only + REG_L1_CACHE_BUS0_ID + NA + 0 + 4 + read-write + + + + L1CACHE_BUS1_ID + NA + 0xCC + 0x20 + - IN_DSCR_TASK_OVF_CH3_INT_ST - The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. - 9 - 1 - read-only + REG_L1_CACHE_BUS1_ID + NA + 0 + 4 + read-write - IN_INT_CLR_CH3 - RX CH3 interrupt clr register - 0x810 + L2_MEM_RDN_ECO_CS + NA + 0xD8 0x20 - IN_DONE_CH3_INT_CLR - Set this bit to clear the IN_DONE_CH_INT interrupt. + REG_L2_MEM_RDN_ECO_EN + NA 0 1 - write-only + read-write - IN_SUC_EOF_CH3_INT_CLR - Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + REG_L2_MEM_RDN_ECO_RESULT + NA 1 1 - write-only - - - IN_ERR_EOF_CH3_INT_CLR - Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. - 2 - 1 - write-only - - - IN_DSCR_ERR_CH3_INT_CLR - Set this bit to clear the INDSCR_ERR_CH_INT interrupt. - 3 - 1 - write-only - - - INFIFO_OVF_L1_CH3_INT_CLR - Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. - 4 - 1 - write-only - - - INFIFO_UDF_L1_CH3_INT_CLR - Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. - 5 - 1 - write-only - - - INFIFO_OVF_L2_CH3_INT_CLR - Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. - 6 - 1 - write-only - - - INFIFO_UDF_L2_CH3_INT_CLR - Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. - 7 - 1 - write-only + read-only + + + + L2_MEM_RDN_ECO_LOW + NA + 0xDC + 0x20 + - IN_DSCR_EMPTY_CH3_INT_CLR - Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. - 8 - 1 - write-only + REG_L2_MEM_RDN_ECO_LOW + NA + 0 + 32 + read-write + + + + L2_MEM_RDN_ECO_HIGH + NA + 0xE0 + 0x20 + 0xFFFFFFFF + - IN_DSCR_TASK_OVF_CH3_INT_CLR - Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt. - 9 - 1 - write-only + REG_L2_MEM_RDN_ECO_HIGH + NA + 0 + 32 + read-write - INFIFO_STATUS_CH3 - RX CH3 INFIFO status register - 0x814 + TCM_RDN_ECO_CS + NA + 0xE4 0x20 - 0x00020082 - INFIFO_FULL_L2_CH3 - Rx FIFO full signal for Rx channel. + REG_HP_TCM_RDN_ECO_EN + NA 0 1 - read-only + read-write - INFIFO_EMPTY_L2_CH3 - Rx FIFO empty signal for Rx channel. + REG_HP_TCM_RDN_ECO_RESULT + NA 1 1 read-only + + + + TCM_RDN_ECO_LOW + NA + 0xE8 + 0x20 + - INFIFO_CNT_L2_CH3 - The register stores the byte number of the data in Rx FIFO for Rx channel. - 2 - 4 - read-only - - - INFIFO_FULL_L1_CH3 - Tx FIFO full signal for Tx channel 1. - 6 - 1 - read-only - - - INFIFO_EMPTY_L1_CH3 - Tx FIFO empty signal for Tx channel 1. - 7 - 1 - read-only + REG_HP_TCM_RDN_ECO_LOW + NA + 0 + 32 + read-write + + + + TCM_RDN_ECO_HIGH + NA + 0xEC + 0x20 + 0xFFFFFFFF + - INFIFO_CNT_L1_CH3 - The register stores the byte number of the data in Tx FIFO for Tx channel 1. - 8 - 5 - read-only + REG_HP_TCM_RDN_ECO_HIGH + NA + 0 + 32 + read-write + + + + GPIO_DED_HOLD_CTRL + NA + 0xF0 + 0x20 + - INFIFO_FULL_L3_CH3 - Tx FIFO full signal for Tx channel 1. - 16 - 1 - read-only + REG_GPIO_DED_HOLD + hold control for gpio63~56 + 0 + 26 + read-write + + + + L2_MEM_SW_ECC_BWE_MASK + NA + 0xF4 + 0x20 + - INFIFO_EMPTY_L3_CH3 - Tx FIFO empty signal for Tx channel 1. - 17 + REG_L2_MEM_SW_ECC_BWE_MASK_CTRL + Set 1 to mask bwe hamming code bit + 0 1 - read-only - - - INFIFO_CNT_L3_CH3 - The register stores the byte number of the data in Tx FIFO for Tx channel 1. - 18 - 2 - read-only + read-write - IN_POP_CH3 - RX CH3 INFIFO pop register - 0x818 + USB20OTG_MEM_CTRL + NA + 0xF8 0x20 - 0x00000400 - INFIFO_RDATA_CH3 - This register stores the data popping from DMA Rx FIFO. + REG_USB20_MEM_CLK_FORCE_ON + NA 0 - 11 - read-only - - - INFIFO_POP_CH3 - Set this bit to pop data from DMA Rx FIFO. - 11 1 read-write - IN_LINK_CONF_CH3 - RX CH3 in_link dscr ctrl register - 0x81C + TCM_INT_RAW + need_des + 0xFC 0x20 - 0x01100000 - INLINK_AUTO_RET_CH3 - Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data. - 20 + TCM_PARITY_ERR_INT_RAW + need_des + 31 1 read-write + + + + TCM_INT_ST + need_des + 0x100 + 0x20 + - INLINK_STOP_CH3 - Set this bit to stop dealing with the inlink descriptors. - 21 + TCM_PARITY_ERR_INT_ST + need_des + 31 1 - read-write + read-only + + + + TCM_INT_ENA + need_des + 0x104 + 0x20 + - INLINK_START_CH3 - Set this bit to start dealing with the inlink descriptors. - 22 + TCM_PARITY_ERR_INT_ENA + need_des + 31 1 read-write + + + + TCM_INT_CLR + need_des + 0x108 + 0x20 + - INLINK_RESTART_CH3 - Set this bit to mount a new inlink descriptor. - 23 + TCM_PARITY_ERR_INT_CLR + need_des + 31 1 - read-write + write-only + + + + TCM_PARITY_INT_RECORD + need_des + 0x10C + 0x20 + - INLINK_PARK_CH3 - 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working. - 24 - 1 + TCM_PARITY_ERR_INT_ADDR + hp tcm_parity_err_addr + 0 + 13 read-only - IN_LINK_ADDR_CH3 - RX CH3 in_link dscr addr register - 0x820 + L1_CACHE_PWR_CTRL + NA + 0x110 0x20 - INLINK_ADDR_CH3 - This register stores the first inlink descriptor's address. + REG_L1_CACHE_MEM_FO + need_des 0 - 32 + 6 read-write - IN_STATE_CH3 - RX CH3 state register - 0x824 + L2_CACHE_PWR_CTRL + NA + 0x114 0x20 - 0x00800000 - INLINK_DSCR_ADDR_CH3 - This register stores the current inlink descriptor's address. + REG_L2_CACHE_MEM_FO + need_des 0 - 18 - read-only + 2 + read-write + + + + CPU_WAITI_CONF + CPU_WAITI configuration register + 0x118 + 0x20 + 0x00000001 + - IN_DSCR_STATE_CH3 - This register stores the current descriptor state machine state. - 18 - 2 - read-only + CPU_WAIT_MODE_FORCE_ON + Set 1 to force cpu_waiti_clk enable. + 0 + 1 + read-write - IN_STATE_CH3 - This register stores the current control module state machine state. - 20 - 3 - read-only + CPU_WAITI_DELAY_NUM + This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk will close + 1 + 4 + read-write + + + + CORE_DEBUG_RUNSTALL_CONF + Core Debug runstall configure register + 0x11C + 0x20 + - IN_RESET_AVAIL_CH3 - This register indicate that if the channel reset is safety. - 23 + CORE_DEBUG_RUNSTALL_ENABLE + Set this field to 1 to enable debug runstall feature between HP-core and LP-core. + 0 1 - read-only + read-write - IN_SUC_EOF_DES_ADDR_CH3 - RX CH3 eof des addr register - 0x828 + CORE_AHB_TIMEOUT + need_des + 0x120 0x20 + 0x0001FFFF - IN_SUC_EOF_DES_ADDR_CH3 - This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. + EN + set this field to 1 to enable hp core0&1 ahb timeout handle 0 - 32 - read-only + 1 + read-write + + + THRES + This field used to set hp core0&1 ahb bus timeout threshold + 1 + 16 + read-write - IN_ERR_EOF_DES_ADDR_CH3 - RX CH3 err eof des addr register - 0x82C + CORE_IBUS_TIMEOUT + need_des + 0x124 0x20 + 0x0001FFFF - IN_ERR_EOF_DES_ADDR_CH3 - This register stores the address of the inlink descriptor when there are some errors in current receiving data. + EN + set this field to 1 to enable hp core0&1 ibus timeout handle 0 - 32 - read-only + 1 + read-write + + + THRES + This field used to set hp core0&1 ibus timeout threshold + 1 + 16 + read-write - IN_DSCR_CH3 - RX CH3 next dscr addr register - 0x830 + CORE_DBUS_TIMEOUT + need_des + 0x128 0x20 + 0x0001FFFF - INLINK_DSCR_CH3 - The address of the next inlink descriptor address x. + EN + set this field to 1 to enable hp core0&1 dbus timeout handle 0 - 32 - read-only + 1 + read-write + + + THRES + This field used to set hp core0&1 dbus timeout threshold + 1 + 16 + read-write - IN_DSCR_BF0_CH3 - RX CH3 last dscr addr register - 0x834 + ICM_CPU_H2X_CFG + need_des + 0x138 0x20 + 0x00000003 - INLINK_DSCR_BF0_CH3 - The address of the last inlink descriptor's next address x-1. + CPU_ICM_H2X_POST_WR_EN + need_des 0 - 32 + 1 + read-write + + + CPU_ICM_H2X_CUT_THROUGH_EN + need_des + 1 + 1 + read-write + + + CPU_ICM_H2X_BRIDGE_BUSY + need_des + 2 + 1 read-only - IN_DSCR_BF1_CH3 - RX CH3 second-to-last dscr addr register - 0x838 + PERI1_APB_POSTW_EN + NA + 0x13C 0x20 - INLINK_DSCR_BF1_CH3 - The address of the second-to-last inlink descriptor's next address x-2. + PERI1_APB_POSTW_EN + hp_peri1 apb register interface post write enable, 1 will speed up write, but will take some time to update value to register 0 - 32 - read-only + 1 + read-write - IN_ARB_CH3 - RX CH3 arb register - 0x840 + BITSCRAMBLER_PERI_SEL + Bitscrambler Peri Sel + 0x140 0x20 - 0x00000041 + 0x000000FF - IN_ARB_TOKEN_NUM_CH3 - Set the max number of token count of arbiter + BITSCRAMBLER_PERI_RX_SEL + Set this field to sel peri with DMA RX interface to connec with bitscrambler: 4'h0 : lcd_cam, 4'h1: gpspi2, 4'h2: gpspi3, 4'h3: parl_io, 4'h4: aes, 4'h5: sha, 4'h6: adc, 4'h7: i2s0, 4'h8: i2s1, 4'h9: i2s2, 4'ha: i3c_mst, 4'hb: uhci0, 4'hc: RMT, else : none 0 4 read-write - INTER_IN_ARB_PRIORITY_CH3 - Set the priority of channel - 6 - 3 + BITSCRAMBLER_PERI_TX_SEL + Set this field to sel peri with DMA TX interface to connec with bitscrambler: 4'h0 : lcd_cam, 4'h1: gpspi2, 4'h2: gpspi3, 4'h3: parl_io, 4'h4: aes, 4'h5: sha, 4'h6: adc, 4'h7: i2s0, 4'h8: i2s1, 4'h9: i2s2, 4'ha: i3c_mst, 4'hb: uhci0, 4'hc: RMT, else : none + 4 + 4 read-write - IN_ETM_CONF_CH3 - RX CH3 ETM config register - 0x848 + APB_SYNC_POSTW_EN + N/A + 0x144 0x20 - 0x00000004 - IN_ETM_EN_CH3 - Set this bit to 1 to enable ETM task function + GMAC_APB_POSTW_EN + N/A 0 1 read-write - IN_ETM_LOOP_EN_CH3 - when this bit is 1, dscr can be processed after receiving a task + DSI_HOST_APB_POSTW_EN + N/A 1 1 read-write - IN_DSCR_TASK_MAK_CH3 - ETM dscr_ready maximum cache numbers + CSI_HOST_APB_SYNC_POSTW_EN + N/A 2 - 2 + 1 + read-write + + + CSI_HOST_APB_ASYNC_POSTW_EN + N/A + 3 + 1 read-write - IN_FIFO_CNT_CH3 - rx CH3 fifo cnt register - 0x880 + GDMA_CTRL + N/A + 0x148 0x20 - IN_CMDFIFO_INFIFO_CNT_CH3 - only for debug + DEBUG_CH_NUM + N/A 0 - 10 - read-only + 2 + read-write - IN_POP_DATA_CNT_CH3 - rx CH3 pop data cnt register - 0x884 + GMAC_CTRL0 + N/A + 0x14C 0x20 - 0x00000007 - IN_CMDFIFO_POP_DATA_CNT_CH3 - only for debug + PTP_PPS + N/A 0 - 8 + 1 + read-only + + + SBD_FLOWCTRL + N/A + 1 + 1 + read-write + + + PHY_INTF_SEL + N/A + 2 + 3 + read-write + + + GMAC_MEM_CLK_FORCE_ON + N/A + 5 + 1 + read-write + + + GMAC_RST_CLK_TX_N + N/A + 6 + 1 + read-only + + + GMAC_RST_CLK_RX_N + N/A + 7 + 1 read-only - IN_XADDR_CH3 - rx CH3 xaddr register - 0x888 + GMAC_CTRL1 + N/A + 0x150 0x20 - IN_CMDFIFO_XADDR_CH3 - only for debug + PTP_TIMESTAMP_L + N/A 0 32 read-only @@ -54908,2207 +53363,1887 @@ - IN_BUF_HB_RCV_CH3 - rx CH3 buf len hb rcv register - 0x88C + GMAC_CTRL2 + N/A + 0x154 0x20 - IN_CMDFIFO_BUF_HB_RCV_CH3 - only for debug + PTP_TIMESTAMP_H + N/A 0 - 29 + 32 read-only - IN_CONF0_CH4 - RX CH4 config0 register - 0x900 + VPU_CTRL + N/A + 0x158 0x20 - INDSCR_BURST_EN_CH4 - Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor when accessing SRAM. - 2 + PPA_LSLP_MEM_PD + N/A + 0 1 read-write - IN_ECC_AES_EN_CH4 - When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned. - 3 + JPEG_SDSLP_MEM_PD + N/A + 1 1 read-write - IN_CHECK_OWNER_CH4 - Set this bit to enable checking the owner attribute of the link descriptor. - 4 + JPEG_LSLP_MEM_PD + N/A + 2 1 read-write - IN_MEM_BURST_LENGTH_CH4 - Block size of Rx channel 1. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes - 6 - 3 + JPEG_DSLP_MEM_PD + N/A + 3 + 1 read-write - IN_PAGE_BOUND_EN_CH4 - Set this bit to 1 to make sure AXI write data don't cross the address boundary which define by mem_burst_length - 12 + DMA2D_LSLP_MEM_PD + N/A + 4 1 read-write + + + + USBOTG20_CTRL + N/A + 0x15C + 0x20 + 0x00822640 + - IN_RST_CH4 - Write 1 then write 0 to this bit to reset Rx channel - 24 + OTG_PHY_TEST_DONE + N/A + 0 1 - read-write + read-only - IN_CMD_DISABLE_CH4 - Write 1 before reset and write 0 after reset - 25 - 1 + USB_MEM_AUX_CTRL + N/A + 1 + 14 read-write - IN_ARB_WEIGHT_OPT_DIS_CH4 - Set this bit to 1 to disable arbiter optimum weight function. - 26 + PHY_SUSPENDM + N/A + 15 1 read-write - - - - IN_INT_RAW_CH4 - RX CH4 interrupt raw register - 0x904 - 0x20 - - IN_DONE_CH4_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been transmitted to peripherals for Rx channel 1. - 0 + PHY_SUSPEND_FORCE_EN + N/A + 16 1 read-write - IN_SUC_EOF_CH4_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1. - 1 + PHY_RSTN + N/A + 17 1 read-write - IN_ERR_EOF_CH4_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and data error is detected - 2 + PHY_RESET_FORCE_EN + N/A + 18 1 read-write - IN_DSCR_ERR_CH4_INT_RAW - The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 1. - 3 + PHY_PLL_FORCE_EN + N/A + 19 1 read-write - INFIFO_OVF_L1_CH4_INT_RAW - This raw interrupt bit turns to high level when fifo of Rx channel is overflow. - 4 + PHY_PLL_EN + N/A + 20 1 read-write - INFIFO_UDF_L1_CH4_INT_RAW - This raw interrupt bit turns to high level when fifo of Rx channel is underflow. - 5 + OTG_SUSPENDM + N/A + 21 1 read-write - INFIFO_OVF_L2_CH4_INT_RAW - This raw interrupt bit turns to high level when fifo of Rx channel is overflow. - 6 + OTG_PHY_TXBITSTUFF_EN + N/A + 22 1 read-write - INFIFO_UDF_L2_CH4_INT_RAW - This raw interrupt bit turns to high level when fifo of Rx channel is underflow. - 7 + OTG_PHY_REFCLK_MODE + N/A + 23 1 read-write - IN_DSCR_EMPTY_CH4_INT_RAW - The raw interrupt bit turns to high level when the last descriptor is done but fifo also remain data. - 8 + OTG_PHY_BISTEN + N/A + 24 1 read-write + + + + TCM_ERR_RESP_CTRL + need_des + 0x160 + 0x20 + - IN_DSCR_TASK_OVF_CH4_INT_RAW - The raw interrupt bit turns to high level when dscr ready task fifo is overflow. - 9 + TCM_ERR_RESP_EN + Set 1 to turn on tcm error response + 0 1 read-write - IN_INT_ENA_CH4 - RX CH4 interrupt ena register - 0x908 + L2_MEM_REFRESH + NA + 0x164 0x20 + 0x00000040 - IN_DONE_CH4_INT_ENA - The interrupt enable bit for the IN_DONE_CH_INT interrupt. + REG_L2_MEM_UNIT0_REFERSH_EN + NA 0 1 read-write - IN_SUC_EOF_CH4_INT_ENA - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + REG_L2_MEM_UNIT1_REFERSH_EN + NA 1 1 read-write - IN_ERR_EOF_CH4_INT_ENA - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + REG_L2_MEM_UNIT2_REFERSH_EN + NA 2 1 read-write - IN_DSCR_ERR_CH4_INT_ENA - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + REG_L2_MEM_UNIT3_REFERSH_EN + NA 3 1 read-write - INFIFO_OVF_L1_CH4_INT_ENA - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + REG_L2_MEM_UNIT4_REFERSH_EN + NA 4 1 read-write - INFIFO_UDF_L1_CH4_INT_ENA - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + REG_L2_MEM_UNIT5_REFERSH_EN + NA 5 1 read-write - INFIFO_OVF_L2_CH4_INT_ENA - The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. + REG_L2_MEM_REFERSH_CNT_RESET + Set 1 to reset l2mem_refresh_cnt 6 1 read-write - INFIFO_UDF_L2_CH4_INT_ENA - The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. + REG_L2_MEM_UNIT0_REFRESH_DONE + NA 7 1 - read-write + read-only - IN_DSCR_EMPTY_CH4_INT_ENA - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + REG_L2_MEM_UNIT1_REFRESH_DONE + NA 8 1 - read-write + read-only - IN_DSCR_TASK_OVF_CH4_INT_ENA - The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. + REG_L2_MEM_UNIT2_REFRESH_DONE + NA 9 1 - read-write - - - - - IN_INT_ST_CH4 - RX CH4 interrupt st register - 0x90C - 0x20 - - - IN_DONE_CH4_INT_ST - The raw interrupt status bit for the IN_DONE_CH_INT interrupt. - 0 - 1 read-only - IN_SUC_EOF_CH4_INT_ST - The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. - 1 + REG_L2_MEM_UNIT3_REFRESH_DONE + NA + 10 1 read-only - IN_ERR_EOF_CH4_INT_ST - The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. - 2 + REG_L2_MEM_UNIT4_REFRESH_DONE + NA + 11 1 read-only - IN_DSCR_ERR_CH4_INT_ST - The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. - 3 + REG_L2_MEM_UNIT5_REFRESH_DONE + NA + 12 1 read-only + + + + TCM_INIT + NA + 0x168 + 0x20 + 0x00000002 + - INFIFO_OVF_L1_CH4_INT_ST - The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. - 4 + REG_TCM_INIT_EN + NA + 0 1 - read-only + read-write - INFIFO_UDF_L1_CH4_INT_ST - The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. - 5 + REG_TCM_INIT_CNT_RESET + Set 1 to reset tcm init cnt + 1 1 - read-only + read-write - INFIFO_OVF_L2_CH4_INT_ST - The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. - 6 + REG_TCM_INIT_DONE + NA + 2 1 read-only + + + + TCM_PARITY_CHECK_CTRL + need_des + 0x16C + 0x20 + - INFIFO_UDF_L2_CH4_INT_ST - The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. - 7 + TCM_PARITY_CHECK_EN + Set 1 to turn on tcm parity check + 0 1 - read-only + read-write + + + + DESIGN_FOR_VERIFICATION0 + need_des + 0x170 + 0x20 + - IN_DSCR_EMPTY_CH4_INT_ST - The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. - 8 - 1 - read-only + DFV0 + register for DV + 0 + 32 + read-write + + + + DESIGN_FOR_VERIFICATION1 + need_des + 0x174 + 0x20 + - IN_DSCR_TASK_OVF_CH4_INT_ST - The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. - 9 - 1 - read-only + DFV1 + register for DV + 0 + 32 + read-write - IN_INT_CLR_CH4 - RX CH4 interrupt clr register - 0x910 + PSRAM_FLASH_ADDR_INTERCHANGE + need_des + 0x180 0x20 - IN_DONE_CH4_INT_CLR - Set this bit to clear the IN_DONE_CH_INT interrupt. + CPU + Set 1 to enable addr interchange between psram and flash in axi matrix when hp cpu access through cache 0 1 - write-only + read-write - IN_SUC_EOF_CH4_INT_CLR - Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + DMA + Set 1 to enable addr interchange between psram and flash in axi matrix when dma device access, lp core access and hp core access through ahb 1 1 - write-only + read-write + + + + AHB2AXI_BRESP_ERR_INT_RAW + NA + 0x188 + 0x20 + - IN_ERR_EOF_CH4_INT_CLR - Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. - 2 + CPU_ICM_H2X_BRESP_ERR_INT_RAW + the raw interrupt status of bresp error, triggered when if bresp err occurs in post write mode in ahb2axi. + 0 1 - write-only + read-write + + + + AHB2AXI_BRESP_ERR_INT_ST + need_des + 0x18C + 0x20 + - IN_DSCR_ERR_CH4_INT_CLR - Set this bit to clear the INDSCR_ERR_CH_INT interrupt. - 3 + CPU_ICM_H2X_BRESP_ERR_INT_ST + the masked interrupt status of cpu_icm_h2x_bresp_err + 31 1 - write-only + read-only + + + + AHB2AXI_BRESP_ERR_INT_ENA + need_des + 0x190 + 0x20 + - INFIFO_OVF_L1_CH4_INT_CLR - Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. - 4 + CPU_ICM_H2X_BRESP_ERR_INT_ENA + Write 1 to enable cpu_icm_h2x_bresp_err int + 31 1 - write-only + read-write - - INFIFO_UDF_L1_CH4_INT_CLR - Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. - 5 + + + + AHB2AXI_BRESP_ERR_INT_CLR + need_des + 0x194 + 0x20 + + + CPU_ICM_H2X_BRESP_ERR_INT_CLR + Write 1 to clear cpu_icm_h2x_bresp_err int + 31 1 write-only + + + + L2_MEM_ERR_RESP_CTRL + need_des + 0x198 + 0x20 + - INFIFO_OVF_L2_CH4_INT_CLR - Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. - 6 + L2_MEM_ERR_RESP_EN + Set 1 to turn on l2mem error response + 0 1 - write-only + read-write + + + + L2_MEM_AHB_BUFFER_CTRL + need_des + 0x19C + 0x20 + - INFIFO_UDF_L2_CH4_INT_CLR - Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. - 7 + L2_MEM_AHB_WRBUFFER_EN + Set 1 to turn on l2mem ahb wr buffer + 0 1 - write-only + read-write - IN_DSCR_EMPTY_CH4_INT_CLR - Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. - 8 + L2_MEM_AHB_RDBUFFER_EN + Set 1 to turn on l2mem ahb rd buffer + 1 1 - write-only + read-write + + + + CORE_DMACTIVE_LPCORE + need_des + 0x1A0 + 0x20 + - IN_DSCR_TASK_OVF_CH4_INT_CLR - Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt. - 9 + CORE_DMACTIVE_LPCORE + hp core dmactive_lpcore value + 0 1 - write-only + read-only - INFIFO_STATUS_CH4 - RX CH4 INFIFO status register - 0x914 + CORE_ERR_RESP_DIS + need_des + 0x1A4 0x20 - 0x00020082 - INFIFO_FULL_L2_CH4 - Rx FIFO full signal for Rx channel. + CORE_ERR_RESP_DIS + Set bit0 to disable ibus err resp. Set bit1 to disable dbus err resp. Set bit 2 to disable ahb err resp. + 0 + 3 + read-write + + + + + CORE_TIMEOUT_INT_RAW + Hp core bus timeout interrupt raw register + 0x1A8 + 0x20 + + + CORE0_AHB_TIMEOUT_INT_RAW + the raw interrupt status of hp core0 ahb timeout 0 1 - read-only + read-write - INFIFO_EMPTY_L2_CH4 - Rx FIFO empty signal for Rx channel. + CORE1_AHB_TIMEOUT_INT_RAW + the raw interrupt status of hp core1 ahb timeout 1 1 - read-only + read-write - INFIFO_CNT_L2_CH4 - The register stores the byte number of the data in Rx FIFO for Rx channel. + CORE0_IBUS_TIMEOUT_INT_RAW + the raw interrupt status of hp core0 ibus timeout 2 - 4 - read-only + 1 + read-write - INFIFO_FULL_L1_CH4 - Tx FIFO full signal for Tx channel 1. - 6 + CORE1_IBUS_TIMEOUT_INT_RAW + the raw interrupt status of hp core1 ibus timeout + 3 1 - read-only + read-write - INFIFO_EMPTY_L1_CH4 - Tx FIFO empty signal for Tx channel 1. - 7 + CORE0_DBUS_TIMEOUT_INT_RAW + the raw interrupt status of hp core0 dbus timeout + 4 1 - read-only + read-write - INFIFO_CNT_L1_CH4 - The register stores the byte number of the data in Tx FIFO for Tx channel 1. - 8 - 5 + CORE1_DBUS_TIMEOUT_INT_RAW + the raw interrupt status of hp core1 dbus timeout + 5 + 1 + read-write + + + + + CORE_TIMEOUT_INT_ST + masked interrupt register + 0x1AC + 0x20 + + + CORE0_AHB_TIMEOUT_INT_ST + the masked interrupt status of hp core0 ahb timeout + 0 + 1 read-only - INFIFO_FULL_L3_CH4 - Tx FIFO full signal for Tx channel 1. - 16 + CORE1_AHB_TIMEOUT_INT_ST + the masked interrupt status of hp core1 ahb timeout + 1 1 read-only - INFIFO_EMPTY_L3_CH4 - Tx FIFO empty signal for Tx channel 1. - 17 + CORE0_IBUS_TIMEOUT_INT_ST + the masked interrupt status of hp core0 ibus timeout + 2 1 read-only - INFIFO_CNT_L3_CH4 - The register stores the byte number of the data in Tx FIFO for Tx channel 1. - 18 - 2 + CORE1_IBUS_TIMEOUT_INT_ST + the masked interrupt status of hp core1 ibus timeout + 3 + 1 read-only - - - - IN_POP_CH4 - RX CH4 INFIFO pop register - 0x918 - 0x20 - 0x00000400 - - INFIFO_RDATA_CH4 - This register stores the data popping from DMA Rx FIFO. - 0 - 11 + CORE0_DBUS_TIMEOUT_INT_ST + the masked interrupt status of hp core0 dbus timeout + 4 + 1 read-only - INFIFO_POP_CH4 - Set this bit to pop data from DMA Rx FIFO. - 11 + CORE1_DBUS_TIMEOUT_INT_ST + the masked interrupt status of hp core1 dbus timeout + 5 1 - read-write + read-only - IN_LINK_CONF_CH4 - RX CH4 in_link dscr ctrl register - 0x91C + CORE_TIMEOUT_INT_ENA + masked interrupt register + 0x1B0 0x20 - 0x01100000 - INLINK_AUTO_RET_CH4 - Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data. - 20 + CORE0_AHB_TIMEOUT_INT_ENA + Write 1 to enable hp_core0_ahb_timeout int + 0 1 read-write - INLINK_STOP_CH4 - Set this bit to stop dealing with the inlink descriptors. - 21 + CORE1_AHB_TIMEOUT_INT_ENA + Write 1 to enable hp_core1_ahb_timeout int + 1 1 read-write - INLINK_START_CH4 - Set this bit to start dealing with the inlink descriptors. - 22 + CORE0_IBUS_TIMEOUT_INT_ENA + Write 1 to enable hp_core0_ibus_timeout int + 2 1 read-write - INLINK_RESTART_CH4 - Set this bit to mount a new inlink descriptor. - 23 + CORE1_IBUS_TIMEOUT_INT_ENA + Write 1 to enable hp_core1_ibus_timeout int + 3 1 read-write - INLINK_PARK_CH4 - 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working. - 24 + CORE0_DBUS_TIMEOUT_INT_ENA + Write 1 to enable hp_core0_dbus_timeout int + 4 1 - read-only + read-write - - - - IN_LINK_ADDR_CH4 - RX CH4 in_link dscr addr register - 0x920 - 0x20 - - INLINK_ADDR_CH4 - This register stores the first inlink descriptor's address. - 0 - 32 + CORE1_DBUS_TIMEOUT_INT_ENA + Write 1 to enable hp_core1_dbus_timeout int + 5 + 1 read-write - IN_STATE_CH4 - RX CH4 state register - 0x924 + CORE_TIMEOUT_INT_CLR + interrupt clear register + 0x1B4 0x20 - 0x00800000 - INLINK_DSCR_ADDR_CH4 - This register stores the current inlink descriptor's address. + CORE0_AHB_TIMEOUT_INT_CLR + Write 1 to clear hp_core0_ahb_timeout int 0 - 18 - read-only - - - IN_DSCR_STATE_CH4 - This register stores the current descriptor state machine state. - 18 - 2 - read-only + 1 + write-only - IN_STATE_CH4 - This register stores the current control module state machine state. - 20 - 3 - read-only + CORE1_AHB_TIMEOUT_INT_CLR + Write 1 to clear hp_core1_ahb_timeout int + 1 + 1 + write-only - IN_RESET_AVAIL_CH4 - This register indicate that if the channel reset is safety. - 23 + CORE0_IBUS_TIMEOUT_INT_CLR + Write 1 to clear hp_core0_ibus_timeout int + 2 1 - read-only + write-only - - - - IN_SUC_EOF_DES_ADDR_CH4 - RX CH4 eof des addr register - 0x928 - 0x20 - - IN_SUC_EOF_DES_ADDR_CH4 - This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. - 0 - 32 - read-only + CORE1_IBUS_TIMEOUT_INT_CLR + Write 1 to clear hp_core1_ibus_timeout int + 3 + 1 + write-only - - - - IN_ERR_EOF_DES_ADDR_CH4 - RX CH4 err eof des addr register - 0x92C - 0x20 - - IN_ERR_EOF_DES_ADDR_CH4 - This register stores the address of the inlink descriptor when there are some errors in current receiving data. - 0 - 32 - read-only + CORE0_DBUS_TIMEOUT_INT_CLR + Write 1 to clear hp_core0_dbus_timeout int + 4 + 1 + write-only - - - - IN_DSCR_CH4 - RX CH4 next dscr addr register - 0x930 - 0x20 - - INLINK_DSCR_CH4 - The address of the next inlink descriptor address x. - 0 - 32 - read-only + CORE1_DBUS_TIMEOUT_INT_CLR + Write 1 to clear hp_core1_dbus_timeout int + 5 + 1 + write-only - IN_DSCR_BF0_CH4 - RX CH4 last dscr addr register - 0x934 + GPIO_O_HYS_CTRL0 + NA + 0x1C0 0x20 - INLINK_DSCR_BF0_CH4 - The address of the last inlink descriptor's next address x-1. + REG_GPIO_0_HYS_LOW + hys control for gpio47~16 0 32 - read-only + read-write - IN_DSCR_BF1_CH4 - RX CH4 second-to-last dscr addr register - 0x938 + GPIO_O_HYS_CTRL1 + NA + 0x1C4 0x20 - INLINK_DSCR_BF1_CH4 - The address of the second-to-last inlink descriptor's next address x-2. + REG_GPIO_0_HYS_HIGH + hys control for gpio56~48 0 - 32 - read-only + 9 + read-write - IN_ARB_CH4 - RX CH4 arb register - 0x940 + RSA_PD_CTRL + rsa pd ctrl register + 0x1D0 0x20 - 0x00000051 + 0x00000002 - IN_ARB_TOKEN_NUM_CH4 - Set the max number of token count of arbiter + RSA_MEM_FORCE_PD + Set this bit to power down rsa internal memory. 0 - 4 + 1 read-write - EXTER_IN_ARB_PRIORITY_CH4 - Set the priority of channel - 4 - 2 + RSA_MEM_FORCE_PU + Set this bit to force power up rsa internal memory + 1 + 1 read-write - INTER_IN_ARB_PRIORITY_CH4 - Set the priority of channel - 6 - 3 + RSA_MEM_PD + Set this bit to force power down rsa internal memory. + 2 + 1 read-write - IN_ETM_CONF_CH4 - RX CH4 ETM config register - 0x948 + ECC_PD_CTRL + ecc pd ctrl register + 0x1D4 0x20 - 0x00000004 + 0x00000002 - IN_ETM_EN_CH4 - Set this bit to 1 to enable ETM task function + ECC_MEM_FORCE_PD + Set this bit to power down ecc internal memory. 0 1 read-write - IN_ETM_LOOP_EN_CH4 - when this bit is 1, dscr can be processed after receiving a task + ECC_MEM_FORCE_PU + Set this bit to force power up ecc internal memory 1 1 read-write - IN_DSCR_TASK_MAK_CH4 - ETM dscr_ready maximum cache numbers + ECC_MEM_PD + Set this bit to force power down ecc internal memory. 2 - 2 + 1 read-write - IN_FIFO_CNT_CH4 - rx CH4 fifo cnt register - 0x980 + RNG_CFG + rng cfg register + 0x1D8 0x20 - IN_CMDFIFO_INFIFO_CNT_CH4 - only for debug + RNG_SAMPLE_ENABLE + enable rng sample chain 0 - 10 + 1 + read-write + + + RNG_CHAIN_CLK_DIV_NUM + chain clk div num to pad for debug + 16 + 8 + read-write + + + RNG_SAMPLE_CNT + debug rng sample cnt + 24 + 8 read-only - IN_POP_DATA_CNT_CH4 - rx CH4 pop data cnt register - 0x984 + UART_PD_CTRL + ecc pd ctrl register + 0x1DC 0x20 - 0x00000007 + 0x00000002 - IN_CMDFIFO_POP_DATA_CNT_CH4 - only for debug + UART_MEM_FORCE_PD + Set this bit to power down hp uart internal memory. 0 - 8 - read-only + 1 + read-write + + + UART_MEM_FORCE_PU + Set this bit to force power up hp uart internal memory + 1 + 1 + read-write - IN_XADDR_CH4 - rx CH4 xaddr register - 0x988 + PERI_MEM_CLK_FORCE_ON + hp peri mem clk force on regpster + 0x1E0 0x20 - IN_CMDFIFO_XADDR_CH4 - only for debug + RMT_MEM_CLK_FORCE_ON + Set this bit to force on mem clk in rmt 0 - 32 - read-only + 1 + read-write + + + BITSCRAMBLER_TX_MEM_CLK_FORCE_ON + Set this bit to force on tx mem clk in bitscrambler + 1 + 1 + read-write + + + BITSCRAMBLER_RX_MEM_CLK_FORCE_ON + Set this bit to force on rx mem clk in bitscrambler + 2 + 1 + read-write + + + GDMA_MEM_CLK_FORCE_ON + Set this bit to force on mem clk in gdma + 3 + 1 + read-write + + + + HP_SYS_CLKRST + HP_SYS_CLKRST Peripheral + HP_SYS_CLKRST + 0x500E6000 + + 0x0 + 0xF0 + registers + + - IN_BUF_HB_RCV_CH4 - rx CH4 buf len hb rcv register - 0x98C + CLK_EN0 + Reserved + 0x0 0x20 + 0x00000001 - IN_CMDFIFO_BUF_HB_RCV_CH4 - only for debug + REG_CLK_EN + Reserved 0 - 29 - read-only + 1 + read-write - IN_CONF0_CH5 - RX CH5 config0 register - 0xA00 + ROOT_CLK_CTRL0 + Reserved + 0x4 0x20 - IN_ECC_AES_EN_CH5 - When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned. - 3 - 1 + REG_CPUICM_DELAY_NUM + Reserved + 0 + 4 read-write - IN_MEM_BURST_LENGTH_CH5 - Block size of Rx channel 1. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes - 6 - 3 - read-write + REG_SOC_CLK_DIV_UPDATE + Reserved + 4 + 1 + write-only - IN_PAGE_BOUND_EN_CH5 - Set this bit to 1 to make sure AXI write data don't cross the address boundary which define by mem_burst_length - 12 - 1 + REG_CPU_CLK_DIV_NUM + Reserved + 5 + 8 read-write - IN_RST_CH5 - Write 1 then write 0 to this bit to reset Rx channel - 24 - 1 + REG_CPU_CLK_DIV_NUMERATOR + Reserved + 13 + 8 read-write - IN_CMD_DISABLE_CH5 - Write 1 before reset and write 0 after reset - 25 - 1 + REG_CPU_CLK_DIV_DENOMINATOR + Reserved + 21 + 8 read-write - IN_CONF1_CH5 - RX CH5 config1 register - 0xA04 + ROOT_CLK_CTRL1 + Reserved + 0x8 0x20 + 0x00000001 - BLOCK_START_ADDR_CH5 - RX Channel 5 destination start address + REG_MEM_CLK_DIV_NUM + Reserved 0 - 32 + 8 + read-write + + + REG_MEM_CLK_DIV_NUMERATOR + Reserved + 8 + 8 + read-write + + + REG_MEM_CLK_DIV_DENOMINATOR + Reserved + 16 + 8 + read-write + + + REG_SYS_CLK_DIV_NUM + Reserved + 24 + 8 read-write - IN_CONF2_CH5 - RX CH5 config2 register - 0xA08 + ROOT_CLK_CTRL2 + Reserved + 0xC 0x20 - 0x3C007800 + 0x00010000 - BLOCK_ROW_LENGTH_12LINE_CH5 - The number of bytes contained in a row block 12line in RX channel 5 + REG_SYS_CLK_DIV_NUMERATOR + Reserved 0 - 16 + 8 read-write - BLOCK_ROW_LENGTH_4LINE_CH5 - The number of bytes contained in a row block 4line in RX channel 5 + REG_SYS_CLK_DIV_DENOMINATOR + Reserved + 8 + 8 + read-write + + + REG_APB_CLK_DIV_NUM + Reserved 16 - 16 + 8 + read-write + + + REG_APB_CLK_DIV_NUMERATOR + Reserved + 24 + 8 read-write - IN_CONF3_CH5 - RX CH5 config3 register - 0xA0C + ROOT_CLK_CTRL3 + Reserved + 0x10 0x20 - 0x00200100 - BLOCK_LENGTH_12LINE_CH5 - The number of bytes contained in a block 12line + REG_APB_CLK_DIV_DENOMINATOR + Reserved 0 - 14 - read-write - - - BLOCK_LENGTH_4LINE_CH5 - The number of bytes contained in a block 4line - 14 - 14 + 8 read-write - IN_INT_RAW_CH5 - RX CH5 interrupt raw register - 0xA10 + SOC_CLK_CTRL0 + Reserved + 0x14 0x20 + 0xE6DF97AF - IN_DONE_CH5_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been transmitted to peripherals for Rx channel 1. + REG_CORE0_CLIC_CLK_EN + Reserved 0 1 read-write - IN_SUC_EOF_CH5_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1. + REG_CORE1_CLIC_CLK_EN + Reserved 1 1 read-write - INFIFO_OVF_L1_CH5_INT_RAW - This raw interrupt bit turns to high level when fifo of Rx channel is overflow. + REG_MISC_CPU_CLK_EN + Reserved 2 1 read-write - INFIFO_UDF_L1_CH5_INT_RAW - This raw interrupt bit turns to high level when fifo of Rx channel is underflow. + REG_CORE0_CPU_CLK_EN + Reserved 3 1 read-write - FETCH_MB_COL_CNT_OVF_CH5_INT_RAW - This raw interrupt bit turns to high level when fifo of Rx channel is underflow. + REG_CORE1_CPU_CLK_EN + Reserved 4 1 read-write - - - - IN_INT_ENA_CH5 - RX CH5 interrupt ena register - 0xA14 - 0x20 - - IN_DONE_CH5_INT_ENA - The interrupt enable bit for the IN_DONE_CH_INT interrupt. - 0 + REG_TCM_CPU_CLK_EN + Reserved + 5 1 read-write - IN_SUC_EOF_CH5_INT_ENA - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. - 1 + REG_BUSMON_CPU_CLK_EN + Reserved + 6 1 read-write - INFIFO_OVF_L1_CH5_INT_ENA - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. - 2 + REG_L1CACHE_CPU_CLK_EN + Reserved + 7 1 read-write - INFIFO_UDF_L1_CH5_INT_ENA - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. - 3 + REG_L1CACHE_D_CPU_CLK_EN + Reserved + 8 1 read-write - FETCH_MB_COL_CNT_OVF_CH5_INT_ENA - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. - 4 + REG_L1CACHE_I0_CPU_CLK_EN + Reserved + 9 1 read-write - - - - IN_INT_ST_CH5 - RX CH5 interrupt st register - 0xA18 - 0x20 - - IN_DONE_CH5_INT_ST - The raw interrupt status bit for the IN_DONE_CH_INT interrupt. - 0 + REG_L1CACHE_I1_CPU_CLK_EN + Reserved + 10 1 - read-only + read-write - IN_SUC_EOF_CH5_INT_ST - The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. - 1 + REG_TRACE_CPU_CLK_EN + Reserved + 11 1 - read-only + read-write - INFIFO_OVF_L1_CH5_INT_ST - The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. - 2 + REG_ICM_CPU_CLK_EN + Reserved + 12 1 - read-only + read-write - INFIFO_UDF_L1_CH5_INT_ST - The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. - 3 + REG_GDMA_CPU_CLK_EN + Reserved + 13 1 - read-only + read-write - FETCH_MB_COL_CNT_OVF_CH5_INT_ST - The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. - 4 + REG_VPU_CPU_CLK_EN + Reserved + 14 1 - read-only + read-write - - - - IN_INT_CLR_CH5 - RX CH5 interrupt clr register - 0xA1C - 0x20 - - IN_DONE_CH5_INT_CLR - Set this bit to clear the IN_DONE_CH_INT interrupt. - 0 + REG_L1CACHE_MEM_CLK_EN + Reserved + 15 1 - write-only + read-write - IN_SUC_EOF_CH5_INT_CLR - Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. - 1 + REG_L1CACHE_D_MEM_CLK_EN + Reserved + 16 1 - write-only + read-write - INFIFO_OVF_L1_CH5_INT_CLR - Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. - 2 + REG_L1CACHE_I0_MEM_CLK_EN + Reserved + 17 1 - write-only + read-write - INFIFO_UDF_L1_CH5_INT_CLR - Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. - 3 + REG_L1CACHE_I1_MEM_CLK_EN + Reserved + 18 1 - write-only + read-write - FETCH_MB_COL_CNT_OVF_CH5_INT_CLR - Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. - 4 + REG_L2CACHE_MEM_CLK_EN + Reserved + 19 1 - write-only + read-write - - - - INFIFO_STATUS_CH5 - RX CH5 INFIFO status register - 0xA20 - 0x20 - 0x00000002 - - INFIFO_FULL_L1_CH5 - Tx FIFO full signal for Tx channel 1. - 0 + REG_L2MEM_MEM_CLK_EN + Reserved + 20 1 - read-only + read-write - INFIFO_EMPTY_L1_CH5 - Tx FIFO empty signal for Tx channel 1. - 1 + REG_L2MEMMON_MEM_CLK_EN + Reserved + 21 1 - read-only + read-write - INFIFO_CNT_L1_CH5 - The register stores the byte number of the data in Tx FIFO for Tx channel 1. - 2 - 5 - read-only + REG_ICM_MEM_CLK_EN + Reserved + 22 + 1 + read-write - - - - IN_POP_CH5 - RX CH5 INFIFO pop register - 0xA24 - 0x20 - 0x00000400 - - INFIFO_RDATA_CH5 - This register stores the data popping from DMA Rx FIFO. - 0 - 11 - read-only + REG_MISC_SYS_CLK_EN + Reserved + 23 + 1 + read-write - INFIFO_POP_CH5 - Set this bit to pop data from DMA Rx FIFO. - 11 + REG_TRACE_SYS_CLK_EN + Reserved + 24 1 read-write - - - - IN_STATE_CH5 - RX CH5 state register - 0xA28 - 0x20 - 0x00000008 - - IN_STATE_CH5 - This register stores the current control module state machine state. - 0 - 3 - read-only + REG_L2CACHE_SYS_CLK_EN + Reserved + 25 + 1 + read-write - IN_RESET_AVAIL_CH5 - This register indicate that if the channel reset is safety. - 3 + REG_L2MEM_SYS_CLK_EN + Reserved + 26 1 - read-only + read-write - - - - IN_ARB_CH5 - RX CH5 arb register - 0xA40 - 0x20 - 0x00000041 - - IN_ARB_TOKEN_NUM_CH5 - Set the max number of token count of arbiter - 0 - 4 + REG_L2MEMMON_SYS_CLK_EN + Reserved + 27 + 1 read-write - INTER_IN_ARB_PRIORITY_CH5 - Set the priority of channel - 6 - 3 + REG_TCMMON_SYS_CLK_EN + Reserved + 28 + 1 read-write - - - - IN_FIFO_CNT_CH5 - rx CH5 fifo cnt register - 0xA80 - 0x20 - - IN_CMDFIFO_INFIFO_CNT_CH5 - only for debug - 0 - 10 - read-only + REG_ICM_SYS_CLK_EN + Reserved + 29 + 1 + read-write - - - - IN_POP_DATA_CNT_CH5 - rx CH5 pop data cnt register - 0xA84 - 0x20 - 0x000000FF - - IN_CMDFIFO_POP_DATA_CNT_CH5 - only for debug - 0 - 8 - read-only + REG_FLASH_SYS_CLK_EN + Reserved + 30 + 1 + read-write - - - - IN_XADDR_CH5 - rx CH5 xaddr register - 0xA88 - 0x20 - - IN_CMDFIFO_XADDR_CH5 - only for debug - 0 - 32 - read-only + REG_PSRAM_SYS_CLK_EN + Reserved + 31 + 1 + read-write - IN_BUF_HB_RCV_CH5 - rx CH5 buf len hb rcv register - 0xA8C + SOC_CLK_CTRL1 + Reserved + 0x18 0x20 + 0x7C7F801F - IN_CMDFIFO_BUF_HB_RCV_CH5 - only for debug + REG_GPSPI2_SYS_CLK_EN + Reserved 0 - 29 - read-only + 1 + read-write - - - - INTER_AXI_ERR - inter memory axi err register - 0xB00 - 0x20 - - INTER_RID_ERR_CNT - AXI read id err cnt - 0 - 4 - read-only + REG_GPSPI3_SYS_CLK_EN + Reserved + 1 + 1 + read-write - INTER_RRESP_ERR_CNT - AXI read resp err cnt - 4 - 4 - read-only + REG_REGDMA_SYS_CLK_EN + Reserved + 2 + 1 + read-write - INTER_WRESP_ERR_CNT - AXI write resp err cnt - 8 - 4 - read-only + REG_AHB_PDMA_SYS_CLK_EN + Reserved + 3 + 1 + read-write - INTER_RD_FIFO_CNT - AXI read cmd fifo remain cmd count - 12 - 3 - read-only + REG_AXI_PDMA_SYS_CLK_EN + Reserved + 4 + 1 + read-write - INTER_RD_BAK_FIFO_CNT - AXI read backup cmd fifo remain cmd count - 15 - 4 - read-only + REG_GDMA_SYS_CLK_EN + Reserved + 5 + 1 + read-write - INTER_WR_FIFO_CNT - AXI write cmd fifo remain cmd count - 19 - 3 - read-only + REG_DMA2D_SYS_CLK_EN + Reserved + 6 + 1 + read-write - INTER_WR_BAK_FIFO_CNT - AXI write backup cmd fifo remain cmd count - 22 - 4 - read-only - - - - - EXTER_AXI_ERR - exter memory axi err register - 0xB04 - 0x20 - - - EXTER_RID_ERR_CNT - AXI read id err cnt - 0 - 4 - read-only + REG_VPU_SYS_CLK_EN + Reserved + 7 + 1 + read-write - EXTER_RRESP_ERR_CNT - AXI read resp err cnt - 4 - 4 - read-only + REG_JPEG_SYS_CLK_EN + Reserved + 8 + 1 + read-write - EXTER_WRESP_ERR_CNT - AXI write resp err cnt - 8 - 4 - read-only + REG_PPA_SYS_CLK_EN + Reserved + 9 + 1 + read-write - EXTER_RD_FIFO_CNT - AXI read cmd fifo remain cmd count - 12 - 3 - read-only + REG_CSI_BRG_SYS_CLK_EN + Reserved + 10 + 1 + read-write - EXTER_RD_BAK_FIFO_CNT - AXI read backup cmd fifo remain cmd count - 15 - 4 - read-only + REG_CSI_HOST_SYS_CLK_EN + Reserved + 11 + 1 + read-write - EXTER_WR_FIFO_CNT - AXI write cmd fifo remain cmd count - 19 - 3 - read-only + REG_DSI_SYS_CLK_EN + Reserved + 12 + 1 + read-write - EXTER_WR_BAK_FIFO_CNT - AXI write backup cmd fifo remain cmd count - 22 - 4 - read-only + REG_EMAC_SYS_CLK_EN + Reserved + 13 + 1 + read-write - - - - RST_CONF - axi reset config register - 0xB08 - 0x20 - - INTER_AXIM_RD_RST - Write 1 then write 0 to this bit to reset axi master read data FIFO. - 0 + REG_SDMMC_SYS_CLK_EN + Reserved + 14 1 read-write - INTER_AXIM_WR_RST - Write 1 then write 0 to this bit to reset axi master write data FIFO. - 1 + REG_USB_OTG11_SYS_CLK_EN + Reserved + 15 1 read-write - EXTER_AXIM_RD_RST - Write 1 then write 0 to this bit to reset axi master read data FIFO. - 2 + REG_USB_OTG20_SYS_CLK_EN + Reserved + 16 1 read-write - EXTER_AXIM_WR_RST - Write 1 then write 0 to this bit to reset axi master write data FIFO. - 3 + REG_UHCI_SYS_CLK_EN + Reserved + 17 1 read-write - CLK_EN - 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers. - 4 + REG_UART0_SYS_CLK_EN + Reserved + 18 1 read-write - - - - INTER_MEM_START_ADDR0 - Start address of inter memory range0 register - 0xB0C - 0x20 - 0x30100000 - - ACCESS_INTER_MEM_START_ADDR0 - The start address of accessible address space. - 0 - 32 + REG_UART1_SYS_CLK_EN + Reserved + 19 + 1 read-write - - - - INTER_MEM_END_ADDR0 - end address of inter memory range0 register - 0xB10 - 0x20 - 0x8FFFFFFF - - ACCESS_INTER_MEM_END_ADDR0 - The end address of accessible address space. The access address beyond this range would lead to descriptor error. - 0 - 32 + REG_UART2_SYS_CLK_EN + Reserved + 20 + 1 read-write - - - - INTER_MEM_START_ADDR1 - Start address of inter memory range1 register - 0xB14 - 0x20 - 0x30100000 - - ACCESS_INTER_MEM_START_ADDR1 - The start address of accessible address space. - 0 - 32 + REG_UART3_SYS_CLK_EN + Reserved + 21 + 1 read-write - - - - INTER_MEM_END_ADDR1 - end address of inter memory range1 register - 0xB18 - 0x20 - 0x8FFFFFFF - - ACCESS_INTER_MEM_END_ADDR1 - The end address of accessible address space. The access address beyond this range would lead to descriptor error. - 0 - 32 + REG_UART4_SYS_CLK_EN + Reserved + 22 + 1 read-write - - - - EXTER_MEM_START_ADDR0 - Start address of exter memory range0 register - 0xB20 - 0x20 - 0x30100000 - - ACCESS_EXTER_MEM_START_ADDR0 - The start address of accessible address space. - 0 - 32 + REG_PARLIO_SYS_CLK_EN + Reserved + 23 + 1 read-write - - - - EXTER_MEM_END_ADDR0 - end address of exter memory range0 register - 0xB24 - 0x20 - 0x8FFFFFFF - - ACCESS_EXTER_MEM_END_ADDR0 - The end address of accessible address space. The access address beyond this range would lead to descriptor error. - 0 - 32 + REG_ETM_SYS_CLK_EN + Reserved + 24 + 1 read-write - - - - EXTER_MEM_START_ADDR1 - Start address of exter memory range1 register - 0xB28 - 0x20 - 0x30100000 - - ACCESS_EXTER_MEM_START_ADDR1 - The start address of accessible address space. - 0 - 32 + REG_PVT_SYS_CLK_EN + Reserved + 25 + 1 read-write - - - - EXTER_MEM_END_ADDR1 - end address of exter memory range1 register - 0xB2C - 0x20 - 0x8FFFFFFF - - ACCESS_EXTER_MEM_END_ADDR1 - The end address of accessible address space. The access address beyond this range would lead to descriptor error. - 0 - 32 + REG_CRYPTO_SYS_CLK_EN + Reserved + 26 + 1 read-write - - - - OUT_ARB_CONFIG - reserved - 0xB30 - 0x20 - - OUT_ARB_TIMEOUT_NUM - Set the max number of timeout count of arbiter - 0 - 16 + REG_KEY_MANAGER_SYS_CLK_EN + Reserved + 27 + 1 read-write - OUT_WEIGHT_EN - reserved - 16 + REG_BITSRAMBLER_SYS_CLK_EN + Reserved + 28 1 read-write - - - - IN_ARB_CONFIG - reserved - 0xB34 - 0x20 - - IN_ARB_TIMEOUT_NUM - Set the max number of timeout count of arbiter - 0 - 16 + REG_BITSRAMBLER_RX_SYS_CLK_EN + Reserved + 29 + 1 read-write - IN_WEIGHT_EN - reserved - 16 + REG_BITSRAMBLER_TX_SYS_CLK_EN + Reserved + 30 1 read-write - - - - DATE - reserved - 0xB3C - 0x20 - 0x20230403 - - DATE - register version. - 0 - 32 + REG_H264_SYS_CLK_EN + Reserved + 31 + 1 read-write - COUNTER_RST - counter reset register - 0xB50 + SOC_CLK_CTRL2 + Reserved + 0x1C 0x20 + 0x20F80FDE - RX_CH0_EXTER_COUNTER_RST - Write 1 then write 0 to this bit to reset rx ch0 counter. + REG_RMT_SYS_CLK_EN + Reserved 0 1 read-write - RX_CH1_EXTER_COUNTER_RST - Write 1 then write 0 to this bit to reset rx ch1 counter. + REG_HP_CLKRST_APB_CLK_EN + Reserved 1 1 read-write - RX_CH2_INTER_COUNTER_RST - Write 1 then write 0 to this bit to reset rx ch2 counter. + REG_SYSREG_APB_CLK_EN + Reserved 2 1 read-write - RX_CH5_INTER_COUNTER_RST - Write 1 then write 0 to this bit to reset rx ch5 counter. + REG_ICM_APB_CLK_EN + Reserved 3 1 read-write - - - - RX_CH0_COUNTER - rx ch0 counter register - 0xB54 - 0x20 - - RX_CH0_CNT - rx ch0 counter register - 0 - 23 - read-only + REG_INTRMTX_APB_CLK_EN + Reserved + 4 + 1 + read-write - - - - RX_CH1_COUNTER - rx ch1 counter register - 0xB58 - 0x20 - - RX_CH1_CNT - rx ch1 counter register - 0 - 21 - read-only + REG_ADC_APB_CLK_EN + Reserved + 5 + 1 + read-write - - - - RX_CH2_COUNTER - rx ch2 counter register - 0xB5C - 0x20 - - RX_CH2_CNT - rx ch2 counter register - 0 - 11 - read-only + REG_UHCI_APB_CLK_EN + Reserved + 6 + 1 + read-write - - - - RX_CH5_COUNTER - rx ch5 counter register - 0xB60 - 0x20 - - RX_CH5_CNT - rx ch5 counter register - 0 - 17 - read-only + REG_UART0_APB_CLK_EN + Reserved + 7 + 1 + read-write - - - - - - HMAC - HMAC (Hash-based Message Authentication Code) Accelerator - HMAC - 0x50095000 - - 0x0 - 0xA4 - registers - - - - SET_START - Process control register 0. - 0x40 - 0x20 - - SET_START - Start hmac operation. - 0 + REG_UART1_APB_CLK_EN + Reserved + 8 1 - write-only + read-write - - - - SET_PARA_PURPOSE - Configure purpose. - 0x44 - 0x20 - - PURPOSE_SET - Set hmac parameter purpose. - 0 - 4 - write-only + REG_UART2_APB_CLK_EN + Reserved + 9 + 1 + read-write - - - - SET_PARA_KEY - Configure key. - 0x48 - 0x20 - - KEY_SET - Set hmac parameter key. - 0 - 3 - write-only + REG_UART3_APB_CLK_EN + Reserved + 10 + 1 + read-write - - - - SET_PARA_FINISH - Finish initial configuration. - 0x4C - 0x20 - - SET_PARA_END - Finish hmac configuration. - 0 + REG_UART4_APB_CLK_EN + Reserved + 11 1 - write-only + read-write - - - - SET_MESSAGE_ONE - Process control register 1. - 0x50 - 0x20 - - SET_TEXT_ONE - Call SHA to calculate one message block. - 0 + REG_I2C0_APB_CLK_EN + Reserved + 12 1 - write-only + read-write - - - - SET_MESSAGE_ING - Process control register 2. - 0x54 - 0x20 - - SET_TEXT_ING - Continue typical hmac. - 0 + REG_I2C1_APB_CLK_EN + Reserved + 13 1 - write-only + read-write - - - - SET_MESSAGE_END - Process control register 3. - 0x58 - 0x20 - - SET_TEXT_END - Start hardware padding. - 0 + REG_I2S0_APB_CLK_EN + Reserved + 14 1 - write-only + read-write - - - - SET_RESULT_FINISH - Process control register 4. - 0x5C - 0x20 - - SET_RESULT_END - After read result from upstream, then let hmac back to idle. - 0 + REG_I2S1_APB_CLK_EN + Reserved + 15 1 - write-only + read-write - - - - SET_INVALIDATE_JTAG - Invalidate register 0. - 0x60 - 0x20 - - SET_INVALIDATE_JTAG - Clear result from hmac downstream JTAG. - 0 + REG_I2S2_APB_CLK_EN + Reserved + 16 1 - write-only + read-write - - - - SET_INVALIDATE_DS - Invalidate register 1. - 0x64 - 0x20 - - SET_INVALIDATE_DS - Clear result from hmac downstream DS. - 0 + REG_I3C_MST_APB_CLK_EN + Reserved + 17 1 - write-only + read-write - - - - QUERY_ERROR - Error register. - 0x68 - 0x20 - - QUERY_CHECK - Hmac configuration state. 0: key are agree with purpose. 1: error - 0 + REG_I3C_SLV_APB_CLK_EN + Reserved + 18 1 - read-only + read-write - - - - QUERY_BUSY - Busy register. - 0x6C - 0x20 - - BUSY_STATE - Hmac state. 1'b0: idle. 1'b1: busy - 0 + REG_GPSPI2_APB_CLK_EN + Reserved + 19 1 - read-only + read-write - - - - 64 - 0x1 - WR_MESSAGE_MEM[%s] - Message block memory. - 0x80 - 0x8 - - - 32 - 0x1 - RD_RESULT_MEM[%s] - Result from upstream. - 0xC0 - 0x8 - - - SET_MESSAGE_PAD - Process control register 5. - 0xF0 - 0x20 - - SET_TEXT_PAD - Start software padding. - 0 + REG_GPSPI3_APB_CLK_EN + Reserved + 20 1 - write-only + read-write - - - - ONE_BLOCK - Process control register 6. - 0xF4 - 0x20 - - SET_ONE_BLOCK - Don't have to do padding. - 0 + REG_TIMERGRP0_APB_CLK_EN + Reserved + 21 1 - write-only + read-write - - - - SOFT_JTAG_CTRL - Jtag register 0. - 0xF8 - 0x20 - - SOFT_JTAG_CTRL - Turn on JTAG verification. - 0 + REG_TIMERGRP1_APB_CLK_EN + Reserved + 22 1 - write-only + read-write - - - - WR_JTAG - Jtag register 1. - 0xFC - 0x20 - - WR_JTAG - 32-bit of key to be compared. - 0 - 32 - write-only + REG_SYSTIMER_APB_CLK_EN + Reserved + 23 + 1 + read-write - - - - DATE - Date register. - 0x1FC - 0x20 - 0x20200618 - - DATE - Hmac date information/ hmac version information. - 0 - 30 + REG_TWAI0_APB_CLK_EN + Reserved + 24 + 1 read-write - - - - - - HP_SYS - High-Power System - HP_SYS - 0x500E5000 - - 0x0 - 0x16C - registers - - - HP_SYS - 110 - - - - VER_DATE - NA - 0x0 - 0x20 - 0x20230519 - - HP_REG_VER_DATE - NA - 0 - 32 + REG_TWAI1_APB_CLK_EN + Reserved + 25 + 1 read-write - - - - HP_CLK_EN - NA - 0x4 - 0x20 - - HP_REG_CLK_EN - NA - 0 + REG_TWAI2_APB_CLK_EN + Reserved + 26 1 read-write - - - - HP_CPU_INT_FROM_CPU_0 - NA - 0x10 - 0x20 - - HP_CPU_INT_FROM_CPU_0 - set 1 will triger a interrupt - 0 + REG_MCPWM0_APB_CLK_EN + Reserved + 27 1 read-write - - - - HP_CPU_INT_FROM_CPU_1 - NA - 0x14 - 0x20 - - HP_CPU_INT_FROM_CPU_1 - set 1 will triger a interrupt - 0 + REG_MCPWM1_APB_CLK_EN + Reserved + 28 1 read-write - - - - HP_CPU_INT_FROM_CPU_2 - NA - 0x18 - 0x20 - - HP_CPU_INT_FROM_CPU_2 - set 1 will triger a interrupt - 0 + REG_USB_DEVICE_APB_CLK_EN + Reserved + 29 1 read-write - - - - HP_CPU_INT_FROM_CPU_3 - NA - 0x1C - 0x20 - - HP_CPU_INT_FROM_CPU_3 - set 1 will triger a interrupt - 0 + REG_PCNT_APB_CLK_EN + Reserved + 30 + 1 + read-write + + + REG_PARLIO_APB_CLK_EN + Reserved + 31 1 read-write - HP_CACHE_CLK_CONFIG - NA + SOC_CLK_CTRL3 + Reserved 0x20 0x20 - 0x00000033 + 0x00000008 - HP_REG_L2_CACHE_CLK_ON - l2 cahce clk enable + REG_LEDC_APB_CLK_EN + Reserved 0 1 read-write - HP_REG_L1_D_CACHE_CLK_ON - l1 dcahce clk enable + REG_LCDCAM_APB_CLK_EN + Reserved 1 1 read-write - HP_REG_L1_I1_CACHE_CLK_ON - l1 icahce1 clk enable - 4 + REG_ETM_APB_CLK_EN + Reserved + 2 1 read-write - HP_REG_L1_I0_CACHE_CLK_ON - l1 icahce0 clk enable - 5 + REG_IOMUX_APB_CLK_EN + Reserved + 3 1 read-write - HP_CACHE_RESET_CONFIG - NA + REF_CLK_CTRL0 + Reserved 0x24 0x20 + 0x02011309 - HP_REG_L1_D_CACHE_RESET - set 1 to reset l1 dcahce - 1 - 1 + REG_REF_50M_CLK_DIV_NUM + Reserved + 0 + 8 read-write - HP_REG_L1_I1_CACHE_RESET - set 1 to reset l1 icahce1 - 4 - 1 + REG_REF_25M_CLK_DIV_NUM + Reserved + 8 + 8 read-write - HP_REG_L1_I0_CACHE_RESET - set 1 to reset l1 icahce0 - 5 - 1 + REG_REF_240M_CLK_DIV_NUM + Reserved + 16 + 8 read-write - - - - DMA_ADDR_CTRL - NA - 0x2C - 0x20 - - HP_REG_SYS_DMA_ADDR_SEL - 0 means dma access extmem use 8xxx_xxxx else use 4xxx_xxxx - 0 - 1 + REG_REF_160M_CLK_DIV_NUM + Reserved + 24 + 8 read-write - HP_TCM_RAM_WRR_CONFIG - NA - 0x34 + REF_CLK_CTRL1 + Reserved + 0x28 0x20 - 0x826ED93F + 0x58170503 - HP_REG_TCM_RAM_IBUS0_WT - weight value of ibus0 + REG_REF_120M_CLK_DIV_NUM + Reserved 0 - 3 + 8 read-write - HP_REG_TCM_RAM_IBUS1_WT - weight value of ibus1 - 3 - 3 + REG_REF_80M_CLK_DIV_NUM + Reserved + 8 + 8 read-write - HP_REG_TCM_RAM_IBUS2_WT - weight value of ibus2 - 6 - 3 + REG_REF_20M_CLK_DIV_NUM + Reserved + 16 + 8 read-write - HP_REG_TCM_RAM_IBUS3_WT - weight value of ibus3 - 9 - 3 + REG_TM_400M_CLK_EN + Reserved + 24 + 1 read-write - HP_REG_TCM_RAM_DBUS0_WT - weight value of dbus0 - 12 - 3 + REG_TM_200M_CLK_EN + Reserved + 25 + 1 read-write - HP_REG_TCM_RAM_DBUS1_WT - weight value of dbus1 - 15 - 3 + REG_TM_100M_CLK_EN + Reserved + 26 + 1 read-write - HP_REG_TCM_RAM_DBUS2_WT - weight value of dbus2 - 18 - 3 + REG_REF_50M_CLK_EN + Reserved + 27 + 1 read-write - HP_REG_TCM_RAM_DBUS3_WT - weight value of dbus3 - 21 - 3 + REG_REF_25M_CLK_EN + Reserved + 28 + 1 read-write - HP_REG_TCM_RAM_DMA_WT - weight value of dma - 24 - 3 + REG_TM_480M_CLK_EN + Reserved + 29 + 1 read-write - HP_REG_TCM_RAM_WRR_HIGH - enable weighted round robin arbitration + REG_REF_240M_CLK_EN + Reserved + 30 + 1 + read-write + + + REG_TM_240M_CLK_EN + Reserved 31 1 read-write @@ -57116,2843 +55251,2441 @@ - HP_TCM_SW_PARITY_BWE_MASK - NA - 0x38 + REF_CLK_CTRL2 + Reserved + 0x2C 0x20 + 0x00000115 - HP_REG_TCM_SW_PARITY_BWE_MASK_CTRL - Set 1 to mask tcm bwe parity code bit + REG_REF_160M_CLK_EN + Reserved 0 1 read-write - - - - HP_TCM_RAM_PWR_CTRL0 - NA - 0x3C - 0x20 - - HP_REG_HP_TCM_CLK_FORCE_ON - hp_tcm clk gatig force on - 0 + REG_TM_160M_CLK_EN + Reserved + 1 1 read-write - - - - HP_L2_ROM_PWR_CTRL0 - NA - 0x40 - 0x20 - - HP_REG_L2_ROM_CLK_FORCE_ON - l2_rom clk gating force on - 0 + REG_REF_120M_CLK_EN + Reserved + 2 1 read-write - - - - HP_PROBEA_CTRL - NA - 0x50 - 0x20 - - HP_REG_PROBE_A_MOD_SEL - Tihs field is used to selec probe_group from probe_group0 to probe_group15 for module's probe_out[31:0] in a mode - 0 - 16 + REG_TM_120M_CLK_EN + Reserved + 3 + 1 read-write - HP_REG_PROBE_A_TOP_SEL - Tihs field is used to selec module's probe_out[31:0] as probe out in a mode - 16 - 8 + REG_REF_80M_CLK_EN + Reserved + 4 + 1 read-write - HP_REG_PROBE_L_SEL - Tihs field is used to selec probe_out[31:16] - 24 - 2 + REG_TM_80M_CLK_EN + Reserved + 5 + 1 read-write - HP_REG_PROBE_H_SEL - Tihs field is used to selec probe_out[31:16] - 26 - 2 + REG_TM_60M_CLK_EN + Reserved + 6 + 1 read-write - HP_REG_PROBE_GLOBAL_EN - Set this bit to enable global debug probe in hp system. - 28 + REG_TM_48M_CLK_EN + Reserved + 7 1 read-write - - - - HP_PROBEB_CTRL - NA - 0x54 - 0x20 - - - HP_REG_PROBE_B_MOD_SEL - Tihs field is used to selec probe_group from probe_group0 to probe_group15 for module's probe_out[31:0] in b mode. - 0 - 16 - read-write - - HP_REG_PROBE_B_TOP_SEL - Tihs field is used to select module's probe_out[31:0] as probe_out in b mode - 16 - 8 + REG_REF_20M_CLK_EN + Reserved + 8 + 1 read-write - HP_REG_PROBE_B_EN - Set this bit to enable b mode for debug probe. 1: b mode, 0: a mode. - 24 + REG_TM_20M_CLK_EN + Reserved + 9 1 read-write - HP_PROBE_OUT - NA - 0x5C + PERI_CLK_CTRL00 + Reserved + 0x30 0x20 + 0x0000C03C - HP_REG_PROBE_TOP_OUT - NA + REG_FLASH_CLK_SRC_SEL + Reserved 0 - 32 - read-only + 2 + read-write - - - - HP_L2_MEM_RAM_PWR_CTRL0 - NA - 0x60 - 0x20 - - HP_REG_L2_MEM_CLK_FORCE_ON - l2ram clk_gating force on - 0 + REG_FLASH_PLL_CLK_EN + Reserved + 2 1 read-write - - - - HP_CPU_CORESTALLED_ST - NA - 0x64 - 0x20 - - HP_REG_CORE0_CORESTALLED_ST - hp core0 corestalled status - 0 + REG_FLASH_CORE_CLK_EN + Reserved + 3 1 - read-only + read-write - HP_REG_CORE1_CORESTALLED_ST - hp core1 corestalled status - 1 - 1 - read-only + REG_FLASH_CORE_CLK_DIV_NUM + Reserved + 4 + 8 + read-write - - - - HP_CRYPTO_CTRL - NA - 0x70 - 0x20 - - HP_REG_ENABLE_SPI_MANUAL_ENCRYPT - NA - 0 - 1 + REG_PSRAM_CLK_SRC_SEL + Reserved + 12 + 2 read-write - HP_REG_ENABLE_DOWNLOAD_DB_ENCRYPT - NA - 1 + REG_PSRAM_PLL_CLK_EN + Reserved + 14 1 read-write - HP_REG_ENABLE_DOWNLOAD_G0CB_DECRYPT - NA - 2 + REG_PSRAM_CORE_CLK_EN + Reserved + 15 1 read-write - HP_REG_ENABLE_DOWNLOAD_MANUAL_ENCRYPT - NA - 3 - 1 + REG_PSRAM_CORE_CLK_DIV_NUM + Reserved + 16 + 8 read-write - - - - HP_GPIO_O_HOLD_CTRL0 - NA - 0x74 - 0x20 - - HP_REG_GPIO_0_HOLD_LOW - hold control for gpio47~16 - 0 - 32 + REG_PAD_EMAC_REF_CLK_EN + Reserved + 24 + 1 read-write - - - - HP_GPIO_O_HOLD_CTRL1 - NA - 0x78 - 0x20 - - HP_REG_GPIO_0_HOLD_HIGH - hold control for gpio56~48 - 0 - 9 + REG_EMAC_RMII_CLK_SRC_SEL + Reserved + 25 + 2 read-write - - - - RDN_ECO_CS - NA - 0x7C - 0x20 - - HP_REG_HP_SYS_RDN_ECO_EN - NA - 0 + REG_EMAC_RMII_CLK_EN + Reserved + 27 1 read-write - HP_REG_HP_SYS_RDN_ECO_RESULT - NA - 1 + REG_EMAC_RX_CLK_SRC_SEL + Reserved + 28 1 - read-only + read-write - - - - HP_CACHE_APB_POSTW_EN - NA - 0x80 - 0x20 - - HP_REG_CACHE_APB_POSTW_EN - cache apb register interface post write enable, 1 will speed up write, but will take some time to update value to register - 0 + REG_EMAC_RX_CLK_EN + Reserved + 29 1 read-write - HP_L2_MEM_SUBSIZE - NA - 0x84 + PERI_CLK_CTRL01 + Reserved + 0x34 0x20 + 0x00000401 - HP_REG_L2_MEM_SUB_BLKSIZE - l2mem sub block size 00=>32 01=>64 10=>128 11=>256 + REG_EMAC_RX_CLK_DIV_NUM + Reserved 0 - 2 + 8 read-write - - - - HP_L2_MEM_INT_RAW - NA - 0x9C - 0x20 - - HP_REG_L2_MEM_ECC_ERR_INT_RAW - intr triggered when two bit error detected and corrected from ecc - 0 + REG_EMAC_TX_CLK_SRC_SEL + Reserved + 8 1 read-write - HP_REG_L2_MEM_EXCEED_ADDR_INT_RAW - intr triggered when access addr exceeds 0xff9ffff at bypass mode or exceeds 0xff80000 at l2cache 128kb mode or exceeds 0xff60000 at l2cache 256kb mode - 1 + REG_EMAC_TX_CLK_EN + Reserved + 9 1 read-write - HP_REG_L2_MEM_ERR_RESP_INT_RAW - intr triggered when err response occurs - 2 + REG_EMAC_TX_CLK_DIV_NUM + Reserved + 10 + 8 + read-write + + + REG_EMAC_PTP_REF_CLK_SRC_SEL + Reserved + 18 1 read-write - - - - HP_L2_MEM_INT_ST - NA - 0xA0 - 0x20 - - HP_REG_L2_MEM_ECC_ERR_INT_ST - NA - 0 + REG_EMAC_PTP_REF_CLK_EN + Reserved + 19 1 - read-only + read-write - HP_REG_L2_MEM_EXCEED_ADDR_INT_ST - NA - 1 + REG_EMAC_UNUSED0_CLK_EN + Reserved + 20 1 - read-only + read-write - HP_REG_L2_MEM_ERR_RESP_INT_ST - NA - 2 + REG_EMAC_UNUSED1_CLK_EN + Reserved + 21 1 - read-only + read-write - - - - HP_L2_MEM_INT_ENA - NA - 0xA4 - 0x20 - - HP_REG_L2_MEM_ECC_ERR_INT_ENA - NA - 0 + REG_SDIO_HS_MODE + Reserved + 22 1 read-write - HP_REG_L2_MEM_EXCEED_ADDR_INT_ENA - NA - 1 + REG_SDIO_LS_CLK_SRC_SEL + Reserved + 23 1 read-write - HP_REG_L2_MEM_ERR_RESP_INT_ENA - NA - 2 + REG_SDIO_LS_CLK_EN + Reserved + 24 1 read-write - HP_L2_MEM_INT_CLR - NA - 0xA8 + PERI_CLK_CTRL02 + Reserved + 0x38 0x20 - HP_REG_L2_MEM_ECC_ERR_INT_CLR - NA + REG_SDIO_LS_CLK_DIV_NUM + Reserved 0 - 1 - write-only + 8 + read-write - HP_REG_L2_MEM_EXCEED_ADDR_INT_CLR - NA - 1 + REG_SDIO_LS_CLK_EDGE_CFG_UPDATE + Reserved + 8 1 write-only - HP_REG_L2_MEM_ERR_RESP_INT_CLR - NA - 2 - 1 - write-only + REG_SDIO_LS_CLK_EDGE_L + Reserved + 9 + 4 + read-write - - - - HP_L2_MEM_L2_RAM_ECC - NA - 0xAC - 0x20 - - HP_REG_L2_RAM_UNIT0_ECC_EN - NA - 0 - 1 + REG_SDIO_LS_CLK_EDGE_H + Reserved + 13 + 4 read-write - HP_REG_L2_RAM_UNIT1_ECC_EN - NA - 1 - 1 + REG_SDIO_LS_CLK_EDGE_N + Reserved + 17 + 4 read-write - HP_REG_L2_RAM_UNIT2_ECC_EN - NA - 2 - 1 + REG_SDIO_LS_SLF_CLK_EDGE_SEL + Reserved + 21 + 2 read-write - HP_REG_L2_RAM_UNIT3_ECC_EN - NA - 3 - 1 + REG_SDIO_LS_DRV_CLK_EDGE_SEL + Reserved + 23 + 2 read-write - HP_REG_L2_RAM_UNIT4_ECC_EN - NA - 4 - 1 + REG_SDIO_LS_SAM_CLK_EDGE_SEL + Reserved + 25 + 2 read-write - HP_REG_L2_RAM_UNIT5_ECC_EN - NA - 5 + REG_SDIO_LS_SLF_CLK_EN + Reserved + 27 1 read-write - - - - HP_L2_MEM_INT_RECORD0 - NA - 0xB0 - 0x20 - - HP_REG_L2_MEM_EXCEED_ADDR_INT_ADDR - NA - 0 - 21 - read-only + REG_SDIO_LS_DRV_CLK_EN + Reserved + 28 + 1 + read-write - HP_REG_L2_MEM_EXCEED_ADDR_INT_WE - NA - 21 + REG_SDIO_LS_SAM_CLK_EN + Reserved + 29 1 - read-only + read-write - HP_REG_L2_MEM_EXCEED_ADDR_INT_MASTER - NA - 22 - 3 - read-only + REG_MIPI_DSI_DPHY_CLK_SRC_SEL + Reserved + 30 + 2 + read-write - HP_L2_MEM_INT_RECORD1 - NA - 0xB4 + PERI_CLK_CTRL03 + Reserved + 0x3C 0x20 - HP_REG_L2_MEM_ECC_ERR_INT_ADDR - NA + REG_MIPI_DSI_DPHY_CFG_CLK_EN + Reserved 0 - 15 - read-only - - - HP_REG_L2_MEM_ECC_ONE_BIT_ERR - NA - 15 1 - read-only + read-write - HP_REG_L2_MEM_ECC_TWO_BIT_ERR - NA - 16 + REG_MIPI_DSI_DPHY_PLL_REFCLK_EN + Reserved + 1 1 - read-only + read-write - HP_REG_L2_MEM_ECC_ERR_BIT - NA - 17 - 9 - read-only + REG_MIPI_CSI_DPHY_CLK_SRC_SEL + Reserved + 2 + 2 + read-write - HP_REG_L2_CACHE_ERR_BANK - NA - 26 + REG_MIPI_CSI_DPHY_CFG_CLK_EN + Reserved + 4 1 - read-only + read-write - - - - HP_L2_MEM_L2_CACHE_ECC - NA - 0xC4 - 0x20 - - HP_REG_L2_CACHE_ECC_EN - NA - 0 - 1 + REG_MIPI_DSI_DPICLK_SRC_SEL + Reserved + 5 + 2 read-write - - - - HP_L1CACHE_BUS0_ID - NA - 0xC8 - 0x20 - - HP_REG_L1_CACHE_BUS0_ID - NA - 0 - 4 + REG_MIPI_DSI_DPICLK_EN + Reserved + 7 + 1 read-write - - - - HP_L1CACHE_BUS1_ID - NA - 0xCC - 0x20 - - HP_REG_L1_CACHE_BUS1_ID - NA - 0 - 4 + REG_MIPI_DSI_DPICLK_DIV_NUM + Reserved + 8 + 8 read-write - HP_L2_MEM_RDN_ECO_CS - NA - 0xD8 + PERI_CLK_CTRL10 + Reserved + 0x40 0x20 - HP_REG_L2_MEM_RDN_ECO_EN - NA + REG_I2C0_CLK_SRC_SEL + Reserved 0 1 read-write - HP_REG_L2_MEM_RDN_ECO_RESULT - NA + REG_I2C0_CLK_EN + Reserved 1 1 - read-only + read-write - - - - HP_L2_MEM_RDN_ECO_LOW - NA - 0xDC - 0x20 - - HP_REG_L2_MEM_RDN_ECO_LOW - NA - 0 - 32 + REG_I2C0_CLK_DIV_NUM + Reserved + 2 + 8 read-write - - - - HP_L2_MEM_RDN_ECO_HIGH - NA - 0xE0 - 0x20 - 0xFFFFFFFF - - HP_REG_L2_MEM_RDN_ECO_HIGH - NA - 0 - 32 + REG_I2C0_CLK_DIV_NUMERATOR + Reserved + 10 + 8 read-write - - - - HP_TCM_RDN_ECO_CS - NA - 0xE4 - 0x20 - - HP_REG_HP_TCM_RDN_ECO_EN - NA - 0 + REG_I2C0_CLK_DIV_DENOMINATOR + Reserved + 18 + 8 + read-write + + + REG_I2C1_CLK_SRC_SEL + Reserved + 26 1 read-write - HP_REG_HP_TCM_RDN_ECO_RESULT - NA - 1 + REG_I2C1_CLK_EN + Reserved + 27 1 - read-only + read-write - HP_TCM_RDN_ECO_LOW - NA - 0xE8 + PERI_CLK_CTRL11 + Reserved + 0x44 0x20 - HP_REG_HP_TCM_RDN_ECO_LOW - NA + REG_I2C1_CLK_DIV_NUM + Reserved 0 - 32 + 8 read-write - - - - HP_TCM_RDN_ECO_HIGH - NA - 0xEC - 0x20 - 0xFFFFFFFF - - HP_REG_HP_TCM_RDN_ECO_HIGH - NA - 0 - 32 + REG_I2C1_CLK_DIV_NUMERATOR + Reserved + 8 + 8 read-write - - - - HP_GPIO_DED_HOLD_CTRL - NA - 0xF0 - 0x20 - - HP_REG_GPIO_DED_HOLD - hold control for gpio63~56 - 0 - 26 + REG_I2C1_CLK_DIV_DENOMINATOR + Reserved + 16 + 8 read-write - - - - HP_L2_MEM_SW_ECC_BWE_MASK - NA - 0xF4 - 0x20 - - HP_REG_L2_MEM_SW_ECC_BWE_MASK_CTRL - Set 1 to mask bwe hamming code bit - 0 + REG_I2S0_RX_CLK_EN + Reserved + 24 1 read-write + + REG_I2S0_RX_CLK_SRC_SEL + Reserved + 25 + 2 + read-write + - HP_USB20OTG_MEM_CTRL - NA - 0xF8 + PERI_CLK_CTRL12 + Reserved + 0x48 0x20 - HP_REG_USB20_MEM_CLK_FORCE_ON - NA + REG_I2S0_RX_DIV_N + Reserved 0 - 1 + 8 read-write - - - - HP_TCM_INT_RAW - need_des - 0xFC - 0x20 - - HP_TCM_PARITY_ERR_INT_RAW - need_des - 31 - 1 + REG_I2S0_RX_DIV_X + Reserved + 8 + 9 read-write - - - - HP_TCM_INT_ST - need_des - 0x100 - 0x20 - - HP_TCM_PARITY_ERR_INT_ST - need_des - 31 - 1 - read-only + REG_I2S0_RX_DIV_Y + Reserved + 17 + 9 + read-write - HP_TCM_INT_ENA - need_des - 0x104 + PERI_CLK_CTRL13 + Reserved + 0x4C 0x20 - HP_TCM_PARITY_ERR_INT_ENA - need_des - 31 + REG_I2S0_RX_DIV_Z + Reserved + 0 + 9 + read-write + + + REG_I2S0_RX_DIV_YN1 + Reserved + 9 1 read-write - - - - HP_TCM_INT_CLR - need_des - 0x108 - 0x20 - - HP_TCM_PARITY_ERR_INT_CLR - need_des - 31 + REG_I2S0_TX_CLK_EN + Reserved + 10 1 - write-only + read-write - - - - HP_TCM_PARITY_INT_RECORD - need_des - 0x10C - 0x20 - - HP_TCM_PARITY_ERR_INT_ADDR - hp tcm_parity_err_addr - 0 - 13 - read-only + REG_I2S0_TX_CLK_SRC_SEL + Reserved + 11 + 2 + read-write - - - - HP_L1_CACHE_PWR_CTRL - NA - 0x110 - 0x20 - - HP_REG_L1_CACHE_MEM_FO - need_des - 0 - 6 + REG_I2S0_TX_DIV_N + Reserved + 13 + 8 read-write - - - - HP_L2_CACHE_PWR_CTRL - NA - 0x114 - 0x20 - - HP_REG_L2_CACHE_MEM_FO - need_des - 0 - 2 + REG_I2S0_TX_DIV_X + Reserved + 21 + 9 read-write - HP_CPU_WAITI_CONF - CPU_WAITI configuration register - 0x118 + PERI_CLK_CTRL14 + Reserved + 0x50 0x20 - 0x00000001 - HP_CPU_WAIT_MODE_FORCE_ON - Set 1 to force cpu_waiti_clk enable. + REG_I2S0_TX_DIV_Y + Reserved 0 - 1 + 9 read-write - HP_CPU_WAITI_DELAY_NUM - This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk will close - 1 - 4 + REG_I2S0_TX_DIV_Z + Reserved + 9 + 9 read-write - - - - CORE_DEBUG_RUNSTALL_CONF - Core Debug runstall configure register - 0x11C - 0x20 - - CORE_DEBUG_RUNSTALL_ENABLE - Set this field to 1 to enable debug runstall feature between HP-core and LP-core. - 0 + REG_I2S0_TX_DIV_YN1 + Reserved + 18 1 read-write - - - - HP_CORE_AHB_TIMEOUT - need_des - 0x120 - 0x20 - 0x0001FFFF - - EN - set this field to 1 to enable hp core0&1 ahb timeout handle - 0 + REG_I2S0_MST_CLK_SEL + Reserved + 19 1 read-write - THRES - This field used to set hp core0&1 ahb bus timeout threshold - 1 - 16 + REG_I2S1_RX_CLK_EN + Reserved + 20 + 1 read-write - - - - HP_CORE_IBUS_TIMEOUT - need_des - 0x124 - 0x20 - 0x0001FFFF - - EN - set this field to 1 to enable hp core0&1 ibus timeout handle - 0 - 1 + REG_I2S1_RX_CLK_SRC_SEL + Reserved + 21 + 2 read-write - THRES - This field used to set hp core0&1 ibus timeout threshold - 1 - 16 + REG_I2S1_RX_DIV_N + Reserved + 23 + 8 read-write - HP_CORE_DBUS_TIMEOUT - need_des - 0x128 + PERI_CLK_CTRL15 + Reserved + 0x54 0x20 - 0x0001FFFF - EN - set this field to 1 to enable hp core0&1 dbus timeout handle + REG_I2S1_RX_DIV_X + Reserved 0 - 1 + 9 read-write - THRES - This field used to set hp core0&1 dbus timeout threshold - 1 - 16 + REG_I2S1_RX_DIV_Y + Reserved + 9 + 9 read-write - - - - HP_ICM_CPU_H2X_CFG - need_des - 0x138 - 0x20 - 0x00000003 - - HP_CPU_ICM_H2X_POST_WR_EN - need_des - 0 - 1 + REG_I2S1_RX_DIV_Z + Reserved + 18 + 9 read-write - HP_CPU_ICM_H2X_CUT_THROUGH_EN - need_des - 1 + REG_I2S1_RX_DIV_YN1 + Reserved + 27 1 read-write - HP_CPU_ICM_H2X_BRIDGE_BUSY - need_des - 2 + REG_I2S1_TX_CLK_EN + Reserved + 28 1 - read-only + read-write - - - - HP_PERI1_APB_POSTW_EN - NA - 0x13C - 0x20 - - HP_PERI1_APB_POSTW_EN - hp_peri1 apb register interface post write enable, 1 will speed up write, but will take some time to update value to register - 0 - 1 + REG_I2S1_TX_CLK_SRC_SEL + Reserved + 29 + 2 read-write - HP_BITSCRAMBLER_PERI_SEL - Bitscrambler Peri Sel - 0x140 + PERI_CLK_CTRL16 + Reserved + 0x58 0x20 - 0x000000FF - HP_BITSCRAMBLER_PERI_RX_SEL - Set this field to sel peri with DMA RX interface to connec with bitscrambler: 4'h0 : lcd_cam, 4'h1: gpspi2, 4'h2: gpspi3, 4'h3: parl_io, 4'h4: aes, 4'h5: sha, 4'h6: adc, 4'h7: i2s0, 4'h8: i2s1, 4'h9: i2s2, 4'ha: i3c_mst, 4'hb: uhci0, 4'hc: RMT, else : none + REG_I2S1_TX_DIV_N + Reserved 0 - 4 + 8 read-write - HP_BITSCRAMBLER_PERI_TX_SEL - Set this field to sel peri with DMA TX interface to connec with bitscrambler: 4'h0 : lcd_cam, 4'h1: gpspi2, 4'h2: gpspi3, 4'h3: parl_io, 4'h4: aes, 4'h5: sha, 4'h6: adc, 4'h7: i2s0, 4'h8: i2s1, 4'h9: i2s2, 4'ha: i3c_mst, 4'hb: uhci0, 4'hc: RMT, else : none - 4 - 4 + REG_I2S1_TX_DIV_X + Reserved + 8 + 9 + read-write + + + REG_I2S1_TX_DIV_Y + Reserved + 17 + 9 read-write - APB_SYNC_POSTW_EN - N/A - 0x144 + PERI_CLK_CTRL17 + Reserved + 0x5C 0x20 - GMAC_APB_POSTW_EN - N/A + REG_I2S1_TX_DIV_Z + Reserved 0 - 1 + 9 read-write - DSI_HOST_APB_POSTW_EN - N/A - 1 + REG_I2S1_TX_DIV_YN1 + Reserved + 9 1 read-write - CSI_HOST_APB_SYNC_POSTW_EN - N/A - 2 + REG_I2S1_MST_CLK_SEL + Reserved + 10 1 read-write - CSI_HOST_APB_ASYNC_POSTW_EN - N/A - 3 + REG_I2S2_RX_CLK_EN + Reserved + 11 1 read-write - - - - GDMA_CTRL - N/A - 0x148 - 0x20 - - DEBUG_CH_NUM - N/A - 0 + REG_I2S2_RX_CLK_SRC_SEL + Reserved + 12 2 read-write + + REG_I2S2_RX_DIV_N + Reserved + 14 + 8 + read-write + + + REG_I2S2_RX_DIV_X + Reserved + 22 + 9 + read-write + - GMAC_CTRL0 - N/A - 0x14C + PERI_CLK_CTRL18 + Reserved + 0x60 0x20 - PTP_PPS - N/A + REG_I2S2_RX_DIV_Y + Reserved 0 - 1 - read-only - - - SBD_FLOWCTRL - N/A - 1 - 1 + 9 read-write - PHY_INTF_SEL - N/A - 2 - 3 + REG_I2S2_RX_DIV_Z + Reserved + 9 + 9 read-write - GMAC_MEM_CLK_FORCE_ON - N/A - 5 + REG_I2S2_RX_DIV_YN1 + Reserved + 18 1 read-write - GMAC_RST_CLK_TX_N - N/A - 6 + REG_I2S2_TX_CLK_EN + Reserved + 19 1 - read-only + read-write - GMAC_RST_CLK_RX_N - N/A - 7 - 1 - read-only + REG_I2S2_TX_CLK_SRC_SEL + Reserved + 20 + 2 + read-write - - - - GMAC_CTRL1 - N/A - 0x150 - 0x20 - - PTP_TIMESTAMP_L - N/A - 0 - 32 - read-only + REG_I2S2_TX_DIV_N + Reserved + 22 + 8 + read-write - GMAC_CTRL2 - N/A - 0x154 + PERI_CLK_CTRL19 + Reserved + 0x64 0x20 - PTP_TIMESTAMP_H - N/A + REG_I2S2_TX_DIV_X + Reserved 0 - 32 - read-only + 9 + read-write - - - - VPU_CTRL - N/A - 0x158 - 0x20 - - PPA_LSLP_MEM_PD - N/A - 0 - 1 + REG_I2S2_TX_DIV_Y + Reserved + 9 + 9 read-write - JPEG_SDSLP_MEM_PD - N/A - 1 - 1 + REG_I2S2_TX_DIV_Z + Reserved + 18 + 9 read-write - JPEG_LSLP_MEM_PD - N/A - 2 + REG_I2S2_TX_DIV_YN1 + Reserved + 27 1 read-write - JPEG_DSLP_MEM_PD - N/A - 3 + REG_I2S2_MST_CLK_SEL + Reserved + 28 1 read-write - DMA2D_LSLP_MEM_PD - N/A - 4 + REG_LCD_CLK_SRC_SEL + Reserved + 29 + 2 + read-write + + + REG_LCD_CLK_EN + Reserved + 31 1 read-write - USBOTG20_CTRL - N/A - 0x15C + PERI_CLK_CTRL110 + Reserved + 0x68 0x20 - 0x00822640 + 0x04000000 - OTG_PHY_TEST_DONE - N/A + REG_LCD_CLK_DIV_NUM + Reserved 0 - 1 - read-only - - - USB_MEM_AUX_CTRL - N/A - 1 - 14 + 8 read-write - PHY_SUSPENDM - N/A - 15 - 1 + REG_LCD_CLK_DIV_NUMERATOR + Reserved + 8 + 8 read-write - PHY_SUSPEND_FORCE_EN - N/A + REG_LCD_CLK_DIV_DENOMINATOR + Reserved 16 - 1 - read-write - - - PHY_RSTN - N/A - 17 - 1 - read-write - - - PHY_RESET_FORCE_EN - N/A - 18 - 1 + 8 read-write - PHY_PLL_FORCE_EN - N/A - 19 - 1 + REG_UART0_CLK_SRC_SEL + Reserved + 24 + 2 read-write - PHY_PLL_EN - N/A - 20 + REG_UART0_CLK_EN + Reserved + 26 1 read-write + + + + PERI_CLK_CTRL111 + Reserved + 0x6C + 0x20 + 0x04000000 + - OTG_SUSPENDM - N/A - 21 - 1 + REG_UART0_SCLK_DIV_NUM + Reserved + 0 + 8 read-write - OTG_PHY_TXBITSTUFF_EN - N/A - 22 - 1 + REG_UART0_SCLK_DIV_NUMERATOR + Reserved + 8 + 8 read-write - OTG_PHY_REFCLK_MODE - N/A - 23 - 1 + REG_UART0_SCLK_DIV_DENOMINATOR + Reserved + 16 + 8 read-write - OTG_PHY_BISTEN - N/A + REG_UART1_CLK_SRC_SEL + Reserved 24 - 1 + 2 read-write - - - - HP_TCM_ERR_RESP_CTRL - need_des - 0x160 - 0x20 - - HP_TCM_ERR_RESP_EN - Set 1 to turn on tcm error response - 0 + REG_UART1_CLK_EN + Reserved + 26 1 read-write - HP_L2_MEM_REFRESH - NA - 0x164 + PERI_CLK_CTRL112 + Reserved + 0x70 0x20 - 0x00000040 + 0x04000000 - HP_REG_L2_MEM_UNIT0_REFERSH_EN - NA + REG_UART1_SCLK_DIV_NUM + Reserved 0 - 1 - read-write - - - HP_REG_L2_MEM_UNIT1_REFERSH_EN - NA - 1 - 1 + 8 read-write - HP_REG_L2_MEM_UNIT2_REFERSH_EN - NA - 2 - 1 + REG_UART1_SCLK_DIV_NUMERATOR + Reserved + 8 + 8 read-write - HP_REG_L2_MEM_UNIT3_REFERSH_EN - NA - 3 - 1 + REG_UART1_SCLK_DIV_DENOMINATOR + Reserved + 16 + 8 read-write - HP_REG_L2_MEM_UNIT4_REFERSH_EN - NA - 4 - 1 + REG_UART2_CLK_SRC_SEL + Reserved + 24 + 2 read-write - HP_REG_L2_MEM_UNIT5_REFERSH_EN - NA - 5 + REG_UART2_CLK_EN + Reserved + 26 1 read-write + + + + PERI_CLK_CTRL113 + Reserved + 0x74 + 0x20 + 0x04000000 + - HP_REG_L2_MEM_REFERSH_CNT_RESET - Set 1 to reset l2mem_refresh_cnt - 6 - 1 + REG_UART2_SCLK_DIV_NUM + Reserved + 0 + 8 read-write - HP_REG_L2_MEM_UNIT0_REFRESH_DONE - NA - 7 - 1 - read-only - - - HP_REG_L2_MEM_UNIT1_REFRESH_DONE - NA + REG_UART2_SCLK_DIV_NUMERATOR + Reserved 8 - 1 - read-only - - - HP_REG_L2_MEM_UNIT2_REFRESH_DONE - NA - 9 - 1 - read-only + 8 + read-write - HP_REG_L2_MEM_UNIT3_REFRESH_DONE - NA - 10 - 1 - read-only + REG_UART2_SCLK_DIV_DENOMINATOR + Reserved + 16 + 8 + read-write - HP_REG_L2_MEM_UNIT4_REFRESH_DONE - NA - 11 - 1 - read-only + REG_UART3_CLK_SRC_SEL + Reserved + 24 + 2 + read-write - HP_REG_L2_MEM_UNIT5_REFRESH_DONE - NA - 12 + REG_UART3_CLK_EN + Reserved + 26 1 - read-only + read-write - HP_TCM_INIT - NA - 0x168 + PERI_CLK_CTRL114 + Reserved + 0x78 0x20 - 0x00000002 + 0x04000000 - HP_REG_TCM_INIT_EN - NA + REG_UART3_SCLK_DIV_NUM + Reserved 0 - 1 + 8 read-write - HP_REG_TCM_INIT_CNT_RESET - Set 1 to reset tcm init cnt - 1 - 1 + REG_UART3_SCLK_DIV_NUMERATOR + Reserved + 8 + 8 read-write - HP_REG_TCM_INIT_DONE - NA - 2 - 1 - read-only + REG_UART3_SCLK_DIV_DENOMINATOR + Reserved + 16 + 8 + read-write - - - - HP_TCM_PARITY_CHECK_CTRL - need_des - 0x16C - 0x20 - - HP_TCM_PARITY_CHECK_EN - Set 1 to turn on tcm parity check - 0 + REG_UART4_CLK_SRC_SEL + Reserved + 24 + 2 + read-write + + + REG_UART4_CLK_EN + Reserved + 26 1 read-write - HP_DESIGN_FOR_VERIFICATION0 - need_des - 0x170 + PERI_CLK_CTRL115 + Reserved + 0x7C 0x20 - HP_DFV0 - register for DV + REG_UART4_SCLK_DIV_NUM + Reserved 0 - 32 + 8 read-write - - - - HP_DESIGN_FOR_VERIFICATION1 - need_des - 0x174 - 0x20 - - HP_DFV1 - register for DV - 0 - 32 + REG_UART4_SCLK_DIV_NUMERATOR + Reserved + 8 + 8 read-write - - - - HP_PSRAM_FLASH_ADDR_INTERCHANGE - need_des - 0x180 - 0x20 - - CPU - Set 1 to enable addr interchange between psram and flash in axi matrix when hp cpu access through cache - 0 - 1 + REG_UART4_SCLK_DIV_DENOMINATOR + Reserved + 16 + 8 read-write - DMA - Set 1 to enable addr interchange between psram and flash in axi matrix when dma device access, lp core access and hp core access through ahb - 1 + REG_TWAI0_CLK_SRC_SEL + Reserved + 24 1 read-write - - - - HP_AHB2AXI_BRESP_ERR_INT_RAW - NA - 0x188 - 0x20 - - HP_CPU_ICM_H2X_BRESP_ERR_INT_RAW - the raw interrupt status of bresp error, triggered when if bresp err occurs in post write mode in ahb2axi. - 0 + REG_TWAI0_CLK_EN + Reserved + 25 1 read-write - - - - HP_AHB2AXI_BRESP_ERR_INT_ST - need_des - 0x18C - 0x20 - - HP_CPU_ICM_H2X_BRESP_ERR_INT_ST - the masked interrupt status of cpu_icm_h2x_bresp_err - 31 + REG_TWAI1_CLK_SRC_SEL + Reserved + 26 1 - read-only + read-write - - - - HP_AHB2AXI_BRESP_ERR_INT_ENA - need_des - 0x190 - 0x20 - - HP_CPU_ICM_H2X_BRESP_ERR_INT_ENA - Write 1 to enable cpu_icm_h2x_bresp_err int - 31 + REG_TWAI1_CLK_EN + Reserved + 27 1 read-write - - - - HP_AHB2AXI_BRESP_ERR_INT_CLR - need_des - 0x194 - 0x20 - - HP_CPU_ICM_H2X_BRESP_ERR_INT_CLR - Write 1 to clear cpu_icm_h2x_bresp_err int - 31 + REG_TWAI2_CLK_SRC_SEL + Reserved + 28 1 - write-only + read-write - - - - HP_L2_MEM_ERR_RESP_CTRL - need_des - 0x198 - 0x20 - - HP_L2_MEM_ERR_RESP_EN - Set 1 to turn on l2mem error response - 0 + REG_TWAI2_CLK_EN + Reserved + 29 1 read-write - HP_L2_MEM_AHB_BUFFER_CTRL - need_des - 0x19C + PERI_CLK_CTRL116 + Reserved + 0x80 0x20 + 0x01100008 - HP_L2_MEM_AHB_WRBUFFER_EN - Set 1 to turn on l2mem ahb wr buffer + REG_GPSPI2_CLK_SRC_SEL + Reserved 0 - 1 + 3 read-write - HP_L2_MEM_AHB_RDBUFFER_EN - Set 1 to turn on l2mem ahb rd buffer - 1 + REG_GPSPI2_HS_CLK_EN + Reserved + 3 1 read-write - - - - HP_CORE_DMACTIVE_LPCORE - need_des - 0x1A0 - 0x20 - - HP_CORE_DMACTIVE_LPCORE - hp core dmactive_lpcore value - 0 + REG_GPSPI2_HS_CLK_DIV_NUM + Reserved + 4 + 8 + read-write + + + REG_GPSPI2_MST_CLK_DIV_NUM + Reserved + 12 + 8 + read-write + + + REG_GPSPI2_MST_CLK_EN + Reserved + 20 1 - read-only + read-write - - - - HP_CORE_ERR_RESP_DIS - need_des - 0x1A4 - 0x20 - - HP_CORE_ERR_RESP_DIS - Set bit0 to disable ibus err resp. Set bit1 to disable dbus err resp. Set bit 2 to disable ahb err resp. - 0 + REG_GPSPI3_CLK_SRC_SEL + Reserved + 21 3 read-write + + REG_GPSPI3_HS_CLK_EN + Reserved + 24 + 1 + read-write + - HP_CORE_TIMEOUT_INT_RAW - Hp core bus timeout interrupt raw register - 0x1A8 + PERI_CLK_CTRL117 + Reserved + 0x84 0x20 + 0x00010000 - HP_CORE0_AHB_TIMEOUT_INT_RAW - the raw interrupt status of hp core0 ahb timeout + REG_GPSPI3_HS_CLK_DIV_NUM + Reserved 0 - 1 + 8 read-write - HP_CORE1_AHB_TIMEOUT_INT_RAW - the raw interrupt status of hp core1 ahb timeout - 1 - 1 + REG_GPSPI3_MST_CLK_DIV_NUM + Reserved + 8 + 8 read-write - HP_CORE0_IBUS_TIMEOUT_INT_RAW - the raw interrupt status of hp core0 ibus timeout - 2 + REG_GPSPI3_MST_CLK_EN + Reserved + 16 1 read-write - HP_CORE1_IBUS_TIMEOUT_INT_RAW - the raw interrupt status of hp core1 ibus timeout - 3 - 1 + REG_PARLIO_RX_CLK_SRC_SEL + Reserved + 17 + 2 read-write - HP_CORE0_DBUS_TIMEOUT_INT_RAW - the raw interrupt status of hp core0 dbus timeout - 4 + REG_PARLIO_RX_CLK_EN + Reserved + 19 1 read-write - HP_CORE1_DBUS_TIMEOUT_INT_RAW - the raw interrupt status of hp core1 dbus timeout - 5 - 1 + REG_PARLIO_RX_CLK_DIV_NUM + Reserved + 20 + 8 read-write - HP_CORE_TIMEOUT_INT_ST - masked interrupt register - 0x1AC + PERI_CLK_CTRL118 + Reserved + 0x88 0x20 - HP_CORE0_AHB_TIMEOUT_INT_ST - the masked interrupt status of hp core0 ahb timeout + REG_PARLIO_RX_CLK_DIV_NUMERATOR + Reserved 0 - 1 - read-only - - - HP_CORE1_AHB_TIMEOUT_INT_ST - the masked interrupt status of hp core1 ahb timeout - 1 - 1 - read-only + 8 + read-write - HP_CORE0_IBUS_TIMEOUT_INT_ST - the masked interrupt status of hp core0 ibus timeout - 2 - 1 - read-only + REG_PARLIO_RX_CLK_DIV_DENOMINATOR + Reserved + 8 + 8 + read-write - HP_CORE1_IBUS_TIMEOUT_INT_ST - the masked interrupt status of hp core1 ibus timeout - 3 - 1 - read-only + REG_PARLIO_TX_CLK_SRC_SEL + Reserved + 16 + 2 + read-write - HP_CORE0_DBUS_TIMEOUT_INT_ST - the masked interrupt status of hp core0 dbus timeout - 4 + REG_PARLIO_TX_CLK_EN + Reserved + 18 1 - read-only + read-write - HP_CORE1_DBUS_TIMEOUT_INT_ST - the masked interrupt status of hp core1 dbus timeout - 5 - 1 - read-only + REG_PARLIO_TX_CLK_DIV_NUM + Reserved + 19 + 8 + read-write - HP_CORE_TIMEOUT_INT_ENA - masked interrupt register - 0x1B0 + PERI_CLK_CTRL119 + Reserved + 0x8C 0x20 - HP_CORE0_AHB_TIMEOUT_INT_ENA - Write 1 to enable hp_core0_ahb_timeout int + REG_PARLIO_TX_CLK_DIV_NUMERATOR + Reserved 0 - 1 + 8 read-write - HP_CORE1_AHB_TIMEOUT_INT_ENA - Write 1 to enable hp_core1_ahb_timeout int - 1 - 1 + REG_PARLIO_TX_CLK_DIV_DENOMINATOR + Reserved + 8 + 8 read-write - HP_CORE0_IBUS_TIMEOUT_INT_ENA - Write 1 to enable hp_core0_ibus_timeout int - 2 - 1 + REG_I3C_MST_CLK_SRC_SEL + Reserved + 16 + 2 read-write - HP_CORE1_IBUS_TIMEOUT_INT_ENA - Write 1 to enable hp_core1_ibus_timeout int - 3 + REG_I3C_MST_CLK_EN + Reserved + 18 1 read-write - HP_CORE0_DBUS_TIMEOUT_INT_ENA - Write 1 to enable hp_core0_dbus_timeout int - 4 - 1 + REG_I3C_MST_CLK_DIV_NUM + Reserved + 19 + 8 read-write - HP_CORE1_DBUS_TIMEOUT_INT_ENA - Write 1 to enable hp_core1_dbus_timeout int - 5 + REG_CAM_CLK_SRC_SEL + Reserved + 27 + 2 + read-write + + + REG_CAM_CLK_EN + Reserved + 29 1 read-write - HP_CORE_TIMEOUT_INT_CLR - interrupt clear register - 0x1B4 + PERI_CLK_CTRL120 + Reserved + 0x90 0x20 - HP_CORE0_AHB_TIMEOUT_INT_CLR - Write 1 to clear hp_core0_ahb_timeout int + REG_CAM_CLK_DIV_NUM + Reserved 0 - 1 - write-only + 8 + read-write - HP_CORE1_AHB_TIMEOUT_INT_CLR - Write 1 to clear hp_core1_ahb_timeout int - 1 - 1 - write-only + REG_CAM_CLK_DIV_NUMERATOR + Reserved + 8 + 8 + read-write - HP_CORE0_IBUS_TIMEOUT_INT_CLR - Write 1 to clear hp_core0_ibus_timeout int + REG_CAM_CLK_DIV_DENOMINATOR + Reserved + 16 + 8 + read-write + + + + + PERI_CLK_CTRL20 + Reserved + 0x94 + 0x20 + 0xC9000000 + + + REG_MCPWM0_CLK_SRC_SEL + Reserved + 0 + 2 + read-write + + + REG_MCPWM0_CLK_EN + Reserved 2 1 - write-only + read-write - HP_CORE1_IBUS_TIMEOUT_INT_CLR - Write 1 to clear hp_core1_ibus_timeout int + REG_MCPWM0_CLK_DIV_NUM + Reserved 3 - 1 - write-only + 8 + read-write - HP_CORE0_DBUS_TIMEOUT_INT_CLR - Write 1 to clear hp_core0_dbus_timeout int - 4 - 1 - write-only + REG_MCPWM1_CLK_SRC_SEL + Reserved + 11 + 2 + read-write - HP_CORE1_DBUS_TIMEOUT_INT_CLR - Write 1 to clear hp_core1_dbus_timeout int - 5 + REG_MCPWM1_CLK_EN + Reserved + 13 1 - write-only + read-write - - - - HP_GPIO_O_HYS_CTRL0 - NA - 0x1C0 - 0x20 - - HP_REG_GPIO_0_HYS_LOW - hys control for gpio47~16 - 0 - 32 + REG_MCPWM1_CLK_DIV_NUM + Reserved + 14 + 8 read-write - - - - HP_GPIO_O_HYS_CTRL1 - NA - 0x1C4 - 0x20 - - HP_REG_GPIO_0_HYS_HIGH - hys control for gpio56~48 - 0 - 9 + REG_TIMERGRP0_T0_SRC_SEL + Reserved + 22 + 2 read-write - - - - HP_RSA_PD_CTRL - rsa pd ctrl register - 0x1D0 - 0x20 - 0x00000002 - - HP_RSA_MEM_FORCE_PD - Set this bit to power down rsa internal memory. - 0 + REG_TIMERGRP0_T0_CLK_EN + Reserved + 24 1 read-write - HP_RSA_MEM_FORCE_PU - Set this bit to force power up rsa internal memory - 1 - 1 + REG_TIMERGRP0_T1_SRC_SEL + Reserved + 25 + 2 read-write - HP_RSA_MEM_PD - Set this bit to force power down rsa internal memory. - 2 + REG_TIMERGRP0_T1_CLK_EN + Reserved + 27 1 read-write - - - - HP_ECC_PD_CTRL - ecc pd ctrl register - 0x1D4 - 0x20 - 0x00000002 - - HP_ECC_MEM_FORCE_PD - Set this bit to power down ecc internal memory. - 0 - 1 + REG_TIMERGRP0_WDT_SRC_SEL + Reserved + 28 + 2 read-write - HP_ECC_MEM_FORCE_PU - Set this bit to force power up ecc internal memory - 1 + REG_TIMERGRP0_WDT_CLK_EN + Reserved + 30 1 read-write - HP_ECC_MEM_PD - Set this bit to force power down ecc internal memory. - 2 + REG_TIMERGRP0_TGRT_CLK_EN + Reserved + 31 1 read-write - HP_RNG_CFG - rng cfg register - 0x1D8 + PERI_CLK_CTRL21 + Reserved + 0x98 0x20 + 0x52400000 - HP_RNG_SAMPLE_ENABLE - enable rng sample chain + REG_TIMERGRP0_TGRT_CLK_SRC_SEL + Reserved 0 - 1 + 4 read-write - HP_RNG_CHAIN_CLK_DIV_NUM - chain clk div num to pad for debug - 16 - 8 + REG_TIMERGRP0_TGRT_CLK_DIV_NUM + Reserved + 4 + 16 read-write - HP_RNG_SAMPLE_CNT - debug rng sample cnt - 24 - 8 - read-only + REG_TIMERGRP1_T0_SRC_SEL + Reserved + 20 + 2 + read-write - - - - HP_UART_PD_CTRL - ecc pd ctrl register - 0x1DC - 0x20 - 0x00000002 - - HP_UART_MEM_FORCE_PD - Set this bit to power down hp uart internal memory. - 0 + REG_TIMERGRP1_T0_CLK_EN + Reserved + 22 1 read-write - HP_UART_MEM_FORCE_PU - Set this bit to force power up hp uart internal memory - 1 - 1 + REG_TIMERGRP1_T1_SRC_SEL + Reserved + 23 + 2 read-write - - - - HP_PERI_MEM_CLK_FORCE_ON - hp peri mem clk force on regpster - 0x1E0 - 0x20 - - HP_RMT_MEM_CLK_FORCE_ON - Set this bit to force on mem clk in rmt - 0 + REG_TIMERGRP1_T1_CLK_EN + Reserved + 25 1 read-write - HP_BITSCRAMBLER_TX_MEM_CLK_FORCE_ON - Set this bit to force on tx mem clk in bitscrambler - 1 - 1 + REG_TIMERGRP1_WDT_SRC_SEL + Reserved + 26 + 2 read-write - HP_BITSCRAMBLER_RX_MEM_CLK_FORCE_ON - Set this bit to force on rx mem clk in bitscrambler - 2 + REG_TIMERGRP1_WDT_CLK_EN + Reserved + 28 1 read-write - HP_GDMA_MEM_CLK_FORCE_ON - Set this bit to force on mem clk in gdma - 3 + REG_SYSTIMER_CLK_SRC_SEL + Reserved + 29 1 read-write - - - - - - HP_SYS_CLKRST - HP_SYS_CLKRST Peripheral - HP_SYS_CLKRST - 0x500E6000 - - 0x0 - 0xF0 - registers - - - - CLK_EN0 - Reserved - 0x0 - 0x20 - 0x00000001 - - REG_CLK_EN + REG_SYSTIMER_CLK_EN Reserved - 0 + 30 1 read-write - ROOT_CLK_CTRL0 + PERI_CLK_CTRL22 Reserved - 0x4 + 0x9C 0x20 - REG_CPUICM_DELAY_NUM + REG_LEDC_CLK_SRC_SEL Reserved 0 - 4 + 2 read-write - REG_SOC_CLK_DIV_UPDATE + REG_LEDC_CLK_EN Reserved - 4 + 2 1 - write-only + read-write - REG_CPU_CLK_DIV_NUM + REG_RMT_CLK_SRC_SEL + Reserved + 3 + 2 + read-write + + + REG_RMT_CLK_EN Reserved 5 + 1 + read-write + + + REG_RMT_CLK_DIV_NUM + Reserved + 6 8 read-write - REG_CPU_CLK_DIV_NUMERATOR + REG_RMT_CLK_DIV_NUMERATOR Reserved - 13 + 14 8 read-write - REG_CPU_CLK_DIV_DENOMINATOR + REG_RMT_CLK_DIV_DENOMINATOR Reserved - 21 + 22 8 read-write + + REG_ADC_CLK_SRC_SEL + Reserved + 30 + 2 + read-write + - ROOT_CLK_CTRL1 + PERI_CLK_CTRL23 Reserved - 0x8 + 0xA0 0x20 - 0x00000001 + 0x00000008 - REG_MEM_CLK_DIV_NUM + REG_ADC_CLK_EN Reserved 0 - 8 + 1 read-write - REG_MEM_CLK_DIV_NUMERATOR + REG_ADC_CLK_DIV_NUM Reserved - 8 + 1 8 read-write - REG_MEM_CLK_DIV_DENOMINATOR + REG_ADC_CLK_DIV_NUMERATOR Reserved - 16 + 9 8 read-write - REG_SYS_CLK_DIV_NUM + REG_ADC_CLK_DIV_DENOMINATOR Reserved - 24 + 17 8 read-write - ROOT_CLK_CTRL2 + PERI_CLK_CTRL24 Reserved - 0xC + 0xA4 0x20 - 0x00010000 + 0x00000404 - REG_SYS_CLK_DIV_NUMERATOR + REG_ADC_SAR1_CLK_DIV_NUM Reserved 0 8 read-write - REG_SYS_CLK_DIV_DENOMINATOR + REG_ADC_SAR2_CLK_DIV_NUM Reserved 8 8 read-write - REG_APB_CLK_DIV_NUM + REG_PVT_CLK_DIV_NUM Reserved 16 8 read-write - REG_APB_CLK_DIV_NUMERATOR + REG_PVT_CLK_EN Reserved 24 - 8 + 1 read-write - ROOT_CLK_CTRL3 + PERI_CLK_CTRL25 Reserved - 0x10 + 0xA8 0x20 + 0x007FC000 - REG_APB_CLK_DIV_DENOMINATOR + REG_PVT_PERI_GROUP_CLK_DIV_NUM Reserved 0 8 read-write - - - - SOC_CLK_CTRL0 - Reserved - 0x14 - 0x20 - 0xE6DF97AF - - REG_CORE0_CLIC_CLK_EN + REG_PVT_PERI_GROUP1_CLK_EN Reserved - 0 + 8 1 read-write - REG_CORE1_CLIC_CLK_EN + REG_PVT_PERI_GROUP2_CLK_EN Reserved - 1 + 9 1 read-write - REG_MISC_CPU_CLK_EN + REG_PVT_PERI_GROUP3_CLK_EN Reserved - 2 + 10 1 read-write - REG_CORE0_CPU_CLK_EN + REG_PVT_PERI_GROUP4_CLK_EN Reserved - 3 + 11 1 read-write - REG_CORE1_CPU_CLK_EN + REG_CRYPTO_CLK_SRC_SEL Reserved - 4 - 1 + 12 + 2 read-write - REG_TCM_CPU_CLK_EN + REG_CRYPTO_AES_CLK_EN Reserved - 5 + 14 1 read-write - REG_BUSMON_CPU_CLK_EN + REG_CRYPTO_DS_CLK_EN Reserved - 6 + 15 1 read-write - REG_L1CACHE_CPU_CLK_EN + REG_CRYPTO_ECC_CLK_EN Reserved - 7 + 16 1 read-write - REG_L1CACHE_D_CPU_CLK_EN + REG_CRYPTO_HMAC_CLK_EN Reserved - 8 + 17 1 read-write - REG_L1CACHE_I0_CPU_CLK_EN + REG_CRYPTO_RSA_CLK_EN Reserved - 9 + 18 1 read-write - REG_L1CACHE_I1_CPU_CLK_EN + REG_CRYPTO_SEC_CLK_EN Reserved - 10 + 19 1 read-write - REG_TRACE_CPU_CLK_EN + REG_CRYPTO_SHA_CLK_EN Reserved - 11 + 20 1 read-write - REG_ICM_CPU_CLK_EN + REG_CRYPTO_ECDSA_CLK_EN Reserved - 12 + 21 1 read-write - REG_GDMA_CPU_CLK_EN + REG_CRYPTO_KM_CLK_EN Reserved - 13 + 22 1 read-write - REG_VPU_CPU_CLK_EN + REG_ISP_CLK_SRC_SEL Reserved - 14 - 1 + 23 + 2 read-write - REG_L1CACHE_MEM_CLK_EN + REG_ISP_CLK_EN Reserved - 15 + 25 1 read-write + + + + PERI_CLK_CTRL26 + Reserved + 0xAC + 0x20 + 0x00000200 + - REG_L1CACHE_D_MEM_CLK_EN + REG_ISP_CLK_DIV_NUM Reserved - 16 - 1 + 0 + 8 read-write - REG_L1CACHE_I0_MEM_CLK_EN - Reserved - 17 - 1 - read-write - - - REG_L1CACHE_I1_MEM_CLK_EN - Reserved - 18 - 1 - read-write - - - REG_L2CACHE_MEM_CLK_EN - Reserved - 19 - 1 - read-write - - - REG_L2MEM_MEM_CLK_EN + REG_IOMUX_CLK_SRC_SEL Reserved - 20 + 8 1 read-write - REG_L2MEMMON_MEM_CLK_EN + REG_IOMUX_CLK_EN Reserved - 21 + 9 1 read-write - REG_ICM_MEM_CLK_EN + REG_IOMUX_CLK_DIV_NUM Reserved - 22 - 1 + 10 + 8 read-write - REG_MISC_SYS_CLK_EN + REG_H264_CLK_SRC_SEL Reserved - 23 + 18 1 read-write - REG_TRACE_SYS_CLK_EN + REG_H264_CLK_EN Reserved - 24 + 19 1 read-write - REG_L2CACHE_SYS_CLK_EN + REG_H264_CLK_DIV_NUM Reserved - 25 - 1 + 20 + 8 read-write - REG_L2MEM_SYS_CLK_EN + REG_PADBIST_RX_CLK_SRC_SEL Reserved - 26 + 28 1 read-write - REG_L2MEMMON_SYS_CLK_EN + REG_PADBIST_RX_CLK_EN Reserved - 27 + 29 1 read-write + + + + PERI_CLK_CTRL27 + Reserved + 0xB0 + 0x20 + - REG_TCMMON_SYS_CLK_EN + REG_PADBIST_RX_CLK_DIV_NUM Reserved - 28 - 1 + 0 + 8 read-write - REG_ICM_SYS_CLK_EN + REG_PADBIST_TX_CLK_SRC_SEL Reserved - 29 + 8 1 read-write - REG_FLASH_SYS_CLK_EN + REG_PADBIST_TX_CLK_EN Reserved - 30 + 9 1 read-write - REG_PSRAM_SYS_CLK_EN + REG_PADBIST_TX_CLK_DIV_NUM Reserved - 31 - 1 + 10 + 8 read-write - SOC_CLK_CTRL1 + CLK_FORCE_ON_CTRL0 Reserved - 0x18 + 0xB4 0x20 - 0x7C7F801F + 0x0003FFFF - REG_GPSPI2_SYS_CLK_EN + REG_CPUICM_GATED_CLK_FORCE_ON Reserved 0 1 read-write - REG_GPSPI3_SYS_CLK_EN + REG_TCM_CPU_CLK_FORCE_ON Reserved 1 1 read-write - REG_REGDMA_SYS_CLK_EN + REG_BUSMON_CPU_CLK_FORCE_ON Reserved 2 1 read-write - REG_AHB_PDMA_SYS_CLK_EN + REG_L1CACHE_CPU_CLK_FORCE_ON Reserved 3 1 read-write - REG_AXI_PDMA_SYS_CLK_EN + REG_L1CACHE_D_CPU_CLK_FORCE_ON Reserved 4 1 read-write - REG_GDMA_SYS_CLK_EN + REG_L1CACHE_I0_CPU_CLK_FORCE_ON Reserved 5 1 read-write - REG_DMA2D_SYS_CLK_EN + REG_L1CACHE_I1_CPU_CLK_FORCE_ON Reserved 6 1 read-write - REG_VPU_SYS_CLK_EN + REG_TRACE_CPU_CLK_FORCE_ON Reserved 7 1 read-write - REG_JPEG_SYS_CLK_EN + REG_TRACE_SYS_CLK_FORCE_ON Reserved 8 1 read-write - REG_PPA_SYS_CLK_EN + REG_L1CACHE_MEM_CLK_FORCE_ON Reserved 9 1 read-write - REG_CSI_BRG_SYS_CLK_EN + REG_L1CACHE_D_MEM_CLK_FORCE_ON Reserved 10 1 read-write - REG_CSI_HOST_SYS_CLK_EN + REG_L1CACHE_I0_MEM_CLK_FORCE_ON Reserved 11 1 read-write - REG_DSI_SYS_CLK_EN + REG_L1CACHE_I1_MEM_CLK_FORCE_ON Reserved 12 1 read-write - REG_EMAC_SYS_CLK_EN + REG_L2CACHE_MEM_CLK_FORCE_ON Reserved 13 1 read-write - REG_SDMMC_SYS_CLK_EN + REG_L2MEM_MEM_CLK_FORCE_ON Reserved 14 1 read-write - REG_USB_OTG11_SYS_CLK_EN + REG_SAR1_CLK_FORCE_ON Reserved 15 1 read-write - REG_USB_OTG20_SYS_CLK_EN + REG_SAR2_CLK_FORCE_ON Reserved 16 1 read-write - REG_UHCI_SYS_CLK_EN + REG_GMAC_TX_CLK_FORCE_ON Reserved 17 1 read-write + + + + DPA_CTRL0 + Reserved + 0xB8 + 0x20 + - REG_UART0_SYS_CLK_EN - Reserved - 18 - 1 - read-write - - - REG_UART1_SYS_CLK_EN - Reserved - 19 - 1 - read-write - - - REG_UART2_SYS_CLK_EN + REG_SEC_DPA_LEVEL Reserved - 20 - 1 + 0 + 2 read-write - REG_UART3_SYS_CLK_EN + REG_SEC_DPA_CFG_SEL Reserved - 21 + 2 1 read-write + + + + ANA_PLL_CTRL0 + Reserved + 0xBC + 0x20 + - REG_UART4_SYS_CLK_EN + REG_PLLA_CAL_END Reserved - 22 + 0 1 - read-write + read-only - REG_PARLIO_SYS_CLK_EN + REG_PLLA_CAL_STOP Reserved - 23 + 1 1 read-write - REG_ETM_SYS_CLK_EN + REG_CPU_PLL_CAL_END Reserved - 24 + 2 1 - read-write + read-only - REG_PVT_SYS_CLK_EN + REG_CPU_PLL_CAL_STOP Reserved - 25 + 3 1 read-write - REG_CRYPTO_SYS_CLK_EN + REG_SDIO_PLL_CAL_END Reserved - 26 + 4 1 - read-write + read-only - REG_KEY_MANAGER_SYS_CLK_EN + REG_SDIO_PLL_CAL_STOP Reserved - 27 + 5 1 read-write - REG_BITSRAMBLER_SYS_CLK_EN + REG_SYS_PLL_CAL_END Reserved - 28 + 6 1 - read-write + read-only - REG_BITSRAMBLER_RX_SYS_CLK_EN + REG_SYS_PLL_CAL_STOP Reserved - 29 + 7 1 read-write - REG_BITSRAMBLER_TX_SYS_CLK_EN + REG_MSPI_CAL_END Reserved - 30 + 8 1 - read-write + read-only - REG_H264_SYS_CLK_EN + REG_MSPI_CAL_STOP Reserved - 31 + 9 1 read-write - SOC_CLK_CTRL2 + HP_RST_EN0 Reserved - 0x1C + 0xC0 0x20 - 0x20F80FDE + 0x00000100 - REG_RMT_SYS_CLK_EN + REG_RST_EN_CORECTRL Reserved 0 1 read-write - REG_HP_CLKRST_APB_CLK_EN + REG_RST_EN_PVT_TOP Reserved 1 1 read-write - REG_SYSREG_APB_CLK_EN + REG_RST_EN_PVT_PERI_GROUP1 Reserved 2 1 read-write - REG_ICM_APB_CLK_EN + REG_RST_EN_PVT_PERI_GROUP2 Reserved 3 1 read-write - REG_INTRMTX_APB_CLK_EN + REG_RST_EN_PVT_PERI_GROUP3 Reserved 4 1 read-write - REG_ADC_APB_CLK_EN + REG_RST_EN_PVT_PERI_GROUP4 Reserved 5 1 read-write - REG_UHCI_APB_CLK_EN + REG_RST_EN_REGDMA Reserved 6 1 read-write - REG_UART0_APB_CLK_EN + REG_RST_EN_CORE0_GLOBAL Reserved 7 1 read-write - REG_UART1_APB_CLK_EN + REG_RST_EN_CORE1_GLOBAL Reserved 8 1 read-write - REG_UART2_APB_CLK_EN + REG_RST_EN_CORETRACE0 Reserved 9 1 read-write - REG_UART3_APB_CLK_EN + REG_RST_EN_CORETRACE1 Reserved 10 1 read-write - REG_UART4_APB_CLK_EN + REG_RST_EN_HP_TCM Reserved 11 1 read-write - REG_I2C0_APB_CLK_EN + REG_RST_EN_HP_CACHE Reserved 12 1 read-write - REG_I2C1_APB_CLK_EN + REG_RST_EN_L1_I0_CACHE Reserved 13 1 read-write - REG_I2S0_APB_CLK_EN + REG_RST_EN_L1_I1_CACHE Reserved 14 1 read-write - REG_I2S1_APB_CLK_EN + REG_RST_EN_L1_D_CACHE Reserved 15 1 read-write - REG_I2S2_APB_CLK_EN + REG_RST_EN_L2_CACHE Reserved 16 1 read-write - REG_I3C_MST_APB_CLK_EN + REG_RST_EN_L2_MEM Reserved 17 1 read-write - REG_I3C_SLV_APB_CLK_EN + REG_RST_EN_L2MEMMON Reserved 18 1 read-write - REG_GPSPI2_APB_CLK_EN + REG_RST_EN_TCMMON Reserved 19 1 read-write - REG_GPSPI3_APB_CLK_EN + REG_RST_EN_PVT_APB Reserved 20 1 read-write - REG_TIMERGRP0_APB_CLK_EN + REG_RST_EN_GDMA Reserved 21 1 read-write - REG_TIMERGRP1_APB_CLK_EN + REG_RST_EN_MSPI_AXI Reserved 22 1 read-write - REG_SYSTIMER_APB_CLK_EN + REG_RST_EN_DUAL_MSPI_AXI Reserved 23 1 read-write - REG_TWAI0_APB_CLK_EN + REG_RST_EN_MSPI_APB Reserved 24 1 read-write - REG_TWAI1_APB_CLK_EN + REG_RST_EN_DUAL_MSPI_APB Reserved 25 1 read-write - REG_TWAI2_APB_CLK_EN + REG_RST_EN_DSI_BRG Reserved 26 1 read-write - REG_MCPWM0_APB_CLK_EN + REG_RST_EN_CSI_HOST Reserved 27 1 read-write - REG_MCPWM1_APB_CLK_EN + REG_RST_EN_CSI_BRG Reserved 28 1 read-write - REG_USB_DEVICE_APB_CLK_EN + REG_RST_EN_ISP Reserved 29 1 read-write - REG_PCNT_APB_CLK_EN + REG_RST_EN_JPEG Reserved 30 1 read-write - REG_PARLIO_APB_CLK_EN + REG_RST_EN_DMA2D Reserved 31 1 @@ -59961,423 +57694,413 @@ - SOC_CLK_CTRL3 + HP_RST_EN1 Reserved - 0x20 + 0xC4 0x20 - 0x00000008 - REG_LEDC_APB_CLK_EN + REG_RST_EN_PPA Reserved 0 1 read-write - REG_LCDCAM_APB_CLK_EN + REG_RST_EN_AHB_PDMA Reserved 1 1 read-write - REG_ETM_APB_CLK_EN + REG_RST_EN_AXI_PDMA Reserved 2 1 read-write - REG_IOMUX_APB_CLK_EN + REG_RST_EN_IOMUX Reserved 3 1 read-write - - - - REF_CLK_CTRL0 - Reserved - 0x24 - 0x20 - 0x02011309 - - REG_REF_50M_CLK_DIV_NUM + REG_RST_EN_PADBIST Reserved - 0 - 8 + 4 + 1 read-write - REG_REF_25M_CLK_DIV_NUM + REG_RST_EN_STIMER + Reserved + 5 + 1 + read-write + + + REG_RST_EN_TIMERGRP0 + Reserved + 6 + 1 + read-write + + + REG_RST_EN_TIMERGRP1 + Reserved + 7 + 1 + read-write + + + REG_RST_EN_UART0_CORE Reserved 8 - 8 + 1 read-write - REG_REF_240M_CLK_DIV_NUM + REG_RST_EN_UART1_CORE Reserved - 16 - 8 + 9 + 1 read-write - REG_REF_160M_CLK_DIV_NUM + REG_RST_EN_UART2_CORE Reserved - 24 - 8 + 10 + 1 read-write - - - - REF_CLK_CTRL1 - Reserved - 0x28 - 0x20 - 0x58170503 - - REG_REF_120M_CLK_DIV_NUM + REG_RST_EN_UART3_CORE Reserved - 0 - 8 + 11 + 1 read-write - REG_REF_80M_CLK_DIV_NUM + REG_RST_EN_UART4_CORE Reserved - 8 - 8 + 12 + 1 read-write - REG_REF_20M_CLK_DIV_NUM + REG_RST_EN_UART0_APB Reserved - 16 - 8 + 13 + 1 read-write - REG_TM_400M_CLK_EN + REG_RST_EN_UART1_APB Reserved - 24 + 14 1 read-write - REG_TM_200M_CLK_EN + REG_RST_EN_UART2_APB Reserved - 25 + 15 1 read-write - REG_TM_100M_CLK_EN + REG_RST_EN_UART3_APB Reserved - 26 + 16 1 read-write - REG_REF_50M_CLK_EN + REG_RST_EN_UART4_APB Reserved - 27 + 17 1 read-write - REG_REF_25M_CLK_EN + REG_RST_EN_UHCI Reserved - 28 + 18 1 read-write - REG_TM_480M_CLK_EN + REG_RST_EN_I3CMST Reserved - 29 + 19 1 read-write - REG_REF_240M_CLK_EN + REG_RST_EN_I3CSLV Reserved - 30 + 20 1 read-write - REG_TM_240M_CLK_EN + REG_RST_EN_I2C1 Reserved - 31 + 21 1 read-write - - - - REF_CLK_CTRL2 - Reserved - 0x2C - 0x20 - 0x00000115 - - REG_REF_160M_CLK_EN + REG_RST_EN_I2C0 Reserved - 0 + 22 1 read-write - REG_TM_160M_CLK_EN + REG_RST_EN_RMT Reserved - 1 + 23 1 read-write - REG_REF_120M_CLK_EN + REG_RST_EN_PWM0 Reserved - 2 + 24 1 read-write - REG_TM_120M_CLK_EN + REG_RST_EN_PWM1 Reserved - 3 + 25 1 read-write - REG_REF_80M_CLK_EN + REG_RST_EN_CAN0 Reserved - 4 + 26 1 read-write - REG_TM_80M_CLK_EN + REG_RST_EN_CAN1 Reserved - 5 + 27 1 read-write - REG_TM_60M_CLK_EN + REG_RST_EN_CAN2 Reserved - 6 + 28 1 read-write - REG_TM_48M_CLK_EN + REG_RST_EN_LEDC Reserved - 7 + 29 1 read-write - REG_REF_20M_CLK_EN + REG_RST_EN_PCNT Reserved - 8 + 30 1 read-write - REG_TM_20M_CLK_EN + REG_RST_EN_ETM Reserved - 9 + 31 1 read-write - PERI_CLK_CTRL00 + HP_RST_EN2 Reserved - 0x30 + 0xC8 0x20 - 0x0000C03C - REG_FLASH_CLK_SRC_SEL + REG_RST_EN_INTRMTX Reserved 0 - 2 + 1 read-write - REG_FLASH_PLL_CLK_EN + REG_RST_EN_PARLIO + Reserved + 1 + 1 + read-write + + + REG_RST_EN_PARLIO_RX Reserved 2 1 read-write - REG_FLASH_CORE_CLK_EN + REG_RST_EN_PARLIO_TX Reserved 3 1 read-write - REG_FLASH_CORE_CLK_DIV_NUM + REG_RST_EN_I2S0_APB Reserved 4 - 8 + 1 read-write - REG_PSRAM_CLK_SRC_SEL + REG_RST_EN_I2S1_APB Reserved - 12 - 2 + 5 + 1 read-write - REG_PSRAM_PLL_CLK_EN + REG_RST_EN_I2S2_APB Reserved - 14 + 6 1 read-write - REG_PSRAM_CORE_CLK_EN + REG_RST_EN_SPI2 Reserved - 15 + 7 1 read-write - REG_PSRAM_CORE_CLK_DIV_NUM + REG_RST_EN_SPI3 Reserved - 16 - 8 + 8 + 1 read-write - REG_PAD_EMAC_REF_CLK_EN + REG_RST_EN_LCDCAM Reserved - 24 + 9 1 read-write - REG_EMAC_RMII_CLK_SRC_SEL + REG_RST_EN_ADC Reserved - 25 - 2 + 10 + 1 read-write - REG_EMAC_RMII_CLK_EN + REG_RST_EN_BITSRAMBLER Reserved - 27 + 11 1 read-write - REG_EMAC_RX_CLK_SRC_SEL + REG_RST_EN_BITSRAMBLER_RX Reserved - 28 + 12 1 read-write - REG_EMAC_RX_CLK_EN + REG_RST_EN_BITSRAMBLER_TX Reserved - 29 + 13 1 read-write - - - - PERI_CLK_CTRL01 - Reserved - 0x34 - 0x20 - 0x00000401 - - REG_EMAC_RX_CLK_DIV_NUM + REG_RST_EN_CRYPTO Reserved - 0 - 8 + 14 + 1 read-write - REG_EMAC_TX_CLK_SRC_SEL + REG_RST_EN_SEC Reserved - 8 + 15 1 read-write - REG_EMAC_TX_CLK_EN + REG_RST_EN_AES Reserved - 9 + 16 1 read-write - REG_EMAC_TX_CLK_DIV_NUM + REG_RST_EN_DS Reserved - 10 - 8 + 17 + 1 read-write - REG_EMAC_PTP_REF_CLK_SRC_SEL + REG_RST_EN_SHA Reserved 18 1 read-write - REG_EMAC_PTP_REF_CLK_EN + REG_RST_EN_HMAC Reserved 19 1 read-write - REG_EMAC_UNUSED0_CLK_EN + REG_RST_EN_ECDSA Reserved 20 1 read-write - REG_EMAC_UNUSED1_CLK_EN + REG_RST_EN_RSA Reserved 21 1 read-write - REG_SDIO_HS_MODE + REG_RST_EN_ECC Reserved 22 1 read-write - REG_SDIO_LS_CLK_SRC_SEL + REG_RST_EN_KM Reserved 23 1 read-write - REG_SDIO_LS_CLK_EN + REG_RST_EN_H264 Reserved 24 1 @@ -60386,9433 +58109,590 @@ - PERI_CLK_CTRL02 + HP_FORCE_NORST0 Reserved - 0x38 + 0xCC 0x20 - REG_SDIO_LS_CLK_DIV_NUM + REG_FORCE_NORST_CORE0 Reserved 0 - 8 - read-write - - - REG_SDIO_LS_CLK_EDGE_CFG_UPDATE - Reserved - 8 1 - write-only - - - REG_SDIO_LS_CLK_EDGE_L - Reserved - 9 - 4 read-write - REG_SDIO_LS_CLK_EDGE_H + REG_FORCE_NORST_CORE1 Reserved - 13 - 4 + 1 + 1 read-write - REG_SDIO_LS_CLK_EDGE_N + REG_FORCE_NORST_CORETRACE0 Reserved - 17 - 4 + 2 + 1 read-write - REG_SDIO_LS_SLF_CLK_EDGE_SEL + REG_FORCE_NORST_CORETRACE1 Reserved - 21 - 2 + 3 + 1 read-write - REG_SDIO_LS_DRV_CLK_EDGE_SEL + REG_FORCE_NORST_L2MEMMON Reserved - 23 - 2 + 4 + 1 read-write - REG_SDIO_LS_SAM_CLK_EDGE_SEL + REG_FORCE_NORST_TCMMON Reserved - 25 - 2 + 5 + 1 read-write - REG_SDIO_LS_SLF_CLK_EN + REG_FORCE_NORST_GDMA Reserved - 27 + 6 1 read-write - REG_SDIO_LS_DRV_CLK_EN + REG_FORCE_NORST_MSPI_AXI Reserved - 28 + 7 1 read-write - REG_SDIO_LS_SAM_CLK_EN + REG_FORCE_NORST_DUAL_MSPI_AXI Reserved - 29 + 8 1 read-write - REG_MIPI_DSI_DPHY_CLK_SRC_SEL + REG_FORCE_NORST_MSPI_APB Reserved - 30 - 2 + 9 + 1 read-write - - - - PERI_CLK_CTRL03 - Reserved - 0x3C - 0x20 - - REG_MIPI_DSI_DPHY_CFG_CLK_EN + REG_FORCE_NORST_DUAL_MSPI_APB Reserved - 0 + 10 1 read-write - REG_MIPI_DSI_DPHY_PLL_REFCLK_EN + REG_FORCE_NORST_DSI_BRG Reserved - 1 + 11 1 read-write - REG_MIPI_CSI_DPHY_CLK_SRC_SEL + REG_FORCE_NORST_CSI_HOST Reserved - 2 - 2 + 12 + 1 read-write - REG_MIPI_CSI_DPHY_CFG_CLK_EN + REG_FORCE_NORST_CSI_BRG Reserved - 4 + 13 1 read-write - REG_MIPI_DSI_DPICLK_SRC_SEL + REG_FORCE_NORST_ISP Reserved - 5 - 2 + 14 + 1 read-write - REG_MIPI_DSI_DPICLK_EN + REG_FORCE_NORST_JPEG Reserved - 7 + 15 1 read-write - REG_MIPI_DSI_DPICLK_DIV_NUM + REG_FORCE_NORST_DMA2D Reserved - 8 - 8 + 16 + 1 read-write - - - - PERI_CLK_CTRL10 - Reserved - 0x40 - 0x20 - - REG_I2C0_CLK_SRC_SEL + REG_FORCE_NORST_PPA Reserved - 0 + 17 1 read-write - REG_I2C0_CLK_EN + REG_FORCE_NORST_AHB_PDMA Reserved - 1 + 18 1 read-write - REG_I2C0_CLK_DIV_NUM + REG_FORCE_NORST_AXI_PDMA Reserved - 2 - 8 + 19 + 1 read-write - REG_I2C0_CLK_DIV_NUMERATOR + REG_FORCE_NORST_IOMUX Reserved - 10 - 8 + 20 + 1 read-write - REG_I2C0_CLK_DIV_DENOMINATOR + REG_FORCE_NORST_PADBIST Reserved - 18 - 8 + 21 + 1 read-write - REG_I2C1_CLK_SRC_SEL + REG_FORCE_NORST_STIMER Reserved - 26 + 22 1 read-write - REG_I2C1_CLK_EN + REG_FORCE_NORST_TIMERGRP0 Reserved - 27 + 23 1 read-write - - - - PERI_CLK_CTRL11 - Reserved - 0x44 - 0x20 - - REG_I2C1_CLK_DIV_NUM + REG_FORCE_NORST_TIMERGRP1 Reserved - 0 - 8 + 24 + 1 read-write - REG_I2C1_CLK_DIV_NUMERATOR + REG_FORCE_NORST_UART0 Reserved - 8 - 8 + 25 + 1 read-write - REG_I2C1_CLK_DIV_DENOMINATOR + REG_FORCE_NORST_UART1 Reserved - 16 - 8 + 26 + 1 read-write - REG_I2S0_RX_CLK_EN + REG_FORCE_NORST_UART2 Reserved - 24 + 27 1 read-write - REG_I2S0_RX_CLK_SRC_SEL + REG_FORCE_NORST_UART3 Reserved - 25 - 2 + 28 + 1 read-write - - - - PERI_CLK_CTRL12 - Reserved - 0x48 - 0x20 - - REG_I2S0_RX_DIV_N + REG_FORCE_NORST_UART4 Reserved - 0 - 8 + 29 + 1 read-write - REG_I2S0_RX_DIV_X + REG_FORCE_NORST_UHCI Reserved - 8 - 9 + 30 + 1 read-write - REG_I2S0_RX_DIV_Y + REG_FORCE_NORST_I3CMST Reserved - 17 - 9 + 31 + 1 read-write - PERI_CLK_CTRL13 + HP_FORCE_NORST1 Reserved - 0x4C + 0xD0 0x20 - REG_I2S0_RX_DIV_Z + REG_FORCE_NORST_I3CSLV Reserved 0 - 9 - read-write - - - REG_I2S0_RX_DIV_YN1 - Reserved - 9 1 read-write - REG_I2S0_TX_CLK_EN + REG_FORCE_NORST_I2C1 Reserved - 10 + 1 1 read-write - REG_I2S0_TX_CLK_SRC_SEL - Reserved - 11 - 2 - read-write - - - REG_I2S0_TX_DIV_N + REG_FORCE_NORST_I2C0 Reserved - 13 - 8 + 2 + 1 read-write - REG_I2S0_TX_DIV_X + REG_FORCE_NORST_RMT Reserved - 21 - 9 + 3 + 1 read-write - - - - PERI_CLK_CTRL14 - Reserved - 0x50 - 0x20 - - REG_I2S0_TX_DIV_Y + REG_FORCE_NORST_PWM0 Reserved - 0 - 9 + 4 + 1 read-write - REG_I2S0_TX_DIV_Z + REG_FORCE_NORST_PWM1 Reserved - 9 - 9 + 5 + 1 read-write - REG_I2S0_TX_DIV_YN1 + REG_FORCE_NORST_CAN0 Reserved - 18 + 6 1 read-write - REG_I2S0_MST_CLK_SEL + REG_FORCE_NORST_CAN1 Reserved - 19 + 7 1 read-write - REG_I2S1_RX_CLK_EN + REG_FORCE_NORST_CAN2 Reserved - 20 + 8 1 read-write - REG_I2S1_RX_CLK_SRC_SEL + REG_FORCE_NORST_LEDC Reserved - 21 - 2 + 9 + 1 read-write - REG_I2S1_RX_DIV_N + REG_FORCE_NORST_PCNT Reserved - 23 - 8 + 10 + 1 read-write - - - - PERI_CLK_CTRL15 - Reserved - 0x54 - 0x20 - - REG_I2S1_RX_DIV_X + REG_FORCE_NORST_ETM Reserved - 0 - 9 + 11 + 1 read-write - REG_I2S1_RX_DIV_Y + REG_FORCE_NORST_INTRMTX Reserved - 9 - 9 + 12 + 1 read-write - REG_I2S1_RX_DIV_Z + REG_FORCE_NORST_PARLIO Reserved - 18 - 9 + 13 + 1 read-write - REG_I2S1_RX_DIV_YN1 + REG_FORCE_NORST_PARLIO_RX Reserved - 27 + 14 1 read-write - REG_I2S1_TX_CLK_EN + REG_FORCE_NORST_PARLIO_TX Reserved - 28 + 15 1 read-write - REG_I2S1_TX_CLK_SRC_SEL + REG_FORCE_NORST_I2S0 Reserved - 29 - 2 + 16 + 1 read-write - - - - PERI_CLK_CTRL16 - Reserved - 0x58 - 0x20 - - REG_I2S1_TX_DIV_N + REG_FORCE_NORST_I2S1 Reserved - 0 - 8 + 17 + 1 read-write - REG_I2S1_TX_DIV_X + REG_FORCE_NORST_I2S2 Reserved - 8 - 9 + 18 + 1 read-write - REG_I2S1_TX_DIV_Y + REG_FORCE_NORST_SPI2 Reserved - 17 - 9 + 19 + 1 read-write - - - - PERI_CLK_CTRL17 - Reserved - 0x5C - 0x20 - - REG_I2S1_TX_DIV_Z + REG_FORCE_NORST_SPI3 Reserved - 0 - 9 + 20 + 1 read-write - REG_I2S1_TX_DIV_YN1 + REG_FORCE_NORST_LCDCAM Reserved - 9 + 21 1 read-write - REG_I2S1_MST_CLK_SEL + REG_FORCE_NORST_ADC Reserved - 10 + 22 1 read-write - REG_I2S2_RX_CLK_EN + REG_FORCE_NORST_BITSRAMBLER Reserved - 11 + 23 1 read-write - REG_I2S2_RX_CLK_SRC_SEL + REG_FORCE_NORST_BITSRAMBLER_RX Reserved - 12 - 2 + 24 + 1 read-write - REG_I2S2_RX_DIV_N + REG_FORCE_NORST_BITSRAMBLER_TX Reserved - 14 - 8 + 25 + 1 read-write - REG_I2S2_RX_DIV_X + REG_FORCE_NORST_H264 Reserved - 22 - 9 + 26 + 1 read-write - PERI_CLK_CTRL18 + HPWDT_CORE0_RST_CTRL0 Reserved - 0x60 + 0xD4 0x20 + 0x00001011 - REG_I2S2_RX_DIV_Y + REG_HPCORE0_STALL_EN Reserved 0 - 9 + 1 read-write - REG_I2S2_RX_DIV_Z + REG_HPCORE0_STALL_WAIT_NUM Reserved - 9 - 9 + 1 + 8 read-write - REG_I2S2_RX_DIV_YN1 + REG_WDT_HPCORE0_RST_LEN Reserved - 18 - 1 + 9 + 8 read-write + + + + HPWDT_CORE1_RST_CTRL0 + Reserved + 0xD8 + 0x20 + 0x00001011 + - REG_I2S2_TX_CLK_EN + REG_HPCORE1_STALL_EN Reserved - 19 + 0 1 read-write - REG_I2S2_TX_CLK_SRC_SEL + REG_HPCORE1_STALL_WAIT_NUM Reserved - 20 - 2 + 1 + 8 read-write - REG_I2S2_TX_DIV_N + REG_WDT_HPCORE1_RST_LEN Reserved - 22 + 9 8 read-write - PERI_CLK_CTRL19 - Reserved - 0x64 + CPU_SRC_FREQ0 + CPU Source Frequency + 0xDC 0x20 - REG_I2S2_TX_DIV_X - Reserved - 0 - 9 - read-write - - - REG_I2S2_TX_DIV_Y - Reserved - 9 - 9 - read-write - - - REG_I2S2_TX_DIV_Z - Reserved - 18 - 9 - read-write - - - REG_I2S2_TX_DIV_YN1 - Reserved - 27 - 1 - read-write - - - REG_I2S2_MST_CLK_SEL - Reserved - 28 - 1 - read-write - - - REG_LCD_CLK_SRC_SEL - Reserved - 29 - 2 - read-write - - - REG_LCD_CLK_EN - Reserved - 31 - 1 - read-write - - - - - PERI_CLK_CTRL110 - Reserved - 0x68 - 0x20 - 0x04000000 - - - REG_LCD_CLK_DIV_NUM - Reserved - 0 - 8 - read-write - - - REG_LCD_CLK_DIV_NUMERATOR - Reserved - 8 - 8 - read-write - - - REG_LCD_CLK_DIV_DENOMINATOR - Reserved - 16 - 8 - read-write - - - REG_UART0_CLK_SRC_SEL - Reserved - 24 - 2 - read-write - - - REG_UART0_CLK_EN - Reserved - 26 - 1 - read-write - - - - - PERI_CLK_CTRL111 - Reserved - 0x6C - 0x20 - 0x04000000 - - - REG_UART0_SCLK_DIV_NUM - Reserved - 0 - 8 - read-write - - - REG_UART0_SCLK_DIV_NUMERATOR - Reserved - 8 - 8 - read-write - - - REG_UART0_SCLK_DIV_DENOMINATOR - Reserved - 16 - 8 - read-write - - - REG_UART1_CLK_SRC_SEL - Reserved - 24 - 2 - read-write - - - REG_UART1_CLK_EN - Reserved - 26 - 1 - read-write - - - - - PERI_CLK_CTRL112 - Reserved - 0x70 - 0x20 - 0x04000000 - - - REG_UART1_SCLK_DIV_NUM - Reserved - 0 - 8 - read-write - - - REG_UART1_SCLK_DIV_NUMERATOR - Reserved - 8 - 8 - read-write - - - REG_UART1_SCLK_DIV_DENOMINATOR - Reserved - 16 - 8 - read-write - - - REG_UART2_CLK_SRC_SEL - Reserved - 24 - 2 - read-write - - - REG_UART2_CLK_EN - Reserved - 26 - 1 - read-write - - - - - PERI_CLK_CTRL113 - Reserved - 0x74 - 0x20 - 0x04000000 - - - REG_UART2_SCLK_DIV_NUM - Reserved - 0 - 8 - read-write - - - REG_UART2_SCLK_DIV_NUMERATOR - Reserved - 8 - 8 - read-write - - - REG_UART2_SCLK_DIV_DENOMINATOR - Reserved - 16 - 8 - read-write - - - REG_UART3_CLK_SRC_SEL - Reserved - 24 - 2 - read-write - - - REG_UART3_CLK_EN - Reserved - 26 - 1 - read-write - - - - - PERI_CLK_CTRL114 - Reserved - 0x78 - 0x20 - 0x04000000 - - - REG_UART3_SCLK_DIV_NUM - Reserved - 0 - 8 - read-write - - - REG_UART3_SCLK_DIV_NUMERATOR - Reserved - 8 - 8 - read-write - - - REG_UART3_SCLK_DIV_DENOMINATOR - Reserved - 16 - 8 - read-write - - - REG_UART4_CLK_SRC_SEL - Reserved - 24 - 2 - read-write - - - REG_UART4_CLK_EN - Reserved - 26 - 1 - read-write - - - - - PERI_CLK_CTRL115 - Reserved - 0x7C - 0x20 - - - REG_UART4_SCLK_DIV_NUM - Reserved - 0 - 8 - read-write - - - REG_UART4_SCLK_DIV_NUMERATOR - Reserved - 8 - 8 - read-write - - - REG_UART4_SCLK_DIV_DENOMINATOR - Reserved - 16 - 8 - read-write - - - REG_TWAI0_CLK_SRC_SEL - Reserved - 24 - 1 - read-write - - - REG_TWAI0_CLK_EN - Reserved - 25 - 1 - read-write - - - REG_TWAI1_CLK_SRC_SEL - Reserved - 26 - 1 - read-write - - - REG_TWAI1_CLK_EN - Reserved - 27 - 1 - read-write - - - REG_TWAI2_CLK_SRC_SEL - Reserved - 28 - 1 - read-write - - - REG_TWAI2_CLK_EN - Reserved - 29 - 1 - read-write - - - - - PERI_CLK_CTRL116 - Reserved - 0x80 - 0x20 - 0x01100008 - - - REG_GPSPI2_CLK_SRC_SEL - Reserved - 0 - 3 - read-write - - - REG_GPSPI2_HS_CLK_EN - Reserved - 3 - 1 - read-write - - - REG_GPSPI2_HS_CLK_DIV_NUM - Reserved - 4 - 8 - read-write - - - REG_GPSPI2_MST_CLK_DIV_NUM - Reserved - 12 - 8 - read-write - - - REG_GPSPI2_MST_CLK_EN - Reserved - 20 - 1 - read-write - - - REG_GPSPI3_CLK_SRC_SEL - Reserved - 21 - 3 - read-write - - - REG_GPSPI3_HS_CLK_EN - Reserved - 24 - 1 - read-write - - - - - PERI_CLK_CTRL117 - Reserved - 0x84 - 0x20 - 0x00010000 - - - REG_GPSPI3_HS_CLK_DIV_NUM - Reserved - 0 - 8 - read-write - - - REG_GPSPI3_MST_CLK_DIV_NUM - Reserved - 8 - 8 - read-write - - - REG_GPSPI3_MST_CLK_EN - Reserved - 16 - 1 - read-write - - - REG_PARLIO_RX_CLK_SRC_SEL - Reserved - 17 - 2 - read-write - - - REG_PARLIO_RX_CLK_EN - Reserved - 19 - 1 - read-write - - - REG_PARLIO_RX_CLK_DIV_NUM - Reserved - 20 - 8 - read-write - - - - - PERI_CLK_CTRL118 - Reserved - 0x88 - 0x20 - - - REG_PARLIO_RX_CLK_DIV_NUMERATOR - Reserved - 0 - 8 - read-write - - - REG_PARLIO_RX_CLK_DIV_DENOMINATOR - Reserved - 8 - 8 - read-write - - - REG_PARLIO_TX_CLK_SRC_SEL - Reserved - 16 - 2 - read-write - - - REG_PARLIO_TX_CLK_EN - Reserved - 18 - 1 - read-write - - - REG_PARLIO_TX_CLK_DIV_NUM - Reserved - 19 - 8 - read-write - - - - - PERI_CLK_CTRL119 - Reserved - 0x8C - 0x20 - - - REG_PARLIO_TX_CLK_DIV_NUMERATOR - Reserved - 0 - 8 - read-write - - - REG_PARLIO_TX_CLK_DIV_DENOMINATOR - Reserved - 8 - 8 - read-write - - - REG_I3C_MST_CLK_SRC_SEL - Reserved - 16 - 2 - read-write - - - REG_I3C_MST_CLK_EN - Reserved - 18 - 1 - read-write - - - REG_I3C_MST_CLK_DIV_NUM - Reserved - 19 - 8 - read-write - - - REG_CAM_CLK_SRC_SEL - Reserved - 27 - 2 - read-write - - - REG_CAM_CLK_EN - Reserved - 29 - 1 - read-write - - - - - PERI_CLK_CTRL120 - Reserved - 0x90 - 0x20 - - - REG_CAM_CLK_DIV_NUM - Reserved - 0 - 8 - read-write - - - REG_CAM_CLK_DIV_NUMERATOR - Reserved - 8 - 8 - read-write - - - REG_CAM_CLK_DIV_DENOMINATOR - Reserved - 16 - 8 - read-write - - - - - PERI_CLK_CTRL20 - Reserved - 0x94 - 0x20 - 0xC9000000 - - - REG_MCPWM0_CLK_SRC_SEL - Reserved - 0 - 2 - read-write - - - REG_MCPWM0_CLK_EN - Reserved - 2 - 1 - read-write - - - REG_MCPWM0_CLK_DIV_NUM - Reserved - 3 - 8 - read-write - - - REG_MCPWM1_CLK_SRC_SEL - Reserved - 11 - 2 - read-write - - - REG_MCPWM1_CLK_EN - Reserved - 13 - 1 - read-write - - - REG_MCPWM1_CLK_DIV_NUM - Reserved - 14 - 8 - read-write - - - REG_TIMERGRP0_T0_SRC_SEL - Reserved - 22 - 2 - read-write - - - REG_TIMERGRP0_T0_CLK_EN - Reserved - 24 - 1 - read-write - - - REG_TIMERGRP0_T1_SRC_SEL - Reserved - 25 - 2 - read-write - - - REG_TIMERGRP0_T1_CLK_EN - Reserved - 27 - 1 - read-write - - - REG_TIMERGRP0_WDT_SRC_SEL - Reserved - 28 - 2 - read-write - - - REG_TIMERGRP0_WDT_CLK_EN - Reserved - 30 - 1 - read-write - - - REG_TIMERGRP0_TGRT_CLK_EN - Reserved - 31 - 1 - read-write - - - - - PERI_CLK_CTRL21 - Reserved - 0x98 - 0x20 - 0x52400000 - - - REG_TIMERGRP0_TGRT_CLK_SRC_SEL - Reserved - 0 - 4 - read-write - - - REG_TIMERGRP0_TGRT_CLK_DIV_NUM - Reserved - 4 - 16 - read-write - - - REG_TIMERGRP1_T0_SRC_SEL - Reserved - 20 - 2 - read-write - - - REG_TIMERGRP1_T0_CLK_EN - Reserved - 22 - 1 - read-write - - - REG_TIMERGRP1_T1_SRC_SEL - Reserved - 23 - 2 - read-write - - - REG_TIMERGRP1_T1_CLK_EN - Reserved - 25 - 1 - read-write - - - REG_TIMERGRP1_WDT_SRC_SEL - Reserved - 26 - 2 - read-write - - - REG_TIMERGRP1_WDT_CLK_EN - Reserved - 28 - 1 - read-write - - - REG_SYSTIMER_CLK_SRC_SEL - Reserved - 29 - 1 - read-write - - - REG_SYSTIMER_CLK_EN - Reserved - 30 - 1 - read-write - - - - - PERI_CLK_CTRL22 - Reserved - 0x9C - 0x20 - - - REG_LEDC_CLK_SRC_SEL - Reserved - 0 - 2 - read-write - - - REG_LEDC_CLK_EN - Reserved - 2 - 1 - read-write - - - REG_RMT_CLK_SRC_SEL - Reserved - 3 - 2 - read-write - - - REG_RMT_CLK_EN - Reserved - 5 - 1 - read-write - - - REG_RMT_CLK_DIV_NUM - Reserved - 6 - 8 - read-write - - - REG_RMT_CLK_DIV_NUMERATOR - Reserved - 14 - 8 - read-write - - - REG_RMT_CLK_DIV_DENOMINATOR - Reserved - 22 - 8 - read-write - - - REG_ADC_CLK_SRC_SEL - Reserved - 30 - 2 - read-write - - - - - PERI_CLK_CTRL23 - Reserved - 0xA0 - 0x20 - 0x00000008 - - - REG_ADC_CLK_EN - Reserved - 0 - 1 - read-write - - - REG_ADC_CLK_DIV_NUM - Reserved - 1 - 8 - read-write - - - REG_ADC_CLK_DIV_NUMERATOR - Reserved - 9 - 8 - read-write - - - REG_ADC_CLK_DIV_DENOMINATOR - Reserved - 17 - 8 - read-write - - - - - PERI_CLK_CTRL24 - Reserved - 0xA4 - 0x20 - 0x00000404 - - - REG_ADC_SAR1_CLK_DIV_NUM - Reserved - 0 - 8 - read-write - - - REG_ADC_SAR2_CLK_DIV_NUM - Reserved - 8 - 8 - read-write - - - REG_PVT_CLK_DIV_NUM - Reserved - 16 - 8 - read-write - - - REG_PVT_CLK_EN - Reserved - 24 - 1 - read-write - - - - - PERI_CLK_CTRL25 - Reserved - 0xA8 - 0x20 - 0x007FC000 - - - REG_PVT_PERI_GROUP_CLK_DIV_NUM - Reserved - 0 - 8 - read-write - - - REG_PVT_PERI_GROUP1_CLK_EN - Reserved - 8 - 1 - read-write - - - REG_PVT_PERI_GROUP2_CLK_EN - Reserved - 9 - 1 - read-write - - - REG_PVT_PERI_GROUP3_CLK_EN - Reserved - 10 - 1 - read-write - - - REG_PVT_PERI_GROUP4_CLK_EN - Reserved - 11 - 1 - read-write - - - REG_CRYPTO_CLK_SRC_SEL - Reserved - 12 - 2 - read-write - - - REG_CRYPTO_AES_CLK_EN - Reserved - 14 - 1 - read-write - - - REG_CRYPTO_DS_CLK_EN - Reserved - 15 - 1 - read-write - - - REG_CRYPTO_ECC_CLK_EN - Reserved - 16 - 1 - read-write - - - REG_CRYPTO_HMAC_CLK_EN - Reserved - 17 - 1 - read-write - - - REG_CRYPTO_RSA_CLK_EN - Reserved - 18 - 1 - read-write - - - REG_CRYPTO_SEC_CLK_EN - Reserved - 19 - 1 - read-write - - - REG_CRYPTO_SHA_CLK_EN - Reserved - 20 - 1 - read-write - - - REG_CRYPTO_ECDSA_CLK_EN - Reserved - 21 - 1 - read-write - - - REG_CRYPTO_KM_CLK_EN - Reserved - 22 - 1 - read-write - - - REG_ISP_CLK_SRC_SEL - Reserved - 23 - 2 - read-write - - - REG_ISP_CLK_EN - Reserved - 25 - 1 - read-write - - - - - PERI_CLK_CTRL26 - Reserved - 0xAC - 0x20 - 0x00000200 - - - REG_ISP_CLK_DIV_NUM - Reserved - 0 - 8 - read-write - - - REG_IOMUX_CLK_SRC_SEL - Reserved - 8 - 1 - read-write - - - REG_IOMUX_CLK_EN - Reserved - 9 - 1 - read-write - - - REG_IOMUX_CLK_DIV_NUM - Reserved - 10 - 8 - read-write - - - REG_H264_CLK_SRC_SEL - Reserved - 18 - 1 - read-write - - - REG_H264_CLK_EN - Reserved - 19 - 1 - read-write - - - REG_H264_CLK_DIV_NUM - Reserved - 20 - 8 - read-write - - - REG_PADBIST_RX_CLK_SRC_SEL - Reserved - 28 - 1 - read-write - - - REG_PADBIST_RX_CLK_EN - Reserved - 29 - 1 - read-write - - - - - PERI_CLK_CTRL27 - Reserved - 0xB0 - 0x20 - - - REG_PADBIST_RX_CLK_DIV_NUM - Reserved - 0 - 8 - read-write - - - REG_PADBIST_TX_CLK_SRC_SEL - Reserved - 8 - 1 - read-write - - - REG_PADBIST_TX_CLK_EN - Reserved - 9 - 1 - read-write - - - REG_PADBIST_TX_CLK_DIV_NUM - Reserved - 10 - 8 - read-write - - - - - CLK_FORCE_ON_CTRL0 - Reserved - 0xB4 - 0x20 - 0x0003FFFF - - - REG_CPUICM_GATED_CLK_FORCE_ON - Reserved - 0 - 1 - read-write - - - REG_TCM_CPU_CLK_FORCE_ON - Reserved - 1 - 1 - read-write - - - REG_BUSMON_CPU_CLK_FORCE_ON - Reserved - 2 - 1 - read-write - - - REG_L1CACHE_CPU_CLK_FORCE_ON - Reserved - 3 - 1 - read-write - - - REG_L1CACHE_D_CPU_CLK_FORCE_ON - Reserved - 4 - 1 - read-write - - - REG_L1CACHE_I0_CPU_CLK_FORCE_ON - Reserved - 5 - 1 - read-write - - - REG_L1CACHE_I1_CPU_CLK_FORCE_ON - Reserved - 6 - 1 - read-write - - - REG_TRACE_CPU_CLK_FORCE_ON - Reserved - 7 - 1 - read-write - - - REG_TRACE_SYS_CLK_FORCE_ON - Reserved - 8 - 1 - read-write - - - REG_L1CACHE_MEM_CLK_FORCE_ON - Reserved - 9 - 1 - read-write - - - REG_L1CACHE_D_MEM_CLK_FORCE_ON - Reserved - 10 - 1 - read-write - - - REG_L1CACHE_I0_MEM_CLK_FORCE_ON - Reserved - 11 - 1 - read-write - - - REG_L1CACHE_I1_MEM_CLK_FORCE_ON - Reserved - 12 - 1 - read-write - - - REG_L2CACHE_MEM_CLK_FORCE_ON - Reserved - 13 - 1 - read-write - - - REG_L2MEM_MEM_CLK_FORCE_ON - Reserved - 14 - 1 - read-write - - - REG_SAR1_CLK_FORCE_ON - Reserved - 15 - 1 - read-write - - - REG_SAR2_CLK_FORCE_ON - Reserved - 16 - 1 - read-write - - - REG_GMAC_TX_CLK_FORCE_ON - Reserved - 17 - 1 - read-write - - - - - DPA_CTRL0 - Reserved - 0xB8 - 0x20 - - - REG_SEC_DPA_LEVEL - Reserved - 0 - 2 - read-write - - - REG_SEC_DPA_CFG_SEL - Reserved - 2 - 1 - read-write - - - - - ANA_PLL_CTRL0 - Reserved - 0xBC - 0x20 - - - REG_PLLA_CAL_END - Reserved - 0 - 1 - read-only - - - REG_PLLA_CAL_STOP - Reserved - 1 - 1 - read-write - - - REG_CPU_PLL_CAL_END - Reserved - 2 - 1 - read-only - - - REG_CPU_PLL_CAL_STOP - Reserved - 3 - 1 - read-write - - - REG_SDIO_PLL_CAL_END - Reserved - 4 - 1 - read-only - - - REG_SDIO_PLL_CAL_STOP - Reserved - 5 - 1 - read-write - - - REG_SYS_PLL_CAL_END - Reserved - 6 - 1 - read-only - - - REG_SYS_PLL_CAL_STOP - Reserved - 7 - 1 - read-write - - - REG_MSPI_CAL_END - Reserved - 8 - 1 - read-only - - - REG_MSPI_CAL_STOP - Reserved - 9 - 1 - read-write - - - - - HP_RST_EN0 - Reserved - 0xC0 - 0x20 - 0x00000100 - - - REG_RST_EN_CORECTRL - Reserved - 0 - 1 - read-write - - - REG_RST_EN_PVT_TOP - Reserved - 1 - 1 - read-write - - - REG_RST_EN_PVT_PERI_GROUP1 - Reserved - 2 - 1 - read-write - - - REG_RST_EN_PVT_PERI_GROUP2 - Reserved - 3 - 1 - read-write - - - REG_RST_EN_PVT_PERI_GROUP3 - Reserved - 4 - 1 - read-write - - - REG_RST_EN_PVT_PERI_GROUP4 - Reserved - 5 - 1 - read-write - - - REG_RST_EN_REGDMA - Reserved - 6 - 1 - read-write - - - REG_RST_EN_CORE0_GLOBAL - Reserved - 7 - 1 - read-write - - - REG_RST_EN_CORE1_GLOBAL - Reserved - 8 - 1 - read-write - - - REG_RST_EN_CORETRACE0 - Reserved - 9 - 1 - read-write - - - REG_RST_EN_CORETRACE1 - Reserved - 10 - 1 - read-write - - - REG_RST_EN_HP_TCM - Reserved - 11 - 1 - read-write - - - REG_RST_EN_HP_CACHE - Reserved - 12 - 1 - read-write - - - REG_RST_EN_L1_I0_CACHE - Reserved - 13 - 1 - read-write - - - REG_RST_EN_L1_I1_CACHE - Reserved - 14 - 1 - read-write - - - REG_RST_EN_L1_D_CACHE - Reserved - 15 - 1 - read-write - - - REG_RST_EN_L2_CACHE - Reserved - 16 - 1 - read-write - - - REG_RST_EN_L2_MEM - Reserved - 17 - 1 - read-write - - - REG_RST_EN_L2MEMMON - Reserved - 18 - 1 - read-write - - - REG_RST_EN_TCMMON - Reserved - 19 - 1 - read-write - - - REG_RST_EN_PVT_APB - Reserved - 20 - 1 - read-write - - - REG_RST_EN_GDMA - Reserved - 21 - 1 - read-write - - - REG_RST_EN_MSPI_AXI - Reserved - 22 - 1 - read-write - - - REG_RST_EN_DUAL_MSPI_AXI - Reserved - 23 - 1 - read-write - - - REG_RST_EN_MSPI_APB - Reserved - 24 - 1 - read-write - - - REG_RST_EN_DUAL_MSPI_APB - Reserved - 25 - 1 - read-write - - - REG_RST_EN_DSI_BRG - Reserved - 26 - 1 - read-write - - - REG_RST_EN_CSI_HOST - Reserved - 27 - 1 - read-write - - - REG_RST_EN_CSI_BRG - Reserved - 28 - 1 - read-write - - - REG_RST_EN_ISP - Reserved - 29 - 1 - read-write - - - REG_RST_EN_JPEG - Reserved - 30 - 1 - read-write - - - REG_RST_EN_DMA2D - Reserved - 31 - 1 - read-write - - - - - HP_RST_EN1 - Reserved - 0xC4 - 0x20 - - - REG_RST_EN_PPA - Reserved - 0 - 1 - read-write - - - REG_RST_EN_AHB_PDMA - Reserved - 1 - 1 - read-write - - - REG_RST_EN_AXI_PDMA - Reserved - 2 - 1 - read-write - - - REG_RST_EN_IOMUX - Reserved - 3 - 1 - read-write - - - REG_RST_EN_PADBIST - Reserved - 4 - 1 - read-write - - - REG_RST_EN_STIMER - Reserved - 5 - 1 - read-write - - - REG_RST_EN_TIMERGRP0 - Reserved - 6 - 1 - read-write - - - REG_RST_EN_TIMERGRP1 - Reserved - 7 - 1 - read-write - - - REG_RST_EN_UART0_CORE - Reserved - 8 - 1 - read-write - - - REG_RST_EN_UART1_CORE - Reserved - 9 - 1 - read-write - - - REG_RST_EN_UART2_CORE - Reserved - 10 - 1 - read-write - - - REG_RST_EN_UART3_CORE - Reserved - 11 - 1 - read-write - - - REG_RST_EN_UART4_CORE - Reserved - 12 - 1 - read-write - - - REG_RST_EN_UART0_APB - Reserved - 13 - 1 - read-write - - - REG_RST_EN_UART1_APB - Reserved - 14 - 1 - read-write - - - REG_RST_EN_UART2_APB - Reserved - 15 - 1 - read-write - - - REG_RST_EN_UART3_APB - Reserved - 16 - 1 - read-write - - - REG_RST_EN_UART4_APB - Reserved - 17 - 1 - read-write - - - REG_RST_EN_UHCI - Reserved - 18 - 1 - read-write - - - REG_RST_EN_I3CMST - Reserved - 19 - 1 - read-write - - - REG_RST_EN_I3CSLV - Reserved - 20 - 1 - read-write - - - REG_RST_EN_I2C1 - Reserved - 21 - 1 - read-write - - - REG_RST_EN_I2C0 - Reserved - 22 - 1 - read-write - - - REG_RST_EN_RMT - Reserved - 23 - 1 - read-write - - - REG_RST_EN_PWM0 - Reserved - 24 - 1 - read-write - - - REG_RST_EN_PWM1 - Reserved - 25 - 1 - read-write - - - REG_RST_EN_CAN0 - Reserved - 26 - 1 - read-write - - - REG_RST_EN_CAN1 - Reserved - 27 - 1 - read-write - - - REG_RST_EN_CAN2 - Reserved - 28 - 1 - read-write - - - REG_RST_EN_LEDC - Reserved - 29 - 1 - read-write - - - REG_RST_EN_PCNT - Reserved - 30 - 1 - read-write - - - REG_RST_EN_ETM - Reserved - 31 - 1 - read-write - - - - - HP_RST_EN2 - Reserved - 0xC8 - 0x20 - - - REG_RST_EN_INTRMTX - Reserved - 0 - 1 - read-write - - - REG_RST_EN_PARLIO - Reserved - 1 - 1 - read-write - - - REG_RST_EN_PARLIO_RX - Reserved - 2 - 1 - read-write - - - REG_RST_EN_PARLIO_TX - Reserved - 3 - 1 - read-write - - - REG_RST_EN_I2S0_APB - Reserved - 4 - 1 - read-write - - - REG_RST_EN_I2S1_APB - Reserved - 5 - 1 - read-write - - - REG_RST_EN_I2S2_APB - Reserved - 6 - 1 - read-write - - - REG_RST_EN_SPI2 - Reserved - 7 - 1 - read-write - - - REG_RST_EN_SPI3 - Reserved - 8 - 1 - read-write - - - REG_RST_EN_LCDCAM - Reserved - 9 - 1 - read-write - - - REG_RST_EN_ADC - Reserved - 10 - 1 - read-write - - - REG_RST_EN_BITSRAMBLER - Reserved - 11 - 1 - read-write - - - REG_RST_EN_BITSRAMBLER_RX - Reserved - 12 - 1 - read-write - - - REG_RST_EN_BITSRAMBLER_TX - Reserved - 13 - 1 - read-write - - - REG_RST_EN_CRYPTO - Reserved - 14 - 1 - read-write - - - REG_RST_EN_SEC - Reserved - 15 - 1 - read-write - - - REG_RST_EN_AES - Reserved - 16 - 1 - read-write - - - REG_RST_EN_DS - Reserved - 17 - 1 - read-write - - - REG_RST_EN_SHA - Reserved - 18 - 1 - read-write - - - REG_RST_EN_HMAC - Reserved - 19 - 1 - read-write - - - REG_RST_EN_ECDSA - Reserved - 20 - 1 - read-write - - - REG_RST_EN_RSA - Reserved - 21 - 1 - read-write - - - REG_RST_EN_ECC - Reserved - 22 - 1 - read-write - - - REG_RST_EN_KM - Reserved - 23 - 1 - read-write - - - REG_RST_EN_H264 - Reserved - 24 - 1 - read-write - - - - - HP_FORCE_NORST0 - Reserved - 0xCC - 0x20 - - - REG_FORCE_NORST_CORE0 - Reserved - 0 - 1 - read-write - - - REG_FORCE_NORST_CORE1 - Reserved - 1 - 1 - read-write - - - REG_FORCE_NORST_CORETRACE0 - Reserved - 2 - 1 - read-write - - - REG_FORCE_NORST_CORETRACE1 - Reserved - 3 - 1 - read-write - - - REG_FORCE_NORST_L2MEMMON - Reserved - 4 - 1 - read-write - - - REG_FORCE_NORST_TCMMON - Reserved - 5 - 1 - read-write - - - REG_FORCE_NORST_GDMA - Reserved - 6 - 1 - read-write - - - REG_FORCE_NORST_MSPI_AXI - Reserved - 7 - 1 - read-write - - - REG_FORCE_NORST_DUAL_MSPI_AXI - Reserved - 8 - 1 - read-write - - - REG_FORCE_NORST_MSPI_APB - Reserved - 9 - 1 - read-write - - - REG_FORCE_NORST_DUAL_MSPI_APB - Reserved - 10 - 1 - read-write - - - REG_FORCE_NORST_DSI_BRG - Reserved - 11 - 1 - read-write - - - REG_FORCE_NORST_CSI_HOST - Reserved - 12 - 1 - read-write - - - REG_FORCE_NORST_CSI_BRG - Reserved - 13 - 1 - read-write - - - REG_FORCE_NORST_ISP - Reserved - 14 - 1 - read-write - - - REG_FORCE_NORST_JPEG - Reserved - 15 - 1 - read-write - - - REG_FORCE_NORST_DMA2D - Reserved - 16 - 1 - read-write - - - REG_FORCE_NORST_PPA - Reserved - 17 - 1 - read-write - - - REG_FORCE_NORST_AHB_PDMA - Reserved - 18 - 1 - read-write - - - REG_FORCE_NORST_AXI_PDMA - Reserved - 19 - 1 - read-write - - - REG_FORCE_NORST_IOMUX - Reserved - 20 - 1 - read-write - - - REG_FORCE_NORST_PADBIST - Reserved - 21 - 1 - read-write - - - REG_FORCE_NORST_STIMER - Reserved - 22 - 1 - read-write - - - REG_FORCE_NORST_TIMERGRP0 - Reserved - 23 - 1 - read-write - - - REG_FORCE_NORST_TIMERGRP1 - Reserved - 24 - 1 - read-write - - - REG_FORCE_NORST_UART0 - Reserved - 25 - 1 - read-write - - - REG_FORCE_NORST_UART1 - Reserved - 26 - 1 - read-write - - - REG_FORCE_NORST_UART2 - Reserved - 27 - 1 - read-write - - - REG_FORCE_NORST_UART3 - Reserved - 28 - 1 - read-write - - - REG_FORCE_NORST_UART4 - Reserved - 29 - 1 - read-write - - - REG_FORCE_NORST_UHCI - Reserved - 30 - 1 - read-write - - - REG_FORCE_NORST_I3CMST - Reserved - 31 - 1 - read-write - - - - - HP_FORCE_NORST1 - Reserved - 0xD0 - 0x20 - - - REG_FORCE_NORST_I3CSLV - Reserved - 0 - 1 - read-write - - - REG_FORCE_NORST_I2C1 - Reserved - 1 - 1 - read-write - - - REG_FORCE_NORST_I2C0 - Reserved - 2 - 1 - read-write - - - REG_FORCE_NORST_RMT - Reserved - 3 - 1 - read-write - - - REG_FORCE_NORST_PWM0 - Reserved - 4 - 1 - read-write - - - REG_FORCE_NORST_PWM1 - Reserved - 5 - 1 - read-write - - - REG_FORCE_NORST_CAN0 - Reserved - 6 - 1 - read-write - - - REG_FORCE_NORST_CAN1 - Reserved - 7 - 1 - read-write - - - REG_FORCE_NORST_CAN2 - Reserved - 8 - 1 - read-write - - - REG_FORCE_NORST_LEDC - Reserved - 9 - 1 - read-write - - - REG_FORCE_NORST_PCNT - Reserved - 10 - 1 - read-write - - - REG_FORCE_NORST_ETM - Reserved - 11 - 1 - read-write - - - REG_FORCE_NORST_INTRMTX - Reserved - 12 - 1 - read-write - - - REG_FORCE_NORST_PARLIO - Reserved - 13 - 1 - read-write - - - REG_FORCE_NORST_PARLIO_RX - Reserved - 14 - 1 - read-write - - - REG_FORCE_NORST_PARLIO_TX - Reserved - 15 - 1 - read-write - - - REG_FORCE_NORST_I2S0 - Reserved - 16 - 1 - read-write - - - REG_FORCE_NORST_I2S1 - Reserved - 17 - 1 - read-write - - - REG_FORCE_NORST_I2S2 - Reserved - 18 - 1 - read-write - - - REG_FORCE_NORST_SPI2 - Reserved - 19 - 1 - read-write - - - REG_FORCE_NORST_SPI3 - Reserved - 20 - 1 - read-write - - - REG_FORCE_NORST_LCDCAM - Reserved - 21 - 1 - read-write - - - REG_FORCE_NORST_ADC - Reserved - 22 - 1 - read-write - - - REG_FORCE_NORST_BITSRAMBLER - Reserved - 23 - 1 - read-write - - - REG_FORCE_NORST_BITSRAMBLER_RX - Reserved - 24 - 1 - read-write - - - REG_FORCE_NORST_BITSRAMBLER_TX - Reserved - 25 - 1 - read-write - - - REG_FORCE_NORST_H264 - Reserved - 26 - 1 - read-write - - - - - HPWDT_CORE0_RST_CTRL0 - Reserved - 0xD4 - 0x20 - 0x00001011 - - - REG_HPCORE0_STALL_EN - Reserved - 0 - 1 - read-write - - - REG_HPCORE0_STALL_WAIT_NUM - Reserved - 1 - 8 - read-write - - - REG_WDT_HPCORE0_RST_LEN - Reserved - 9 - 8 - read-write - - - - - HPWDT_CORE1_RST_CTRL0 - Reserved - 0xD8 - 0x20 - 0x00001011 - - - REG_HPCORE1_STALL_EN - Reserved - 0 - 1 - read-write - - - REG_HPCORE1_STALL_WAIT_NUM - Reserved - 1 - 8 - read-write - - - REG_WDT_HPCORE1_RST_LEN - Reserved - 9 - 8 - read-write - - - - - CPU_SRC_FREQ0 - CPU Source Frequency - 0xDC - 0x20 - - - REG_CPU_SRC_FREQ - cpu source clock frequency, step by 0.25MHz - 0 - 32 - read-only - - - - - CPU_CLK_STATUS0 - CPU Clock Status - 0xE0 - 0x20 - - - REG_ASIC_OR_FPGA - 0: ASIC mode, 1: FPGA mode - 0 - 1 - read-only - - - REG_CPU_DIV_EFFECT - 0: Divider bypass, 1: Divider takes effect - 1 - 1 - read-only - - - REG_CPU_SRC_IS_CPLL - 0: CPU source isn't cpll_400m, 1: CPU Source is cll_400m - 2 - 1 - read-only - - - REG_CPU_DIV_NUM_CUR - cpu current div number - 3 - 8 - read-only - - - REG_CPU_DIV_NUMERATOR_CUR - cpu current div numerator - 11 - 8 - read-only - - - REG_CPU_DIV_DENOMINATOR_CUR - cpu current div denominator - 19 - 8 - read-only - - - - - DBG_CLK_CTRL0 - Reserved - 0xE4 - 0x20 - 0x03FFFFFF - - - REG_DBG_CH0_SEL - Reserved - 0 - 8 - read-write - - - REG_DBG_CH1_SEL - Reserved - 8 - 8 - read-write - - - REG_DBG_CH2_SEL - Reserved - 16 - 8 - read-write - - - REG_DBG_CH0_DIV_NUM - Reserved - 24 - 8 - read-write - - - - - DBG_CLK_CTRL1 - Reserved - 0xE8 - 0x20 - 0x00000303 - - - REG_DBG_CH1_DIV_NUM - Reserved - 0 - 8 - read-write - - - REG_DBG_CH2_DIV_NUM - Reserved - 8 - 8 - read-write - - - REG_DBG_CH0_EN - Reserved - 16 - 1 - read-write - - - REG_DBG_CH1_EN - Reserved - 17 - 1 - read-write - - - REG_DBG_CH2_EN - Reserved - 18 - 1 - read-write - - - - - HPCORE_WDT_RESET_SOURCE0 - Reserved - 0xEC - 0x20 - 0x00000002 - - - REG_HPCORE0_WDT_RESET_SOURCE_SEL - 1'b0: use wdt0 to reset hpcore0, 1'b1: use wdt1 to reset hpcore0 - 0 - 1 - read-write - - - REG_HPCORE1_WDT_RESET_SOURCE_SEL - 1'b0: use wdt0 to reset hpcore1, 1'b1: use wdt1 to reset hpcore1 - 1 - 1 - read-write - - - - - - - LP_HUK - LP_HUK Peripheral - HUK - 0x50114000 - - 0x0 - 0x1A8 - registers - - - LP_HUK - 20 - - - - CLK - HUK Generator clock gate control register - 0x4 - 0x20 - 0x00000001 - - - EN - Write 1 to force on register clock gate. - 0 - 1 - read-write - - - MEM_CG_FORCE_ON - Write 1 to force on memory clock gate. - 1 - 1 - read-write - - - - - INT_RAW - HUK Generator interrupt raw register, valid in level. - 0x8 - 0x20 - - - PREP_DONE_INT_RAW - The raw interrupt status bit for the huk_prep_done_int interrupt - 0 - 1 - read-only - - - PROC_DONE_INT_RAW - The raw interrupt status bit for the huk_proc_done_int interrupt - 1 - 1 - read-only - - - POST_DONE_INT_RAW - The raw interrupt status bit for the huk_post_done_int interrupt - 2 - 1 - read-only - - - - - INT_ST - HUK Generator interrupt status register. - 0xC - 0x20 - - - PREP_DONE_INT_ST - The masked interrupt status bit for the huk_prep_done_int interrupt - 0 - 1 - read-only - - - PROC_DONE_INT_ST - The masked interrupt status bit for the huk_proc_done_int interrupt - 1 - 1 - read-only - - - POST_DONE_INT_ST - The masked interrupt status bit for the huk_post_done_int interrupt - 2 - 1 - read-only - - - - - INT_ENA - HUK Generator interrupt enable register. - 0x10 - 0x20 - - - PREP_DONE_INT_ENA - The interrupt enable bit for the huk_prep_done_int interrupt - 0 - 1 - read-write - - - PROC_DONE_INT_ENA - The interrupt enable bit for the huk_proc_done_int interrupt - 1 - 1 - read-write - - - POST_DONE_INT_ENA - The interrupt enable bit for the huk_post_done_int interrupt - 2 - 1 - read-write - - - - - INT_CLR - HUK Generator interrupt clear register. - 0x14 - 0x20 - - - PREP_DONE_INT_CLR - Set this bit to clear the huk_prep_done_int interrupt - 0 - 1 - write-only - - - PROC_DONE_INT_CLR - Set this bit to clear the huk_proc_done_int interrupt - 1 - 1 - write-only - - - POST_DONE_INT_CLR - Set this bit to clear the huk_post_done_int interrupt - 2 - 1 - write-only - - - - - CONF - HUK Generator configuration register - 0x20 - 0x20 - - - MODE - Set this field to choose the huk process. 1: process huk generate mode. 0: process huk recovery mode. - 0 - 1 - read-write - - - - - START - HUK Generator control register - 0x24 - 0x20 - - - START - Write 1 to continue HUK Generator operation at LOAD/GAIN state. - 0 - 1 - write-only - - - CONTINUE - Write 1 to start HUK Generator at IDLE state. - 1 - 1 - write-only - - - - - STATE - HUK Generator state register - 0x28 - 0x20 - - - STATE - The state of HUK Generator. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY. - 0 - 2 - read-only - - - - - STATUS - HUK Generator HUK status register - 0x34 - 0x20 - - - STATUS - The HUK generation status. 0: HUK is not generated. 1: HUK is generated and valid. 2: HUK is generated but invalid. 3: reserved. - 0 - 2 - read-only - - - RISK_LEVEL - The risk level of HUK. 0-6: the higher the risk level is, the more error bits there are in the PUF SRAM. 7: Error Level, HUK is invalid. - 2 - 3 - read-only - - - - - DATE - Version control register - 0xFC - 0x20 - 0x02305040 - - - DATE - HUK Generator version control register. - 0 - 28 - read-write - - - - - 384 - 0x1 - INFO_MEM[%s] - The memory that stores HUK info. - 0x100 - 0x8 - - - - - I2C0 - I2C (Inter-Integrated Circuit) Controller 0 - I2C - 0x500C4000 - - 0x0 - 0x90 - registers - - - I2C0 - 44 - - - - SCL_LOW_PERIOD - Configures the low level width of the SCL Clock. - 0x0 - 0x20 - - - SCL_LOW_PERIOD - Configures the low level width of the SCL Clock. -Measurement unit: i2c_sclk. - 0 - 9 - read-write - - - - - CTR - Transmission setting - 0x4 - 0x20 - 0x00000208 - - - SDA_FORCE_OUT - Configures the SDA output mode -1: Direct output, - -0: Open drain output. - 0 - 1 - read-write - - - SCL_FORCE_OUT - Configures the SCL output mode -1: Direct output, - -0: Open drain output. - 1 - 1 - read-write - - - SAMPLE_SCL_LEVEL - Configures the sample mode for SDA. -1: Sample SDA data on the SCL low level. - -0: Sample SDA data on the SCL high level. - 2 - 1 - read-write - - - RX_FULL_ACK_LEVEL - Configures the ACK value that needs to be sent by master when the rx_fifo_cnt has reached the threshold. - 3 - 1 - read-write - - - MS_MODE - Configures the module as an I2C Master or Slave. -0: Slave - -1: Master - 4 - 1 - read-write - - - TRANS_START - Configures to start sending the data in txfifo for slave. -0: No effect - -1: Start - 5 - 1 - write-only - - - TX_LSB_FIRST - Configures to control the sending order for data needing to be sent. -1: send data from the least significant bit, - -0: send data from the most significant bit. - 6 - 1 - read-write - - - RX_LSB_FIRST - Configures to control the storage order for received data. -1: receive data from the least significant bit - -0: receive data from the most significant bit. - 7 - 1 - read-write - - - CLK_EN - Configures whether to gate clock signal for registers. - -0: Force clock on for registers - -1: Support clock only when registers are read or written to by software. - 8 - 1 - read-write - - - ARBITRATION_EN - Configures to enable I2C bus arbitration detection. -0: No effect - -1: Enable - 9 - 1 - read-write - - - FSM_RST - Configures to reset the SCL_FSM. -0: No effect - -1: Reset - 10 - 1 - write-only - - - CONF_UPGATE - Configures this bit for synchronization -0: No effect - -1: Synchronize - 11 - 1 - write-only - - - SLV_TX_AUTO_START_EN - Configures to enable slave to send data automatically -0: Disable - -1: Enable - 12 - 1 - read-write - - - ADDR_10BIT_RW_CHECK_EN - Configures to check if the r/w bit of 10bit addressing consists with I2C protocol. -0: Not check - -1: Check - 13 - 1 - read-write - - - ADDR_BROADCASTING_EN - Configures to support the 7bit general call function. -0: Not support - -1: Support - 14 - 1 - read-write - - - - - SR - Describe I2C work status. - 0x8 - 0x20 - 0x0000C000 - - - RESP_REC - Represents the received ACK value in master mode or slave mode. -0: ACK, - -1: NACK. - 0 - 1 - read-only - - - SLAVE_RW - Represents the transfer direction in slave mode,. -1: Master reads from slave, - -0: Master writes to slave. - 1 - 1 - read-only - - - ARB_LOST - Represents whether the I2C controller loses control of SCL line. -0: No arbitration lost - -1: Arbitration lost - 3 - 1 - read-only - - - BUS_BUSY - Represents the I2C bus state. -1: The I2C bus is busy transferring data, - -0: The I2C bus is in idle state. - 4 - 1 - read-only - - - SLAVE_ADDRESSED - Represents whether the address sent by the master is equal to the address of the slave. -Valid only when the module is configured as an I2C Slave. -0: Not equal - -1: Equal - 5 - 1 - read-only - - - RXFIFO_CNT - Represents the number of data bytes to be sent. - 8 - 6 - read-only - - - STRETCH_CAUSE - Represents the cause of SCL clocking stretching in slave mode. -0: Stretching SCL low when the master starts to read data. - -1: Stretching SCL low when I2C TX FIFO is empty in slave mode. - -2: Stretching SCL low when I2C RX FIFO is full in slave mode. - 14 - 2 - read-only - - - TXFIFO_CNT - Represents the number of data bytes received in RAM. - 18 - 6 - read-only - - - SCL_MAIN_STATE_LAST - Represents the states of the I2C module state machine. -0: Idle, - -1: Address shift, - -2: ACK address, - -3: Rx data, - -4: Tx data, - -5: Send ACK, - -6: Wait ACK - 24 - 3 - read-only - - - SCL_STATE_LAST - Represents the states of the state machine used to produce SCL. -0: Idle, - -1: Start, - -2: Negative edge, - -3: Low, - -4: Positive edge, - -5: High, - -6: Stop - 28 - 3 - read-only - - - - - TO - Setting time out control for receiving data. - 0xC - 0x20 - 0x00000010 - - - TIME_OUT_VALUE - Configures the timeout threshold period for SCL stucking at high or low level. The actual period is 2^(reg_time_out_value). -Measurement unit: i2c_sclk. - 0 - 5 - read-write - - - TIME_OUT_EN - Configures to enable time out control. -0: No effect - -1: Enable - 5 - 1 - read-write - - - - - SLAVE_ADDR - Local slave address setting - 0x10 - 0x20 - - - SLAVE_ADDR - Configure the slave address of I2C Slave. - 0 - 15 - read-write - - - ADDR_10BIT_EN - Configures to enable the slave 10-bit addressing mode in master mode. -0: No effect - -1: Enable - 31 - 1 - read-write - - - - - FIFO_ST - FIFO status register. - 0x14 - 0x20 - - - RXFIFO_RADDR - Represents the offset address of the APB reading from RXFIFO - 0 - 5 - read-only - - - RXFIFO_WADDR - Represents the offset address of i2c module receiving data and writing to RXFIFO. - 5 - 5 - read-only - - - TXFIFO_RADDR - Represents the offset address of i2c module reading from TXFIFO. - 10 - 5 - read-only - - - TXFIFO_WADDR - Represents the offset address of APB bus writing to TXFIFO. - 15 - 5 - read-only - - - SLAVE_RW_POINT - Represents the offset address in the I2C Slave RAM addressed by I2C Master when in I2C slave mode. - 22 - 8 - read-only - - - - - FIFO_CONF - FIFO configuration register. - 0x18 - 0x20 - 0x0000408B - - - RXFIFO_WM_THRHD - Configures the water mark threshold of RXFIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than reg_rxfifo_wm_thrhd[4:0], reg_rxfifo_wm_int_raw bit will be valid. - 0 - 5 - read-write - - - TXFIFO_WM_THRHD - Configures the water mark threshold of TXFIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than reg_txfifo_wm_thrhd[4:0], reg_txfifo_wm_int_raw bit will be valid. - 5 - 5 - read-write - - - NONFIFO_EN - Configures to enable APB nonfifo access. - 10 - 1 - read-write - - - FIFO_ADDR_CFG_EN - Configures to enable double addressing mode. When this mode is enabled, the byte received after the I2C address byte represents the offset address in the I2C Slave RAM. -0: Disable - -1: Enable - 11 - 1 - read-write - - - RX_FIFO_RST - Configures to reset RXFIFO. -0: No effect - -1: Reset - 12 - 1 - read-write - - - TX_FIFO_RST - Configures to reset TXFIFO. -0: No effect - -1: Reset - 13 - 1 - read-write - - - FIFO_PRT_EN - Configures to enable FIFO pointer in non-fifo access mode. This bit controls the valid bits and the TX/RX FIFO overflow, underflow, full and empty interrupts. -0: No effect - -1: Enable - 14 - 1 - read-write - - - - - DATA - Rx FIFO read data. - 0x1C - 0x20 - - - FIFO_RDATA - Represents the value of RXFIFO read data. - 0 - 8 - read-only - - - - - INT_RAW - Raw interrupt status - 0x20 - 0x20 - 0x00000002 - - - RXFIFO_WM_INT_RAW - The raw interrupt status of I2C_RXFIFO_WM_INT interrupt. - 0 - 1 - read-only - - - TXFIFO_WM_INT_RAW - The raw interrupt status of I2C_TXFIFO_WM_INT interrupt. - 1 - 1 - read-only - - - RXFIFO_OVF_INT_RAW - The raw interrupt status of I2C_RXFIFO_OVF_INT interrupt. - 2 - 1 - read-only - - - END_DETECT_INT_RAW - The raw interrupt status of the I2C_END_DETECT_INT interrupt. - 3 - 1 - read-only - - - BYTE_TRANS_DONE_INT_RAW - The raw interrupt status of the I2C_END_DETECT_INT interrupt. - 4 - 1 - read-only - - - ARBITRATION_LOST_INT_RAW - The raw interrupt status of the I2C_ARBITRATION_LOST_INT interrupt. - 5 - 1 - read-only - - - MST_TXFIFO_UDF_INT_RAW - The raw interrupt status of I2C_TRANS_COMPLETE_INT interrupt. - 6 - 1 - read-only - - - TRANS_COMPLETE_INT_RAW - The raw interrupt status of the I2C_TRANS_COMPLETE_INT interrupt. - 7 - 1 - read-only - - - TIME_OUT_INT_RAW - The raw interrupt status of the I2C_TIME_OUT_INT interrupt. - 8 - 1 - read-only - - - TRANS_START_INT_RAW - The raw interrupt status of the I2C_TRANS_START_INT interrupt. - 9 - 1 - read-only - - - NACK_INT_RAW - The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt. - 10 - 1 - read-only - - - TXFIFO_OVF_INT_RAW - The raw interrupt status of I2C_TXFIFO_OVF_INT interrupt. - 11 - 1 - read-only - - - RXFIFO_UDF_INT_RAW - The raw interrupt status of I2C_RXFIFO_UDF_INT interrupt. - 12 - 1 - read-only - - - SCL_ST_TO_INT_RAW - The raw interrupt status of I2C_SCL_ST_TO_INT interrupt. - 13 - 1 - read-only - - - SCL_MAIN_ST_TO_INT_RAW - The raw interrupt status of I2C_SCL_MAIN_ST_TO_INT interrupt. - 14 - 1 - read-only - - - DET_START_INT_RAW - The raw interrupt status of I2C_DET_START_INT interrupt. - 15 - 1 - read-only - - - SLAVE_STRETCH_INT_RAW - The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt. - 16 - 1 - read-only - - - GENERAL_CALL_INT_RAW - The raw interrupt status of I2C_GENARAL_CALL_INT interrupt. - 17 - 1 - read-only - - - SLAVE_ADDR_UNMATCH_INT_RAW - The raw interrupt status of I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt. - 18 - 1 - read-only - - - - - INT_CLR - Interrupt clear bits - 0x24 - 0x20 - - - RXFIFO_WM_INT_CLR - Write 1 to clear I2C_RXFIFO_WM_INT interrupt. - 0 - 1 - write-only - - - TXFIFO_WM_INT_CLR - Write 1 to clear I2C_TXFIFO_WM_INT interrupt. - 1 - 1 - write-only - - - RXFIFO_OVF_INT_CLR - Write 1 to clear I2C_RXFIFO_OVF_INT interrupt. - 2 - 1 - write-only - - - END_DETECT_INT_CLR - Write 1 to clear the I2C_END_DETECT_INT interrupt. - 3 - 1 - write-only - - - BYTE_TRANS_DONE_INT_CLR - Write 1 to clear the I2C_END_DETECT_INT interrupt. - 4 - 1 - write-only - - - ARBITRATION_LOST_INT_CLR - Write 1 to clear the I2C_ARBITRATION_LOST_INT interrupt. - 5 - 1 - write-only - - - MST_TXFIFO_UDF_INT_CLR - Write 1 to clear I2C_TRANS_COMPLETE_INT interrupt. - 6 - 1 - write-only - - - TRANS_COMPLETE_INT_CLR - Write 1 to clear the I2C_TRANS_COMPLETE_INT interrupt. - 7 - 1 - write-only - - - TIME_OUT_INT_CLR - Write 1 to clear the I2C_TIME_OUT_INT interrupt. - 8 - 1 - write-only - - - TRANS_START_INT_CLR - Write 1 to clear the I2C_TRANS_START_INT interrupt. - 9 - 1 - write-only - - - NACK_INT_CLR - Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt. - 10 - 1 - write-only - - - TXFIFO_OVF_INT_CLR - Write 1 to clear I2C_TXFIFO_OVF_INT interrupt. - 11 - 1 - write-only - - - RXFIFO_UDF_INT_CLR - Write 1 to clear I2C_RXFIFO_UDF_INT interrupt. - 12 - 1 - write-only - - - SCL_ST_TO_INT_CLR - Write 1 to clear I2C_SCL_ST_TO_INT interrupt. - 13 - 1 - write-only - - - SCL_MAIN_ST_TO_INT_CLR - Write 1 to clear I2C_SCL_MAIN_ST_TO_INT interrupt. - 14 - 1 - write-only - - - DET_START_INT_CLR - Write 1 to clear I2C_DET_START_INT interrupt. - 15 - 1 - write-only - - - SLAVE_STRETCH_INT_CLR - Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt. - 16 - 1 - write-only - - - GENERAL_CALL_INT_CLR - Write 1 to clear I2C_GENARAL_CALL_INT interrupt. - 17 - 1 - write-only - - - SLAVE_ADDR_UNMATCH_INT_CLR - Write 1 to clear I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt. - 18 - 1 - write-only - - - - - INT_ENA - Interrupt enable bits - 0x28 - 0x20 - - - RXFIFO_WM_INT_ENA - Write 1 to enable I2C_RXFIFO_WM_INT interrupt. - 0 - 1 - read-write - - - TXFIFO_WM_INT_ENA - Write 1 to enable I2C_TXFIFO_WM_INT interrupt. - 1 - 1 - read-write - - - RXFIFO_OVF_INT_ENA - Write 1 to enable I2C_RXFIFO_OVF_INT interrupt. - 2 - 1 - read-write - - - END_DETECT_INT_ENA - Write 1 to enable the I2C_END_DETECT_INT interrupt. - 3 - 1 - read-write - - - BYTE_TRANS_DONE_INT_ENA - Write 1 to enable the I2C_END_DETECT_INT interrupt. - 4 - 1 - read-write - - - ARBITRATION_LOST_INT_ENA - Write 1 to enable the I2C_ARBITRATION_LOST_INT interrupt. - 5 - 1 - read-write - - - MST_TXFIFO_UDF_INT_ENA - Write 1 to enable I2C_TRANS_COMPLETE_INT interrupt. - 6 - 1 - read-write - - - TRANS_COMPLETE_INT_ENA - Write 1 to enable the I2C_TRANS_COMPLETE_INT interrupt. - 7 - 1 - read-write - - - TIME_OUT_INT_ENA - Write 1 to enable the I2C_TIME_OUT_INT interrupt. - 8 - 1 - read-write - - - TRANS_START_INT_ENA - Write 1 to enable the I2C_TRANS_START_INT interrupt. - 9 - 1 - read-write - - - NACK_INT_ENA - Write 1 to enable I2C_SLAVE_STRETCH_INT interrupt. - 10 - 1 - read-write - - - TXFIFO_OVF_INT_ENA - Write 1 to enable I2C_TXFIFO_OVF_INT interrupt. - 11 - 1 - read-write - - - RXFIFO_UDF_INT_ENA - Write 1 to enable I2C_RXFIFO_UDF_INT interrupt. - 12 - 1 - read-write - - - SCL_ST_TO_INT_ENA - Write 1 to enable I2C_SCL_ST_TO_INT interrupt. - 13 - 1 - read-write - - - SCL_MAIN_ST_TO_INT_ENA - Write 1 to enable I2C_SCL_MAIN_ST_TO_INT interrupt. - 14 - 1 - read-write - - - DET_START_INT_ENA - Write 1 to enable I2C_DET_START_INT interrupt. - 15 - 1 - read-write - - - SLAVE_STRETCH_INT_ENA - Write 1 to enable I2C_SLAVE_STRETCH_INT interrupt. - 16 - 1 - read-write - - - GENERAL_CALL_INT_ENA - Write 1 to enable I2C_GENARAL_CALL_INT interrupt. - 17 - 1 - read-write - - - SLAVE_ADDR_UNMATCH_INT_ENA - Write 1 to enable I2C_SLAVE_ADDR_UNMATCH_INT interrupt. - 18 - 1 - read-write - - - - - INT_STATUS - Status of captured I2C communication events - 0x2C - 0x20 - - - RXFIFO_WM_INT_ST - The masked interrupt status status of I2C_RXFIFO_WM_INT interrupt. - 0 - 1 - read-only - - - TXFIFO_WM_INT_ST - The masked interrupt status status of I2C_TXFIFO_WM_INT interrupt. - 1 - 1 - read-only - - - RXFIFO_OVF_INT_ST - The masked interrupt status status of I2C_RXFIFO_OVF_INT interrupt. - 2 - 1 - read-only - - - END_DETECT_INT_ST - The masked interrupt status status of the I2C_END_DETECT_INT interrupt. - 3 - 1 - read-only - - - BYTE_TRANS_DONE_INT_ST - The masked interrupt status status of the I2C_END_DETECT_INT interrupt. - 4 - 1 - read-only - - - ARBITRATION_LOST_INT_ST - The masked interrupt status status of the I2C_ARBITRATION_LOST_INT interrupt. - 5 - 1 - read-only - - - MST_TXFIFO_UDF_INT_ST - The masked interrupt status status of I2C_TRANS_COMPLETE_INT interrupt. - 6 - 1 - read-only - - - TRANS_COMPLETE_INT_ST - The masked interrupt status status of the I2C_TRANS_COMPLETE_INT interrupt. - 7 - 1 - read-only - - - TIME_OUT_INT_ST - The masked interrupt status status of the I2C_TIME_OUT_INT interrupt. - 8 - 1 - read-only - - - TRANS_START_INT_ST - The masked interrupt status status of the I2C_TRANS_START_INT interrupt. - 9 - 1 - read-only - - - NACK_INT_ST - The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt. - 10 - 1 - read-only - - - TXFIFO_OVF_INT_ST - The masked interrupt status status of I2C_TXFIFO_OVF_INT interrupt. - 11 - 1 - read-only - - - RXFIFO_UDF_INT_ST - The masked interrupt status status of I2C_RXFIFO_UDF_INT interrupt. - 12 - 1 - read-only - - - SCL_ST_TO_INT_ST - The masked interrupt status status of I2C_SCL_ST_TO_INT interrupt. - 13 - 1 - read-only - - - SCL_MAIN_ST_TO_INT_ST - The masked interrupt status status of I2C_SCL_MAIN_ST_TO_INT interrupt. - 14 - 1 - read-only - - - DET_START_INT_ST - The masked interrupt status status of I2C_DET_START_INT interrupt. - 15 - 1 - read-only - - - SLAVE_STRETCH_INT_ST - The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt. - 16 - 1 - read-only - - - GENERAL_CALL_INT_ST - The masked interrupt status status of I2C_GENARAL_CALL_INT interrupt. - 17 - 1 - read-only - - - SLAVE_ADDR_UNMATCH_INT_ST - The masked interrupt status status of I2C_SLAVE_ADDR_UNMATCH_INT interrupt. - 18 - 1 - read-only - - - - - SDA_HOLD - Configures the hold time after a negative SCL edge. - 0x30 - 0x20 - - - TIME - Configures the time to hold the data after the falling edge of SCL. -Measurement unit: i2c_sclk - 0 - 9 - read-write - - - - - SDA_SAMPLE - Configures the sample time after a positive SCL edge. - 0x34 - 0x20 - - - TIME - Configures the sample time after a positive SCL edge. -Measurement unit: i2c_sclk - 0 - 9 - read-write - - - - - SCL_HIGH_PERIOD - Configures the high level width of SCL - 0x38 - 0x20 - - - SCL_HIGH_PERIOD - Configures for how long SCL remains high in master mode. -Measurement unit: i2c_sclk - 0 - 9 - read-write - - - SCL_WAIT_HIGH_PERIOD - Configures the SCL_FSM's waiting period for SCL high level in master mode. -Measurement unit: i2c_sclk - 9 - 7 - read-write - - - - - SCL_START_HOLD - Configures the delay between the SDA and SCL negative edge for a start condition - 0x40 - 0x20 - 0x00000008 - - - TIME - Configures the time between the falling edge of SDA and the falling edge of SCL for a START condition. -Measurement unit: i2c_sclk. - 0 - 9 - read-write - - - - - SCL_RSTART_SETUP - Configures the delay between the positive edge of SCL and the negative edge of SDA - 0x44 - 0x20 - 0x00000008 - - - TIME - Configures the time between the positive edge of SCL and the negative edge of SDA for a RESTART condition. -Measurement unit: i2c_sclk - 0 - 9 - read-write - - - - - SCL_STOP_HOLD - Configures the delay after the SCL clock edge for a stop condition - 0x48 - 0x20 - 0x00000008 - - - TIME - Configures the delay after the STOP condition. -Measurement unit: i2c_sclk - 0 - 9 - read-write - - - - - SCL_STOP_SETUP - Configures the delay between the SDA and SCL rising edge for a stop condition. -Measurement unit: i2c_sclk - 0x4C - 0x20 - 0x00000008 - - - TIME - Configures the time between the rising edge of SCL and the rising edge of SDA. -Measurement unit: i2c_sclk - 0 - 9 - read-write - - - - - FILTER_CFG - SCL and SDA filter configuration register - 0x50 - 0x20 - 0x00000300 - - - SCL_FILTER_THRES - Configures the threshold pulse width to be filtered on SCL. When a pulse on the SCL input has smaller width than this register value, the I2C controller will ignore that pulse. -Measurement unit: i2c_sclk - 0 - 4 - read-write - - - SDA_FILTER_THRES - Configures the threshold pulse width to be filtered on SDA. When a pulse on the SDA input has smaller width than this register value, the I2C controller will ignore that pulse. -Measurement unit: i2c_sclk - 4 - 4 - read-write - - - SCL_FILTER_EN - Configures to enable the filter function for SCL. - 8 - 1 - read-write - - - SDA_FILTER_EN - Configures to enable the filter function for SDA. - 9 - 1 - read-write - - - - - CLK_CONF - I2C CLK configuration register - 0x54 - 0x20 - 0x00200000 - - - SCLK_DIV_NUM - the integral part of the fractional divisor for i2c module - 0 - 8 - read-write - - - SCLK_DIV_A - the numerator of the fractional part of the fractional divisor for i2c module - 8 - 6 - read-write - - - SCLK_DIV_B - the denominator of the fractional part of the fractional divisor for i2c module - 14 - 6 - read-write - - - SCLK_SEL - The clock selection for i2c module:0-XTAL,1-CLK_8MHz. - 20 - 1 - read-write - - - SCLK_ACTIVE - The clock switch for i2c module - 21 - 1 - read-write - - - - - COMD0 - I2C command register 0 - 0x58 - 0x20 - - - COMMAND0 - Configures command 0. It consists of three parts: -op_code is the command, -0: RSTART, -1: WRITE, -2: READ, -3: STOP, -4: END. - -Byte_num represents the number of bytes that need to be sent or received. -ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more information. - 0 - 14 - read-write - - - COMMAND0_DONE - Represents whether command 0 is done in I2C Master mode. -0: Not done - -1: Done - 31 - 1 - read-write - - - - - COMD1 - I2C command register 1 - 0x5C - 0x20 - - - COMMAND1 - Configures command 1. See details in I2C_CMD0_REG[13:0]. - 0 - 14 - read-write - - - COMMAND1_DONE - Represents whether command 1 is done in I2C Master mode. -0: Not done - -1: Done - 31 - 1 - read-write - - - - - COMD2 - I2C command register 2 - 0x60 - 0x20 - - - COMMAND2 - Configures command 2. See details in I2C_CMD0_REG[13:0]. - 0 - 14 - read-write - - - COMMAND2_DONE - Represents whether command 2 is done in I2C Master mode. -0: Not done - -1: Done - 31 - 1 - read-write - - - - - COMD3 - I2C command register 3 - 0x64 - 0x20 - - - COMMAND3 - Configures command 3. See details in I2C_CMD0_REG[13:0]. - 0 - 14 - read-write - - - COMMAND3_DONE - Represents whether command 3 is done in I2C Master mode. -0: Not done - -1: Done - 31 - 1 - read-write - - - - - COMD4 - I2C command register 4 - 0x68 - 0x20 - - - COMMAND4 - Configures command 4. See details in I2C_CMD0_REG[13:0]. - 0 - 14 - read-write - - - COMMAND4_DONE - Represents whether command 4 is done in I2C Master mode. -0: Not done - -1: Done - 31 - 1 - read-write - - - - - COMD5 - I2C command register 5 - 0x6C - 0x20 - - - COMMAND5 - Configures command 5. See details in I2C_CMD0_REG[13:0]. - 0 - 14 - read-write - - - COMMAND5_DONE - Represents whether command 5 is done in I2C Master mode. -0: Not done - -1: Done - 31 - 1 - read-write - - - - - COMD6 - I2C command register 6 - 0x70 - 0x20 - - - COMMAND6 - Configures command 6. See details in I2C_CMD0_REG[13:0]. - 0 - 14 - read-write - - - COMMAND6_DONE - Represents whether command 6 is done in I2C Master mode. -0: Not done - -1: Done - 31 - 1 - read-write - - - - - COMD7 - I2C command register 7 - 0x74 - 0x20 - - - COMMAND7 - Configures command 7. See details in I2C_CMD0_REG[13:0]. - 0 - 14 - read-write - - - COMMAND7_DONE - Represents whether command 7 is done in I2C Master mode. -0: Not done - -1: Done - 31 - 1 - read-write - - - - - SCL_ST_TIME_OUT - SCL status time out register - 0x78 - 0x20 - 0x00000010 - - - SCL_ST_TO_I2C - Configures the threshold value of SCL_FSM state unchanged period. It should be no more than 23. -Measurement unit: i2c_sclk - 0 - 5 - read-write - - - - - SCL_MAIN_ST_TIME_OUT - SCL main status time out register - 0x7C - 0x20 - 0x00000010 - - - SCL_MAIN_ST_TO_I2C - Configures the threshold value of SCL_MAIN_FSM state unchanged period.nIt should be no more than 23. -Measurement unit: i2c_sclk - 0 - 5 - read-write - - - - - SCL_SP_CONF - Power configuration register - 0x80 - 0x20 - - - SCL_RST_SLV_EN - Configures to send out SCL pulses when I2C master is IDLE. The number of pulses equals to reg_scl_rst_slv_num[4:0]. - 0 - 1 - read-write - - - SCL_RST_SLV_NUM - Configure the pulses of SCL generated in I2C master mode. -Valid when reg_scl_rst_slv_en is 1. -Measurement unit: i2c_sclk - 1 - 5 - read-write - - - SCL_PD_EN - Configures to power down the I2C output SCL line. -0: Not power down. - -1: Power down. -Valid only when reg_scl_force_out is 1. - 6 - 1 - read-write - - - SDA_PD_EN - Configures to power down the I2C output SDA line. -0: Not power down. - -1: Power down. -Valid only when reg_sda_force_out is 1. - 7 - 1 - read-write - - - - - SCL_STRETCH_CONF - Set SCL stretch of I2C slave - 0x84 - 0x20 - - - STRETCH_PROTECT_NUM - Configures the time period to release the SCL line from stretching to avoid timing violation. Usually it should be larger than the SDA setup time. -Measurement unit: i2c_sclk - 0 - 10 - read-write - - - SLAVE_SCL_STRETCH_EN - Configures to enable slave SCL stretch function. -0: Disable - -1: Enable -The SCL output line will be stretched low when reg_slave_scl_stretch_en is 1 and stretch event happens. The stretch cause can be seen in reg_stretch_cause. - 10 - 1 - read-write - - - SLAVE_SCL_STRETCH_CLR - Configures to clear the I2C slave SCL stretch function. -0: No effect - -1: Clear - 11 - 1 - write-only - - - SLAVE_BYTE_ACK_CTL_EN - Configures to enable the function for slave to control ACK level. -0: Disable - -1: Enable - 12 - 1 - read-write - - - SLAVE_BYTE_ACK_LVL - Set the ACK level when slave controlling ACK level function enables. -0: Low level - -1: High level - 13 - 1 - read-write - - - - - DATE - Version register - 0xF8 - 0x20 - 0x02201172 - - - DATE - Version control register. - 0 - 32 - read-write - - - - - TXFIFO_START_ADDR - I2C TXFIFO base address register - 0x100 - 0x20 - - - TXFIFO_START_ADDR - Represents the I2C txfifo first address. - 0 - 32 - read-only - - - - - RXFIFO_START_ADDR - I2C RXFIFO base address register - 0x180 - 0x20 - - - RXFIFO_START_ADDR - Represents the I2C rxfifo first address. - 0 - 32 - read-only - - - - - - - I2C1 - I2C (Inter-Integrated Circuit) Controller 1 - 0x500C5000 - - I2C1 - 45 - - - - I2S0 - I2S (Inter-IC Sound) Controller 0 - I2S - 0x500C6000 - - 0x0 - 0x60 - registers - - - I2S0 - 27 - - - - INT_RAW - I2S interrupt raw register, valid in level. - 0xC - 0x20 - - - RX_DONE_INT_RAW - The raw interrupt status bit for the i2s_rx_done_int interrupt - 0 - 1 - read-only - - - TX_DONE_INT_RAW - The raw interrupt status bit for the i2s_tx_done_int interrupt - 1 - 1 - read-only - - - RX_HUNG_INT_RAW - The raw interrupt status bit for the i2s_rx_hung_int interrupt - 2 - 1 - read-only - - - TX_HUNG_INT_RAW - The raw interrupt status bit for the i2s_tx_hung_int interrupt - 3 - 1 - read-only - - - - - INT_ST - I2S interrupt status register. - 0x10 - 0x20 - - - RX_DONE_INT_ST - The masked interrupt status bit for the i2s_rx_done_int interrupt - 0 - 1 - read-only - - - TX_DONE_INT_ST - The masked interrupt status bit for the i2s_tx_done_int interrupt - 1 - 1 - read-only - - - RX_HUNG_INT_ST - The masked interrupt status bit for the i2s_rx_hung_int interrupt - 2 - 1 - read-only - - - TX_HUNG_INT_ST - The masked interrupt status bit for the i2s_tx_hung_int interrupt - 3 - 1 - read-only - - - - - INT_ENA - I2S interrupt enable register. - 0x14 - 0x20 - - - RX_DONE_INT_ENA - The interrupt enable bit for the i2s_rx_done_int interrupt - 0 - 1 - read-write - - - TX_DONE_INT_ENA - The interrupt enable bit for the i2s_tx_done_int interrupt - 1 - 1 - read-write - - - RX_HUNG_INT_ENA - The interrupt enable bit for the i2s_rx_hung_int interrupt - 2 - 1 - read-write - - - TX_HUNG_INT_ENA - The interrupt enable bit for the i2s_tx_hung_int interrupt - 3 - 1 - read-write - - - - - INT_CLR - I2S interrupt clear register. - 0x18 - 0x20 - - - RX_DONE_INT_CLR - Set this bit to clear the i2s_rx_done_int interrupt - 0 - 1 - write-only - - - TX_DONE_INT_CLR - Set this bit to clear the i2s_tx_done_int interrupt - 1 - 1 - write-only - - - RX_HUNG_INT_CLR - Set this bit to clear the i2s_rx_hung_int interrupt - 2 - 1 - write-only - - - TX_HUNG_INT_CLR - Set this bit to clear the i2s_tx_hung_int interrupt - 3 - 1 - write-only - - - - - RX_CONF - I2S RX configure register - 0x20 - 0x20 - 0x00C0B600 - - - RX_RESET - Set this bit to reset receiver - 0 - 1 - write-only - - - RX_FIFO_RESET - Set this bit to reset Rx AFIFO - 1 - 1 - write-only - - - RX_START - Set this bit to start receiving data - 2 - 1 - read-write - - - RX_SLAVE_MOD - Set this bit to enable slave receiver mode - 3 - 1 - read-write - - - RX_STOP_MODE - 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full. - 4 - 2 - read-write - - - RX_MONO - Set this bit to enable receiver in mono mode - 6 - 1 - read-write - - - RX_BIG_ENDIAN - I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value. - 7 - 1 - read-write - - - RX_UPDATE - Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done. - 8 - 1 - read-write - - - RX_MONO_FST_VLD - 1: The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is valid in I2S RX mono mode. - 9 - 1 - read-write - - - RX_PCM_CONF - I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & - 10 - 2 - read-write - - - RX_PCM_BYPASS - Set this bit to bypass Compress/Decompress module for received data. - 12 - 1 - read-write - - - RX_MSB_SHIFT - Set this bit to enable receiver in Phillips standard mode - 13 - 1 - read-write - - - RX_LEFT_ALIGN - 1: I2S RX left alignment mode. 0: I2S RX right alignment mode. - 15 - 1 - read-write - - - RX_24_FILL_EN - 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits. - 16 - 1 - read-write - - - RX_WS_IDLE_POL - 0: WS should be 0 when receiving left channel data, and WS is 1in right channel. 1: WS should be 1 when receiving left channel data, and WS is 0in right channel. - 17 - 1 - read-write - - - RX_BIT_ORDER - I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first. - 18 - 1 - read-write - - - RX_TDM_EN - 1: Enable I2S TDM Rx mode . 0: Disable. - 19 - 1 - read-write - - - RX_PDM_EN - 1: Enable I2S PDM Rx mode . 0: Disable. - 20 - 1 - read-write - - - RX_BCK_DIV_NUM - Bit clock configuration bits in receiver mode. - 21 - 6 - read-write - - - - - TX_CONF - I2S TX configure register - 0x24 - 0x20 - 0x00C0F210 - - - TX_RESET - Set this bit to reset transmitter - 0 - 1 - write-only - - - TX_FIFO_RESET - Set this bit to reset Tx AFIFO - 1 - 1 - write-only - - - TX_START - Set this bit to start transmitting data - 2 - 1 - read-write - - - TX_SLAVE_MOD - Set this bit to enable slave transmitter mode - 3 - 1 - read-write - - - TX_STOP_EN - Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy - 4 - 1 - read-write - - - TX_CHAN_EQUAL - 1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode. - 5 - 1 - read-write - - - TX_MONO - Set this bit to enable transmitter in mono mode - 6 - 1 - read-write - - - TX_BIG_ENDIAN - I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr value. - 7 - 1 - read-write - - - TX_UPDATE - Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done. - 8 - 1 - read-write - - - TX_MONO_FST_VLD - 1: The first channel data value is valid in I2S TX mono mode. 0: The second channel data value is valid in I2S TX mono mode. - 9 - 1 - read-write - - - TX_PCM_CONF - I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & - 10 - 2 - read-write - - - TX_PCM_BYPASS - Set this bit to bypass Compress/Decompress module for transmitted data. - 12 - 1 - read-write - - - TX_MSB_SHIFT - Set this bit to enable transmitter in Phillips standard mode - 13 - 1 - read-write - - - TX_BCK_NO_DLY - 1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to generate pos/neg edge in master mode. - 14 - 1 - read-write - - - TX_LEFT_ALIGN - 1: I2S TX left alignment mode. 0: I2S TX right alignment mode. - 15 - 1 - read-write - - - TX_24_FILL_EN - 1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode - 16 - 1 - read-write - - - TX_WS_IDLE_POL - 0: WS should be 0 when sending left channel data, and WS is 1in right channel. 1: WS should be 1 when sending left channel data, and WS is 0in right channel. - 17 - 1 - read-write - - - TX_BIT_ORDER - I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is sent first. - 18 - 1 - read-write - - - TX_TDM_EN - 1: Enable I2S TDM Tx mode . 0: Disable. - 19 - 1 - read-write - - - TX_PDM_EN - 1: Enable I2S PDM Tx mode . 0: Disable. - 20 - 1 - read-write - - - TX_BCK_DIV_NUM - Bit clock configuration bits in transmitter mode. - 21 - 6 - read-write - - - TX_CHAN_MOD - I2S transmitter channel mode configuration bits. - 27 - 3 - read-write - - - SIG_LOOPBACK - Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals. - 30 - 1 - read-write - - - - - RX_CONF1 - I2S RX configure register 1 - 0x28 - 0x20 - 0x787BC000 - - - RX_TDM_WS_WIDTH - The width of rx_ws_out at idle level in TDM mode is (I2S_RX_TDM_WS_WIDTH[8:0] +1) * T_bck - 0 - 9 - read-write - - - RX_BITS_MOD - Set the bits to configure the valid data bit length of I2S receiver channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode. - 14 - 5 - read-write - - - RX_HALF_SAMPLE_BITS - I2S Rx half sample bits -1. - 19 - 8 - read-write - - - RX_TDM_CHAN_BITS - The Rx bit number for each channel minus 1in TDM mode. - 27 - 5 - read-write - - - - - TX_CONF1 - I2S TX configure register 1 - 0x2C - 0x20 - 0x787BC000 - - - TX_TDM_WS_WIDTH - The width of tx_ws_out at idle level in TDM mode is (I2S_TX_TDM_WS_WIDTH[8:0] +1) * T_bck - 0 - 9 - read-write - - - TX_BITS_MOD - Set the bits to configure the valid data bit length of I2S transmitter channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode. - 14 - 5 - read-write - - - TX_HALF_SAMPLE_BITS - I2S Tx half sample bits -1. - 19 - 8 - read-write - - - TX_TDM_CHAN_BITS - The Tx bit number for each channel minus 1in TDM mode. - 27 - 5 - read-write - - - - - TX_PCM2PDM_CONF - I2S TX PCM2PDM configuration register - 0x40 - 0x20 - 0x004AA004 - - - TX_PDM_HP_BYPASS - I2S TX PDM bypass hp filter or not. The option has been removed. - 0 - 1 - read-write - - - TX_PDM_SINC_OSR2 - I2S TX PDM OSR2 value - 1 - 4 - read-write - - - TX_PDM_PRESCALE - I2S TX PDM prescale for sigmadelta - 5 - 8 - read-write - - - TX_PDM_HP_IN_SHIFT - I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 - 13 - 2 - read-write - - - TX_PDM_LP_IN_SHIFT - I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 - 15 - 2 - read-write - - - TX_PDM_SINC_IN_SHIFT - I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 - 17 - 2 - read-write - - - TX_PDM_SIGMADELTA_IN_SHIFT - I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 - 19 - 2 - read-write - - - TX_PDM_SIGMADELTA_DITHER2 - I2S TX PDM sigmadelta dither2 value - 21 - 1 - read-write - - - TX_PDM_SIGMADELTA_DITHER - I2S TX PDM sigmadelta dither value - 22 - 1 - read-write - - - TX_PDM_DAC_2OUT_EN - I2S TX PDM dac mode enable - 23 - 1 - read-write - - - TX_PDM_DAC_MODE_EN - I2S TX PDM dac 2channel enable - 24 - 1 - read-write - - - PCM2PDM_CONV_EN - I2S TX PDM Converter enable - 25 - 1 - read-write - - - - - TX_PCM2PDM_CONF1 - I2S TX PCM2PDM configuration register - 0x44 - 0x20 - 0x03F783C0 - - - TX_PDM_FP - I2S TX PDM Fp - 0 - 10 - read-write - - - TX_PDM_FS - I2S TX PDM Fs - 10 - 10 - read-write - - - TX_IIR_HP_MULT12_5 - The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + I2S_TX_IIR_HP_MULT12_5[2:0]) - 20 - 3 - read-write - - - TX_IIR_HP_MULT12_0 - The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + I2S_TX_IIR_HP_MULT12_0[2:0]) - 23 - 3 - read-write - - - - - RX_PDM2PCM_CONF - I2S RX configure register - 0x48 - 0x20 - 0xF8200000 - - - RX_PDM2PCM_EN - 1: Enable PDM2PCM RX mode. 0: DIsable. - 19 - 1 - read-write - - - RX_PDM_SINC_DSR_16_EN - Configure the down sampling rate of PDM RX filter group1 module. 1: The down sampling rate is 128. 0: down sampling rate is 64. - 20 - 1 - read-write - - - RX_PDM2PCM_AMPLIFY_NUM - Configure PDM RX amplify number. - 21 - 4 - read-write - - - RX_PDM_HP_BYPASS - I2S PDM RX bypass hp filter or not. - 25 - 1 - read-write - - - RX_IIR_HP_MULT12_5 - The fourth parameter of PDM RX IIR_HP filter stage 2 is (504 + LP_I2S_RX_IIR_HP_MULT12_5[2:0]) - 26 - 3 - read-write - - - RX_IIR_HP_MULT12_0 - The fourth parameter of PDM RX IIR_HP filter stage 1 is (504 + LP_I2S_RX_IIR_HP_MULT12_0[2:0]) - 29 - 3 - read-write - - - - - RX_TDM_CTRL - I2S TX TDM mode control register - 0x50 - 0x20 - 0x0000FFFF - - - RX_TDM_PDM_CHAN0_EN - 1: Enable the valid data input of I2S RX TDM or PDM channel 0. 0: Disable, just input 0 in this channel. - 0 - 1 - read-write - - - RX_TDM_PDM_CHAN1_EN - 1: Enable the valid data input of I2S RX TDM or PDM channel 1. 0: Disable, just input 0 in this channel. - 1 - 1 - read-write - - - RX_TDM_PDM_CHAN2_EN - 1: Enable the valid data input of I2S RX TDM or PDM channel 2. 0: Disable, just input 0 in this channel. - 2 - 1 - read-write - - - RX_TDM_PDM_CHAN3_EN - 1: Enable the valid data input of I2S RX TDM or PDM channel 3. 0: Disable, just input 0 in this channel. - 3 - 1 - read-write - - - RX_TDM_PDM_CHAN4_EN - 1: Enable the valid data input of I2S RX TDM or PDM channel 4. 0: Disable, just input 0 in this channel. - 4 - 1 - read-write - - - RX_TDM_PDM_CHAN5_EN - 1: Enable the valid data input of I2S RX TDM or PDM channel 5. 0: Disable, just input 0 in this channel. - 5 - 1 - read-write - - - RX_TDM_PDM_CHAN6_EN - 1: Enable the valid data input of I2S RX TDM or PDM channel 6. 0: Disable, just input 0 in this channel. - 6 - 1 - read-write - - - RX_TDM_PDM_CHAN7_EN - 1: Enable the valid data input of I2S RX TDM or PDM channel 7. 0: Disable, just input 0 in this channel. - 7 - 1 - read-write - - - RX_TDM_CHAN8_EN - 1: Enable the valid data input of I2S RX TDM channel 8. 0: Disable, just input 0 in this channel. - 8 - 1 - read-write - - - RX_TDM_CHAN9_EN - 1: Enable the valid data input of I2S RX TDM channel 9. 0: Disable, just input 0 in this channel. - 9 - 1 - read-write - - - RX_TDM_CHAN10_EN - 1: Enable the valid data input of I2S RX TDM channel 10. 0: Disable, just input 0 in this channel. - 10 - 1 - read-write - - - RX_TDM_CHAN11_EN - 1: Enable the valid data input of I2S RX TDM channel 11. 0: Disable, just input 0 in this channel. - 11 - 1 - read-write - - - RX_TDM_CHAN12_EN - 1: Enable the valid data input of I2S RX TDM channel 12. 0: Disable, just input 0 in this channel. - 12 - 1 - read-write - - - RX_TDM_CHAN13_EN - 1: Enable the valid data input of I2S RX TDM channel 13. 0: Disable, just input 0 in this channel. - 13 - 1 - read-write - - - RX_TDM_CHAN14_EN - 1: Enable the valid data input of I2S RX TDM channel 14. 0: Disable, just input 0 in this channel. - 14 - 1 - read-write - - - RX_TDM_CHAN15_EN - 1: Enable the valid data input of I2S RX TDM channel 15. 0: Disable, just input 0 in this channel. - 15 - 1 - read-write - - - RX_TDM_TOT_CHAN_NUM - The total channel number of I2S TX TDM mode. - 16 - 4 - read-write - - - - - TX_TDM_CTRL - I2S TX TDM mode control register - 0x54 - 0x20 - 0x0000FFFF - - - TX_TDM_CHAN0_EN - 1: Enable the valid data output of I2S TX TDM channel 0. 0: Disable, just output 0 in this channel. - 0 - 1 - read-write - - - TX_TDM_CHAN1_EN - 1: Enable the valid data output of I2S TX TDM channel 1. 0: Disable, just output 0 in this channel. - 1 - 1 - read-write - - - TX_TDM_CHAN2_EN - 1: Enable the valid data output of I2S TX TDM channel 2. 0: Disable, just output 0 in this channel. - 2 - 1 - read-write - - - TX_TDM_CHAN3_EN - 1: Enable the valid data output of I2S TX TDM channel 3. 0: Disable, just output 0 in this channel. - 3 - 1 - read-write - - - TX_TDM_CHAN4_EN - 1: Enable the valid data output of I2S TX TDM channel 4. 0: Disable, just output 0 in this channel. - 4 - 1 - read-write - - - TX_TDM_CHAN5_EN - 1: Enable the valid data output of I2S TX TDM channel 5. 0: Disable, just output 0 in this channel. - 5 - 1 - read-write - - - TX_TDM_CHAN6_EN - 1: Enable the valid data output of I2S TX TDM channel 6. 0: Disable, just output 0 in this channel. - 6 - 1 - read-write - - - TX_TDM_CHAN7_EN - 1: Enable the valid data output of I2S TX TDM channel 7. 0: Disable, just output 0 in this channel. - 7 - 1 - read-write - - - TX_TDM_CHAN8_EN - 1: Enable the valid data output of I2S TX TDM channel 8. 0: Disable, just output 0 in this channel. - 8 - 1 - read-write - - - TX_TDM_CHAN9_EN - 1: Enable the valid data output of I2S TX TDM channel 9. 0: Disable, just output 0 in this channel. - 9 - 1 - read-write - - - TX_TDM_CHAN10_EN - 1: Enable the valid data output of I2S TX TDM channel 10. 0: Disable, just output 0 in this channel. - 10 - 1 - read-write - - - TX_TDM_CHAN11_EN - 1: Enable the valid data output of I2S TX TDM channel 11. 0: Disable, just output 0 in this channel. - 11 - 1 - read-write - - - TX_TDM_CHAN12_EN - 1: Enable the valid data output of I2S TX TDM channel 12. 0: Disable, just output 0 in this channel. - 12 - 1 - read-write - - - TX_TDM_CHAN13_EN - 1: Enable the valid data output of I2S TX TDM channel 13. 0: Disable, just output 0 in this channel. - 13 - 1 - read-write - - - TX_TDM_CHAN14_EN - 1: Enable the valid data output of I2S TX TDM channel 14. 0: Disable, just output 0 in this channel. - 14 - 1 - read-write - - - TX_TDM_CHAN15_EN - 1: Enable the valid data output of I2S TX TDM channel 15. 0: Disable, just output 0 in this channel. - 15 - 1 - read-write - - - TX_TDM_TOT_CHAN_NUM - The total channel number of I2S TX TDM mode. - 16 - 4 - read-write - - - TX_TDM_SKIP_MSK_EN - When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels, and only the data of the enabled channels is sent, then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels. - 20 - 1 - read-write - - - - - RX_TIMING - I2S RX timing control register - 0x58 - 0x20 - - - RX_SD_IN_DM - The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. - 0 - 2 - read-write - - - RX_SD1_IN_DM - The delay mode of I2S Rx SD1 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. - 4 - 2 - read-write - - - RX_SD2_IN_DM - The delay mode of I2S Rx SD2 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. - 8 - 2 - read-write - - - RX_SD3_IN_DM - The delay mode of I2S Rx SD3 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. - 12 - 2 - read-write - - - RX_WS_OUT_DM - The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. - 16 - 2 - read-write - - - RX_BCK_OUT_DM - The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. - 20 - 2 - read-write - - - RX_WS_IN_DM - The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. - 24 - 2 - read-write - - - RX_BCK_IN_DM - The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. - 28 - 2 - read-write - - - - - TX_TIMING - I2S TX timing control register - 0x5C - 0x20 - - - TX_SD_OUT_DM - The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. - 0 - 2 - read-write - - - TX_SD1_OUT_DM - The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. - 4 - 2 - read-write - - - TX_WS_OUT_DM - The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. - 16 - 2 - read-write - - - TX_BCK_OUT_DM - The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. - 20 - 2 - read-write - - - TX_WS_IN_DM - The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. - 24 - 2 - read-write - - - TX_BCK_IN_DM - The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. - 28 - 2 - read-write - - - - - LC_HUNG_CONF - I2S HUNG configure register. - 0x60 - 0x20 - 0x00000810 - - - LC_FIFO_TIMEOUT - the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value - 0 - 8 - read-write - - - LC_FIFO_TIMEOUT_SHIFT - The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift - 8 - 3 - read-write - - - LC_FIFO_TIMEOUT_ENA - The enable bit for FIFO timeout - 11 - 1 - read-write - - - - - RXEOF_NUM - I2S RX data number control register. - 0x64 - 0x20 - 0x00000040 - - - RX_EOF_NUM - The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel. - 0 - 12 - read-write - - - - - CONF_SIGLE_DATA - I2S signal data register - 0x68 - 0x20 - - - SINGLE_DATA - The configured constant channel data to be sent out. - 0 - 32 - read-write - - - - - STATE - I2S TX status register - 0x6C - 0x20 - 0x00000001 - - - TX_IDLE - 1: i2s_tx is idle state. 0: i2s_tx is working. - 0 - 1 - read-only - - - - - ETM_CONF - I2S ETM configure register - 0x70 - 0x20 - 0x00010040 - - - ETM_TX_SEND_WORD_NUM - I2S ETM send x words event. When sending word number of reg_etm_tx_send_word_num[9:0], i2s will trigger an etm event. - 0 - 10 - read-write - - - ETM_RX_RECEIVE_WORD_NUM - I2S ETM receive x words event. When receiving word number of reg_etm_rx_receive_word_num[9:0], i2s will trigger an etm event. - 10 - 10 - read-write - - - - - FIFO_CNT - I2S sync counter register - 0x74 - 0x20 - - - TX_FIFO_CNT - tx fifo counter value. - 0 - 31 - read-only - - - TX_FIFO_CNT_RST - Set this bit to reset tx fifo counter. - 31 - 1 - write-only - - - - - BCK_CNT - I2S sync counter register - 0x78 - 0x20 - - - TX_BCK_CNT - tx bck counter value. - 0 - 31 - read-only - - - TX_BCK_CNT_RST - Set this bit to reset tx bck counter. - 31 - 1 - write-only - - - - - CLK_GATE - Clock gate register - 0x7C - 0x20 - - - CLK_EN - set this bit to enable clock gate - 0 - 1 - read-write - - - - - DATE - Version control register - 0x80 - 0x20 - 0x02303240 - - - DATE - I2S version control register - 0 - 28 - read-write - - - - - - - I2S1 - I2S (Inter-IC Sound) Controller 1 - 0x500C7000 - - I2S1 - 28 - - - - I2S2 - I2S (Inter-IC Sound) Controller 2 - 0x500C8000 - - I2S2 - 29 - - - - I3C_MST - I3C Controller (Master) - I3C_MST - 0x500DA000 - - 0x0 - 0x90 - registers - - - I3C - 101 - - - - DEVICE_CTRL - DEVICE_CTRL register controls the transfer properties and disposition of controllers capabilities. - 0x0 - 0x20 - 0x00001020 - - - REG_BA_INCLUDE - This bit is used to include I3C broadcast address(0x7E) for private transfer.(If I3C broadcast address is not include for the private transfer, In-Band Interrupts driven from Slaves may not win address arbitration. Hence IBIs will get delayed) - 1 - 1 - read-write - - - REG_TRANS_START - Transfer Start - 2 - 1 - read-write - - - REG_CLK_EN - NA - 3 - 1 - read-write - - - REG_IBI_RSTART_TRANS_EN - NA - 4 - 1 - read-write - - - REG_AUTO_DIS_IBI_EN - NA - 5 - 1 - read-write - - - REG_DMA_RX_EN - NA - 6 - 1 - read-write - - - REG_DMA_TX_EN - NA - 7 - 1 - read-write - - - REG_MULTI_SLV_SINGLE_CCC_EN - 0: rx high bit first, 1: rx low bit first - 8 - 1 - read-write - - - REG_RX_BIT_ORDER - 0: rx low byte fist, 1: rx high byte first - 9 - 1 - read-write - - - REG_RX_BYTE_ORDER - NA - 10 - 1 - read-write - - - REG_SCL_PULLUP_FORCE_EN - This bit is used to force scl_pullup_en - 11 - 1 - read-write - - - REG_SCL_OE_FORCE_EN - This bit is used to force scl_oe - 12 - 1 - read-write - - - REG_SDA_PP_RD_PULLUP_EN - NA - 13 - 1 - read-write - - - REG_SDA_RD_TBIT_HLVL_PULLUP_EN - NA - 14 - 1 - read-write - - - REG_SDA_PP_WR_PULLUP_EN - NA - 15 - 1 - read-write - - - REG_DATA_BYTE_CNT_UNLATCH - 1: read current real-time updated value 0: read latch data byte cnt value - 16 - 1 - read-write - - - REG_MEM_CLK_FORCE_ON - 1: dev characteristic and address table memory clk date force on . 0 : clock gating by rd/wr. - 17 - 1 - read-write - - - - - BUFFER_THLD_CTRL - In-Band Interrupt Status Threshold Value . Every In Band Interrupt received by I3C controller generates an IBI status. This field controls the number of IBI status entries in the IBI buffer that trigger the IBI_STATUS_THLD_STAT interrupt. - 0x1C - 0x20 - 0x00041041 - - - REG_CMD_BUF_EMPTY_THLD - Command Buffer Empty Threshold Value is used to control the number of empty locations(or greater) in the Command Buffer that trigger CMD_BUFFER_READY_STAT interrupt. - 0 - 4 - read-write - - - REG_RESP_BUF_THLD - Response Buffer Threshold Value is used to control the number of entries in the Response Buffer that trigger the RESP_READY_STAT_INTR. - 6 - 3 - read-write - - - REG_IBI_DATA_BUF_THLD - In-Band Interrupt Data Threshold Value . Every In Band Interrupt received by I3C controller generates an IBI status. This field controls the number of IBI data entries in the IBI buffer that trigger the IBI_DATA_THLD_STAT interrupt. - 12 - 3 - read-write - - - REG_IBI_STATUS_BUF_THLD - NA - 18 - 3 - read-write - - - - - DATA_BUFFER_THLD_CTRL - NA - 0x20 - 0x20 - 0x00000009 - - - REG_TX_DATA_BUF_THLD - Transmit Buffer Threshold Value. This field controls the number of empty locations in the Transmit FIFO that trigger the TX_THLD_STAT interrupt. Supports values: 000:2 001:4 010:8 011:16 100:31, else:31 - 0 - 3 - read-write - - - REG_RX_DATA_BUF_THLD - Receive Buffer Threshold Value. This field controls the number of empty locations in the Receive FIFO that trigger the RX_THLD_STAT interrupt. Supports: 000:2 001:4 010:8 011:16 100:31, else:31 - 3 - 3 - read-write - - - - - IBI_NOTIFY_CTRL - NA - 0x24 - 0x20 - - - REG_NOTIFY_SIR_REJECTED - Notify Rejected Slave Interrupt Request Control. This bit is used to suppress reporting to the application about Slave Interrupt Request. 0:Suppress passing the IBI Status to the IBI FIFO(hence not notifying the application) when a SIR request is NACKed and auto-disabled base on the IBI_SIR_REQ_REJECT register. 1: Writes IBI Status to the IBI FIFO(hence notifying the application) when SIR request is NACKed and auto-disabled based on the IBI_SIR_REQ_REJECT registerl. - 2 - 1 - read-write - - - - - IBI_SIR_REQ_PAYLOAD - NA - 0x28 - 0x20 - - - REG_SIR_REQ_PAYLOAD - NA - 0 - 32 - read-write - - - - - IBI_SIR_REQ_REJECT - NA - 0x2C - 0x20 - - - REG_SIR_REQ_REJECT - The application of controller can decide whether to send ACK or NACK for Slave request received from any I3C device. A device specific response control bit is provided to select the response option, Master will ACK/NACK the Master Request based on programming of control bit, corresponding to the interrupting device. 0:ACK the SIR Request 1:NACK and send direct auto disable CCC - 0 - 32 - read-write - - - - - INT_CLR - NA - 0x30 - 0x20 - - - TX_DATA_BUF_THLD_INT_CLR - NA - 0 - 1 - write-only - - - RX_DATA_BUF_THLD_INT_CLR - NA - 1 - 1 - write-only - - - IBI_STATUS_THLD_INT_CLR - NA - 2 - 1 - write-only - - - CMD_BUF_EMPTY_THLD_INT_CLR - NA - 3 - 1 - write-only - - - RESP_READY_INT_CLR - NA - 4 - 1 - write-only - - - NXT_CMD_REQ_ERR_INT_CLR - NA - 5 - 1 - write-only - - - TRANSFER_ERR_INT_CLR - NA - 6 - 1 - write-only - - - TRANSFER_COMPLETE_INT_CLR - NA - 7 - 1 - write-only - - - COMMAND_DONE_INT_CLR - NA - 8 - 1 - write-only - - - DETECT_START_INT_CLR - NA - 9 - 1 - write-only - - - RESP_BUF_OVF_INT_CLR - NA - 10 - 1 - write-only - - - IBI_DATA_BUF_OVF_INT_CLR - NA - 11 - 1 - write-only - - - IBI_STATUS_BUF_OVF_INT_CLR - NA - 12 - 1 - write-only - - - IBI_HANDLE_DONE_INT_CLR - NA - 13 - 1 - write-only - - - IBI_DETECT_INT_CLR - NA - 14 - 1 - write-only - - - CMD_CCC_MISMATCH_INT_CLR - NA - 15 - 1 - write-only - - - - - INT_RAW - NA - 0x34 - 0x20 - 0x00000008 - - - TX_DATA_BUF_THLD_INT_RAW - NA - 0 - 1 - read-write - - - RX_DATA_BUF_THLD_INT_RAW - NA - 1 - 1 - read-write - - - IBI_STATUS_THLD_INT_RAW - NA - 2 - 1 - read-write - - - CMD_BUF_EMPTY_THLD_INT_RAW - NA - 3 - 1 - read-write - - - RESP_READY_INT_RAW - NA - 4 - 1 - read-write - - - NXT_CMD_REQ_ERR_INT_RAW - NA - 5 - 1 - read-write - - - TRANSFER_ERR_INT_RAW - NA - 6 - 1 - read-write - - - TRANSFER_COMPLETE_INT_RAW - NA - 7 - 1 - read-write - - - COMMAND_DONE_INT_RAW - NA - 8 - 1 - read-write - - - DETECT_START_INT_RAW - NA - 9 - 1 - read-write - - - RESP_BUF_OVF_INT_RAW - NA - 10 - 1 - read-write - - - IBI_DATA_BUF_OVF_INT_RAW - NA - 11 - 1 - read-write - - - IBI_STATUS_BUF_OVF_INT_RAW - NA - 12 - 1 - read-write - - - IBI_HANDLE_DONE_INT_RAW - NA - 13 - 1 - read-write - - - IBI_DETECT_INT_RAW - NA - 14 - 1 - read-write - - - CMD_CCC_MISMATCH_INT_RAW - NA - 15 - 1 - read-write - - - - - INT_ST - NA - 0x38 - 0x20 - - - TX_DATA_BUF_THLD_INT_ST - This interrupt is generated when number of empty locations in transmit buffer is greater than or equal to threshold value specified by TX_EMPTY_BUS_THLD field in DATA_BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of empty locations in transmit buffer is less than threshold value. - 0 - 1 - read-only - - - RX_DATA_BUF_THLD_INT_ST - This interrupt is generated when number of entries in receive buffer is greater than or equal to threshold value specified by RX_BUF_THLD field in DATA_BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of entries in receive buffer is less than threshold value. - 1 - 1 - read-only - - - IBI_STATUS_THLD_INT_ST - Only used in master mode. This interrupt is generated when number of entries in IBI buffer is greater than or equal to threshold value specified by IBI_BUF_THLD field in BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of entries in IBI buffer is less than threshold value. - 2 - 1 - read-only - - - CMD_BUF_EMPTY_THLD_INT_ST - This interrupt is generated when number of empty locations in command buffer is greater than or equal to threshold value specified by CMD_EMPTY_BUF_THLD field in BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of empty locations in command buffer is less than threshold value. - 3 - 1 - read-only - - - RESP_READY_INT_ST - This interrupt is generated when number of entries in response buffer is greater than or equal to threshold value specified by RESP_BUF_THLD field in BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of entries in response buffer is less than threshold value. - 4 - 1 - read-only - - - NXT_CMD_REQ_ERR_INT_ST - This interrupt is generated if toc is 0(master will restart next command), but command buf is empty. - 5 - 1 - read-only - - - TRANSFER_ERR_INT_ST - This interrupt is generated if any error occurs during transfer. The error type will be specified in the response packet associated with the command (in ERR_STATUS field of RESPONSE_BUFFER_PORT register). This bit can be cleared by writing 1'h1. - 6 - 1 - read-only - - - TRANSFER_COMPLETE_INT_ST - NA - 7 - 1 - read-only - - - COMMAND_DONE_INT_ST - NA - 8 - 1 - read-only - - - DETECT_START_INT_ST - NA - 9 - 1 - read-only - - - RESP_BUF_OVF_INT_ST - NA - 10 - 1 - read-only - - - IBI_DATA_BUF_OVF_INT_ST - NA - 11 - 1 - read-only - - - IBI_STATUS_BUF_OVF_INT_ST - NA - 12 - 1 - read-only - - - IBI_HANDLE_DONE_INT_ST - NA - 13 - 1 - read-only - - - IBI_DETECT_INT_ST - NA - 14 - 1 - read-only - - - CMD_CCC_MISMATCH_INT_ST - NA - 15 - 1 - read-only - - - - - INT_ST_ENA - The Interrupt status will be updated in INTR_STATUS register if corresponding Status Enable bit set. - 0x3C - 0x20 - - - TX_DATA_BUF_THLD_INT_ENA - Transmit Buffer threshold status enable. - 0 - 1 - read-write - - - RX_DATA_BUF_THLD_INT_ENA - Receive Buffer threshold status enable. - 1 - 1 - read-write - - - IBI_STATUS_THLD_INT_ENA - Only used in master mode. IBI Buffer threshold status enable. - 2 - 1 - read-write - - - CMD_BUF_EMPTY_THLD_INT_ENA - Command buffer ready status enable. - 3 - 1 - read-write - - - RESP_READY_INT_ENA - Response buffer ready status enable. - 4 - 1 - read-write - - - NXT_CMD_REQ_ERR_INT_ENA - next command request error status enable - 5 - 1 - read-write - - - TRANSFER_ERR_INT_ENA - Transfer error status enable - 6 - 1 - read-write - - - TRANSFER_COMPLETE_INT_ENA - NA - 7 - 1 - read-write - - - COMMAND_DONE_INT_ENA - NA - 8 - 1 - read-write - - - DETECT_START_INT_ENA - NA - 9 - 1 - read-write - - - RESP_BUF_OVF_INT_ENA - NA - 10 - 1 - read-write - - - IBI_DATA_BUF_OVF_INT_ENA - NA - 11 - 1 - read-write - - - IBI_STATUS_BUF_OVF_INT_ENA - NA - 12 - 1 - read-write - - - IBI_HANDLE_DONE_INT_ENA - NA - 13 - 1 - read-write - - - IBI_DETECT_INT_ENA - NA - 14 - 1 - read-write - - - CMD_CCC_MISMATCH_INT_ENA - NA - 15 - 1 - read-write - - - - - RESET_CTRL - NA - 0x44 - 0x20 - - - REG_CORE_SOFT_RST - NA - 0 - 1 - write-only - - - REG_CMD_BUF_RST - NA - 1 - 1 - read-write - - - REG_RESP_BUF_RST - NA - 2 - 1 - read-write - - - REG_TX_DATA_BUF_BUF_RST - NA - 3 - 1 - read-write - - - REG_RX_DATA_BUF_RST - NA - 4 - 1 - read-write - - - REG_IBI_DATA_BUF_RST - NA - 5 - 1 - read-write - - - REG_IBI_STATUS_BUF_RST - NA - 6 - 1 - read-write - - - - - BUFFER_STATUS_LEVEL - BUFFER_STATUS_LEVEL reflects the status level of Buffers in the controller. - 0x48 - 0x20 - 0x00000010 - - - CMD_BUF_EMPTY_CNT - Command Buffer Empty Locations contains the number of empty locations in the command buffer. - 0 - 5 - read-only - - - RESP_BUF_CNT - Response Buffer Level Value contains the number of valid data entries in the response buffer. - 8 - 4 - read-only - - - IBI_DATA_BUF_CNT - IBI Buffer Level Value contains the number of valid entries in the IBI Buffer. This is field is used in master mode. - 16 - 4 - read-only - - - IBI_STATUS_BUF_CNT - IBI Buffer Status Count contains the number of IBI status entries in the IBI Buffer. This field is used in master mode. - 24 - 4 - read-only - - - - - DATA_BUFFER_STATUS_LEVEL - DATA_BUFFER_STATUS_LEVEL reflects the status level of the Buffers in the controller. - 0x4C - 0x20 - 0x00000020 - - - TX_DATA_BUF_EMPTY_CNT - Transmit Buffer Empty Level Value contains the number of empty locations in the transmit Buffer. - 0 - 6 - read-only - - - RX_DATA_BUF_CNT - Receive Buffer Level value contains the number of valid data entries in the receive buffer. - 16 - 6 - read-only - - - - - PRESENT_STATE0 - NA - 0x50 - 0x20 - 0x00000003 - - - SDA_LVL - This bit is used to check the SCL line level to recover from error and for debugging. This bit reflects the value of synchronized scl_in_a. - 0 - 1 - read-only - - - SCL_LVL - This bit is used to check the SDA line level to recover from error and for debugging. This bit reflects the value of synchronized sda_in_a. - 1 - 1 - read-only - - - BUS_BUSY - NA - 2 - 1 - read-only - - - BUS_FREE - NA - 3 - 1 - read-only - - - CMD_TID - NA - 9 - 4 - read-only - - - SCL_GEN_FSM_STATE - NA - 13 - 3 - read-only - - - IBI_EV_HANDLE_FSM_STATE - NA - 16 - 3 - read-only - - - I2C_MODE_FSM_STATE - NA - 19 - 3 - read-only - - - SDR_MODE_FSM_STATE - NA - 22 - 4 - read-only - - - DAA_MODE_FSM_STATE - Reflects whether the Master Controller is in IDLE or not. This bit will be set when all the buffer(Command, Response, IBI, Transmit, Receive) are empty along with the Master State machine is in idle state. 0X0: not in idle 0x1: in idle - 26 - 3 - read-only - - - MAIN_FSM_STATE - NA - 29 - 3 - read-only - - - - - PRESENT_STATE1 - NA - 0x54 - 0x20 - - - DATA_BYTE_CNT - Present transfer data byte cnt: tx data byte cnt if write rx data byte cnt if read ibi data byte cnt if IBI handle. - 0 - 16 - read-only - - - - - DEVICE_TABLE - Pointer for Device Address Table - 0x58 - 0x20 - - - REG_DCT_DAA_INIT_INDEX - Reserved - 0 - 4 - read-write - - - REG_DAT_DAA_INIT_INDEX - NA - 4 - 4 - read-write - - - PRESENT_DCT_INDEX - NA - 8 - 4 - read-only - - - PRESENT_DAT_INDEX - NA - 12 - 4 - read-only - - - - - TIME_OUT_VALUE - NA - 0x5C - 0x20 - 0x00410410 - - - REG_RESP_BUF_TO_VALUE - NA - 0 - 5 - read-write - - - REG_RESP_BUF_TO_EN - NA - 5 - 1 - read-write - - - REG_IBI_DATA_BUF_TO_VALUE - NA - 6 - 5 - read-write - - - REG_IBI_DATA_BUF_TO_EN - NA - 11 - 1 - read-write - - - REG_IBI_STATUS_BUF_TO_VALUE - NA - 12 - 5 - read-write - - - REG_IBI_STATUS_BUF_TO_EN - NA - 17 - 1 - read-write - - - REG_RX_DATA_BUF_TO_VALUE - NA - 18 - 5 - read-write - - - REG_RX_DATA_BUF_TO_EN - NA - 23 - 1 - read-write - - - - - SCL_I3C_MST_OD_TIME - NA - 0x60 - 0x20 - 0x00050019 - - - REG_I3C_MST_OD_LOW_PERIOD - SCL Open-Drain low count for I3C transfers targeted to I3C devices. - 0 - 16 - read-write - - - REG_I3C_MST_OD_HIGH_PERIOD - SCL Open-Drain High count for I3C transfers targeted to I3C devices. - 16 - 16 - read-write - - - - - SCL_I3C_MST_PP_TIME - NA - 0x64 - 0x20 - 0x00050005 - - - REG_I3C_MST_PP_LOW_PERIOD - NA - 0 - 8 - read-write - - - REG_I3C_MST_PP_HIGH_PERIOD - NA - 16 - 8 - read-write - - - - - SCL_I2C_FM_TIME - NA - 0x68 - 0x20 - 0x004B00A3 - - - REG_I2C_FM_LOW_PERIOD - NA - 0 - 16 - read-write - - - REG_I2C_FM_HIGH_PERIOD - The SCL open-drain low count timing for I2C Fast Mode transfers. - 16 - 16 - read-write - - - - - SCL_I2C_FMP_TIME - NA - 0x6C - 0x20 - 0x0021003F - - - REG_I2C_FMP_LOW_PERIOD - NA - 0 - 16 - read-write - - - REG_I2C_FMP_HIGH_PERIOD - NA - 16 - 8 - read-write - - - - - SCL_EXT_LOW_TIME - NA - 0x70 - 0x20 - - - REG_I3C_MST_EXT_LOW_PERIOD1 - NA - 0 - 8 - read-write - - - REG_I3C_MST_EXT_LOW_PERIOD2 - NA - 8 - 8 - read-write - - - REG_I3C_MST_EXT_LOW_PERIOD3 - NA - 16 - 8 - read-write - - - REG_I3C_MST_EXT_LOW_PERIOD4 - NA - 24 - 8 - read-write - - - - - SDA_SAMPLE_TIME - NA - 0x74 - 0x20 - - - REG_SDA_OD_SAMPLE_TIME - It is used to adjust sda sample point when scl high under open drain speed - 0 - 9 - read-write - - - REG_SDA_PP_SAMPLE_TIME - It is used to adjust sda sample point when scl high under push pull speed - 9 - 5 - read-write - - - - - SDA_HOLD_TIME - NA - 0x78 - 0x20 - 0x00000001 - - - REG_SDA_OD_TX_HOLD_TIME - It is used to adjust sda drive point after scl neg under open drain speed - 0 - 9 - read-write - - - REG_SDA_PP_TX_HOLD_TIME - It is used to adjust sda dirve point after scl neg under push pull speed - 9 - 5 - read-write - - - - - SCL_START_HOLD - NA - 0x7C - 0x20 - 0x00000008 - - - REG_SCL_START_HOLD_TIME - I2C_SCL_START_HOLD_TIME - 0 - 9 - read-write - - - REG_START_DET_HOLD_TIME - NA - 9 - 2 - read-write - - - - - SCL_RSTART_SETUP - NA - 0x80 - 0x20 - 0x00000008 - - - REG_SCL_RSTART_SETUP_TIME - I2C_SCL_RSTART_SETUP_TIME - 0 - 9 - read-write - - - - - SCL_STOP_HOLD - NA - 0x84 - 0x20 - 0x00000008 - - - REG_SCL_STOP_HOLD_TIME - I2C_SCL_STOP_HOLD_TIME - 0 - 9 - read-write - - - - - SCL_STOP_SETUP - NA - 0x88 - 0x20 - 0x00000008 - - - REG_SCL_STOP_SETUP_TIME - I2C_SCL_STOP_SETUP_TIME - 0 - 9 - read-write - - - - - BUS_FREE_TIME - NA - 0x90 - 0x20 - 0x00000005 - - - REG_BUS_FREE_TIME - I3C Bus Free Count Value. This field is used only in Master mode. In pure Bus System, this field represents tCAS. In Mixed Bus System, this field is expected to be programmed to tLOW of I2C Timing. - 0 - 16 - read-write - - - - - SCL_TERMN_T_EXT_LOW_TIME - NA - 0x94 - 0x20 - 0x00000002 - - - REG_I3C_MST_TERMN_T_EXT_LOW_TIME - NA - 0 - 8 - read-write - - - - - VER_ID - NA - 0xA0 - 0x20 - 0x20230504 - - - REG_I3C_MST_VER_ID - This field indicates the controller current release number that is read by an application. - 0 - 32 - read-write - - - - - VER_TYPE - NA - 0xA4 - 0x20 - - - REG_I3C_MST_VER_TYPE - This field indicates the controller current release type that is read by an application. - 0 - 32 - read-write - - - - - FPGA_DEBUG_PROBE - NA - 0xAC - 0x20 - 0x00000001 - - - REG_I3C_MST_FPGA_DEBUG_PROBE - For Debug Probe Test on FPGA - 0 - 32 - read-write - - - - - RND_ECO_CS - NA - 0xB0 - 0x20 - - - REG_RND_ECO_EN - NA - 0 - 1 - read-write - - - RND_ECO_RESULT - NA - 1 - 1 - read-only - - - - - RND_ECO_LOW - NA - 0xB4 - 0x20 - - - REG_RND_ECO_LOW - NA - 0 - 32 - read-write - - - - - RND_ECO_HIGH - NA - 0xB8 - 0x20 - 0x0000FFFF - - - REG_RND_ECO_HIGH - NA - 0 - 32 - read-write - - - - - - - I3C_MST_MEM - I3C_MST_MEM Peripheral - I3C_MST_MEM - 0x500DA000 - - 0x0 - 0x108 - registers - - - - COMMAND_BUF_PORT - NA - 0x8 - 0x20 - - - REG_COMMAND - Contains a Command Descriptor structure that depends on the requested transfer type. Command Descriptor structure is used to schedule the transfers to devices on I3C bus. - 0 - 32 - read-write - - - - - RESPONSE_BUF_PORT - NA - 0xC - 0x20 - - - RESPONSE - The Response Buffer can be read through this register. The response status for each Command is written into the Response Buffer by the controller if ROC (Response On Completion) bit is set or if transfer error has occurred. The response buffer can be read through this register. - 0 - 32 - read-only - - - - - RX_DATA_PORT - NA - 0x10 - 0x20 - - - RX_DATA_PORT - Receive Data Port. Receive data is mapped to the Rx-data buffer and receive data is always packed in 4-byte aligned data words. If the length of data transfer is not aligned to 4-bytes boundary, then there will be extra(unused) bytes(the additional data bytes have to be ignored) at the end of the transferred data. The valid data must be identified using the DATA_LENGTH filed in the Response Descriptor. - 0 - 32 - read-only - - - - - TX_DATA_PORT - NA - 0x14 - 0x20 - - - REG_TX_DATA_PORT - Transmit Data Port. Transmit data is mapped to the Tx-data buffer and transmit data is always packed in 4-byte aligned data words. If the length of data transfer is not aligned to 4-bytes boundary, then there will be extra(unused) bytes(the additional data bytes have to be ignored) at the end of the transferred data. The valid data must be identified using the DATA_LENGTH filed in the Response Descriptor. - 0 - 32 - read-write - - - - - IBI_STATUS_BUF - In-Band Interrupt Buffer Status/Data Register. When receiving an IBI, IBI_PORT is used to both: Read the IBI Status Read the IBI Data(which is raw/opaque data) - 0x18 - 0x20 - - - DATA_LENGTH - This field represents the length of data received along with IBI, in bytes. - 0 - 8 - read-only - - - IBI_ID - IBI Identifier. The byte received after START which includes the address the R/W bit: Device address and R/W bit in case of Slave Interrupt or Master Request. - 8 - 8 - read-only - - - IBI_STS - IBI received data/status. IBI Data register is mapped to the IBI Buffer. The IBI Data is always packed in4-byte aligned and put to the IBI Buffer. This register When read from, reads the data from the IBI buffer. IBI Status register when read from, returns the data from the IBI Buffer and indicates how the controller responded to incoming IBI(SIR, MR and HJ). - 28 - 1 - read-only - - - - - IBI_DATA_BUF - NA - 0x40 - 0x20 - - - IBI_DATA - NA - 0 - 32 - read-only - - - - - DEV_ADDR_TABLE1_LOC - NA - 0xC0 - 0x20 - - - REG_DAT_DEV1_STATIC_ADDR - NA - 0 - 7 - read-write - - - REG_DAT_DEV1_DYNAMIC_ADDR - Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address. - 16 - 8 - read-write - - - REG_DAT_DEV1_NACK_RETRY_CNT - This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state. - 29 - 2 - read-write - - - REG_DAT_DEV1_I2C - Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. - 31 - 1 - read-write - - - - - DEV_ADDR_TABLE2_LOC - NA - 0xC4 - 0x20 - - - REG_DAT_DEV2_STATIC_ADDR - NA - 0 - 7 - read-write - - - REG_DAT_DEV2_DYNAMIC_ADDR - Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address. - 16 - 8 - read-write - - - REG_DAT_DEV2_NACK_RETRY_CNT - This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state. - 29 - 2 - read-write - - - REG_DAT_DEV2_I2C - Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. - 31 - 1 - read-write - - - - - DEV_ADDR_TABLE3_LOC - NA - 0xC8 - 0x20 - - - REG_DAT_DEV3_STATIC_ADDR - NA - 0 - 7 - read-write - - - REG_DAT_DEV3_DYNAMIC_ADDR - Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address. - 16 - 8 - read-write - - - REG_DAT_DEV3_NACK_RETRY_CNT - This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state. - 29 - 2 - read-write - - - REG_DAT_DEV3_I2C - Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. - 31 - 1 - read-write - - - - - DEV_ADDR_TABLE4_LOC - NA - 0xCC - 0x20 - - - REG_DAT_DEV4_STATIC_ADDR - NA - 0 - 7 - read-write - - - REG_DAT_DEV4_DYNAMIC_ADDR - Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address. - 16 - 8 - read-write - - - REG_DAT_DEV4_NACK_RETRY_CNT - This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state. - 29 - 2 - read-write - - - REG_DAT_DEV4_I2C - Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. - 31 - 1 - read-write - - - - - DEV_ADDR_TABLE5_LOC - NA - 0xD0 - 0x20 - - - REG_DAT_DEV5_STATIC_ADDR - NA - 0 - 7 - read-write - - - REG_DAT_DEV5_DYNAMIC_ADDR - Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address. - 16 - 8 - read-write - - - REG_DAT_DEV5_NACK_RETRY_CNT - This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state. - 29 - 2 - read-write - - - REG_DAT_DEV5_I2C - Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. - 31 - 1 - read-write - - - - - DEV_ADDR_TABLE6_LOC - NA - 0xD4 - 0x20 - - - REG_DAT_DEV6_STATIC_ADDR - NA - 0 - 7 - read-write - - - REG_DAT_DEV6_DYNAMIC_ADDR - Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address. - 16 - 8 - read-write - - - REG_DAT_DEV6_NACK_RETRY_CNT - This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state. - 29 - 2 - read-write - - - REG_DAT_DEV6_I2C - Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. - 31 - 1 - read-write - - - - - DEV_ADDR_TABLE7_LOC - NA - 0xD8 - 0x20 - - - REG_DAT_DEV7_STATIC_ADDR - NA - 0 - 7 - read-write - - - REG_DAT_DEV7_DYNAMIC_ADDR - Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address. - 16 - 8 - read-write - - - REG_DAT_DEV7_NACK_RETRY_CNT - This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state. - 29 - 2 - read-write - - - REG_DAT_DEV7_I2C - Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. - 31 - 1 - read-write - - - - - DEV_ADDR_TABLE8_LOC - NA - 0xDC - 0x20 - - - REG_DAT_DEV8_STATIC_ADDR - NA - 0 - 7 - read-write - - - REG_DAT_DEV8_DYNAMIC_ADDR - Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address. - 16 - 8 - read-write - - - REG_DAT_DEV8_NACK_RETRY_CNT - This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state. - 29 - 2 - read-write - - - REG_DAT_DEV8_I2C - Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. - 31 - 1 - read-write - - - - - DEV_ADDR_TABLE9_LOC - NA - 0xE0 - 0x20 - - - REG_DAT_DEV9_STATIC_ADDR - NA - 0 - 7 - read-write - - - REG_DAT_DEV9_DYNAMIC_ADDR - Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address. - 16 - 8 - read-write - - - REG_DAT_DEV9_NACK_RETRY_CNT - This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state. - 29 - 2 - read-write - - - REG_DAT_DEV9_I2C - Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. - 31 - 1 - read-write - - - - - DEV_ADDR_TABLE10_LOC - NA - 0xE4 - 0x20 - - - REG_DAT_DEV10_STATIC_ADDR - NA - 0 - 7 - read-write - - - REG_DAT_DEV10_DYNAMIC_ADDR - Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address. - 16 - 8 - read-write - - - REG_DAT_DEV10_NACK_RETRY_CNT - This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state. - 29 - 2 - read-write - - - REG_DAT_DEV10_I2C - Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. - 31 - 1 - read-write - - - - - DEV_ADDR_TABLE11_LOC - NA - 0xE8 - 0x20 - - - REG_DAT_DEV11_STATIC_ADDR - NA - 0 - 7 - read-write - - - REG_DAT_DEV11_DYNAMIC_ADDR - Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address. - 16 - 8 - read-write - - - REG_DAT_DEV11_NACK_RETRY_CNT - This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state. - 29 - 2 - read-write - - - REG_DAT_DEV11_I2C - Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. - 31 - 1 - read-write - - - - - DEV_ADDR_TABLE12_LOC - NA - 0xEC - 0x20 - - - REG_DAT_DEV12_STATIC_ADDR - NA - 0 - 7 - read-write - - - REG_DAT_DEV12_DYNAMIC_ADDR - Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address. - 16 - 8 - read-write - - - REG_DAT_DEV12_NACK_RETRY_CNT - This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state. - 29 - 2 - read-write - - - REG_DAT_DEV12_I2C - Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. - 31 - 1 - read-write - - - - - DEV_CHAR_TABLE1_LOC1 - NA - 0x100 - 0x20 - - - DCT_DEV1_LOC1 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE1_LOC2 - NA - 0x104 - 0x20 - - - DCT_DEV1_LOC2 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE1_LOC3 - NA - 0x108 - 0x20 - - - DCT_DEV1_LOC3 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE1_LOC4 - NA - 0x10C - 0x20 - - - DCT_DEV1_LOC4 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE2_LOC1 - NA - 0x110 - 0x20 - - - DCT_DEV2_LOC1 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE2_LOC2 - NA - 0x114 - 0x20 - - - DCT_DEV2_LOC2 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE2_LOC3 - NA - 0x118 - 0x20 - - - DCT_DEV2_LOC3 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE2_LOC4 - NA - 0x11C - 0x20 - - - DCT_DEV2_LOC4 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE3_LOC1 - NA - 0x120 - 0x20 - - - DCT_DEV3_LOC1 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE3_LOC2 - NA - 0x124 - 0x20 - - - DCT_DEV3_LOC2 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE3_LOC3 - NA - 0x128 - 0x20 - - - DCT_DEV3_LOC3 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE3_LOC4 - NA - 0x12C - 0x20 - - - DCT_DEV3_LOC4 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE4_LOC1 - NA - 0x130 - 0x20 - - - DCT_DEV4_LOC1 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE4_LOC2 - NA - 0x134 - 0x20 - - - DCT_DEV4_LOC2 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE4_LOC3 - NA - 0x138 - 0x20 - - - DCT_DEV4_LOC3 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE4_LOC4 - NA - 0x13C - 0x20 - - - DCT_DEV4_LOC4 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE5_LOC1 - NA - 0x140 - 0x20 - - - DCT_DEV5_LOC1 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE5_LOC2 - NA - 0x144 - 0x20 - - - DCT_DEV5_LOC2 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE5_LOC3 - NA - 0x148 - 0x20 - - - DCT_DEV5_LOC3 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE5_LOC4 - NA - 0x14C - 0x20 - - - DCT_DEV5_LOC4 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE6_LOC1 - NA - 0x150 - 0x20 - - - DCT_DEV6_LOC1 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE6_LOC2 - NA - 0x154 - 0x20 - - - DCT_DEV6_LOC2 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE6_LOC3 - NA - 0x158 - 0x20 - - - DCT_DEV6_LOC3 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE6_LOC4 - NA - 0x15C - 0x20 - - - DCT_DEV6_LOC4 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE7_LOC1 - NA - 0x160 - 0x20 - - - DCT_DEV7_LOC1 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE7_LOC2 - NA - 0x164 - 0x20 - - - DCT_DEV7_LOC2 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE7_LOC3 - NA - 0x168 - 0x20 - - - DCT_DEV7_LOC3 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE7_LOC4 - NA - 0x16C - 0x20 - - - DCT_DEV7_LOC4 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE8_LOC1 - NA - 0x170 - 0x20 - - - DCT_DEV8_LOC1 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE8_LOC2 - NA - 0x174 - 0x20 - - - DCT_DEV8_LOC2 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE8_LOC3 - NA - 0x178 - 0x20 - - - DCT_DEV8_LOC3 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE8_LOC4 - NA - 0x17C - 0x20 - - - DCT_DEV8_LOC4 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE9_LOC1 - NA - 0x180 - 0x20 - - - DCT_DEV9_LOC1 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE9_LOC2 - NA - 0x184 - 0x20 - - - DCT_DEV9_LOC2 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE9_LOC3 - NA - 0x188 - 0x20 - - - DCT_DEV9_LOC3 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE9_LOC4 - NA - 0x18C - 0x20 - - - DCT_DEV9_LOC4 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE10_LOC1 - NA - 0x190 - 0x20 - - - DCT_DEV10_LOC1 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE10_LOC2 - NA - 0x194 - 0x20 - - - DCT_DEV10_LOC2 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE10_LOC3 - NA - 0x198 - 0x20 - - - DCT_DEV10_LOC3 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE10_LOC4 - NA - 0x19C - 0x20 - - - DCT_DEV10_LOC4 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE11_LOC1 - NA - 0x1A0 - 0x20 - - - DCT_DEV11_LOC1 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE11_LOC2 - NA - 0x1A4 - 0x20 - - - DCT_DEV11_LOC2 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE11_LOC3 - NA - 0x1A8 - 0x20 - - - DCT_DEV11_LOC3 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE11_LOC4 - NA - 0x1AC - 0x20 - - - DCT_DEV11_LOC4 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE12_LOC1 - NA - 0x1B0 - 0x20 - - - DCT_DEV12_LOC1 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE12_LOC2 - NA - 0x1B4 - 0x20 - - - DCT_DEV12_LOC2 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE12_LOC3 - NA - 0x1B8 - 0x20 - - - DCT_DEV12_LOC3 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE12_LOC4 - NA - 0x1BC - 0x20 - - - DCT_DEV12_LOC4 - NA + REG_CPU_SRC_FREQ + cpu source clock frequency, step by 0.25MHz 0 32 read-only - - - - I3C_SLV - I3C Controller (Slave) - I3C_SLV - 0x500DB000 - - 0x0 - 0x40 - registers - - - I3C_SLV - 102 - - - - CONFIG - NA - 0x4 - 0x20 - 0x002F0001 - - - SLVENA - 1: allow the slave to operate on i2c or i3c bus. 0: the slave will ignore the bus. This should be not set until registers such as PARTNO, IDEXT and the like are set 1st -if used- since they impact data to the master - 0 - 1 - read-write - - - NACK - 1:the slave will NACK all requests to it except CCC broadcast. This should be used with caution as the Master may determine the slave is missing if overused. - 1 - 1 - read-write - - - MATCHSS - 1: the START and STOP sticky STATUS bits will only be set if MATCHED is set..This allows START and STOP to be used to detect end of a message to /from this slave. - 2 - 1 - read-write - - - S0IGNORE - If 1, the Slave will not detect S0 or S1 errors and so not lock up waiting on an Exit Pattern. This should only be used when the bus will not use HDR. - 3 - 1 - read-write - - - DDROK - NA - 4 - 1 - read-write - - - IDRAND - NA - 8 - 1 - read-write - - - OFFLINE - NA - 9 - 1 - read-write - - - BAMATCH - Bus Available condition match value for current ???Slow clock???. This provides the count of the slow clock to count out 1us (or more) to allow an IBI to drive SDA Low when the Master is not doing so. The max width , and so max value, is controlled by the block. Only if enabled for events such IBI or MR or HJ, and if enabled to provide this as a register. With is limited to CLK_SLOW_BITS - 16 - 8 - read-write - - - SADDR - If allowed by the block:sets i2c 7 bits static address,else should be 0. If enabled to use one and to be provided by SW. Block may provide in HW as well. - 25 - 7 - read-write - - - - STATUS - NA - 0x8 - 0x20 - - - STNOTSTOP - Is 1 if bus is busy(activity) and 0 when in a STOP condition. Other bits may also set when busy. Note that this can also be true from an S0 or S1 error, which waits for an Exit Pattern. - 0 - 1 - read-only - - - STMSG - Is 1 if this bus Slave is listening to the bus traffic or repsonding, If STNOSTOP=1, then this will be 0 when a non-matching address seen until next respeated START it STOP. - 1 - 1 - read-only - - - STCCCH - Is 1 if a CCC message is being handled automatically. - 2 - 1 - read-only - - - STREQRD - 1 if the req in process is an sdr read from this slave or an IBI is being pushed out, - 3 - 1 - read-only - - - STREQWR - NA - 4 - 1 - read-only - - - STDAA - NA - 5 - 1 - read-only - - - STHDR - NA - 6 - 1 - read-only - - - START - NA - 8 - 1 - read-write - - - MATCHED - NA - 9 - 1 - read-write - - - STOP - NA - 10 - 1 - read-write - + CPU_CLK_STATUS0 + CPU Clock Status + 0xE0 + 0x20 + - RXPEND - Receiving a message from master,which is not being handled by block(not a CCC internally processed). For all but External FIFO, this uses DATACTRL RXTRIG, which defaults to not-empty. If DMA is enabled for RX, DMA will be signaled as well. Will self-clear if data is read(FIFO and non-FIFO) - 11 + REG_ASIC_OR_FPGA + 0: ASIC mode, 1: FPGA mode + 0 1 read-only - TXNOTFULL - Is 1 when the To-bus buffer/FIFO can accept more data to go out. Defau:1. For all but External FIFO, this uses DATACTRL TXTRIG,which defaults to not-full. If DMA is enabled for TX, it will also be signaled to provide more. - 12 + REG_CPU_DIV_EFFECT + 0: Divider bypass, 1: Divider takes effect + 1 1 read-only - DACHG - The Slv Dynamic Address has been assigned, reassigned, or reset(lost) and is now in that state of being valid or none. Actual DA can be seen in the DYNADDR register. Note that this will also be used when MAP Auto feature is configured. This will be changing one or more MAP items. See DYNADDR and/or MAPCTRLn. DYNAADDR for the main DA(0) will indicate if last change was due to Auto MAP. - 13 + REG_CPU_SRC_IS_CPLL + 0: CPU source isn't cpll_400m, 1: CPU Source is cll_400m + 2 1 - read-write + read-only - CCC - A common -command-code(CCC), not handled by block, has been received. This acts differently between: *Broadcasted ones, which will then also correspond with RXPEND and the 1st byte will be the CCC(command) . *Direct ones, which may never be directed to this device. If it is, then the TXSEND or RXPEND will be triggered with this end the RXPEND will contain the command. - 14 - 1 - read-write + REG_CPU_DIV_NUM_CUR + cpu current div number + 3 + 8 + read-only - ERRWARN - NA - 15 - 1 + REG_CPU_DIV_NUMERATOR_CUR + cpu current div numerator + 11 + 8 read-only - HDRMATCH - NA - 16 - 1 - read-write + REG_CPU_DIV_DENOMINATOR_CUR + cpu current div denominator + 19 + 8 + read-only - CTRL - NA - 0xC + DBG_CLK_CTRL0 + Reserved + 0xE4 0x20 + 0x03FFFFFF - SLV_EVENT - If set to non-0, will request an event. Once requested, STATUS.EVENT and EVDET will show the status as it progresses. Once completed, the field will automatically return to 0. Once non-0, only 0 can be written(to cancel) until done. 0: Normal mode. If set to 0 after was a non-0 value, will cancel if not already in flight. 1: start an IBI. This will try to push through an IBI on the bus. If data associate with the IBI, it will be drawn from the IBIDATA field. Note that if Time control is enabled, this will include anytime control related bytes further, the IBIDATA byte will have bit7 set to 1. + REG_DBG_CH0_SEL + Reserved 0 - 2 - read-write - - - EXTDATA - reserved - 3 - 1 - read-write - - - MAPIDX - Index of Dynamic Address that IBI is for. This is 0 for the main or base Dynamic Address, or can be any valid index. - 4 - 4 + 8 read-write - IBIDATA - Data byte to go with an IBI, if enabled for it. If enabled (was in BCR), then it is required. + REG_DBG_CH1_SEL + Reserved 8 8 read-write - PENDINT - Should be set to the pending interrupt that GETSTATUS CCC will return. This should be maintained by the application if used and configured, as the Master will read this. If not configured, the GETSTATUS field will return 1 if an IBI is pending, and 0 otherwise. + REG_DBG_CH2_SEL + Reserved 16 - 4 - read-write - - - ACTSTATE - NA - 20 - 2 + 8 read-write - VENDINFO - NA + REG_DBG_CH0_DIV_NUM + Reserved 24 8 read-write @@ -69820,483 +58700,802 @@ The SCL output line will be stretched low when reg_slave_scl_stretch_en is 1 and - INTSET - INSET allows setting enables for interrupts(connecting the corresponding STATUS source to causing an IRQ to the processor) - 0x10 + DBG_CLK_CTRL1 + Reserved + 0xE8 0x20 + 0x00000303 - STOP_ENA - Interrupt on STOP state on the bus. See Start as the preferred interrupt when needed. This interrupt may not trigger for quick STOP/START combination, as it relates to the state of being stopped. - 10 + REG_DBG_CH1_DIV_NUM + Reserved + 0 + 8 + read-write + + + REG_DBG_CH2_DIV_NUM + Reserved + 8 + 8 + read-write + + + REG_DBG_CH0_EN + Reserved + 16 1 read-write - RXPEND_ENA - Interrupt when receiving a message from Master, which is not being handled by the block (excludes CCCs being handled automatically). If FIFO, then RX fullness trigger. If DMA, then message end. - 11 + REG_DBG_CH1_EN + Reserved + 17 1 read-write - TXSEND_ENA - NA - 12 + REG_DBG_CH2_EN + Reserved + 18 1 read-write - INTCLR - NA - 0x14 + HPCORE_WDT_RESET_SOURCE0 + Reserved + 0xEC 0x20 + 0x00000002 - STOP_CLR - Interrupt on STOP state on the bus. See Start as the preferred interrupt when needed. This interrupt may not trigger for quick STOP/START combination, as it relates to the state of being stopped. - 10 + REG_HPCORE0_WDT_RESET_SOURCE_SEL + 1'b0: use wdt0 to reset hpcore0, 1'b1: use wdt1 to reset hpcore0 + 0 1 - write-only + read-write - RXPEND_CLR - Interrupt when receiving a message from Master, which is not being handled by the block (excludes CCCs being handled automatically). If FIFO, then RX fullness trigger. If DMA, then message end. - 11 + REG_HPCORE1_WDT_RESET_SOURCE_SEL + 1'b0: use wdt0 to reset hpcore1, 1'b1: use wdt1 to reset hpcore1 + 1 1 - write-only + read-write + + + + + + LP_HUK + LP_HUK Peripheral + HUK + 0x50114000 + + 0x0 + 0x1A8 + registers + + + LP_HUK + 20 + + + + CLK + HUK Generator clock gate control register + 0x4 + 0x20 + 0x00000001 + - TXSEND_CLR - NA - 12 + EN + Write 1 to force on register clock gate. + 0 1 - write-only + read-write + + + MEM_CG_FORCE_ON + Write 1 to force on memory clock gate. + 1 + 1 + read-write - INTMASKED - NA - 0x18 + INT_RAW + HUK Generator interrupt raw register, valid in level. + 0x8 0x20 - STOP_MASK - Interrupt on STOP state on the bus. See Start as the preferred interrupt when needed. This interrupt may not trigger for quick STOP/START combination, as it relates to the state of being stopped. - 10 + PREP_DONE_INT_RAW + The raw interrupt status bit for the huk_prep_done_int interrupt + 0 1 read-only - RXPEND_MASK - Interrupt when receiving a message from Master, which is not being handled by the block (excludes CCCs being handled automatically). If FIFO, then RX fullness trigger. If DMA, then message end. - 11 + PROC_DONE_INT_RAW + The raw interrupt status bit for the huk_proc_done_int interrupt + 1 1 read-only - TXSEND_MASK - NA - 12 + POST_DONE_INT_RAW + The raw interrupt status bit for the huk_post_done_int interrupt + 2 1 read-only - DATACTRL - NA - 0x2C + INT_ST + HUK Generator interrupt status register. + 0xC 0x20 - 0x000000B0 - FLUSHTB - Flushes the from-bus buffer/FIFO. Not normally used + PREP_DONE_INT_ST + The masked interrupt status bit for the huk_prep_done_int interrupt 0 1 - write-only + read-only - FLUSHFB - Flushes the to-bus buffer/FIFO. Used when Master terminates a to-bus (read) message prematurely + PROC_DONE_INT_ST + The masked interrupt status bit for the huk_proc_done_int interrupt 1 1 - write-only + read-only - UNLOCK - If this bit is not written 1, the register bits from 7 to 4 are not changed on write. - 3 + POST_DONE_INT_ST + The masked interrupt status bit for the huk_post_done_int interrupt + 2 1 - write-only - - - TXTRIG - Trigger level for tx emptiness when FIFOed, Affects interrupt and DMA(if enabled). The defaults is 3 - 4 - 2 - read-write - - - RXTRIG - Trigger level for rx fulless when FIFOed, Affects interrupt and DMA(if enabled). The defaults is 3 - 6 - 2 - read-write - - - TXCOUNT - NA - 16 - 5 read-only + + + + INT_ENA + HUK Generator interrupt enable register. + 0x10 + 0x20 + - RXCOUNT - NA - 24 - 5 - read-only + PREP_DONE_INT_ENA + The interrupt enable bit for the huk_prep_done_int interrupt + 0 + 1 + read-write - TXFULL - NA - 30 + PROC_DONE_INT_ENA + The interrupt enable bit for the huk_proc_done_int interrupt + 1 1 - read-only + read-write - RXEMPTY - NA - 31 + POST_DONE_INT_ENA + The interrupt enable bit for the huk_post_done_int interrupt + 2 1 - read-only + read-write - WDATAB - NA - 0x30 + INT_CLR + HUK Generator interrupt clear register. + 0x14 0x20 - WDATAB - NA + PREP_DONE_INT_CLR + Set this bit to clear the huk_prep_done_int interrupt 0 - 8 + 1 write-only - WDATA_END - NA - 8 + PROC_DONE_INT_CLR + Set this bit to clear the huk_proc_done_int interrupt + 1 1 write-only - - - - WDATABE - NA - 0x34 - 0x20 - - WDATABE - NA - 0 - 8 + POST_DONE_INT_CLR + Set this bit to clear the huk_post_done_int interrupt + 2 + 1 write-only - RDARAB - Read Byte Data (from-bus) register - 0x40 + CONF + HUK Generator configuration register + 0x20 0x20 - DATA0 - This register allows reading a byte from the bus unless external FIFO is used. A byte should not be read unless there is data waiting, as indicated by the RXPEND bit being set in the STATUS register + MODE + Set this field to choose the huk process. 1: process huk generate mode. 0: process huk recovery mode. 0 - 8 - read-only + 1 + read-write - RDATAH - Read Half-word Data (from-bus) register - 0x48 + START + HUK Generator control register + 0x24 0x20 - DATA_LSB - NA + START + Write 1 to continue HUK Generator operation at LOAD/GAIN state. 0 - 8 - read-only + 1 + write-only - DATA_MSB - This register allows reading a Half-word (byte pair) from the bus unless external FIFO is used. A Half-word should not be read unless there is at least 2 bytes of data waiting, as indicated by the RX FIFO level trigger or RXCOUNT available space in the DATACTRL register - 8 - 8 - read-only + CONTINUE + Write 1 to start HUK Generator at IDLE state. + 1 + 1 + write-only - CAPABILITIES2 - NA - 0x5C + STATE + HUK Generator state register + 0x28 0x20 - 0x00000100 - CAPABLITIES2 - NA + STATE + The state of HUK Generator. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY. 0 - 32 + 2 read-only - CAPABILITIES - NA - 0x60 + STATUS + HUK Generator HUK status register + 0x34 0x20 - 0x7C13FC1C - CAPABLITIES - NA + STATUS + The HUK generation status. 0: HUK is not generated. 1: HUK is generated and valid. 2: HUK is generated but invalid. 3: reserved. 0 - 32 + 2 read-only - - - - IDPARTNO - NA - 0x6C - 0x20 - - PARTNO - NA - 0 - 32 - read-write + RISK_LEVEL + The risk level of HUK. 0-6: the higher the risk level is, the more error bits there are in the PUF SRAM. 7: Error Level, HUK is invalid. + 2 + 3 + read-only - IDEXT - NA - 0x70 + DATE + Version control register + 0xFC 0x20 + 0x02305040 - IDEXT - NA + DATE + HUK Generator version control register. 0 - 32 + 28 read-write - VENDORID - NA - 0x74 + 96 + 0x4 + INFO_MEM[%s] + The memory that stores HUK info. + 0x100 0x20 - 0x00005550 - - - VID - NA - 0 - 15 - read-write - - - AXI_ICM - AXI_ICM Peripheral - ICM_AXI - 0x500A4000 + I2C0 + I2C (Inter-Integrated Circuit) Controller 0 + I2C + 0x500C4000 0x0 - 0x10 + 0x90 registers + + I2C0 + 44 + - VERID_FILEDS - NA + SCL_LOW_PERIOD + Configures the low level width of the SCL Clock. 0x0 0x20 - 0x3430342A - ICM_REG_VERID - NA + SCL_LOW_PERIOD + Configures the low level width of the SCL Clock. +Measurement unit: i2c_sclk. 0 - 32 - read-only + 9 + read-write - HW_CFG - NA + CTR + Transmission setting 0x4 0x20 - 0x0070D151 + 0x00000208 - ICM_REG_AXI_HWCFG_QOS_SUPPORT - NA + SDA_FORCE_OUT + Configures the SDA output mode +1: Direct output, + +0: Open drain output. 0 1 - read-only + read-write - ICM_REG_AXI_HWCFG_APB3_SUPPORT - NA + SCL_FORCE_OUT + Configures the SCL output mode +1: Direct output, + +0: Open drain output. 1 1 - read-only + read-write - ICM_REG_AXI_HWCFG_AXI4_SUPPORT - NA + SAMPLE_SCL_LEVEL + Configures the sample mode for SDA. +1: Sample SDA data on the SCL low level. + +0: Sample SDA data on the SCL high level. 2 1 - read-only + read-write - ICM_REG_AXI_HWCFG_LOCK_EN - NA + RX_FULL_ACK_LEVEL + Configures the ACK value that needs to be sent by master when the rx_fifo_cnt has reached the threshold. 3 1 - read-only + read-write - ICM_REG_AXI_HWCFG_TRUST_ZONE_EN - NA + MS_MODE + Configures the module as an I2C Master or Slave. +0: Slave + +1: Master 4 1 - read-only + read-write - ICM_REG_AXI_HWCFG_DECODER_TYPE - NA + TRANS_START + Configures to start sending the data in txfifo for slave. +0: No effect + +1: Start 5 1 - read-only + write-only - ICM_REG_AXI_HWCFG_REMAP_EN - NA + TX_LSB_FIRST + Configures to control the sending order for data needing to be sent. +1: send data from the least significant bit, + +0: send data from the most significant bit. 6 1 - read-only + read-write - ICM_REG_AXI_HWCFG_BI_DIR_CMD_EN - NA + RX_LSB_FIRST + Configures to control the storage order for received data. +1: receive data from the least significant bit + +0: receive data from the most significant bit. 7 1 + read-write + + + CLK_EN + Configures whether to gate clock signal for registers. + +0: Force clock on for registers + +1: Support clock only when registers are read or written to by software. + 8 + 1 + read-write + + + ARBITRATION_EN + Configures to enable I2C bus arbitration detection. +0: No effect + +1: Enable + 9 + 1 + read-write + + + FSM_RST + Configures to reset the SCL_FSM. +0: No effect + +1: Reset + 10 + 1 + write-only + + + CONF_UPGATE + Configures this bit for synchronization +0: No effect + +1: Synchronize + 11 + 1 + write-only + + + SLV_TX_AUTO_START_EN + Configures to enable slave to send data automatically +0: Disable + +1: Enable + 12 + 1 + read-write + + + ADDR_10BIT_RW_CHECK_EN + Configures to check if the r/w bit of 10bit addressing consists with I2C protocol. +0: Not check + +1: Check + 13 + 1 + read-write + + + ADDR_BROADCASTING_EN + Configures to support the 7bit general call function. +0: Not support + +1: Support + 14 + 1 + read-write + + + + + SR + Describe I2C work status. + 0x8 + 0x20 + 0x0000C000 + + + RESP_REC + Represents the received ACK value in master mode or slave mode. +0: ACK, + +1: NACK. + 0 + 1 read-only - ICM_REG_AXI_HWCFG_LOW_POWER_INF_EN - NA + SLAVE_RW + Represents the transfer direction in slave mode,. +1: Master reads from slave, + +0: Master writes to slave. + 1 + 1 + read-only + + + ARB_LOST + Represents whether the I2C controller loses control of SCL line. +0: No arbitration lost + +1: Arbitration lost + 3 + 1 + read-only + + + BUS_BUSY + Represents the I2C bus state. +1: The I2C bus is busy transferring data, + +0: The I2C bus is in idle state. + 4 + 1 + read-only + + + SLAVE_ADDRESSED + Represents whether the address sent by the master is equal to the address of the slave. +Valid only when the module is configured as an I2C Slave. +0: Not equal + +1: Equal + 5 + 1 + read-only + + + RXFIFO_CNT + Represents the number of data bytes to be sent. 8 + 6 + read-only + + + STRETCH_CAUSE + Represents the cause of SCL clocking stretching in slave mode. +0: Stretching SCL low when the master starts to read data. + +1: Stretching SCL low when I2C TX FIFO is empty in slave mode. + +2: Stretching SCL low when I2C RX FIFO is full in slave mode. + 14 + 2 + read-only + + + TXFIFO_CNT + Represents the number of data bytes received in RAM. + 18 + 6 + read-only + + + SCL_MAIN_STATE_LAST + Represents the states of the I2C module state machine. +0: Idle, + +1: Address shift, + +2: ACK address, + +3: Rx data, + +4: Tx data, + +5: Send ACK, + +6: Wait ACK + 24 + 3 + read-only + + + SCL_STATE_LAST + Represents the states of the state machine used to produce SCL. +0: Idle, + +1: Start, + +2: Negative edge, + +3: Low, + +4: Positive edge, + +5: High, + +6: Stop + 28 + 3 + read-only + + + + + TO + Setting time out control for receiving data. + 0xC + 0x20 + 0x00000010 + + + TIME_OUT_VALUE + Configures the timeout threshold period for SCL stucking at high or low level. The actual period is 2^(reg_time_out_value). +Measurement unit: i2c_sclk. + 0 + 5 + read-write + + + TIME_OUT_EN + Configures to enable time out control. +0: No effect + +1: Enable + 5 + 1 + read-write + + + + + SLAVE_ADDR + Local slave address setting + 0x10 + 0x20 + + + SLAVE_ADDR + Configure the slave address of I2C Slave. + 0 + 15 + read-write + + + ADDR_10BIT_EN + Configures to enable the slave 10-bit addressing mode in master mode. +0: No effect + +1: Enable + 31 1 + read-write + + + + + FIFO_ST + FIFO status register. + 0x14 + 0x20 + + + RXFIFO_RADDR + Represents the offset address of the APB reading from RXFIFO + 0 + 5 read-only - ICM_REG_AXI_HWCFG_AXI_NUM_MASTERS - NA - 12 + RXFIFO_WADDR + Represents the offset address of i2c module receiving data and writing to RXFIFO. + 5 5 read-only - ICM_REG_AXI_HWCFG_AXI_NUM_SLAVES - NA - 20 + TXFIFO_RADDR + Represents the offset address of i2c module reading from TXFIFO. + 10 + 5 + read-only + + + TXFIFO_WADDR + Represents the offset address of APB bus writing to TXFIFO. + 15 5 read-only + + SLAVE_RW_POINT + Represents the offset address in the I2C Slave RAM addressed by I2C Master when in I2C slave mode. + 22 + 8 + read-only + - CMD - NA - 0x8 + FIFO_CONF + FIFO configuration register. + 0x18 0x20 + 0x0000408B - ICM_REG_AXI_CMD - NA + RXFIFO_WM_THRHD + Configures the water mark threshold of RXFIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than reg_rxfifo_wm_thrhd[4:0], reg_rxfifo_wm_int_raw bit will be valid. 0 - 3 + 5 read-write - ICM_REG_RD_WR_CHAN - NA - 7 - 1 + TXFIFO_WM_THRHD + Configures the water mark threshold of TXFIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than reg_txfifo_wm_thrhd[4:0], reg_txfifo_wm_int_raw bit will be valid. + 5 + 5 read-write - ICM_REG_AXI_MASTER_PORT - NA - 8 - 4 + NONFIFO_EN + Configures to enable APB nonfifo access. + 10 + 1 read-write - ICM_REG_AXI_ERR_BIT - NA - 28 + FIFO_ADDR_CFG_EN + Configures to enable double addressing mode. When this mode is enabled, the byte received after the I2C address byte represents the offset address in the I2C Slave RAM. +0: Disable + +1: Enable + 11 1 - read-only + read-write - ICM_REG_AXI_SOFT_RESET_BIT - NA - 29 + RX_FIFO_RST + Configures to reset RXFIFO. +0: No effect + +1: Reset + 12 1 read-write - ICM_REG_AXI_RD_WR_CMD - NA - 30 + TX_FIFO_RST + Configures to reset TXFIFO. +0: No effect + +1: Reset + 13 1 read-write - ICM_REG_AXI_CMD_EN - NA - 31 + FIFO_PRT_EN + Configures to enable FIFO pointer in non-fifo access mode. This bit controls the valid bits and the TX/RX FIFO overflow, underflow, full and empty interrupts. +0: No effect + +1: Enable + 14 1 read-write @@ -70304,2723 +59503,2976 @@ The SCL output line will be stretched low when reg_slave_scl_stretch_en is 1 and DATA - NA - 0xC + Rx FIFO read data. + 0x1C 0x20 - ICM_REG_DATA - NA + FIFO_RDATA + Represents the value of RXFIFO read data. 0 - 32 - read-write + 8 + read-only - - - - IO_MUX - Input/Output Multiplexer - IO_MUX - 0x500E1000 - - 0x0 - 0xE8 - registers - - - gpio0 - iomux control register for gpio0 - 0x4 + INT_RAW + Raw interrupt status + 0x20 0x20 - 0x00000800 + 0x00000002 - GPIO0_MCU_OE - output enable on sleep mode + RXFIFO_WM_INT_RAW + The raw interrupt status of I2C_RXFIFO_WM_INT interrupt. 0 1 - read-write + read-only - GPIO0_SLP_SEL - io sleep mode enable. set 1 to enable sleep mode. + TXFIFO_WM_INT_RAW + The raw interrupt status of I2C_TXFIFO_WM_INT interrupt. 1 1 - read-write + read-only - GPIO0_MCU_WPD - pull-down enable on sleep mode + RXFIFO_OVF_INT_RAW + The raw interrupt status of I2C_RXFIFO_OVF_INT interrupt. 2 1 - read-write + read-only - GPIO0_MCU_WPU - pull-up enable on sleep mode + END_DETECT_INT_RAW + The raw interrupt status of the I2C_END_DETECT_INT interrupt. 3 1 - read-write + read-only - GPIO0_MCU_IE - input enable on sleep mode + BYTE_TRANS_DONE_INT_RAW + The raw interrupt status of the I2C_END_DETECT_INT interrupt. 4 1 - read-write + read-only - GPIO0_MCU_DRV - select drive strenth on sleep mode + ARBITRATION_LOST_INT_RAW + The raw interrupt status of the I2C_ARBITRATION_LOST_INT interrupt. 5 - 2 - read-write + 1 + read-only + + + MST_TXFIFO_UDF_INT_RAW + The raw interrupt status of I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + read-only - GPIO0_FUN_WPD - pull-down enable + TRANS_COMPLETE_INT_RAW + The raw interrupt status of the I2C_TRANS_COMPLETE_INT interrupt. 7 1 - read-write + read-only - GPIO0_FUN_WPU - pull-up enable + TIME_OUT_INT_RAW + The raw interrupt status of the I2C_TIME_OUT_INT interrupt. 8 1 - read-write + read-only - GPIO0_FUN_IE - input enable + TRANS_START_INT_RAW + The raw interrupt status of the I2C_TRANS_START_INT interrupt. 9 1 - read-write + read-only + + + NACK_INT_RAW + The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt. + 10 + 1 + read-only + + + TXFIFO_OVF_INT_RAW + The raw interrupt status of I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + read-only + + + RXFIFO_UDF_INT_RAW + The raw interrupt status of I2C_RXFIFO_UDF_INT interrupt. + 12 + 1 + read-only + + + SCL_ST_TO_INT_RAW + The raw interrupt status of I2C_SCL_ST_TO_INT interrupt. + 13 + 1 + read-only + + + SCL_MAIN_ST_TO_INT_RAW + The raw interrupt status of I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 + 1 + read-only + + + DET_START_INT_RAW + The raw interrupt status of I2C_DET_START_INT interrupt. + 15 + 1 + read-only - GPIO0_FUN_DRV - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - 10 - 2 - read-write + SLAVE_STRETCH_INT_RAW + The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt. + 16 + 1 + read-only - GPIO0_MCU_SEL - 0:select function0, 1:select function1 ... - 12 - 3 - read-write + GENERAL_CALL_INT_RAW + The raw interrupt status of I2C_GENARAL_CALL_INT interrupt. + 17 + 1 + read-only - GPIO0_FILTER_EN - input filter enable - 15 + SLAVE_ADDR_UNMATCH_INT_RAW + The raw interrupt status of I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt. + 18 1 - read-write + read-only - gpio1 - iomux control register for gpio1 - 0x8 + INT_CLR + Interrupt clear bits + 0x24 0x20 - 0x00000800 - GPIO1_MCU_OE - output enable on sleep mode + RXFIFO_WM_INT_CLR + Write 1 to clear I2C_RXFIFO_WM_INT interrupt. 0 1 - read-write + write-only - GPIO1_SLP_SEL - io sleep mode enable. set 1 to enable sleep mode. + TXFIFO_WM_INT_CLR + Write 1 to clear I2C_TXFIFO_WM_INT interrupt. 1 1 - read-write + write-only - GPIO1_MCU_WPD - pull-down enable on sleep mode + RXFIFO_OVF_INT_CLR + Write 1 to clear I2C_RXFIFO_OVF_INT interrupt. 2 1 - read-write + write-only - GPIO1_MCU_WPU - pull-up enable on sleep mode + END_DETECT_INT_CLR + Write 1 to clear the I2C_END_DETECT_INT interrupt. 3 1 - read-write + write-only - GPIO1_MCU_IE - input enable on sleep mode + BYTE_TRANS_DONE_INT_CLR + Write 1 to clear the I2C_END_DETECT_INT interrupt. 4 1 - read-write + write-only - GPIO1_MCU_DRV - select drive strenth on sleep mode + ARBITRATION_LOST_INT_CLR + Write 1 to clear the I2C_ARBITRATION_LOST_INT interrupt. 5 - 2 - read-write + 1 + write-only + + + MST_TXFIFO_UDF_INT_CLR + Write 1 to clear I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + write-only - GPIO1_FUN_WPD - pull-down enable + TRANS_COMPLETE_INT_CLR + Write 1 to clear the I2C_TRANS_COMPLETE_INT interrupt. 7 1 - read-write + write-only - GPIO1_FUN_WPU - pull-up enable + TIME_OUT_INT_CLR + Write 1 to clear the I2C_TIME_OUT_INT interrupt. 8 1 - read-write + write-only - GPIO1_FUN_IE - input enable + TRANS_START_INT_CLR + Write 1 to clear the I2C_TRANS_START_INT interrupt. 9 1 - read-write + write-only - GPIO1_FUN_DRV - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA + NACK_INT_CLR + Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt. 10 - 2 - read-write - - - GPIO1_MCU_SEL - 0:select function0, 1:select function1 ... - 12 - 3 - read-write - - - GPIO1_FILTER_EN - input filter enable - 15 - 1 - read-write - - - - - gpio2 - iomux control register for gpio2 - 0xC - 0x20 - 0x00000800 - - - GPIO2_MCU_OE - output enable on sleep mode - 0 1 - read-write + write-only - GPIO2_SLP_SEL - io sleep mode enable. set 1 to enable sleep mode. - 1 + TXFIFO_OVF_INT_CLR + Write 1 to clear I2C_TXFIFO_OVF_INT interrupt. + 11 1 - read-write + write-only - GPIO2_MCU_WPD - pull-down enable on sleep mode - 2 + RXFIFO_UDF_INT_CLR + Write 1 to clear I2C_RXFIFO_UDF_INT interrupt. + 12 1 - read-write + write-only - GPIO2_MCU_WPU - pull-up enable on sleep mode - 3 + SCL_ST_TO_INT_CLR + Write 1 to clear I2C_SCL_ST_TO_INT interrupt. + 13 1 - read-write + write-only - GPIO2_MCU_IE - input enable on sleep mode - 4 + SCL_MAIN_ST_TO_INT_CLR + Write 1 to clear I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 1 - read-write - - - GPIO2_MCU_DRV - select drive strenth on sleep mode - 5 - 2 - read-write + write-only - GPIO2_FUN_WPD - pull-down enable - 7 + DET_START_INT_CLR + Write 1 to clear I2C_DET_START_INT interrupt. + 15 1 - read-write + write-only - GPIO2_FUN_WPU - pull-up enable - 8 + SLAVE_STRETCH_INT_CLR + Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt. + 16 1 - read-write + write-only - GPIO2_FUN_IE - input enable - 9 + GENERAL_CALL_INT_CLR + Write 1 to clear I2C_GENARAL_CALL_INT interrupt. + 17 1 - read-write - - - GPIO2_FUN_DRV - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - 10 - 2 - read-write - - - GPIO2_MCU_SEL - 0:select function0, 1:select function1 ... - 12 - 3 - read-write + write-only - GPIO2_FILTER_EN - input filter enable - 15 + SLAVE_ADDR_UNMATCH_INT_CLR + Write 1 to clear I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt. + 18 1 - read-write + write-only - gpio3 - iomux control register for gpio3 - 0x10 + INT_ENA + Interrupt enable bits + 0x28 0x20 - 0x00000800 - GPIO3_MCU_OE - output enable on sleep mode + RXFIFO_WM_INT_ENA + Write 1 to enable I2C_RXFIFO_WM_INT interrupt. 0 1 read-write - GPIO3_SLP_SEL - io sleep mode enable. set 1 to enable sleep mode. + TXFIFO_WM_INT_ENA + Write 1 to enable I2C_TXFIFO_WM_INT interrupt. 1 1 read-write - GPIO3_MCU_WPD - pull-down enable on sleep mode + RXFIFO_OVF_INT_ENA + Write 1 to enable I2C_RXFIFO_OVF_INT interrupt. 2 1 read-write - GPIO3_MCU_WPU - pull-up enable on sleep mode + END_DETECT_INT_ENA + Write 1 to enable the I2C_END_DETECT_INT interrupt. 3 1 read-write - GPIO3_MCU_IE - input enable on sleep mode + BYTE_TRANS_DONE_INT_ENA + Write 1 to enable the I2C_END_DETECT_INT interrupt. 4 1 read-write - GPIO3_MCU_DRV - select drive strenth on sleep mode + ARBITRATION_LOST_INT_ENA + Write 1 to enable the I2C_ARBITRATION_LOST_INT interrupt. 5 - 2 - read-write - - - GPIO3_FUN_WPD - pull-down enable - 7 1 read-write - GPIO3_FUN_WPU - pull-up enable - 8 + MST_TXFIFO_UDF_INT_ENA + Write 1 to enable I2C_TRANS_COMPLETE_INT interrupt. + 6 1 read-write - GPIO3_FUN_IE - input enable - 9 + TRANS_COMPLETE_INT_ENA + Write 1 to enable the I2C_TRANS_COMPLETE_INT interrupt. + 7 1 read-write - GPIO3_FUN_DRV - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - 10 - 2 - read-write - - - GPIO3_MCU_SEL - 0:select function0, 1:select function1 ... - 12 - 3 - read-write - - - GPIO3_FILTER_EN - input filter enable - 15 + TIME_OUT_INT_ENA + Write 1 to enable the I2C_TIME_OUT_INT interrupt. + 8 1 read-write - - - - gpio4 - iomux control register for gpio4 - 0x14 - 0x20 - 0x00000800 - - GPIO4_MCU_OE - output enable on sleep mode - 0 + TRANS_START_INT_ENA + Write 1 to enable the I2C_TRANS_START_INT interrupt. + 9 1 read-write - GPIO4_SLP_SEL - io sleep mode enable. set 1 to enable sleep mode. - 1 + NACK_INT_ENA + Write 1 to enable I2C_SLAVE_STRETCH_INT interrupt. + 10 1 read-write - GPIO4_MCU_WPD - pull-down enable on sleep mode - 2 + TXFIFO_OVF_INT_ENA + Write 1 to enable I2C_TXFIFO_OVF_INT interrupt. + 11 1 read-write - GPIO4_MCU_WPU - pull-up enable on sleep mode - 3 + RXFIFO_UDF_INT_ENA + Write 1 to enable I2C_RXFIFO_UDF_INT interrupt. + 12 1 read-write - GPIO4_MCU_IE - input enable on sleep mode - 4 + SCL_ST_TO_INT_ENA + Write 1 to enable I2C_SCL_ST_TO_INT interrupt. + 13 1 read-write - GPIO4_MCU_DRV - select drive strenth on sleep mode - 5 - 2 - read-write - - - GPIO4_FUN_WPD - pull-down enable - 7 + SCL_MAIN_ST_TO_INT_ENA + Write 1 to enable I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 1 read-write - GPIO4_FUN_WPU - pull-up enable - 8 + DET_START_INT_ENA + Write 1 to enable I2C_DET_START_INT interrupt. + 15 1 read-write - GPIO4_FUN_IE - input enable - 9 + SLAVE_STRETCH_INT_ENA + Write 1 to enable I2C_SLAVE_STRETCH_INT interrupt. + 16 1 read-write - GPIO4_FUN_DRV - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - 10 - 2 - read-write - - - GPIO4_MCU_SEL - 0:select function0, 1:select function1 ... - 12 - 3 + GENERAL_CALL_INT_ENA + Write 1 to enable I2C_GENARAL_CALL_INT interrupt. + 17 + 1 read-write - GPIO4_FILTER_EN - input filter enable - 15 + SLAVE_ADDR_UNMATCH_INT_ENA + Write 1 to enable I2C_SLAVE_ADDR_UNMATCH_INT interrupt. + 18 1 read-write - gpio5 - iomux control register for gpio5 - 0x18 + INT_STATUS + Status of captured I2C communication events + 0x2C 0x20 - 0x00000800 - GPIO5_MCU_OE - output enable on sleep mode + RXFIFO_WM_INT_ST + The masked interrupt status status of I2C_RXFIFO_WM_INT interrupt. 0 1 - read-write + read-only - GPIO5_SLP_SEL - io sleep mode enable. set 1 to enable sleep mode. + TXFIFO_WM_INT_ST + The masked interrupt status status of I2C_TXFIFO_WM_INT interrupt. 1 1 - read-write + read-only - GPIO5_MCU_WPD - pull-down enable on sleep mode + RXFIFO_OVF_INT_ST + The masked interrupt status status of I2C_RXFIFO_OVF_INT interrupt. 2 1 - read-write + read-only - GPIO5_MCU_WPU - pull-up enable on sleep mode + END_DETECT_INT_ST + The masked interrupt status status of the I2C_END_DETECT_INT interrupt. 3 1 - read-write + read-only - GPIO5_MCU_IE - input enable on sleep mode + BYTE_TRANS_DONE_INT_ST + The masked interrupt status status of the I2C_END_DETECT_INT interrupt. 4 1 - read-write + read-only - GPIO5_MCU_DRV - select drive strenth on sleep mode + ARBITRATION_LOST_INT_ST + The masked interrupt status status of the I2C_ARBITRATION_LOST_INT interrupt. 5 - 2 - read-write + 1 + read-only + + + MST_TXFIFO_UDF_INT_ST + The masked interrupt status status of I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + read-only - GPIO5_FUN_WPD - pull-down enable + TRANS_COMPLETE_INT_ST + The masked interrupt status status of the I2C_TRANS_COMPLETE_INT interrupt. 7 1 - read-write + read-only - GPIO5_FUN_WPU - pull-up enable + TIME_OUT_INT_ST + The masked interrupt status status of the I2C_TIME_OUT_INT interrupt. 8 1 - read-write + read-only - GPIO5_FUN_IE - input enable + TRANS_START_INT_ST + The masked interrupt status status of the I2C_TRANS_START_INT interrupt. 9 1 - read-write + read-only - GPIO5_FUN_DRV - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA + NACK_INT_ST + The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt. 10 - 2 - read-write + 1 + read-only - GPIO5_MCU_SEL - 0:select function0, 1:select function1 ... + TXFIFO_OVF_INT_ST + The masked interrupt status status of I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + read-only + + + RXFIFO_UDF_INT_ST + The masked interrupt status status of I2C_RXFIFO_UDF_INT interrupt. 12 - 3 - read-write + 1 + read-only - GPIO5_FILTER_EN - input filter enable - 15 + SCL_ST_TO_INT_ST + The masked interrupt status status of I2C_SCL_ST_TO_INT interrupt. + 13 1 - read-write + read-only - - - - gpio6 - iomux control register for gpio6 - 0x1C - 0x20 - 0x00000800 - - GPIO6_MCU_OE - output enable on sleep mode - 0 + SCL_MAIN_ST_TO_INT_ST + The masked interrupt status status of I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 1 - read-write + read-only - GPIO6_SLP_SEL - io sleep mode enable. set 1 to enable sleep mode. - 1 + DET_START_INT_ST + The masked interrupt status status of I2C_DET_START_INT interrupt. + 15 1 - read-write + read-only - GPIO6_MCU_WPD - pull-down enable on sleep mode - 2 + SLAVE_STRETCH_INT_ST + The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt. + 16 1 - read-write + read-only - GPIO6_MCU_WPU - pull-up enable on sleep mode - 3 + GENERAL_CALL_INT_ST + The masked interrupt status status of I2C_GENARAL_CALL_INT interrupt. + 17 1 - read-write + read-only - GPIO6_MCU_IE - input enable on sleep mode - 4 + SLAVE_ADDR_UNMATCH_INT_ST + The masked interrupt status status of I2C_SLAVE_ADDR_UNMATCH_INT interrupt. + 18 1 - read-write + read-only + + + + SDA_HOLD + Configures the hold time after a negative SCL edge. + 0x30 + 0x20 + - GPIO6_MCU_DRV - select drive strenth on sleep mode - 5 - 2 + TIME + Configures the time to hold the data after the falling edge of SCL. +Measurement unit: i2c_sclk + 0 + 9 read-write + + + + SDA_SAMPLE + Configures the sample time after a positive SCL edge. + 0x34 + 0x20 + - GPIO6_FUN_WPD - pull-down enable - 7 - 1 + TIME + Configures the sample time after a positive SCL edge. +Measurement unit: i2c_sclk + 0 + 9 read-write + + + + SCL_HIGH_PERIOD + Configures the high level width of SCL + 0x38 + 0x20 + - GPIO6_FUN_WPU - pull-up enable - 8 - 1 + SCL_HIGH_PERIOD + Configures for how long SCL remains high in master mode. +Measurement unit: i2c_sclk + 0 + 9 read-write - GPIO6_FUN_IE - input enable + SCL_WAIT_HIGH_PERIOD + Configures the SCL_FSM's waiting period for SCL high level in master mode. +Measurement unit: i2c_sclk 9 - 1 + 7 read-write + + + + SCL_START_HOLD + Configures the delay between the SDA and SCL negative edge for a start condition + 0x40 + 0x20 + 0x00000008 + - GPIO6_FUN_DRV - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - 10 - 2 + TIME + Configures the time between the falling edge of SDA and the falling edge of SCL for a START condition. +Measurement unit: i2c_sclk. + 0 + 9 read-write + + + + SCL_RSTART_SETUP + Configures the delay between the positive edge of SCL and the negative edge of SDA + 0x44 + 0x20 + 0x00000008 + - GPIO6_MCU_SEL - 0:select function0, 1:select function1 ... - 12 - 3 + TIME + Configures the time between the positive edge of SCL and the negative edge of SDA for a RESTART condition. +Measurement unit: i2c_sclk + 0 + 9 read-write + + + + SCL_STOP_HOLD + Configures the delay after the SCL clock edge for a stop condition + 0x48 + 0x20 + 0x00000008 + - GPIO6_FILTER_EN - input filter enable - 15 - 1 + TIME + Configures the delay after the STOP condition. +Measurement unit: i2c_sclk + 0 + 9 read-write - gpio7 - iomux control register for gpio7 - 0x20 + SCL_STOP_SETUP + Configures the delay between the SDA and SCL rising edge for a stop condition. +Measurement unit: i2c_sclk + 0x4C 0x20 - 0x00000800 + 0x00000008 - GPIO7_MCU_OE - output enable on sleep mode + TIME + Configures the time between the rising edge of SCL and the rising edge of SDA. +Measurement unit: i2c_sclk 0 - 1 + 9 read-write + + + + FILTER_CFG + SCL and SDA filter configuration register + 0x50 + 0x20 + 0x00000300 + - GPIO7_SLP_SEL - io sleep mode enable. set 1 to enable sleep mode. - 1 - 1 + SCL_FILTER_THRES + Configures the threshold pulse width to be filtered on SCL. When a pulse on the SCL input has smaller width than this register value, the I2C controller will ignore that pulse. +Measurement unit: i2c_sclk + 0 + 4 read-write - GPIO7_MCU_WPD - pull-down enable on sleep mode - 2 - 1 + SDA_FILTER_THRES + Configures the threshold pulse width to be filtered on SDA. When a pulse on the SDA input has smaller width than this register value, the I2C controller will ignore that pulse. +Measurement unit: i2c_sclk + 4 + 4 read-write - GPIO7_MCU_WPU - pull-up enable on sleep mode - 3 + SCL_FILTER_EN + Configures to enable the filter function for SCL. + 8 1 read-write - GPIO7_MCU_IE - input enable on sleep mode - 4 + SDA_FILTER_EN + Configures to enable the filter function for SDA. + 9 1 read-write + + + + CLK_CONF + I2C CLK configuration register + 0x54 + 0x20 + 0x00200000 + - GPIO7_MCU_DRV - select drive strenth on sleep mode - 5 - 2 + SCLK_DIV_NUM + the integral part of the fractional divisor for i2c module + 0 + 8 read-write - GPIO7_FUN_WPD - pull-down enable - 7 - 1 + SCLK_DIV_A + the numerator of the fractional part of the fractional divisor for i2c module + 8 + 6 read-write - GPIO7_FUN_WPU - pull-up enable - 8 - 1 + SCLK_DIV_B + the denominator of the fractional part of the fractional divisor for i2c module + 14 + 6 read-write - GPIO7_FUN_IE - input enable - 9 + SCLK_SEL + The clock selection for i2c module:0-XTAL,1-CLK_8MHz. + 20 1 read-write - GPIO7_FUN_DRV - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - 10 - 2 + SCLK_ACTIVE + The clock switch for i2c module + 21 + 1 read-write + + + + COMD0 + I2C command register 0 + 0x58 + 0x20 + - GPIO7_MCU_SEL - 0:select function0, 1:select function1 ... - 12 - 3 + COMMAND0 + Configures command 0. It consists of three parts: +op_code is the command, +0: RSTART, +1: WRITE, +2: READ, +3: STOP, +4: END. + +Byte_num represents the number of bytes that need to be sent or received. +ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more information. + 0 + 14 read-write - GPIO7_FILTER_EN - input filter enable - 15 + COMMAND0_DONE + Represents whether command 0 is done in I2C Master mode. +0: Not done + +1: Done + 31 1 read-write - gpio8 - iomux control register for gpio8 - 0x24 + COMD1 + I2C command register 1 + 0x5C 0x20 - 0x00000800 - GPIO8_MCU_OE - output enable on sleep mode + COMMAND1 + Configures command 1. See details in I2C_CMD0_REG[13:0]. 0 - 1 - read-write - - - GPIO8_SLP_SEL - io sleep mode enable. set 1 to enable sleep mode. - 1 - 1 + 14 read-write - GPIO8_MCU_WPD - pull-down enable on sleep mode - 2 + COMMAND1_DONE + Represents whether command 1 is done in I2C Master mode. +0: Not done + +1: Done + 31 1 read-write + + + + COMD2 + I2C command register 2 + 0x60 + 0x20 + - GPIO8_MCU_WPU - pull-up enable on sleep mode - 3 - 1 + COMMAND2 + Configures command 2. See details in I2C_CMD0_REG[13:0]. + 0 + 14 read-write - GPIO8_MCU_IE - input enable on sleep mode - 4 + COMMAND2_DONE + Represents whether command 2 is done in I2C Master mode. +0: Not done + +1: Done + 31 1 read-write + + + + COMD3 + I2C command register 3 + 0x64 + 0x20 + - GPIO8_MCU_DRV - select drive strenth on sleep mode - 5 - 2 + COMMAND3 + Configures command 3. See details in I2C_CMD0_REG[13:0]. + 0 + 14 read-write - GPIO8_FUN_WPD - pull-down enable - 7 + COMMAND3_DONE + Represents whether command 3 is done in I2C Master mode. +0: Not done + +1: Done + 31 1 read-write + + + + COMD4 + I2C command register 4 + 0x68 + 0x20 + - GPIO8_FUN_WPU - pull-up enable - 8 - 1 + COMMAND4 + Configures command 4. See details in I2C_CMD0_REG[13:0]. + 0 + 14 read-write - GPIO8_FUN_IE - input enable - 9 + COMMAND4_DONE + Represents whether command 4 is done in I2C Master mode. +0: Not done + +1: Done + 31 1 read-write + + + + COMD5 + I2C command register 5 + 0x6C + 0x20 + - GPIO8_FUN_DRV - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - 10 - 2 - read-write - - - GPIO8_MCU_SEL - 0:select function0, 1:select function1 ... - 12 - 3 + COMMAND5 + Configures command 5. See details in I2C_CMD0_REG[13:0]. + 0 + 14 read-write - GPIO8_FILTER_EN - input filter enable - 15 + COMMAND5_DONE + Represents whether command 5 is done in I2C Master mode. +0: Not done + +1: Done + 31 1 read-write - gpio9 - iomux control register for gpio9 - 0x28 + COMD6 + I2C command register 6 + 0x70 0x20 - 0x00000800 - GPIO9_MCU_OE - output enable on sleep mode + COMMAND6 + Configures command 6. See details in I2C_CMD0_REG[13:0]. 0 - 1 + 14 read-write - GPIO9_SLP_SEL - io sleep mode enable. set 1 to enable sleep mode. - 1 + COMMAND6_DONE + Represents whether command 6 is done in I2C Master mode. +0: Not done + +1: Done + 31 1 read-write + + + + COMD7 + I2C command register 7 + 0x74 + 0x20 + - GPIO9_MCU_WPD - pull-down enable on sleep mode - 2 - 1 + COMMAND7 + Configures command 7. See details in I2C_CMD0_REG[13:0]. + 0 + 14 read-write - GPIO9_MCU_WPU - pull-up enable on sleep mode - 3 + COMMAND7_DONE + Represents whether command 7 is done in I2C Master mode. +0: Not done + +1: Done + 31 1 read-write + + + + SCL_ST_TIME_OUT + SCL status time out register + 0x78 + 0x20 + 0x00000010 + - GPIO9_MCU_IE - input enable on sleep mode - 4 - 1 + SCL_ST_TO_I2C + Configures the threshold value of SCL_FSM state unchanged period. It should be no more than 23. +Measurement unit: i2c_sclk + 0 + 5 read-write + + + + SCL_MAIN_ST_TIME_OUT + SCL main status time out register + 0x7C + 0x20 + 0x00000010 + - GPIO9_MCU_DRV - select drive strenth on sleep mode - 5 - 2 + SCL_MAIN_ST_TO_I2C + Configures the threshold value of SCL_MAIN_FSM state unchanged period.nIt should be no more than 23. +Measurement unit: i2c_sclk + 0 + 5 read-write + + + + SCL_SP_CONF + Power configuration register + 0x80 + 0x20 + - GPIO9_FUN_WPD - pull-down enable - 7 + SCL_RST_SLV_EN + Configures to send out SCL pulses when I2C master is IDLE. The number of pulses equals to reg_scl_rst_slv_num[4:0]. + 0 1 read-write - GPIO9_FUN_WPU - pull-up enable - 8 - 1 + SCL_RST_SLV_NUM + Configure the pulses of SCL generated in I2C master mode. +Valid when reg_scl_rst_slv_en is 1. +Measurement unit: i2c_sclk + 1 + 5 read-write - GPIO9_FUN_IE - input enable - 9 + SCL_PD_EN + Configures to power down the I2C output SCL line. +0: Not power down. + +1: Power down. +Valid only when reg_scl_force_out is 1. + 6 1 read-write - GPIO9_FUN_DRV - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - 10 - 2 - read-write - - - GPIO9_MCU_SEL - 0:select function0, 1:select function1 ... - 12 - 3 - read-write - - - GPIO9_FILTER_EN - input filter enable - 15 + SDA_PD_EN + Configures to power down the I2C output SDA line. +0: Not power down. + +1: Power down. +Valid only when reg_sda_force_out is 1. + 7 1 read-write - gpio10 - iomux control register for gpio10 - 0x2C + SCL_STRETCH_CONF + Set SCL stretch of I2C slave + 0x84 0x20 - 0x00000800 - GPIO10_MCU_OE - output enable on sleep mode + STRETCH_PROTECT_NUM + Configures the time period to release the SCL line from stretching to avoid timing violation. Usually it should be larger than the SDA setup time. +Measurement unit: i2c_sclk 0 - 1 + 10 read-write - GPIO10_SLP_SEL - io sleep mode enable. set 1 to enable sleep mode. - 1 + SLAVE_SCL_STRETCH_EN + Configures to enable slave SCL stretch function. +0: Disable + +1: Enable +The SCL output line will be stretched low when reg_slave_scl_stretch_en is 1 and stretch event happens. The stretch cause can be seen in reg_stretch_cause. + 10 1 read-write - GPIO10_MCU_WPD - pull-down enable on sleep mode - 2 + SLAVE_SCL_STRETCH_CLR + Configures to clear the I2C slave SCL stretch function. +0: No effect + +1: Clear + 11 1 - read-write + write-only - GPIO10_MCU_WPU - pull-up enable on sleep mode - 3 + SLAVE_BYTE_ACK_CTL_EN + Configures to enable the function for slave to control ACK level. +0: Disable + +1: Enable + 12 1 read-write - GPIO10_MCU_IE - input enable on sleep mode - 4 + SLAVE_BYTE_ACK_LVL + Set the ACK level when slave controlling ACK level function enables. +0: Low level + +1: High level + 13 1 read-write + + + + DATE + Version register + 0xF8 + 0x20 + 0x02201172 + - GPIO10_MCU_DRV - select drive strenth on sleep mode - 5 - 2 + DATE + Version control register. + 0 + 32 read-write + + + + TXFIFO_START_ADDR + I2C TXFIFO base address register + 0x100 + 0x20 + - GPIO10_FUN_WPD - pull-down enable - 7 - 1 - read-write + TXFIFO_START_ADDR + Represents the I2C txfifo first address. + 0 + 32 + read-only + + + + RXFIFO_START_ADDR + I2C RXFIFO base address register + 0x180 + 0x20 + - GPIO10_FUN_WPU - pull-up enable - 8 - 1 - read-write + RXFIFO_START_ADDR + Represents the I2C rxfifo first address. + 0 + 32 + read-only + + + + + + I2C1 + I2C (Inter-Integrated Circuit) Controller 1 + 0x500C5000 + + I2C1 + 45 + + + + I2S0 + I2S (Inter-IC Sound) Controller 0 + I2S + 0x500C6000 + + 0x0 + 0x60 + registers + + + I2S0 + 27 + + + + INT_RAW + I2S interrupt raw register, valid in level. + 0xC + 0x20 + - GPIO10_FUN_IE - input enable - 9 + RX_DONE_INT_RAW + The raw interrupt status bit for the i2s_rx_done_int interrupt + 0 1 - read-write + read-only - GPIO10_FUN_DRV - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - 10 - 2 - read-write + TX_DONE_INT_RAW + The raw interrupt status bit for the i2s_tx_done_int interrupt + 1 + 1 + read-only - GPIO10_MCU_SEL - 0:select function0, 1:select function1 ... - 12 - 3 - read-write + RX_HUNG_INT_RAW + The raw interrupt status bit for the i2s_rx_hung_int interrupt + 2 + 1 + read-only - GPIO10_FILTER_EN - input filter enable - 15 + TX_HUNG_INT_RAW + The raw interrupt status bit for the i2s_tx_hung_int interrupt + 3 1 - read-write + read-only - gpio11 - iomux control register for gpio11 - 0x30 + INT_ST + I2S interrupt status register. + 0x10 0x20 - 0x00000800 - GPIO11_MCU_OE - output enable on sleep mode + RX_DONE_INT_ST + The masked interrupt status bit for the i2s_rx_done_int interrupt 0 1 - read-write + read-only - GPIO11_SLP_SEL - io sleep mode enable. set 1 to enable sleep mode. + TX_DONE_INT_ST + The masked interrupt status bit for the i2s_tx_done_int interrupt 1 1 - read-write + read-only - GPIO11_MCU_WPD - pull-down enable on sleep mode + RX_HUNG_INT_ST + The masked interrupt status bit for the i2s_rx_hung_int interrupt 2 1 - read-write + read-only - GPIO11_MCU_WPU - pull-up enable on sleep mode + TX_HUNG_INT_ST + The masked interrupt status bit for the i2s_tx_hung_int interrupt 3 1 - read-write + read-only + + + + INT_ENA + I2S interrupt enable register. + 0x14 + 0x20 + - GPIO11_MCU_IE - input enable on sleep mode - 4 + RX_DONE_INT_ENA + The interrupt enable bit for the i2s_rx_done_int interrupt + 0 1 read-write - GPIO11_MCU_DRV - select drive strenth on sleep mode - 5 - 2 + TX_DONE_INT_ENA + The interrupt enable bit for the i2s_tx_done_int interrupt + 1 + 1 read-write - GPIO11_FUN_WPD - pull-down enable - 7 + RX_HUNG_INT_ENA + The interrupt enable bit for the i2s_rx_hung_int interrupt + 2 1 read-write - GPIO11_FUN_WPU - pull-up enable - 8 + TX_HUNG_INT_ENA + The interrupt enable bit for the i2s_tx_hung_int interrupt + 3 1 read-write + + + + INT_CLR + I2S interrupt clear register. + 0x18 + 0x20 + - GPIO11_FUN_IE - input enable - 9 + RX_DONE_INT_CLR + Set this bit to clear the i2s_rx_done_int interrupt + 0 1 - read-write + write-only - GPIO11_FUN_DRV - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - 10 - 2 - read-write + TX_DONE_INT_CLR + Set this bit to clear the i2s_tx_done_int interrupt + 1 + 1 + write-only - GPIO11_MCU_SEL - 0:select function0, 1:select function1 ... - 12 - 3 - read-write + RX_HUNG_INT_CLR + Set this bit to clear the i2s_rx_hung_int interrupt + 2 + 1 + write-only - GPIO11_FILTER_EN - input filter enable - 15 + TX_HUNG_INT_CLR + Set this bit to clear the i2s_tx_hung_int interrupt + 3 1 - read-write + write-only - gpio12 - iomux control register for gpio12 - 0x34 + RX_CONF + I2S RX configure register + 0x20 0x20 - 0x00000800 + 0x00C0B600 - GPIO12_MCU_OE - output enable on sleep mode + RX_RESET + Set this bit to reset receiver 0 1 - read-write + write-only - GPIO12_SLP_SEL - io sleep mode enable. set 1 to enable sleep mode. + RX_FIFO_RESET + Set this bit to reset Rx AFIFO 1 1 - read-write + write-only - GPIO12_MCU_WPD - pull-down enable on sleep mode + RX_START + Set this bit to start receiving data 2 1 read-write - GPIO12_MCU_WPU - pull-up enable on sleep mode + RX_SLAVE_MOD + Set this bit to enable slave receiver mode 3 1 read-write - GPIO12_MCU_IE - input enable on sleep mode + RX_STOP_MODE + 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full. 4 - 1 + 2 read-write - GPIO12_MCU_DRV - select drive strenth on sleep mode - 5 - 2 + RX_MONO + Set this bit to enable receiver in mono mode + 6 + 1 read-write - GPIO12_FUN_WPD - pull-down enable + RX_BIG_ENDIAN + I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value. 7 1 read-write - GPIO12_FUN_WPU - pull-up enable + RX_UPDATE + Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done. 8 1 read-write - GPIO12_FUN_IE - input enable + RX_MONO_FST_VLD + 1: The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is valid in I2S RX mono mode. 9 1 read-write - GPIO12_FUN_DRV - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA + RX_PCM_CONF + I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & 10 2 read-write - GPIO12_MCU_SEL - 0:select function0, 1:select function1 ... + RX_PCM_BYPASS + Set this bit to bypass Compress/Decompress module for received data. 12 - 3 - read-write - - - GPIO12_FILTER_EN - input filter enable - 15 - 1 - read-write - - - - - gpio13 - iomux control register for gpio13 - 0x38 - 0x20 - 0x00000800 - - - GPIO13_MCU_OE - output enable on sleep mode - 0 1 read-write - GPIO13_SLP_SEL - io sleep mode enable. set 1 to enable sleep mode. - 1 + RX_MSB_SHIFT + Set this bit to enable receiver in Phillips standard mode + 13 1 read-write - GPIO13_MCU_WPD - pull-down enable on sleep mode - 2 + RX_LEFT_ALIGN + 1: I2S RX left alignment mode. 0: I2S RX right alignment mode. + 15 1 read-write - GPIO13_MCU_WPU - pull-up enable on sleep mode - 3 + RX_24_FILL_EN + 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits. + 16 1 read-write - GPIO13_MCU_IE - input enable on sleep mode - 4 + RX_WS_IDLE_POL + 0: WS should be 0 when receiving left channel data, and WS is 1in right channel. 1: WS should be 1 when receiving left channel data, and WS is 0in right channel. + 17 1 read-write - GPIO13_MCU_DRV - select drive strenth on sleep mode - 5 - 2 - read-write - - - GPIO13_FUN_WPD - pull-down enable - 7 + RX_BIT_ORDER + I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first. + 18 1 read-write - GPIO13_FUN_WPU - pull-up enable - 8 + RX_TDM_EN + 1: Enable I2S TDM Rx mode . 0: Disable. + 19 1 read-write - GPIO13_FUN_IE - input enable - 9 + RX_PDM_EN + 1: Enable I2S PDM Rx mode . 0: Disable. + 20 1 read-write - GPIO13_FUN_DRV - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - 10 - 2 - read-write - - - GPIO13_MCU_SEL - 0:select function0, 1:select function1 ... - 12 - 3 - read-write - - - GPIO13_FILTER_EN - input filter enable - 15 - 1 + RX_BCK_DIV_NUM + Bit clock configuration bits in receiver mode. + 21 + 6 read-write - gpio14 - iomux control register for gpio14 - 0x3C + TX_CONF + I2S TX configure register + 0x24 0x20 - 0x00000800 + 0x00C0F210 - GPIO14_MCU_OE - output enable on sleep mode + TX_RESET + Set this bit to reset transmitter 0 1 - read-write + write-only - GPIO14_SLP_SEL - io sleep mode enable. set 1 to enable sleep mode. + TX_FIFO_RESET + Set this bit to reset Tx AFIFO 1 1 - read-write + write-only - GPIO14_MCU_WPD - pull-down enable on sleep mode + TX_START + Set this bit to start transmitting data 2 1 read-write - GPIO14_MCU_WPU - pull-up enable on sleep mode + TX_SLAVE_MOD + Set this bit to enable slave transmitter mode 3 1 read-write - GPIO14_MCU_IE - input enable on sleep mode + TX_STOP_EN + Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy 4 1 read-write - GPIO14_MCU_DRV - select drive strenth on sleep mode + TX_CHAN_EQUAL + 1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode. 5 - 2 + 1 + read-write + + + TX_MONO + Set this bit to enable transmitter in mono mode + 6 + 1 read-write - GPIO14_FUN_WPD - pull-down enable + TX_BIG_ENDIAN + I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr value. 7 1 read-write - GPIO14_FUN_WPU - pull-up enable + TX_UPDATE + Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done. 8 1 read-write - GPIO14_FUN_IE - input enable + TX_MONO_FST_VLD + 1: The first channel data value is valid in I2S TX mono mode. 0: The second channel data value is valid in I2S TX mono mode. 9 1 read-write - GPIO14_FUN_DRV - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA + TX_PCM_CONF + I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & 10 2 read-write - GPIO14_MCU_SEL - 0:select function0, 1:select function1 ... + TX_PCM_BYPASS + Set this bit to bypass Compress/Decompress module for transmitted data. 12 - 3 - read-write - - - GPIO14_FILTER_EN - input filter enable - 15 1 read-write - - - - gpio15 - iomux control register for gpio15 - 0x40 - 0x20 - 0x00000800 - - GPIO15_MCU_OE - output enable on sleep mode - 0 + TX_MSB_SHIFT + Set this bit to enable transmitter in Phillips standard mode + 13 1 read-write - GPIO15_SLP_SEL - io sleep mode enable. set 1 to enable sleep mode. - 1 + TX_BCK_NO_DLY + 1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to generate pos/neg edge in master mode. + 14 1 read-write - GPIO15_MCU_WPD - pull-down enable on sleep mode - 2 + TX_LEFT_ALIGN + 1: I2S TX left alignment mode. 0: I2S TX right alignment mode. + 15 1 read-write - GPIO15_MCU_WPU - pull-up enable on sleep mode - 3 + TX_24_FILL_EN + 1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode + 16 1 read-write - GPIO15_MCU_IE - input enable on sleep mode - 4 + TX_WS_IDLE_POL + 0: WS should be 0 when sending left channel data, and WS is 1in right channel. 1: WS should be 1 when sending left channel data, and WS is 0in right channel. + 17 1 read-write - GPIO15_MCU_DRV - select drive strenth on sleep mode - 5 - 2 - read-write - - - GPIO15_FUN_WPD - pull-down enable - 7 + TX_BIT_ORDER + I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is sent first. + 18 1 read-write - GPIO15_FUN_WPU - pull-up enable - 8 + TX_TDM_EN + 1: Enable I2S TDM Tx mode . 0: Disable. + 19 1 read-write - GPIO15_FUN_IE - input enable - 9 + TX_PDM_EN + 1: Enable I2S PDM Tx mode . 0: Disable. + 20 1 read-write - GPIO15_FUN_DRV - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - 10 - 2 + TX_BCK_DIV_NUM + Bit clock configuration bits in transmitter mode. + 21 + 6 read-write - GPIO15_MCU_SEL - 0:select function0, 1:select function1 ... - 12 + TX_CHAN_MOD + I2S transmitter channel mode configuration bits. + 27 3 read-write - GPIO15_FILTER_EN - input filter enable - 15 + SIG_LOOPBACK + Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals. + 30 1 read-write - gpio16 - iomux control register for gpio16 - 0x44 + RX_CONF1 + I2S RX configure register 1 + 0x28 0x20 - 0x00000800 + 0x787BC000 - GPIO16_MCU_OE - output enable on sleep mode + RX_TDM_WS_WIDTH + The width of rx_ws_out at idle level in TDM mode is (I2S_RX_TDM_WS_WIDTH[8:0] +1) * T_bck 0 - 1 - read-write - - - GPIO16_SLP_SEL - io sleep mode enable. set 1 to enable sleep mode. - 1 - 1 - read-write - - - GPIO16_MCU_WPD - pull-down enable on sleep mode - 2 - 1 - read-write - - - GPIO16_MCU_WPU - pull-up enable on sleep mode - 3 - 1 - read-write - - - GPIO16_MCU_IE - input enable on sleep mode - 4 - 1 + 9 read-write - GPIO16_MCU_DRV - select drive strenth on sleep mode - 5 - 2 + RX_BITS_MOD + Set the bits to configure the valid data bit length of I2S receiver channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode. + 14 + 5 read-write - GPIO16_FUN_WPD - pull-down enable - 7 - 1 + RX_HALF_SAMPLE_BITS + I2S Rx half sample bits -1. + 19 + 8 read-write - GPIO16_FUN_WPU - pull-up enable - 8 - 1 + RX_TDM_CHAN_BITS + The Rx bit number for each channel minus 1in TDM mode. + 27 + 5 read-write + + + + TX_CONF1 + I2S TX configure register 1 + 0x2C + 0x20 + 0x787BC000 + - GPIO16_FUN_IE - input enable - 9 - 1 + TX_TDM_WS_WIDTH + The width of tx_ws_out at idle level in TDM mode is (I2S_TX_TDM_WS_WIDTH[8:0] +1) * T_bck + 0 + 9 read-write - GPIO16_FUN_DRV - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - 10 - 2 + TX_BITS_MOD + Set the bits to configure the valid data bit length of I2S transmitter channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode. + 14 + 5 read-write - GPIO16_MCU_SEL - 0:select function0, 1:select function1 ... - 12 - 3 + TX_HALF_SAMPLE_BITS + I2S Tx half sample bits -1. + 19 + 8 read-write - GPIO16_FILTER_EN - input filter enable - 15 - 1 + TX_TDM_CHAN_BITS + The Tx bit number for each channel minus 1in TDM mode. + 27 + 5 read-write - gpio17 - iomux control register for gpio17 - 0x48 + TX_PCM2PDM_CONF + I2S TX PCM2PDM configuration register + 0x40 0x20 - 0x00000800 + 0x004AA004 - GPIO17_MCU_OE - output enable on sleep mode + TX_PDM_HP_BYPASS + I2S TX PDM bypass hp filter or not. The option has been removed. 0 1 read-write - GPIO17_SLP_SEL - io sleep mode enable. set 1 to enable sleep mode. + TX_PDM_SINC_OSR2 + I2S TX PDM OSR2 value 1 - 1 + 4 read-write - GPIO17_MCU_WPD - pull-down enable on sleep mode - 2 - 1 + TX_PDM_PRESCALE + I2S TX PDM prescale for sigmadelta + 5 + 8 read-write - GPIO17_MCU_WPU - pull-up enable on sleep mode - 3 - 1 + TX_PDM_HP_IN_SHIFT + I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + 13 + 2 read-write - GPIO17_MCU_IE - input enable on sleep mode - 4 - 1 + TX_PDM_LP_IN_SHIFT + I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + 15 + 2 read-write - GPIO17_MCU_DRV - select drive strenth on sleep mode - 5 + TX_PDM_SINC_IN_SHIFT + I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + 17 2 read-write - GPIO17_FUN_WPD - pull-down enable - 7 - 1 + TX_PDM_SIGMADELTA_IN_SHIFT + I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + 19 + 2 read-write - GPIO17_FUN_WPU - pull-up enable - 8 + TX_PDM_SIGMADELTA_DITHER2 + I2S TX PDM sigmadelta dither2 value + 21 1 read-write - GPIO17_FUN_IE - input enable - 9 + TX_PDM_SIGMADELTA_DITHER + I2S TX PDM sigmadelta dither value + 22 1 read-write - GPIO17_FUN_DRV - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - 10 - 2 + TX_PDM_DAC_2OUT_EN + I2S TX PDM dac mode enable + 23 + 1 read-write - GPIO17_MCU_SEL - 0:select function0, 1:select function1 ... - 12 - 3 + TX_PDM_DAC_MODE_EN + I2S TX PDM dac 2channel enable + 24 + 1 read-write - GPIO17_FILTER_EN - input filter enable - 15 + PCM2PDM_CONV_EN + I2S TX PDM Converter enable + 25 1 read-write - gpio18 - iomux control register for gpio18 - 0x4C + TX_PCM2PDM_CONF1 + I2S TX PCM2PDM configuration register + 0x44 0x20 - 0x00000800 + 0x03F783C0 - GPIO18_MCU_OE - output enable on sleep mode + TX_PDM_FP + I2S TX PDM Fp 0 - 1 + 10 read-write - GPIO18_SLP_SEL - io sleep mode enable. set 1 to enable sleep mode. - 1 - 1 + TX_PDM_FS + I2S TX PDM Fs + 10 + 10 read-write - GPIO18_MCU_WPD - pull-down enable on sleep mode - 2 - 1 + TX_IIR_HP_MULT12_5 + The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + I2S_TX_IIR_HP_MULT12_5[2:0]) + 20 + 3 read-write - GPIO18_MCU_WPU - pull-up enable on sleep mode - 3 - 1 + TX_IIR_HP_MULT12_0 + The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + I2S_TX_IIR_HP_MULT12_0[2:0]) + 23 + 3 read-write + + + + RX_PDM2PCM_CONF + I2S RX configure register + 0x48 + 0x20 + 0xF8200000 + - GPIO18_MCU_IE - input enable on sleep mode - 4 + RX_PDM2PCM_EN + 1: Enable PDM2PCM RX mode. 0: DIsable. + 19 1 read-write - GPIO18_MCU_DRV - select drive strenth on sleep mode - 5 - 2 - read-write - - - GPIO18_FUN_WPD - pull-down enable - 7 + RX_PDM_SINC_DSR_16_EN + Configure the down sampling rate of PDM RX filter group1 module. 1: The down sampling rate is 128. 0: down sampling rate is 64. + 20 1 read-write - GPIO18_FUN_WPU - pull-up enable - 8 - 1 + RX_PDM2PCM_AMPLIFY_NUM + Configure PDM RX amplify number. + 21 + 4 read-write - GPIO18_FUN_IE - input enable - 9 + RX_PDM_HP_BYPASS + I2S PDM RX bypass hp filter or not. + 25 1 read-write - GPIO18_FUN_DRV - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - 10 - 2 - read-write - - - GPIO18_MCU_SEL - 0:select function0, 1:select function1 ... - 12 + RX_IIR_HP_MULT12_5 + The fourth parameter of PDM RX IIR_HP filter stage 2 is (504 + LP_I2S_RX_IIR_HP_MULT12_5[2:0]) + 26 3 read-write - GPIO18_FILTER_EN - input filter enable - 15 - 1 + RX_IIR_HP_MULT12_0 + The fourth parameter of PDM RX IIR_HP filter stage 1 is (504 + LP_I2S_RX_IIR_HP_MULT12_0[2:0]) + 29 + 3 read-write - gpio19 - iomux control register for gpio19 + RX_TDM_CTRL + I2S TX TDM mode control register 0x50 0x20 - 0x00000800 + 0x0000FFFF - GPIO19_MCU_OE - output enable on sleep mode + RX_TDM_PDM_CHAN0_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 0. 0: Disable, just input 0 in this channel. 0 1 read-write - GPIO19_SLP_SEL - io sleep mode enable. set 1 to enable sleep mode. + RX_TDM_PDM_CHAN1_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 1. 0: Disable, just input 0 in this channel. 1 1 read-write - GPIO19_MCU_WPD - pull-down enable on sleep mode + RX_TDM_PDM_CHAN2_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 2. 0: Disable, just input 0 in this channel. 2 1 read-write - GPIO19_MCU_WPU - pull-up enable on sleep mode + RX_TDM_PDM_CHAN3_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 3. 0: Disable, just input 0 in this channel. 3 1 read-write - GPIO19_MCU_IE - input enable on sleep mode + RX_TDM_PDM_CHAN4_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 4. 0: Disable, just input 0 in this channel. 4 1 read-write - GPIO19_MCU_DRV - select drive strenth on sleep mode + RX_TDM_PDM_CHAN5_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 5. 0: Disable, just input 0 in this channel. 5 - 2 + 1 read-write - GPIO19_FUN_WPD - pull-down enable + RX_TDM_PDM_CHAN6_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 6. 0: Disable, just input 0 in this channel. + 6 + 1 + read-write + + + RX_TDM_PDM_CHAN7_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 7. 0: Disable, just input 0 in this channel. 7 1 read-write - GPIO19_FUN_WPU - pull-up enable + RX_TDM_CHAN8_EN + 1: Enable the valid data input of I2S RX TDM channel 8. 0: Disable, just input 0 in this channel. 8 1 read-write - GPIO19_FUN_IE - input enable + RX_TDM_CHAN9_EN + 1: Enable the valid data input of I2S RX TDM channel 9. 0: Disable, just input 0 in this channel. 9 1 read-write - GPIO19_FUN_DRV - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA + RX_TDM_CHAN10_EN + 1: Enable the valid data input of I2S RX TDM channel 10. 0: Disable, just input 0 in this channel. 10 - 2 + 1 + read-write + + + RX_TDM_CHAN11_EN + 1: Enable the valid data input of I2S RX TDM channel 11. 0: Disable, just input 0 in this channel. + 11 + 1 read-write - GPIO19_MCU_SEL - 0:select function0, 1:select function1 ... + RX_TDM_CHAN12_EN + 1: Enable the valid data input of I2S RX TDM channel 12. 0: Disable, just input 0 in this channel. 12 - 3 + 1 + read-write + + + RX_TDM_CHAN13_EN + 1: Enable the valid data input of I2S RX TDM channel 13. 0: Disable, just input 0 in this channel. + 13 + 1 + read-write + + + RX_TDM_CHAN14_EN + 1: Enable the valid data input of I2S RX TDM channel 14. 0: Disable, just input 0 in this channel. + 14 + 1 read-write - GPIO19_FILTER_EN - input filter enable + RX_TDM_CHAN15_EN + 1: Enable the valid data input of I2S RX TDM channel 15. 0: Disable, just input 0 in this channel. 15 1 read-write + + RX_TDM_TOT_CHAN_NUM + The total channel number of I2S TX TDM mode. + 16 + 4 + read-write + - gpio20 - iomux control register for gpio20 + TX_TDM_CTRL + I2S TX TDM mode control register 0x54 0x20 - 0x00000800 + 0x0000FFFF - GPIO20_MCU_OE - output enable on sleep mode + TX_TDM_CHAN0_EN + 1: Enable the valid data output of I2S TX TDM channel 0. 0: Disable, just output 0 in this channel. 0 1 read-write - GPIO20_SLP_SEL - io sleep mode enable. set 1 to enable sleep mode. + TX_TDM_CHAN1_EN + 1: Enable the valid data output of I2S TX TDM channel 1. 0: Disable, just output 0 in this channel. 1 1 read-write - GPIO20_MCU_WPD - pull-down enable on sleep mode + TX_TDM_CHAN2_EN + 1: Enable the valid data output of I2S TX TDM channel 2. 0: Disable, just output 0 in this channel. 2 1 read-write - GPIO20_MCU_WPU - pull-up enable on sleep mode + TX_TDM_CHAN3_EN + 1: Enable the valid data output of I2S TX TDM channel 3. 0: Disable, just output 0 in this channel. 3 1 read-write - GPIO20_MCU_IE - input enable on sleep mode + TX_TDM_CHAN4_EN + 1: Enable the valid data output of I2S TX TDM channel 4. 0: Disable, just output 0 in this channel. 4 1 read-write - GPIO20_MCU_DRV - select drive strenth on sleep mode + TX_TDM_CHAN5_EN + 1: Enable the valid data output of I2S TX TDM channel 5. 0: Disable, just output 0 in this channel. 5 - 2 + 1 + read-write + + + TX_TDM_CHAN6_EN + 1: Enable the valid data output of I2S TX TDM channel 6. 0: Disable, just output 0 in this channel. + 6 + 1 read-write - GPIO20_FUN_WPD - pull-down enable + TX_TDM_CHAN7_EN + 1: Enable the valid data output of I2S TX TDM channel 7. 0: Disable, just output 0 in this channel. 7 1 read-write - GPIO20_FUN_WPU - pull-up enable + TX_TDM_CHAN8_EN + 1: Enable the valid data output of I2S TX TDM channel 8. 0: Disable, just output 0 in this channel. 8 1 read-write - GPIO20_FUN_IE - input enable + TX_TDM_CHAN9_EN + 1: Enable the valid data output of I2S TX TDM channel 9. 0: Disable, just output 0 in this channel. 9 1 read-write - GPIO20_FUN_DRV - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA + TX_TDM_CHAN10_EN + 1: Enable the valid data output of I2S TX TDM channel 10. 0: Disable, just output 0 in this channel. 10 - 2 + 1 read-write - GPIO20_MCU_SEL - 0:select function0, 1:select function1 ... - 12 - 3 + TX_TDM_CHAN11_EN + 1: Enable the valid data output of I2S TX TDM channel 11. 0: Disable, just output 0 in this channel. + 11 + 1 read-write - GPIO20_FILTER_EN - input filter enable - 15 + TX_TDM_CHAN12_EN + 1: Enable the valid data output of I2S TX TDM channel 12. 0: Disable, just output 0 in this channel. + 12 1 read-write - - - - gpio21 - iomux control register for gpio21 - 0x58 - 0x20 - 0x00000800 - - GPIO21_MCU_OE - output enable on sleep mode - 0 + TX_TDM_CHAN13_EN + 1: Enable the valid data output of I2S TX TDM channel 13. 0: Disable, just output 0 in this channel. + 13 1 read-write - GPIO21_SLP_SEL - io sleep mode enable. set 1 to enable sleep mode. - 1 + TX_TDM_CHAN14_EN + 1: Enable the valid data output of I2S TX TDM channel 14. 0: Disable, just output 0 in this channel. + 14 1 read-write - GPIO21_MCU_WPD - pull-down enable on sleep mode - 2 + TX_TDM_CHAN15_EN + 1: Enable the valid data output of I2S TX TDM channel 15. 0: Disable, just output 0 in this channel. + 15 1 read-write - GPIO21_MCU_WPU - pull-up enable on sleep mode - 3 - 1 + TX_TDM_TOT_CHAN_NUM + The total channel number of I2S TX TDM mode. + 16 + 4 read-write - GPIO21_MCU_IE - input enable on sleep mode - 4 + TX_TDM_SKIP_MSK_EN + When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels, and only the data of the enabled channels is sent, then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels. + 20 1 read-write + + + + RX_TIMING + I2S RX timing control register + 0x58 + 0x20 + - GPIO21_MCU_DRV - select drive strenth on sleep mode - 5 + RX_SD_IN_DM + The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 0 2 read-write - GPIO21_FUN_WPD - pull-down enable - 7 - 1 + RX_SD1_IN_DM + The delay mode of I2S Rx SD1 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 4 + 2 read-write - GPIO21_FUN_WPU - pull-up enable + RX_SD2_IN_DM + The delay mode of I2S Rx SD2 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. 8 - 1 + 2 read-write - GPIO21_FUN_IE - input enable - 9 - 1 + RX_SD3_IN_DM + The delay mode of I2S Rx SD3 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 12 + 2 read-write - GPIO21_FUN_DRV - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - 10 + RX_WS_OUT_DM + The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 16 2 read-write - GPIO21_MCU_SEL - 0:select function0, 1:select function1 ... - 12 - 3 + RX_BCK_OUT_DM + The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 20 + 2 read-write - GPIO21_FILTER_EN - input filter enable - 15 - 1 + RX_WS_IN_DM + The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 24 + 2 + read-write + + + RX_BCK_IN_DM + The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 28 + 2 read-write - gpio22 - iomux control register for gpio22 + TX_TIMING + I2S TX timing control register 0x5C 0x20 - 0x00000800 - GPIO22_MCU_OE - output enable on sleep mode + TX_SD_OUT_DM + The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. 0 - 1 - read-write - - - GPIO22_SLP_SEL - io sleep mode enable. set 1 to enable sleep mode. - 1 - 1 - read-write - - - GPIO22_MCU_WPD - pull-down enable on sleep mode - 2 - 1 - read-write - - - GPIO22_MCU_WPU - pull-up enable on sleep mode - 3 - 1 + 2 read-write - GPIO22_MCU_IE - input enable on sleep mode + TX_SD1_OUT_DM + The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. 4 - 1 + 2 read-write - GPIO22_MCU_DRV - select drive strenth on sleep mode - 5 + TX_WS_OUT_DM + The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 16 2 read-write - GPIO22_FUN_WPD - pull-down enable - 7 - 1 + TX_BCK_OUT_DM + The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 20 + 2 read-write - GPIO22_FUN_WPU - pull-up enable - 8 - 1 + TX_WS_IN_DM + The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 24 + 2 read-write - GPIO22_FUN_IE - input enable - 9 - 1 + TX_BCK_IN_DM + The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 28 + 2 read-write + + + + LC_HUNG_CONF + I2S HUNG configure register. + 0x60 + 0x20 + 0x00000810 + - GPIO22_FUN_DRV - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - 10 - 2 + LC_FIFO_TIMEOUT + the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value + 0 + 8 read-write - GPIO22_MCU_SEL - 0:select function0, 1:select function1 ... - 12 + LC_FIFO_TIMEOUT_SHIFT + The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift + 8 3 read-write - GPIO22_FILTER_EN - input filter enable - 15 + LC_FIFO_TIMEOUT_ENA + The enable bit for FIFO timeout + 11 1 read-write - gpio23 - iomux control register for gpio23 - 0x60 + RXEOF_NUM + I2S RX data number control register. + 0x64 0x20 - 0x00000800 + 0x00000040 - GPIO23_MCU_OE - output enable on sleep mode + RX_EOF_NUM + The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel. 0 - 1 + 12 read-write + + + + CONF_SIGLE_DATA + I2S signal data register + 0x68 + 0x20 + - GPIO23_SLP_SEL - io sleep mode enable. set 1 to enable sleep mode. - 1 - 1 + SINGLE_DATA + The configured constant channel data to be sent out. + 0 + 32 read-write + + + + STATE + I2S TX status register + 0x6C + 0x20 + 0x00000001 + - GPIO23_MCU_WPD - pull-down enable on sleep mode - 2 + TX_IDLE + 1: i2s_tx is idle state. 0: i2s_tx is working. + 0 1 - read-write + read-only + + + + ETM_CONF + I2S ETM configure register + 0x70 + 0x20 + 0x00010040 + - GPIO23_MCU_WPU - pull-up enable on sleep mode - 3 - 1 + ETM_TX_SEND_WORD_NUM + I2S ETM send x words event. When sending word number of reg_etm_tx_send_word_num[9:0], i2s will trigger an etm event. + 0 + 10 read-write - GPIO23_MCU_IE - input enable on sleep mode - 4 - 1 + ETM_RX_RECEIVE_WORD_NUM + I2S ETM receive x words event. When receiving word number of reg_etm_rx_receive_word_num[9:0], i2s will trigger an etm event. + 10 + 10 read-write + + + + FIFO_CNT + I2S sync counter register + 0x74 + 0x20 + - GPIO23_MCU_DRV - select drive strenth on sleep mode - 5 - 2 - read-write + TX_FIFO_CNT + tx fifo counter value. + 0 + 31 + read-only - GPIO23_FUN_WPD - pull-down enable - 7 + TX_FIFO_CNT_RST + Set this bit to reset tx fifo counter. + 31 1 - read-write + write-only + + + + BCK_CNT + I2S sync counter register + 0x78 + 0x20 + - GPIO23_FUN_WPU - pull-up enable - 8 - 1 - read-write + TX_BCK_CNT + tx bck counter value. + 0 + 31 + read-only - GPIO23_FUN_IE - input enable - 9 + TX_BCK_CNT_RST + Set this bit to reset tx bck counter. + 31 1 - read-write - - - GPIO23_FUN_DRV - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - 10 - 2 - read-write - - - GPIO23_MCU_SEL - 0:select function0, 1:select function1 ... - 12 - 3 - read-write + write-only + + + + CLK_GATE + Clock gate register + 0x7C + 0x20 + - GPIO23_FILTER_EN - input filter enable - 15 + CLK_EN + set this bit to enable clock gate + 0 1 read-write - gpio24 - iomux control register for gpio24 - 0x64 + DATE + Version control register + 0x80 0x20 - 0x00000800 + 0x02303240 - GPIO24_MCU_OE - output enable on sleep mode + DATE + I2S version control register 0 - 1 + 28 read-write + + + + + + I2S1 + I2S (Inter-IC Sound) Controller 1 + 0x500C7000 + + I2S1 + 28 + + + + I2S2 + I2S (Inter-IC Sound) Controller 2 + 0x500C8000 + + I2S2 + 29 + + + + I3C_MST + I3C Controller (Master) + I3C_MST + 0x500DA000 + + 0x0 + 0x90 + registers + + + I3C + 101 + + + + DEVICE_CTRL + DEVICE_CTRL register controls the transfer properties and disposition of controllers capabilities. + 0x0 + 0x20 + 0x00001020 + - GPIO24_SLP_SEL - io sleep mode enable. set 1 to enable sleep mode. + REG_BA_INCLUDE + This bit is used to include I3C broadcast address(0x7E) for private transfer.(If I3C broadcast address is not include for the private transfer, In-Band Interrupts driven from Slaves may not win address arbitration. Hence IBIs will get delayed) 1 1 read-write - GPIO24_MCU_WPD - pull-down enable on sleep mode + REG_TRANS_START + Transfer Start 2 1 read-write - GPIO24_MCU_WPU - pull-up enable on sleep mode + REG_CLK_EN + NA 3 1 read-write - GPIO24_MCU_IE - input enable on sleep mode + REG_IBI_RSTART_TRANS_EN + NA 4 1 read-write - GPIO24_MCU_DRV - select drive strenth on sleep mode + REG_AUTO_DIS_IBI_EN + NA 5 - 2 + 1 + read-write + + + REG_DMA_RX_EN + NA + 6 + 1 read-write - GPIO24_FUN_WPD - pull-down enable + REG_DMA_TX_EN + NA 7 1 read-write - GPIO24_FUN_WPU - pull-up enable + REG_MULTI_SLV_SINGLE_CCC_EN + 0: rx high bit first, 1: rx low bit first 8 1 read-write - GPIO24_FUN_IE - input enable + REG_RX_BIT_ORDER + 0: rx low byte fist, 1: rx high byte first 9 1 read-write - GPIO24_FUN_DRV - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA + REG_RX_BYTE_ORDER + NA 10 - 2 + 1 read-write - GPIO24_MCU_SEL - 0:select function0, 1:select function1 ... - 12 - 3 + REG_SCL_PULLUP_FORCE_EN + This bit is used to force scl_pullup_en + 11 + 1 read-write - GPIO24_FILTER_EN - input filter enable - 15 + REG_SCL_OE_FORCE_EN + This bit is used to force scl_oe + 12 1 read-write - - - - gpio25 - iomux control register for gpio25 - 0x68 - 0x20 - 0x00000800 - - GPIO25_MCU_OE - output enable on sleep mode - 0 + REG_SDA_PP_RD_PULLUP_EN + NA + 13 1 read-write - GPIO25_SLP_SEL - io sleep mode enable. set 1 to enable sleep mode. - 1 + REG_SDA_RD_TBIT_HLVL_PULLUP_EN + NA + 14 1 read-write - GPIO25_MCU_WPD - pull-down enable on sleep mode - 2 + REG_SDA_PP_WR_PULLUP_EN + NA + 15 1 read-write - GPIO25_MCU_WPU - pull-up enable on sleep mode - 3 + REG_DATA_BYTE_CNT_UNLATCH + 1: read current real-time updated value 0: read latch data byte cnt value + 16 1 read-write - GPIO25_MCU_IE - input enable on sleep mode - 4 + REG_MEM_CLK_FORCE_ON + 1: dev characteristic and address table memory clk date force on . 0 : clock gating by rd/wr. + 17 1 read-write + + + + BUFFER_THLD_CTRL + In-Band Interrupt Status Threshold Value . Every In Band Interrupt received by I3C controller generates an IBI status. This field controls the number of IBI status entries in the IBI buffer that trigger the IBI_STATUS_THLD_STAT interrupt. + 0x1C + 0x20 + 0x00041041 + + + REG_CMD_BUF_EMPTY_THLD + Command Buffer Empty Threshold Value is used to control the number of empty locations(or greater) in the Command Buffer that trigger CMD_BUFFER_READY_STAT interrupt. + 0 + 4 + read-write + - GPIO25_MCU_DRV - select drive strenth on sleep mode - 5 - 2 + REG_RESP_BUF_THLD + Response Buffer Threshold Value is used to control the number of entries in the Response Buffer that trigger the RESP_READY_STAT_INTR. + 6 + 3 read-write - GPIO25_FUN_WPD - pull-down enable - 7 - 1 + REG_IBI_DATA_BUF_THLD + In-Band Interrupt Data Threshold Value . Every In Band Interrupt received by I3C controller generates an IBI status. This field controls the number of IBI data entries in the IBI buffer that trigger the IBI_DATA_THLD_STAT interrupt. + 12 + 3 read-write - GPIO25_FUN_WPU - pull-up enable - 8 - 1 + REG_IBI_STATUS_BUF_THLD + NA + 18 + 3 + read-write + + + + + DATA_BUFFER_THLD_CTRL + NA + 0x20 + 0x20 + 0x00000009 + + + REG_TX_DATA_BUF_THLD + Transmit Buffer Threshold Value. This field controls the number of empty locations in the Transmit FIFO that trigger the TX_THLD_STAT interrupt. Supports values: 000:2 001:4 010:8 011:16 100:31, else:31 + 0 + 3 read-write - GPIO25_FUN_IE - input enable - 9 - 1 + REG_RX_DATA_BUF_THLD + Receive Buffer Threshold Value. This field controls the number of empty locations in the Receive FIFO that trigger the RX_THLD_STAT interrupt. Supports: 000:2 001:4 010:8 011:16 100:31, else:31 + 3 + 3 read-write + + + + IBI_NOTIFY_CTRL + NA + 0x24 + 0x20 + - GPIO25_FUN_DRV - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - 10 - 2 + REG_NOTIFY_SIR_REJECTED + Notify Rejected Slave Interrupt Request Control. This bit is used to suppress reporting to the application about Slave Interrupt Request. 0:Suppress passing the IBI Status to the IBI FIFO(hence not notifying the application) when a SIR request is NACKed and auto-disabled base on the IBI_SIR_REQ_REJECT register. 1: Writes IBI Status to the IBI FIFO(hence notifying the application) when SIR request is NACKed and auto-disabled based on the IBI_SIR_REQ_REJECT registerl. + 2 + 1 read-write + + + + IBI_SIR_REQ_PAYLOAD + NA + 0x28 + 0x20 + - GPIO25_MCU_SEL - 0:select function0, 1:select function1 ... - 12 - 3 + REG_SIR_REQ_PAYLOAD + NA + 0 + 32 read-write + + + + IBI_SIR_REQ_REJECT + NA + 0x2C + 0x20 + - GPIO25_FILTER_EN - input filter enable - 15 - 1 + REG_SIR_REQ_REJECT + The application of controller can decide whether to send ACK or NACK for Slave request received from any I3C device. A device specific response control bit is provided to select the response option, Master will ACK/NACK the Master Request based on programming of control bit, corresponding to the interrupting device. 0:ACK the SIR Request 1:NACK and send direct auto disable CCC + 0 + 32 read-write - gpio26 - iomux control register for gpio26 - 0x6C + INT_CLR + NA + 0x30 0x20 - 0x00000800 - GPIO26_MCU_OE - output enable on sleep mode + TX_DATA_BUF_THLD_INT_CLR + NA 0 1 - read-write + write-only - GPIO26_SLP_SEL - io sleep mode enable. set 1 to enable sleep mode. + RX_DATA_BUF_THLD_INT_CLR + NA 1 1 - read-write + write-only - GPIO26_MCU_WPD - pull-down enable on sleep mode + IBI_STATUS_THLD_INT_CLR + NA 2 1 - read-write + write-only - GPIO26_MCU_WPU - pull-up enable on sleep mode + CMD_BUF_EMPTY_THLD_INT_CLR + NA 3 1 - read-write + write-only - GPIO26_MCU_IE - input enable on sleep mode + RESP_READY_INT_CLR + NA 4 1 - read-write + write-only - GPIO26_MCU_DRV - select drive strenth on sleep mode + NXT_CMD_REQ_ERR_INT_CLR + NA 5 - 2 - read-write + 1 + write-only + + + TRANSFER_ERR_INT_CLR + NA + 6 + 1 + write-only - GPIO26_FUN_WPD - pull-down enable + TRANSFER_COMPLETE_INT_CLR + NA 7 1 - read-write + write-only - GPIO26_FUN_WPU - pull-up enable + COMMAND_DONE_INT_CLR + NA 8 1 - read-write + write-only - GPIO26_FUN_IE - input enable + DETECT_START_INT_CLR + NA 9 1 - read-write + write-only - GPIO26_FUN_DRV - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA + RESP_BUF_OVF_INT_CLR + NA 10 - 2 - read-write + 1 + write-only + + + IBI_DATA_BUF_OVF_INT_CLR + NA + 11 + 1 + write-only - GPIO26_MCU_SEL - 0:select function0, 1:select function1 ... + IBI_STATUS_BUF_OVF_INT_CLR + NA 12 - 3 - read-write + 1 + write-only + + + IBI_HANDLE_DONE_INT_CLR + NA + 13 + 1 + write-only + + + IBI_DETECT_INT_CLR + NA + 14 + 1 + write-only - GPIO26_FILTER_EN - input filter enable + CMD_CCC_MISMATCH_INT_CLR + NA 15 1 - read-write + write-only - gpio27 - iomux control register for gpio27 - 0x70 + INT_RAW + NA + 0x34 0x20 - 0x00000800 + 0x00000008 - GPIO27_MCU_OE - output enable on sleep mode + TX_DATA_BUF_THLD_INT_RAW + NA 0 1 read-write - GPIO27_SLP_SEL - io sleep mode enable. set 1 to enable sleep mode. + RX_DATA_BUF_THLD_INT_RAW + NA 1 1 read-write - GPIO27_MCU_WPD - pull-down enable on sleep mode + IBI_STATUS_THLD_INT_RAW + NA 2 1 read-write - GPIO27_MCU_WPU - pull-up enable on sleep mode + CMD_BUF_EMPTY_THLD_INT_RAW + NA 3 1 read-write - GPIO27_MCU_IE - input enable on sleep mode + RESP_READY_INT_RAW + NA 4 1 read-write - GPIO27_MCU_DRV - select drive strenth on sleep mode + NXT_CMD_REQ_ERR_INT_RAW + NA 5 - 2 - read-write - - - GPIO27_FUN_WPD - pull-down enable - 7 - 1 - read-write - - - GPIO27_FUN_WPU - pull-up enable - 8 - 1 - read-write - - - GPIO27_FUN_IE - input enable - 9 1 read-write - GPIO27_FUN_DRV - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - 10 - 2 - read-write - - - GPIO27_MCU_SEL - 0:select function0, 1:select function1 ... - 12 - 3 - read-write - - - GPIO27_FILTER_EN - input filter enable - 15 + TRANSFER_ERR_INT_RAW + NA + 6 1 read-write - - - - gpio28 - iomux control register for gpio28 - 0x74 - 0x20 - 0x00000800 - - GPIO28_MCU_OE - output enable on sleep mode - 0 + TRANSFER_COMPLETE_INT_RAW + NA + 7 1 read-write - GPIO28_SLP_SEL - io sleep mode enable. set 1 to enable sleep mode. - 1 + COMMAND_DONE_INT_RAW + NA + 8 1 read-write - GPIO28_MCU_WPD - pull-down enable on sleep mode - 2 + DETECT_START_INT_RAW + NA + 9 1 read-write - GPIO28_MCU_WPU - pull-up enable on sleep mode - 3 + RESP_BUF_OVF_INT_RAW + NA + 10 1 read-write - GPIO28_MCU_IE - input enable on sleep mode - 4 + IBI_DATA_BUF_OVF_INT_RAW + NA + 11 1 read-write - GPIO28_MCU_DRV - select drive strenth on sleep mode - 5 - 2 - read-write - - - GPIO28_FUN_WPD - pull-down enable - 7 + IBI_STATUS_BUF_OVF_INT_RAW + NA + 12 1 read-write - GPIO28_FUN_WPU - pull-up enable - 8 + IBI_HANDLE_DONE_INT_RAW + NA + 13 1 read-write - GPIO28_FUN_IE - input enable - 9 + IBI_DETECT_INT_RAW + NA + 14 1 read-write - GPIO28_FUN_DRV - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - 10 - 2 - read-write - - - GPIO28_MCU_SEL - 0:select function0, 1:select function1 ... - 12 - 3 - read-write - - - GPIO28_FILTER_EN - input filter enable + CMD_CCC_MISMATCH_INT_RAW + NA 15 1 read-write @@ -73028,185 +62480,239 @@ The SCL output line will be stretched low when reg_slave_scl_stretch_en is 1 and - gpio29 - iomux control register for gpio29 - 0x78 + INT_ST + NA + 0x38 0x20 - 0x00000800 - GPIO29_MCU_OE - output enable on sleep mode + TX_DATA_BUF_THLD_INT_ST + This interrupt is generated when number of empty locations in transmit buffer is greater than or equal to threshold value specified by TX_EMPTY_BUS_THLD field in DATA_BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of empty locations in transmit buffer is less than threshold value. 0 1 - read-write + read-only - GPIO29_SLP_SEL - io sleep mode enable. set 1 to enable sleep mode. + RX_DATA_BUF_THLD_INT_ST + This interrupt is generated when number of entries in receive buffer is greater than or equal to threshold value specified by RX_BUF_THLD field in DATA_BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of entries in receive buffer is less than threshold value. 1 1 - read-write + read-only - GPIO29_MCU_WPD - pull-down enable on sleep mode + IBI_STATUS_THLD_INT_ST + Only used in master mode. This interrupt is generated when number of entries in IBI buffer is greater than or equal to threshold value specified by IBI_BUF_THLD field in BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of entries in IBI buffer is less than threshold value. 2 1 - read-write + read-only - GPIO29_MCU_WPU - pull-up enable on sleep mode + CMD_BUF_EMPTY_THLD_INT_ST + This interrupt is generated when number of empty locations in command buffer is greater than or equal to threshold value specified by CMD_EMPTY_BUF_THLD field in BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of empty locations in command buffer is less than threshold value. 3 1 - read-write + read-only - GPIO29_MCU_IE - input enable on sleep mode + RESP_READY_INT_ST + This interrupt is generated when number of entries in response buffer is greater than or equal to threshold value specified by RESP_BUF_THLD field in BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of entries in response buffer is less than threshold value. 4 1 - read-write + read-only - GPIO29_MCU_DRV - select drive strenth on sleep mode + NXT_CMD_REQ_ERR_INT_ST + This interrupt is generated if toc is 0(master will restart next command), but command buf is empty. 5 - 2 - read-write + 1 + read-only + + + TRANSFER_ERR_INT_ST + This interrupt is generated if any error occurs during transfer. The error type will be specified in the response packet associated with the command (in ERR_STATUS field of RESPONSE_BUFFER_PORT register). This bit can be cleared by writing 1'h1. + 6 + 1 + read-only - GPIO29_FUN_WPD - pull-down enable + TRANSFER_COMPLETE_INT_ST + NA 7 1 - read-write + read-only - GPIO29_FUN_WPU - pull-up enable + COMMAND_DONE_INT_ST + NA 8 1 - read-write + read-only - GPIO29_FUN_IE - input enable + DETECT_START_INT_ST + NA 9 1 - read-write + read-only - GPIO29_FUN_DRV - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA + RESP_BUF_OVF_INT_ST + NA 10 - 2 - read-write + 1 + read-only + + + IBI_DATA_BUF_OVF_INT_ST + NA + 11 + 1 + read-only - GPIO29_MCU_SEL - 0:select function0, 1:select function1 ... + IBI_STATUS_BUF_OVF_INT_ST + NA 12 - 3 - read-write + 1 + read-only + + + IBI_HANDLE_DONE_INT_ST + NA + 13 + 1 + read-only + + + IBI_DETECT_INT_ST + NA + 14 + 1 + read-only - GPIO29_FILTER_EN - input filter enable + CMD_CCC_MISMATCH_INT_ST + NA 15 1 - read-write + read-only - gpio30 - iomux control register for gpio30 - 0x7C + INT_ST_ENA + The Interrupt status will be updated in INTR_STATUS register if corresponding Status Enable bit set. + 0x3C 0x20 - 0x00000800 - GPIO30_MCU_OE - output enable on sleep mode + TX_DATA_BUF_THLD_INT_ENA + Transmit Buffer threshold status enable. 0 1 read-write - GPIO30_SLP_SEL - io sleep mode enable. set 1 to enable sleep mode. + RX_DATA_BUF_THLD_INT_ENA + Receive Buffer threshold status enable. 1 1 read-write - GPIO30_MCU_WPD - pull-down enable on sleep mode + IBI_STATUS_THLD_INT_ENA + Only used in master mode. IBI Buffer threshold status enable. 2 1 read-write - GPIO30_MCU_WPU - pull-up enable on sleep mode + CMD_BUF_EMPTY_THLD_INT_ENA + Command buffer ready status enable. 3 1 read-write - GPIO30_MCU_IE - input enable on sleep mode + RESP_READY_INT_ENA + Response buffer ready status enable. 4 1 read-write - GPIO30_MCU_DRV - select drive strenth on sleep mode + NXT_CMD_REQ_ERR_INT_ENA + next command request error status enable 5 - 2 + 1 + read-write + + + TRANSFER_ERR_INT_ENA + Transfer error status enable + 6 + 1 read-write - GPIO30_FUN_WPD - pull-down enable + TRANSFER_COMPLETE_INT_ENA + NA 7 1 read-write - GPIO30_FUN_WPU - pull-up enable + COMMAND_DONE_INT_ENA + NA 8 1 read-write - GPIO30_FUN_IE - input enable + DETECT_START_INT_ENA + NA 9 1 read-write - GPIO30_FUN_DRV - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA + RESP_BUF_OVF_INT_ENA + NA 10 - 2 + 1 read-write - GPIO30_MCU_SEL - 0:select function0, 1:select function1 ... + IBI_DATA_BUF_OVF_INT_ENA + NA + 11 + 1 + read-write + + + IBI_STATUS_BUF_OVF_INT_ENA + NA 12 - 3 + 1 + read-write + + + IBI_HANDLE_DONE_INT_ENA + NA + 13 + 1 + read-write + + + IBI_DETECT_INT_ENA + NA + 14 + 1 read-write - GPIO30_FILTER_EN - input filter enable + CMD_CCC_MISMATCH_INT_ENA + NA 15 1 read-write @@ -73214,2478 +62720,2843 @@ The SCL output line will be stretched low when reg_slave_scl_stretch_en is 1 and - gpio31 - iomux control register for gpio31 - 0x80 + RESET_CTRL + NA + 0x44 0x20 - 0x00000800 - GPIO31_MCU_OE - output enable on sleep mode + REG_CORE_SOFT_RST + NA 0 1 - read-write + write-only - GPIO31_SLP_SEL - io sleep mode enable. set 1 to enable sleep mode. + REG_CMD_BUF_RST + NA 1 1 read-write - GPIO31_MCU_WPD - pull-down enable on sleep mode + REG_RESP_BUF_RST + NA 2 1 read-write - GPIO31_MCU_WPU - pull-up enable on sleep mode + REG_TX_DATA_BUF_BUF_RST + NA 3 1 read-write - GPIO31_MCU_IE - input enable on sleep mode + REG_RX_DATA_BUF_RST + NA 4 1 read-write - GPIO31_MCU_DRV - select drive strenth on sleep mode + REG_IBI_DATA_BUF_RST + NA 5 - 2 + 1 read-write - GPIO31_FUN_WPD - pull-down enable - 7 + REG_IBI_STATUS_BUF_RST + NA + 6 1 read-write + + + + BUFFER_STATUS_LEVEL + BUFFER_STATUS_LEVEL reflects the status level of Buffers in the controller. + 0x48 + 0x20 + 0x00000010 + + + CMD_BUF_EMPTY_CNT + Command Buffer Empty Locations contains the number of empty locations in the command buffer. + 0 + 5 + read-only + - GPIO31_FUN_WPU - pull-up enable + RESP_BUF_CNT + Response Buffer Level Value contains the number of valid data entries in the response buffer. 8 - 1 - read-write + 4 + read-only - GPIO31_FUN_IE - input enable - 9 - 1 - read-write + IBI_DATA_BUF_CNT + IBI Buffer Level Value contains the number of valid entries in the IBI Buffer. This is field is used in master mode. + 16 + 4 + read-only - GPIO31_FUN_DRV - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - 10 - 2 - read-write + IBI_STATUS_BUF_CNT + IBI Buffer Status Count contains the number of IBI status entries in the IBI Buffer. This field is used in master mode. + 24 + 4 + read-only + + + + DATA_BUFFER_STATUS_LEVEL + DATA_BUFFER_STATUS_LEVEL reflects the status level of the Buffers in the controller. + 0x4C + 0x20 + 0x00000020 + - GPIO31_MCU_SEL - 0:select function0, 1:select function1 ... - 12 - 3 - read-write + TX_DATA_BUF_EMPTY_CNT + Transmit Buffer Empty Level Value contains the number of empty locations in the transmit Buffer. + 0 + 6 + read-only - GPIO31_FILTER_EN - input filter enable - 15 - 1 - read-write + RX_DATA_BUF_CNT + Receive Buffer Level value contains the number of valid data entries in the receive buffer. + 16 + 6 + read-only - gpio32 - iomux control register for gpio32 - 0x84 + PRESENT_STATE0 + NA + 0x50 0x20 - 0x00000800 + 0x00000003 - GPIO32_MCU_OE - output enable on sleep mode + SDA_LVL + This bit is used to check the SCL line level to recover from error and for debugging. This bit reflects the value of synchronized scl_in_a. 0 1 - read-write + read-only - GPIO32_SLP_SEL - io sleep mode enable. set 1 to enable sleep mode. + SCL_LVL + This bit is used to check the SDA line level to recover from error and for debugging. This bit reflects the value of synchronized sda_in_a. 1 1 - read-write + read-only - GPIO32_MCU_WPD - pull-down enable on sleep mode + BUS_BUSY + NA 2 1 - read-write + read-only - GPIO32_MCU_WPU - pull-up enable on sleep mode + BUS_FREE + NA 3 1 - read-write - - - GPIO32_MCU_IE - input enable on sleep mode - 4 - 1 - read-write - - - GPIO32_MCU_DRV - select drive strenth on sleep mode - 5 - 2 - read-write - - - GPIO32_FUN_WPD - pull-down enable - 7 - 1 - read-write - - - GPIO32_FUN_WPU - pull-up enable - 8 - 1 - read-write + read-only - GPIO32_FUN_IE - input enable + CMD_TID + NA 9 - 1 - read-write + 4 + read-only - GPIO32_FUN_DRV - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - 10 - 2 - read-write + SCL_GEN_FSM_STATE + NA + 13 + 3 + read-only - GPIO32_MCU_SEL - 0:select function0, 1:select function1 ... - 12 + IBI_EV_HANDLE_FSM_STATE + NA + 16 3 - read-write + read-only - GPIO32_FILTER_EN - input filter enable - 15 - 1 - read-write + I2C_MODE_FSM_STATE + NA + 19 + 3 + read-only - GPIO32_RUE_I3C + SDR_MODE_FSM_STATE NA - 16 - 1 - read-write + 22 + 4 + read-only - GPIO32_RU_I3C - NA - 17 - 2 - read-write + DAA_MODE_FSM_STATE + Reflects whether the Master Controller is in IDLE or not. This bit will be set when all the buffer(Command, Response, IBI, Transmit, Receive) are empty along with the Master State machine is in idle state. 0X0: not in idle 0x1: in idle + 26 + 3 + read-only - GPIO32_RUE_SEL_I3C + MAIN_FSM_STATE NA - 19 - 1 - read-write + 29 + 3 + read-only - gpio33 - iomux control register for gpio33 - 0x88 + PRESENT_STATE1 + NA + 0x54 0x20 - 0x00000800 - GPIO33_MCU_OE - output enable on sleep mode + DATA_BYTE_CNT + Present transfer data byte cnt: tx data byte cnt if write rx data byte cnt if read ibi data byte cnt if IBI handle. 0 - 1 - read-write + 16 + read-only + + + + DEVICE_TABLE + Pointer for Device Address Table + 0x58 + 0x20 + - GPIO33_SLP_SEL - io sleep mode enable. set 1 to enable sleep mode. - 1 - 1 + REG_DCT_DAA_INIT_INDEX + Reserved + 0 + 4 read-write - GPIO33_MCU_WPD - pull-down enable on sleep mode - 2 - 1 + REG_DAT_DAA_INIT_INDEX + NA + 4 + 4 read-write - GPIO33_MCU_WPU - pull-up enable on sleep mode - 3 - 1 - read-write + PRESENT_DCT_INDEX + NA + 8 + 4 + read-only - GPIO33_MCU_IE - input enable on sleep mode - 4 - 1 - read-write + PRESENT_DAT_INDEX + NA + 12 + 4 + read-only + + + + TIME_OUT_VALUE + NA + 0x5C + 0x20 + 0x00410410 + - GPIO33_MCU_DRV - select drive strenth on sleep mode - 5 - 2 + REG_RESP_BUF_TO_VALUE + NA + 0 + 5 read-write - GPIO33_FUN_WPD - pull-down enable - 7 + REG_RESP_BUF_TO_EN + NA + 5 1 read-write - GPIO33_FUN_WPU - pull-up enable - 8 - 1 + REG_IBI_DATA_BUF_TO_VALUE + NA + 6 + 5 read-write - GPIO33_FUN_IE - input enable - 9 + REG_IBI_DATA_BUF_TO_EN + NA + 11 1 read-write - GPIO33_FUN_DRV - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - 10 - 2 - read-write - - - GPIO33_MCU_SEL - 0:select function0, 1:select function1 ... + REG_IBI_STATUS_BUF_TO_VALUE + NA 12 - 3 - read-write - - - GPIO33_FILTER_EN - input filter enable - 15 - 1 + 5 read-write - GPIO33_RUE_I3C + REG_IBI_STATUS_BUF_TO_EN NA - 16 + 17 1 read-write - GPIO33_RU_I3C + REG_RX_DATA_BUF_TO_VALUE NA - 17 - 2 + 18 + 5 read-write - GPIO33_RUE_SEL_I3C + REG_RX_DATA_BUF_TO_EN NA - 19 + 23 1 read-write - gpio34 - iomux control register for gpio34 - 0x8C + SCL_I3C_MST_OD_TIME + NA + 0x60 0x20 - 0x00000800 + 0x00050019 - GPIO34_MCU_OE - output enable on sleep mode + REG_I3C_MST_OD_LOW_PERIOD + SCL Open-Drain low count for I3C transfers targeted to I3C devices. 0 - 1 + 16 read-write - GPIO34_SLP_SEL - io sleep mode enable. set 1 to enable sleep mode. - 1 - 1 + REG_I3C_MST_OD_HIGH_PERIOD + SCL Open-Drain High count for I3C transfers targeted to I3C devices. + 16 + 16 read-write + + + + SCL_I3C_MST_PP_TIME + NA + 0x64 + 0x20 + 0x00050005 + - GPIO34_MCU_WPD - pull-down enable on sleep mode - 2 - 1 + REG_I3C_MST_PP_LOW_PERIOD + NA + 0 + 8 read-write - GPIO34_MCU_WPU - pull-up enable on sleep mode - 3 - 1 + REG_I3C_MST_PP_HIGH_PERIOD + NA + 16 + 8 read-write + + + + SCL_I2C_FM_TIME + NA + 0x68 + 0x20 + 0x004B00A3 + - GPIO34_MCU_IE - input enable on sleep mode - 4 - 1 + REG_I2C_FM_LOW_PERIOD + NA + 0 + 16 read-write - GPIO34_MCU_DRV - select drive strenth on sleep mode - 5 - 2 + REG_I2C_FM_HIGH_PERIOD + The SCL open-drain low count timing for I2C Fast Mode transfers. + 16 + 16 read-write + + + + SCL_I2C_FMP_TIME + NA + 0x6C + 0x20 + 0x0021003F + - GPIO34_FUN_WPD - pull-down enable - 7 - 1 + REG_I2C_FMP_LOW_PERIOD + NA + 0 + 16 read-write - GPIO34_FUN_WPU - pull-up enable - 8 - 1 + REG_I2C_FMP_HIGH_PERIOD + NA + 16 + 8 read-write + + + + SCL_EXT_LOW_TIME + NA + 0x70 + 0x20 + - GPIO34_FUN_IE - input enable - 9 - 1 + REG_I3C_MST_EXT_LOW_PERIOD1 + NA + 0 + 8 read-write - GPIO34_FUN_DRV - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - 10 - 2 + REG_I3C_MST_EXT_LOW_PERIOD2 + NA + 8 + 8 read-write - GPIO34_MCU_SEL - 0:select function0, 1:select function1 ... - 12 - 3 + REG_I3C_MST_EXT_LOW_PERIOD3 + NA + 16 + 8 read-write - GPIO34_FILTER_EN - input filter enable - 15 - 1 + REG_I3C_MST_EXT_LOW_PERIOD4 + NA + 24 + 8 read-write - gpio35 - iomux control register for gpio35 - 0x90 + SDA_SAMPLE_TIME + NA + 0x74 0x20 - 0x00000800 - GPIO35_MCU_OE - output enable on sleep mode + REG_SDA_OD_SAMPLE_TIME + It is used to adjust sda sample point when scl high under open drain speed 0 - 1 - read-write - - - GPIO35_SLP_SEL - io sleep mode enable. set 1 to enable sleep mode. - 1 - 1 - read-write - - - GPIO35_MCU_WPD - pull-down enable on sleep mode - 2 - 1 - read-write - - - GPIO35_MCU_WPU - pull-up enable on sleep mode - 3 - 1 + 9 read-write - GPIO35_MCU_IE - input enable on sleep mode - 4 - 1 + REG_SDA_PP_SAMPLE_TIME + It is used to adjust sda sample point when scl high under push pull speed + 9 + 5 read-write + + + + SDA_HOLD_TIME + NA + 0x78 + 0x20 + 0x00000001 + - GPIO35_MCU_DRV - select drive strenth on sleep mode - 5 - 2 + REG_SDA_OD_TX_HOLD_TIME + It is used to adjust sda drive point after scl neg under open drain speed + 0 + 9 read-write - GPIO35_FUN_WPD - pull-down enable - 7 - 1 + REG_SDA_PP_TX_HOLD_TIME + It is used to adjust sda dirve point after scl neg under push pull speed + 9 + 5 read-write + + + + SCL_START_HOLD + NA + 0x7C + 0x20 + 0x00000008 + - GPIO35_FUN_WPU - pull-up enable - 8 - 1 + REG_SCL_START_HOLD_TIME + I2C_SCL_START_HOLD_TIME + 0 + 9 read-write - GPIO35_FUN_IE - input enable + REG_START_DET_HOLD_TIME + NA 9 - 1 - read-write - - - GPIO35_FUN_DRV - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - 10 2 read-write + + + + SCL_RSTART_SETUP + NA + 0x80 + 0x20 + 0x00000008 + - GPIO35_MCU_SEL - 0:select function0, 1:select function1 ... - 12 - 3 + REG_SCL_RSTART_SETUP_TIME + I2C_SCL_RSTART_SETUP_TIME + 0 + 9 read-write + + + + SCL_STOP_HOLD + NA + 0x84 + 0x20 + 0x00000008 + - GPIO35_FILTER_EN - input filter enable - 15 - 1 + REG_SCL_STOP_HOLD_TIME + I2C_SCL_STOP_HOLD_TIME + 0 + 9 read-write - gpio36 - iomux control register for gpio36 - 0x94 + SCL_STOP_SETUP + NA + 0x88 0x20 - 0x00000800 + 0x00000008 - GPIO36_MCU_OE - output enable on sleep mode + REG_SCL_STOP_SETUP_TIME + I2C_SCL_STOP_SETUP_TIME 0 - 1 + 9 read-write + + + + BUS_FREE_TIME + NA + 0x90 + 0x20 + 0x00000005 + - GPIO36_SLP_SEL - io sleep mode enable. set 1 to enable sleep mode. - 1 - 1 + REG_BUS_FREE_TIME + I3C Bus Free Count Value. This field is used only in Master mode. In pure Bus System, this field represents tCAS. In Mixed Bus System, this field is expected to be programmed to tLOW of I2C Timing. + 0 + 16 read-write + + + + SCL_TERMN_T_EXT_LOW_TIME + NA + 0x94 + 0x20 + 0x00000002 + - GPIO36_MCU_WPD - pull-down enable on sleep mode - 2 - 1 + REG_I3C_MST_TERMN_T_EXT_LOW_TIME + NA + 0 + 8 read-write + + + + VER_ID + NA + 0xA0 + 0x20 + 0x20230504 + - GPIO36_MCU_WPU - pull-up enable on sleep mode - 3 - 1 + REG_I3C_MST_VER_ID + This field indicates the controller current release number that is read by an application. + 0 + 32 read-write + + + + VER_TYPE + NA + 0xA4 + 0x20 + - GPIO36_MCU_IE - input enable on sleep mode - 4 - 1 + REG_I3C_MST_VER_TYPE + This field indicates the controller current release type that is read by an application. + 0 + 32 read-write + + + + FPGA_DEBUG_PROBE + NA + 0xAC + 0x20 + 0x00000001 + - GPIO36_MCU_DRV - select drive strenth on sleep mode - 5 - 2 + REG_I3C_MST_FPGA_DEBUG_PROBE + For Debug Probe Test on FPGA + 0 + 32 read-write + + + + RND_ECO_CS + NA + 0xB0 + 0x20 + - GPIO36_FUN_WPD - pull-down enable - 7 + REG_RND_ECO_EN + NA + 0 1 read-write - GPIO36_FUN_WPU - pull-up enable - 8 + RND_ECO_RESULT + NA + 1 1 - read-write + read-only + + + + RND_ECO_LOW + NA + 0xB4 + 0x20 + - GPIO36_FUN_IE - input enable - 9 - 1 + REG_RND_ECO_LOW + NA + 0 + 32 read-write + + + + RND_ECO_HIGH + NA + 0xB8 + 0x20 + 0x0000FFFF + - GPIO36_FUN_DRV - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - 10 - 2 + REG_RND_ECO_HIGH + NA + 0 + 32 read-write + + + + + + I3C_MST_MEM + I3C_MST_MEM Peripheral + I3C_MST_MEM + 0x500DA000 + + 0x0 + 0x108 + registers + + + + COMMAND_BUF_PORT + NA + 0x8 + 0x20 + - GPIO36_MCU_SEL - 0:select function0, 1:select function1 ... - 12 - 3 + REG_COMMAND + Contains a Command Descriptor structure that depends on the requested transfer type. Command Descriptor structure is used to schedule the transfers to devices on I3C bus. + 0 + 32 read-write + + + + RESPONSE_BUF_PORT + NA + 0xC + 0x20 + - GPIO36_FILTER_EN - input filter enable - 15 - 1 - read-write + RESPONSE + The Response Buffer can be read through this register. The response status for each Command is written into the Response Buffer by the controller if ROC (Response On Completion) bit is set or if transfer error has occurred. The response buffer can be read through this register. + 0 + 32 + read-only - gpio37 - iomux control register for gpio37 - 0x98 + RX_DATA_PORT + NA + 0x10 0x20 - 0x00000800 - GPIO37_MCU_OE - output enable on sleep mode + RX_DATA_PORT + Receive Data Port. Receive data is mapped to the Rx-data buffer and receive data is always packed in 4-byte aligned data words. If the length of data transfer is not aligned to 4-bytes boundary, then there will be extra(unused) bytes(the additional data bytes have to be ignored) at the end of the transferred data. The valid data must be identified using the DATA_LENGTH filed in the Response Descriptor. 0 - 1 - read-write + 32 + read-only + + + + TX_DATA_PORT + NA + 0x14 + 0x20 + - GPIO37_SLP_SEL - io sleep mode enable. set 1 to enable sleep mode. - 1 - 1 + REG_TX_DATA_PORT + Transmit Data Port. Transmit data is mapped to the Tx-data buffer and transmit data is always packed in 4-byte aligned data words. If the length of data transfer is not aligned to 4-bytes boundary, then there will be extra(unused) bytes(the additional data bytes have to be ignored) at the end of the transferred data. The valid data must be identified using the DATA_LENGTH filed in the Response Descriptor. + 0 + 32 read-write + + + + IBI_STATUS_BUF + In-Band Interrupt Buffer Status/Data Register. When receiving an IBI, IBI_PORT is used to both: Read the IBI Status Read the IBI Data(which is raw/opaque data) + 0x18 + 0x20 + - GPIO37_MCU_WPD - pull-down enable on sleep mode - 2 - 1 - read-write + DATA_LENGTH + This field represents the length of data received along with IBI, in bytes. + 0 + 8 + read-only - GPIO37_MCU_WPU - pull-up enable on sleep mode - 3 - 1 - read-write + IBI_ID + IBI Identifier. The byte received after START which includes the address the R/W bit: Device address and R/W bit in case of Slave Interrupt or Master Request. + 8 + 8 + read-only - GPIO37_MCU_IE - input enable on sleep mode - 4 + IBI_STS + IBI received data/status. IBI Data register is mapped to the IBI Buffer. The IBI Data is always packed in4-byte aligned and put to the IBI Buffer. This register When read from, reads the data from the IBI buffer. IBI Status register when read from, returns the data from the IBI Buffer and indicates how the controller responded to incoming IBI(SIR, MR and HJ). + 28 1 - read-write - - - GPIO37_MCU_DRV - select drive strenth on sleep mode - 5 - 2 - read-write + read-only + + + + IBI_DATA_BUF + NA + 0x40 + 0x20 + - GPIO37_FUN_WPD - pull-down enable - 7 - 1 - read-write + IBI_DATA + NA + 0 + 32 + read-only + + + + DEV_ADDR_TABLE1_LOC + NA + 0xC0 + 0x20 + - GPIO37_FUN_WPU - pull-up enable - 8 - 1 + REG_DAT_DEV1_STATIC_ADDR + NA + 0 + 7 read-write - GPIO37_FUN_IE - input enable - 9 - 1 + REG_DAT_DEV1_DYNAMIC_ADDR + Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address. + 16 + 8 read-write - GPIO37_FUN_DRV - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - 10 + REG_DAT_DEV1_NACK_RETRY_CNT + This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state. + 29 2 read-write - GPIO37_MCU_SEL - 0:select function0, 1:select function1 ... - 12 - 3 - read-write - - - GPIO37_FILTER_EN - input filter enable - 15 + REG_DAT_DEV1_I2C + Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. + 31 1 read-write - gpio38 - iomux control register for gpio38 - 0x9C + DEV_ADDR_TABLE2_LOC + NA + 0xC4 0x20 - 0x00000800 - GPIO38_MCU_OE - output enable on sleep mode + REG_DAT_DEV2_STATIC_ADDR + NA 0 - 1 - read-write - - - GPIO38_SLP_SEL - io sleep mode enable. set 1 to enable sleep mode. - 1 - 1 - read-write - - - GPIO38_MCU_WPD - pull-down enable on sleep mode - 2 - 1 - read-write - - - GPIO38_MCU_WPU - pull-up enable on sleep mode - 3 - 1 + 7 read-write - GPIO38_MCU_IE - input enable on sleep mode - 4 - 1 + REG_DAT_DEV2_DYNAMIC_ADDR + Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address. + 16 + 8 read-write - GPIO38_MCU_DRV - select drive strenth on sleep mode - 5 + REG_DAT_DEV2_NACK_RETRY_CNT + This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state. + 29 2 read-write - GPIO38_FUN_WPD - pull-down enable - 7 + REG_DAT_DEV2_I2C + Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. + 31 1 read-write + + + + DEV_ADDR_TABLE3_LOC + NA + 0xC8 + 0x20 + - GPIO38_FUN_WPU - pull-up enable - 8 - 1 + REG_DAT_DEV3_STATIC_ADDR + NA + 0 + 7 read-write - GPIO38_FUN_IE - input enable - 9 - 1 + REG_DAT_DEV3_DYNAMIC_ADDR + Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address. + 16 + 8 read-write - GPIO38_FUN_DRV - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - 10 + REG_DAT_DEV3_NACK_RETRY_CNT + This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state. + 29 2 read-write - GPIO38_MCU_SEL - 0:select function0, 1:select function1 ... - 12 - 3 - read-write - - - GPIO38_FILTER_EN - input filter enable - 15 + REG_DAT_DEV3_I2C + Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. + 31 1 read-write - gpio39 - iomux control register for gpio39 - 0xA0 + DEV_ADDR_TABLE4_LOC + NA + 0xCC 0x20 - 0x00000800 - GPIO39_MCU_OE - output enable on sleep mode + REG_DAT_DEV4_STATIC_ADDR + NA 0 - 1 - read-write - - - GPIO39_SLP_SEL - io sleep mode enable. set 1 to enable sleep mode. - 1 - 1 - read-write - - - GPIO39_MCU_WPD - pull-down enable on sleep mode - 2 - 1 - read-write - - - GPIO39_MCU_WPU - pull-up enable on sleep mode - 3 - 1 + 7 read-write - GPIO39_MCU_IE - input enable on sleep mode - 4 - 1 + REG_DAT_DEV4_DYNAMIC_ADDR + Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address. + 16 + 8 read-write - GPIO39_MCU_DRV - select drive strenth on sleep mode - 5 + REG_DAT_DEV4_NACK_RETRY_CNT + This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state. + 29 2 read-write - GPIO39_FUN_WPD - pull-down enable - 7 + REG_DAT_DEV4_I2C + Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. + 31 1 read-write + + + + DEV_ADDR_TABLE5_LOC + NA + 0xD0 + 0x20 + - GPIO39_FUN_WPU - pull-up enable - 8 - 1 + REG_DAT_DEV5_STATIC_ADDR + NA + 0 + 7 read-write - GPIO39_FUN_IE - input enable - 9 - 1 + REG_DAT_DEV5_DYNAMIC_ADDR + Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address. + 16 + 8 read-write - GPIO39_FUN_DRV - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - 10 + REG_DAT_DEV5_NACK_RETRY_CNT + This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state. + 29 2 read-write - GPIO39_MCU_SEL - 0:select function0, 1:select function1 ... - 12 - 3 - read-write - - - GPIO39_FILTER_EN - input filter enable - 15 + REG_DAT_DEV5_I2C + Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. + 31 1 read-write - gpio40 - iomux control register for gpio40 - 0xA4 + DEV_ADDR_TABLE6_LOC + NA + 0xD4 0x20 - 0x00000800 - GPIO40_MCU_OE - output enable on sleep mode + REG_DAT_DEV6_STATIC_ADDR + NA 0 - 1 - read-write - - - GPIO40_SLP_SEL - io sleep mode enable. set 1 to enable sleep mode. - 1 - 1 - read-write - - - GPIO40_MCU_WPD - pull-down enable on sleep mode - 2 - 1 - read-write - - - GPIO40_MCU_WPU - pull-up enable on sleep mode - 3 - 1 + 7 read-write - GPIO40_MCU_IE - input enable on sleep mode - 4 - 1 + REG_DAT_DEV6_DYNAMIC_ADDR + Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address. + 16 + 8 read-write - GPIO40_MCU_DRV - select drive strenth on sleep mode - 5 + REG_DAT_DEV6_NACK_RETRY_CNT + This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state. + 29 2 read-write - GPIO40_FUN_WPD - pull-down enable - 7 + REG_DAT_DEV6_I2C + Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. + 31 1 read-write + + + + DEV_ADDR_TABLE7_LOC + NA + 0xD8 + 0x20 + - GPIO40_FUN_WPU - pull-up enable - 8 - 1 + REG_DAT_DEV7_STATIC_ADDR + NA + 0 + 7 read-write - GPIO40_FUN_IE - input enable - 9 - 1 + REG_DAT_DEV7_DYNAMIC_ADDR + Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address. + 16 + 8 read-write - GPIO40_FUN_DRV - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - 10 + REG_DAT_DEV7_NACK_RETRY_CNT + This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state. + 29 2 read-write - GPIO40_MCU_SEL - 0:select function0, 1:select function1 ... - 12 - 3 - read-write - - - GPIO40_FILTER_EN - input filter enable - 15 + REG_DAT_DEV7_I2C + Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. + 31 1 read-write - gpio41 - iomux control register for gpio41 - 0xA8 + DEV_ADDR_TABLE8_LOC + NA + 0xDC 0x20 - 0x00000800 - GPIO41_MCU_OE - output enable on sleep mode + REG_DAT_DEV8_STATIC_ADDR + NA 0 - 1 - read-write - - - GPIO41_SLP_SEL - io sleep mode enable. set 1 to enable sleep mode. - 1 - 1 - read-write - - - GPIO41_MCU_WPD - pull-down enable on sleep mode - 2 - 1 - read-write - - - GPIO41_MCU_WPU - pull-up enable on sleep mode - 3 - 1 + 7 read-write - GPIO41_MCU_IE - input enable on sleep mode - 4 - 1 + REG_DAT_DEV8_DYNAMIC_ADDR + Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address. + 16 + 8 read-write - GPIO41_MCU_DRV - select drive strenth on sleep mode - 5 + REG_DAT_DEV8_NACK_RETRY_CNT + This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state. + 29 2 read-write - GPIO41_FUN_WPD - pull-down enable - 7 + REG_DAT_DEV8_I2C + Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. + 31 1 read-write + + + + DEV_ADDR_TABLE9_LOC + NA + 0xE0 + 0x20 + - GPIO41_FUN_WPU - pull-up enable - 8 - 1 + REG_DAT_DEV9_STATIC_ADDR + NA + 0 + 7 read-write - GPIO41_FUN_IE - input enable - 9 - 1 + REG_DAT_DEV9_DYNAMIC_ADDR + Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address. + 16 + 8 read-write - GPIO41_FUN_DRV - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - 10 + REG_DAT_DEV9_NACK_RETRY_CNT + This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state. + 29 2 read-write - GPIO41_MCU_SEL - 0:select function0, 1:select function1 ... - 12 - 3 - read-write - - - GPIO41_FILTER_EN - input filter enable - 15 + REG_DAT_DEV9_I2C + Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. + 31 1 read-write - gpio42 - iomux control register for gpio42 - 0xAC + DEV_ADDR_TABLE10_LOC + NA + 0xE4 0x20 - 0x00000800 - GPIO42_MCU_OE - output enable on sleep mode + REG_DAT_DEV10_STATIC_ADDR + NA 0 - 1 + 7 read-write - GPIO42_SLP_SEL - io sleep mode enable. set 1 to enable sleep mode. - 1 - 1 + REG_DAT_DEV10_DYNAMIC_ADDR + Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address. + 16 + 8 read-write - GPIO42_MCU_WPD - pull-down enable on sleep mode - 2 - 1 + REG_DAT_DEV10_NACK_RETRY_CNT + This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state. + 29 + 2 read-write - GPIO42_MCU_WPU - pull-up enable on sleep mode - 3 + REG_DAT_DEV10_I2C + Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. + 31 1 read-write + + + + DEV_ADDR_TABLE11_LOC + NA + 0xE8 + 0x20 + - GPIO42_MCU_IE - input enable on sleep mode - 4 - 1 + REG_DAT_DEV11_STATIC_ADDR + NA + 0 + 7 read-write - GPIO42_MCU_DRV - select drive strenth on sleep mode - 5 - 2 + REG_DAT_DEV11_DYNAMIC_ADDR + Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address. + 16 + 8 read-write - GPIO42_FUN_WPD - pull-down enable - 7 - 1 + REG_DAT_DEV11_NACK_RETRY_CNT + This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state. + 29 + 2 read-write - GPIO42_FUN_WPU - pull-up enable - 8 + REG_DAT_DEV11_I2C + Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. + 31 1 read-write + + + + DEV_ADDR_TABLE12_LOC + NA + 0xEC + 0x20 + - GPIO42_FUN_IE - input enable - 9 - 1 + REG_DAT_DEV12_STATIC_ADDR + NA + 0 + 7 read-write - GPIO42_FUN_DRV - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - 10 - 2 + REG_DAT_DEV12_DYNAMIC_ADDR + Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address. + 16 + 8 read-write - GPIO42_MCU_SEL - 0:select function0, 1:select function1 ... - 12 - 3 + REG_DAT_DEV12_NACK_RETRY_CNT + This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state. + 29 + 2 read-write - GPIO42_FILTER_EN - input filter enable - 15 + REG_DAT_DEV12_I2C + Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. + 31 1 read-write - gpio43 - iomux control register for gpio43 - 0xB0 + DEV_CHAR_TABLE1_LOC1 + NA + 0x100 0x20 - 0x00000800 - GPIO43_MCU_OE - output enable on sleep mode + DCT_DEV1_LOC1 + NA 0 - 1 - read-write + 32 + read-only + + + + DEV_CHAR_TABLE1_LOC2 + NA + 0x104 + 0x20 + - GPIO43_SLP_SEL - io sleep mode enable. set 1 to enable sleep mode. - 1 - 1 - read-write + DCT_DEV1_LOC2 + NA + 0 + 32 + read-only + + + + DEV_CHAR_TABLE1_LOC3 + NA + 0x108 + 0x20 + - GPIO43_MCU_WPD - pull-down enable on sleep mode - 2 - 1 - read-write + DCT_DEV1_LOC3 + NA + 0 + 32 + read-only + + + + DEV_CHAR_TABLE1_LOC4 + NA + 0x10C + 0x20 + - GPIO43_MCU_WPU - pull-up enable on sleep mode - 3 - 1 - read-write + DCT_DEV1_LOC4 + NA + 0 + 32 + read-only + + + + DEV_CHAR_TABLE2_LOC1 + NA + 0x110 + 0x20 + - GPIO43_MCU_IE - input enable on sleep mode - 4 - 1 - read-write + DCT_DEV2_LOC1 + NA + 0 + 32 + read-only + + + + DEV_CHAR_TABLE2_LOC2 + NA + 0x114 + 0x20 + - GPIO43_MCU_DRV - select drive strenth on sleep mode - 5 - 2 - read-write + DCT_DEV2_LOC2 + NA + 0 + 32 + read-only + + + + DEV_CHAR_TABLE2_LOC3 + NA + 0x118 + 0x20 + - GPIO43_FUN_WPD - pull-down enable - 7 - 1 - read-write + DCT_DEV2_LOC3 + NA + 0 + 32 + read-only + + + + DEV_CHAR_TABLE2_LOC4 + NA + 0x11C + 0x20 + - GPIO43_FUN_WPU - pull-up enable - 8 - 1 - read-write + DCT_DEV2_LOC4 + NA + 0 + 32 + read-only + + + + DEV_CHAR_TABLE3_LOC1 + NA + 0x120 + 0x20 + - GPIO43_FUN_IE - input enable - 9 - 1 - read-write + DCT_DEV3_LOC1 + NA + 0 + 32 + read-only + + + + DEV_CHAR_TABLE3_LOC2 + NA + 0x124 + 0x20 + - GPIO43_FUN_DRV - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - 10 - 2 - read-write + DCT_DEV3_LOC2 + NA + 0 + 32 + read-only + + + + DEV_CHAR_TABLE3_LOC3 + NA + 0x128 + 0x20 + - GPIO43_MCU_SEL - 0:select function0, 1:select function1 ... - 12 - 3 - read-write + DCT_DEV3_LOC3 + NA + 0 + 32 + read-only + + + + DEV_CHAR_TABLE3_LOC4 + NA + 0x12C + 0x20 + - GPIO43_FILTER_EN - input filter enable - 15 - 1 - read-write + DCT_DEV3_LOC4 + NA + 0 + 32 + read-only - gpio44 - iomux control register for gpio44 - 0xB4 + DEV_CHAR_TABLE4_LOC1 + NA + 0x130 0x20 - 0x00000800 - GPIO44_MCU_OE - output enable on sleep mode + DCT_DEV4_LOC1 + NA 0 - 1 - read-write + 32 + read-only + + + + DEV_CHAR_TABLE4_LOC2 + NA + 0x134 + 0x20 + - GPIO44_SLP_SEL - io sleep mode enable. set 1 to enable sleep mode. - 1 - 1 - read-write + DCT_DEV4_LOC2 + NA + 0 + 32 + read-only + + + + DEV_CHAR_TABLE4_LOC3 + NA + 0x138 + 0x20 + - GPIO44_MCU_WPD - pull-down enable on sleep mode - 2 - 1 - read-write + DCT_DEV4_LOC3 + NA + 0 + 32 + read-only + + + + DEV_CHAR_TABLE4_LOC4 + NA + 0x13C + 0x20 + - GPIO44_MCU_WPU - pull-up enable on sleep mode - 3 - 1 - read-write + DCT_DEV4_LOC4 + NA + 0 + 32 + read-only + + + + DEV_CHAR_TABLE5_LOC1 + NA + 0x140 + 0x20 + - GPIO44_MCU_IE - input enable on sleep mode - 4 - 1 - read-write + DCT_DEV5_LOC1 + NA + 0 + 32 + read-only + + + + DEV_CHAR_TABLE5_LOC2 + NA + 0x144 + 0x20 + - GPIO44_MCU_DRV - select drive strenth on sleep mode - 5 - 2 - read-write + DCT_DEV5_LOC2 + NA + 0 + 32 + read-only + + + + DEV_CHAR_TABLE5_LOC3 + NA + 0x148 + 0x20 + - GPIO44_FUN_WPD - pull-down enable - 7 - 1 - read-write + DCT_DEV5_LOC3 + NA + 0 + 32 + read-only + + + + DEV_CHAR_TABLE5_LOC4 + NA + 0x14C + 0x20 + - GPIO44_FUN_WPU - pull-up enable - 8 - 1 - read-write + DCT_DEV5_LOC4 + NA + 0 + 32 + read-only + + + + DEV_CHAR_TABLE6_LOC1 + NA + 0x150 + 0x20 + - GPIO44_FUN_IE - input enable - 9 - 1 - read-write + DCT_DEV6_LOC1 + NA + 0 + 32 + read-only + + + + DEV_CHAR_TABLE6_LOC2 + NA + 0x154 + 0x20 + - GPIO44_FUN_DRV - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - 10 - 2 - read-write + DCT_DEV6_LOC2 + NA + 0 + 32 + read-only + + + + DEV_CHAR_TABLE6_LOC3 + NA + 0x158 + 0x20 + - GPIO44_MCU_SEL - 0:select function0, 1:select function1 ... - 12 - 3 - read-write + DCT_DEV6_LOC3 + NA + 0 + 32 + read-only + + + + DEV_CHAR_TABLE6_LOC4 + NA + 0x15C + 0x20 + - GPIO44_FILTER_EN - input filter enable - 15 - 1 - read-write + DCT_DEV6_LOC4 + NA + 0 + 32 + read-only - gpio45 - iomux control register for gpio45 - 0xB8 + DEV_CHAR_TABLE7_LOC1 + NA + 0x160 0x20 - 0x00000800 - GPIO45_MCU_OE - output enable on sleep mode + DCT_DEV7_LOC1 + NA 0 - 1 - read-write + 32 + read-only + + + + DEV_CHAR_TABLE7_LOC2 + NA + 0x164 + 0x20 + - GPIO45_SLP_SEL - io sleep mode enable. set 1 to enable sleep mode. - 1 - 1 - read-write + DCT_DEV7_LOC2 + NA + 0 + 32 + read-only + + + + DEV_CHAR_TABLE7_LOC3 + NA + 0x168 + 0x20 + - GPIO45_MCU_WPD - pull-down enable on sleep mode - 2 - 1 - read-write + DCT_DEV7_LOC3 + NA + 0 + 32 + read-only + + + + DEV_CHAR_TABLE7_LOC4 + NA + 0x16C + 0x20 + - GPIO45_MCU_WPU - pull-up enable on sleep mode - 3 - 1 - read-write + DCT_DEV7_LOC4 + NA + 0 + 32 + read-only + + + + DEV_CHAR_TABLE8_LOC1 + NA + 0x170 + 0x20 + - GPIO45_MCU_IE - input enable on sleep mode - 4 - 1 - read-write + DCT_DEV8_LOC1 + NA + 0 + 32 + read-only + + + + DEV_CHAR_TABLE8_LOC2 + NA + 0x174 + 0x20 + - GPIO45_MCU_DRV - select drive strenth on sleep mode - 5 - 2 - read-write + DCT_DEV8_LOC2 + NA + 0 + 32 + read-only + + + + DEV_CHAR_TABLE8_LOC3 + NA + 0x178 + 0x20 + - GPIO45_FUN_WPD - pull-down enable - 7 - 1 - read-write + DCT_DEV8_LOC3 + NA + 0 + 32 + read-only + + + + DEV_CHAR_TABLE8_LOC4 + NA + 0x17C + 0x20 + - GPIO45_FUN_WPU - pull-up enable - 8 - 1 - read-write + DCT_DEV8_LOC4 + NA + 0 + 32 + read-only + + + + DEV_CHAR_TABLE9_LOC1 + NA + 0x180 + 0x20 + - GPIO45_FUN_IE - input enable - 9 - 1 - read-write + DCT_DEV9_LOC1 + NA + 0 + 32 + read-only + + + + DEV_CHAR_TABLE9_LOC2 + NA + 0x184 + 0x20 + - GPIO45_FUN_DRV - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - 10 - 2 - read-write + DCT_DEV9_LOC2 + NA + 0 + 32 + read-only + + + + DEV_CHAR_TABLE9_LOC3 + NA + 0x188 + 0x20 + - GPIO45_MCU_SEL - 0:select function0, 1:select function1 ... - 12 - 3 - read-write + DCT_DEV9_LOC3 + NA + 0 + 32 + read-only + + + + DEV_CHAR_TABLE9_LOC4 + NA + 0x18C + 0x20 + - GPIO45_FILTER_EN - input filter enable - 15 - 1 - read-write + DCT_DEV9_LOC4 + NA + 0 + 32 + read-only - gpio46 - iomux control register for gpio46 - 0xBC + DEV_CHAR_TABLE10_LOC1 + NA + 0x190 0x20 - 0x00000800 - GPIO46_MCU_OE - output enable on sleep mode + DCT_DEV10_LOC1 + NA 0 - 1 - read-write + 32 + read-only + + + + DEV_CHAR_TABLE10_LOC2 + NA + 0x194 + 0x20 + - GPIO46_SLP_SEL - io sleep mode enable. set 1 to enable sleep mode. - 1 - 1 - read-write + DCT_DEV10_LOC2 + NA + 0 + 32 + read-only + + + + DEV_CHAR_TABLE10_LOC3 + NA + 0x198 + 0x20 + - GPIO46_MCU_WPD - pull-down enable on sleep mode - 2 - 1 - read-write + DCT_DEV10_LOC3 + NA + 0 + 32 + read-only + + + + DEV_CHAR_TABLE10_LOC4 + NA + 0x19C + 0x20 + - GPIO46_MCU_WPU - pull-up enable on sleep mode - 3 - 1 - read-write + DCT_DEV10_LOC4 + NA + 0 + 32 + read-only + + + + DEV_CHAR_TABLE11_LOC1 + NA + 0x1A0 + 0x20 + - GPIO46_MCU_IE - input enable on sleep mode - 4 - 1 - read-write + DCT_DEV11_LOC1 + NA + 0 + 32 + read-only + + + + DEV_CHAR_TABLE11_LOC2 + NA + 0x1A4 + 0x20 + - GPIO46_MCU_DRV - select drive strenth on sleep mode - 5 - 2 - read-write + DCT_DEV11_LOC2 + NA + 0 + 32 + read-only + + + + DEV_CHAR_TABLE11_LOC3 + NA + 0x1A8 + 0x20 + - GPIO46_FUN_WPD - pull-down enable - 7 - 1 - read-write + DCT_DEV11_LOC3 + NA + 0 + 32 + read-only + + + + DEV_CHAR_TABLE11_LOC4 + NA + 0x1AC + 0x20 + - GPIO46_FUN_WPU - pull-up enable - 8 - 1 - read-write + DCT_DEV11_LOC4 + NA + 0 + 32 + read-only + + + + DEV_CHAR_TABLE12_LOC1 + NA + 0x1B0 + 0x20 + - GPIO46_FUN_IE - input enable - 9 - 1 - read-write + DCT_DEV12_LOC1 + NA + 0 + 32 + read-only + + + + DEV_CHAR_TABLE12_LOC2 + NA + 0x1B4 + 0x20 + - GPIO46_FUN_DRV - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - 10 - 2 - read-write + DCT_DEV12_LOC2 + NA + 0 + 32 + read-only + + + + DEV_CHAR_TABLE12_LOC3 + NA + 0x1B8 + 0x20 + - GPIO46_MCU_SEL - 0:select function0, 1:select function1 ... - 12 - 3 - read-write + DCT_DEV12_LOC3 + NA + 0 + 32 + read-only + + + + DEV_CHAR_TABLE12_LOC4 + NA + 0x1BC + 0x20 + - GPIO46_FILTER_EN - input filter enable - 15 - 1 - read-write + DCT_DEV12_LOC4 + NA + 0 + 32 + read-only + + + + I3C_SLV + I3C Controller (Slave) + I3C_SLV + 0x500DB000 + + 0x0 + 0x40 + registers + + + I3C_SLV + 102 + + - gpio47 - iomux control register for gpio47 - 0xC0 + CONFIG + NA + 0x4 0x20 - 0x00000800 + 0x002F0001 - GPIO47_MCU_OE - output enable on sleep mode + SLVENA + 1: allow the slave to operate on i2c or i3c bus. 0: the slave will ignore the bus. This should be not set until registers such as PARTNO, IDEXT and the like are set 1st -if used- since they impact data to the master 0 1 read-write - GPIO47_SLP_SEL - io sleep mode enable. set 1 to enable sleep mode. + NACK + 1:the slave will NACK all requests to it except CCC broadcast. This should be used with caution as the Master may determine the slave is missing if overused. 1 1 read-write - GPIO47_MCU_WPD - pull-down enable on sleep mode + MATCHSS + 1: the START and STOP sticky STATUS bits will only be set if MATCHED is set..This allows START and STOP to be used to detect end of a message to /from this slave. 2 1 read-write - GPIO47_MCU_WPU - pull-up enable on sleep mode + S0IGNORE + If 1, the Slave will not detect S0 or S1 errors and so not lock up waiting on an Exit Pattern. This should only be used when the bus will not use HDR. 3 1 read-write - GPIO47_MCU_IE - input enable on sleep mode + DDROK + NA 4 1 read-write - GPIO47_MCU_DRV - select drive strenth on sleep mode - 5 - 2 - read-write - - - GPIO47_FUN_WPD - pull-down enable - 7 - 1 - read-write - - - GPIO47_FUN_WPU - pull-up enable + IDRAND + NA 8 1 read-write - GPIO47_FUN_IE - input enable + OFFLINE + NA 9 1 read-write - GPIO47_FUN_DRV - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - 10 - 2 - read-write - - - GPIO47_MCU_SEL - 0:select function0, 1:select function1 ... - 12 - 3 + BAMATCH + Bus Available condition match value for current ???Slow clock???. This provides the count of the slow clock to count out 1us (or more) to allow an IBI to drive SDA Low when the Master is not doing so. The max width , and so max value, is controlled by the block. Only if enabled for events such IBI or MR or HJ, and if enabled to provide this as a register. With is limited to CLK_SLOW_BITS + 16 + 8 read-write - GPIO47_FILTER_EN - input filter enable - 15 - 1 + SADDR + If allowed by the block:sets i2c 7 bits static address,else should be 0. If enabled to use one and to be provided by SW. Block may provide in HW as well. + 25 + 7 read-write - gpio48 - iomux control register for gpio48 - 0xC4 + STATUS + NA + 0x8 0x20 - 0x00000800 - GPIO48_MCU_OE - output enable on sleep mode + STNOTSTOP + Is 1 if bus is busy(activity) and 0 when in a STOP condition. Other bits may also set when busy. Note that this can also be true from an S0 or S1 error, which waits for an Exit Pattern. 0 1 - read-write + read-only - GPIO48_SLP_SEL - io sleep mode enable. set 1 to enable sleep mode. + STMSG + Is 1 if this bus Slave is listening to the bus traffic or repsonding, If STNOSTOP=1, then this will be 0 when a non-matching address seen until next respeated START it STOP. 1 1 - read-write + read-only - GPIO48_MCU_WPD - pull-down enable on sleep mode + STCCCH + Is 1 if a CCC message is being handled automatically. 2 1 - read-write + read-only - GPIO48_MCU_WPU - pull-up enable on sleep mode + STREQRD + 1 if the req in process is an sdr read from this slave or an IBI is being pushed out, 3 1 - read-write + read-only - GPIO48_MCU_IE - input enable on sleep mode + STREQWR + NA 4 1 - read-write + read-only - GPIO48_MCU_DRV - select drive strenth on sleep mode + STDAA + NA 5 - 2 - read-write + 1 + read-only - GPIO48_FUN_WPD - pull-down enable - 7 + STHDR + NA + 6 1 - read-write + read-only - GPIO48_FUN_WPU - pull-up enable + START + NA 8 1 read-write - GPIO48_FUN_IE - input enable + MATCHED + NA 9 1 read-write - GPIO48_FUN_DRV - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA + STOP + NA 10 - 2 - read-write - - - GPIO48_MCU_SEL - 0:select function0, 1:select function1 ... - 12 - 3 - read-write - - - GPIO48_FILTER_EN - input filter enable - 15 - 1 - read-write - - - - - gpio49 - iomux control register for gpio49 - 0xC8 - 0x20 - 0x00000800 - - - GPIO49_MCU_OE - output enable on sleep mode - 0 - 1 - read-write - - - GPIO49_SLP_SEL - io sleep mode enable. set 1 to enable sleep mode. - 1 - 1 - read-write - - - GPIO49_MCU_WPD - pull-down enable on sleep mode - 2 1 read-write - GPIO49_MCU_WPU - pull-up enable on sleep mode - 3 + RXPEND + Receiving a message from master,which is not being handled by block(not a CCC internally processed). For all but External FIFO, this uses DATACTRL RXTRIG, which defaults to not-empty. If DMA is enabled for RX, DMA will be signaled as well. Will self-clear if data is read(FIFO and non-FIFO) + 11 1 - read-write + read-only - GPIO49_MCU_IE - input enable on sleep mode - 4 + TXNOTFULL + Is 1 when the To-bus buffer/FIFO can accept more data to go out. Defau:1. For all but External FIFO, this uses DATACTRL TXTRIG,which defaults to not-full. If DMA is enabled for TX, it will also be signaled to provide more. + 12 1 - read-write - - - GPIO49_MCU_DRV - select drive strenth on sleep mode - 5 - 2 - read-write + read-only - GPIO49_FUN_WPD - pull-down enable - 7 + DACHG + The Slv Dynamic Address has been assigned, reassigned, or reset(lost) and is now in that state of being valid or none. Actual DA can be seen in the DYNADDR register. Note that this will also be used when MAP Auto feature is configured. This will be changing one or more MAP items. See DYNADDR and/or MAPCTRLn. DYNAADDR for the main DA(0) will indicate if last change was due to Auto MAP. + 13 1 read-write - GPIO49_FUN_WPU - pull-up enable - 8 + CCC + A common -command-code(CCC), not handled by block, has been received. This acts differently between: *Broadcasted ones, which will then also correspond with RXPEND and the 1st byte will be the CCC(command) . *Direct ones, which may never be directed to this device. If it is, then the TXSEND or RXPEND will be triggered with this end the RXPEND will contain the command. + 14 1 read-write - GPIO49_FUN_IE - input enable - 9 + ERRWARN + NA + 15 1 - read-write - - - GPIO49_FUN_DRV - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - 10 - 2 - read-write - - - GPIO49_MCU_SEL - 0:select function0, 1:select function1 ... - 12 - 3 - read-write + read-only - GPIO49_FILTER_EN - input filter enable - 15 + HDRMATCH + NA + 16 1 read-write - gpio50 - iomux control register for gpio50 - 0xCC + CTRL + NA + 0xC 0x20 - 0x00000800 - GPIO50_MCU_OE - output enable on sleep mode + SLV_EVENT + If set to non-0, will request an event. Once requested, STATUS.EVENT and EVDET will show the status as it progresses. Once completed, the field will automatically return to 0. Once non-0, only 0 can be written(to cancel) until done. 0: Normal mode. If set to 0 after was a non-0 value, will cancel if not already in flight. 1: start an IBI. This will try to push through an IBI on the bus. If data associate with the IBI, it will be drawn from the IBIDATA field. Note that if Time control is enabled, this will include anytime control related bytes further, the IBIDATA byte will have bit7 set to 1. 0 - 1 - read-write - - - GPIO50_SLP_SEL - io sleep mode enable. set 1 to enable sleep mode. - 1 - 1 - read-write - - - GPIO50_MCU_WPD - pull-down enable on sleep mode - 2 - 1 + 2 read-write - GPIO50_MCU_WPU - pull-up enable on sleep mode + EXTDATA + reserved 3 1 read-write - GPIO50_MCU_IE - input enable on sleep mode + MAPIDX + Index of Dynamic Address that IBI is for. This is 0 for the main or base Dynamic Address, or can be any valid index. 4 - 1 - read-write - - - GPIO50_MCU_DRV - select drive strenth on sleep mode - 5 - 2 - read-write - - - GPIO50_FUN_WPD - pull-down enable - 7 - 1 + 4 read-write - GPIO50_FUN_WPU - pull-up enable + IBIDATA + Data byte to go with an IBI, if enabled for it. If enabled (was in BCR), then it is required. 8 - 1 + 8 read-write - GPIO50_FUN_IE - input enable - 9 - 1 + PENDINT + Should be set to the pending interrupt that GETSTATUS CCC will return. This should be maintained by the application if used and configured, as the Master will read this. If not configured, the GETSTATUS field will return 1 if an IBI is pending, and 0 otherwise. + 16 + 4 read-write - GPIO50_FUN_DRV - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - 10 + ACTSTATE + NA + 20 2 read-write - GPIO50_MCU_SEL - 0:select function0, 1:select function1 ... - 12 - 3 - read-write - - - GPIO50_FILTER_EN - input filter enable - 15 - 1 + VENDINFO + NA + 24 + 8 read-write - gpio51 - iomux control register for gpio51 - 0xD0 + INTSET + INSET allows setting enables for interrupts(connecting the corresponding STATUS source to causing an IRQ to the processor) + 0x10 0x20 - 0x00000800 - GPIO51_MCU_OE - output enable on sleep mode - 0 + STOP_ENA + Interrupt on STOP state on the bus. See Start as the preferred interrupt when needed. This interrupt may not trigger for quick STOP/START combination, as it relates to the state of being stopped. + 10 1 read-write - GPIO51_SLP_SEL - io sleep mode enable. set 1 to enable sleep mode. - 1 + RXPEND_ENA + Interrupt when receiving a message from Master, which is not being handled by the block (excludes CCCs being handled automatically). If FIFO, then RX fullness trigger. If DMA, then message end. + 11 1 read-write - GPIO51_MCU_WPD - pull-down enable on sleep mode - 2 + TXSEND_ENA + NA + 12 1 read-write + + + + INTCLR + NA + 0x14 + 0x20 + - GPIO51_MCU_WPU - pull-up enable on sleep mode - 3 + STOP_CLR + Interrupt on STOP state on the bus. See Start as the preferred interrupt when needed. This interrupt may not trigger for quick STOP/START combination, as it relates to the state of being stopped. + 10 1 - read-write + write-only - GPIO51_MCU_IE - input enable on sleep mode - 4 + RXPEND_CLR + Interrupt when receiving a message from Master, which is not being handled by the block (excludes CCCs being handled automatically). If FIFO, then RX fullness trigger. If DMA, then message end. + 11 1 - read-write - - - GPIO51_MCU_DRV - select drive strenth on sleep mode - 5 - 2 - read-write + write-only - GPIO51_FUN_WPD - pull-down enable - 7 + TXSEND_CLR + NA + 12 1 - read-write + write-only + + + + INTMASKED + NA + 0x18 + 0x20 + - GPIO51_FUN_WPU - pull-up enable - 8 + STOP_MASK + Interrupt on STOP state on the bus. See Start as the preferred interrupt when needed. This interrupt may not trigger for quick STOP/START combination, as it relates to the state of being stopped. + 10 1 - read-write + read-only - GPIO51_FUN_IE - input enable - 9 + RXPEND_MASK + Interrupt when receiving a message from Master, which is not being handled by the block (excludes CCCs being handled automatically). If FIFO, then RX fullness trigger. If DMA, then message end. + 11 1 - read-write - - - GPIO51_FUN_DRV - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - 10 - 2 - read-write + read-only - GPIO51_MCU_SEL - 0:select function0, 1:select function1 ... + TXSEND_MASK + NA 12 - 3 - read-write - - - GPIO51_FILTER_EN - input filter enable - 15 1 - read-write + read-only - gpio52 - iomux control register for gpio52 - 0xD4 + DATACTRL + NA + 0x2C 0x20 - 0x00000800 + 0x000000B0 - GPIO52_MCU_OE - output enable on sleep mode + FLUSHTB + Flushes the from-bus buffer/FIFO. Not normally used 0 1 - read-write + write-only - GPIO52_SLP_SEL - io sleep mode enable. set 1 to enable sleep mode. + FLUSHFB + Flushes the to-bus buffer/FIFO. Used when Master terminates a to-bus (read) message prematurely 1 1 - read-write - - - GPIO52_MCU_WPD - pull-down enable on sleep mode - 2 - 1 - read-write + write-only - GPIO52_MCU_WPU - pull-up enable on sleep mode + UNLOCK + If this bit is not written 1, the register bits from 7 to 4 are not changed on write. 3 1 - read-write + write-only - GPIO52_MCU_IE - input enable on sleep mode + TXTRIG + Trigger level for tx emptiness when FIFOed, Affects interrupt and DMA(if enabled). The defaults is 3 4 - 1 + 2 read-write - GPIO52_MCU_DRV - select drive strenth on sleep mode - 5 + RXTRIG + Trigger level for rx fulless when FIFOed, Affects interrupt and DMA(if enabled). The defaults is 3 + 6 2 read-write - GPIO52_FUN_WPD - pull-down enable - 7 - 1 - read-write + TXCOUNT + NA + 16 + 5 + read-only - GPIO52_FUN_WPU - pull-up enable - 8 - 1 - read-write + RXCOUNT + NA + 24 + 5 + read-only - GPIO52_FUN_IE - input enable - 9 + TXFULL + NA + 30 1 - read-write - - - GPIO52_FUN_DRV - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - 10 - 2 - read-write - - - GPIO52_MCU_SEL - 0:select function0, 1:select function1 ... - 12 - 3 - read-write + read-only - GPIO52_FILTER_EN - input filter enable - 15 + RXEMPTY + NA + 31 1 - read-write + read-only - gpio53 - iomux control register for gpio53 - 0xD8 + WDATAB + NA + 0x30 0x20 - 0x00000800 - GPIO53_MCU_OE - output enable on sleep mode + WDATAB + NA 0 - 1 - read-write + 8 + write-only - GPIO53_SLP_SEL - io sleep mode enable. set 1 to enable sleep mode. - 1 + WDATA_END + NA + 8 1 - read-write + write-only + + + + WDATABE + NA + 0x34 + 0x20 + - GPIO53_MCU_WPD - pull-down enable on sleep mode - 2 - 1 - read-write + WDATABE + NA + 0 + 8 + write-only + + + + RDARAB + Read Byte Data (from-bus) register + 0x40 + 0x20 + - GPIO53_MCU_WPU - pull-up enable on sleep mode - 3 - 1 - read-write + DATA0 + This register allows reading a byte from the bus unless external FIFO is used. A byte should not be read unless there is data waiting, as indicated by the RXPEND bit being set in the STATUS register + 0 + 8 + read-only + + + + RDATAH + Read Half-word Data (from-bus) register + 0x48 + 0x20 + - GPIO53_MCU_IE - input enable on sleep mode - 4 - 1 - read-write + DATA_LSB + NA + 0 + 8 + read-only - GPIO53_MCU_DRV - select drive strenth on sleep mode - 5 - 2 - read-write + DATA_MSB + This register allows reading a Half-word (byte pair) from the bus unless external FIFO is used. A Half-word should not be read unless there is at least 2 bytes of data waiting, as indicated by the RX FIFO level trigger or RXCOUNT available space in the DATACTRL register + 8 + 8 + read-only + + + + CAPABILITIES2 + NA + 0x5C + 0x20 + 0x00000100 + - GPIO53_FUN_WPD - pull-down enable - 7 - 1 - read-write + CAPABLITIES2 + NA + 0 + 32 + read-only + + + + CAPABILITIES + NA + 0x60 + 0x20 + 0x7C13FC1C + - GPIO53_FUN_WPU - pull-up enable - 8 - 1 - read-write + CAPABLITIES + NA + 0 + 32 + read-only + + + + IDPARTNO + NA + 0x6C + 0x20 + - GPIO53_FUN_IE - input enable - 9 - 1 + PARTNO + NA + 0 + 32 read-write + + + + IDEXT + NA + 0x70 + 0x20 + - GPIO53_FUN_DRV - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - 10 - 2 + IDEXT + NA + 0 + 32 read-write + + + + VENDORID + NA + 0x74 + 0x20 + 0x00005550 + - GPIO53_MCU_SEL - 0:select function0, 1:select function1 ... - 12 - 3 + VID + NA + 0 + 15 read-write + + + + + + AXI_ICM + AXI_ICM Peripheral + ICM_AXI + 0x500A4000 + + 0x0 + 0x10 + registers + + + + VERID_FILEDS + NA + 0x0 + 0x20 + 0x3430342A + - GPIO53_FILTER_EN - input filter enable - 15 - 1 - read-write + ICM_REG_VERID + NA + 0 + 32 + read-only - gpio54 - iomux control register for gpio54 - 0xDC + HW_CFG + NA + 0x4 0x20 - 0x00000800 + 0x0070D151 - GPIO54_MCU_OE - output enable on sleep mode + ICM_REG_AXI_HWCFG_QOS_SUPPORT + NA 0 1 - read-write + read-only - GPIO54_SLP_SEL - io sleep mode enable. set 1 to enable sleep mode. + ICM_REG_AXI_HWCFG_APB3_SUPPORT + NA 1 1 - read-write + read-only - GPIO54_MCU_WPD - pull-down enable on sleep mode + ICM_REG_AXI_HWCFG_AXI4_SUPPORT + NA 2 1 - read-write + read-only - GPIO54_MCU_WPU - pull-up enable on sleep mode + ICM_REG_AXI_HWCFG_LOCK_EN + NA 3 1 - read-write + read-only - GPIO54_MCU_IE - input enable on sleep mode + ICM_REG_AXI_HWCFG_TRUST_ZONE_EN + NA 4 1 - read-write + read-only - GPIO54_MCU_DRV - select drive strenth on sleep mode + ICM_REG_AXI_HWCFG_DECODER_TYPE + NA 5 - 2 - read-write - - - GPIO54_FUN_WPD - pull-down enable - 7 1 - read-write + read-only - GPIO54_FUN_WPU - pull-up enable - 8 + ICM_REG_AXI_HWCFG_REMAP_EN + NA + 6 1 - read-write + read-only - GPIO54_FUN_IE - input enable - 9 + ICM_REG_AXI_HWCFG_BI_DIR_CMD_EN + NA + 7 1 - read-write + read-only - GPIO54_FUN_DRV - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - 10 - 2 - read-write + ICM_REG_AXI_HWCFG_LOW_POWER_INF_EN + NA + 8 + 1 + read-only - GPIO54_MCU_SEL - 0:select function0, 1:select function1 ... + ICM_REG_AXI_HWCFG_AXI_NUM_MASTERS + NA 12 - 3 - read-write + 5 + read-only - GPIO54_FILTER_EN - input filter enable - 15 - 1 - read-write + ICM_REG_AXI_HWCFG_AXI_NUM_SLAVES + NA + 20 + 5 + read-only - gpio55 - iomux control register for gpio55 - 0xE0 + CMD + NA + 0x8 0x20 - 0x00000800 - GPIO55_MCU_OE - output enable on sleep mode + ICM_REG_AXI_CMD + NA 0 - 1 - read-write - - - GPIO55_SLP_SEL - io sleep mode enable. set 1 to enable sleep mode. - 1 - 1 + 3 read-write - GPIO55_MCU_WPD - pull-down enable on sleep mode - 2 + ICM_REG_RD_WR_CHAN + NA + 7 1 read-write - GPIO55_MCU_WPU - pull-up enable on sleep mode - 3 - 1 + ICM_REG_AXI_MASTER_PORT + NA + 8 + 4 read-write - GPIO55_MCU_IE - input enable on sleep mode - 4 + ICM_REG_AXI_ERR_BIT + NA + 28 1 - read-write - - - GPIO55_MCU_DRV - select drive strenth on sleep mode - 5 - 2 - read-write + read-only - GPIO55_FUN_WPD - pull-down enable - 7 + ICM_REG_AXI_SOFT_RESET_BIT + NA + 29 1 read-write - GPIO55_FUN_WPU - pull-up enable - 8 + ICM_REG_AXI_RD_WR_CMD + NA + 30 1 read-write - GPIO55_FUN_IE - input enable - 9 + ICM_REG_AXI_CMD_EN + NA + 31 1 read-write + + + + DATA + NA + 0xC + 0x20 + - GPIO55_FUN_DRV - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA - 10 - 2 - read-write - - - GPIO55_MCU_SEL - 0:select function0, 1:select function1 ... - 12 - 3 + ICM_REG_DATA + NA + 0 + 32 read-write + + + + + + IO_MUX + Input/Output Multiplexer + IO_MUX + 0x500E1000 + + 0x0 + 0xE8 + registers + + + + DATE + iomux version + 0x104 + 0x20 + 0x00201222 + - GPIO55_FILTER_EN - input filter enable - 15 - 1 + DATE + csv date + 0 + 28 read-write - gpio56 - iomux control register for gpio56 - 0xE4 + 54 + 0x4 + 0-53 + GPIO%s + IO_MUX Control Register + 0x4 0x20 - 0x00000800 + read-write - GPIO56_MCU_OE - output enable on sleep mode + MCU_OE + Configures whether or not to enable the output of GPIOn in sleep mode. 0: Disable 1: Enable 0 1 - read-write - GPIO56_SLP_SEL - io sleep mode enable. set 1 to enable sleep mode. + SLP_SEL + Configures whether or not to enter sleep mode for GPIOn. 0: Not enter 1: Enter 1 1 - read-write - GPIO56_MCU_WPD - pull-down enable on sleep mode + MCU_WPD + Configure whether or not to enable pull-down resistor of GPIOn during sleep mode. 0: Disable 1: Enable 2 1 - read-write - GPIO56_MCU_WPU - pull-up enable on sleep mode + MCU_WPU + Configures whether or not to enable pull-up resistor of GPIOn during sleep mode. 0: Disable 1: Enable 3 1 - read-write - GPIO56_MCU_IE - input enable on sleep mode + MCU_IE + Configures whether or not to enable the input of GPIOn during sleep mode. 0: Disable 1: Enable 4 1 - read-write - GPIO56_MCU_DRV - select drive strenth on sleep mode + MCU_DRV + Configures the drive strength of GPIOn during sleep mode. 0: ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA 5 2 - read-write - GPIO56_FUN_WPD - pull-down enable + FUN_WPD + Configures whether or not to enable pull-down resistor of GPIOn. 0: Disable 1: Enable 7 1 - read-write - GPIO56_FUN_WPU - pull-up enable + FUN_WPU + Configures whether or not enable pull-up resistor of GPIOn. 0: Disable 1: Enable 8 1 - read-write - GPIO56_FUN_IE - input enable + FUN_IE + Configures whether or not to enable input of GPIOn. 0: Disable 1: Enable 9 1 - read-write - GPIO56_FUN_DRV - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA + FUN_DRV + Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA 10 2 - read-write - GPIO56_MCU_SEL - 0:select function0, 1:select function1 ... + MCU_SEL + Configures to select IO MUX function for this pin. 0: Select Function 0 1: Select Function 1 ...... 12 3 - read-write - GPIO56_FILTER_EN - input filter enable + FILTER_EN + Configures whether or not to enable filter for pin input signals. 0: Disable 1: Enable 15 1 - read-write - - - - - DATE - iomux version - 0x104 - 0x20 - 0x00201222 - - - DATE - csv date - 0 - 28 - read-write @@ -114045,36 +103916,36 @@ Any pulses with width less than this will be ignored when the filter is enabled. - 16 - 0x1 + 4 + 0x4 M_MEM[%s] Represents M 0x0 - 0x8 + 0x20 - 16 - 0x1 + 4 + 0x4 Z_MEM[%s] Represents Z 0x200 - 0x8 + 0x20 - 16 - 0x1 + 4 + 0x4 Y_MEM[%s] Represents Y 0x400 - 0x8 + 0x20 - 16 - 0x1 + 4 + 0x4 X_MEM[%s] Represents X 0x600 - 0x8 + 0x20 M_PRIME @@ -118729,20 +108600,20 @@ IDINTEN[4]: DU Interrupt. - 64 - 0x1 + 16 + 0x4 H_MEM[%s] Sha H memory which contains intermediate hash or finial hash. 0x40 - 0x8 + 0x20 - 64 - 0x1 + 16 + 0x4 M_MEM[%s] Sha M memory which contains message. 0x80 - 0x8 + 0x20 @@ -141124,6 +130995,42 @@ protection is enabled. + + UART1 + UART (Universal Asynchronous Receiver-Transmitter) Controller 1 + 0x500CB000 + + UART1 + 32 + + + + UART2 + UART (Universal Asynchronous Receiver-Transmitter) Controller 2 + 0x500CC000 + + UART2 + 33 + + + + UART3 + UART (Universal Asynchronous Receiver-Transmitter) Controller 3 + 0x500CD000 + + UART3 + 34 + + + + UART4 + UART (Universal Asynchronous Receiver-Transmitter) Controller 4 + 0x500CE000 + + UART4 + 35 + + UHCI0 Universal Host Controller Interface 0 diff --git a/esp32p4/svd/patches/esp32p4.yaml b/esp32p4/svd/patches/esp32p4.yaml index ecc9632d35..390e94b0b7 100644 --- a/esp32p4/svd/patches/esp32p4.yaml +++ b/esp32p4/svd/patches/esp32p4.yaml @@ -1,274 +1 @@ _svd: "../esp32p4.base.svd" - -AES: - _modify: - "IV_MEM*": - dim: 4 - dimIncrement: 0x4 - size: 0x20 - "H_MEM*": - dim: 4 - dimIncrement: 0x4 - size: 0x20 - "J0_MEM*": - dim: 4 - dimIncrement: 0x4 - size: 0x20 - "T0_MEM*": - dim: 4 - dimIncrement: 0x4 - size: 0x20 - -DS: - _modify: - "Y_MEM*": - dim: 128 - dimIncrement: 0x4 - size: 0x20 - "M_MEM*": - dim: 128 - dimIncrement: 0x4 - size: 0x20 - "RB_MEM*": - dim: 128 - dimIncrement: 0x4 - size: 0x20 - "BOX_MEM*": - dim: 12 - dimIncrement: 0x4 - size: 0x20 - "IV_MEM*": - dim: 4 - dimIncrement: 0x4 - size: 0x20 - "X_MEM*": - dim: 128 - dimIncrement: 0x4 - size: 0x20 - "Z_MEM*": - dim: 128 - dimIncrement: 0x4 - size: 0x20 - -ECC: - _modify: - "K_MEM*": - dim: 8 - dimIncrement: 0x4 - size: 0x20 - "PX_MEM*": - dim: 8 - dimIncrement: 0x4 - size: 0x20 - "PY_MEM*": - dim: 8 - dimIncrement: 0x4 - size: 0x20 - -ECDSA: - _modify: - "MESSAGE_MEM*": - dim: 8 - dimIncrement: 0x4 - size: 0x20 - "R_MEM*": - dim: 8 - dimIncrement: 0x4 - size: 0x20 - "S_MEM*": - dim: 8 - dimIncrement: 0x4 - size: 0x20 - "Z_MEM*": - dim: 8 - dimIncrement: 0x4 - size: 0x20 - "QAX_MEM*": - dim: 8 - dimIncrement: 0x4 - size: 0x20 - "QAY_MEM*": - dim: 8 - dimIncrement: 0x4 - size: 0x20 - -HMAC: - _modify: - "WR_MESSAGE_MEM*": - dim: 16 - dimIncrement: 0x4 - size: 0x20 - "RD_RESULT_MEM*": - dim: 8 - dimIncrement: 0x4 - size: 0x20 - -HP_SYS: - _strip: "HP_" - - "*": - _strip: "HP_" - - _modify: - CPU_INT_FROM_CPU_0: - name: CPU_INTR_FROM_CPU_0 - CPU_INT_FROM_CPU_1: - name: CPU_INTR_FROM_CPU_1 - CPU_INT_FROM_CPU_2: - name: CPU_INTR_FROM_CPU_2 - CPU_INT_FROM_CPU_3: - name: CPU_INTR_FROM_CPU_3 - - CPU_INTR_FROM_CPU_0: - _modify: - CPU_INT_FROM_CPU_0: - name: CPU_INTR_FROM_CPU_0 - CPU_INTR_FROM_CPU_1: - _modify: - CPU_INT_FROM_CPU_1: - name: CPU_INTR_FROM_CPU_1 - CPU_INTR_FROM_CPU_2: - _modify: - CPU_INT_FROM_CPU_2: - name: CPU_INTR_FROM_CPU_2 - CPU_INTR_FROM_CPU_3: - _modify: - CPU_INT_FROM_CPU_3: - name: CPU_INTR_FROM_CPU_3 - -LP_HUK: - _modify: - "INFO_MEM*": - dim: 96 - dimIncrement: 0x4 - size: 0x20 - -RSA: - _modify: - "M_MEM*": - dim: 4 - dimIncrement: 0x4 - size: 0x20 - "Z_MEM*": - dim: 4 - dimIncrement: 0x4 - size: 0x20 - "Y_MEM*": - dim: 4 - dimIncrement: 0x4 - size: 0x20 - "X_MEM*": - dim: 4 - dimIncrement: 0x4 - size: 0x20 - -SHA: - _modify: - "H_MEM*": - dim: 16 - dimIncrement: 0x4 - size: 0x20 - "M_MEM*": - dim: 16 - dimIncrement: 0x4 - size: 0x20 - -GPIO: - _delete: - - FUNC*_IN_SEL_CFG - _add: - FUNC%s_IN_SEL_CFG: - dim: 254 - dimIncrement: 0x04 - dimIndex: 1-255 - description: GPIO input function configuration register - addressOffset: 0x15c - access: read-write - reset-value: 0x0000003F - size: 0x20 - fields: - IN_SEL: - description: "set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level." - bitOffset: 0 - bitWidth: 6 - IN_INV_SEL: - description: "set this bit to invert input signal. 1:invert. 0:not invert." - bitOffset: 6 - bitWidth: 1 - SEL: - description: "set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO." - bitOffset: 7 - bitWidth: 1 - FUNC%s_OUT_SEL_CFG: - _modify: - FUNC_OUT_SEL: - name: OUT_SEL - FUNC_OUT_INV_SEL: - name: INV_SEL - FUNC_OEN_SEL: - name: OEN_SEL - FUNC_OEN_INV_SEL: - name: OEN_INV_SEL - -IO_MUX: - _delete: - - gpio* - _add: - GPIO%s: - dim: 54 - dimIncrement: 0x04 - dimIndex: 0-54 - description: IO_MUX Control Register - addressOffset: 0x4 - access: read-write - reset-value: 0x800 - size: 0x20 - fields: - MCU_OE: - description: "Configures whether or not to enable the output of GPIOn in sleep mode. 0: Disable 1: Enable" - bitOffset: 0 - bitWidth: 1 - SLP_SEL: - description: "Configures whether or not to enter sleep mode for GPIOn. 0: Not enter 1: Enter" - bitOffset: 1 - bitWidth: 1 - MCU_WPD: - description: "Configure whether or not to enable pull-down resistor of GPIOn during sleep mode. 0: Disable 1: Enable" - bitOffset: 2 - bitWidth: 1 - MCU_WPU: - description: "Configures whether or not to enable pull-up resistor of GPIOn during sleep mode. 0: Disable 1: Enable" - bitOffset: 3 - bitWidth: 1 - MCU_IE: - description: "Configures whether or not to enable the input of GPIOn during sleep mode. 0: Disable 1: Enable" - bitOffset: 4 - bitWidth: 1 - MCU_DRV: - description: "Configures the drive strength of GPIOn during sleep mode. 0: ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA" - bitOffset: 5 - bitWidth: 2 - FUN_WPD: - description: "Configures whether or not to enable pull-down resistor of GPIOn. 0: Disable 1: Enable" - bitOffset: 7 - bitWidth: 1 - FUN_WPU: - description: "Configures whether or not enable pull-up resistor of GPIOn. 0: Disable 1: Enable" - bitOffset: 8 - bitWidth: 1 - FUN_IE: - description: "Configures whether or not to enable input of GPIOn. 0: Disable 1: Enable" - bitOffset: 9 - bitWidth: 1 - FUN_DRV: - description: "Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA" - bitOffset: 10 - bitWidth: 2 - MCU_SEL: - description: "Configures to select IO MUX function for this pin. 0: Select Function 0 1: Select Function 1 ......" - bitOffset: 12 - bitWidth: 3 - FILTER_EN: - description: "Configures whether or not to enable filter for pin input signals. 0: Disable 1: Enable" - bitOffset: 15 - bitWidth: 1