From c69e3cc0f4967d4573dd5d04628619082749ca3a Mon Sep 17 00:00:00 2001 From: rmsyn Date: Wed, 19 Feb 2025 12:32:13 +0000 Subject: [PATCH] esp32c6: generate the SLC peripheral Generates the `slc` peripheral using the definitions added to the SVD patches file. --- esp32c6/src/lib.rs | 51 ++- esp32c6/src/slc.rs | 345 +++++++++++++++++++ esp32c6/src/slc/slc0_len_conf.rs | 53 +++ esp32c6/src/slc/slc0_rx_sharemem_end.rs | 52 +++ esp32c6/src/slc/slc0_rx_sharemem_start.rs | 52 +++ esp32c6/src/slc/slc0_tx_sharemem_end.rs | 52 +++ esp32c6/src/slc/slc0_tx_sharemem_start.rs | 52 +++ esp32c6/src/slc/slc0int_clr.rs | 175 ++++++++++ esp32c6/src/slc/slc0int_ena.rs | 374 +++++++++++++++++++++ esp32c6/src/slc/slc0int_raw.rs | 370 ++++++++++++++++++++ esp32c6/src/slc/slc0int_st.rs | 208 ++++++++++++ esp32c6/src/slc/slc0rx_link.rs | 92 +++++ esp32c6/src/slc/slc0rx_link_addr.rs | 47 +++ esp32c6/src/slc/slc0token1.rs | 68 ++++ esp32c6/src/slc/slc0tx_link.rs | 92 +++++ esp32c6/src/slc/slc0tx_link_addr.rs | 47 +++ esp32c6/src/slc/slc10_length.rs | 30 ++ esp32c6/src/slc/slc1_rx_sharemem_end.rs | 52 +++ esp32c6/src/slc/slc1_rx_sharemem_start.rs | 52 +++ esp32c6/src/slc/slc1_tx_sharemem_end.rs | 52 +++ esp32c6/src/slc/slc1_tx_sharemem_start.rs | 52 +++ esp32c6/src/slc/slc1int_clr.rs | 175 ++++++++++ esp32c6/src/slc/slc1int_ena1.rs | 387 +++++++++++++++++++++ esp32c6/src/slc/slc1int_raw.rs | 370 ++++++++++++++++++++ esp32c6/src/slc/slc1int_st1.rs | 214 ++++++++++++ esp32c6/src/slc/slc1rx_link.rs | 92 +++++ esp32c6/src/slc/slc1rx_link_addr.rs | 47 +++ esp32c6/src/slc/slc1token1.rs | 68 ++++ esp32c6/src/slc/slc1tx_link.rs | 92 +++++ esp32c6/src/slc/slc1tx_link_addr.rs | 47 +++ esp32c6/src/slc/slc_burst_len.rs | 112 +++++++ esp32c6/src/slc/slc_rx_dscr_conf.rs | 52 +++ esp32c6/src/slc/slcconf0.rs | 392 ++++++++++++++++++++++ esp32c6/src/slc/slcconf1.rs | 137 ++++++++ esp32c6/src/slc/slcintvec_tohost.rs | 39 +++ 35 files changed, 4591 insertions(+), 1 deletion(-) create mode 100644 esp32c6/src/slc.rs create mode 100644 esp32c6/src/slc/slc0_len_conf.rs create mode 100644 esp32c6/src/slc/slc0_rx_sharemem_end.rs create mode 100644 esp32c6/src/slc/slc0_rx_sharemem_start.rs create mode 100644 esp32c6/src/slc/slc0_tx_sharemem_end.rs create mode 100644 esp32c6/src/slc/slc0_tx_sharemem_start.rs create mode 100644 esp32c6/src/slc/slc0int_clr.rs create mode 100644 esp32c6/src/slc/slc0int_ena.rs create mode 100644 esp32c6/src/slc/slc0int_raw.rs create mode 100644 esp32c6/src/slc/slc0int_st.rs create mode 100644 esp32c6/src/slc/slc0rx_link.rs create mode 100644 esp32c6/src/slc/slc0rx_link_addr.rs create mode 100644 esp32c6/src/slc/slc0token1.rs create mode 100644 esp32c6/src/slc/slc0tx_link.rs create mode 100644 esp32c6/src/slc/slc0tx_link_addr.rs create mode 100644 esp32c6/src/slc/slc10_length.rs create mode 100644 esp32c6/src/slc/slc1_rx_sharemem_end.rs create mode 100644 esp32c6/src/slc/slc1_rx_sharemem_start.rs create mode 100644 esp32c6/src/slc/slc1_tx_sharemem_end.rs create mode 100644 esp32c6/src/slc/slc1_tx_sharemem_start.rs create mode 100644 esp32c6/src/slc/slc1int_clr.rs create mode 100644 esp32c6/src/slc/slc1int_ena1.rs create mode 100644 esp32c6/src/slc/slc1int_raw.rs create mode 100644 esp32c6/src/slc/slc1int_st1.rs create mode 100644 esp32c6/src/slc/slc1rx_link.rs create mode 100644 esp32c6/src/slc/slc1rx_link_addr.rs create mode 100644 esp32c6/src/slc/slc1token1.rs create mode 100644 esp32c6/src/slc/slc1tx_link.rs create mode 100644 esp32c6/src/slc/slc1tx_link_addr.rs create mode 100644 esp32c6/src/slc/slc_burst_len.rs create mode 100644 esp32c6/src/slc/slc_rx_dscr_conf.rs create mode 100644 esp32c6/src/slc/slcconf0.rs create mode 100644 esp32c6/src/slc/slcconf1.rs create mode 100644 esp32c6/src/slc/slcintvec_tohost.rs diff --git a/esp32c6/src/lib.rs b/esp32c6/src/lib.rs index ec02f251d..304cbcf4c 100644 --- a/esp32c6/src/lib.rs +++ b/esp32c6/src/lib.rs @@ -2518,7 +2518,7 @@ pub struct SLCHOST { unsafe impl Send for SLCHOST {} impl SLCHOST { #[doc = r"Pointer to the register block"] - pub const PTR: *const slchost::RegisterBlock = 0x6001_7000 as *const _; + pub const PTR: *const slchost::RegisterBlock = 0x6001_8000 as *const _; #[doc = r"Return the pointer to the register block"] #[inline(always)] pub const fn ptr() -> *const slchost::RegisterBlock { @@ -3431,6 +3431,52 @@ impl core::fmt::Debug for I2C_ANA_MST { } #[doc = "I2C_ANA_MST Peripheral"] pub mod i2c_ana_mst; +#[doc = "SDIO SLC"] +pub struct SLC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SLC {} +impl SLC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const slc::RegisterBlock = 0x6001_7000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const slc::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for SLC { + type Target = slc::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SLC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SLC").finish() + } +} +#[doc = "SDIO SLC"] +pub mod slc; #[no_mangle] static mut DEVICE_PERIPHERALS: bool = false; #[doc = r" All the peripherals."] @@ -3574,6 +3620,8 @@ pub struct Peripherals { pub PLIC_UX: PLIC_UX, #[doc = "I2C_ANA_MST"] pub I2C_ANA_MST: I2C_ANA_MST, + #[doc = "SLC"] + pub SLC: SLC, } impl Peripherals { #[doc = r" Returns all the peripherals *once*."] @@ -3665,6 +3713,7 @@ impl Peripherals { PLIC_MX: PLIC_MX::steal(), PLIC_UX: PLIC_UX::steal(), I2C_ANA_MST: I2C_ANA_MST::steal(), + SLC: SLC::steal(), } } } diff --git a/esp32c6/src/slc.rs b/esp32c6/src/slc.rs new file mode 100644 index 000000000..5c00602d8 --- /dev/null +++ b/esp32c6/src/slc.rs @@ -0,0 +1,345 @@ +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +#[doc = "Register block"] +pub struct RegisterBlock { + slcconf0: SLCCONF0, + slc0int_raw: SLC0INT_RAW, + slc0int_st: SLC0INT_ST, + slc0int_ena: SLC0INT_ENA, + slc0int_clr: SLC0INT_CLR, + slc1int_raw: SLC1INT_RAW, + _reserved6: [u8; 0x08], + slc1int_clr: SLC1INT_CLR, + _reserved7: [u8; 0x18], + slc0rx_link: SLC0RX_LINK, + slc0rx_link_addr: SLC0RX_LINK_ADDR, + slc0tx_link: SLC0TX_LINK, + slc0tx_link_addr: SLC0TX_LINK_ADDR, + slc1rx_link: SLC1RX_LINK, + slc1rx_link_addr: SLC1RX_LINK_ADDR, + slc1tx_link: SLC1TX_LINK, + slc1tx_link_addr: SLC1TX_LINK_ADDR, + slcintvec_tohost: SLCINTVEC_TOHOST, + _reserved16: [u8; 0x04], + slc0token1: SLC0TOKEN1, + _reserved17: [u8; 0x04], + slc1token1: SLC1TOKEN1, + slcconf1: SLCCONF1, + _reserved19: [u8; 0x34], + slc_rx_dscr_conf: SLC_RX_DSCR_CONF, + _reserved20: [u8; 0x48], + slc0_len_conf: SLC0_LEN_CONF, + slc10_length: SLC10_LENGTH, + _reserved22: [u8; 0x50], + slc1int_st1: SLC1INT_ST1, + slc1int_ena1: SLC1INT_ENA1, + slc0_tx_sharemem_start: SLC0_TX_SHAREMEM_START, + slc0_tx_sharemem_end: SLC0_TX_SHAREMEM_END, + slc0_rx_sharemem_start: SLC0_RX_SHAREMEM_START, + slc0_rx_sharemem_end: SLC0_RX_SHAREMEM_END, + slc1_tx_sharemem_start: SLC1_TX_SHAREMEM_START, + slc1_tx_sharemem_end: SLC1_TX_SHAREMEM_END, + slc1_rx_sharemem_start: SLC1_RX_SHAREMEM_START, + slc1_rx_sharemem_end: SLC1_RX_SHAREMEM_END, + _reserved32: [u8; 0x08], + slc_burst_len: SLC_BURST_LEN, +} +impl RegisterBlock { + #[doc = "0x00 - DMA configuration"] + #[inline(always)] + pub const fn slcconf0(&self) -> &SLCCONF0 { + &self.slcconf0 + } + #[doc = "0x04 - SLC0 to slave raw interrupt status"] + #[inline(always)] + pub const fn slc0int_raw(&self) -> &SLC0INT_RAW { + &self.slc0int_raw + } + #[doc = "0x08 - SLC0 to slave masked interrupt status"] + #[inline(always)] + pub const fn slc0int_st(&self) -> &SLC0INT_ST { + &self.slc0int_st + } + #[doc = "0x0c - SLC0 to slave interrupt enable"] + #[inline(always)] + pub const fn slc0int_ena(&self) -> &SLC0INT_ENA { + &self.slc0int_ena + } + #[doc = "0x10 - SLC0 to slave interrupt clear"] + #[inline(always)] + pub const fn slc0int_clr(&self) -> &SLC0INT_CLR { + &self.slc0int_clr + } + #[doc = "0x14 - SLC1 to slave raw interrupt status"] + #[inline(always)] + pub const fn slc1int_raw(&self) -> &SLC1INT_RAW { + &self.slc1int_raw + } + #[doc = "0x20 - SLC1 to slave interrupt clear"] + #[inline(always)] + pub const fn slc1int_clr(&self) -> &SLC1INT_CLR { + &self.slc1int_clr + } + #[doc = "0x3c - SLC0 RX linked list configuration"] + #[inline(always)] + pub const fn slc0rx_link(&self) -> &SLC0RX_LINK { + &self.slc0rx_link + } + #[doc = "0x40 - SLC0 RX linked list address"] + #[inline(always)] + pub const fn slc0rx_link_addr(&self) -> &SLC0RX_LINK_ADDR { + &self.slc0rx_link_addr + } + #[doc = "0x44 - SLC0 TX linked list configuration"] + #[inline(always)] + pub const fn slc0tx_link(&self) -> &SLC0TX_LINK { + &self.slc0tx_link + } + #[doc = "0x48 - SLC0 TX linked list address"] + #[inline(always)] + pub const fn slc0tx_link_addr(&self) -> &SLC0TX_LINK_ADDR { + &self.slc0tx_link_addr + } + #[doc = "0x4c - SLC1 RX linked list configuration"] + #[inline(always)] + pub const fn slc1rx_link(&self) -> &SLC1RX_LINK { + &self.slc1rx_link + } + #[doc = "0x50 - SLC1 RX linked list address"] + #[inline(always)] + pub const fn slc1rx_link_addr(&self) -> &SLC1RX_LINK_ADDR { + &self.slc1rx_link_addr + } + #[doc = "0x54 - SLC1 TX linked list configuration"] + #[inline(always)] + pub const fn slc1tx_link(&self) -> &SLC1TX_LINK { + &self.slc1tx_link + } + #[doc = "0x58 - SLC1 TX linked list address"] + #[inline(always)] + pub const fn slc1tx_link_addr(&self) -> &SLC1TX_LINK_ADDR { + &self.slc1tx_link_addr + } + #[doc = "0x5c - Slave to host interrupt vector set"] + #[inline(always)] + pub const fn slcintvec_tohost(&self) -> &SLCINTVEC_TOHOST { + &self.slcintvec_tohost + } + #[doc = "0x64 - SLC0 receiving buffer configuration"] + #[inline(always)] + pub const fn slc0token1(&self) -> &SLC0TOKEN1 { + &self.slc0token1 + } + #[doc = "0x6c - SLC1 receiving buffer configuration"] + #[inline(always)] + pub const fn slc1token1(&self) -> &SLC1TOKEN1 { + &self.slc1token1 + } + #[doc = "0x70 - DMA configuration"] + #[inline(always)] + pub const fn slcconf1(&self) -> &SLCCONF1 { + &self.slcconf1 + } + #[doc = "0xa8 - DMA slave to host configuration register"] + #[inline(always)] + pub const fn slc_rx_dscr_conf(&self) -> &SLC_RX_DSCR_CONF { + &self.slc_rx_dscr_conf + } + #[doc = "0xf4 - Length control of transmitting packets"] + #[inline(always)] + pub const fn slc0_len_conf(&self) -> &SLC0_LEN_CONF { + &self.slc0_len_conf + } + #[doc = "0xf8 - Length of transmitting packets"] + #[inline(always)] + pub const fn slc10_length(&self) -> &SLC10_LENGTH { + &self.slc10_length + } + #[doc = "0x14c - SLC1 to slave masked interrupt status"] + #[inline(always)] + pub const fn slc1int_st1(&self) -> &SLC1INT_ST1 { + &self.slc1int_st1 + } + #[doc = "0x150 - SLC1 to slave interrupt enable"] + #[inline(always)] + pub const fn slc1int_ena1(&self) -> &SLC1INT_ENA1 { + &self.slc1int_ena1 + } + #[doc = "0x154 - SLC0 AHB TX start address range"] + #[inline(always)] + pub const fn slc0_tx_sharemem_start(&self) -> &SLC0_TX_SHAREMEM_START { + &self.slc0_tx_sharemem_start + } + #[doc = "0x158 - SLC0 AHB TX end address range"] + #[inline(always)] + pub const fn slc0_tx_sharemem_end(&self) -> &SLC0_TX_SHAREMEM_END { + &self.slc0_tx_sharemem_end + } + #[doc = "0x15c - SLC0 AHB RX start address range"] + #[inline(always)] + pub const fn slc0_rx_sharemem_start(&self) -> &SLC0_RX_SHAREMEM_START { + &self.slc0_rx_sharemem_start + } + #[doc = "0x160 - SLC0 AHB RX end address range"] + #[inline(always)] + pub const fn slc0_rx_sharemem_end(&self) -> &SLC0_RX_SHAREMEM_END { + &self.slc0_rx_sharemem_end + } + #[doc = "0x164 - SLC1 AHB TX start address range"] + #[inline(always)] + pub const fn slc1_tx_sharemem_start(&self) -> &SLC1_TX_SHAREMEM_START { + &self.slc1_tx_sharemem_start + } + #[doc = "0x168 - SLC1 AHB TX end address range"] + #[inline(always)] + pub const fn slc1_tx_sharemem_end(&self) -> &SLC1_TX_SHAREMEM_END { + &self.slc1_tx_sharemem_end + } + #[doc = "0x16c - SLC1 AHB RX start address range"] + #[inline(always)] + pub const fn slc1_rx_sharemem_start(&self) -> &SLC1_RX_SHAREMEM_START { + &self.slc1_rx_sharemem_start + } + #[doc = "0x170 - SLC1 AHB RX end address range"] + #[inline(always)] + pub const fn slc1_rx_sharemem_end(&self) -> &SLC1_RX_SHAREMEM_END { + &self.slc1_rx_sharemem_end + } + #[doc = "0x17c - DMA AHB burst type configuration"] + #[inline(always)] + pub const fn slc_burst_len(&self) -> &SLC_BURST_LEN { + &self.slc_burst_len + } +} +#[doc = "SLCCONF0 (rw) register accessor: DMA configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`slcconf0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slcconf0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slcconf0`] module"] +pub type SLCCONF0 = crate::Reg; +#[doc = "DMA configuration"] +pub mod slcconf0; +#[doc = "SLC0RX_LINK (rw) register accessor: SLC0 RX linked list configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`slc0rx_link::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc0rx_link::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc0rx_link`] module"] +pub type SLC0RX_LINK = crate::Reg; +#[doc = "SLC0 RX linked list configuration"] +pub mod slc0rx_link; +#[doc = "SLC0RX_LINK_ADDR (rw) register accessor: SLC0 RX linked list address\n\nYou can [`read`](crate::Reg::read) this register and get [`slc0rx_link_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc0rx_link_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc0rx_link_addr`] module"] +pub type SLC0RX_LINK_ADDR = crate::Reg; +#[doc = "SLC0 RX linked list address"] +pub mod slc0rx_link_addr; +#[doc = "SLC0TX_LINK (rw) register accessor: SLC0 TX linked list configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`slc0tx_link::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc0tx_link::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc0tx_link`] module"] +pub type SLC0TX_LINK = crate::Reg; +#[doc = "SLC0 TX linked list configuration"] +pub mod slc0tx_link; +#[doc = "SLC0TX_LINK_ADDR (rw) register accessor: SLC0 TX linked list address\n\nYou can [`read`](crate::Reg::read) this register and get [`slc0tx_link_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc0tx_link_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc0tx_link_addr`] module"] +pub type SLC0TX_LINK_ADDR = crate::Reg; +#[doc = "SLC0 TX linked list address"] +pub mod slc0tx_link_addr; +#[doc = "SLC1RX_LINK (rw) register accessor: SLC1 RX linked list configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`slc1rx_link::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc1rx_link::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc1rx_link`] module"] +pub type SLC1RX_LINK = crate::Reg; +#[doc = "SLC1 RX linked list configuration"] +pub mod slc1rx_link; +#[doc = "SLC1RX_LINK_ADDR (rw) register accessor: SLC1 RX linked list address\n\nYou can [`read`](crate::Reg::read) this register and get [`slc1rx_link_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc1rx_link_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc1rx_link_addr`] module"] +pub type SLC1RX_LINK_ADDR = crate::Reg; +#[doc = "SLC1 RX linked list address"] +pub mod slc1rx_link_addr; +#[doc = "SLC1TX_LINK (rw) register accessor: SLC1 TX linked list configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`slc1tx_link::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc1tx_link::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc1tx_link`] module"] +pub type SLC1TX_LINK = crate::Reg; +#[doc = "SLC1 TX linked list configuration"] +pub mod slc1tx_link; +#[doc = "SLC1TX_LINK_ADDR (rw) register accessor: SLC1 TX linked list address\n\nYou can [`read`](crate::Reg::read) this register and get [`slc1tx_link_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc1tx_link_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc1tx_link_addr`] module"] +pub type SLC1TX_LINK_ADDR = crate::Reg; +#[doc = "SLC1 TX linked list address"] +pub mod slc1tx_link_addr; +#[doc = "SLC0TOKEN1 (rw) register accessor: SLC0 receiving buffer configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`slc0token1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc0token1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc0token1`] module"] +pub type SLC0TOKEN1 = crate::Reg; +#[doc = "SLC0 receiving buffer configuration"] +pub mod slc0token1; +#[doc = "SLC1TOKEN1 (rw) register accessor: SLC1 receiving buffer configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`slc1token1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc1token1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc1token1`] module"] +pub type SLC1TOKEN1 = crate::Reg; +#[doc = "SLC1 receiving buffer configuration"] +pub mod slc1token1; +#[doc = "SLCCONF1 (rw) register accessor: DMA configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`slcconf1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slcconf1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slcconf1`] module"] +pub type SLCCONF1 = crate::Reg; +#[doc = "DMA configuration"] +pub mod slcconf1; +#[doc = "SLC_RX_DSCR_CONF (rw) register accessor: DMA slave to host configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`slc_rx_dscr_conf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc_rx_dscr_conf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc_rx_dscr_conf`] module"] +pub type SLC_RX_DSCR_CONF = crate::Reg; +#[doc = "DMA slave to host configuration register"] +pub mod slc_rx_dscr_conf; +#[doc = "SLC0_LEN_CONF (w) register accessor: Length control of transmitting packets\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc0_len_conf::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc0_len_conf`] module"] +pub type SLC0_LEN_CONF = crate::Reg; +#[doc = "Length control of transmitting packets"] +pub mod slc0_len_conf; +#[doc = "SLC0_TX_SHAREMEM_START (rw) register accessor: SLC0 AHB TX start address range\n\nYou can [`read`](crate::Reg::read) this register and get [`slc0_tx_sharemem_start::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc0_tx_sharemem_start::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc0_tx_sharemem_start`] module"] +pub type SLC0_TX_SHAREMEM_START = crate::Reg; +#[doc = "SLC0 AHB TX start address range"] +pub mod slc0_tx_sharemem_start; +#[doc = "SLC0_TX_SHAREMEM_END (rw) register accessor: SLC0 AHB TX end address range\n\nYou can [`read`](crate::Reg::read) this register and get [`slc0_tx_sharemem_end::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc0_tx_sharemem_end::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc0_tx_sharemem_end`] module"] +pub type SLC0_TX_SHAREMEM_END = crate::Reg; +#[doc = "SLC0 AHB TX end address range"] +pub mod slc0_tx_sharemem_end; +#[doc = "SLC0_RX_SHAREMEM_START (rw) register accessor: SLC0 AHB RX start address range\n\nYou can [`read`](crate::Reg::read) this register and get [`slc0_rx_sharemem_start::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc0_rx_sharemem_start::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc0_rx_sharemem_start`] module"] +pub type SLC0_RX_SHAREMEM_START = crate::Reg; +#[doc = "SLC0 AHB RX start address range"] +pub mod slc0_rx_sharemem_start; +#[doc = "SLC0_RX_SHAREMEM_END (rw) register accessor: SLC0 AHB RX end address range\n\nYou can [`read`](crate::Reg::read) this register and get [`slc0_rx_sharemem_end::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc0_rx_sharemem_end::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc0_rx_sharemem_end`] module"] +pub type SLC0_RX_SHAREMEM_END = crate::Reg; +#[doc = "SLC0 AHB RX end address range"] +pub mod slc0_rx_sharemem_end; +#[doc = "SLC1_TX_SHAREMEM_START (rw) register accessor: SLC1 AHB TX start address range\n\nYou can [`read`](crate::Reg::read) this register and get [`slc1_tx_sharemem_start::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc1_tx_sharemem_start::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc1_tx_sharemem_start`] module"] +pub type SLC1_TX_SHAREMEM_START = crate::Reg; +#[doc = "SLC1 AHB TX start address range"] +pub mod slc1_tx_sharemem_start; +#[doc = "SLC1_TX_SHAREMEM_END (rw) register accessor: SLC1 AHB TX end address range\n\nYou can [`read`](crate::Reg::read) this register and get [`slc1_tx_sharemem_end::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc1_tx_sharemem_end::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc1_tx_sharemem_end`] module"] +pub type SLC1_TX_SHAREMEM_END = crate::Reg; +#[doc = "SLC1 AHB TX end address range"] +pub mod slc1_tx_sharemem_end; +#[doc = "SLC1_RX_SHAREMEM_START (rw) register accessor: SLC1 AHB RX start address range\n\nYou can [`read`](crate::Reg::read) this register and get [`slc1_rx_sharemem_start::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc1_rx_sharemem_start::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc1_rx_sharemem_start`] module"] +pub type SLC1_RX_SHAREMEM_START = crate::Reg; +#[doc = "SLC1 AHB RX start address range"] +pub mod slc1_rx_sharemem_start; +#[doc = "SLC1_RX_SHAREMEM_END (rw) register accessor: SLC1 AHB RX end address range\n\nYou can [`read`](crate::Reg::read) this register and get [`slc1_rx_sharemem_end::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc1_rx_sharemem_end::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc1_rx_sharemem_end`] module"] +pub type SLC1_RX_SHAREMEM_END = crate::Reg; +#[doc = "SLC1 AHB RX end address range"] +pub mod slc1_rx_sharemem_end; +#[doc = "SLC_BURST_LEN (rw) register accessor: DMA AHB burst type configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`slc_burst_len::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc_burst_len::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc_burst_len`] module"] +pub type SLC_BURST_LEN = crate::Reg; +#[doc = "DMA AHB burst type configuration"] +pub mod slc_burst_len; +#[doc = "SLC0INT_RAW (rw) register accessor: SLC0 to slave raw interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`slc0int_raw::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc0int_raw::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc0int_raw`] module"] +pub type SLC0INT_RAW = crate::Reg; +#[doc = "SLC0 to slave raw interrupt status"] +pub mod slc0int_raw; +#[doc = "SLC0INT_ST (r) register accessor: SLC0 to slave masked interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`slc0int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc0int_st`] module"] +pub type SLC0INT_ST = crate::Reg; +#[doc = "SLC0 to slave masked interrupt status"] +pub mod slc0int_st; +#[doc = "SLC0INT_ENA (rw) register accessor: SLC0 to slave interrupt enable\n\nYou can [`read`](crate::Reg::read) this register and get [`slc0int_ena::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc0int_ena::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc0int_ena`] module"] +pub type SLC0INT_ENA = crate::Reg; +#[doc = "SLC0 to slave interrupt enable"] +pub mod slc0int_ena; +#[doc = "SLC0INT_CLR (w) register accessor: SLC0 to slave interrupt clear\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc0int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc0int_clr`] module"] +pub type SLC0INT_CLR = crate::Reg; +#[doc = "SLC0 to slave interrupt clear"] +pub mod slc0int_clr; +#[doc = "SLC1INT_RAW (rw) register accessor: SLC1 to slave raw interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`slc1int_raw::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc1int_raw::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc1int_raw`] module"] +pub type SLC1INT_RAW = crate::Reg; +#[doc = "SLC1 to slave raw interrupt status"] +pub mod slc1int_raw; +#[doc = "SLC1INT_CLR (w) register accessor: SLC1 to slave interrupt clear\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc1int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc1int_clr`] module"] +pub type SLC1INT_CLR = crate::Reg; +#[doc = "SLC1 to slave interrupt clear"] +pub mod slc1int_clr; +#[doc = "SLCINTVEC_TOHOST (w) register accessor: Slave to host interrupt vector set\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slcintvec_tohost::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slcintvec_tohost`] module"] +pub type SLCINTVEC_TOHOST = crate::Reg; +#[doc = "Slave to host interrupt vector set"] +pub mod slcintvec_tohost; +#[doc = "SLC1INT_ST1 (r) register accessor: SLC1 to slave masked interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`slc1int_st1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc1int_st1`] module"] +pub type SLC1INT_ST1 = crate::Reg; +#[doc = "SLC1 to slave masked interrupt status"] +pub mod slc1int_st1; +#[doc = "SLC1INT_ENA1 (rw) register accessor: SLC1 to slave interrupt enable\n\nYou can [`read`](crate::Reg::read) this register and get [`slc1int_ena1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc1int_ena1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc1int_ena1`] module"] +pub type SLC1INT_ENA1 = crate::Reg; +#[doc = "SLC1 to slave interrupt enable"] +pub mod slc1int_ena1; +#[doc = "SLC10_LENGTH (r) register accessor: Length of transmitting packets\n\nYou can [`read`](crate::Reg::read) this register and get [`slc10_length::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc10_length`] module"] +pub type SLC10_LENGTH = crate::Reg; +#[doc = "Length of transmitting packets"] +pub mod slc10_length; diff --git a/esp32c6/src/slc/slc0_len_conf.rs b/esp32c6/src/slc/slc0_len_conf.rs new file mode 100644 index 000000000..d5c88d164 --- /dev/null +++ b/esp32c6/src/slc/slc0_len_conf.rs @@ -0,0 +1,53 @@ +#[doc = "Register `SLC0_LEN_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `SDIO_SLC0_LEN_WDATA` writer - Configures the length of the data that the slave wants to send."] +pub type SDIO_SLC0_LEN_WDATA_W<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>; +#[doc = "Field `SDIO_SLC0_LEN_WR` writer - Configures this bit to 1 to write SDIO_SLC0_LEN_WDATA into SDIO_SLC0_LEN and SLCHOST_HOSTSLCHOST_SLC0_LEN."] +pub type SDIO_SLC0_LEN_WR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC0_LEN_INC` writer - Configures this bit to 1 to add 1 to SDIO_SLC0_LEN and SLCHOST_HOSTSLCHOST_SLC0_LEN."] +pub type SDIO_SLC0_LEN_INC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC0_LEN_INC_MORE` writer - Configures this bit to 1 to add the value of SDIO_SLC0_LEN_WDATA to SDIO_SLC0_LEN and SLCHOST_HOSTSLCHOST_SLC0_LEN."] +pub type SDIO_SLC0_LEN_INC_MORE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bits 0:19 - Configures the length of the data that the slave wants to send."] + #[inline(always)] + pub fn sdio_slc0_len_wdata(&mut self) -> SDIO_SLC0_LEN_WDATA_W { + SDIO_SLC0_LEN_WDATA_W::new(self, 0) + } + #[doc = "Bit 20 - Configures this bit to 1 to write SDIO_SLC0_LEN_WDATA into SDIO_SLC0_LEN and SLCHOST_HOSTSLCHOST_SLC0_LEN."] + #[inline(always)] + pub fn sdio_slc0_len_wr(&mut self) -> SDIO_SLC0_LEN_WR_W { + SDIO_SLC0_LEN_WR_W::new(self, 20) + } + #[doc = "Bit 21 - Configures this bit to 1 to add 1 to SDIO_SLC0_LEN and SLCHOST_HOSTSLCHOST_SLC0_LEN."] + #[inline(always)] + pub fn sdio_slc0_len_inc(&mut self) -> SDIO_SLC0_LEN_INC_W { + SDIO_SLC0_LEN_INC_W::new(self, 21) + } + #[doc = "Bit 22 - Configures this bit to 1 to add the value of SDIO_SLC0_LEN_WDATA to SDIO_SLC0_LEN and SLCHOST_HOSTSLCHOST_SLC0_LEN."] + #[inline(always)] + pub fn sdio_slc0_len_inc_more(&mut self) -> SDIO_SLC0_LEN_INC_MORE_W { + SDIO_SLC0_LEN_INC_MORE_W::new(self, 22) + } +} +#[doc = "Length control of transmitting packets\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc0_len_conf::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SLC0_LEN_CONF_SPEC; +impl crate::RegisterSpec for SLC0_LEN_CONF_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`slc0_len_conf::W`](W) writer structure"] +impl crate::Writable for SLC0_LEN_CONF_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SLC0_LEN_CONF to value 0x2000_0000"] +impl crate::Resettable for SLC0_LEN_CONF_SPEC { + const RESET_VALUE: u32 = 0x2000_0000; +} diff --git a/esp32c6/src/slc/slc0_rx_sharemem_end.rs b/esp32c6/src/slc/slc0_rx_sharemem_end.rs new file mode 100644 index 000000000..a66072984 --- /dev/null +++ b/esp32c6/src/slc/slc0_rx_sharemem_end.rs @@ -0,0 +1,52 @@ +#[doc = "Register `SLC0_RX_SHAREMEM_END` reader"] +pub type R = crate::R; +#[doc = "Register `SLC0_RX_SHAREMEM_END` writer"] +pub type W = crate::W; +#[doc = "Field `SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR` reader - Configures SLC0 slave to host channel AHB end address boundary."] +pub type SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR_R = crate::FieldReader; +#[doc = "Field `SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR` writer - Configures SLC0 slave to host channel AHB end address boundary."] +pub type SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Configures SLC0 slave to host channel AHB end address boundary."] + #[inline(always)] + pub fn sdio_sdio_slc0_rx_sharemem_end_addr(&self) -> SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR_R { + SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SLC0_RX_SHAREMEM_END") + .field( + "sdio_sdio_slc0_rx_sharemem_end_addr", + &self.sdio_sdio_slc0_rx_sharemem_end_addr(), + ) + .finish() + } +} +impl W { + #[doc = "Bits 0:31 - Configures SLC0 slave to host channel AHB end address boundary."] + #[inline(always)] + pub fn sdio_sdio_slc0_rx_sharemem_end_addr( + &mut self, + ) -> SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR_W { + SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR_W::new(self, 0) + } +} +#[doc = "SLC0 AHB RX end address range\n\nYou can [`read`](crate::Reg::read) this register and get [`slc0_rx_sharemem_end::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc0_rx_sharemem_end::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SLC0_RX_SHAREMEM_END_SPEC; +impl crate::RegisterSpec for SLC0_RX_SHAREMEM_END_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`slc0_rx_sharemem_end::R`](R) reader structure"] +impl crate::Readable for SLC0_RX_SHAREMEM_END_SPEC {} +#[doc = "`write(|w| ..)` method takes [`slc0_rx_sharemem_end::W`](W) writer structure"] +impl crate::Writable for SLC0_RX_SHAREMEM_END_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SLC0_RX_SHAREMEM_END to value 0xffff_ffff"] +impl crate::Resettable for SLC0_RX_SHAREMEM_END_SPEC { + const RESET_VALUE: u32 = 0xffff_ffff; +} diff --git a/esp32c6/src/slc/slc0_rx_sharemem_start.rs b/esp32c6/src/slc/slc0_rx_sharemem_start.rs new file mode 100644 index 000000000..20211d764 --- /dev/null +++ b/esp32c6/src/slc/slc0_rx_sharemem_start.rs @@ -0,0 +1,52 @@ +#[doc = "Register `SLC0_RX_SHAREMEM_START` reader"] +pub type R = crate::R; +#[doc = "Register `SLC0_RX_SHAREMEM_START` writer"] +pub type W = crate::W; +#[doc = "Field `SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR` reader - Configures SLC0 slave to host channel AHB start address boundary."] +pub type SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR_R = crate::FieldReader; +#[doc = "Field `SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR` writer - Configures SLC0 slave to host channel AHB start address boundary."] +pub type SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Configures SLC0 slave to host channel AHB start address boundary."] + #[inline(always)] + pub fn sdio_sdio_slc0_rx_sharemem_start_addr(&self) -> SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR_R { + SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SLC0_RX_SHAREMEM_START") + .field( + "sdio_sdio_slc0_rx_sharemem_start_addr", + &self.sdio_sdio_slc0_rx_sharemem_start_addr(), + ) + .finish() + } +} +impl W { + #[doc = "Bits 0:31 - Configures SLC0 slave to host channel AHB start address boundary."] + #[inline(always)] + pub fn sdio_sdio_slc0_rx_sharemem_start_addr( + &mut self, + ) -> SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR_W { + SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR_W::new(self, 0) + } +} +#[doc = "SLC0 AHB RX start address range\n\nYou can [`read`](crate::Reg::read) this register and get [`slc0_rx_sharemem_start::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc0_rx_sharemem_start::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SLC0_RX_SHAREMEM_START_SPEC; +impl crate::RegisterSpec for SLC0_RX_SHAREMEM_START_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`slc0_rx_sharemem_start::R`](R) reader structure"] +impl crate::Readable for SLC0_RX_SHAREMEM_START_SPEC {} +#[doc = "`write(|w| ..)` method takes [`slc0_rx_sharemem_start::W`](W) writer structure"] +impl crate::Writable for SLC0_RX_SHAREMEM_START_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SLC0_RX_SHAREMEM_START to value 0"] +impl crate::Resettable for SLC0_RX_SHAREMEM_START_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32c6/src/slc/slc0_tx_sharemem_end.rs b/esp32c6/src/slc/slc0_tx_sharemem_end.rs new file mode 100644 index 000000000..7921f1964 --- /dev/null +++ b/esp32c6/src/slc/slc0_tx_sharemem_end.rs @@ -0,0 +1,52 @@ +#[doc = "Register `SLC0_TX_SHAREMEM_END` reader"] +pub type R = crate::R; +#[doc = "Register `SLC0_TX_SHAREMEM_END` writer"] +pub type W = crate::W; +#[doc = "Field `SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR` reader - Configures SLC0 host to slave channel AHB end address boundary."] +pub type SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR_R = crate::FieldReader; +#[doc = "Field `SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR` writer - Configures SLC0 host to slave channel AHB end address boundary."] +pub type SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Configures SLC0 host to slave channel AHB end address boundary."] + #[inline(always)] + pub fn sdio_sdio_slc0_tx_sharemem_end_addr(&self) -> SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR_R { + SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SLC0_TX_SHAREMEM_END") + .field( + "sdio_sdio_slc0_tx_sharemem_end_addr", + &self.sdio_sdio_slc0_tx_sharemem_end_addr(), + ) + .finish() + } +} +impl W { + #[doc = "Bits 0:31 - Configures SLC0 host to slave channel AHB end address boundary."] + #[inline(always)] + pub fn sdio_sdio_slc0_tx_sharemem_end_addr( + &mut self, + ) -> SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR_W { + SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR_W::new(self, 0) + } +} +#[doc = "SLC0 AHB TX end address range\n\nYou can [`read`](crate::Reg::read) this register and get [`slc0_tx_sharemem_end::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc0_tx_sharemem_end::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SLC0_TX_SHAREMEM_END_SPEC; +impl crate::RegisterSpec for SLC0_TX_SHAREMEM_END_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`slc0_tx_sharemem_end::R`](R) reader structure"] +impl crate::Readable for SLC0_TX_SHAREMEM_END_SPEC {} +#[doc = "`write(|w| ..)` method takes [`slc0_tx_sharemem_end::W`](W) writer structure"] +impl crate::Writable for SLC0_TX_SHAREMEM_END_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SLC0_TX_SHAREMEM_END to value 0xffff_ffff"] +impl crate::Resettable for SLC0_TX_SHAREMEM_END_SPEC { + const RESET_VALUE: u32 = 0xffff_ffff; +} diff --git a/esp32c6/src/slc/slc0_tx_sharemem_start.rs b/esp32c6/src/slc/slc0_tx_sharemem_start.rs new file mode 100644 index 000000000..12f61e94a --- /dev/null +++ b/esp32c6/src/slc/slc0_tx_sharemem_start.rs @@ -0,0 +1,52 @@ +#[doc = "Register `SLC0_TX_SHAREMEM_START` reader"] +pub type R = crate::R; +#[doc = "Register `SLC0_TX_SHAREMEM_START` writer"] +pub type W = crate::W; +#[doc = "Field `SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR` reader - Configures SLC0 host to slave channel AHB start address boundary."] +pub type SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR_R = crate::FieldReader; +#[doc = "Field `SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR` writer - Configures SLC0 host to slave channel AHB start address boundary."] +pub type SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Configures SLC0 host to slave channel AHB start address boundary."] + #[inline(always)] + pub fn sdio_sdio_slc0_tx_sharemem_start_addr(&self) -> SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR_R { + SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SLC0_TX_SHAREMEM_START") + .field( + "sdio_sdio_slc0_tx_sharemem_start_addr", + &self.sdio_sdio_slc0_tx_sharemem_start_addr(), + ) + .finish() + } +} +impl W { + #[doc = "Bits 0:31 - Configures SLC0 host to slave channel AHB start address boundary."] + #[inline(always)] + pub fn sdio_sdio_slc0_tx_sharemem_start_addr( + &mut self, + ) -> SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR_W { + SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR_W::new(self, 0) + } +} +#[doc = "SLC0 AHB TX start address range\n\nYou can [`read`](crate::Reg::read) this register and get [`slc0_tx_sharemem_start::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc0_tx_sharemem_start::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SLC0_TX_SHAREMEM_START_SPEC; +impl crate::RegisterSpec for SLC0_TX_SHAREMEM_START_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`slc0_tx_sharemem_start::R`](R) reader structure"] +impl crate::Readable for SLC0_TX_SHAREMEM_START_SPEC {} +#[doc = "`write(|w| ..)` method takes [`slc0_tx_sharemem_start::W`](W) writer structure"] +impl crate::Writable for SLC0_TX_SHAREMEM_START_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SLC0_TX_SHAREMEM_START to value 0"] +impl crate::Resettable for SLC0_TX_SHAREMEM_START_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32c6/src/slc/slc0int_clr.rs b/esp32c6/src/slc/slc0int_clr.rs new file mode 100644 index 000000000..c10d411e9 --- /dev/null +++ b/esp32c6/src/slc/slc0int_clr.rs @@ -0,0 +1,175 @@ +#[doc = "Register `SLC0INT_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `SDIO_SLC_FRHOST_BIT_INT_CLR(0-7)` writer - Write 1 to clear interrupt SLC_FRHOST_BITn_INT (n: 0-7)."] +pub type SDIO_SLC_FRHOST_BIT_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC0_RX_CLRART_INT_CLR` writer - Write 1 to clear interrupt SLC0_RX_CLRART_INT."] +pub type SDIO_SLC0_RX_CLRART_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC0_TX_CLRART_INT_CLR` writer - Write 1 to clear interrupt SLC0_TX_CLRART_INT."] +pub type SDIO_SLC0_TX_CLRART_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC0_RX_UDF_INT_CLR` writer - Write 1 to clear interrupt SLC0_RX_UDF_INT."] +pub type SDIO_SLC0_RX_UDF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC0_TX_OVF_INT_CLR` writer - Write 1 to clear interrupt SLC0_TX_OVF_INT."] +pub type SDIO_SLC0_TX_OVF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC0_TX_DONE_INT_CLR` writer - Write 1 to clear interrupt SLC0_TX_DONE_INT."] +pub type SDIO_SLC0_TX_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC0_TX_SUC_EOF_INT_CLR` writer - Write 1 to clear interrupt SLC0_TX_SUC_EOF_INT."] +pub type SDIO_SLC0_TX_SUC_EOF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC0_RX_DONE_INT_CLR` writer - Write 1 to clear interrupt SLC0_RX_DONE_INT."] +pub type SDIO_SLC0_RX_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC0_RX_EOF_INT_CLR` writer - Write 1 to clear interrupt SLC0_RX_EOF_INT."] +pub type SDIO_SLC0_RX_EOF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC0_TX_DSCR_ERR_INT_CLR` writer - Write 1 to clear interrupt SLC0_TX_DSCR_ERR_INT."] +pub type SDIO_SLC0_TX_DSCR_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC0_RX_DSCR_ERR_INT_CLR` writer - Write 1 to clear interrupt SLC0_RX_DSCR_ERR_INT."] +pub type SDIO_SLC0_RX_DSCR_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Write 1 to clear interrupt SLC_FRHOST_BITn_INT (n: 0-7)."] + #[doc = ""] + #[doc = "
`n` is number of field in register. `n == 0` corresponds to `SDIO_SLC_FRHOST_BIT0_INT_CLR` field.
"] + #[inline(always)] + pub fn sdio_slc_frhost_bit_int_clr( + &mut self, + n: u8, + ) -> SDIO_SLC_FRHOST_BIT_INT_CLR_W { + #[allow(clippy::no_effect)] + [(); 8][n as usize]; + SDIO_SLC_FRHOST_BIT_INT_CLR_W::new(self, n) + } + #[doc = "Bit 0 - Write 1 to clear interrupt SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit0_int_clr( + &mut self, + ) -> SDIO_SLC_FRHOST_BIT_INT_CLR_W { + SDIO_SLC_FRHOST_BIT_INT_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - Write 1 to clear interrupt SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit1_int_clr( + &mut self, + ) -> SDIO_SLC_FRHOST_BIT_INT_CLR_W { + SDIO_SLC_FRHOST_BIT_INT_CLR_W::new(self, 1) + } + #[doc = "Bit 2 - Write 1 to clear interrupt SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit2_int_clr( + &mut self, + ) -> SDIO_SLC_FRHOST_BIT_INT_CLR_W { + SDIO_SLC_FRHOST_BIT_INT_CLR_W::new(self, 2) + } + #[doc = "Bit 3 - Write 1 to clear interrupt SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit3_int_clr( + &mut self, + ) -> SDIO_SLC_FRHOST_BIT_INT_CLR_W { + SDIO_SLC_FRHOST_BIT_INT_CLR_W::new(self, 3) + } + #[doc = "Bit 4 - Write 1 to clear interrupt SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit4_int_clr( + &mut self, + ) -> SDIO_SLC_FRHOST_BIT_INT_CLR_W { + SDIO_SLC_FRHOST_BIT_INT_CLR_W::new(self, 4) + } + #[doc = "Bit 5 - Write 1 to clear interrupt SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit5_int_clr( + &mut self, + ) -> SDIO_SLC_FRHOST_BIT_INT_CLR_W { + SDIO_SLC_FRHOST_BIT_INT_CLR_W::new(self, 5) + } + #[doc = "Bit 6 - Write 1 to clear interrupt SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit6_int_clr( + &mut self, + ) -> SDIO_SLC_FRHOST_BIT_INT_CLR_W { + SDIO_SLC_FRHOST_BIT_INT_CLR_W::new(self, 6) + } + #[doc = "Bit 7 - Write 1 to clear interrupt SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit7_int_clr( + &mut self, + ) -> SDIO_SLC_FRHOST_BIT_INT_CLR_W { + SDIO_SLC_FRHOST_BIT_INT_CLR_W::new(self, 7) + } + #[doc = "Bit 8 - Write 1 to clear interrupt SLC0_RX_CLRART_INT."] + #[inline(always)] + pub fn sdio_slc0_rx_clrart_int_clr( + &mut self, + ) -> SDIO_SLC0_RX_CLRART_INT_CLR_W { + SDIO_SLC0_RX_CLRART_INT_CLR_W::new(self, 8) + } + #[doc = "Bit 9 - Write 1 to clear interrupt SLC0_TX_CLRART_INT."] + #[inline(always)] + pub fn sdio_slc0_tx_clrart_int_clr( + &mut self, + ) -> SDIO_SLC0_TX_CLRART_INT_CLR_W { + SDIO_SLC0_TX_CLRART_INT_CLR_W::new(self, 9) + } + #[doc = "Bit 10 - Write 1 to clear interrupt SLC0_RX_UDF_INT."] + #[inline(always)] + pub fn sdio_slc0_rx_udf_int_clr(&mut self) -> SDIO_SLC0_RX_UDF_INT_CLR_W { + SDIO_SLC0_RX_UDF_INT_CLR_W::new(self, 10) + } + #[doc = "Bit 11 - Write 1 to clear interrupt SLC0_TX_OVF_INT."] + #[inline(always)] + pub fn sdio_slc0_tx_ovf_int_clr(&mut self) -> SDIO_SLC0_TX_OVF_INT_CLR_W { + SDIO_SLC0_TX_OVF_INT_CLR_W::new(self, 11) + } + #[doc = "Bit 14 - Write 1 to clear interrupt SLC0_TX_DONE_INT."] + #[inline(always)] + pub fn sdio_slc0_tx_done_int_clr(&mut self) -> SDIO_SLC0_TX_DONE_INT_CLR_W { + SDIO_SLC0_TX_DONE_INT_CLR_W::new(self, 14) + } + #[doc = "Bit 15 - Write 1 to clear interrupt SLC0_TX_SUC_EOF_INT."] + #[inline(always)] + pub fn sdio_slc0_tx_suc_eof_int_clr( + &mut self, + ) -> SDIO_SLC0_TX_SUC_EOF_INT_CLR_W { + SDIO_SLC0_TX_SUC_EOF_INT_CLR_W::new(self, 15) + } + #[doc = "Bit 16 - Write 1 to clear interrupt SLC0_RX_DONE_INT."] + #[inline(always)] + pub fn sdio_slc0_rx_done_int_clr(&mut self) -> SDIO_SLC0_RX_DONE_INT_CLR_W { + SDIO_SLC0_RX_DONE_INT_CLR_W::new(self, 16) + } + #[doc = "Bit 17 - Write 1 to clear interrupt SLC0_RX_EOF_INT."] + #[inline(always)] + pub fn sdio_slc0_rx_eof_int_clr(&mut self) -> SDIO_SLC0_RX_EOF_INT_CLR_W { + SDIO_SLC0_RX_EOF_INT_CLR_W::new(self, 17) + } + #[doc = "Bit 19 - Write 1 to clear interrupt SLC0_TX_DSCR_ERR_INT."] + #[inline(always)] + pub fn sdio_slc0_tx_dscr_err_int_clr( + &mut self, + ) -> SDIO_SLC0_TX_DSCR_ERR_INT_CLR_W { + SDIO_SLC0_TX_DSCR_ERR_INT_CLR_W::new(self, 19) + } + #[doc = "Bit 20 - Write 1 to clear interrupt SLC0_RX_DSCR_ERR_INT."] + #[inline(always)] + pub fn sdio_slc0_rx_dscr_err_int_clr( + &mut self, + ) -> SDIO_SLC0_RX_DSCR_ERR_INT_CLR_W { + SDIO_SLC0_RX_DSCR_ERR_INT_CLR_W::new(self, 20) + } +} +#[doc = "SLC0 to slave interrupt clear\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc0int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SLC0INT_CLR_SPEC; +impl crate::RegisterSpec for SLC0INT_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`slc0int_clr::W`](W) writer structure"] +impl crate::Writable for SLC0INT_CLR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SLC0INT_CLR to value 0"] +impl crate::Resettable for SLC0INT_CLR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32c6/src/slc/slc0int_ena.rs b/esp32c6/src/slc/slc0int_ena.rs new file mode 100644 index 000000000..e44957c0e --- /dev/null +++ b/esp32c6/src/slc/slc0int_ena.rs @@ -0,0 +1,374 @@ +#[doc = "Register `SLC0INT_ENA` reader"] +pub type R = crate::R; +#[doc = "Register `SLC0INT_ENA` writer"] +pub type W = crate::W; +#[doc = "Field `SDIO_SLC_FRHOST_BIT_INT_ENA(0-7)` reader - Write 1 to enable interrupt SLC_FRHOST_BITn_INT (n: 0-7)."] +pub type SDIO_SLC_FRHOST_BIT_INT_ENA_R = crate::BitReader; +#[doc = "Field `SDIO_SLC_FRHOST_BIT_INT_ENA(0-7)` writer - Write 1 to enable interrupt SLC_FRHOST_BITn_INT (n: 0-7)."] +pub type SDIO_SLC_FRHOST_BIT_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC0_RX_ENAART_INT_ENA` reader - Write 1 to enable interrupt SLC0_RX_ENAART_INT."] +pub type SDIO_SLC0_RX_ENAART_INT_ENA_R = crate::BitReader; +#[doc = "Field `SDIO_SLC0_RX_ENAART_INT_ENA` writer - Write 1 to enable interrupt SLC0_RX_ENAART_INT."] +pub type SDIO_SLC0_RX_ENAART_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC0_TX_ENAART_INT_ENA` reader - Write 1 to enable interrupt SLC0_TX_ENAART_INT."] +pub type SDIO_SLC0_TX_ENAART_INT_ENA_R = crate::BitReader; +#[doc = "Field `SDIO_SLC0_TX_ENAART_INT_ENA` writer - Write 1 to enable interrupt SLC0_TX_ENAART_INT."] +pub type SDIO_SLC0_TX_ENAART_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC0_RX_UDF_INT_ENA` reader - Write 1 to enable interrupt SLC0_RX_UDF_INT."] +pub type SDIO_SLC0_RX_UDF_INT_ENA_R = crate::BitReader; +#[doc = "Field `SDIO_SLC0_RX_UDF_INT_ENA` writer - Write 1 to enable interrupt SLC0_RX_UDF_INT."] +pub type SDIO_SLC0_RX_UDF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC0_TX_OVF_INT_ENA` reader - Write 1 to enable interrupt SLC0_TX_OVF_INT."] +pub type SDIO_SLC0_TX_OVF_INT_ENA_R = crate::BitReader; +#[doc = "Field `SDIO_SLC0_TX_OVF_INT_ENA` writer - Write 1 to enable interrupt SLC0_TX_OVF_INT."] +pub type SDIO_SLC0_TX_OVF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC0_TX_DONE_INT_ENA` reader - Write 1 to enable interrupt SLC0_TX_DONE_INT."] +pub type SDIO_SLC0_TX_DONE_INT_ENA_R = crate::BitReader; +#[doc = "Field `SDIO_SLC0_TX_DONE_INT_ENA` writer - Write 1 to enable interrupt SLC0_TX_DONE_INT."] +pub type SDIO_SLC0_TX_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC0_TX_SUC_EOF_INT_ENA` reader - Write 1 to enable interrupt SLC0_TX_SUC_EOF_INT."] +pub type SDIO_SLC0_TX_SUC_EOF_INT_ENA_R = crate::BitReader; +#[doc = "Field `SDIO_SLC0_TX_SUC_EOF_INT_ENA` writer - Write 1 to enable interrupt SLC0_TX_SUC_EOF_INT."] +pub type SDIO_SLC0_TX_SUC_EOF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC0_RX_DONE_INT_ENA` reader - Write 1 to enable interrupt SLC0_RX_DONE_INT."] +pub type SDIO_SLC0_RX_DONE_INT_ENA_R = crate::BitReader; +#[doc = "Field `SDIO_SLC0_RX_DONE_INT_ENA` writer - Write 1 to enable interrupt SLC0_RX_DONE_INT."] +pub type SDIO_SLC0_RX_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC0_RX_EOF_INT_ENA` reader - Write 1 to enable interrupt SLC0_RX_EOF_INT."] +pub type SDIO_SLC0_RX_EOF_INT_ENA_R = crate::BitReader; +#[doc = "Field `SDIO_SLC0_RX_EOF_INT_ENA` writer - Write 1 to enable interrupt SLC0_RX_EOF_INT."] +pub type SDIO_SLC0_RX_EOF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC0_TX_DSCR_ERR_INT_ENA` reader - Write 1 to enable interrupt SLC0_TX_DSCR_ERR_INT."] +pub type SDIO_SLC0_TX_DSCR_ERR_INT_ENA_R = crate::BitReader; +#[doc = "Field `SDIO_SLC0_TX_DSCR_ERR_INT_ENA` writer - Write 1 to enable interrupt SLC0_TX_DSCR_ERR_INT."] +pub type SDIO_SLC0_TX_DSCR_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC0_RX_DSCR_ERR_INT_ENA` reader - Write 1 to enable interrupt SLC0_RX_DSCR_ERR_INT."] +pub type SDIO_SLC0_RX_DSCR_ERR_INT_ENA_R = crate::BitReader; +#[doc = "Field `SDIO_SLC0_RX_DSCR_ERR_INT_ENA` writer - Write 1 to enable interrupt SLC0_RX_DSCR_ERR_INT."] +pub type SDIO_SLC0_RX_DSCR_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Write 1 to enable interrupt SLC_FRHOST_BITn_INT (n: 0-7)."] + #[doc = ""] + #[doc = "
`n` is number of field in register. `n == 0` corresponds to `SDIO_SLC_FRHOST_BIT0_INT_ENA` field.
"] + #[inline(always)] + pub fn sdio_slc_frhost_bit_int_ena(&self, n: u8) -> SDIO_SLC_FRHOST_BIT_INT_ENA_R { + #[allow(clippy::no_effect)] + [(); 8][n as usize]; + SDIO_SLC_FRHOST_BIT_INT_ENA_R::new(((self.bits >> n) & 1) != 0) + } + #[doc = "Iterator for array of:"] + #[doc = "Write 1 to enable interrupt SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit_int_ena_iter( + &self, + ) -> impl Iterator + '_ { + (0..8).map(move |n| SDIO_SLC_FRHOST_BIT_INT_ENA_R::new(((self.bits >> n) & 1) != 0)) + } + #[doc = "Bit 0 - Write 1 to enable interrupt SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit0_int_ena(&self) -> SDIO_SLC_FRHOST_BIT_INT_ENA_R { + SDIO_SLC_FRHOST_BIT_INT_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Write 1 to enable interrupt SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit1_int_ena(&self) -> SDIO_SLC_FRHOST_BIT_INT_ENA_R { + SDIO_SLC_FRHOST_BIT_INT_ENA_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Write 1 to enable interrupt SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit2_int_ena(&self) -> SDIO_SLC_FRHOST_BIT_INT_ENA_R { + SDIO_SLC_FRHOST_BIT_INT_ENA_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Write 1 to enable interrupt SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit3_int_ena(&self) -> SDIO_SLC_FRHOST_BIT_INT_ENA_R { + SDIO_SLC_FRHOST_BIT_INT_ENA_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Write 1 to enable interrupt SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit4_int_ena(&self) -> SDIO_SLC_FRHOST_BIT_INT_ENA_R { + SDIO_SLC_FRHOST_BIT_INT_ENA_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Write 1 to enable interrupt SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit5_int_ena(&self) -> SDIO_SLC_FRHOST_BIT_INT_ENA_R { + SDIO_SLC_FRHOST_BIT_INT_ENA_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Write 1 to enable interrupt SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit6_int_ena(&self) -> SDIO_SLC_FRHOST_BIT_INT_ENA_R { + SDIO_SLC_FRHOST_BIT_INT_ENA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Write 1 to enable interrupt SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit7_int_ena(&self) -> SDIO_SLC_FRHOST_BIT_INT_ENA_R { + SDIO_SLC_FRHOST_BIT_INT_ENA_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Write 1 to enable interrupt SLC0_RX_ENAART_INT."] + #[inline(always)] + pub fn sdio_slc0_rx_enaart_int_ena(&self) -> SDIO_SLC0_RX_ENAART_INT_ENA_R { + SDIO_SLC0_RX_ENAART_INT_ENA_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Write 1 to enable interrupt SLC0_TX_ENAART_INT."] + #[inline(always)] + pub fn sdio_slc0_tx_enaart_int_ena(&self) -> SDIO_SLC0_TX_ENAART_INT_ENA_R { + SDIO_SLC0_TX_ENAART_INT_ENA_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Write 1 to enable interrupt SLC0_RX_UDF_INT."] + #[inline(always)] + pub fn sdio_slc0_rx_udf_int_ena(&self) -> SDIO_SLC0_RX_UDF_INT_ENA_R { + SDIO_SLC0_RX_UDF_INT_ENA_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Write 1 to enable interrupt SLC0_TX_OVF_INT."] + #[inline(always)] + pub fn sdio_slc0_tx_ovf_int_ena(&self) -> SDIO_SLC0_TX_OVF_INT_ENA_R { + SDIO_SLC0_TX_OVF_INT_ENA_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 14 - Write 1 to enable interrupt SLC0_TX_DONE_INT."] + #[inline(always)] + pub fn sdio_slc0_tx_done_int_ena(&self) -> SDIO_SLC0_TX_DONE_INT_ENA_R { + SDIO_SLC0_TX_DONE_INT_ENA_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Write 1 to enable interrupt SLC0_TX_SUC_EOF_INT."] + #[inline(always)] + pub fn sdio_slc0_tx_suc_eof_int_ena(&self) -> SDIO_SLC0_TX_SUC_EOF_INT_ENA_R { + SDIO_SLC0_TX_SUC_EOF_INT_ENA_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Write 1 to enable interrupt SLC0_RX_DONE_INT."] + #[inline(always)] + pub fn sdio_slc0_rx_done_int_ena(&self) -> SDIO_SLC0_RX_DONE_INT_ENA_R { + SDIO_SLC0_RX_DONE_INT_ENA_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Write 1 to enable interrupt SLC0_RX_EOF_INT."] + #[inline(always)] + pub fn sdio_slc0_rx_eof_int_ena(&self) -> SDIO_SLC0_RX_EOF_INT_ENA_R { + SDIO_SLC0_RX_EOF_INT_ENA_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 19 - Write 1 to enable interrupt SLC0_TX_DSCR_ERR_INT."] + #[inline(always)] + pub fn sdio_slc0_tx_dscr_err_int_ena(&self) -> SDIO_SLC0_TX_DSCR_ERR_INT_ENA_R { + SDIO_SLC0_TX_DSCR_ERR_INT_ENA_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Write 1 to enable interrupt SLC0_RX_DSCR_ERR_INT."] + #[inline(always)] + pub fn sdio_slc0_rx_dscr_err_int_ena(&self) -> SDIO_SLC0_RX_DSCR_ERR_INT_ENA_R { + SDIO_SLC0_RX_DSCR_ERR_INT_ENA_R::new(((self.bits >> 20) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SLC0INT_ENA") + .field( + "sdio_slc_frhost_bit0_int_ena", + &self.sdio_slc_frhost_bit0_int_ena(), + ) + .field( + "sdio_slc_frhost_bit1_int_ena", + &self.sdio_slc_frhost_bit1_int_ena(), + ) + .field( + "sdio_slc_frhost_bit2_int_ena", + &self.sdio_slc_frhost_bit2_int_ena(), + ) + .field( + "sdio_slc_frhost_bit3_int_ena", + &self.sdio_slc_frhost_bit3_int_ena(), + ) + .field( + "sdio_slc_frhost_bit4_int_ena", + &self.sdio_slc_frhost_bit4_int_ena(), + ) + .field( + "sdio_slc_frhost_bit5_int_ena", + &self.sdio_slc_frhost_bit5_int_ena(), + ) + .field( + "sdio_slc_frhost_bit6_int_ena", + &self.sdio_slc_frhost_bit6_int_ena(), + ) + .field( + "sdio_slc_frhost_bit7_int_ena", + &self.sdio_slc_frhost_bit7_int_ena(), + ) + .field( + "sdio_slc0_rx_enaart_int_ena", + &self.sdio_slc0_rx_enaart_int_ena(), + ) + .field( + "sdio_slc0_tx_enaart_int_ena", + &self.sdio_slc0_tx_enaart_int_ena(), + ) + .field("sdio_slc0_rx_udf_int_ena", &self.sdio_slc0_rx_udf_int_ena()) + .field("sdio_slc0_tx_ovf_int_ena", &self.sdio_slc0_tx_ovf_int_ena()) + .field( + "sdio_slc0_tx_done_int_ena", + &self.sdio_slc0_tx_done_int_ena(), + ) + .field( + "sdio_slc0_tx_suc_eof_int_ena", + &self.sdio_slc0_tx_suc_eof_int_ena(), + ) + .field( + "sdio_slc0_rx_done_int_ena", + &self.sdio_slc0_rx_done_int_ena(), + ) + .field("sdio_slc0_rx_eof_int_ena", &self.sdio_slc0_rx_eof_int_ena()) + .field( + "sdio_slc0_tx_dscr_err_int_ena", + &self.sdio_slc0_tx_dscr_err_int_ena(), + ) + .field( + "sdio_slc0_rx_dscr_err_int_ena", + &self.sdio_slc0_rx_dscr_err_int_ena(), + ) + .finish() + } +} +impl W { + #[doc = "Write 1 to enable interrupt SLC_FRHOST_BITn_INT (n: 0-7)."] + #[doc = ""] + #[doc = "
`n` is number of field in register. `n == 0` corresponds to `SDIO_SLC_FRHOST_BIT0_INT_ENA` field.
"] + #[inline(always)] + pub fn sdio_slc_frhost_bit_int_ena( + &mut self, + n: u8, + ) -> SDIO_SLC_FRHOST_BIT_INT_ENA_W { + #[allow(clippy::no_effect)] + [(); 8][n as usize]; + SDIO_SLC_FRHOST_BIT_INT_ENA_W::new(self, n) + } + #[doc = "Bit 0 - Write 1 to enable interrupt SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit0_int_ena( + &mut self, + ) -> SDIO_SLC_FRHOST_BIT_INT_ENA_W { + SDIO_SLC_FRHOST_BIT_INT_ENA_W::new(self, 0) + } + #[doc = "Bit 1 - Write 1 to enable interrupt SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit1_int_ena( + &mut self, + ) -> SDIO_SLC_FRHOST_BIT_INT_ENA_W { + SDIO_SLC_FRHOST_BIT_INT_ENA_W::new(self, 1) + } + #[doc = "Bit 2 - Write 1 to enable interrupt SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit2_int_ena( + &mut self, + ) -> SDIO_SLC_FRHOST_BIT_INT_ENA_W { + SDIO_SLC_FRHOST_BIT_INT_ENA_W::new(self, 2) + } + #[doc = "Bit 3 - Write 1 to enable interrupt SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit3_int_ena( + &mut self, + ) -> SDIO_SLC_FRHOST_BIT_INT_ENA_W { + SDIO_SLC_FRHOST_BIT_INT_ENA_W::new(self, 3) + } + #[doc = "Bit 4 - Write 1 to enable interrupt SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit4_int_ena( + &mut self, + ) -> SDIO_SLC_FRHOST_BIT_INT_ENA_W { + SDIO_SLC_FRHOST_BIT_INT_ENA_W::new(self, 4) + } + #[doc = "Bit 5 - Write 1 to enable interrupt SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit5_int_ena( + &mut self, + ) -> SDIO_SLC_FRHOST_BIT_INT_ENA_W { + SDIO_SLC_FRHOST_BIT_INT_ENA_W::new(self, 5) + } + #[doc = "Bit 6 - Write 1 to enable interrupt SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit6_int_ena( + &mut self, + ) -> SDIO_SLC_FRHOST_BIT_INT_ENA_W { + SDIO_SLC_FRHOST_BIT_INT_ENA_W::new(self, 6) + } + #[doc = "Bit 7 - Write 1 to enable interrupt SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit7_int_ena( + &mut self, + ) -> SDIO_SLC_FRHOST_BIT_INT_ENA_W { + SDIO_SLC_FRHOST_BIT_INT_ENA_W::new(self, 7) + } + #[doc = "Bit 8 - Write 1 to enable interrupt SLC0_RX_ENAART_INT."] + #[inline(always)] + pub fn sdio_slc0_rx_enaart_int_ena( + &mut self, + ) -> SDIO_SLC0_RX_ENAART_INT_ENA_W { + SDIO_SLC0_RX_ENAART_INT_ENA_W::new(self, 8) + } + #[doc = "Bit 9 - Write 1 to enable interrupt SLC0_TX_ENAART_INT."] + #[inline(always)] + pub fn sdio_slc0_tx_enaart_int_ena( + &mut self, + ) -> SDIO_SLC0_TX_ENAART_INT_ENA_W { + SDIO_SLC0_TX_ENAART_INT_ENA_W::new(self, 9) + } + #[doc = "Bit 10 - Write 1 to enable interrupt SLC0_RX_UDF_INT."] + #[inline(always)] + pub fn sdio_slc0_rx_udf_int_ena(&mut self) -> SDIO_SLC0_RX_UDF_INT_ENA_W { + SDIO_SLC0_RX_UDF_INT_ENA_W::new(self, 10) + } + #[doc = "Bit 11 - Write 1 to enable interrupt SLC0_TX_OVF_INT."] + #[inline(always)] + pub fn sdio_slc0_tx_ovf_int_ena(&mut self) -> SDIO_SLC0_TX_OVF_INT_ENA_W { + SDIO_SLC0_TX_OVF_INT_ENA_W::new(self, 11) + } + #[doc = "Bit 14 - Write 1 to enable interrupt SLC0_TX_DONE_INT."] + #[inline(always)] + pub fn sdio_slc0_tx_done_int_ena(&mut self) -> SDIO_SLC0_TX_DONE_INT_ENA_W { + SDIO_SLC0_TX_DONE_INT_ENA_W::new(self, 14) + } + #[doc = "Bit 15 - Write 1 to enable interrupt SLC0_TX_SUC_EOF_INT."] + #[inline(always)] + pub fn sdio_slc0_tx_suc_eof_int_ena( + &mut self, + ) -> SDIO_SLC0_TX_SUC_EOF_INT_ENA_W { + SDIO_SLC0_TX_SUC_EOF_INT_ENA_W::new(self, 15) + } + #[doc = "Bit 16 - Write 1 to enable interrupt SLC0_RX_DONE_INT."] + #[inline(always)] + pub fn sdio_slc0_rx_done_int_ena(&mut self) -> SDIO_SLC0_RX_DONE_INT_ENA_W { + SDIO_SLC0_RX_DONE_INT_ENA_W::new(self, 16) + } + #[doc = "Bit 17 - Write 1 to enable interrupt SLC0_RX_EOF_INT."] + #[inline(always)] + pub fn sdio_slc0_rx_eof_int_ena(&mut self) -> SDIO_SLC0_RX_EOF_INT_ENA_W { + SDIO_SLC0_RX_EOF_INT_ENA_W::new(self, 17) + } + #[doc = "Bit 19 - Write 1 to enable interrupt SLC0_TX_DSCR_ERR_INT."] + #[inline(always)] + pub fn sdio_slc0_tx_dscr_err_int_ena( + &mut self, + ) -> SDIO_SLC0_TX_DSCR_ERR_INT_ENA_W { + SDIO_SLC0_TX_DSCR_ERR_INT_ENA_W::new(self, 19) + } + #[doc = "Bit 20 - Write 1 to enable interrupt SLC0_RX_DSCR_ERR_INT."] + #[inline(always)] + pub fn sdio_slc0_rx_dscr_err_int_ena( + &mut self, + ) -> SDIO_SLC0_RX_DSCR_ERR_INT_ENA_W { + SDIO_SLC0_RX_DSCR_ERR_INT_ENA_W::new(self, 20) + } +} +#[doc = "SLC0 to slave interrupt enable\n\nYou can [`read`](crate::Reg::read) this register and get [`slc0int_ena::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc0int_ena::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SLC0INT_ENA_SPEC; +impl crate::RegisterSpec for SLC0INT_ENA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`slc0int_ena::R`](R) reader structure"] +impl crate::Readable for SLC0INT_ENA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`slc0int_ena::W`](W) writer structure"] +impl crate::Writable for SLC0INT_ENA_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SLC0INT_ENA to value 0"] +impl crate::Resettable for SLC0INT_ENA_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32c6/src/slc/slc0int_raw.rs b/esp32c6/src/slc/slc0int_raw.rs new file mode 100644 index 000000000..2a3ec373d --- /dev/null +++ b/esp32c6/src/slc/slc0int_raw.rs @@ -0,0 +1,370 @@ +#[doc = "Register `SLC0INT_RAW` reader"] +pub type R = crate::R; +#[doc = "Register `SLC0INT_RAW` writer"] +pub type W = crate::W; +#[doc = "Field `SDIO_SLC_FRHOST_BIT_INT_RAW(0-7)` reader - The raw interrupt status of SLC_FRHOST_BITn_INT (n: 0-7)."] +pub type SDIO_SLC_FRHOST_BIT_INT_RAW_R = crate::BitReader; +#[doc = "Field `SDIO_SLC_FRHOST_BIT_INT_RAW(0-7)` writer - The raw interrupt status of SLC_FRHOST_BITn_INT (n: 0-7)."] +pub type SDIO_SLC_FRHOST_BIT_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC0_RX_START_INT_RAW` reader - The raw interrupt status of SLC0_RX_START_INT."] +pub type SDIO_SLC0_RX_START_INT_RAW_R = crate::BitReader; +#[doc = "Field `SDIO_SLC0_RX_START_INT_RAW` writer - The raw interrupt status of SLC0_RX_START_INT."] +pub type SDIO_SLC0_RX_START_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC0_TX_START_INT_RAW` reader - The raw interrupt status of SLC0_TX_START_INT."] +pub type SDIO_SLC0_TX_START_INT_RAW_R = crate::BitReader; +#[doc = "Field `SDIO_SLC0_TX_START_INT_RAW` writer - The raw interrupt status of SLC0_TX_START_INT."] +pub type SDIO_SLC0_TX_START_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC0_RX_UDF_INT_RAW` reader - The raw interrupt status of SLC0_RX_UDF_INT."] +pub type SDIO_SLC0_RX_UDF_INT_RAW_R = crate::BitReader; +#[doc = "Field `SDIO_SLC0_RX_UDF_INT_RAW` writer - The raw interrupt status of SLC0_RX_UDF_INT."] +pub type SDIO_SLC0_RX_UDF_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC0_TX_OVF_INT_RAW` reader - The raw interrupt status of SLC0_TX_OVF_INT."] +pub type SDIO_SLC0_TX_OVF_INT_RAW_R = crate::BitReader; +#[doc = "Field `SDIO_SLC0_TX_OVF_INT_RAW` writer - The raw interrupt status of SLC0_TX_OVF_INT."] +pub type SDIO_SLC0_TX_OVF_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC0_TX_DONE_INT_RAW` reader - The raw interrupt status of SLC0_TX_DONE_INT."] +pub type SDIO_SLC0_TX_DONE_INT_RAW_R = crate::BitReader; +#[doc = "Field `SDIO_SLC0_TX_DONE_INT_RAW` writer - The raw interrupt status of SLC0_TX_DONE_INT."] +pub type SDIO_SLC0_TX_DONE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC0_TX_SUC_EOF_INT_RAW` reader - The raw interrupt status of SLC0_TX_SUC_EOF_INT."] +pub type SDIO_SLC0_TX_SUC_EOF_INT_RAW_R = crate::BitReader; +#[doc = "Field `SDIO_SLC0_TX_SUC_EOF_INT_RAW` writer - The raw interrupt status of SLC0_TX_SUC_EOF_INT."] +pub type SDIO_SLC0_TX_SUC_EOF_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC0_RX_DONE_INT_RAW` reader - The raw interrupt status of SLC0_RX_DONE_INT."] +pub type SDIO_SLC0_RX_DONE_INT_RAW_R = crate::BitReader; +#[doc = "Field `SDIO_SLC0_RX_DONE_INT_RAW` writer - The raw interrupt status of SLC0_RX_DONE_INT."] +pub type SDIO_SLC0_RX_DONE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC0_RX_EOF_INT_RAW` reader - The raw interrupt status of SLC0_RX_EOF_INT."] +pub type SDIO_SLC0_RX_EOF_INT_RAW_R = crate::BitReader; +#[doc = "Field `SDIO_SLC0_RX_EOF_INT_RAW` writer - The raw interrupt status of SLC0_RX_EOF_INT."] +pub type SDIO_SLC0_RX_EOF_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC0_TX_DSCR_ERR_INT_RAW` reader - The raw interrupt status of SLC0_TX_DSCR_ERR_INT."] +pub type SDIO_SLC0_TX_DSCR_ERR_INT_RAW_R = crate::BitReader; +#[doc = "Field `SDIO_SLC0_TX_DSCR_ERR_INT_RAW` writer - The raw interrupt status of SLC0_TX_DSCR_ERR_INT."] +pub type SDIO_SLC0_TX_DSCR_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC0_RX_DSCR_ERR_INT_RAW` reader - The raw interrupt status of SLC0_RX_DSCR_ERR_INT."] +pub type SDIO_SLC0_RX_DSCR_ERR_INT_RAW_R = crate::BitReader; +#[doc = "Field `SDIO_SLC0_RX_DSCR_ERR_INT_RAW` writer - The raw interrupt status of SLC0_RX_DSCR_ERR_INT."] +pub type SDIO_SLC0_RX_DSCR_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "The raw interrupt status of SLC_FRHOST_BITn_INT (n: 0-7)."] + #[doc = ""] + #[doc = "
`n` is number of field in register. `n == 0` corresponds to `SDIO_SLC_FRHOST_BIT0_INT_RAW` field.
"] + #[inline(always)] + pub fn sdio_slc_frhost_bit_int_raw(&self, n: u8) -> SDIO_SLC_FRHOST_BIT_INT_RAW_R { + #[allow(clippy::no_effect)] + [(); 8][n as usize]; + SDIO_SLC_FRHOST_BIT_INT_RAW_R::new(((self.bits >> n) & 1) != 0) + } + #[doc = "Iterator for array of:"] + #[doc = "The raw interrupt status of SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit_int_raw_iter( + &self, + ) -> impl Iterator + '_ { + (0..8).map(move |n| SDIO_SLC_FRHOST_BIT_INT_RAW_R::new(((self.bits >> n) & 1) != 0)) + } + #[doc = "Bit 0 - The raw interrupt status of SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit0_int_raw(&self) -> SDIO_SLC_FRHOST_BIT_INT_RAW_R { + SDIO_SLC_FRHOST_BIT_INT_RAW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The raw interrupt status of SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit1_int_raw(&self) -> SDIO_SLC_FRHOST_BIT_INT_RAW_R { + SDIO_SLC_FRHOST_BIT_INT_RAW_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The raw interrupt status of SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit2_int_raw(&self) -> SDIO_SLC_FRHOST_BIT_INT_RAW_R { + SDIO_SLC_FRHOST_BIT_INT_RAW_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The raw interrupt status of SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit3_int_raw(&self) -> SDIO_SLC_FRHOST_BIT_INT_RAW_R { + SDIO_SLC_FRHOST_BIT_INT_RAW_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The raw interrupt status of SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit4_int_raw(&self) -> SDIO_SLC_FRHOST_BIT_INT_RAW_R { + SDIO_SLC_FRHOST_BIT_INT_RAW_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The raw interrupt status of SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit5_int_raw(&self) -> SDIO_SLC_FRHOST_BIT_INT_RAW_R { + SDIO_SLC_FRHOST_BIT_INT_RAW_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The raw interrupt status of SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit6_int_raw(&self) -> SDIO_SLC_FRHOST_BIT_INT_RAW_R { + SDIO_SLC_FRHOST_BIT_INT_RAW_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - The raw interrupt status of SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit7_int_raw(&self) -> SDIO_SLC_FRHOST_BIT_INT_RAW_R { + SDIO_SLC_FRHOST_BIT_INT_RAW_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The raw interrupt status of SLC0_RX_START_INT."] + #[inline(always)] + pub fn sdio_slc0_rx_start_int_raw(&self) -> SDIO_SLC0_RX_START_INT_RAW_R { + SDIO_SLC0_RX_START_INT_RAW_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - The raw interrupt status of SLC0_TX_START_INT."] + #[inline(always)] + pub fn sdio_slc0_tx_start_int_raw(&self) -> SDIO_SLC0_TX_START_INT_RAW_R { + SDIO_SLC0_TX_START_INT_RAW_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - The raw interrupt status of SLC0_RX_UDF_INT."] + #[inline(always)] + pub fn sdio_slc0_rx_udf_int_raw(&self) -> SDIO_SLC0_RX_UDF_INT_RAW_R { + SDIO_SLC0_RX_UDF_INT_RAW_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - The raw interrupt status of SLC0_TX_OVF_INT."] + #[inline(always)] + pub fn sdio_slc0_tx_ovf_int_raw(&self) -> SDIO_SLC0_TX_OVF_INT_RAW_R { + SDIO_SLC0_TX_OVF_INT_RAW_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 14 - The raw interrupt status of SLC0_TX_DONE_INT."] + #[inline(always)] + pub fn sdio_slc0_tx_done_int_raw(&self) -> SDIO_SLC0_TX_DONE_INT_RAW_R { + SDIO_SLC0_TX_DONE_INT_RAW_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - The raw interrupt status of SLC0_TX_SUC_EOF_INT."] + #[inline(always)] + pub fn sdio_slc0_tx_suc_eof_int_raw(&self) -> SDIO_SLC0_TX_SUC_EOF_INT_RAW_R { + SDIO_SLC0_TX_SUC_EOF_INT_RAW_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - The raw interrupt status of SLC0_RX_DONE_INT."] + #[inline(always)] + pub fn sdio_slc0_rx_done_int_raw(&self) -> SDIO_SLC0_RX_DONE_INT_RAW_R { + SDIO_SLC0_RX_DONE_INT_RAW_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - The raw interrupt status of SLC0_RX_EOF_INT."] + #[inline(always)] + pub fn sdio_slc0_rx_eof_int_raw(&self) -> SDIO_SLC0_RX_EOF_INT_RAW_R { + SDIO_SLC0_RX_EOF_INT_RAW_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 19 - The raw interrupt status of SLC0_TX_DSCR_ERR_INT."] + #[inline(always)] + pub fn sdio_slc0_tx_dscr_err_int_raw(&self) -> SDIO_SLC0_TX_DSCR_ERR_INT_RAW_R { + SDIO_SLC0_TX_DSCR_ERR_INT_RAW_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - The raw interrupt status of SLC0_RX_DSCR_ERR_INT."] + #[inline(always)] + pub fn sdio_slc0_rx_dscr_err_int_raw(&self) -> SDIO_SLC0_RX_DSCR_ERR_INT_RAW_R { + SDIO_SLC0_RX_DSCR_ERR_INT_RAW_R::new(((self.bits >> 20) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SLC0INT_RAW") + .field( + "sdio_slc_frhost_bit0_int_raw", + &self.sdio_slc_frhost_bit0_int_raw(), + ) + .field( + "sdio_slc_frhost_bit1_int_raw", + &self.sdio_slc_frhost_bit1_int_raw(), + ) + .field( + "sdio_slc_frhost_bit2_int_raw", + &self.sdio_slc_frhost_bit2_int_raw(), + ) + .field( + "sdio_slc_frhost_bit3_int_raw", + &self.sdio_slc_frhost_bit3_int_raw(), + ) + .field( + "sdio_slc_frhost_bit4_int_raw", + &self.sdio_slc_frhost_bit4_int_raw(), + ) + .field( + "sdio_slc_frhost_bit5_int_raw", + &self.sdio_slc_frhost_bit5_int_raw(), + ) + .field( + "sdio_slc_frhost_bit6_int_raw", + &self.sdio_slc_frhost_bit6_int_raw(), + ) + .field( + "sdio_slc_frhost_bit7_int_raw", + &self.sdio_slc_frhost_bit7_int_raw(), + ) + .field( + "sdio_slc0_rx_start_int_raw", + &self.sdio_slc0_rx_start_int_raw(), + ) + .field( + "sdio_slc0_tx_start_int_raw", + &self.sdio_slc0_tx_start_int_raw(), + ) + .field("sdio_slc0_rx_udf_int_raw", &self.sdio_slc0_rx_udf_int_raw()) + .field("sdio_slc0_tx_ovf_int_raw", &self.sdio_slc0_tx_ovf_int_raw()) + .field( + "sdio_slc0_tx_done_int_raw", + &self.sdio_slc0_tx_done_int_raw(), + ) + .field( + "sdio_slc0_tx_suc_eof_int_raw", + &self.sdio_slc0_tx_suc_eof_int_raw(), + ) + .field( + "sdio_slc0_rx_done_int_raw", + &self.sdio_slc0_rx_done_int_raw(), + ) + .field("sdio_slc0_rx_eof_int_raw", &self.sdio_slc0_rx_eof_int_raw()) + .field( + "sdio_slc0_tx_dscr_err_int_raw", + &self.sdio_slc0_tx_dscr_err_int_raw(), + ) + .field( + "sdio_slc0_rx_dscr_err_int_raw", + &self.sdio_slc0_rx_dscr_err_int_raw(), + ) + .finish() + } +} +impl W { + #[doc = "The raw interrupt status of SLC_FRHOST_BITn_INT (n: 0-7)."] + #[doc = ""] + #[doc = "
`n` is number of field in register. `n == 0` corresponds to `SDIO_SLC_FRHOST_BIT0_INT_RAW` field.
"] + #[inline(always)] + pub fn sdio_slc_frhost_bit_int_raw( + &mut self, + n: u8, + ) -> SDIO_SLC_FRHOST_BIT_INT_RAW_W { + #[allow(clippy::no_effect)] + [(); 8][n as usize]; + SDIO_SLC_FRHOST_BIT_INT_RAW_W::new(self, n) + } + #[doc = "Bit 0 - The raw interrupt status of SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit0_int_raw( + &mut self, + ) -> SDIO_SLC_FRHOST_BIT_INT_RAW_W { + SDIO_SLC_FRHOST_BIT_INT_RAW_W::new(self, 0) + } + #[doc = "Bit 1 - The raw interrupt status of SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit1_int_raw( + &mut self, + ) -> SDIO_SLC_FRHOST_BIT_INT_RAW_W { + SDIO_SLC_FRHOST_BIT_INT_RAW_W::new(self, 1) + } + #[doc = "Bit 2 - The raw interrupt status of SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit2_int_raw( + &mut self, + ) -> SDIO_SLC_FRHOST_BIT_INT_RAW_W { + SDIO_SLC_FRHOST_BIT_INT_RAW_W::new(self, 2) + } + #[doc = "Bit 3 - The raw interrupt status of SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit3_int_raw( + &mut self, + ) -> SDIO_SLC_FRHOST_BIT_INT_RAW_W { + SDIO_SLC_FRHOST_BIT_INT_RAW_W::new(self, 3) + } + #[doc = "Bit 4 - The raw interrupt status of SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit4_int_raw( + &mut self, + ) -> SDIO_SLC_FRHOST_BIT_INT_RAW_W { + SDIO_SLC_FRHOST_BIT_INT_RAW_W::new(self, 4) + } + #[doc = "Bit 5 - The raw interrupt status of SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit5_int_raw( + &mut self, + ) -> SDIO_SLC_FRHOST_BIT_INT_RAW_W { + SDIO_SLC_FRHOST_BIT_INT_RAW_W::new(self, 5) + } + #[doc = "Bit 6 - The raw interrupt status of SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit6_int_raw( + &mut self, + ) -> SDIO_SLC_FRHOST_BIT_INT_RAW_W { + SDIO_SLC_FRHOST_BIT_INT_RAW_W::new(self, 6) + } + #[doc = "Bit 7 - The raw interrupt status of SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit7_int_raw( + &mut self, + ) -> SDIO_SLC_FRHOST_BIT_INT_RAW_W { + SDIO_SLC_FRHOST_BIT_INT_RAW_W::new(self, 7) + } + #[doc = "Bit 8 - The raw interrupt status of SLC0_RX_START_INT."] + #[inline(always)] + pub fn sdio_slc0_rx_start_int_raw(&mut self) -> SDIO_SLC0_RX_START_INT_RAW_W { + SDIO_SLC0_RX_START_INT_RAW_W::new(self, 8) + } + #[doc = "Bit 9 - The raw interrupt status of SLC0_TX_START_INT."] + #[inline(always)] + pub fn sdio_slc0_tx_start_int_raw(&mut self) -> SDIO_SLC0_TX_START_INT_RAW_W { + SDIO_SLC0_TX_START_INT_RAW_W::new(self, 9) + } + #[doc = "Bit 10 - The raw interrupt status of SLC0_RX_UDF_INT."] + #[inline(always)] + pub fn sdio_slc0_rx_udf_int_raw(&mut self) -> SDIO_SLC0_RX_UDF_INT_RAW_W { + SDIO_SLC0_RX_UDF_INT_RAW_W::new(self, 10) + } + #[doc = "Bit 11 - The raw interrupt status of SLC0_TX_OVF_INT."] + #[inline(always)] + pub fn sdio_slc0_tx_ovf_int_raw(&mut self) -> SDIO_SLC0_TX_OVF_INT_RAW_W { + SDIO_SLC0_TX_OVF_INT_RAW_W::new(self, 11) + } + #[doc = "Bit 14 - The raw interrupt status of SLC0_TX_DONE_INT."] + #[inline(always)] + pub fn sdio_slc0_tx_done_int_raw(&mut self) -> SDIO_SLC0_TX_DONE_INT_RAW_W { + SDIO_SLC0_TX_DONE_INT_RAW_W::new(self, 14) + } + #[doc = "Bit 15 - The raw interrupt status of SLC0_TX_SUC_EOF_INT."] + #[inline(always)] + pub fn sdio_slc0_tx_suc_eof_int_raw( + &mut self, + ) -> SDIO_SLC0_TX_SUC_EOF_INT_RAW_W { + SDIO_SLC0_TX_SUC_EOF_INT_RAW_W::new(self, 15) + } + #[doc = "Bit 16 - The raw interrupt status of SLC0_RX_DONE_INT."] + #[inline(always)] + pub fn sdio_slc0_rx_done_int_raw(&mut self) -> SDIO_SLC0_RX_DONE_INT_RAW_W { + SDIO_SLC0_RX_DONE_INT_RAW_W::new(self, 16) + } + #[doc = "Bit 17 - The raw interrupt status of SLC0_RX_EOF_INT."] + #[inline(always)] + pub fn sdio_slc0_rx_eof_int_raw(&mut self) -> SDIO_SLC0_RX_EOF_INT_RAW_W { + SDIO_SLC0_RX_EOF_INT_RAW_W::new(self, 17) + } + #[doc = "Bit 19 - The raw interrupt status of SLC0_TX_DSCR_ERR_INT."] + #[inline(always)] + pub fn sdio_slc0_tx_dscr_err_int_raw( + &mut self, + ) -> SDIO_SLC0_TX_DSCR_ERR_INT_RAW_W { + SDIO_SLC0_TX_DSCR_ERR_INT_RAW_W::new(self, 19) + } + #[doc = "Bit 20 - The raw interrupt status of SLC0_RX_DSCR_ERR_INT."] + #[inline(always)] + pub fn sdio_slc0_rx_dscr_err_int_raw( + &mut self, + ) -> SDIO_SLC0_RX_DSCR_ERR_INT_RAW_W { + SDIO_SLC0_RX_DSCR_ERR_INT_RAW_W::new(self, 20) + } +} +#[doc = "SLC0 to slave raw interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`slc0int_raw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc0int_raw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SLC0INT_RAW_SPEC; +impl crate::RegisterSpec for SLC0INT_RAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`slc0int_raw::R`](R) reader structure"] +impl crate::Readable for SLC0INT_RAW_SPEC {} +#[doc = "`write(|w| ..)` method takes [`slc0int_raw::W`](W) writer structure"] +impl crate::Writable for SLC0INT_RAW_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SLC0INT_RAW to value 0"] +impl crate::Resettable for SLC0INT_RAW_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32c6/src/slc/slc0int_st.rs b/esp32c6/src/slc/slc0int_st.rs new file mode 100644 index 000000000..5dac3838d --- /dev/null +++ b/esp32c6/src/slc/slc0int_st.rs @@ -0,0 +1,208 @@ +#[doc = "Register `SLC0INT_ST` reader"] +pub type R = crate::R; +#[doc = "Field `SDIO_SLC_FRHOST_BIT_INT_ST(0-7)` reader - The masked interrupt status of SLC_FRHOST_BITn_INT (n: 0-7)."] +pub type SDIO_SLC_FRHOST_BIT_INT_ST_R = crate::BitReader; +#[doc = "Field `SDIO_SLC0_RX_START_INT_ST` reader - The masked interrupt status of SLC0_RX_START_INT."] +pub type SDIO_SLC0_RX_START_INT_ST_R = crate::BitReader; +#[doc = "Field `SDIO_SLC0_TX_START_INT_ST` reader - The masked interrupt status of SLC0_TX_START_INT."] +pub type SDIO_SLC0_TX_START_INT_ST_R = crate::BitReader; +#[doc = "Field `SDIO_SLC0_RX_UDF_INT_ST` reader - The masked interrupt status of SLC0_RX_UDF_INT."] +pub type SDIO_SLC0_RX_UDF_INT_ST_R = crate::BitReader; +#[doc = "Field `SDIO_SLC0_TX_OVF_INT_ST` reader - The masked interrupt status of SLC0_TX_OVF_INT."] +pub type SDIO_SLC0_TX_OVF_INT_ST_R = crate::BitReader; +#[doc = "Field `SDIO_SLC0_TX_DONE_INT_ST` reader - The masked interrupt status of SLC0_TX_DONE_INT."] +pub type SDIO_SLC0_TX_DONE_INT_ST_R = crate::BitReader; +#[doc = "Field `SDIO_SLC0_TX_SUC_EOF_INT_ST` reader - The masked interrupt status of SLC0_TX_SUC_EOF_INT."] +pub type SDIO_SLC0_TX_SUC_EOF_INT_ST_R = crate::BitReader; +#[doc = "Field `SDIO_SLC0_RX_DONE_INT_ST` reader - The masked interrupt status of SLC0_RX_DONE_INT."] +pub type SDIO_SLC0_RX_DONE_INT_ST_R = crate::BitReader; +#[doc = "Field `SDIO_SLC0_RX_EOF_INT_ST` reader - The masked interrupt status of SLC0_RX_EOF_INT."] +pub type SDIO_SLC0_RX_EOF_INT_ST_R = crate::BitReader; +#[doc = "Field `SDIO_SLC0_TX_DSCR_ERR_INT_ST` reader - The masked interrupt status of SLC0_TX_DSCR_ERR_INT."] +pub type SDIO_SLC0_TX_DSCR_ERR_INT_ST_R = crate::BitReader; +#[doc = "Field `SDIO_SLC0_RX_DSCR_ERR_INT_ST` reader - The masked interrupt status of SLC0_RX_DSCR_ERR_INT."] +pub type SDIO_SLC0_RX_DSCR_ERR_INT_ST_R = crate::BitReader; +impl R { + #[doc = "The masked interrupt status of SLC_FRHOST_BITn_INT (n: 0-7)."] + #[doc = ""] + #[doc = "
`n` is number of field in register. `n == 0` corresponds to `SDIO_SLC_FRHOST_BIT0_INT_ST` field.
"] + #[inline(always)] + pub fn sdio_slc_frhost_bit_int_st(&self, n: u8) -> SDIO_SLC_FRHOST_BIT_INT_ST_R { + #[allow(clippy::no_effect)] + [(); 8][n as usize]; + SDIO_SLC_FRHOST_BIT_INT_ST_R::new(((self.bits >> n) & 1) != 0) + } + #[doc = "Iterator for array of:"] + #[doc = "The masked interrupt status of SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit_int_st_iter( + &self, + ) -> impl Iterator + '_ { + (0..8).map(move |n| SDIO_SLC_FRHOST_BIT_INT_ST_R::new(((self.bits >> n) & 1) != 0)) + } + #[doc = "Bit 0 - The masked interrupt status of SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit0_int_st(&self) -> SDIO_SLC_FRHOST_BIT_INT_ST_R { + SDIO_SLC_FRHOST_BIT_INT_ST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The masked interrupt status of SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit1_int_st(&self) -> SDIO_SLC_FRHOST_BIT_INT_ST_R { + SDIO_SLC_FRHOST_BIT_INT_ST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The masked interrupt status of SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit2_int_st(&self) -> SDIO_SLC_FRHOST_BIT_INT_ST_R { + SDIO_SLC_FRHOST_BIT_INT_ST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The masked interrupt status of SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit3_int_st(&self) -> SDIO_SLC_FRHOST_BIT_INT_ST_R { + SDIO_SLC_FRHOST_BIT_INT_ST_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The masked interrupt status of SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit4_int_st(&self) -> SDIO_SLC_FRHOST_BIT_INT_ST_R { + SDIO_SLC_FRHOST_BIT_INT_ST_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The masked interrupt status of SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit5_int_st(&self) -> SDIO_SLC_FRHOST_BIT_INT_ST_R { + SDIO_SLC_FRHOST_BIT_INT_ST_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The masked interrupt status of SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit6_int_st(&self) -> SDIO_SLC_FRHOST_BIT_INT_ST_R { + SDIO_SLC_FRHOST_BIT_INT_ST_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - The masked interrupt status of SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit7_int_st(&self) -> SDIO_SLC_FRHOST_BIT_INT_ST_R { + SDIO_SLC_FRHOST_BIT_INT_ST_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The masked interrupt status of SLC0_RX_START_INT."] + #[inline(always)] + pub fn sdio_slc0_rx_start_int_st(&self) -> SDIO_SLC0_RX_START_INT_ST_R { + SDIO_SLC0_RX_START_INT_ST_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - The masked interrupt status of SLC0_TX_START_INT."] + #[inline(always)] + pub fn sdio_slc0_tx_start_int_st(&self) -> SDIO_SLC0_TX_START_INT_ST_R { + SDIO_SLC0_TX_START_INT_ST_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - The masked interrupt status of SLC0_RX_UDF_INT."] + #[inline(always)] + pub fn sdio_slc0_rx_udf_int_st(&self) -> SDIO_SLC0_RX_UDF_INT_ST_R { + SDIO_SLC0_RX_UDF_INT_ST_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - The masked interrupt status of SLC0_TX_OVF_INT."] + #[inline(always)] + pub fn sdio_slc0_tx_ovf_int_st(&self) -> SDIO_SLC0_TX_OVF_INT_ST_R { + SDIO_SLC0_TX_OVF_INT_ST_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 14 - The masked interrupt status of SLC0_TX_DONE_INT."] + #[inline(always)] + pub fn sdio_slc0_tx_done_int_st(&self) -> SDIO_SLC0_TX_DONE_INT_ST_R { + SDIO_SLC0_TX_DONE_INT_ST_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - The masked interrupt status of SLC0_TX_SUC_EOF_INT."] + #[inline(always)] + pub fn sdio_slc0_tx_suc_eof_int_st(&self) -> SDIO_SLC0_TX_SUC_EOF_INT_ST_R { + SDIO_SLC0_TX_SUC_EOF_INT_ST_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - The masked interrupt status of SLC0_RX_DONE_INT."] + #[inline(always)] + pub fn sdio_slc0_rx_done_int_st(&self) -> SDIO_SLC0_RX_DONE_INT_ST_R { + SDIO_SLC0_RX_DONE_INT_ST_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - The masked interrupt status of SLC0_RX_EOF_INT."] + #[inline(always)] + pub fn sdio_slc0_rx_eof_int_st(&self) -> SDIO_SLC0_RX_EOF_INT_ST_R { + SDIO_SLC0_RX_EOF_INT_ST_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 19 - The masked interrupt status of SLC0_TX_DSCR_ERR_INT."] + #[inline(always)] + pub fn sdio_slc0_tx_dscr_err_int_st(&self) -> SDIO_SLC0_TX_DSCR_ERR_INT_ST_R { + SDIO_SLC0_TX_DSCR_ERR_INT_ST_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - The masked interrupt status of SLC0_RX_DSCR_ERR_INT."] + #[inline(always)] + pub fn sdio_slc0_rx_dscr_err_int_st(&self) -> SDIO_SLC0_RX_DSCR_ERR_INT_ST_R { + SDIO_SLC0_RX_DSCR_ERR_INT_ST_R::new(((self.bits >> 20) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SLC0INT_ST") + .field( + "sdio_slc_frhost_bit0_int_st", + &self.sdio_slc_frhost_bit0_int_st(), + ) + .field( + "sdio_slc_frhost_bit1_int_st", + &self.sdio_slc_frhost_bit1_int_st(), + ) + .field( + "sdio_slc_frhost_bit2_int_st", + &self.sdio_slc_frhost_bit2_int_st(), + ) + .field( + "sdio_slc_frhost_bit3_int_st", + &self.sdio_slc_frhost_bit3_int_st(), + ) + .field( + "sdio_slc_frhost_bit4_int_st", + &self.sdio_slc_frhost_bit4_int_st(), + ) + .field( + "sdio_slc_frhost_bit5_int_st", + &self.sdio_slc_frhost_bit5_int_st(), + ) + .field( + "sdio_slc_frhost_bit6_int_st", + &self.sdio_slc_frhost_bit6_int_st(), + ) + .field( + "sdio_slc_frhost_bit7_int_st", + &self.sdio_slc_frhost_bit7_int_st(), + ) + .field( + "sdio_slc0_rx_start_int_st", + &self.sdio_slc0_rx_start_int_st(), + ) + .field( + "sdio_slc0_tx_start_int_st", + &self.sdio_slc0_tx_start_int_st(), + ) + .field("sdio_slc0_rx_udf_int_st", &self.sdio_slc0_rx_udf_int_st()) + .field("sdio_slc0_tx_ovf_int_st", &self.sdio_slc0_tx_ovf_int_st()) + .field("sdio_slc0_tx_done_int_st", &self.sdio_slc0_tx_done_int_st()) + .field( + "sdio_slc0_tx_suc_eof_int_st", + &self.sdio_slc0_tx_suc_eof_int_st(), + ) + .field("sdio_slc0_rx_done_int_st", &self.sdio_slc0_rx_done_int_st()) + .field("sdio_slc0_rx_eof_int_st", &self.sdio_slc0_rx_eof_int_st()) + .field( + "sdio_slc0_tx_dscr_err_int_st", + &self.sdio_slc0_tx_dscr_err_int_st(), + ) + .field( + "sdio_slc0_rx_dscr_err_int_st", + &self.sdio_slc0_rx_dscr_err_int_st(), + ) + .finish() + } +} +#[doc = "SLC0 to slave masked interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`slc0int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SLC0INT_ST_SPEC; +impl crate::RegisterSpec for SLC0INT_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`slc0int_st::R`](R) reader structure"] +impl crate::Readable for SLC0INT_ST_SPEC {} +#[doc = "`reset()` method sets SLC0INT_ST to value 0"] +impl crate::Resettable for SLC0INT_ST_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32c6/src/slc/slc0rx_link.rs b/esp32c6/src/slc/slc0rx_link.rs new file mode 100644 index 000000000..f01dbe4ae --- /dev/null +++ b/esp32c6/src/slc/slc0rx_link.rs @@ -0,0 +1,92 @@ +#[doc = "Register `SLC0RX_LINK` reader"] +pub type R = crate::R; +#[doc = "Register `SLC0RX_LINK` writer"] +pub type W = crate::W; +#[doc = "Field `SDIO_SLC0_RXLINK_STOP` reader - Configures whether to stop SLC0 RX linked list operation."] +pub type SDIO_SLC0_RXLINK_STOP_R = crate::BitReader; +#[doc = "Field `SDIO_SLC0_RXLINK_STOP` writer - Configures whether to stop SLC0 RX linked list operation."] +pub type SDIO_SLC0_RXLINK_STOP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC0_RXLINK_START` reader - Configures whether to start SLC0 RX linked list operation from the address indicated by SDIO_SLC0_RXLINK_ADDR."] +pub type SDIO_SLC0_RXLINK_START_R = crate::BitReader; +#[doc = "Field `SDIO_SLC0_RXLINK_START` writer - Configures whether to start SLC0 RX linked list operation from the address indicated by SDIO_SLC0_RXLINK_ADDR."] +pub type SDIO_SLC0_RXLINK_START_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC0_RXLINK_RESTART` reader - Configures whether to restart and continue SLC0 RX linked list operation."] +pub type SDIO_SLC0_RXLINK_RESTART_R = crate::BitReader; +#[doc = "Field `SDIO_SLC0_RXLINK_RESTART` writer - Configures whether to restart and continue SLC0 RX linked list operation."] +pub type SDIO_SLC0_RXLINK_RESTART_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC0_RXLINK_PARK` reader - Represents SLC0 RX linked list FSM state."] +pub type SDIO_SLC0_RXLINK_PARK_R = crate::BitReader; +#[doc = "Field `SDIO_SLC0_RXLINK_PARK` writer - Represents SLC0 RX linked list FSM state."] +pub type SDIO_SLC0_RXLINK_PARK_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 28 - Configures whether to stop SLC0 RX linked list operation."] + #[inline(always)] + pub fn sdio_slc0_rxlink_stop(&self) -> SDIO_SLC0_RXLINK_STOP_R { + SDIO_SLC0_RXLINK_STOP_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Configures whether to start SLC0 RX linked list operation from the address indicated by SDIO_SLC0_RXLINK_ADDR."] + #[inline(always)] + pub fn sdio_slc0_rxlink_start(&self) -> SDIO_SLC0_RXLINK_START_R { + SDIO_SLC0_RXLINK_START_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Configures whether to restart and continue SLC0 RX linked list operation."] + #[inline(always)] + pub fn sdio_slc0_rxlink_restart(&self) -> SDIO_SLC0_RXLINK_RESTART_R { + SDIO_SLC0_RXLINK_RESTART_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Represents SLC0 RX linked list FSM state."] + #[inline(always)] + pub fn sdio_slc0_rxlink_park(&self) -> SDIO_SLC0_RXLINK_PARK_R { + SDIO_SLC0_RXLINK_PARK_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SLC0RX_LINK") + .field("sdio_slc0_rxlink_stop", &self.sdio_slc0_rxlink_stop()) + .field("sdio_slc0_rxlink_start", &self.sdio_slc0_rxlink_start()) + .field("sdio_slc0_rxlink_restart", &self.sdio_slc0_rxlink_restart()) + .field("sdio_slc0_rxlink_park", &self.sdio_slc0_rxlink_park()) + .finish() + } +} +impl W { + #[doc = "Bit 28 - Configures whether to stop SLC0 RX linked list operation."] + #[inline(always)] + pub fn sdio_slc0_rxlink_stop(&mut self) -> SDIO_SLC0_RXLINK_STOP_W { + SDIO_SLC0_RXLINK_STOP_W::new(self, 28) + } + #[doc = "Bit 29 - Configures whether to start SLC0 RX linked list operation from the address indicated by SDIO_SLC0_RXLINK_ADDR."] + #[inline(always)] + pub fn sdio_slc0_rxlink_start(&mut self) -> SDIO_SLC0_RXLINK_START_W { + SDIO_SLC0_RXLINK_START_W::new(self, 29) + } + #[doc = "Bit 30 - Configures whether to restart and continue SLC0 RX linked list operation."] + #[inline(always)] + pub fn sdio_slc0_rxlink_restart(&mut self) -> SDIO_SLC0_RXLINK_RESTART_W { + SDIO_SLC0_RXLINK_RESTART_W::new(self, 30) + } + #[doc = "Bit 31 - Represents SLC0 RX linked list FSM state."] + #[inline(always)] + pub fn sdio_slc0_rxlink_park(&mut self) -> SDIO_SLC0_RXLINK_PARK_W { + SDIO_SLC0_RXLINK_PARK_W::new(self, 31) + } +} +#[doc = "SLC0 RX linked list configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`slc0rx_link::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc0rx_link::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SLC0RX_LINK_SPEC; +impl crate::RegisterSpec for SLC0RX_LINK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`slc0rx_link::R`](R) reader structure"] +impl crate::Readable for SLC0RX_LINK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`slc0rx_link::W`](W) writer structure"] +impl crate::Writable for SLC0RX_LINK_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SLC0RX_LINK to value 0x8000_0000"] +impl crate::Resettable for SLC0RX_LINK_SPEC { + const RESET_VALUE: u32 = 0x8000_0000; +} diff --git a/esp32c6/src/slc/slc0rx_link_addr.rs b/esp32c6/src/slc/slc0rx_link_addr.rs new file mode 100644 index 000000000..368b29420 --- /dev/null +++ b/esp32c6/src/slc/slc0rx_link_addr.rs @@ -0,0 +1,47 @@ +#[doc = "Register `SLC0RX_LINK_ADDR` reader"] +pub type R = crate::R; +#[doc = "Register `SLC0RX_LINK_ADDR` writer"] +pub type W = crate::W; +#[doc = "Field `SDIO_SLC0_RXLINK_ADDR` reader - Configures SLC0 RX linked list initial address."] +pub type SDIO_SLC0_RXLINK_ADDR_R = crate::FieldReader; +#[doc = "Field `SDIO_SLC0_RXLINK_ADDR` writer - Configures SLC0 RX linked list initial address."] +pub type SDIO_SLC0_RXLINK_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Configures SLC0 RX linked list initial address."] + #[inline(always)] + pub fn sdio_slc0_rxlink_addr(&self) -> SDIO_SLC0_RXLINK_ADDR_R { + SDIO_SLC0_RXLINK_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SLC0RX_LINK_ADDR") + .field("sdio_slc0_rxlink_addr", &self.sdio_slc0_rxlink_addr()) + .finish() + } +} +impl W { + #[doc = "Bits 0:31 - Configures SLC0 RX linked list initial address."] + #[inline(always)] + pub fn sdio_slc0_rxlink_addr(&mut self) -> SDIO_SLC0_RXLINK_ADDR_W { + SDIO_SLC0_RXLINK_ADDR_W::new(self, 0) + } +} +#[doc = "SLC0 RX linked list address\n\nYou can [`read`](crate::Reg::read) this register and get [`slc0rx_link_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc0rx_link_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SLC0RX_LINK_ADDR_SPEC; +impl crate::RegisterSpec for SLC0RX_LINK_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`slc0rx_link_addr::R`](R) reader structure"] +impl crate::Readable for SLC0RX_LINK_ADDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`slc0rx_link_addr::W`](W) writer structure"] +impl crate::Writable for SLC0RX_LINK_ADDR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SLC0RX_LINK_ADDR to value 0"] +impl crate::Resettable for SLC0RX_LINK_ADDR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32c6/src/slc/slc0token1.rs b/esp32c6/src/slc/slc0token1.rs new file mode 100644 index 000000000..ef41224f6 --- /dev/null +++ b/esp32c6/src/slc/slc0token1.rs @@ -0,0 +1,68 @@ +#[doc = "Register `SLC0TOKEN1` reader"] +pub type R = crate::R; +#[doc = "Register `SLC0TOKEN1` writer"] +pub type W = crate::W; +#[doc = "Field `SDIO_SLC0_TOKEN1_WDATA` writer - Configures SLC0 token 1 value."] +pub type SDIO_SLC0_TOKEN1_WDATA_W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `SDIO_SLC0_TOKEN1_WR` writer - Configures this bit to 1 to write SDIO_SLC0_TOKEN1_WDATA into SDIO_SLC0_TOKEN1."] +pub type SDIO_SLC0_TOKEN1_WR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC0_TOKEN1_INC` writer - Configures this bit to 1 to add 1 to SDIO_SLC0_TOKEN1."] +pub type SDIO_SLC0_TOKEN1_INC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC0_TOKEN1_INC_MORE` writer - Configures this bit to 1 to add the value of SDIO_SLC0_TOKEN1_WDATA to SDIO_SLC0_TOKEN1."] +pub type SDIO_SLC0_TOKEN1_INC_MORE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC0_TOKEN1` reader - Represents the SLC0 accumulated number of buffers for receiving packets."] +pub type SDIO_SLC0_TOKEN1_R = crate::FieldReader; +impl R { + #[doc = "Bits 16:27 - Represents the SLC0 accumulated number of buffers for receiving packets."] + #[inline(always)] + pub fn sdio_slc0_token1(&self) -> SDIO_SLC0_TOKEN1_R { + SDIO_SLC0_TOKEN1_R::new(((self.bits >> 16) & 0x0fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SLC0TOKEN1") + .field("sdio_slc0_token1", &self.sdio_slc0_token1()) + .finish() + } +} +impl W { + #[doc = "Bits 0:10 - Configures SLC0 token 1 value."] + #[inline(always)] + pub fn sdio_slc0_token1_wdata(&mut self) -> SDIO_SLC0_TOKEN1_WDATA_W { + SDIO_SLC0_TOKEN1_WDATA_W::new(self, 0) + } + #[doc = "Bit 12 - Configures this bit to 1 to write SDIO_SLC0_TOKEN1_WDATA into SDIO_SLC0_TOKEN1."] + #[inline(always)] + pub fn sdio_slc0_token1_wr(&mut self) -> SDIO_SLC0_TOKEN1_WR_W { + SDIO_SLC0_TOKEN1_WR_W::new(self, 12) + } + #[doc = "Bit 13 - Configures this bit to 1 to add 1 to SDIO_SLC0_TOKEN1."] + #[inline(always)] + pub fn sdio_slc0_token1_inc(&mut self) -> SDIO_SLC0_TOKEN1_INC_W { + SDIO_SLC0_TOKEN1_INC_W::new(self, 13) + } + #[doc = "Bit 14 - Configures this bit to 1 to add the value of SDIO_SLC0_TOKEN1_WDATA to SDIO_SLC0_TOKEN1."] + #[inline(always)] + pub fn sdio_slc0_token1_inc_more(&mut self) -> SDIO_SLC0_TOKEN1_INC_MORE_W { + SDIO_SLC0_TOKEN1_INC_MORE_W::new(self, 14) + } +} +#[doc = "SLC0 receiving buffer configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`slc0token1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc0token1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SLC0TOKEN1_SPEC; +impl crate::RegisterSpec for SLC0TOKEN1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`slc0token1::R`](R) reader structure"] +impl crate::Readable for SLC0TOKEN1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`slc0token1::W`](W) writer structure"] +impl crate::Writable for SLC0TOKEN1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SLC0TOKEN1 to value 0"] +impl crate::Resettable for SLC0TOKEN1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32c6/src/slc/slc0tx_link.rs b/esp32c6/src/slc/slc0tx_link.rs new file mode 100644 index 000000000..db772a8cd --- /dev/null +++ b/esp32c6/src/slc/slc0tx_link.rs @@ -0,0 +1,92 @@ +#[doc = "Register `SLC0TX_LINK` reader"] +pub type R = crate::R; +#[doc = "Register `SLC0TX_LINK` writer"] +pub type W = crate::W; +#[doc = "Field `SDIO_SLC0_TXLINK_STOP` reader - Configures whether to stop SLC0 TX linked list operation."] +pub type SDIO_SLC0_TXLINK_STOP_R = crate::BitReader; +#[doc = "Field `SDIO_SLC0_TXLINK_STOP` writer - Configures whether to stop SLC0 TX linked list operation."] +pub type SDIO_SLC0_TXLINK_STOP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC0_TXLINK_START` reader - Configures whether to start SLC0 TX linked list operation from the address indicated by SDIO_SLC0_TXLINK_ADDR."] +pub type SDIO_SLC0_TXLINK_START_R = crate::BitReader; +#[doc = "Field `SDIO_SLC0_TXLINK_START` writer - Configures whether to start SLC0 TX linked list operation from the address indicated by SDIO_SLC0_TXLINK_ADDR."] +pub type SDIO_SLC0_TXLINK_START_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC0_TXLINK_RESTART` reader - Configures whether to restart and continue SLC0 TX linked list operation."] +pub type SDIO_SLC0_TXLINK_RESTART_R = crate::BitReader; +#[doc = "Field `SDIO_SLC0_TXLINK_RESTART` writer - Configures whether to restart and continue SLC0 TX linked list operation."] +pub type SDIO_SLC0_TXLINK_RESTART_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC0_TXLINK_PARK` reader - Represents SLC0 TX linked list FSM state."] +pub type SDIO_SLC0_TXLINK_PARK_R = crate::BitReader; +#[doc = "Field `SDIO_SLC0_TXLINK_PARK` writer - Represents SLC0 TX linked list FSM state."] +pub type SDIO_SLC0_TXLINK_PARK_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 28 - Configures whether to stop SLC0 TX linked list operation."] + #[inline(always)] + pub fn sdio_slc0_txlink_stop(&self) -> SDIO_SLC0_TXLINK_STOP_R { + SDIO_SLC0_TXLINK_STOP_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Configures whether to start SLC0 TX linked list operation from the address indicated by SDIO_SLC0_TXLINK_ADDR."] + #[inline(always)] + pub fn sdio_slc0_txlink_start(&self) -> SDIO_SLC0_TXLINK_START_R { + SDIO_SLC0_TXLINK_START_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Configures whether to restart and continue SLC0 TX linked list operation."] + #[inline(always)] + pub fn sdio_slc0_txlink_restart(&self) -> SDIO_SLC0_TXLINK_RESTART_R { + SDIO_SLC0_TXLINK_RESTART_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Represents SLC0 TX linked list FSM state."] + #[inline(always)] + pub fn sdio_slc0_txlink_park(&self) -> SDIO_SLC0_TXLINK_PARK_R { + SDIO_SLC0_TXLINK_PARK_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SLC0TX_LINK") + .field("sdio_slc0_txlink_stop", &self.sdio_slc0_txlink_stop()) + .field("sdio_slc0_txlink_start", &self.sdio_slc0_txlink_start()) + .field("sdio_slc0_txlink_restart", &self.sdio_slc0_txlink_restart()) + .field("sdio_slc0_txlink_park", &self.sdio_slc0_txlink_park()) + .finish() + } +} +impl W { + #[doc = "Bit 28 - Configures whether to stop SLC0 TX linked list operation."] + #[inline(always)] + pub fn sdio_slc0_txlink_stop(&mut self) -> SDIO_SLC0_TXLINK_STOP_W { + SDIO_SLC0_TXLINK_STOP_W::new(self, 28) + } + #[doc = "Bit 29 - Configures whether to start SLC0 TX linked list operation from the address indicated by SDIO_SLC0_TXLINK_ADDR."] + #[inline(always)] + pub fn sdio_slc0_txlink_start(&mut self) -> SDIO_SLC0_TXLINK_START_W { + SDIO_SLC0_TXLINK_START_W::new(self, 29) + } + #[doc = "Bit 30 - Configures whether to restart and continue SLC0 TX linked list operation."] + #[inline(always)] + pub fn sdio_slc0_txlink_restart(&mut self) -> SDIO_SLC0_TXLINK_RESTART_W { + SDIO_SLC0_TXLINK_RESTART_W::new(self, 30) + } + #[doc = "Bit 31 - Represents SLC0 TX linked list FSM state."] + #[inline(always)] + pub fn sdio_slc0_txlink_park(&mut self) -> SDIO_SLC0_TXLINK_PARK_W { + SDIO_SLC0_TXLINK_PARK_W::new(self, 31) + } +} +#[doc = "SLC0 TX linked list configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`slc0tx_link::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc0tx_link::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SLC0TX_LINK_SPEC; +impl crate::RegisterSpec for SLC0TX_LINK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`slc0tx_link::R`](R) reader structure"] +impl crate::Readable for SLC0TX_LINK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`slc0tx_link::W`](W) writer structure"] +impl crate::Writable for SLC0TX_LINK_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SLC0TX_LINK to value 0x8000_0000"] +impl crate::Resettable for SLC0TX_LINK_SPEC { + const RESET_VALUE: u32 = 0x8000_0000; +} diff --git a/esp32c6/src/slc/slc0tx_link_addr.rs b/esp32c6/src/slc/slc0tx_link_addr.rs new file mode 100644 index 000000000..f6453f665 --- /dev/null +++ b/esp32c6/src/slc/slc0tx_link_addr.rs @@ -0,0 +1,47 @@ +#[doc = "Register `SLC0TX_LINK_ADDR` reader"] +pub type R = crate::R; +#[doc = "Register `SLC0TX_LINK_ADDR` writer"] +pub type W = crate::W; +#[doc = "Field `SDIO_SLC0_TXLINK_ADDR` reader - Configures SLC0 TX linked list initial address."] +pub type SDIO_SLC0_TXLINK_ADDR_R = crate::FieldReader; +#[doc = "Field `SDIO_SLC0_TXLINK_ADDR` writer - Configures SLC0 TX linked list initial address."] +pub type SDIO_SLC0_TXLINK_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Configures SLC0 TX linked list initial address."] + #[inline(always)] + pub fn sdio_slc0_txlink_addr(&self) -> SDIO_SLC0_TXLINK_ADDR_R { + SDIO_SLC0_TXLINK_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SLC0TX_LINK_ADDR") + .field("sdio_slc0_txlink_addr", &self.sdio_slc0_txlink_addr()) + .finish() + } +} +impl W { + #[doc = "Bits 0:31 - Configures SLC0 TX linked list initial address."] + #[inline(always)] + pub fn sdio_slc0_txlink_addr(&mut self) -> SDIO_SLC0_TXLINK_ADDR_W { + SDIO_SLC0_TXLINK_ADDR_W::new(self, 0) + } +} +#[doc = "SLC0 TX linked list address\n\nYou can [`read`](crate::Reg::read) this register and get [`slc0tx_link_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc0tx_link_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SLC0TX_LINK_ADDR_SPEC; +impl crate::RegisterSpec for SLC0TX_LINK_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`slc0tx_link_addr::R`](R) reader structure"] +impl crate::Readable for SLC0TX_LINK_ADDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`slc0tx_link_addr::W`](W) writer structure"] +impl crate::Writable for SLC0TX_LINK_ADDR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SLC0TX_LINK_ADDR to value 0"] +impl crate::Resettable for SLC0TX_LINK_ADDR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32c6/src/slc/slc10_length.rs b/esp32c6/src/slc/slc10_length.rs new file mode 100644 index 000000000..9aa3d5e54 --- /dev/null +++ b/esp32c6/src/slc/slc10_length.rs @@ -0,0 +1,30 @@ +#[doc = "Register `SLC10_LENGTH` reader"] +pub type R = crate::R; +#[doc = "Field `SDIO_SLC0_LEN` reader - Represents the accumulated length of data that the slave wants to send."] +pub type SDIO_SLC0_LEN_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:19 - Represents the accumulated length of data that the slave wants to send."] + #[inline(always)] + pub fn sdio_slc0_len(&self) -> SDIO_SLC0_LEN_R { + SDIO_SLC0_LEN_R::new(self.bits & 0x000f_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SLC10_LENGTH") + .field("sdio_slc0_len", &self.sdio_slc0_len()) + .finish() + } +} +#[doc = "Length of transmitting packets\n\nYou can [`read`](crate::Reg::read) this register and get [`slc10_length::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SLC10_LENGTH_SPEC; +impl crate::RegisterSpec for SLC10_LENGTH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`slc10_length::R`](R) reader structure"] +impl crate::Readable for SLC10_LENGTH_SPEC {} +#[doc = "`reset()` method sets SLC10_LENGTH to value 0"] +impl crate::Resettable for SLC10_LENGTH_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32c6/src/slc/slc1_rx_sharemem_end.rs b/esp32c6/src/slc/slc1_rx_sharemem_end.rs new file mode 100644 index 000000000..415757e29 --- /dev/null +++ b/esp32c6/src/slc/slc1_rx_sharemem_end.rs @@ -0,0 +1,52 @@ +#[doc = "Register `SLC1_RX_SHAREMEM_END` reader"] +pub type R = crate::R; +#[doc = "Register `SLC1_RX_SHAREMEM_END` writer"] +pub type W = crate::W; +#[doc = "Field `SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR` reader - Configures SLC1 slave to host channel AHB end address boundary."] +pub type SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR_R = crate::FieldReader; +#[doc = "Field `SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR` writer - Configures SLC1 slave to host channel AHB end address boundary."] +pub type SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Configures SLC1 slave to host channel AHB end address boundary."] + #[inline(always)] + pub fn sdio_sdio_slc1_rx_sharemem_end_addr(&self) -> SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR_R { + SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SLC1_RX_SHAREMEM_END") + .field( + "sdio_sdio_slc1_rx_sharemem_end_addr", + &self.sdio_sdio_slc1_rx_sharemem_end_addr(), + ) + .finish() + } +} +impl W { + #[doc = "Bits 0:31 - Configures SLC1 slave to host channel AHB end address boundary."] + #[inline(always)] + pub fn sdio_sdio_slc1_rx_sharemem_end_addr( + &mut self, + ) -> SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR_W { + SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR_W::new(self, 0) + } +} +#[doc = "SLC1 AHB RX end address range\n\nYou can [`read`](crate::Reg::read) this register and get [`slc1_rx_sharemem_end::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc1_rx_sharemem_end::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SLC1_RX_SHAREMEM_END_SPEC; +impl crate::RegisterSpec for SLC1_RX_SHAREMEM_END_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`slc1_rx_sharemem_end::R`](R) reader structure"] +impl crate::Readable for SLC1_RX_SHAREMEM_END_SPEC {} +#[doc = "`write(|w| ..)` method takes [`slc1_rx_sharemem_end::W`](W) writer structure"] +impl crate::Writable for SLC1_RX_SHAREMEM_END_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SLC1_RX_SHAREMEM_END to value 0xffff_ffff"] +impl crate::Resettable for SLC1_RX_SHAREMEM_END_SPEC { + const RESET_VALUE: u32 = 0xffff_ffff; +} diff --git a/esp32c6/src/slc/slc1_rx_sharemem_start.rs b/esp32c6/src/slc/slc1_rx_sharemem_start.rs new file mode 100644 index 000000000..677be0f4e --- /dev/null +++ b/esp32c6/src/slc/slc1_rx_sharemem_start.rs @@ -0,0 +1,52 @@ +#[doc = "Register `SLC1_RX_SHAREMEM_START` reader"] +pub type R = crate::R; +#[doc = "Register `SLC1_RX_SHAREMEM_START` writer"] +pub type W = crate::W; +#[doc = "Field `SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR` reader - Configures SLC1 slave to host channel AHB start address boundary."] +pub type SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR_R = crate::FieldReader; +#[doc = "Field `SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR` writer - Configures SLC1 slave to host channel AHB start address boundary."] +pub type SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Configures SLC1 slave to host channel AHB start address boundary."] + #[inline(always)] + pub fn sdio_sdio_slc1_rx_sharemem_start_addr(&self) -> SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR_R { + SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SLC1_RX_SHAREMEM_START") + .field( + "sdio_sdio_slc1_rx_sharemem_start_addr", + &self.sdio_sdio_slc1_rx_sharemem_start_addr(), + ) + .finish() + } +} +impl W { + #[doc = "Bits 0:31 - Configures SLC1 slave to host channel AHB start address boundary."] + #[inline(always)] + pub fn sdio_sdio_slc1_rx_sharemem_start_addr( + &mut self, + ) -> SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR_W { + SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR_W::new(self, 0) + } +} +#[doc = "SLC1 AHB RX start address range\n\nYou can [`read`](crate::Reg::read) this register and get [`slc1_rx_sharemem_start::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc1_rx_sharemem_start::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SLC1_RX_SHAREMEM_START_SPEC; +impl crate::RegisterSpec for SLC1_RX_SHAREMEM_START_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`slc1_rx_sharemem_start::R`](R) reader structure"] +impl crate::Readable for SLC1_RX_SHAREMEM_START_SPEC {} +#[doc = "`write(|w| ..)` method takes [`slc1_rx_sharemem_start::W`](W) writer structure"] +impl crate::Writable for SLC1_RX_SHAREMEM_START_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SLC1_RX_SHAREMEM_START to value 0"] +impl crate::Resettable for SLC1_RX_SHAREMEM_START_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32c6/src/slc/slc1_tx_sharemem_end.rs b/esp32c6/src/slc/slc1_tx_sharemem_end.rs new file mode 100644 index 000000000..a8e63da4c --- /dev/null +++ b/esp32c6/src/slc/slc1_tx_sharemem_end.rs @@ -0,0 +1,52 @@ +#[doc = "Register `SLC1_TX_SHAREMEM_END` reader"] +pub type R = crate::R; +#[doc = "Register `SLC1_TX_SHAREMEM_END` writer"] +pub type W = crate::W; +#[doc = "Field `SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR` reader - Configures SLC1 host to slave channel AHB end address boundary."] +pub type SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR_R = crate::FieldReader; +#[doc = "Field `SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR` writer - Configures SLC1 host to slave channel AHB end address boundary."] +pub type SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Configures SLC1 host to slave channel AHB end address boundary."] + #[inline(always)] + pub fn sdio_sdio_slc1_tx_sharemem_end_addr(&self) -> SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR_R { + SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SLC1_TX_SHAREMEM_END") + .field( + "sdio_sdio_slc1_tx_sharemem_end_addr", + &self.sdio_sdio_slc1_tx_sharemem_end_addr(), + ) + .finish() + } +} +impl W { + #[doc = "Bits 0:31 - Configures SLC1 host to slave channel AHB end address boundary."] + #[inline(always)] + pub fn sdio_sdio_slc1_tx_sharemem_end_addr( + &mut self, + ) -> SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR_W { + SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR_W::new(self, 0) + } +} +#[doc = "SLC1 AHB TX end address range\n\nYou can [`read`](crate::Reg::read) this register and get [`slc1_tx_sharemem_end::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc1_tx_sharemem_end::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SLC1_TX_SHAREMEM_END_SPEC; +impl crate::RegisterSpec for SLC1_TX_SHAREMEM_END_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`slc1_tx_sharemem_end::R`](R) reader structure"] +impl crate::Readable for SLC1_TX_SHAREMEM_END_SPEC {} +#[doc = "`write(|w| ..)` method takes [`slc1_tx_sharemem_end::W`](W) writer structure"] +impl crate::Writable for SLC1_TX_SHAREMEM_END_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SLC1_TX_SHAREMEM_END to value 0xffff_ffff"] +impl crate::Resettable for SLC1_TX_SHAREMEM_END_SPEC { + const RESET_VALUE: u32 = 0xffff_ffff; +} diff --git a/esp32c6/src/slc/slc1_tx_sharemem_start.rs b/esp32c6/src/slc/slc1_tx_sharemem_start.rs new file mode 100644 index 000000000..8c998b14d --- /dev/null +++ b/esp32c6/src/slc/slc1_tx_sharemem_start.rs @@ -0,0 +1,52 @@ +#[doc = "Register `SLC1_TX_SHAREMEM_START` reader"] +pub type R = crate::R; +#[doc = "Register `SLC1_TX_SHAREMEM_START` writer"] +pub type W = crate::W; +#[doc = "Field `SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR` reader - Configures SLC0 slave to host channel AHB start address boundary."] +pub type SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR_R = crate::FieldReader; +#[doc = "Field `SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR` writer - Configures SLC0 slave to host channel AHB start address boundary."] +pub type SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Configures SLC0 slave to host channel AHB start address boundary."] + #[inline(always)] + pub fn sdio_sdio_slc0_rx_sharemem_start_addr(&self) -> SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR_R { + SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SLC1_TX_SHAREMEM_START") + .field( + "sdio_sdio_slc0_rx_sharemem_start_addr", + &self.sdio_sdio_slc0_rx_sharemem_start_addr(), + ) + .finish() + } +} +impl W { + #[doc = "Bits 0:31 - Configures SLC0 slave to host channel AHB start address boundary."] + #[inline(always)] + pub fn sdio_sdio_slc0_rx_sharemem_start_addr( + &mut self, + ) -> SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR_W { + SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR_W::new(self, 0) + } +} +#[doc = "SLC1 AHB TX start address range\n\nYou can [`read`](crate::Reg::read) this register and get [`slc1_tx_sharemem_start::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc1_tx_sharemem_start::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SLC1_TX_SHAREMEM_START_SPEC; +impl crate::RegisterSpec for SLC1_TX_SHAREMEM_START_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`slc1_tx_sharemem_start::R`](R) reader structure"] +impl crate::Readable for SLC1_TX_SHAREMEM_START_SPEC {} +#[doc = "`write(|w| ..)` method takes [`slc1_tx_sharemem_start::W`](W) writer structure"] +impl crate::Writable for SLC1_TX_SHAREMEM_START_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SLC1_TX_SHAREMEM_START to value 0"] +impl crate::Resettable for SLC1_TX_SHAREMEM_START_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32c6/src/slc/slc1int_clr.rs b/esp32c6/src/slc/slc1int_clr.rs new file mode 100644 index 000000000..b6e95ecdf --- /dev/null +++ b/esp32c6/src/slc/slc1int_clr.rs @@ -0,0 +1,175 @@ +#[doc = "Register `SLC1INT_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `SDIO_SLC_FRHOST_BIT_INT_CLR(0-7)` writer - Write 1 to clear interrupt SLC_FRHOST_BITn_INT (n: 0-7)."] +pub type SDIO_SLC_FRHOST_BIT_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC1_RX_CLRART_INT_CLR` writer - Write 1 to clear interrupt SLC1_RX_CLRART_INT."] +pub type SDIO_SLC1_RX_CLRART_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC1_TX_CLRART_INT_CLR` writer - Write 1 to clear interrupt SLC1_TX_CLRART_INT."] +pub type SDIO_SLC1_TX_CLRART_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC1_RX_UDF_INT_CLR` writer - Write 1 to clear interrupt SLC1_RX_UDF_INT."] +pub type SDIO_SLC1_RX_UDF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC1_TX_OVF_INT_CLR` writer - Write 1 to clear interrupt SLC1_TX_OVF_INT."] +pub type SDIO_SLC1_TX_OVF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC1_TX_DONE_INT_CLR` writer - Write 1 to clear interrupt SLC1_TX_DONE_INT."] +pub type SDIO_SLC1_TX_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC1_TX_SUC_EOF_INT_CLR` writer - Write 1 to clear interrupt SLC1_TX_SUC_EOF_INT."] +pub type SDIO_SLC1_TX_SUC_EOF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC1_RX_DONE_INT_CLR` writer - Write 1 to clear interrupt SLC1_RX_DONE_INT."] +pub type SDIO_SLC1_RX_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC1_RX_EOF_INT_CLR` writer - Write 1 to clear interrupt SLC1_RX_EOF_INT."] +pub type SDIO_SLC1_RX_EOF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC1_TX_DSCR_ERR_INT_CLR` writer - Write 1 to clear interrupt SLC1_TX_DSCR_ERR_INT."] +pub type SDIO_SLC1_TX_DSCR_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC1_RX_DSCR_ERR_INT_CLR` writer - Write 1 to clear interrupt SLC1_RX_DSCR_ERR_INT."] +pub type SDIO_SLC1_RX_DSCR_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Write 1 to clear interrupt SLC_FRHOST_BITn_INT (n: 0-7)."] + #[doc = ""] + #[doc = "
`n` is number of field in register. `n == 0` corresponds to `SDIO_SLC_FRHOST_BIT0_INT_CLR` field.
"] + #[inline(always)] + pub fn sdio_slc_frhost_bit_int_clr( + &mut self, + n: u8, + ) -> SDIO_SLC_FRHOST_BIT_INT_CLR_W { + #[allow(clippy::no_effect)] + [(); 8][n as usize]; + SDIO_SLC_FRHOST_BIT_INT_CLR_W::new(self, n) + } + #[doc = "Bit 0 - Write 1 to clear interrupt SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit0_int_clr( + &mut self, + ) -> SDIO_SLC_FRHOST_BIT_INT_CLR_W { + SDIO_SLC_FRHOST_BIT_INT_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - Write 1 to clear interrupt SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit1_int_clr( + &mut self, + ) -> SDIO_SLC_FRHOST_BIT_INT_CLR_W { + SDIO_SLC_FRHOST_BIT_INT_CLR_W::new(self, 1) + } + #[doc = "Bit 2 - Write 1 to clear interrupt SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit2_int_clr( + &mut self, + ) -> SDIO_SLC_FRHOST_BIT_INT_CLR_W { + SDIO_SLC_FRHOST_BIT_INT_CLR_W::new(self, 2) + } + #[doc = "Bit 3 - Write 1 to clear interrupt SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit3_int_clr( + &mut self, + ) -> SDIO_SLC_FRHOST_BIT_INT_CLR_W { + SDIO_SLC_FRHOST_BIT_INT_CLR_W::new(self, 3) + } + #[doc = "Bit 4 - Write 1 to clear interrupt SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit4_int_clr( + &mut self, + ) -> SDIO_SLC_FRHOST_BIT_INT_CLR_W { + SDIO_SLC_FRHOST_BIT_INT_CLR_W::new(self, 4) + } + #[doc = "Bit 5 - Write 1 to clear interrupt SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit5_int_clr( + &mut self, + ) -> SDIO_SLC_FRHOST_BIT_INT_CLR_W { + SDIO_SLC_FRHOST_BIT_INT_CLR_W::new(self, 5) + } + #[doc = "Bit 6 - Write 1 to clear interrupt SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit6_int_clr( + &mut self, + ) -> SDIO_SLC_FRHOST_BIT_INT_CLR_W { + SDIO_SLC_FRHOST_BIT_INT_CLR_W::new(self, 6) + } + #[doc = "Bit 7 - Write 1 to clear interrupt SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit7_int_clr( + &mut self, + ) -> SDIO_SLC_FRHOST_BIT_INT_CLR_W { + SDIO_SLC_FRHOST_BIT_INT_CLR_W::new(self, 7) + } + #[doc = "Bit 8 - Write 1 to clear interrupt SLC1_RX_CLRART_INT."] + #[inline(always)] + pub fn sdio_slc1_rx_clrart_int_clr( + &mut self, + ) -> SDIO_SLC1_RX_CLRART_INT_CLR_W { + SDIO_SLC1_RX_CLRART_INT_CLR_W::new(self, 8) + } + #[doc = "Bit 9 - Write 1 to clear interrupt SLC1_TX_CLRART_INT."] + #[inline(always)] + pub fn sdio_slc1_tx_clrart_int_clr( + &mut self, + ) -> SDIO_SLC1_TX_CLRART_INT_CLR_W { + SDIO_SLC1_TX_CLRART_INT_CLR_W::new(self, 9) + } + #[doc = "Bit 10 - Write 1 to clear interrupt SLC1_RX_UDF_INT."] + #[inline(always)] + pub fn sdio_slc1_rx_udf_int_clr(&mut self) -> SDIO_SLC1_RX_UDF_INT_CLR_W { + SDIO_SLC1_RX_UDF_INT_CLR_W::new(self, 10) + } + #[doc = "Bit 11 - Write 1 to clear interrupt SLC1_TX_OVF_INT."] + #[inline(always)] + pub fn sdio_slc1_tx_ovf_int_clr(&mut self) -> SDIO_SLC1_TX_OVF_INT_CLR_W { + SDIO_SLC1_TX_OVF_INT_CLR_W::new(self, 11) + } + #[doc = "Bit 14 - Write 1 to clear interrupt SLC1_TX_DONE_INT."] + #[inline(always)] + pub fn sdio_slc1_tx_done_int_clr(&mut self) -> SDIO_SLC1_TX_DONE_INT_CLR_W { + SDIO_SLC1_TX_DONE_INT_CLR_W::new(self, 14) + } + #[doc = "Bit 15 - Write 1 to clear interrupt SLC1_TX_SUC_EOF_INT."] + #[inline(always)] + pub fn sdio_slc1_tx_suc_eof_int_clr( + &mut self, + ) -> SDIO_SLC1_TX_SUC_EOF_INT_CLR_W { + SDIO_SLC1_TX_SUC_EOF_INT_CLR_W::new(self, 15) + } + #[doc = "Bit 16 - Write 1 to clear interrupt SLC1_RX_DONE_INT."] + #[inline(always)] + pub fn sdio_slc1_rx_done_int_clr(&mut self) -> SDIO_SLC1_RX_DONE_INT_CLR_W { + SDIO_SLC1_RX_DONE_INT_CLR_W::new(self, 16) + } + #[doc = "Bit 17 - Write 1 to clear interrupt SLC1_RX_EOF_INT."] + #[inline(always)] + pub fn sdio_slc1_rx_eof_int_clr(&mut self) -> SDIO_SLC1_RX_EOF_INT_CLR_W { + SDIO_SLC1_RX_EOF_INT_CLR_W::new(self, 17) + } + #[doc = "Bit 19 - Write 1 to clear interrupt SLC1_TX_DSCR_ERR_INT."] + #[inline(always)] + pub fn sdio_slc1_tx_dscr_err_int_clr( + &mut self, + ) -> SDIO_SLC1_TX_DSCR_ERR_INT_CLR_W { + SDIO_SLC1_TX_DSCR_ERR_INT_CLR_W::new(self, 19) + } + #[doc = "Bit 20 - Write 1 to clear interrupt SLC1_RX_DSCR_ERR_INT."] + #[inline(always)] + pub fn sdio_slc1_rx_dscr_err_int_clr( + &mut self, + ) -> SDIO_SLC1_RX_DSCR_ERR_INT_CLR_W { + SDIO_SLC1_RX_DSCR_ERR_INT_CLR_W::new(self, 20) + } +} +#[doc = "SLC1 to slave interrupt clear\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc1int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SLC1INT_CLR_SPEC; +impl crate::RegisterSpec for SLC1INT_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`slc1int_clr::W`](W) writer structure"] +impl crate::Writable for SLC1INT_CLR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SLC1INT_CLR to value 0"] +impl crate::Resettable for SLC1INT_CLR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32c6/src/slc/slc1int_ena1.rs b/esp32c6/src/slc/slc1int_ena1.rs new file mode 100644 index 000000000..d7d65d427 --- /dev/null +++ b/esp32c6/src/slc/slc1int_ena1.rs @@ -0,0 +1,387 @@ +#[doc = "Register `SLC1INT_ENA1` reader"] +pub type R = crate::R; +#[doc = "Register `SLC1INT_ENA1` writer"] +pub type W = crate::W; +#[doc = "Field `SDIO_SLC_FRHOST_BIT_INT_ENA1(0-7)` reader - Write 1 to enable interrupt SLC_FRHOST_BITn_INT (n: 0-7)."] +pub type SDIO_SLC_FRHOST_BIT_INT_ENA1_R = crate::BitReader; +#[doc = "Field `SDIO_SLC_FRHOST_BIT_INT_ENA1(0-7)` writer - Write 1 to enable interrupt SLC_FRHOST_BITn_INT (n: 0-7)."] +pub type SDIO_SLC_FRHOST_BIT_INT_ENA1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC1_RX_ENAART_INT_ENA1` reader - Write 1 to enable interrupt SLC1_RX_ENAART_INT."] +pub type SDIO_SLC1_RX_ENAART_INT_ENA1_R = crate::BitReader; +#[doc = "Field `SDIO_SLC1_RX_ENAART_INT_ENA1` writer - Write 1 to enable interrupt SLC1_RX_ENAART_INT."] +pub type SDIO_SLC1_RX_ENAART_INT_ENA1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC1_TX_ENAART_INT_ENA1` reader - Write 1 to enable interrupt SLC1_TX_ENAART_INT."] +pub type SDIO_SLC1_TX_ENAART_INT_ENA1_R = crate::BitReader; +#[doc = "Field `SDIO_SLC1_TX_ENAART_INT_ENA1` writer - Write 1 to enable interrupt SLC1_TX_ENAART_INT."] +pub type SDIO_SLC1_TX_ENAART_INT_ENA1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC1_RX_UDF_INT_ENA1` reader - Write 1 to enable interrupt SLC1_RX_UDF_INT."] +pub type SDIO_SLC1_RX_UDF_INT_ENA1_R = crate::BitReader; +#[doc = "Field `SDIO_SLC1_RX_UDF_INT_ENA1` writer - Write 1 to enable interrupt SLC1_RX_UDF_INT."] +pub type SDIO_SLC1_RX_UDF_INT_ENA1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC1_TX_OVF_INT_ENA1` reader - Write 1 to enable interrupt SLC1_TX_OVF_INT."] +pub type SDIO_SLC1_TX_OVF_INT_ENA1_R = crate::BitReader; +#[doc = "Field `SDIO_SLC1_TX_OVF_INT_ENA1` writer - Write 1 to enable interrupt SLC1_TX_OVF_INT."] +pub type SDIO_SLC1_TX_OVF_INT_ENA1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC1_TX_DONE_INT_ENA1` reader - Write 1 to enable interrupt SLC1_TX_DONE_INT."] +pub type SDIO_SLC1_TX_DONE_INT_ENA1_R = crate::BitReader; +#[doc = "Field `SDIO_SLC1_TX_DONE_INT_ENA1` writer - Write 1 to enable interrupt SLC1_TX_DONE_INT."] +pub type SDIO_SLC1_TX_DONE_INT_ENA1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC1_TX_SUC_EOF_INT_ENA1` reader - Write 1 to enable interrupt SLC1_TX_SUC_EOF_INT."] +pub type SDIO_SLC1_TX_SUC_EOF_INT_ENA1_R = crate::BitReader; +#[doc = "Field `SDIO_SLC1_TX_SUC_EOF_INT_ENA1` writer - Write 1 to enable interrupt SLC1_TX_SUC_EOF_INT."] +pub type SDIO_SLC1_TX_SUC_EOF_INT_ENA1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC1_RX_DONE_INT_ENA1` reader - Write 1 to enable interrupt SLC1_RX_DONE_INT."] +pub type SDIO_SLC1_RX_DONE_INT_ENA1_R = crate::BitReader; +#[doc = "Field `SDIO_SLC1_RX_DONE_INT_ENA1` writer - Write 1 to enable interrupt SLC1_RX_DONE_INT."] +pub type SDIO_SLC1_RX_DONE_INT_ENA1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC1_RX_EOF_INT_ENA1` reader - Write 1 to enable interrupt SLC1_RX_EOF_INT."] +pub type SDIO_SLC1_RX_EOF_INT_ENA1_R = crate::BitReader; +#[doc = "Field `SDIO_SLC1_RX_EOF_INT_ENA1` writer - Write 1 to enable interrupt SLC1_RX_EOF_INT."] +pub type SDIO_SLC1_RX_EOF_INT_ENA1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC1_TX_DSCR_ERR_INT_ENA1` reader - Write 1 to enable interrupt SLC1_TX_DSCR_ERR_INT."] +pub type SDIO_SLC1_TX_DSCR_ERR_INT_ENA1_R = crate::BitReader; +#[doc = "Field `SDIO_SLC1_TX_DSCR_ERR_INT_ENA1` writer - Write 1 to enable interrupt SLC1_TX_DSCR_ERR_INT."] +pub type SDIO_SLC1_TX_DSCR_ERR_INT_ENA1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC1_RX_DSCR_ERR_INT_ENA1` reader - Write 1 to enable interrupt SLC1_RX_DSCR_ERR_INT."] +pub type SDIO_SLC1_RX_DSCR_ERR_INT_ENA1_R = crate::BitReader; +#[doc = "Field `SDIO_SLC1_RX_DSCR_ERR_INT_ENA1` writer - Write 1 to enable interrupt SLC1_RX_DSCR_ERR_INT."] +pub type SDIO_SLC1_RX_DSCR_ERR_INT_ENA1_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Write 1 to enable interrupt SLC_FRHOST_BITn_INT (n: 0-7)."] + #[doc = ""] + #[doc = "
`n` is number of field in register. `n == 0` corresponds to `SDIO_SLC_FRHOST_BIT0_INT_ENA1` field.
"] + #[inline(always)] + pub fn sdio_slc_frhost_bit_int_ena1(&self, n: u8) -> SDIO_SLC_FRHOST_BIT_INT_ENA1_R { + #[allow(clippy::no_effect)] + [(); 8][n as usize]; + SDIO_SLC_FRHOST_BIT_INT_ENA1_R::new(((self.bits >> n) & 1) != 0) + } + #[doc = "Iterator for array of:"] + #[doc = "Write 1 to enable interrupt SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit_int_ena1_iter( + &self, + ) -> impl Iterator + '_ { + (0..8).map(move |n| SDIO_SLC_FRHOST_BIT_INT_ENA1_R::new(((self.bits >> n) & 1) != 0)) + } + #[doc = "Bit 0 - Write 1 to enable interrupt SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit0_int_ena1(&self) -> SDIO_SLC_FRHOST_BIT_INT_ENA1_R { + SDIO_SLC_FRHOST_BIT_INT_ENA1_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Write 1 to enable interrupt SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit1_int_ena1(&self) -> SDIO_SLC_FRHOST_BIT_INT_ENA1_R { + SDIO_SLC_FRHOST_BIT_INT_ENA1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Write 1 to enable interrupt SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit2_int_ena1(&self) -> SDIO_SLC_FRHOST_BIT_INT_ENA1_R { + SDIO_SLC_FRHOST_BIT_INT_ENA1_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Write 1 to enable interrupt SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit3_int_ena1(&self) -> SDIO_SLC_FRHOST_BIT_INT_ENA1_R { + SDIO_SLC_FRHOST_BIT_INT_ENA1_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Write 1 to enable interrupt SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit4_int_ena1(&self) -> SDIO_SLC_FRHOST_BIT_INT_ENA1_R { + SDIO_SLC_FRHOST_BIT_INT_ENA1_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Write 1 to enable interrupt SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit5_int_ena1(&self) -> SDIO_SLC_FRHOST_BIT_INT_ENA1_R { + SDIO_SLC_FRHOST_BIT_INT_ENA1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Write 1 to enable interrupt SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit6_int_ena1(&self) -> SDIO_SLC_FRHOST_BIT_INT_ENA1_R { + SDIO_SLC_FRHOST_BIT_INT_ENA1_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Write 1 to enable interrupt SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit7_int_ena1(&self) -> SDIO_SLC_FRHOST_BIT_INT_ENA1_R { + SDIO_SLC_FRHOST_BIT_INT_ENA1_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Write 1 to enable interrupt SLC1_RX_ENAART_INT."] + #[inline(always)] + pub fn sdio_slc1_rx_enaart_int_ena1(&self) -> SDIO_SLC1_RX_ENAART_INT_ENA1_R { + SDIO_SLC1_RX_ENAART_INT_ENA1_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Write 1 to enable interrupt SLC1_TX_ENAART_INT."] + #[inline(always)] + pub fn sdio_slc1_tx_enaart_int_ena1(&self) -> SDIO_SLC1_TX_ENAART_INT_ENA1_R { + SDIO_SLC1_TX_ENAART_INT_ENA1_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Write 1 to enable interrupt SLC1_RX_UDF_INT."] + #[inline(always)] + pub fn sdio_slc1_rx_udf_int_ena1(&self) -> SDIO_SLC1_RX_UDF_INT_ENA1_R { + SDIO_SLC1_RX_UDF_INT_ENA1_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Write 1 to enable interrupt SLC1_TX_OVF_INT."] + #[inline(always)] + pub fn sdio_slc1_tx_ovf_int_ena1(&self) -> SDIO_SLC1_TX_OVF_INT_ENA1_R { + SDIO_SLC1_TX_OVF_INT_ENA1_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 14 - Write 1 to enable interrupt SLC1_TX_DONE_INT."] + #[inline(always)] + pub fn sdio_slc1_tx_done_int_ena1(&self) -> SDIO_SLC1_TX_DONE_INT_ENA1_R { + SDIO_SLC1_TX_DONE_INT_ENA1_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Write 1 to enable interrupt SLC1_TX_SUC_EOF_INT."] + #[inline(always)] + pub fn sdio_slc1_tx_suc_eof_int_ena1(&self) -> SDIO_SLC1_TX_SUC_EOF_INT_ENA1_R { + SDIO_SLC1_TX_SUC_EOF_INT_ENA1_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Write 1 to enable interrupt SLC1_RX_DONE_INT."] + #[inline(always)] + pub fn sdio_slc1_rx_done_int_ena1(&self) -> SDIO_SLC1_RX_DONE_INT_ENA1_R { + SDIO_SLC1_RX_DONE_INT_ENA1_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Write 1 to enable interrupt SLC1_RX_EOF_INT."] + #[inline(always)] + pub fn sdio_slc1_rx_eof_int_ena1(&self) -> SDIO_SLC1_RX_EOF_INT_ENA1_R { + SDIO_SLC1_RX_EOF_INT_ENA1_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 19 - Write 1 to enable interrupt SLC1_TX_DSCR_ERR_INT."] + #[inline(always)] + pub fn sdio_slc1_tx_dscr_err_int_ena1(&self) -> SDIO_SLC1_TX_DSCR_ERR_INT_ENA1_R { + SDIO_SLC1_TX_DSCR_ERR_INT_ENA1_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Write 1 to enable interrupt SLC1_RX_DSCR_ERR_INT."] + #[inline(always)] + pub fn sdio_slc1_rx_dscr_err_int_ena1(&self) -> SDIO_SLC1_RX_DSCR_ERR_INT_ENA1_R { + SDIO_SLC1_RX_DSCR_ERR_INT_ENA1_R::new(((self.bits >> 20) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SLC1INT_ENA1") + .field( + "sdio_slc_frhost_bit0_int_ena1", + &self.sdio_slc_frhost_bit0_int_ena1(), + ) + .field( + "sdio_slc_frhost_bit1_int_ena1", + &self.sdio_slc_frhost_bit1_int_ena1(), + ) + .field( + "sdio_slc_frhost_bit2_int_ena1", + &self.sdio_slc_frhost_bit2_int_ena1(), + ) + .field( + "sdio_slc_frhost_bit3_int_ena1", + &self.sdio_slc_frhost_bit3_int_ena1(), + ) + .field( + "sdio_slc_frhost_bit4_int_ena1", + &self.sdio_slc_frhost_bit4_int_ena1(), + ) + .field( + "sdio_slc_frhost_bit5_int_ena1", + &self.sdio_slc_frhost_bit5_int_ena1(), + ) + .field( + "sdio_slc_frhost_bit6_int_ena1", + &self.sdio_slc_frhost_bit6_int_ena1(), + ) + .field( + "sdio_slc_frhost_bit7_int_ena1", + &self.sdio_slc_frhost_bit7_int_ena1(), + ) + .field( + "sdio_slc1_rx_enaart_int_ena1", + &self.sdio_slc1_rx_enaart_int_ena1(), + ) + .field( + "sdio_slc1_tx_enaart_int_ena1", + &self.sdio_slc1_tx_enaart_int_ena1(), + ) + .field( + "sdio_slc1_rx_udf_int_ena1", + &self.sdio_slc1_rx_udf_int_ena1(), + ) + .field( + "sdio_slc1_tx_ovf_int_ena1", + &self.sdio_slc1_tx_ovf_int_ena1(), + ) + .field( + "sdio_slc1_tx_done_int_ena1", + &self.sdio_slc1_tx_done_int_ena1(), + ) + .field( + "sdio_slc1_tx_suc_eof_int_ena1", + &self.sdio_slc1_tx_suc_eof_int_ena1(), + ) + .field( + "sdio_slc1_rx_done_int_ena1", + &self.sdio_slc1_rx_done_int_ena1(), + ) + .field( + "sdio_slc1_rx_eof_int_ena1", + &self.sdio_slc1_rx_eof_int_ena1(), + ) + .field( + "sdio_slc1_tx_dscr_err_int_ena1", + &self.sdio_slc1_tx_dscr_err_int_ena1(), + ) + .field( + "sdio_slc1_rx_dscr_err_int_ena1", + &self.sdio_slc1_rx_dscr_err_int_ena1(), + ) + .finish() + } +} +impl W { + #[doc = "Write 1 to enable interrupt SLC_FRHOST_BITn_INT (n: 0-7)."] + #[doc = ""] + #[doc = "
`n` is number of field in register. `n == 0` corresponds to `SDIO_SLC_FRHOST_BIT0_INT_ENA1` field.
"] + #[inline(always)] + pub fn sdio_slc_frhost_bit_int_ena1( + &mut self, + n: u8, + ) -> SDIO_SLC_FRHOST_BIT_INT_ENA1_W { + #[allow(clippy::no_effect)] + [(); 8][n as usize]; + SDIO_SLC_FRHOST_BIT_INT_ENA1_W::new(self, n) + } + #[doc = "Bit 0 - Write 1 to enable interrupt SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit0_int_ena1( + &mut self, + ) -> SDIO_SLC_FRHOST_BIT_INT_ENA1_W { + SDIO_SLC_FRHOST_BIT_INT_ENA1_W::new(self, 0) + } + #[doc = "Bit 1 - Write 1 to enable interrupt SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit1_int_ena1( + &mut self, + ) -> SDIO_SLC_FRHOST_BIT_INT_ENA1_W { + SDIO_SLC_FRHOST_BIT_INT_ENA1_W::new(self, 1) + } + #[doc = "Bit 2 - Write 1 to enable interrupt SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit2_int_ena1( + &mut self, + ) -> SDIO_SLC_FRHOST_BIT_INT_ENA1_W { + SDIO_SLC_FRHOST_BIT_INT_ENA1_W::new(self, 2) + } + #[doc = "Bit 3 - Write 1 to enable interrupt SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit3_int_ena1( + &mut self, + ) -> SDIO_SLC_FRHOST_BIT_INT_ENA1_W { + SDIO_SLC_FRHOST_BIT_INT_ENA1_W::new(self, 3) + } + #[doc = "Bit 4 - Write 1 to enable interrupt SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit4_int_ena1( + &mut self, + ) -> SDIO_SLC_FRHOST_BIT_INT_ENA1_W { + SDIO_SLC_FRHOST_BIT_INT_ENA1_W::new(self, 4) + } + #[doc = "Bit 5 - Write 1 to enable interrupt SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit5_int_ena1( + &mut self, + ) -> SDIO_SLC_FRHOST_BIT_INT_ENA1_W { + SDIO_SLC_FRHOST_BIT_INT_ENA1_W::new(self, 5) + } + #[doc = "Bit 6 - Write 1 to enable interrupt SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit6_int_ena1( + &mut self, + ) -> SDIO_SLC_FRHOST_BIT_INT_ENA1_W { + SDIO_SLC_FRHOST_BIT_INT_ENA1_W::new(self, 6) + } + #[doc = "Bit 7 - Write 1 to enable interrupt SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit7_int_ena1( + &mut self, + ) -> SDIO_SLC_FRHOST_BIT_INT_ENA1_W { + SDIO_SLC_FRHOST_BIT_INT_ENA1_W::new(self, 7) + } + #[doc = "Bit 8 - Write 1 to enable interrupt SLC1_RX_ENAART_INT."] + #[inline(always)] + pub fn sdio_slc1_rx_enaart_int_ena1( + &mut self, + ) -> SDIO_SLC1_RX_ENAART_INT_ENA1_W { + SDIO_SLC1_RX_ENAART_INT_ENA1_W::new(self, 8) + } + #[doc = "Bit 9 - Write 1 to enable interrupt SLC1_TX_ENAART_INT."] + #[inline(always)] + pub fn sdio_slc1_tx_enaart_int_ena1( + &mut self, + ) -> SDIO_SLC1_TX_ENAART_INT_ENA1_W { + SDIO_SLC1_TX_ENAART_INT_ENA1_W::new(self, 9) + } + #[doc = "Bit 10 - Write 1 to enable interrupt SLC1_RX_UDF_INT."] + #[inline(always)] + pub fn sdio_slc1_rx_udf_int_ena1(&mut self) -> SDIO_SLC1_RX_UDF_INT_ENA1_W { + SDIO_SLC1_RX_UDF_INT_ENA1_W::new(self, 10) + } + #[doc = "Bit 11 - Write 1 to enable interrupt SLC1_TX_OVF_INT."] + #[inline(always)] + pub fn sdio_slc1_tx_ovf_int_ena1(&mut self) -> SDIO_SLC1_TX_OVF_INT_ENA1_W { + SDIO_SLC1_TX_OVF_INT_ENA1_W::new(self, 11) + } + #[doc = "Bit 14 - Write 1 to enable interrupt SLC1_TX_DONE_INT."] + #[inline(always)] + pub fn sdio_slc1_tx_done_int_ena1( + &mut self, + ) -> SDIO_SLC1_TX_DONE_INT_ENA1_W { + SDIO_SLC1_TX_DONE_INT_ENA1_W::new(self, 14) + } + #[doc = "Bit 15 - Write 1 to enable interrupt SLC1_TX_SUC_EOF_INT."] + #[inline(always)] + pub fn sdio_slc1_tx_suc_eof_int_ena1( + &mut self, + ) -> SDIO_SLC1_TX_SUC_EOF_INT_ENA1_W { + SDIO_SLC1_TX_SUC_EOF_INT_ENA1_W::new(self, 15) + } + #[doc = "Bit 16 - Write 1 to enable interrupt SLC1_RX_DONE_INT."] + #[inline(always)] + pub fn sdio_slc1_rx_done_int_ena1( + &mut self, + ) -> SDIO_SLC1_RX_DONE_INT_ENA1_W { + SDIO_SLC1_RX_DONE_INT_ENA1_W::new(self, 16) + } + #[doc = "Bit 17 - Write 1 to enable interrupt SLC1_RX_EOF_INT."] + #[inline(always)] + pub fn sdio_slc1_rx_eof_int_ena1(&mut self) -> SDIO_SLC1_RX_EOF_INT_ENA1_W { + SDIO_SLC1_RX_EOF_INT_ENA1_W::new(self, 17) + } + #[doc = "Bit 19 - Write 1 to enable interrupt SLC1_TX_DSCR_ERR_INT."] + #[inline(always)] + pub fn sdio_slc1_tx_dscr_err_int_ena1( + &mut self, + ) -> SDIO_SLC1_TX_DSCR_ERR_INT_ENA1_W { + SDIO_SLC1_TX_DSCR_ERR_INT_ENA1_W::new(self, 19) + } + #[doc = "Bit 20 - Write 1 to enable interrupt SLC1_RX_DSCR_ERR_INT."] + #[inline(always)] + pub fn sdio_slc1_rx_dscr_err_int_ena1( + &mut self, + ) -> SDIO_SLC1_RX_DSCR_ERR_INT_ENA1_W { + SDIO_SLC1_RX_DSCR_ERR_INT_ENA1_W::new(self, 20) + } +} +#[doc = "SLC1 to slave interrupt enable\n\nYou can [`read`](crate::Reg::read) this register and get [`slc1int_ena1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc1int_ena1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SLC1INT_ENA1_SPEC; +impl crate::RegisterSpec for SLC1INT_ENA1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`slc1int_ena1::R`](R) reader structure"] +impl crate::Readable for SLC1INT_ENA1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`slc1int_ena1::W`](W) writer structure"] +impl crate::Writable for SLC1INT_ENA1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SLC1INT_ENA1 to value 0"] +impl crate::Resettable for SLC1INT_ENA1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32c6/src/slc/slc1int_raw.rs b/esp32c6/src/slc/slc1int_raw.rs new file mode 100644 index 000000000..08dc2a77d --- /dev/null +++ b/esp32c6/src/slc/slc1int_raw.rs @@ -0,0 +1,370 @@ +#[doc = "Register `SLC1INT_RAW` reader"] +pub type R = crate::R; +#[doc = "Register `SLC1INT_RAW` writer"] +pub type W = crate::W; +#[doc = "Field `SDIO_SLC_FRHOST_BIT_INT_RAW(0-7)` reader - The raw interrupt status of SLC_FRHOST_BITn_INT (n: 0-7)."] +pub type SDIO_SLC_FRHOST_BIT_INT_RAW_R = crate::BitReader; +#[doc = "Field `SDIO_SLC_FRHOST_BIT_INT_RAW(0-7)` writer - The raw interrupt status of SLC_FRHOST_BITn_INT (n: 0-7)."] +pub type SDIO_SLC_FRHOST_BIT_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC1_RX_START_INT_RAW` reader - The raw interrupt status of SLC1_RX_START_INT."] +pub type SDIO_SLC1_RX_START_INT_RAW_R = crate::BitReader; +#[doc = "Field `SDIO_SLC1_RX_START_INT_RAW` writer - The raw interrupt status of SLC1_RX_START_INT."] +pub type SDIO_SLC1_RX_START_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC1_TX_START_INT_RAW` reader - The raw interrupt status of SLC1_TX_START_INT."] +pub type SDIO_SLC1_TX_START_INT_RAW_R = crate::BitReader; +#[doc = "Field `SDIO_SLC1_TX_START_INT_RAW` writer - The raw interrupt status of SLC1_TX_START_INT."] +pub type SDIO_SLC1_TX_START_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC1_RX_UDF_INT_RAW` reader - The raw interrupt status of SLC1_RX_UDF_INT."] +pub type SDIO_SLC1_RX_UDF_INT_RAW_R = crate::BitReader; +#[doc = "Field `SDIO_SLC1_RX_UDF_INT_RAW` writer - The raw interrupt status of SLC1_RX_UDF_INT."] +pub type SDIO_SLC1_RX_UDF_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC1_TX_OVF_INT_RAW` reader - The raw interrupt status of SLC1_TX_OVF_INT."] +pub type SDIO_SLC1_TX_OVF_INT_RAW_R = crate::BitReader; +#[doc = "Field `SDIO_SLC1_TX_OVF_INT_RAW` writer - The raw interrupt status of SLC1_TX_OVF_INT."] +pub type SDIO_SLC1_TX_OVF_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC1_TX_DONE_INT_RAW` reader - The raw interrupt status of SLC1_TX_DONE_INT."] +pub type SDIO_SLC1_TX_DONE_INT_RAW_R = crate::BitReader; +#[doc = "Field `SDIO_SLC1_TX_DONE_INT_RAW` writer - The raw interrupt status of SLC1_TX_DONE_INT."] +pub type SDIO_SLC1_TX_DONE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC1_TX_SUC_EOF_INT_RAW` reader - The raw interrupt status of SLC1_TX_SUC_EOF_INT."] +pub type SDIO_SLC1_TX_SUC_EOF_INT_RAW_R = crate::BitReader; +#[doc = "Field `SDIO_SLC1_TX_SUC_EOF_INT_RAW` writer - The raw interrupt status of SLC1_TX_SUC_EOF_INT."] +pub type SDIO_SLC1_TX_SUC_EOF_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC1_RX_DONE_INT_RAW` reader - The raw interrupt status of SLC1_RX_DONE_INT."] +pub type SDIO_SLC1_RX_DONE_INT_RAW_R = crate::BitReader; +#[doc = "Field `SDIO_SLC1_RX_DONE_INT_RAW` writer - The raw interrupt status of SLC1_RX_DONE_INT."] +pub type SDIO_SLC1_RX_DONE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC1_RX_EOF_INT_RAW` reader - The raw interrupt status of SLC1_RX_EOF_INT."] +pub type SDIO_SLC1_RX_EOF_INT_RAW_R = crate::BitReader; +#[doc = "Field `SDIO_SLC1_RX_EOF_INT_RAW` writer - The raw interrupt status of SLC1_RX_EOF_INT."] +pub type SDIO_SLC1_RX_EOF_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC1_TX_DSCR_ERR_INT_RAW` reader - The raw interrupt status of SLC1_TX_DSCR_ERR_INT."] +pub type SDIO_SLC1_TX_DSCR_ERR_INT_RAW_R = crate::BitReader; +#[doc = "Field `SDIO_SLC1_TX_DSCR_ERR_INT_RAW` writer - The raw interrupt status of SLC1_TX_DSCR_ERR_INT."] +pub type SDIO_SLC1_TX_DSCR_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC1_RX_DSCR_ERR_INT_RAW` reader - The raw interrupt status of SLC1_RX_DSCR_ERR_INT."] +pub type SDIO_SLC1_RX_DSCR_ERR_INT_RAW_R = crate::BitReader; +#[doc = "Field `SDIO_SLC1_RX_DSCR_ERR_INT_RAW` writer - The raw interrupt status of SLC1_RX_DSCR_ERR_INT."] +pub type SDIO_SLC1_RX_DSCR_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "The raw interrupt status of SLC_FRHOST_BITn_INT (n: 0-7)."] + #[doc = ""] + #[doc = "
`n` is number of field in register. `n == 0` corresponds to `SDIO_SLC_FRHOST_BIT0_INT_RAW` field.
"] + #[inline(always)] + pub fn sdio_slc_frhost_bit_int_raw(&self, n: u8) -> SDIO_SLC_FRHOST_BIT_INT_RAW_R { + #[allow(clippy::no_effect)] + [(); 8][n as usize]; + SDIO_SLC_FRHOST_BIT_INT_RAW_R::new(((self.bits >> n) & 1) != 0) + } + #[doc = "Iterator for array of:"] + #[doc = "The raw interrupt status of SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit_int_raw_iter( + &self, + ) -> impl Iterator + '_ { + (0..8).map(move |n| SDIO_SLC_FRHOST_BIT_INT_RAW_R::new(((self.bits >> n) & 1) != 0)) + } + #[doc = "Bit 0 - The raw interrupt status of SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit0_int_raw(&self) -> SDIO_SLC_FRHOST_BIT_INT_RAW_R { + SDIO_SLC_FRHOST_BIT_INT_RAW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The raw interrupt status of SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit1_int_raw(&self) -> SDIO_SLC_FRHOST_BIT_INT_RAW_R { + SDIO_SLC_FRHOST_BIT_INT_RAW_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The raw interrupt status of SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit2_int_raw(&self) -> SDIO_SLC_FRHOST_BIT_INT_RAW_R { + SDIO_SLC_FRHOST_BIT_INT_RAW_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The raw interrupt status of SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit3_int_raw(&self) -> SDIO_SLC_FRHOST_BIT_INT_RAW_R { + SDIO_SLC_FRHOST_BIT_INT_RAW_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The raw interrupt status of SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit4_int_raw(&self) -> SDIO_SLC_FRHOST_BIT_INT_RAW_R { + SDIO_SLC_FRHOST_BIT_INT_RAW_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The raw interrupt status of SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit5_int_raw(&self) -> SDIO_SLC_FRHOST_BIT_INT_RAW_R { + SDIO_SLC_FRHOST_BIT_INT_RAW_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The raw interrupt status of SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit6_int_raw(&self) -> SDIO_SLC_FRHOST_BIT_INT_RAW_R { + SDIO_SLC_FRHOST_BIT_INT_RAW_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - The raw interrupt status of SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit7_int_raw(&self) -> SDIO_SLC_FRHOST_BIT_INT_RAW_R { + SDIO_SLC_FRHOST_BIT_INT_RAW_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The raw interrupt status of SLC1_RX_START_INT."] + #[inline(always)] + pub fn sdio_slc1_rx_start_int_raw(&self) -> SDIO_SLC1_RX_START_INT_RAW_R { + SDIO_SLC1_RX_START_INT_RAW_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - The raw interrupt status of SLC1_TX_START_INT."] + #[inline(always)] + pub fn sdio_slc1_tx_start_int_raw(&self) -> SDIO_SLC1_TX_START_INT_RAW_R { + SDIO_SLC1_TX_START_INT_RAW_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - The raw interrupt status of SLC1_RX_UDF_INT."] + #[inline(always)] + pub fn sdio_slc1_rx_udf_int_raw(&self) -> SDIO_SLC1_RX_UDF_INT_RAW_R { + SDIO_SLC1_RX_UDF_INT_RAW_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - The raw interrupt status of SLC1_TX_OVF_INT."] + #[inline(always)] + pub fn sdio_slc1_tx_ovf_int_raw(&self) -> SDIO_SLC1_TX_OVF_INT_RAW_R { + SDIO_SLC1_TX_OVF_INT_RAW_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 14 - The raw interrupt status of SLC1_TX_DONE_INT."] + #[inline(always)] + pub fn sdio_slc1_tx_done_int_raw(&self) -> SDIO_SLC1_TX_DONE_INT_RAW_R { + SDIO_SLC1_TX_DONE_INT_RAW_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - The raw interrupt status of SLC1_TX_SUC_EOF_INT."] + #[inline(always)] + pub fn sdio_slc1_tx_suc_eof_int_raw(&self) -> SDIO_SLC1_TX_SUC_EOF_INT_RAW_R { + SDIO_SLC1_TX_SUC_EOF_INT_RAW_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - The raw interrupt status of SLC1_RX_DONE_INT."] + #[inline(always)] + pub fn sdio_slc1_rx_done_int_raw(&self) -> SDIO_SLC1_RX_DONE_INT_RAW_R { + SDIO_SLC1_RX_DONE_INT_RAW_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - The raw interrupt status of SLC1_RX_EOF_INT."] + #[inline(always)] + pub fn sdio_slc1_rx_eof_int_raw(&self) -> SDIO_SLC1_RX_EOF_INT_RAW_R { + SDIO_SLC1_RX_EOF_INT_RAW_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 19 - The raw interrupt status of SLC1_TX_DSCR_ERR_INT."] + #[inline(always)] + pub fn sdio_slc1_tx_dscr_err_int_raw(&self) -> SDIO_SLC1_TX_DSCR_ERR_INT_RAW_R { + SDIO_SLC1_TX_DSCR_ERR_INT_RAW_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - The raw interrupt status of SLC1_RX_DSCR_ERR_INT."] + #[inline(always)] + pub fn sdio_slc1_rx_dscr_err_int_raw(&self) -> SDIO_SLC1_RX_DSCR_ERR_INT_RAW_R { + SDIO_SLC1_RX_DSCR_ERR_INT_RAW_R::new(((self.bits >> 20) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SLC1INT_RAW") + .field( + "sdio_slc_frhost_bit0_int_raw", + &self.sdio_slc_frhost_bit0_int_raw(), + ) + .field( + "sdio_slc_frhost_bit1_int_raw", + &self.sdio_slc_frhost_bit1_int_raw(), + ) + .field( + "sdio_slc_frhost_bit2_int_raw", + &self.sdio_slc_frhost_bit2_int_raw(), + ) + .field( + "sdio_slc_frhost_bit3_int_raw", + &self.sdio_slc_frhost_bit3_int_raw(), + ) + .field( + "sdio_slc_frhost_bit4_int_raw", + &self.sdio_slc_frhost_bit4_int_raw(), + ) + .field( + "sdio_slc_frhost_bit5_int_raw", + &self.sdio_slc_frhost_bit5_int_raw(), + ) + .field( + "sdio_slc_frhost_bit6_int_raw", + &self.sdio_slc_frhost_bit6_int_raw(), + ) + .field( + "sdio_slc_frhost_bit7_int_raw", + &self.sdio_slc_frhost_bit7_int_raw(), + ) + .field( + "sdio_slc1_rx_start_int_raw", + &self.sdio_slc1_rx_start_int_raw(), + ) + .field( + "sdio_slc1_tx_start_int_raw", + &self.sdio_slc1_tx_start_int_raw(), + ) + .field("sdio_slc1_rx_udf_int_raw", &self.sdio_slc1_rx_udf_int_raw()) + .field("sdio_slc1_tx_ovf_int_raw", &self.sdio_slc1_tx_ovf_int_raw()) + .field( + "sdio_slc1_tx_done_int_raw", + &self.sdio_slc1_tx_done_int_raw(), + ) + .field( + "sdio_slc1_tx_suc_eof_int_raw", + &self.sdio_slc1_tx_suc_eof_int_raw(), + ) + .field( + "sdio_slc1_rx_done_int_raw", + &self.sdio_slc1_rx_done_int_raw(), + ) + .field("sdio_slc1_rx_eof_int_raw", &self.sdio_slc1_rx_eof_int_raw()) + .field( + "sdio_slc1_tx_dscr_err_int_raw", + &self.sdio_slc1_tx_dscr_err_int_raw(), + ) + .field( + "sdio_slc1_rx_dscr_err_int_raw", + &self.sdio_slc1_rx_dscr_err_int_raw(), + ) + .finish() + } +} +impl W { + #[doc = "The raw interrupt status of SLC_FRHOST_BITn_INT (n: 0-7)."] + #[doc = ""] + #[doc = "
`n` is number of field in register. `n == 0` corresponds to `SDIO_SLC_FRHOST_BIT0_INT_RAW` field.
"] + #[inline(always)] + pub fn sdio_slc_frhost_bit_int_raw( + &mut self, + n: u8, + ) -> SDIO_SLC_FRHOST_BIT_INT_RAW_W { + #[allow(clippy::no_effect)] + [(); 8][n as usize]; + SDIO_SLC_FRHOST_BIT_INT_RAW_W::new(self, n) + } + #[doc = "Bit 0 - The raw interrupt status of SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit0_int_raw( + &mut self, + ) -> SDIO_SLC_FRHOST_BIT_INT_RAW_W { + SDIO_SLC_FRHOST_BIT_INT_RAW_W::new(self, 0) + } + #[doc = "Bit 1 - The raw interrupt status of SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit1_int_raw( + &mut self, + ) -> SDIO_SLC_FRHOST_BIT_INT_RAW_W { + SDIO_SLC_FRHOST_BIT_INT_RAW_W::new(self, 1) + } + #[doc = "Bit 2 - The raw interrupt status of SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit2_int_raw( + &mut self, + ) -> SDIO_SLC_FRHOST_BIT_INT_RAW_W { + SDIO_SLC_FRHOST_BIT_INT_RAW_W::new(self, 2) + } + #[doc = "Bit 3 - The raw interrupt status of SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit3_int_raw( + &mut self, + ) -> SDIO_SLC_FRHOST_BIT_INT_RAW_W { + SDIO_SLC_FRHOST_BIT_INT_RAW_W::new(self, 3) + } + #[doc = "Bit 4 - The raw interrupt status of SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit4_int_raw( + &mut self, + ) -> SDIO_SLC_FRHOST_BIT_INT_RAW_W { + SDIO_SLC_FRHOST_BIT_INT_RAW_W::new(self, 4) + } + #[doc = "Bit 5 - The raw interrupt status of SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit5_int_raw( + &mut self, + ) -> SDIO_SLC_FRHOST_BIT_INT_RAW_W { + SDIO_SLC_FRHOST_BIT_INT_RAW_W::new(self, 5) + } + #[doc = "Bit 6 - The raw interrupt status of SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit6_int_raw( + &mut self, + ) -> SDIO_SLC_FRHOST_BIT_INT_RAW_W { + SDIO_SLC_FRHOST_BIT_INT_RAW_W::new(self, 6) + } + #[doc = "Bit 7 - The raw interrupt status of SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit7_int_raw( + &mut self, + ) -> SDIO_SLC_FRHOST_BIT_INT_RAW_W { + SDIO_SLC_FRHOST_BIT_INT_RAW_W::new(self, 7) + } + #[doc = "Bit 8 - The raw interrupt status of SLC1_RX_START_INT."] + #[inline(always)] + pub fn sdio_slc1_rx_start_int_raw(&mut self) -> SDIO_SLC1_RX_START_INT_RAW_W { + SDIO_SLC1_RX_START_INT_RAW_W::new(self, 8) + } + #[doc = "Bit 9 - The raw interrupt status of SLC1_TX_START_INT."] + #[inline(always)] + pub fn sdio_slc1_tx_start_int_raw(&mut self) -> SDIO_SLC1_TX_START_INT_RAW_W { + SDIO_SLC1_TX_START_INT_RAW_W::new(self, 9) + } + #[doc = "Bit 10 - The raw interrupt status of SLC1_RX_UDF_INT."] + #[inline(always)] + pub fn sdio_slc1_rx_udf_int_raw(&mut self) -> SDIO_SLC1_RX_UDF_INT_RAW_W { + SDIO_SLC1_RX_UDF_INT_RAW_W::new(self, 10) + } + #[doc = "Bit 11 - The raw interrupt status of SLC1_TX_OVF_INT."] + #[inline(always)] + pub fn sdio_slc1_tx_ovf_int_raw(&mut self) -> SDIO_SLC1_TX_OVF_INT_RAW_W { + SDIO_SLC1_TX_OVF_INT_RAW_W::new(self, 11) + } + #[doc = "Bit 14 - The raw interrupt status of SLC1_TX_DONE_INT."] + #[inline(always)] + pub fn sdio_slc1_tx_done_int_raw(&mut self) -> SDIO_SLC1_TX_DONE_INT_RAW_W { + SDIO_SLC1_TX_DONE_INT_RAW_W::new(self, 14) + } + #[doc = "Bit 15 - The raw interrupt status of SLC1_TX_SUC_EOF_INT."] + #[inline(always)] + pub fn sdio_slc1_tx_suc_eof_int_raw( + &mut self, + ) -> SDIO_SLC1_TX_SUC_EOF_INT_RAW_W { + SDIO_SLC1_TX_SUC_EOF_INT_RAW_W::new(self, 15) + } + #[doc = "Bit 16 - The raw interrupt status of SLC1_RX_DONE_INT."] + #[inline(always)] + pub fn sdio_slc1_rx_done_int_raw(&mut self) -> SDIO_SLC1_RX_DONE_INT_RAW_W { + SDIO_SLC1_RX_DONE_INT_RAW_W::new(self, 16) + } + #[doc = "Bit 17 - The raw interrupt status of SLC1_RX_EOF_INT."] + #[inline(always)] + pub fn sdio_slc1_rx_eof_int_raw(&mut self) -> SDIO_SLC1_RX_EOF_INT_RAW_W { + SDIO_SLC1_RX_EOF_INT_RAW_W::new(self, 17) + } + #[doc = "Bit 19 - The raw interrupt status of SLC1_TX_DSCR_ERR_INT."] + #[inline(always)] + pub fn sdio_slc1_tx_dscr_err_int_raw( + &mut self, + ) -> SDIO_SLC1_TX_DSCR_ERR_INT_RAW_W { + SDIO_SLC1_TX_DSCR_ERR_INT_RAW_W::new(self, 19) + } + #[doc = "Bit 20 - The raw interrupt status of SLC1_RX_DSCR_ERR_INT."] + #[inline(always)] + pub fn sdio_slc1_rx_dscr_err_int_raw( + &mut self, + ) -> SDIO_SLC1_RX_DSCR_ERR_INT_RAW_W { + SDIO_SLC1_RX_DSCR_ERR_INT_RAW_W::new(self, 20) + } +} +#[doc = "SLC1 to slave raw interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`slc1int_raw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc1int_raw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SLC1INT_RAW_SPEC; +impl crate::RegisterSpec for SLC1INT_RAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`slc1int_raw::R`](R) reader structure"] +impl crate::Readable for SLC1INT_RAW_SPEC {} +#[doc = "`write(|w| ..)` method takes [`slc1int_raw::W`](W) writer structure"] +impl crate::Writable for SLC1INT_RAW_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SLC1INT_RAW to value 0"] +impl crate::Resettable for SLC1INT_RAW_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32c6/src/slc/slc1int_st1.rs b/esp32c6/src/slc/slc1int_st1.rs new file mode 100644 index 000000000..c437eb00a --- /dev/null +++ b/esp32c6/src/slc/slc1int_st1.rs @@ -0,0 +1,214 @@ +#[doc = "Register `SLC1INT_ST1` reader"] +pub type R = crate::R; +#[doc = "Field `SDIO_SLC_FRHOST_BIT_INT_ST1(0-7)` reader - The masked interrupt status of SLC_FRHOST_BITn_INT (n: 0-7)."] +pub type SDIO_SLC_FRHOST_BIT_INT_ST1_R = crate::BitReader; +#[doc = "Field `SDIO_SLC1_RX_START_INT_ST1` reader - The masked interrupt status of SLC1_RX_START_INT."] +pub type SDIO_SLC1_RX_START_INT_ST1_R = crate::BitReader; +#[doc = "Field `SDIO_SLC1_TX_START_INT_ST1` reader - The masked interrupt status of SLC1_TX_START_INT."] +pub type SDIO_SLC1_TX_START_INT_ST1_R = crate::BitReader; +#[doc = "Field `SDIO_SLC1_RX_UDF_INT_ST1` reader - The masked interrupt status of SLC1_RX_UDF_INT."] +pub type SDIO_SLC1_RX_UDF_INT_ST1_R = crate::BitReader; +#[doc = "Field `SDIO_SLC1_TX_OVF_INT_ST1` reader - The masked interrupt status of SLC1_TX_OVF_INT."] +pub type SDIO_SLC1_TX_OVF_INT_ST1_R = crate::BitReader; +#[doc = "Field `SDIO_SLC1_TX_DONE_INT_ST1` reader - The masked interrupt status of SLC1_TX_DONE_INT."] +pub type SDIO_SLC1_TX_DONE_INT_ST1_R = crate::BitReader; +#[doc = "Field `SDIO_SLC1_TX_SUC_EOF_INT_ST1` reader - The masked interrupt status of SLC1_TX_SUC_EOF_INT."] +pub type SDIO_SLC1_TX_SUC_EOF_INT_ST1_R = crate::BitReader; +#[doc = "Field `SDIO_SLC1_RX_DONE_INT_ST1` reader - The masked interrupt status of SLC1_RX_DONE_INT."] +pub type SDIO_SLC1_RX_DONE_INT_ST1_R = crate::BitReader; +#[doc = "Field `SDIO_SLC1_RX_EOF_INT_ST1` reader - The masked interrupt status of SLC1_RX_EOF_INT."] +pub type SDIO_SLC1_RX_EOF_INT_ST1_R = crate::BitReader; +#[doc = "Field `SDIO_SLC1_TX_DSCR_ERR_INT_ST1` reader - The masked interrupt status of SLC1_TX_DSCR_ERR_INT."] +pub type SDIO_SLC1_TX_DSCR_ERR_INT_ST1_R = crate::BitReader; +#[doc = "Field `SDIO_SLC1_RX_DSCR_ERR_INT_ST1` reader - The masked interrupt status of SLC1_RX_DSCR_ERR_INT."] +pub type SDIO_SLC1_RX_DSCR_ERR_INT_ST1_R = crate::BitReader; +impl R { + #[doc = "The masked interrupt status of SLC_FRHOST_BITn_INT (n: 0-7)."] + #[doc = ""] + #[doc = "
`n` is number of field in register. `n == 0` corresponds to `SDIO_SLC_FRHOST_BIT0_INT_ST1` field.
"] + #[inline(always)] + pub fn sdio_slc_frhost_bit_int_st1(&self, n: u8) -> SDIO_SLC_FRHOST_BIT_INT_ST1_R { + #[allow(clippy::no_effect)] + [(); 8][n as usize]; + SDIO_SLC_FRHOST_BIT_INT_ST1_R::new(((self.bits >> n) & 1) != 0) + } + #[doc = "Iterator for array of:"] + #[doc = "The masked interrupt status of SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit_int_st1_iter( + &self, + ) -> impl Iterator + '_ { + (0..8).map(move |n| SDIO_SLC_FRHOST_BIT_INT_ST1_R::new(((self.bits >> n) & 1) != 0)) + } + #[doc = "Bit 0 - The masked interrupt status of SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit0_int_st1(&self) -> SDIO_SLC_FRHOST_BIT_INT_ST1_R { + SDIO_SLC_FRHOST_BIT_INT_ST1_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The masked interrupt status of SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit1_int_st1(&self) -> SDIO_SLC_FRHOST_BIT_INT_ST1_R { + SDIO_SLC_FRHOST_BIT_INT_ST1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The masked interrupt status of SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit2_int_st1(&self) -> SDIO_SLC_FRHOST_BIT_INT_ST1_R { + SDIO_SLC_FRHOST_BIT_INT_ST1_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The masked interrupt status of SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit3_int_st1(&self) -> SDIO_SLC_FRHOST_BIT_INT_ST1_R { + SDIO_SLC_FRHOST_BIT_INT_ST1_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The masked interrupt status of SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit4_int_st1(&self) -> SDIO_SLC_FRHOST_BIT_INT_ST1_R { + SDIO_SLC_FRHOST_BIT_INT_ST1_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The masked interrupt status of SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit5_int_st1(&self) -> SDIO_SLC_FRHOST_BIT_INT_ST1_R { + SDIO_SLC_FRHOST_BIT_INT_ST1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The masked interrupt status of SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit6_int_st1(&self) -> SDIO_SLC_FRHOST_BIT_INT_ST1_R { + SDIO_SLC_FRHOST_BIT_INT_ST1_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - The masked interrupt status of SLC_FRHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc_frhost_bit7_int_st1(&self) -> SDIO_SLC_FRHOST_BIT_INT_ST1_R { + SDIO_SLC_FRHOST_BIT_INT_ST1_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The masked interrupt status of SLC1_RX_START_INT."] + #[inline(always)] + pub fn sdio_slc1_rx_start_int_st1(&self) -> SDIO_SLC1_RX_START_INT_ST1_R { + SDIO_SLC1_RX_START_INT_ST1_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - The masked interrupt status of SLC1_TX_START_INT."] + #[inline(always)] + pub fn sdio_slc1_tx_start_int_st1(&self) -> SDIO_SLC1_TX_START_INT_ST1_R { + SDIO_SLC1_TX_START_INT_ST1_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - The masked interrupt status of SLC1_RX_UDF_INT."] + #[inline(always)] + pub fn sdio_slc1_rx_udf_int_st1(&self) -> SDIO_SLC1_RX_UDF_INT_ST1_R { + SDIO_SLC1_RX_UDF_INT_ST1_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - The masked interrupt status of SLC1_TX_OVF_INT."] + #[inline(always)] + pub fn sdio_slc1_tx_ovf_int_st1(&self) -> SDIO_SLC1_TX_OVF_INT_ST1_R { + SDIO_SLC1_TX_OVF_INT_ST1_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 14 - The masked interrupt status of SLC1_TX_DONE_INT."] + #[inline(always)] + pub fn sdio_slc1_tx_done_int_st1(&self) -> SDIO_SLC1_TX_DONE_INT_ST1_R { + SDIO_SLC1_TX_DONE_INT_ST1_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - The masked interrupt status of SLC1_TX_SUC_EOF_INT."] + #[inline(always)] + pub fn sdio_slc1_tx_suc_eof_int_st1(&self) -> SDIO_SLC1_TX_SUC_EOF_INT_ST1_R { + SDIO_SLC1_TX_SUC_EOF_INT_ST1_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - The masked interrupt status of SLC1_RX_DONE_INT."] + #[inline(always)] + pub fn sdio_slc1_rx_done_int_st1(&self) -> SDIO_SLC1_RX_DONE_INT_ST1_R { + SDIO_SLC1_RX_DONE_INT_ST1_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - The masked interrupt status of SLC1_RX_EOF_INT."] + #[inline(always)] + pub fn sdio_slc1_rx_eof_int_st1(&self) -> SDIO_SLC1_RX_EOF_INT_ST1_R { + SDIO_SLC1_RX_EOF_INT_ST1_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 19 - The masked interrupt status of SLC1_TX_DSCR_ERR_INT."] + #[inline(always)] + pub fn sdio_slc1_tx_dscr_err_int_st1(&self) -> SDIO_SLC1_TX_DSCR_ERR_INT_ST1_R { + SDIO_SLC1_TX_DSCR_ERR_INT_ST1_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - The masked interrupt status of SLC1_RX_DSCR_ERR_INT."] + #[inline(always)] + pub fn sdio_slc1_rx_dscr_err_int_st1(&self) -> SDIO_SLC1_RX_DSCR_ERR_INT_ST1_R { + SDIO_SLC1_RX_DSCR_ERR_INT_ST1_R::new(((self.bits >> 20) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SLC1INT_ST1") + .field( + "sdio_slc_frhost_bit0_int_st1", + &self.sdio_slc_frhost_bit0_int_st1(), + ) + .field( + "sdio_slc_frhost_bit1_int_st1", + &self.sdio_slc_frhost_bit1_int_st1(), + ) + .field( + "sdio_slc_frhost_bit2_int_st1", + &self.sdio_slc_frhost_bit2_int_st1(), + ) + .field( + "sdio_slc_frhost_bit3_int_st1", + &self.sdio_slc_frhost_bit3_int_st1(), + ) + .field( + "sdio_slc_frhost_bit4_int_st1", + &self.sdio_slc_frhost_bit4_int_st1(), + ) + .field( + "sdio_slc_frhost_bit5_int_st1", + &self.sdio_slc_frhost_bit5_int_st1(), + ) + .field( + "sdio_slc_frhost_bit6_int_st1", + &self.sdio_slc_frhost_bit6_int_st1(), + ) + .field( + "sdio_slc_frhost_bit7_int_st1", + &self.sdio_slc_frhost_bit7_int_st1(), + ) + .field( + "sdio_slc1_rx_start_int_st1", + &self.sdio_slc1_rx_start_int_st1(), + ) + .field( + "sdio_slc1_tx_start_int_st1", + &self.sdio_slc1_tx_start_int_st1(), + ) + .field("sdio_slc1_rx_udf_int_st1", &self.sdio_slc1_rx_udf_int_st1()) + .field("sdio_slc1_tx_ovf_int_st1", &self.sdio_slc1_tx_ovf_int_st1()) + .field( + "sdio_slc1_tx_done_int_st1", + &self.sdio_slc1_tx_done_int_st1(), + ) + .field( + "sdio_slc1_tx_suc_eof_int_st1", + &self.sdio_slc1_tx_suc_eof_int_st1(), + ) + .field( + "sdio_slc1_rx_done_int_st1", + &self.sdio_slc1_rx_done_int_st1(), + ) + .field("sdio_slc1_rx_eof_int_st1", &self.sdio_slc1_rx_eof_int_st1()) + .field( + "sdio_slc1_tx_dscr_err_int_st1", + &self.sdio_slc1_tx_dscr_err_int_st1(), + ) + .field( + "sdio_slc1_rx_dscr_err_int_st1", + &self.sdio_slc1_rx_dscr_err_int_st1(), + ) + .finish() + } +} +#[doc = "SLC1 to slave masked interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`slc1int_st1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SLC1INT_ST1_SPEC; +impl crate::RegisterSpec for SLC1INT_ST1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`slc1int_st1::R`](R) reader structure"] +impl crate::Readable for SLC1INT_ST1_SPEC {} +#[doc = "`reset()` method sets SLC1INT_ST1 to value 0"] +impl crate::Resettable for SLC1INT_ST1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32c6/src/slc/slc1rx_link.rs b/esp32c6/src/slc/slc1rx_link.rs new file mode 100644 index 000000000..77a06fdef --- /dev/null +++ b/esp32c6/src/slc/slc1rx_link.rs @@ -0,0 +1,92 @@ +#[doc = "Register `SLC1RX_LINK` reader"] +pub type R = crate::R; +#[doc = "Register `SLC1RX_LINK` writer"] +pub type W = crate::W; +#[doc = "Field `SDIO_SLC1_RXLINK_STOP` reader - Configures whether to stop SLC1 RX linked list operation."] +pub type SDIO_SLC1_RXLINK_STOP_R = crate::BitReader; +#[doc = "Field `SDIO_SLC1_RXLINK_STOP` writer - Configures whether to stop SLC1 RX linked list operation."] +pub type SDIO_SLC1_RXLINK_STOP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC1_RXLINK_START` reader - Configures whether to start SLC1 RX linked list operation from the address indicated by SDIO_SLC1_RXLINK_ADDR."] +pub type SDIO_SLC1_RXLINK_START_R = crate::BitReader; +#[doc = "Field `SDIO_SLC1_RXLINK_START` writer - Configures whether to start SLC1 RX linked list operation from the address indicated by SDIO_SLC1_RXLINK_ADDR."] +pub type SDIO_SLC1_RXLINK_START_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC1_RXLINK_RESTART` reader - Configures whether to restart and continue SLC1 RX linked list operation."] +pub type SDIO_SLC1_RXLINK_RESTART_R = crate::BitReader; +#[doc = "Field `SDIO_SLC1_RXLINK_RESTART` writer - Configures whether to restart and continue SLC1 RX linked list operation."] +pub type SDIO_SLC1_RXLINK_RESTART_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC1_RXLINK_PARK` reader - Represents SLC1 RX linked list FSM state."] +pub type SDIO_SLC1_RXLINK_PARK_R = crate::BitReader; +#[doc = "Field `SDIO_SLC1_RXLINK_PARK` writer - Represents SLC1 RX linked list FSM state."] +pub type SDIO_SLC1_RXLINK_PARK_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 28 - Configures whether to stop SLC1 RX linked list operation."] + #[inline(always)] + pub fn sdio_slc1_rxlink_stop(&self) -> SDIO_SLC1_RXLINK_STOP_R { + SDIO_SLC1_RXLINK_STOP_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Configures whether to start SLC1 RX linked list operation from the address indicated by SDIO_SLC1_RXLINK_ADDR."] + #[inline(always)] + pub fn sdio_slc1_rxlink_start(&self) -> SDIO_SLC1_RXLINK_START_R { + SDIO_SLC1_RXLINK_START_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Configures whether to restart and continue SLC1 RX linked list operation."] + #[inline(always)] + pub fn sdio_slc1_rxlink_restart(&self) -> SDIO_SLC1_RXLINK_RESTART_R { + SDIO_SLC1_RXLINK_RESTART_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Represents SLC1 RX linked list FSM state."] + #[inline(always)] + pub fn sdio_slc1_rxlink_park(&self) -> SDIO_SLC1_RXLINK_PARK_R { + SDIO_SLC1_RXLINK_PARK_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SLC1RX_LINK") + .field("sdio_slc1_rxlink_stop", &self.sdio_slc1_rxlink_stop()) + .field("sdio_slc1_rxlink_start", &self.sdio_slc1_rxlink_start()) + .field("sdio_slc1_rxlink_restart", &self.sdio_slc1_rxlink_restart()) + .field("sdio_slc1_rxlink_park", &self.sdio_slc1_rxlink_park()) + .finish() + } +} +impl W { + #[doc = "Bit 28 - Configures whether to stop SLC1 RX linked list operation."] + #[inline(always)] + pub fn sdio_slc1_rxlink_stop(&mut self) -> SDIO_SLC1_RXLINK_STOP_W { + SDIO_SLC1_RXLINK_STOP_W::new(self, 28) + } + #[doc = "Bit 29 - Configures whether to start SLC1 RX linked list operation from the address indicated by SDIO_SLC1_RXLINK_ADDR."] + #[inline(always)] + pub fn sdio_slc1_rxlink_start(&mut self) -> SDIO_SLC1_RXLINK_START_W { + SDIO_SLC1_RXLINK_START_W::new(self, 29) + } + #[doc = "Bit 30 - Configures whether to restart and continue SLC1 RX linked list operation."] + #[inline(always)] + pub fn sdio_slc1_rxlink_restart(&mut self) -> SDIO_SLC1_RXLINK_RESTART_W { + SDIO_SLC1_RXLINK_RESTART_W::new(self, 30) + } + #[doc = "Bit 31 - Represents SLC1 RX linked list FSM state."] + #[inline(always)] + pub fn sdio_slc1_rxlink_park(&mut self) -> SDIO_SLC1_RXLINK_PARK_W { + SDIO_SLC1_RXLINK_PARK_W::new(self, 31) + } +} +#[doc = "SLC1 RX linked list configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`slc1rx_link::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc1rx_link::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SLC1RX_LINK_SPEC; +impl crate::RegisterSpec for SLC1RX_LINK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`slc1rx_link::R`](R) reader structure"] +impl crate::Readable for SLC1RX_LINK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`slc1rx_link::W`](W) writer structure"] +impl crate::Writable for SLC1RX_LINK_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SLC1RX_LINK to value 0x8000_0000"] +impl crate::Resettable for SLC1RX_LINK_SPEC { + const RESET_VALUE: u32 = 0x8000_0000; +} diff --git a/esp32c6/src/slc/slc1rx_link_addr.rs b/esp32c6/src/slc/slc1rx_link_addr.rs new file mode 100644 index 000000000..4f52aa0e1 --- /dev/null +++ b/esp32c6/src/slc/slc1rx_link_addr.rs @@ -0,0 +1,47 @@ +#[doc = "Register `SLC1RX_LINK_ADDR` reader"] +pub type R = crate::R; +#[doc = "Register `SLC1RX_LINK_ADDR` writer"] +pub type W = crate::W; +#[doc = "Field `SDIO_SLC1_RXLINK_ADDR` reader - Configures SLC1 RX linked list initial address."] +pub type SDIO_SLC1_RXLINK_ADDR_R = crate::FieldReader; +#[doc = "Field `SDIO_SLC1_RXLINK_ADDR` writer - Configures SLC1 RX linked list initial address."] +pub type SDIO_SLC1_RXLINK_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Configures SLC1 RX linked list initial address."] + #[inline(always)] + pub fn sdio_slc1_rxlink_addr(&self) -> SDIO_SLC1_RXLINK_ADDR_R { + SDIO_SLC1_RXLINK_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SLC1RX_LINK_ADDR") + .field("sdio_slc1_rxlink_addr", &self.sdio_slc1_rxlink_addr()) + .finish() + } +} +impl W { + #[doc = "Bits 0:31 - Configures SLC1 RX linked list initial address."] + #[inline(always)] + pub fn sdio_slc1_rxlink_addr(&mut self) -> SDIO_SLC1_RXLINK_ADDR_W { + SDIO_SLC1_RXLINK_ADDR_W::new(self, 0) + } +} +#[doc = "SLC1 RX linked list address\n\nYou can [`read`](crate::Reg::read) this register and get [`slc1rx_link_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc1rx_link_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SLC1RX_LINK_ADDR_SPEC; +impl crate::RegisterSpec for SLC1RX_LINK_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`slc1rx_link_addr::R`](R) reader structure"] +impl crate::Readable for SLC1RX_LINK_ADDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`slc1rx_link_addr::W`](W) writer structure"] +impl crate::Writable for SLC1RX_LINK_ADDR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SLC1RX_LINK_ADDR to value 0"] +impl crate::Resettable for SLC1RX_LINK_ADDR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32c6/src/slc/slc1token1.rs b/esp32c6/src/slc/slc1token1.rs new file mode 100644 index 000000000..370a2e6de --- /dev/null +++ b/esp32c6/src/slc/slc1token1.rs @@ -0,0 +1,68 @@ +#[doc = "Register `SLC1TOKEN1` reader"] +pub type R = crate::R; +#[doc = "Register `SLC1TOKEN1` writer"] +pub type W = crate::W; +#[doc = "Field `SDIO_SLC1_TOKEN1_WDATA` writer - Configures SLC1 token1 value."] +pub type SDIO_SLC1_TOKEN1_WDATA_W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `SDIO_SLC0_TOKEN1_WR` writer - Configures this bit to 1 to write SDIO_SLC1_TOKEN1_WDATA into SDIO_SLC1_TOKEN1."] +pub type SDIO_SLC0_TOKEN1_WR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC0_TOKEN1_INC` writer - Configures this bit to 1 to add 1 to SDIO_SLC1_TOKEN1."] +pub type SDIO_SLC0_TOKEN1_INC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC0_TOKEN1_INC_MORE` writer - Configures this bit to 1 to add the value of SDIO_SLC1_TOKEN1_WDATA to SDIO_SLC1_TOKEN1."] +pub type SDIO_SLC0_TOKEN1_INC_MORE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC0_TOKEN1` reader - Represents the SLC1 accumulated number of buffers for receiving packets."] +pub type SDIO_SLC0_TOKEN1_R = crate::FieldReader; +impl R { + #[doc = "Bits 16:27 - Represents the SLC1 accumulated number of buffers for receiving packets."] + #[inline(always)] + pub fn sdio_slc0_token1(&self) -> SDIO_SLC0_TOKEN1_R { + SDIO_SLC0_TOKEN1_R::new(((self.bits >> 16) & 0x0fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SLC1TOKEN1") + .field("sdio_slc0_token1", &self.sdio_slc0_token1()) + .finish() + } +} +impl W { + #[doc = "Bits 0:10 - Configures SLC1 token1 value."] + #[inline(always)] + pub fn sdio_slc1_token1_wdata(&mut self) -> SDIO_SLC1_TOKEN1_WDATA_W { + SDIO_SLC1_TOKEN1_WDATA_W::new(self, 0) + } + #[doc = "Bit 12 - Configures this bit to 1 to write SDIO_SLC1_TOKEN1_WDATA into SDIO_SLC1_TOKEN1."] + #[inline(always)] + pub fn sdio_slc0_token1_wr(&mut self) -> SDIO_SLC0_TOKEN1_WR_W { + SDIO_SLC0_TOKEN1_WR_W::new(self, 12) + } + #[doc = "Bit 13 - Configures this bit to 1 to add 1 to SDIO_SLC1_TOKEN1."] + #[inline(always)] + pub fn sdio_slc0_token1_inc(&mut self) -> SDIO_SLC0_TOKEN1_INC_W { + SDIO_SLC0_TOKEN1_INC_W::new(self, 13) + } + #[doc = "Bit 14 - Configures this bit to 1 to add the value of SDIO_SLC1_TOKEN1_WDATA to SDIO_SLC1_TOKEN1."] + #[inline(always)] + pub fn sdio_slc0_token1_inc_more(&mut self) -> SDIO_SLC0_TOKEN1_INC_MORE_W { + SDIO_SLC0_TOKEN1_INC_MORE_W::new(self, 14) + } +} +#[doc = "SLC1 receiving buffer configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`slc1token1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc1token1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SLC1TOKEN1_SPEC; +impl crate::RegisterSpec for SLC1TOKEN1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`slc1token1::R`](R) reader structure"] +impl crate::Readable for SLC1TOKEN1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`slc1token1::W`](W) writer structure"] +impl crate::Writable for SLC1TOKEN1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SLC1TOKEN1 to value 0"] +impl crate::Resettable for SLC1TOKEN1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32c6/src/slc/slc1tx_link.rs b/esp32c6/src/slc/slc1tx_link.rs new file mode 100644 index 000000000..d06b37b67 --- /dev/null +++ b/esp32c6/src/slc/slc1tx_link.rs @@ -0,0 +1,92 @@ +#[doc = "Register `SLC1TX_LINK` reader"] +pub type R = crate::R; +#[doc = "Register `SLC1TX_LINK` writer"] +pub type W = crate::W; +#[doc = "Field `SDIO_SLC1_TXLINK_STOP` reader - Configures whether to stop SLC1 TX linked list operation."] +pub type SDIO_SLC1_TXLINK_STOP_R = crate::BitReader; +#[doc = "Field `SDIO_SLC1_TXLINK_STOP` writer - Configures whether to stop SLC1 TX linked list operation."] +pub type SDIO_SLC1_TXLINK_STOP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC1_TXLINK_START` reader - Configures whether to start SLC1 TX linked list operation from the address indicated by SDIO_SLC1_TXLINK_ADDR."] +pub type SDIO_SLC1_TXLINK_START_R = crate::BitReader; +#[doc = "Field `SDIO_SLC1_TXLINK_START` writer - Configures whether to start SLC1 TX linked list operation from the address indicated by SDIO_SLC1_TXLINK_ADDR."] +pub type SDIO_SLC1_TXLINK_START_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC1_TXLINK_RESTART` reader - Configures whether to restart and continue SLC1 TX linked list operation."] +pub type SDIO_SLC1_TXLINK_RESTART_R = crate::BitReader; +#[doc = "Field `SDIO_SLC1_TXLINK_RESTART` writer - Configures whether to restart and continue SLC1 TX linked list operation."] +pub type SDIO_SLC1_TXLINK_RESTART_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC1_TXLINK_PARK` reader - Represents SLC1 TX linked list FSM state."] +pub type SDIO_SLC1_TXLINK_PARK_R = crate::BitReader; +#[doc = "Field `SDIO_SLC1_TXLINK_PARK` writer - Represents SLC1 TX linked list FSM state."] +pub type SDIO_SLC1_TXLINK_PARK_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 28 - Configures whether to stop SLC1 TX linked list operation."] + #[inline(always)] + pub fn sdio_slc1_txlink_stop(&self) -> SDIO_SLC1_TXLINK_STOP_R { + SDIO_SLC1_TXLINK_STOP_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Configures whether to start SLC1 TX linked list operation from the address indicated by SDIO_SLC1_TXLINK_ADDR."] + #[inline(always)] + pub fn sdio_slc1_txlink_start(&self) -> SDIO_SLC1_TXLINK_START_R { + SDIO_SLC1_TXLINK_START_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Configures whether to restart and continue SLC1 TX linked list operation."] + #[inline(always)] + pub fn sdio_slc1_txlink_restart(&self) -> SDIO_SLC1_TXLINK_RESTART_R { + SDIO_SLC1_TXLINK_RESTART_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Represents SLC1 TX linked list FSM state."] + #[inline(always)] + pub fn sdio_slc1_txlink_park(&self) -> SDIO_SLC1_TXLINK_PARK_R { + SDIO_SLC1_TXLINK_PARK_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SLC1TX_LINK") + .field("sdio_slc1_txlink_stop", &self.sdio_slc1_txlink_stop()) + .field("sdio_slc1_txlink_start", &self.sdio_slc1_txlink_start()) + .field("sdio_slc1_txlink_restart", &self.sdio_slc1_txlink_restart()) + .field("sdio_slc1_txlink_park", &self.sdio_slc1_txlink_park()) + .finish() + } +} +impl W { + #[doc = "Bit 28 - Configures whether to stop SLC1 TX linked list operation."] + #[inline(always)] + pub fn sdio_slc1_txlink_stop(&mut self) -> SDIO_SLC1_TXLINK_STOP_W { + SDIO_SLC1_TXLINK_STOP_W::new(self, 28) + } + #[doc = "Bit 29 - Configures whether to start SLC1 TX linked list operation from the address indicated by SDIO_SLC1_TXLINK_ADDR."] + #[inline(always)] + pub fn sdio_slc1_txlink_start(&mut self) -> SDIO_SLC1_TXLINK_START_W { + SDIO_SLC1_TXLINK_START_W::new(self, 29) + } + #[doc = "Bit 30 - Configures whether to restart and continue SLC1 TX linked list operation."] + #[inline(always)] + pub fn sdio_slc1_txlink_restart(&mut self) -> SDIO_SLC1_TXLINK_RESTART_W { + SDIO_SLC1_TXLINK_RESTART_W::new(self, 30) + } + #[doc = "Bit 31 - Represents SLC1 TX linked list FSM state."] + #[inline(always)] + pub fn sdio_slc1_txlink_park(&mut self) -> SDIO_SLC1_TXLINK_PARK_W { + SDIO_SLC1_TXLINK_PARK_W::new(self, 31) + } +} +#[doc = "SLC1 TX linked list configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`slc1tx_link::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc1tx_link::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SLC1TX_LINK_SPEC; +impl crate::RegisterSpec for SLC1TX_LINK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`slc1tx_link::R`](R) reader structure"] +impl crate::Readable for SLC1TX_LINK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`slc1tx_link::W`](W) writer structure"] +impl crate::Writable for SLC1TX_LINK_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SLC1TX_LINK to value 0x8000_0000"] +impl crate::Resettable for SLC1TX_LINK_SPEC { + const RESET_VALUE: u32 = 0x8000_0000; +} diff --git a/esp32c6/src/slc/slc1tx_link_addr.rs b/esp32c6/src/slc/slc1tx_link_addr.rs new file mode 100644 index 000000000..05f2d797f --- /dev/null +++ b/esp32c6/src/slc/slc1tx_link_addr.rs @@ -0,0 +1,47 @@ +#[doc = "Register `SLC1TX_LINK_ADDR` reader"] +pub type R = crate::R; +#[doc = "Register `SLC1TX_LINK_ADDR` writer"] +pub type W = crate::W; +#[doc = "Field `SDIO_SLC1_TXLINK_ADDR` reader - Configures SLC1 TX linked list initial address."] +pub type SDIO_SLC1_TXLINK_ADDR_R = crate::FieldReader; +#[doc = "Field `SDIO_SLC1_TXLINK_ADDR` writer - Configures SLC1 TX linked list initial address."] +pub type SDIO_SLC1_TXLINK_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Configures SLC1 TX linked list initial address."] + #[inline(always)] + pub fn sdio_slc1_txlink_addr(&self) -> SDIO_SLC1_TXLINK_ADDR_R { + SDIO_SLC1_TXLINK_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SLC1TX_LINK_ADDR") + .field("sdio_slc1_txlink_addr", &self.sdio_slc1_txlink_addr()) + .finish() + } +} +impl W { + #[doc = "Bits 0:31 - Configures SLC1 TX linked list initial address."] + #[inline(always)] + pub fn sdio_slc1_txlink_addr(&mut self) -> SDIO_SLC1_TXLINK_ADDR_W { + SDIO_SLC1_TXLINK_ADDR_W::new(self, 0) + } +} +#[doc = "SLC1 TX linked list address\n\nYou can [`read`](crate::Reg::read) this register and get [`slc1tx_link_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc1tx_link_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SLC1TX_LINK_ADDR_SPEC; +impl crate::RegisterSpec for SLC1TX_LINK_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`slc1tx_link_addr::R`](R) reader structure"] +impl crate::Readable for SLC1TX_LINK_ADDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`slc1tx_link_addr::W`](W) writer structure"] +impl crate::Writable for SLC1TX_LINK_ADDR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SLC1TX_LINK_ADDR to value 0"] +impl crate::Resettable for SLC1TX_LINK_ADDR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32c6/src/slc/slc_burst_len.rs b/esp32c6/src/slc/slc_burst_len.rs new file mode 100644 index 000000000..e8d8ef015 --- /dev/null +++ b/esp32c6/src/slc/slc_burst_len.rs @@ -0,0 +1,112 @@ +#[doc = "Register `SLC_BURST_LEN` reader"] +pub type R = crate::R; +#[doc = "Register `SLC_BURST_LEN` writer"] +pub type W = crate::W; +#[doc = "Field `SDIO_SLC0_TXDATA_BURST_LEN` reader - Configures SLC0 host to slave channel AHB burst type."] +pub type SDIO_SLC0_TXDATA_BURST_LEN_R = crate::BitReader; +#[doc = "Field `SDIO_SLC0_TXDATA_BURST_LEN` writer - Configures SLC0 host to slave channel AHB burst type."] +pub type SDIO_SLC0_TXDATA_BURST_LEN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC0_RXDATA_BURST_LEN` reader - Configures SLC0 slave to host channel AHB burst type."] +pub type SDIO_SLC0_RXDATA_BURST_LEN_R = crate::BitReader; +#[doc = "Field `SDIO_SLC0_RXDATA_BURST_LEN` writer - Configures SLC0 slave to host channel AHB burst type."] +pub type SDIO_SLC0_RXDATA_BURST_LEN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC1_TXDATA_BURST_LEN` reader - Configures SLC1 host to slave channel AHB burst type."] +pub type SDIO_SLC1_TXDATA_BURST_LEN_R = crate::BitReader; +#[doc = "Field `SDIO_SLC1_TXDATA_BURST_LEN` writer - Configures SLC1 host to slave channel AHB burst type."] +pub type SDIO_SLC1_TXDATA_BURST_LEN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC1_RXDATA_BURST_LEN` reader - Configures SLC1 slave to host channel AHB burst type."] +pub type SDIO_SLC1_RXDATA_BURST_LEN_R = crate::BitReader; +#[doc = "Field `SDIO_SLC1_RXDATA_BURST_LEN` writer - Configures SLC1 slave to host channel AHB burst type."] +pub type SDIO_SLC1_RXDATA_BURST_LEN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Configures SLC0 host to slave channel AHB burst type."] + #[inline(always)] + pub fn sdio_slc0_txdata_burst_len(&self) -> SDIO_SLC0_TXDATA_BURST_LEN_R { + SDIO_SLC0_TXDATA_BURST_LEN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Configures SLC0 slave to host channel AHB burst type."] + #[inline(always)] + pub fn sdio_slc0_rxdata_burst_len(&self) -> SDIO_SLC0_RXDATA_BURST_LEN_R { + SDIO_SLC0_RXDATA_BURST_LEN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Configures SLC1 host to slave channel AHB burst type."] + #[inline(always)] + pub fn sdio_slc1_txdata_burst_len(&self) -> SDIO_SLC1_TXDATA_BURST_LEN_R { + SDIO_SLC1_TXDATA_BURST_LEN_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Configures SLC1 slave to host channel AHB burst type."] + #[inline(always)] + pub fn sdio_slc1_rxdata_burst_len(&self) -> SDIO_SLC1_RXDATA_BURST_LEN_R { + SDIO_SLC1_RXDATA_BURST_LEN_R::new(((self.bits >> 3) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SLC_BURST_LEN") + .field( + "sdio_slc0_txdata_burst_len", + &self.sdio_slc0_txdata_burst_len(), + ) + .field( + "sdio_slc0_rxdata_burst_len", + &self.sdio_slc0_rxdata_burst_len(), + ) + .field( + "sdio_slc1_txdata_burst_len", + &self.sdio_slc1_txdata_burst_len(), + ) + .field( + "sdio_slc1_rxdata_burst_len", + &self.sdio_slc1_rxdata_burst_len(), + ) + .finish() + } +} +impl W { + #[doc = "Bit 0 - Configures SLC0 host to slave channel AHB burst type."] + #[inline(always)] + pub fn sdio_slc0_txdata_burst_len( + &mut self, + ) -> SDIO_SLC0_TXDATA_BURST_LEN_W { + SDIO_SLC0_TXDATA_BURST_LEN_W::new(self, 0) + } + #[doc = "Bit 1 - Configures SLC0 slave to host channel AHB burst type."] + #[inline(always)] + pub fn sdio_slc0_rxdata_burst_len( + &mut self, + ) -> SDIO_SLC0_RXDATA_BURST_LEN_W { + SDIO_SLC0_RXDATA_BURST_LEN_W::new(self, 1) + } + #[doc = "Bit 2 - Configures SLC1 host to slave channel AHB burst type."] + #[inline(always)] + pub fn sdio_slc1_txdata_burst_len( + &mut self, + ) -> SDIO_SLC1_TXDATA_BURST_LEN_W { + SDIO_SLC1_TXDATA_BURST_LEN_W::new(self, 2) + } + #[doc = "Bit 3 - Configures SLC1 slave to host channel AHB burst type."] + #[inline(always)] + pub fn sdio_slc1_rxdata_burst_len( + &mut self, + ) -> SDIO_SLC1_RXDATA_BURST_LEN_W { + SDIO_SLC1_RXDATA_BURST_LEN_W::new(self, 3) + } +} +#[doc = "DMA AHB burst type configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`slc_burst_len::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc_burst_len::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SLC_BURST_LEN_SPEC; +impl crate::RegisterSpec for SLC_BURST_LEN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`slc_burst_len::R`](R) reader structure"] +impl crate::Readable for SLC_BURST_LEN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`slc_burst_len::W`](W) writer structure"] +impl crate::Writable for SLC_BURST_LEN_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SLC_BURST_LEN to value 0x0f"] +impl crate::Resettable for SLC_BURST_LEN_SPEC { + const RESET_VALUE: u32 = 0x0f; +} diff --git a/esp32c6/src/slc/slc_rx_dscr_conf.rs b/esp32c6/src/slc/slc_rx_dscr_conf.rs new file mode 100644 index 000000000..4add2e44b --- /dev/null +++ b/esp32c6/src/slc/slc_rx_dscr_conf.rs @@ -0,0 +1,52 @@ +#[doc = "Register `SLC_RX_DSCR_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `SLC_RX_DSCR_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `SDIO_SLC0_TOKEN_NO_REPLACE` reader - Please initialize to 1, and do not modify it."] +pub type SDIO_SLC0_TOKEN_NO_REPLACE_R = crate::BitReader; +#[doc = "Field `SDIO_SLC0_TOKEN_NO_REPLACE` writer - Please initialize to 1, and do not modify it."] +pub type SDIO_SLC0_TOKEN_NO_REPLACE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 1 - Please initialize to 1, and do not modify it."] + #[inline(always)] + pub fn sdio_slc0_token_no_replace(&self) -> SDIO_SLC0_TOKEN_NO_REPLACE_R { + SDIO_SLC0_TOKEN_NO_REPLACE_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SLC_RX_DSCR_CONF") + .field( + "sdio_slc0_token_no_replace", + &self.sdio_slc0_token_no_replace(), + ) + .finish() + } +} +impl W { + #[doc = "Bit 1 - Please initialize to 1, and do not modify it."] + #[inline(always)] + pub fn sdio_slc0_token_no_replace( + &mut self, + ) -> SDIO_SLC0_TOKEN_NO_REPLACE_W { + SDIO_SLC0_TOKEN_NO_REPLACE_W::new(self, 1) + } +} +#[doc = "DMA slave to host configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`slc_rx_dscr_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc_rx_dscr_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SLC_RX_DSCR_CONF_SPEC; +impl crate::RegisterSpec for SLC_RX_DSCR_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`slc_rx_dscr_conf::R`](R) reader structure"] +impl crate::Readable for SLC_RX_DSCR_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`slc_rx_dscr_conf::W`](W) writer structure"] +impl crate::Writable for SLC_RX_DSCR_CONF_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SLC_RX_DSCR_CONF to value 0x0203_701a"] +impl crate::Resettable for SLC_RX_DSCR_CONF_SPEC { + const RESET_VALUE: u32 = 0x0203_701a; +} diff --git a/esp32c6/src/slc/slcconf0.rs b/esp32c6/src/slc/slcconf0.rs new file mode 100644 index 000000000..5da684e3e --- /dev/null +++ b/esp32c6/src/slc/slcconf0.rs @@ -0,0 +1,392 @@ +#[doc = "Register `SLCCONF0` reader"] +pub type R = crate::R; +#[doc = "Register `SLCCONF0` writer"] +pub type W = crate::W; +#[doc = "Field `SDIO_SLC0_TX_RST` reader - Configures whether to reset TX (host to slave) FSM (finite state machine) in SLC0."] +pub type SDIO_SLC0_TX_RST_R = crate::BitReader; +#[doc = "Field `SDIO_SLC0_TX_RST` writer - Configures whether to reset TX (host to slave) FSM (finite state machine) in SLC0."] +pub type SDIO_SLC0_TX_RST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC0_RX_RST` reader - Configures whether to reset RX (slave to host) FSM in SCL0."] +pub type SDIO_SLC0_RX_RST_R = crate::BitReader; +#[doc = "Field `SDIO_SLC0_RX_RST` writer - Configures whether to reset RX (slave to host) FSM in SCL0."] +pub type SDIO_SLC0_RX_RST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC0_TX_LOOP_TEST` reader - Configures whether SCL0 loops around when the slave buffer finishes receiving packets from the host."] +pub type SDIO_SLC0_TX_LOOP_TEST_R = crate::BitReader; +#[doc = "Field `SDIO_SLC0_TX_LOOP_TEST` writer - Configures whether SCL0 loops around when the slave buffer finishes receiving packets from the host."] +pub type SDIO_SLC0_TX_LOOP_TEST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC0_RX_LOOP_TEST` reader - Configures whether SCL0 loops around when the slave buffer finishes sending packets to the host."] +pub type SDIO_SLC0_RX_LOOP_TEST_R = crate::BitReader; +#[doc = "Field `SDIO_SLC0_RX_LOOP_TEST` writer - Configures whether SCL0 loops around when the slave buffer finishes sending packets to the host."] +pub type SDIO_SLC0_RX_LOOP_TEST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC0_RX_AUTO_WRBACK` reader - Configures whether SCL0 changes the owner bit of RX linked list."] +pub type SDIO_SLC0_RX_AUTO_WRBACK_R = crate::BitReader; +#[doc = "Field `SDIO_SLC0_RX_AUTO_WRBACK` writer - Configures whether SCL0 changes the owner bit of RX linked list."] +pub type SDIO_SLC0_RX_AUTO_WRBACK_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC0_RX_NO_RESTART_CLR` reader - Please initialize to 1, and do not modify it."] +pub type SDIO_SLC0_RX_NO_RESTART_CLR_R = crate::BitReader; +#[doc = "Field `SDIO_SLC0_RX_NO_RESTART_CLR` writer - Please initialize to 1, and do not modify it."] +pub type SDIO_SLC0_RX_NO_RESTART_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC0_RXDSCR_BURST_EN` reader - Configures whether SCL0 can use AHB burst operation when reading the RX linked list from memory."] +pub type SDIO_SLC0_RXDSCR_BURST_EN_R = crate::BitReader; +#[doc = "Field `SDIO_SLC0_RXDSCR_BURST_EN` writer - Configures whether SCL0 can use AHB burst operation when reading the RX linked list from memory."] +pub type SDIO_SLC0_RXDSCR_BURST_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC0_RXDATA_BURST_EN` reader - Configures whether SCL0 can use AHB burst operation when read data from memory."] +pub type SDIO_SLC0_RXDATA_BURST_EN_R = crate::BitReader; +#[doc = "Field `SDIO_SLC0_RXDATA_BURST_EN` writer - Configures whether SCL0 can use AHB burst operation when read data from memory."] +pub type SDIO_SLC0_RXDATA_BURST_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC0_TXDSCR_BURST_EN` reader - Configures whether SCL0 can use AHB burst operation when read the TX linked list from memory."] +pub type SDIO_SLC0_TXDSCR_BURST_EN_R = crate::BitReader; +#[doc = "Field `SDIO_SLC0_TXDSCR_BURST_EN` writer - Configures whether SCL0 can use AHB burst operation when read the TX linked list from memory."] +pub type SDIO_SLC0_TXDSCR_BURST_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC0_TXDATA_BURST_EN` reader - Configures whether SCL0 can use AHB burst operation when send data to memory."] +pub type SDIO_SLC0_TXDATA_BURST_EN_R = crate::BitReader; +#[doc = "Field `SDIO_SLC0_TXDATA_BURST_EN` writer - Configures whether SCL0 can use AHB burst operation when send data to memory."] +pub type SDIO_SLC0_TXDATA_BURST_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC0_TOKEN_AUTO_CLR` reader - Please initialize to 0, and do not modify it."] +pub type SDIO_SLC0_TOKEN_AUTO_CLR_R = crate::BitReader; +#[doc = "Field `SDIO_SLC0_TOKEN_AUTO_CLR` writer - Please initialize to 0, and do not modify it."] +pub type SDIO_SLC0_TOKEN_AUTO_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC1_TX_RST` reader - Configures whether to reset TX FSM in SLC1."] +pub type SDIO_SLC1_TX_RST_R = crate::BitReader; +#[doc = "Field `SDIO_SLC1_TX_RST` writer - Configures whether to reset TX FSM in SLC1."] +pub type SDIO_SLC1_TX_RST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC1_RX_RST` reader - Configures whether to reset RX FSM in SLC1."] +pub type SDIO_SLC1_RX_RST_R = crate::BitReader; +#[doc = "Field `SDIO_SLC1_RX_RST` writer - Configures whether to reset RX FSM in SLC1."] +pub type SDIO_SLC1_RX_RST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC1_TX_LOOP_TEST` reader - Configures whether SCL1 loops around when the slave buffer finishes receiving packets from the host."] +pub type SDIO_SLC1_TX_LOOP_TEST_R = crate::BitReader; +#[doc = "Field `SDIO_SLC1_TX_LOOP_TEST` writer - Configures whether SCL1 loops around when the slave buffer finishes receiving packets from the host."] +pub type SDIO_SLC1_TX_LOOP_TEST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC1_RX_LOOP_TEST` reader - Configures whether SCL1 loops around when the slave buffer finishes sending packets to the host."] +pub type SDIO_SLC1_RX_LOOP_TEST_R = crate::BitReader; +#[doc = "Field `SDIO_SLC1_RX_LOOP_TEST` writer - Configures whether SCL1 loops around when the slave buffer finishes sending packets to the host."] +pub type SDIO_SLC1_RX_LOOP_TEST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC1_RX_AUTO_WRBACK` reader - Configures whether SCL1 changes the owner bit of the RX linked list."] +pub type SDIO_SLC1_RX_AUTO_WRBACK_R = crate::BitReader; +#[doc = "Field `SDIO_SLC1_RX_AUTO_WRBACK` writer - Configures whether SCL1 changes the owner bit of the RX linked list."] +pub type SDIO_SLC1_RX_AUTO_WRBACK_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC1_RX_NO_RESTART_CLR` reader - Please initialize to 1, and do not modify it."] +pub type SDIO_SLC1_RX_NO_RESTART_CLR_R = crate::BitReader; +#[doc = "Field `SDIO_SLC1_RX_NO_RESTART_CLR` writer - Please initialize to 1, and do not modify it."] +pub type SDIO_SLC1_RX_NO_RESTART_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC1_RXDSCR_BURST_EN` reader - Configures whether SCL1 can use AHB burst operation when read the RX linked list from memory."] +pub type SDIO_SLC1_RXDSCR_BURST_EN_R = crate::BitReader; +#[doc = "Field `SDIO_SLC1_RXDSCR_BURST_EN` writer - Configures whether SCL1 can use AHB burst operation when read the RX linked list from memory."] +pub type SDIO_SLC1_RXDSCR_BURST_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC1_RXDATA_BURST_EN` reader - Configures whether SCL1 can use AHB burst operation when reading data from memory."] +pub type SDIO_SLC1_RXDATA_BURST_EN_R = crate::BitReader; +#[doc = "Field `SDIO_SLC1_RXDATA_BURST_EN` writer - Configures whether SCL1 can use AHB burst operation when reading data from memory."] +pub type SDIO_SLC1_RXDATA_BURST_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC1_TXDSCR_BURST_EN` reader - Configures whether SCL1 can use AHB burst operation when read the TX linked list from memory."] +pub type SDIO_SLC1_TXDSCR_BURST_EN_R = crate::BitReader; +#[doc = "Field `SDIO_SLC1_TXDSCR_BURST_EN` writer - Configures whether SCL1 can use AHB burst operation when read the TX linked list from memory."] +pub type SDIO_SLC1_TXDSCR_BURST_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC1_TXDATA_BURST_EN` reader - Configures whether SCL1 can use AHB burst operation when send data to memory."] +pub type SDIO_SLC1_TXDATA_BURST_EN_R = crate::BitReader; +#[doc = "Field `SDIO_SLC1_TXDATA_BURST_EN` writer - Configures whether SCL1 can use AHB burst operation when send data to memory."] +pub type SDIO_SLC1_TXDATA_BURST_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC1_TOKEN_AUTO_CLR` reader - Please initialize to 0, and do not modify it."] +pub type SDIO_SLC1_TOKEN_AUTO_CLR_R = crate::BitReader; +#[doc = "Field `SDIO_SLC1_TOKEN_AUTO_CLR` writer - Please initialize to 0, and do not modify it."] +pub type SDIO_SLC1_TOKEN_AUTO_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Configures whether to reset TX (host to slave) FSM (finite state machine) in SLC0."] + #[inline(always)] + pub fn sdio_slc0_tx_rst(&self) -> SDIO_SLC0_TX_RST_R { + SDIO_SLC0_TX_RST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Configures whether to reset RX (slave to host) FSM in SCL0."] + #[inline(always)] + pub fn sdio_slc0_rx_rst(&self) -> SDIO_SLC0_RX_RST_R { + SDIO_SLC0_RX_RST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 4 - Configures whether SCL0 loops around when the slave buffer finishes receiving packets from the host."] + #[inline(always)] + pub fn sdio_slc0_tx_loop_test(&self) -> SDIO_SLC0_TX_LOOP_TEST_R { + SDIO_SLC0_TX_LOOP_TEST_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Configures whether SCL0 loops around when the slave buffer finishes sending packets to the host."] + #[inline(always)] + pub fn sdio_slc0_rx_loop_test(&self) -> SDIO_SLC0_RX_LOOP_TEST_R { + SDIO_SLC0_RX_LOOP_TEST_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Configures whether SCL0 changes the owner bit of RX linked list."] + #[inline(always)] + pub fn sdio_slc0_rx_auto_wrback(&self) -> SDIO_SLC0_RX_AUTO_WRBACK_R { + SDIO_SLC0_RX_AUTO_WRBACK_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Please initialize to 1, and do not modify it."] + #[inline(always)] + pub fn sdio_slc0_rx_no_restart_clr(&self) -> SDIO_SLC0_RX_NO_RESTART_CLR_R { + SDIO_SLC0_RX_NO_RESTART_CLR_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Configures whether SCL0 can use AHB burst operation when reading the RX linked list from memory."] + #[inline(always)] + pub fn sdio_slc0_rxdscr_burst_en(&self) -> SDIO_SLC0_RXDSCR_BURST_EN_R { + SDIO_SLC0_RXDSCR_BURST_EN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Configures whether SCL0 can use AHB burst operation when read data from memory."] + #[inline(always)] + pub fn sdio_slc0_rxdata_burst_en(&self) -> SDIO_SLC0_RXDATA_BURST_EN_R { + SDIO_SLC0_RXDATA_BURST_EN_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 12 - Configures whether SCL0 can use AHB burst operation when read the TX linked list from memory."] + #[inline(always)] + pub fn sdio_slc0_txdscr_burst_en(&self) -> SDIO_SLC0_TXDSCR_BURST_EN_R { + SDIO_SLC0_TXDSCR_BURST_EN_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Configures whether SCL0 can use AHB burst operation when send data to memory."] + #[inline(always)] + pub fn sdio_slc0_txdata_burst_en(&self) -> SDIO_SLC0_TXDATA_BURST_EN_R { + SDIO_SLC0_TXDATA_BURST_EN_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Please initialize to 0, and do not modify it."] + #[inline(always)] + pub fn sdio_slc0_token_auto_clr(&self) -> SDIO_SLC0_TOKEN_AUTO_CLR_R { + SDIO_SLC0_TOKEN_AUTO_CLR_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 16 - Configures whether to reset TX FSM in SLC1."] + #[inline(always)] + pub fn sdio_slc1_tx_rst(&self) -> SDIO_SLC1_TX_RST_R { + SDIO_SLC1_TX_RST_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Configures whether to reset RX FSM in SLC1."] + #[inline(always)] + pub fn sdio_slc1_rx_rst(&self) -> SDIO_SLC1_RX_RST_R { + SDIO_SLC1_RX_RST_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 20 - Configures whether SCL1 loops around when the slave buffer finishes receiving packets from the host."] + #[inline(always)] + pub fn sdio_slc1_tx_loop_test(&self) -> SDIO_SLC1_TX_LOOP_TEST_R { + SDIO_SLC1_TX_LOOP_TEST_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Configures whether SCL1 loops around when the slave buffer finishes sending packets to the host."] + #[inline(always)] + pub fn sdio_slc1_rx_loop_test(&self) -> SDIO_SLC1_RX_LOOP_TEST_R { + SDIO_SLC1_RX_LOOP_TEST_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Configures whether SCL1 changes the owner bit of the RX linked list."] + #[inline(always)] + pub fn sdio_slc1_rx_auto_wrback(&self) -> SDIO_SLC1_RX_AUTO_WRBACK_R { + SDIO_SLC1_RX_AUTO_WRBACK_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Please initialize to 1, and do not modify it."] + #[inline(always)] + pub fn sdio_slc1_rx_no_restart_clr(&self) -> SDIO_SLC1_RX_NO_RESTART_CLR_R { + SDIO_SLC1_RX_NO_RESTART_CLR_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Configures whether SCL1 can use AHB burst operation when read the RX linked list from memory."] + #[inline(always)] + pub fn sdio_slc1_rxdscr_burst_en(&self) -> SDIO_SLC1_RXDSCR_BURST_EN_R { + SDIO_SLC1_RXDSCR_BURST_EN_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Configures whether SCL1 can use AHB burst operation when reading data from memory."] + #[inline(always)] + pub fn sdio_slc1_rxdata_burst_en(&self) -> SDIO_SLC1_RXDATA_BURST_EN_R { + SDIO_SLC1_RXDATA_BURST_EN_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 28 - Configures whether SCL1 can use AHB burst operation when read the TX linked list from memory."] + #[inline(always)] + pub fn sdio_slc1_txdscr_burst_en(&self) -> SDIO_SLC1_TXDSCR_BURST_EN_R { + SDIO_SLC1_TXDSCR_BURST_EN_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Configures whether SCL1 can use AHB burst operation when send data to memory."] + #[inline(always)] + pub fn sdio_slc1_txdata_burst_en(&self) -> SDIO_SLC1_TXDATA_BURST_EN_R { + SDIO_SLC1_TXDATA_BURST_EN_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Please initialize to 0, and do not modify it."] + #[inline(always)] + pub fn sdio_slc1_token_auto_clr(&self) -> SDIO_SLC1_TOKEN_AUTO_CLR_R { + SDIO_SLC1_TOKEN_AUTO_CLR_R::new(((self.bits >> 30) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SLCCONF0") + .field("sdio_slc0_tx_rst", &self.sdio_slc0_tx_rst()) + .field("sdio_slc0_rx_rst", &self.sdio_slc0_rx_rst()) + .field("sdio_slc0_tx_loop_test", &self.sdio_slc0_tx_loop_test()) + .field("sdio_slc0_rx_loop_test", &self.sdio_slc0_rx_loop_test()) + .field("sdio_slc0_rx_auto_wrback", &self.sdio_slc0_rx_auto_wrback()) + .field( + "sdio_slc0_rx_no_restart_clr", + &self.sdio_slc0_rx_no_restart_clr(), + ) + .field( + "sdio_slc0_rxdscr_burst_en", + &self.sdio_slc0_rxdscr_burst_en(), + ) + .field( + "sdio_slc0_rxdata_burst_en", + &self.sdio_slc0_rxdata_burst_en(), + ) + .field( + "sdio_slc0_txdscr_burst_en", + &self.sdio_slc0_txdscr_burst_en(), + ) + .field( + "sdio_slc0_txdata_burst_en", + &self.sdio_slc0_txdata_burst_en(), + ) + .field("sdio_slc0_token_auto_clr", &self.sdio_slc0_token_auto_clr()) + .field("sdio_slc1_tx_rst", &self.sdio_slc1_tx_rst()) + .field("sdio_slc1_rx_rst", &self.sdio_slc1_rx_rst()) + .field("sdio_slc1_tx_loop_test", &self.sdio_slc1_tx_loop_test()) + .field("sdio_slc1_rx_loop_test", &self.sdio_slc1_rx_loop_test()) + .field("sdio_slc1_rx_auto_wrback", &self.sdio_slc1_rx_auto_wrback()) + .field( + "sdio_slc1_rx_no_restart_clr", + &self.sdio_slc1_rx_no_restart_clr(), + ) + .field( + "sdio_slc1_rxdscr_burst_en", + &self.sdio_slc1_rxdscr_burst_en(), + ) + .field( + "sdio_slc1_rxdata_burst_en", + &self.sdio_slc1_rxdata_burst_en(), + ) + .field( + "sdio_slc1_txdscr_burst_en", + &self.sdio_slc1_txdscr_burst_en(), + ) + .field( + "sdio_slc1_txdata_burst_en", + &self.sdio_slc1_txdata_burst_en(), + ) + .field("sdio_slc1_token_auto_clr", &self.sdio_slc1_token_auto_clr()) + .finish() + } +} +impl W { + #[doc = "Bit 0 - Configures whether to reset TX (host to slave) FSM (finite state machine) in SLC0."] + #[inline(always)] + pub fn sdio_slc0_tx_rst(&mut self) -> SDIO_SLC0_TX_RST_W { + SDIO_SLC0_TX_RST_W::new(self, 0) + } + #[doc = "Bit 1 - Configures whether to reset RX (slave to host) FSM in SCL0."] + #[inline(always)] + pub fn sdio_slc0_rx_rst(&mut self) -> SDIO_SLC0_RX_RST_W { + SDIO_SLC0_RX_RST_W::new(self, 1) + } + #[doc = "Bit 4 - Configures whether SCL0 loops around when the slave buffer finishes receiving packets from the host."] + #[inline(always)] + pub fn sdio_slc0_tx_loop_test(&mut self) -> SDIO_SLC0_TX_LOOP_TEST_W { + SDIO_SLC0_TX_LOOP_TEST_W::new(self, 4) + } + #[doc = "Bit 5 - Configures whether SCL0 loops around when the slave buffer finishes sending packets to the host."] + #[inline(always)] + pub fn sdio_slc0_rx_loop_test(&mut self) -> SDIO_SLC0_RX_LOOP_TEST_W { + SDIO_SLC0_RX_LOOP_TEST_W::new(self, 5) + } + #[doc = "Bit 6 - Configures whether SCL0 changes the owner bit of RX linked list."] + #[inline(always)] + pub fn sdio_slc0_rx_auto_wrback(&mut self) -> SDIO_SLC0_RX_AUTO_WRBACK_W { + SDIO_SLC0_RX_AUTO_WRBACK_W::new(self, 6) + } + #[doc = "Bit 7 - Please initialize to 1, and do not modify it."] + #[inline(always)] + pub fn sdio_slc0_rx_no_restart_clr(&mut self) -> SDIO_SLC0_RX_NO_RESTART_CLR_W { + SDIO_SLC0_RX_NO_RESTART_CLR_W::new(self, 7) + } + #[doc = "Bit 8 - Configures whether SCL0 can use AHB burst operation when reading the RX linked list from memory."] + #[inline(always)] + pub fn sdio_slc0_rxdscr_burst_en(&mut self) -> SDIO_SLC0_RXDSCR_BURST_EN_W { + SDIO_SLC0_RXDSCR_BURST_EN_W::new(self, 8) + } + #[doc = "Bit 9 - Configures whether SCL0 can use AHB burst operation when read data from memory."] + #[inline(always)] + pub fn sdio_slc0_rxdata_burst_en(&mut self) -> SDIO_SLC0_RXDATA_BURST_EN_W { + SDIO_SLC0_RXDATA_BURST_EN_W::new(self, 9) + } + #[doc = "Bit 12 - Configures whether SCL0 can use AHB burst operation when read the TX linked list from memory."] + #[inline(always)] + pub fn sdio_slc0_txdscr_burst_en(&mut self) -> SDIO_SLC0_TXDSCR_BURST_EN_W { + SDIO_SLC0_TXDSCR_BURST_EN_W::new(self, 12) + } + #[doc = "Bit 13 - Configures whether SCL0 can use AHB burst operation when send data to memory."] + #[inline(always)] + pub fn sdio_slc0_txdata_burst_en(&mut self) -> SDIO_SLC0_TXDATA_BURST_EN_W { + SDIO_SLC0_TXDATA_BURST_EN_W::new(self, 13) + } + #[doc = "Bit 14 - Please initialize to 0, and do not modify it."] + #[inline(always)] + pub fn sdio_slc0_token_auto_clr(&mut self) -> SDIO_SLC0_TOKEN_AUTO_CLR_W { + SDIO_SLC0_TOKEN_AUTO_CLR_W::new(self, 14) + } + #[doc = "Bit 16 - Configures whether to reset TX FSM in SLC1."] + #[inline(always)] + pub fn sdio_slc1_tx_rst(&mut self) -> SDIO_SLC1_TX_RST_W { + SDIO_SLC1_TX_RST_W::new(self, 16) + } + #[doc = "Bit 17 - Configures whether to reset RX FSM in SLC1."] + #[inline(always)] + pub fn sdio_slc1_rx_rst(&mut self) -> SDIO_SLC1_RX_RST_W { + SDIO_SLC1_RX_RST_W::new(self, 17) + } + #[doc = "Bit 20 - Configures whether SCL1 loops around when the slave buffer finishes receiving packets from the host."] + #[inline(always)] + pub fn sdio_slc1_tx_loop_test(&mut self) -> SDIO_SLC1_TX_LOOP_TEST_W { + SDIO_SLC1_TX_LOOP_TEST_W::new(self, 20) + } + #[doc = "Bit 21 - Configures whether SCL1 loops around when the slave buffer finishes sending packets to the host."] + #[inline(always)] + pub fn sdio_slc1_rx_loop_test(&mut self) -> SDIO_SLC1_RX_LOOP_TEST_W { + SDIO_SLC1_RX_LOOP_TEST_W::new(self, 21) + } + #[doc = "Bit 22 - Configures whether SCL1 changes the owner bit of the RX linked list."] + #[inline(always)] + pub fn sdio_slc1_rx_auto_wrback(&mut self) -> SDIO_SLC1_RX_AUTO_WRBACK_W { + SDIO_SLC1_RX_AUTO_WRBACK_W::new(self, 22) + } + #[doc = "Bit 23 - Please initialize to 1, and do not modify it."] + #[inline(always)] + pub fn sdio_slc1_rx_no_restart_clr(&mut self) -> SDIO_SLC1_RX_NO_RESTART_CLR_W { + SDIO_SLC1_RX_NO_RESTART_CLR_W::new(self, 23) + } + #[doc = "Bit 24 - Configures whether SCL1 can use AHB burst operation when read the RX linked list from memory."] + #[inline(always)] + pub fn sdio_slc1_rxdscr_burst_en(&mut self) -> SDIO_SLC1_RXDSCR_BURST_EN_W { + SDIO_SLC1_RXDSCR_BURST_EN_W::new(self, 24) + } + #[doc = "Bit 25 - Configures whether SCL1 can use AHB burst operation when reading data from memory."] + #[inline(always)] + pub fn sdio_slc1_rxdata_burst_en(&mut self) -> SDIO_SLC1_RXDATA_BURST_EN_W { + SDIO_SLC1_RXDATA_BURST_EN_W::new(self, 25) + } + #[doc = "Bit 28 - Configures whether SCL1 can use AHB burst operation when read the TX linked list from memory."] + #[inline(always)] + pub fn sdio_slc1_txdscr_burst_en(&mut self) -> SDIO_SLC1_TXDSCR_BURST_EN_W { + SDIO_SLC1_TXDSCR_BURST_EN_W::new(self, 28) + } + #[doc = "Bit 29 - Configures whether SCL1 can use AHB burst operation when send data to memory."] + #[inline(always)] + pub fn sdio_slc1_txdata_burst_en(&mut self) -> SDIO_SLC1_TXDATA_BURST_EN_W { + SDIO_SLC1_TXDATA_BURST_EN_W::new(self, 29) + } + #[doc = "Bit 30 - Please initialize to 0, and do not modify it."] + #[inline(always)] + pub fn sdio_slc1_token_auto_clr(&mut self) -> SDIO_SLC1_TOKEN_AUTO_CLR_W { + SDIO_SLC1_TOKEN_AUTO_CLR_W::new(self, 30) + } +} +#[doc = "DMA configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`slcconf0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slcconf0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SLCCONF0_SPEC; +impl crate::RegisterSpec for SLCCONF0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`slcconf0::R`](R) reader structure"] +impl crate::Readable for SLCCONF0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`slcconf0::W`](W) writer structure"] +impl crate::Writable for SLCCONF0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SLCCONF0 to value 0xff3c_ff00"] +impl crate::Resettable for SLCCONF0_SPEC { + const RESET_VALUE: u32 = 0xff3c_ff00; +} diff --git a/esp32c6/src/slc/slcconf1.rs b/esp32c6/src/slc/slcconf1.rs new file mode 100644 index 000000000..80509c81b --- /dev/null +++ b/esp32c6/src/slc/slcconf1.rs @@ -0,0 +1,137 @@ +#[doc = "Register `SLCCONF1` reader"] +pub type R = crate::R; +#[doc = "Register `SLCCONF1` writer"] +pub type W = crate::W; +#[doc = "Field `SDIO_SDIO_CMD_HOLD_EN` reader - Please initialize to 0, and do not modify it."] +pub type SDIO_SDIO_CMD_HOLD_EN_R = crate::BitReader; +#[doc = "Field `SDIO_SDIO_CMD_HOLD_EN` writer - Please initialize to 0, and do not modify it."] +pub type SDIO_SDIO_CMD_HOLD_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC0_LEN_AUTO_CLR` reader - Please initialize to 0, and do not modify it."] +pub type SDIO_SLC0_LEN_AUTO_CLR_R = crate::BitReader; +#[doc = "Field `SDIO_SLC0_LEN_AUTO_CLR` writer - Please initialize to 0, and do not modify it."] +pub type SDIO_SLC0_LEN_AUTO_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC0_TX_STITCH_EN` reader - Please initialize to 0, and do not modify it."] +pub type SDIO_SLC0_TX_STITCH_EN_R = crate::BitReader; +#[doc = "Field `SDIO_SLC0_TX_STITCH_EN` writer - Please initialize to 0, and do not modify it."] +pub type SDIO_SLC0_TX_STITCH_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC0_RX_STITCH_EN` reader - Please initialize to 0, and do not modify it."] +pub type SDIO_SLC0_RX_STITCH_EN_R = crate::BitReader; +#[doc = "Field `SDIO_SLC0_RX_STITCH_EN` writer - Please initialize to 0, and do not modify it."] +pub type SDIO_SLC0_RX_STITCH_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_HOST_INT_LEVEL_SEL` reader - Configures the polarity of interrupt to host."] +pub type SDIO_HOST_INT_LEVEL_SEL_R = crate::BitReader; +#[doc = "Field `SDIO_HOST_INT_LEVEL_SEL` writer - Configures the polarity of interrupt to host."] +pub type SDIO_HOST_INT_LEVEL_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC1_TX_STITCH_EN` reader - Please initialize to 0, and do not modify it."] +pub type SDIO_SLC1_TX_STITCH_EN_R = crate::BitReader; +#[doc = "Field `SDIO_SLC1_TX_STITCH_EN` writer - Please initialize to 0, and do not modify it."] +pub type SDIO_SLC1_TX_STITCH_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_SLC1_RX_STITCH_EN` reader - Please initialize to 0, and do not modify it."] +pub type SDIO_SLC1_RX_STITCH_EN_R = crate::BitReader; +#[doc = "Field `SDIO_SLC1_RX_STITCH_EN` writer - Please initialize to 0, and do not modify it."] +pub type SDIO_SLC1_RX_STITCH_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 3 - Please initialize to 0, and do not modify it."] + #[inline(always)] + pub fn sdio_sdio_cmd_hold_en(&self) -> SDIO_SDIO_CMD_HOLD_EN_R { + SDIO_SDIO_CMD_HOLD_EN_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Please initialize to 0, and do not modify it."] + #[inline(always)] + pub fn sdio_slc0_len_auto_clr(&self) -> SDIO_SLC0_LEN_AUTO_CLR_R { + SDIO_SLC0_LEN_AUTO_CLR_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Please initialize to 0, and do not modify it."] + #[inline(always)] + pub fn sdio_slc0_tx_stitch_en(&self) -> SDIO_SLC0_TX_STITCH_EN_R { + SDIO_SLC0_TX_STITCH_EN_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Please initialize to 0, and do not modify it."] + #[inline(always)] + pub fn sdio_slc0_rx_stitch_en(&self) -> SDIO_SLC0_RX_STITCH_EN_R { + SDIO_SLC0_RX_STITCH_EN_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 19 - Configures the polarity of interrupt to host."] + #[inline(always)] + pub fn sdio_host_int_level_sel(&self) -> SDIO_HOST_INT_LEVEL_SEL_R { + SDIO_HOST_INT_LEVEL_SEL_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Please initialize to 0, and do not modify it."] + #[inline(always)] + pub fn sdio_slc1_tx_stitch_en(&self) -> SDIO_SLC1_TX_STITCH_EN_R { + SDIO_SLC1_TX_STITCH_EN_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Please initialize to 0, and do not modify it."] + #[inline(always)] + pub fn sdio_slc1_rx_stitch_en(&self) -> SDIO_SLC1_RX_STITCH_EN_R { + SDIO_SLC1_RX_STITCH_EN_R::new(((self.bits >> 21) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SLCCONF1") + .field("sdio_sdio_cmd_hold_en", &self.sdio_sdio_cmd_hold_en()) + .field("sdio_slc0_len_auto_clr", &self.sdio_slc0_len_auto_clr()) + .field("sdio_slc0_tx_stitch_en", &self.sdio_slc0_tx_stitch_en()) + .field("sdio_slc0_rx_stitch_en", &self.sdio_slc0_rx_stitch_en()) + .field("sdio_host_int_level_sel", &self.sdio_host_int_level_sel()) + .field("sdio_slc1_tx_stitch_en", &self.sdio_slc1_tx_stitch_en()) + .field("sdio_slc1_rx_stitch_en", &self.sdio_slc1_rx_stitch_en()) + .finish() + } +} +impl W { + #[doc = "Bit 3 - Please initialize to 0, and do not modify it."] + #[inline(always)] + pub fn sdio_sdio_cmd_hold_en(&mut self) -> SDIO_SDIO_CMD_HOLD_EN_W { + SDIO_SDIO_CMD_HOLD_EN_W::new(self, 3) + } + #[doc = "Bit 4 - Please initialize to 0, and do not modify it."] + #[inline(always)] + pub fn sdio_slc0_len_auto_clr(&mut self) -> SDIO_SLC0_LEN_AUTO_CLR_W { + SDIO_SLC0_LEN_AUTO_CLR_W::new(self, 4) + } + #[doc = "Bit 5 - Please initialize to 0, and do not modify it."] + #[inline(always)] + pub fn sdio_slc0_tx_stitch_en(&mut self) -> SDIO_SLC0_TX_STITCH_EN_W { + SDIO_SLC0_TX_STITCH_EN_W::new(self, 5) + } + #[doc = "Bit 6 - Please initialize to 0, and do not modify it."] + #[inline(always)] + pub fn sdio_slc0_rx_stitch_en(&mut self) -> SDIO_SLC0_RX_STITCH_EN_W { + SDIO_SLC0_RX_STITCH_EN_W::new(self, 6) + } + #[doc = "Bit 19 - Configures the polarity of interrupt to host."] + #[inline(always)] + pub fn sdio_host_int_level_sel(&mut self) -> SDIO_HOST_INT_LEVEL_SEL_W { + SDIO_HOST_INT_LEVEL_SEL_W::new(self, 19) + } + #[doc = "Bit 20 - Please initialize to 0, and do not modify it."] + #[inline(always)] + pub fn sdio_slc1_tx_stitch_en(&mut self) -> SDIO_SLC1_TX_STITCH_EN_W { + SDIO_SLC1_TX_STITCH_EN_W::new(self, 20) + } + #[doc = "Bit 21 - Please initialize to 0, and do not modify it."] + #[inline(always)] + pub fn sdio_slc1_rx_stitch_en(&mut self) -> SDIO_SLC1_RX_STITCH_EN_W { + SDIO_SLC1_RX_STITCH_EN_W::new(self, 21) + } +} +#[doc = "DMA configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`slcconf1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slcconf1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SLCCONF1_SPEC; +impl crate::RegisterSpec for SLCCONF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`slcconf1::R`](R) reader structure"] +impl crate::Readable for SLCCONF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`slcconf1::W`](W) writer structure"] +impl crate::Writable for SLCCONF1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SLCCONF1 to value 0x0030_0078"] +impl crate::Resettable for SLCCONF1_SPEC { + const RESET_VALUE: u32 = 0x0030_0078; +} diff --git a/esp32c6/src/slc/slcintvec_tohost.rs b/esp32c6/src/slc/slcintvec_tohost.rs new file mode 100644 index 000000000..2858e6e26 --- /dev/null +++ b/esp32c6/src/slc/slcintvec_tohost.rs @@ -0,0 +1,39 @@ +#[doc = "Register `SLCINTVEC_TOHOST` writer"] +pub type W = crate::W; +#[doc = "Field `SDIO_SLC0_TOHOST_INTVEC` writer - The interrupt set bit of SLCHOST_SLC0_TOHOST_BITn_INT (n: 0-7)."] +pub type SDIO_SLC0_TOHOST_INTVEC_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `SDIO_SLC1_TOHOST_INTVEC` writer - The interrupt set bit of SLCHOST_SLC1_TOHOST_BITn_INT (n: 0-7)."] +pub type SDIO_SLC1_TOHOST_INTVEC_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bits 0:7 - The interrupt set bit of SLCHOST_SLC0_TOHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc0_tohost_intvec(&mut self) -> SDIO_SLC0_TOHOST_INTVEC_W { + SDIO_SLC0_TOHOST_INTVEC_W::new(self, 0) + } + #[doc = "Bits 16:23 - The interrupt set bit of SLCHOST_SLC1_TOHOST_BITn_INT (n: 0-7)."] + #[inline(always)] + pub fn sdio_slc1_tohost_intvec(&mut self) -> SDIO_SLC1_TOHOST_INTVEC_W { + SDIO_SLC1_TOHOST_INTVEC_W::new(self, 16) + } +} +#[doc = "Slave to host interrupt vector set\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slcintvec_tohost::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SLCINTVEC_TOHOST_SPEC; +impl crate::RegisterSpec for SLCINTVEC_TOHOST_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`slcintvec_tohost::W`](W) writer structure"] +impl crate::Writable for SLCINTVEC_TOHOST_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SLCINTVEC_TOHOST to value 0"] +impl crate::Resettable for SLCINTVEC_TOHOST_SPEC { + const RESET_VALUE: u32 = 0; +}