esp32c6: generate the SLC peripheral

Generates the `slc` peripheral using the definitions added to the SVD
patches file.

esp32c6/src/lib.rs

@@ -2518,7 +2518,7 @@ pub struct SLCHOST {
 unsafe impl Send for SLCHOST {}
 impl SLCHOST {
     #[doc = r"Pointer to the register block"]
-    pub const PTR: *const slchost::RegisterBlock = 0x6001_7000 as *const _;
+    pub const PTR: *const slchost::RegisterBlock = 0x6001_8000 as *const _;
     #[doc = r"Return the pointer to the register block"]
     #[inline(always)]
     pub const fn ptr() -> *const slchost::RegisterBlock {
@@ -3431,6 +3431,52 @@ impl core::fmt::Debug for I2C_ANA_MST {
 }
 #[doc = "I2C_ANA_MST Peripheral"]
 pub mod i2c_ana_mst;
+#[doc = "SDIO SLC"]
+pub struct SLC {
+    _marker: PhantomData<*const ()>,
+}
+unsafe impl Send for SLC {}
+impl SLC {
+    #[doc = r"Pointer to the register block"]
+    pub const PTR: *const slc::RegisterBlock = 0x6001_7000 as *const _;
+    #[doc = r"Return the pointer to the register block"]
+    #[inline(always)]
+    pub const fn ptr() -> *const slc::RegisterBlock {
+        Self::PTR
+    }
+    #[doc = r" Steal an instance of this peripheral"]
+    #[doc = r""]
+    #[doc = r" # Safety"]
+    #[doc = r""]
+    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
+    #[doc = r" that may race with any existing instances, for example by only"]
+    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
+    #[doc = r" original peripheral and using critical sections to coordinate"]
+    #[doc = r" access between multiple new instances."]
+    #[doc = r""]
+    #[doc = r" Additionally, other software such as HALs may rely on only one"]
+    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
+    #[doc = r" no stolen instances are passed to such software."]
+    pub unsafe fn steal() -> Self {
+        Self {
+            _marker: PhantomData,
+        }
+    }
+}
+impl Deref for SLC {
+    type Target = slc::RegisterBlock;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        unsafe { &*Self::PTR }
+    }
+}
+impl core::fmt::Debug for SLC {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SLC").finish()
+    }
+}
+#[doc = "SDIO SLC"]
+pub mod slc;
 #[no_mangle]
 static mut DEVICE_PERIPHERALS: bool = false;
 #[doc = r" All the peripherals."]
@@ -3574,6 +3620,8 @@ pub struct Peripherals {
     pub PLIC_UX: PLIC_UX,
     #[doc = "I2C_ANA_MST"]
     pub I2C_ANA_MST: I2C_ANA_MST,
+    #[doc = "SLC"]
+    pub SLC: SLC,
 }
 impl Peripherals {
     #[doc = r" Returns all the peripherals *once*."]
@@ -3665,6 +3713,7 @@ impl Peripherals {
             PLIC_MX: PLIC_MX::steal(),
             PLIC_UX: PLIC_UX::steal(),
             I2C_ANA_MST: I2C_ANA_MST::steal(),
+            SLC: SLC::steal(),
         }
     }
 }

esp32c6/src/slc/slc0_len_conf.rs

@@ -0,0 +1,53 @@
+#[doc = "Register `SLC0_LEN_CONF` writer"]
+pub type W = crate::W<SLC0_LEN_CONF_SPEC>;
+#[doc = "Field `SDIO_SLC0_LEN_WDATA` writer - Configures the length of the data that the slave wants to send."]
+pub type SDIO_SLC0_LEN_WDATA_W<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>;
+#[doc = "Field `SDIO_SLC0_LEN_WR` writer - Configures this bit to 1 to write SDIO_SLC0_LEN_WDATA into SDIO_SLC0_LEN and SLCHOST_HOSTSLCHOST_SLC0_LEN."]
+pub type SDIO_SLC0_LEN_WR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SDIO_SLC0_LEN_INC` writer - Configures this bit to 1 to add 1 to SDIO_SLC0_LEN and SLCHOST_HOSTSLCHOST_SLC0_LEN."]
+pub type SDIO_SLC0_LEN_INC_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SDIO_SLC0_LEN_INC_MORE` writer - Configures this bit to 1 to add the value of SDIO_SLC0_LEN_WDATA to SDIO_SLC0_LEN and SLCHOST_HOSTSLCHOST_SLC0_LEN."]
+pub type SDIO_SLC0_LEN_INC_MORE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for crate::generic::Reg<SLC0_LEN_CONF_SPEC> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        write!(f, "(not readable)")
+    }
+}
+impl W {
+    #[doc = "Bits 0:19 - Configures the length of the data that the slave wants to send."]
+    #[inline(always)]
+    pub fn sdio_slc0_len_wdata(&mut self) -> SDIO_SLC0_LEN_WDATA_W<SLC0_LEN_CONF_SPEC> {
+        SDIO_SLC0_LEN_WDATA_W::new(self, 0)
+    }
+    #[doc = "Bit 20 - Configures this bit to 1 to write SDIO_SLC0_LEN_WDATA into SDIO_SLC0_LEN and SLCHOST_HOSTSLCHOST_SLC0_LEN."]
+    #[inline(always)]
+    pub fn sdio_slc0_len_wr(&mut self) -> SDIO_SLC0_LEN_WR_W<SLC0_LEN_CONF_SPEC> {
+        SDIO_SLC0_LEN_WR_W::new(self, 20)
+    }
+    #[doc = "Bit 21 - Configures this bit to 1 to add 1 to SDIO_SLC0_LEN and SLCHOST_HOSTSLCHOST_SLC0_LEN."]
+    #[inline(always)]
+    pub fn sdio_slc0_len_inc(&mut self) -> SDIO_SLC0_LEN_INC_W<SLC0_LEN_CONF_SPEC> {
+        SDIO_SLC0_LEN_INC_W::new(self, 21)
+    }
+    #[doc = "Bit 22 - Configures this bit to 1 to add the value of SDIO_SLC0_LEN_WDATA to SDIO_SLC0_LEN and SLCHOST_HOSTSLCHOST_SLC0_LEN."]
+    #[inline(always)]
+    pub fn sdio_slc0_len_inc_more(&mut self) -> SDIO_SLC0_LEN_INC_MORE_W<SLC0_LEN_CONF_SPEC> {
+        SDIO_SLC0_LEN_INC_MORE_W::new(self, 22)
+    }
+}
+#[doc = "Length control of transmitting packets\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc0_len_conf::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SLC0_LEN_CONF_SPEC;
+impl crate::RegisterSpec for SLC0_LEN_CONF_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [`slc0_len_conf::W`](W) writer structure"]
+impl crate::Writable for SLC0_LEN_CONF_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SLC0_LEN_CONF to value 0x2000_0000"]
+impl crate::Resettable for SLC0_LEN_CONF_SPEC {
+    const RESET_VALUE: u32 = 0x2000_0000;
+}

esp32c6/src/slc/slc0_rx_sharemem_end.rs

@@ -0,0 +1,52 @@
+#[doc = "Register `SLC0_RX_SHAREMEM_END` reader"]
+pub type R = crate::R<SLC0_RX_SHAREMEM_END_SPEC>;
+#[doc = "Register `SLC0_RX_SHAREMEM_END` writer"]
+pub type W = crate::W<SLC0_RX_SHAREMEM_END_SPEC>;
+#[doc = "Field `SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR` reader - Configures SLC0 slave to host channel AHB end address boundary."]
+pub type SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR_R = crate::FieldReader<u32>;
+#[doc = "Field `SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR` writer - Configures SLC0 slave to host channel AHB end address boundary."]
+pub type SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - Configures SLC0 slave to host channel AHB end address boundary."]
+    #[inline(always)]
+    pub fn sdio_sdio_slc0_rx_sharemem_end_addr(&self) -> SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR_R {
+        SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SLC0_RX_SHAREMEM_END")
+            .field(
+                "sdio_sdio_slc0_rx_sharemem_end_addr",
+                &self.sdio_sdio_slc0_rx_sharemem_end_addr(),
+            )
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - Configures SLC0 slave to host channel AHB end address boundary."]
+    #[inline(always)]
+    pub fn sdio_sdio_slc0_rx_sharemem_end_addr(
+        &mut self,
+    ) -> SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR_W<SLC0_RX_SHAREMEM_END_SPEC> {
+        SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR_W::new(self, 0)
+    }
+}
+#[doc = "SLC0 AHB RX end address range\n\nYou can [`read`](crate::Reg::read) this register and get [`slc0_rx_sharemem_end::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc0_rx_sharemem_end::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SLC0_RX_SHAREMEM_END_SPEC;
+impl crate::RegisterSpec for SLC0_RX_SHAREMEM_END_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`slc0_rx_sharemem_end::R`](R) reader structure"]
+impl crate::Readable for SLC0_RX_SHAREMEM_END_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`slc0_rx_sharemem_end::W`](W) writer structure"]
+impl crate::Writable for SLC0_RX_SHAREMEM_END_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SLC0_RX_SHAREMEM_END to value 0xffff_ffff"]
+impl crate::Resettable for SLC0_RX_SHAREMEM_END_SPEC {
+    const RESET_VALUE: u32 = 0xffff_ffff;
+}

esp32c6/src/slc/slc0_rx_sharemem_start.rs

@@ -0,0 +1,52 @@
+#[doc = "Register `SLC0_RX_SHAREMEM_START` reader"]
+pub type R = crate::R<SLC0_RX_SHAREMEM_START_SPEC>;
+#[doc = "Register `SLC0_RX_SHAREMEM_START` writer"]
+pub type W = crate::W<SLC0_RX_SHAREMEM_START_SPEC>;
+#[doc = "Field `SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR` reader - Configures SLC0 slave to host channel AHB start address boundary."]
+pub type SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR_R = crate::FieldReader<u32>;
+#[doc = "Field `SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR` writer - Configures SLC0 slave to host channel AHB start address boundary."]
+pub type SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - Configures SLC0 slave to host channel AHB start address boundary."]
+    #[inline(always)]
+    pub fn sdio_sdio_slc0_rx_sharemem_start_addr(&self) -> SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR_R {
+        SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SLC0_RX_SHAREMEM_START")
+            .field(
+                "sdio_sdio_slc0_rx_sharemem_start_addr",
+                &self.sdio_sdio_slc0_rx_sharemem_start_addr(),
+            )
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - Configures SLC0 slave to host channel AHB start address boundary."]
+    #[inline(always)]
+    pub fn sdio_sdio_slc0_rx_sharemem_start_addr(
+        &mut self,
+    ) -> SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR_W<SLC0_RX_SHAREMEM_START_SPEC> {
+        SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR_W::new(self, 0)
+    }
+}
+#[doc = "SLC0 AHB RX start address range\n\nYou can [`read`](crate::Reg::read) this register and get [`slc0_rx_sharemem_start::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc0_rx_sharemem_start::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SLC0_RX_SHAREMEM_START_SPEC;
+impl crate::RegisterSpec for SLC0_RX_SHAREMEM_START_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`slc0_rx_sharemem_start::R`](R) reader structure"]
+impl crate::Readable for SLC0_RX_SHAREMEM_START_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`slc0_rx_sharemem_start::W`](W) writer structure"]
+impl crate::Writable for SLC0_RX_SHAREMEM_START_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SLC0_RX_SHAREMEM_START to value 0"]
+impl crate::Resettable for SLC0_RX_SHAREMEM_START_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

esp32c6/src/slc/slc0_tx_sharemem_end.rs

@@ -0,0 +1,52 @@
+#[doc = "Register `SLC0_TX_SHAREMEM_END` reader"]
+pub type R = crate::R<SLC0_TX_SHAREMEM_END_SPEC>;
+#[doc = "Register `SLC0_TX_SHAREMEM_END` writer"]
+pub type W = crate::W<SLC0_TX_SHAREMEM_END_SPEC>;
+#[doc = "Field `SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR` reader - Configures SLC0 host to slave channel AHB end address boundary."]
+pub type SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR_R = crate::FieldReader<u32>;
+#[doc = "Field `SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR` writer - Configures SLC0 host to slave channel AHB end address boundary."]
+pub type SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - Configures SLC0 host to slave channel AHB end address boundary."]
+    #[inline(always)]
+    pub fn sdio_sdio_slc0_tx_sharemem_end_addr(&self) -> SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR_R {
+        SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SLC0_TX_SHAREMEM_END")
+            .field(
+                "sdio_sdio_slc0_tx_sharemem_end_addr",
+                &self.sdio_sdio_slc0_tx_sharemem_end_addr(),
+            )
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - Configures SLC0 host to slave channel AHB end address boundary."]
+    #[inline(always)]
+    pub fn sdio_sdio_slc0_tx_sharemem_end_addr(
+        &mut self,
+    ) -> SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR_W<SLC0_TX_SHAREMEM_END_SPEC> {
+        SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR_W::new(self, 0)
+    }
+}
+#[doc = "SLC0 AHB TX end address range\n\nYou can [`read`](crate::Reg::read) this register and get [`slc0_tx_sharemem_end::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc0_tx_sharemem_end::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SLC0_TX_SHAREMEM_END_SPEC;
+impl crate::RegisterSpec for SLC0_TX_SHAREMEM_END_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`slc0_tx_sharemem_end::R`](R) reader structure"]
+impl crate::Readable for SLC0_TX_SHAREMEM_END_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`slc0_tx_sharemem_end::W`](W) writer structure"]
+impl crate::Writable for SLC0_TX_SHAREMEM_END_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SLC0_TX_SHAREMEM_END to value 0xffff_ffff"]
+impl crate::Resettable for SLC0_TX_SHAREMEM_END_SPEC {
+    const RESET_VALUE: u32 = 0xffff_ffff;
+}

esp32c6/src/slc/slc0_tx_sharemem_start.rs

@@ -0,0 +1,52 @@
+#[doc = "Register `SLC0_TX_SHAREMEM_START` reader"]
+pub type R = crate::R<SLC0_TX_SHAREMEM_START_SPEC>;
+#[doc = "Register `SLC0_TX_SHAREMEM_START` writer"]
+pub type W = crate::W<SLC0_TX_SHAREMEM_START_SPEC>;
+#[doc = "Field `SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR` reader - Configures SLC0 host to slave channel AHB start address boundary."]
+pub type SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR_R = crate::FieldReader<u32>;
+#[doc = "Field `SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR` writer - Configures SLC0 host to slave channel AHB start address boundary."]
+pub type SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - Configures SLC0 host to slave channel AHB start address boundary."]
+    #[inline(always)]
+    pub fn sdio_sdio_slc0_tx_sharemem_start_addr(&self) -> SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR_R {
+        SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SLC0_TX_SHAREMEM_START")
+            .field(
+                "sdio_sdio_slc0_tx_sharemem_start_addr",
+                &self.sdio_sdio_slc0_tx_sharemem_start_addr(),
+            )
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - Configures SLC0 host to slave channel AHB start address boundary."]
+    #[inline(always)]
+    pub fn sdio_sdio_slc0_tx_sharemem_start_addr(
+        &mut self,
+    ) -> SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR_W<SLC0_TX_SHAREMEM_START_SPEC> {
+        SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR_W::new(self, 0)
+    }
+}
+#[doc = "SLC0 AHB TX start address range\n\nYou can [`read`](crate::Reg::read) this register and get [`slc0_tx_sharemem_start::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc0_tx_sharemem_start::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SLC0_TX_SHAREMEM_START_SPEC;
+impl crate::RegisterSpec for SLC0_TX_SHAREMEM_START_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`slc0_tx_sharemem_start::R`](R) reader structure"]
+impl crate::Readable for SLC0_TX_SHAREMEM_START_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`slc0_tx_sharemem_start::W`](W) writer structure"]
+impl crate::Writable for SLC0_TX_SHAREMEM_START_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SLC0_TX_SHAREMEM_START to value 0"]
+impl crate::Resettable for SLC0_TX_SHAREMEM_START_SPEC {
+    const RESET_VALUE: u32 = 0;
+}