Align RSA interrupt register/field names and access (#286)

* Align RSA interrupt enable register/field name for S2/S3 with other chips * Align RSA interrupt clear register/field name for S2/S3 with other chips * More RSA interrupt clear cleanup I guess * Make RSA's interrupt clear field R/W
esp-rs · Oct 22, 2024 · 78d5232 · 78d5232
1 parent 262388a
commit 78d5232
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diff --git a/esp32c3/src/rsa.rs b/esp32c3/src/rsa.rs
@@ -179,7 +179,7 @@ pub mod set_start_mult;
 pub type QUERY_IDLE = crate::Reg<query_idle::QUERY_IDLE_SPEC>;
 #[doc = "RSA query idle register"]
 pub mod query_idle;
-#[doc = "INT_CLR (w) register accessor: RSA interrupt clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr`] module"]
+#[doc = "INT_CLR (rw) register accessor: RSA interrupt clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_clr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr`] module"]
 pub type INT_CLR = crate::Reg<int_clr::INT_CLR_SPEC>;
 #[doc = "RSA interrupt clear register"]
 pub mod int_clr;

diff --git a/esp32c3/src/rsa/int_clr.rs b/esp32c3/src/rsa/int_clr.rs
@@ -1,26 +1,41 @@
+#[doc = "Register `INT_CLR` reader"]
+pub type R = crate::R<INT_CLR_SPEC>;
 #[doc = "Register `INT_CLR` writer"]
 pub type W = crate::W<INT_CLR_SPEC>;
-#[doc = "Field `CLEAR_INTERRUPT` writer - set this bit to clear RSA interrupt."]
-pub type CLEAR_INTERRUPT_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `INT_CLR` reader - set this bit to clear RSA interrupt."]
+pub type INT_CLR_R = crate::BitReader;
+#[doc = "Field `INT_CLR` writer - set this bit to clear RSA interrupt."]
+pub type INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - set this bit to clear RSA interrupt."]
+    #[inline(always)]
+    pub fn int_clr(&self) -> INT_CLR_R {
+        INT_CLR_R::new((self.bits & 1) != 0)
+    }
+}
 #[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        write!(f, "(not readable)")
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("INT_CLR")
+            .field("int_clr", &self.int_clr())
+            .finish()
     }
 }
 impl W {
     #[doc = "Bit 0 - set this bit to clear RSA interrupt."]
     #[inline(always)]
     #[must_use]
-    pub fn clear_interrupt(&mut self) -> CLEAR_INTERRUPT_W<INT_CLR_SPEC> {
-        CLEAR_INTERRUPT_W::new(self, 0)
+    pub fn int_clr(&mut self) -> INT_CLR_W<INT_CLR_SPEC> {
+        INT_CLR_W::new(self, 0)
     }
 }
-#[doc = "RSA interrupt clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "RSA interrupt clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_CLR_SPEC;
 impl crate::RegisterSpec for INT_CLR_SPEC {
     type Ux = u32;
 }
+#[doc = "`read()` method returns [`int_clr::R`](R) reader structure"]
+impl crate::Readable for INT_CLR_SPEC {}
 #[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"]
 impl crate::Writable for INT_CLR_SPEC {
     type Safety = crate::Unsafe;

diff --git a/esp32c3/svd/patches/esp32c3.yaml b/esp32c3/svd/patches/esp32c3.yaml
@@ -66,21 +66,21 @@ _add:
       usage: registers
     registers:
       GEN_CTRL:
-          description: "FE General Control Register"
-          addressOffset: 0x0090
-          size: 0x2
-          access: read-write
-          fields:
-            IQ_EST_FORCE_PU:
-              description: "Force Power Up for IQ Estimation"
-              bitOffset: 5
-              bitWidth: 1
-              access: read-write
-            IQ_EST_FORCE_PD:
-              description: "Force Power Down for IQ Estimation"
-              bitOffset: 4
-              bitWidth: 1
-              access: read-write
+        description: "FE General Control Register"
+        addressOffset: 0x0090
+        size: 0x2
+        access: read-write
+        fields:
+          IQ_EST_FORCE_PU:
+            description: "Force Power Up for IQ Estimation"
+            bitOffset: 5
+            bitWidth: 1
+            access: read-write
+          IQ_EST_FORCE_PD:
+            description: "Force Power Down for IQ Estimation"
+            bitOffset: 4
+            bitWidth: 1
+            access: read-write
   FE2:
     description: need des
     baseAddress: 0x60005000
@@ -91,22 +91,21 @@ _add:
       usage: registers
     registers:
       TX_INTERP_CTRL:
-          description: "FE2 TX Interpolation Control Register"
-          addressOffset: 0x00f0
-          size: 0x20
-          access: read-write
-          fields:
-            TX_INF_FORCE_PU:
-              description: "Force Power Up field"
-              bitOffset: 10
-              bitWidth: 1
-              access: read-write
-            TX_INF_FORCE_PD:
-              description: "Force Power Down field"
-              bitOffset: 9
-              bitWidth: 1
-              access: read-write
-
+        description: "FE2 TX Interpolation Control Register"
+        addressOffset: 0x00f0
+        size: 0x20
+        access: read-write
+        fields:
+          TX_INF_FORCE_PU:
+            description: "Force Power Up field"
+            bitOffset: 10
+            bitWidth: 1
+            access: read-write
+          TX_INF_FORCE_PD:
+            description: "Force Power Down field"
+            bitOffset: 9
+            bitWidth: 1
+            access: read-write
 
 _modify:
   SPI?:
@@ -186,7 +185,6 @@ LEDC:
       "*":
         modifiedWriteValues: oneToClear
 
-
 APB_CTRL:
   PERI_BACKUP_INT_RAW:
     _strip: PERI_BACKUP_
@@ -241,16 +239,16 @@ SPI2:
 
 DS:
   _add:
-      IV_MEM%s:
-        dim: 4
-        dimIncrement: 0x4
-        name: IV_MEM%s
-        description: IV block data
-        addressOffset: 0x630
-        size: 0x20
+    IV_MEM%s:
+      dim: 4
+      dimIncrement: 0x4
+      name: IV_MEM%s
+      description: IV block data
+      addressOffset: 0x630
+      size: 0x20
 
 SYSTIMER:
-  _include: 
+  _include:
     - ../../../common_patches/int_strip.yaml
     - ../../../common_patches/systimer.yaml
 
@@ -340,4 +338,10 @@ DMA:
 
 ASSIST_DEBUG:
   _include: ../../../common_patches/assist_debug.yaml
-
+
+RSA:
+  INT_CLR:
+    _modify:
+      CLEAR_INTERRUPT:
+        name: INT_CLR
+        access: read-write
diff --git a/esp32c6/src/rsa.rs b/esp32c6/src/rsa.rs
@@ -179,7 +179,7 @@ pub mod set_start_mult;
 pub type QUERY_IDLE = crate::Reg<query_idle::QUERY_IDLE_SPEC>;
 #[doc = "RSA query idle register"]
 pub mod query_idle;
-#[doc = "INT_CLR (w) register accessor: RSA interrupt clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr`] module"]
+#[doc = "INT_CLR (rw) register accessor: RSA interrupt clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_clr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr`] module"]
 pub type INT_CLR = crate::Reg<int_clr::INT_CLR_SPEC>;
 #[doc = "RSA interrupt clear register"]
 pub mod int_clr;

diff --git a/esp32c6/src/rsa/int_clr.rs b/esp32c6/src/rsa/int_clr.rs
@@ -1,26 +1,41 @@
+#[doc = "Register `INT_CLR` reader"]
+pub type R = crate::R<INT_CLR_SPEC>;
 #[doc = "Register `INT_CLR` writer"]
 pub type W = crate::W<INT_CLR_SPEC>;
-#[doc = "Field `CLEAR_INTERRUPT` writer - set this bit to clear RSA interrupt."]
-pub type CLEAR_INTERRUPT_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `INT_CLR` reader - set this bit to clear RSA interrupt."]
+pub type INT_CLR_R = crate::BitReader;
+#[doc = "Field `INT_CLR` writer - set this bit to clear RSA interrupt."]
+pub type INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - set this bit to clear RSA interrupt."]
+    #[inline(always)]
+    pub fn int_clr(&self) -> INT_CLR_R {
+        INT_CLR_R::new((self.bits & 1) != 0)
+    }
+}
 #[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        write!(f, "(not readable)")
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("INT_CLR")
+            .field("int_clr", &self.int_clr())
+            .finish()
     }
 }
 impl W {
     #[doc = "Bit 0 - set this bit to clear RSA interrupt."]
     #[inline(always)]
     #[must_use]
-    pub fn clear_interrupt(&mut self) -> CLEAR_INTERRUPT_W<INT_CLR_SPEC> {
-        CLEAR_INTERRUPT_W::new(self, 0)
+    pub fn int_clr(&mut self) -> INT_CLR_W<INT_CLR_SPEC> {
+        INT_CLR_W::new(self, 0)
     }
 }
-#[doc = "RSA interrupt clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "RSA interrupt clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_CLR_SPEC;
 impl crate::RegisterSpec for INT_CLR_SPEC {
     type Ux = u32;
 }
+#[doc = "`read()` method returns [`int_clr::R`](R) reader structure"]
+impl crate::Readable for INT_CLR_SPEC {}
 #[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"]
 impl crate::Writable for INT_CLR_SPEC {
     type Safety = crate::Unsafe;

diff --git a/esp32c6/svd/patches/esp32c6.yaml b/esp32c6/svd/patches/esp32c6.yaml
@@ -477,3 +477,10 @@ RMT:
       - SCLK_DIV_B
       - SCLK_SEL
       - SCLK_ACTIVE
+
+RSA:
+  INT_CLR:
+    _modify:
+      CLEAR_INTERRUPT:
+        name: INT_CLR
+        access: read-write
diff --git a/esp32h2/src/rsa.rs b/esp32h2/src/rsa.rs
@@ -179,7 +179,7 @@ pub mod set_start_mult;
 pub type QUERY_IDLE = crate::Reg<query_idle::QUERY_IDLE_SPEC>;
 #[doc = "Represents the RSA status"]
 pub mod query_idle;
-#[doc = "INT_CLR (w) register accessor: Clears RSA interrupt\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr`] module"]
+#[doc = "INT_CLR (rw) register accessor: Clears RSA interrupt\n\nYou can [`read`](crate::Reg::read) this register and get [`int_clr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr`] module"]
 pub type INT_CLR = crate::Reg<int_clr::INT_CLR_SPEC>;
 #[doc = "Clears RSA interrupt"]
 pub mod int_clr;

diff --git a/esp32h2/src/rsa/int_clr.rs b/esp32h2/src/rsa/int_clr.rs
@@ -1,26 +1,41 @@
+#[doc = "Register `INT_CLR` reader"]
+pub type R = crate::R<INT_CLR_SPEC>;
 #[doc = "Register `INT_CLR` writer"]
 pub type W = crate::W<INT_CLR_SPEC>;
-#[doc = "Field `CLEAR_INTERRUPT` writer - Write 1 to clear the RSA interrupt."]
-pub type CLEAR_INTERRUPT_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `INT_CLR` reader - Write 1 to clear the RSA interrupt."]
+pub type INT_CLR_R = crate::BitReader;
+#[doc = "Field `INT_CLR` writer - Write 1 to clear the RSA interrupt."]
+pub type INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - Write 1 to clear the RSA interrupt."]
+    #[inline(always)]
+    pub fn int_clr(&self) -> INT_CLR_R {
+        INT_CLR_R::new((self.bits & 1) != 0)
+    }
+}
 #[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        write!(f, "(not readable)")
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("INT_CLR")
+            .field("int_clr", &self.int_clr())
+            .finish()
     }
 }
 impl W {
     #[doc = "Bit 0 - Write 1 to clear the RSA interrupt."]
     #[inline(always)]
     #[must_use]
-    pub fn clear_interrupt(&mut self) -> CLEAR_INTERRUPT_W<INT_CLR_SPEC> {
-        CLEAR_INTERRUPT_W::new(self, 0)
+    pub fn int_clr(&mut self) -> INT_CLR_W<INT_CLR_SPEC> {
+        INT_CLR_W::new(self, 0)
     }
 }
-#[doc = "Clears RSA interrupt\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Clears RSA interrupt\n\nYou can [`read`](crate::Reg::read) this register and get [`int_clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_CLR_SPEC;
 impl crate::RegisterSpec for INT_CLR_SPEC {
     type Ux = u32;
 }
+#[doc = "`read()` method returns [`int_clr::R`](R) reader structure"]
+impl crate::Readable for INT_CLR_SPEC {}
 #[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"]
 impl crate::Writable for INT_CLR_SPEC {
     type Safety = crate::Unsafe;

diff --git a/esp32h2/svd/patches/esp32h2.yaml b/esp32h2/svd/patches/esp32h2.yaml
@@ -493,3 +493,10 @@ RMT:
       - SCLK_DIV_B
       - SCLK_SEL
       - SCLK_ACTIVE
+
+RSA:
+  INT_CLR:
+    _modify:
+      CLEAR_INTERRUPT:
+        name: INT_CLR
+        access: read-write
diff --git a/esp32s2/src/rsa.rs b/esp32s2/src/rsa.rs
@@ -13,11 +13,11 @@ pub struct RegisterBlock {
     modmult_start: MODMULT_START,
     mult_start: MULT_START,
     idle: IDLE,
-    clear_interrupt: CLEAR_INTERRUPT,
+    int_clr: INT_CLR,
     constant_time: CONSTANT_TIME,
     search_enable: SEARCH_ENABLE,
     search_pos: SEARCH_POS,
-    interrupt_ena: INTERRUPT_ENA,
+    int_ena: INT_ENA,
     date: DATE,
 }
 impl RegisterBlock {
@@ -102,8 +102,8 @@ impl RegisterBlock {
     }
     #[doc = "0x81c - RSA clear interrupt register"]
     #[inline(always)]
-    pub const fn clear_interrupt(&self) -> &CLEAR_INTERRUPT {
-        &self.clear_interrupt
+    pub const fn int_clr(&self) -> &INT_CLR {
+        &self.int_clr
     }
     #[doc = "0x820 - The constant_time option"]
     #[inline(always)]
@@ -122,8 +122,8 @@ impl RegisterBlock {
     }
     #[doc = "0x82c - RSA interrupt enable register"]
     #[inline(always)]
-    pub const fn interrupt_ena(&self) -> &INTERRUPT_ENA {
-        &self.interrupt_ena
+    pub const fn int_ena(&self) -> &INT_ENA {
+        &self.int_ena
     }
     #[doc = "0x830 - Version control register"]
     #[inline(always)]
@@ -159,10 +159,10 @@ pub mod mult_start;
 pub type IDLE = crate::Reg<idle::IDLE_SPEC>;
 #[doc = "RSA idle register"]
 pub mod idle;
-#[doc = "CLEAR_INTERRUPT (w) register accessor: RSA clear interrupt register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clear_interrupt::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clear_interrupt`] module"]
-pub type CLEAR_INTERRUPT = crate::Reg<clear_interrupt::CLEAR_INTERRUPT_SPEC>;
+#[doc = "INT_CLR (rw) register accessor: RSA clear interrupt register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_clr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr`] module"]
+pub type INT_CLR = crate::Reg<int_clr::INT_CLR_SPEC>;
 #[doc = "RSA clear interrupt register"]
-pub mod clear_interrupt;
+pub mod int_clr;
 #[doc = "CONSTANT_TIME (rw) register accessor: The constant_time option\n\nYou can [`read`](crate::Reg::read) this register and get [`constant_time::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`constant_time::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@constant_time`] module"]
 pub type CONSTANT_TIME = crate::Reg<constant_time::CONSTANT_TIME_SPEC>;
 #[doc = "The constant_time option"]
@@ -175,10 +175,10 @@ pub mod search_enable;
 pub type SEARCH_POS = crate::Reg<search_pos::SEARCH_POS_SPEC>;
 #[doc = "The search position"]
 pub mod search_pos;
-#[doc = "INTERRUPT_ENA (rw) register accessor: RSA interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`interrupt_ena::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interrupt_ena::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@interrupt_ena`] module"]
-pub type INTERRUPT_ENA = crate::Reg<interrupt_ena::INTERRUPT_ENA_SPEC>;
+#[doc = "INT_ENA (rw) register accessor: RSA interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ena::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ena::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ena`] module"]
+pub type INT_ENA = crate::Reg<int_ena::INT_ENA_SPEC>;
 #[doc = "RSA interrupt enable register"]
-pub mod interrupt_ena;
+pub mod int_ena;
 #[doc = "DATE (rw) register accessor: Version control register\n\nYou can [`read`](crate::Reg::read) this register and get [`date::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`date::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@date`] module"]
 pub type DATE = crate::Reg<date::DATE_SPEC>;
 #[doc = "Version control register"]