From 207964207e83c413ee495ea0545d4f89c04eefc5 Mon Sep 17 00:00:00 2001 From: Frostie314159 Date: Mon, 13 Jan 2025 09:55:17 +0100 Subject: [PATCH] Add minimal support for Wi-Fi on the ESP32-S2. (#309) * Added support for the WiFi peripheral. * Added basic crypto and cleaned up filtering. * Added some statistic registers. * Regenerated PAC. * Fixed addressOffset fields for filters. * Revert "Fixed addressOffset fields for filters." This reverts commit 6bc584dba76d58065526bd0b5def657d04db0c8b. * Added unknown PMD register. * Temporarily removed crypto support * Made Wi-Fi patches relocatable for different chips. * Added more registers to SVD. * Removed CTS_UNKNOWN field. * Declustered TX parameters --- common_patches/wifi/mac_interrupt.yaml | 14 + common_patches/wifi/pwr_interrupt.yaml | 13 + common_patches/wifi/rx.yaml | 31 ++ common_patches/wifi/rx_filter_masked.yaml | 63 ++++ common_patches/wifi/tx.yaml | 150 ++++++++ esp32/src/wifi.rs | 353 +++++++++++------- esp32/src/wifi/crypto_key_entry.rs | 28 -- esp32/src/wifi/crypto_key_entry/addr_high.rs | 92 ----- .../wifi/{tx_slot_parameters => }/duration.rs | 6 +- esp32/src/wifi/filter_bank.rs | 32 +- .../wifi/{tx_slot_parameters => }/ht_sig.rs | 6 +- .../{tx_slot_parameters => }/ht_unknown.rs | 6 +- esp32/src/wifi/interface_rx_control.rs | 77 ++++ esp32/src/wifi/mac_interrupt.rs | 27 ++ .../{ => mac_interrupt}/wifi_int_clear.rs | 0 .../src/wifi/mac_interrupt/wifi_int_status.rs | 28 ++ .../wifi/{tx_slot_parameters => }/plcp1.rs | 58 ++- .../wifi/{tx_slot_parameters => }/plcp2.rs | 6 +- .../src/wifi/{tx_slot_parameters => }/pmd.rs | 6 +- esp32/src/wifi/rx_dma_list.rs | 37 ++ .../wifi/{ => rx_dma_list}/rx_descr_base.rs | 0 .../wifi/{ => rx_dma_list}/rx_descr_last.rs | 0 .../wifi/{ => rx_dma_list}/rx_descr_next.rs | 0 esp32/src/wifi/tx_slot_config/config.rs | 53 ++- esp32/src/wifi/tx_slot_config/plcp0.rs | 52 ++- esp32/src/wifi/tx_slot_parameters.rs | 69 ---- esp32/src/wifi/txq_state.rs | 47 +++ .../wifi/{ => txq_state}/tx_complete_clear.rs | 0 .../{ => txq_state}/tx_complete_status.rs | 0 .../wifi/{ => txq_state}/tx_error_clear.rs | 0 .../wifi/{ => txq_state}/tx_error_status.rs | 0 esp32/src/wifi/unknown_rx_policy.rs | 28 -- esp32/src/wifi/wifi_int_status.rs | 77 ---- esp32/svd/patches/esp32-wifi.yaml | 270 +++----------- esp32s2/src/lib.rs | 49 +++ esp32s2/src/wifi.rs | 315 ++++++++++++++++ esp32s2/src/wifi/ctrl.rs | 28 ++ esp32s2/src/wifi/duration.rs | 28 ++ esp32s2/src/wifi/filter_bank.rs | 119 ++++++ esp32s2/src/wifi/filter_bank/addr_high.rs | 47 +++ .../src/wifi/filter_bank}/addr_low.rs | 8 +- esp32s2/src/wifi/filter_bank/mask_high.rs | 62 +++ esp32s2/src/wifi/filter_bank/mask_low.rs | 28 ++ esp32s2/src/wifi/ht_sig.rs | 28 ++ esp32s2/src/wifi/ht_unknown.rs | 47 +++ esp32s2/src/wifi/interface_rx_control.rs | 77 ++++ esp32s2/src/wifi/mac_interrupt.rs | 27 ++ .../src/wifi/mac_interrupt/wifi_int_clear.rs | 28 ++ .../src/wifi/mac_interrupt/wifi_int_status.rs | 28 ++ esp32s2/src/wifi/plcp1.rs | 122 ++++++ esp32s2/src/wifi/plcp2.rs | 47 +++ esp32s2/src/wifi/pmd.rs | 28 ++ esp32s2/src/wifi/pwr_interrupt.rs | 27 ++ .../src/wifi/pwr_interrupt/pwr_int_clear.rs | 28 ++ .../src/wifi/pwr_interrupt/pwr_int_status.rs | 28 ++ esp32s2/src/wifi/rx_ctrl.rs | 62 +++ esp32s2/src/wifi/rx_dma_list.rs | 37 ++ esp32s2/src/wifi/rx_dma_list/rx_descr_base.rs | 28 ++ esp32s2/src/wifi/rx_dma_list/rx_descr_last.rs | 28 ++ esp32s2/src/wifi/rx_dma_list/rx_descr_next.rs | 28 ++ esp32s2/src/wifi/tx_slot_config.rs | 27 ++ esp32s2/src/wifi/tx_slot_config/config.rs | 77 ++++ esp32s2/src/wifi/tx_slot_config/plcp0.rs | 92 +++++ esp32s2/src/wifi/txq_state.rs | 47 +++ .../src/wifi/txq_state/tx_complete_clear.rs | 47 +++ .../src/wifi/txq_state/tx_complete_status.rs | 47 +++ esp32s2/src/wifi/txq_state/tx_error_clear.rs | 62 +++ esp32s2/src/wifi/txq_state/tx_error_status.rs | 62 +++ esp32s2/svd/patches/esp32s2-wifi.yaml | 96 +++++ esp32s2/svd/patches/esp32s2.yaml | 2 + 70 files changed, 2867 insertions(+), 703 deletions(-) create mode 100644 common_patches/wifi/mac_interrupt.yaml create mode 100644 common_patches/wifi/pwr_interrupt.yaml create mode 100644 common_patches/wifi/rx.yaml create mode 100644 common_patches/wifi/rx_filter_masked.yaml create mode 100644 common_patches/wifi/tx.yaml delete mode 100644 esp32/src/wifi/crypto_key_entry.rs delete mode 100644 esp32/src/wifi/crypto_key_entry/addr_high.rs rename esp32/src/wifi/{tx_slot_parameters => }/duration.rs (89%) rename esp32/src/wifi/{tx_slot_parameters => }/ht_sig.rs (90%) rename esp32/src/wifi/{tx_slot_parameters => }/ht_unknown.rs (93%) create mode 100644 esp32/src/wifi/interface_rx_control.rs create mode 100644 esp32/src/wifi/mac_interrupt.rs rename esp32/src/wifi/{ => mac_interrupt}/wifi_int_clear.rs (100%) create mode 100644 esp32/src/wifi/mac_interrupt/wifi_int_status.rs rename esp32/src/wifi/{tx_slot_parameters => }/plcp1.rs (58%) rename esp32/src/wifi/{tx_slot_parameters => }/plcp2.rs (93%) rename esp32/src/wifi/{tx_slot_parameters => }/pmd.rs (90%) create mode 100644 esp32/src/wifi/rx_dma_list.rs rename esp32/src/wifi/{ => rx_dma_list}/rx_descr_base.rs (100%) rename esp32/src/wifi/{ => rx_dma_list}/rx_descr_last.rs (100%) rename esp32/src/wifi/{ => rx_dma_list}/rx_descr_next.rs (100%) delete mode 100644 esp32/src/wifi/tx_slot_parameters.rs create mode 100644 esp32/src/wifi/txq_state.rs rename esp32/src/wifi/{ => txq_state}/tx_complete_clear.rs (100%) rename esp32/src/wifi/{ => txq_state}/tx_complete_status.rs (100%) rename esp32/src/wifi/{ => txq_state}/tx_error_clear.rs (100%) rename esp32/src/wifi/{ => txq_state}/tx_error_status.rs (100%) delete mode 100644 esp32/src/wifi/unknown_rx_policy.rs delete mode 100644 esp32/src/wifi/wifi_int_status.rs create mode 100644 esp32s2/src/wifi.rs create mode 100644 esp32s2/src/wifi/ctrl.rs create mode 100644 esp32s2/src/wifi/duration.rs create mode 100644 esp32s2/src/wifi/filter_bank.rs create mode 100644 esp32s2/src/wifi/filter_bank/addr_high.rs rename {esp32/src/wifi/crypto_key_entry => esp32s2/src/wifi/filter_bank}/addr_low.rs (59%) create mode 100644 esp32s2/src/wifi/filter_bank/mask_high.rs create mode 100644 esp32s2/src/wifi/filter_bank/mask_low.rs create mode 100644 esp32s2/src/wifi/ht_sig.rs create mode 100644 esp32s2/src/wifi/ht_unknown.rs create mode 100644 esp32s2/src/wifi/interface_rx_control.rs create mode 100644 esp32s2/src/wifi/mac_interrupt.rs create mode 100644 esp32s2/src/wifi/mac_interrupt/wifi_int_clear.rs create mode 100644 esp32s2/src/wifi/mac_interrupt/wifi_int_status.rs create mode 100644 esp32s2/src/wifi/plcp1.rs create mode 100644 esp32s2/src/wifi/plcp2.rs create mode 100644 esp32s2/src/wifi/pmd.rs create mode 100644 esp32s2/src/wifi/pwr_interrupt.rs create mode 100644 esp32s2/src/wifi/pwr_interrupt/pwr_int_clear.rs create mode 100644 esp32s2/src/wifi/pwr_interrupt/pwr_int_status.rs create mode 100644 esp32s2/src/wifi/rx_ctrl.rs create mode 100644 esp32s2/src/wifi/rx_dma_list.rs create mode 100644 esp32s2/src/wifi/rx_dma_list/rx_descr_base.rs create mode 100644 esp32s2/src/wifi/rx_dma_list/rx_descr_last.rs create mode 100644 esp32s2/src/wifi/rx_dma_list/rx_descr_next.rs create mode 100644 esp32s2/src/wifi/tx_slot_config.rs create mode 100644 esp32s2/src/wifi/tx_slot_config/config.rs create mode 100644 esp32s2/src/wifi/tx_slot_config/plcp0.rs create mode 100644 esp32s2/src/wifi/txq_state.rs create mode 100644 esp32s2/src/wifi/txq_state/tx_complete_clear.rs create mode 100644 esp32s2/src/wifi/txq_state/tx_complete_status.rs create mode 100644 esp32s2/src/wifi/txq_state/tx_error_clear.rs create mode 100644 esp32s2/src/wifi/txq_state/tx_error_status.rs create mode 100644 esp32s2/svd/patches/esp32s2-wifi.yaml diff --git a/common_patches/wifi/mac_interrupt.yaml b/common_patches/wifi/mac_interrupt.yaml new file mode 100644 index 000000000..2d3b8d044 --- /dev/null +++ b/common_patches/wifi/mac_interrupt.yaml @@ -0,0 +1,14 @@ +WIFI: + MAC_INTERRUPT: + _delete: DUMMY + _add: + WIFI_INT_STATUS: + addressOffset: 0x0 + description: Interrupt status of WIFI peripheral + access: read + + WIFI_INT_CLEAR: + addressOffset: 0x4 + description: Interrupt status clear of WIFI peripheral + access: write + diff --git a/common_patches/wifi/pwr_interrupt.yaml b/common_patches/wifi/pwr_interrupt.yaml new file mode 100644 index 000000000..cc9ab0066 --- /dev/null +++ b/common_patches/wifi/pwr_interrupt.yaml @@ -0,0 +1,13 @@ +WIFI: + PWR_INTERRUPT: + _delete: DUMMY + _add: + PWR_INT_STATUS: + addressOffset: 0x0 + description: Interrupt status for the WIFI_PWR interrupt + access: read + + PWR_INT_CLEAR: + addressOffset: 0x4 + description: Interrupt status clear for the WIFI_PWR interrupt + access: write diff --git a/common_patches/wifi/rx.yaml b/common_patches/wifi/rx.yaml new file mode 100644 index 000000000..428e0477a --- /dev/null +++ b/common_patches/wifi/rx.yaml @@ -0,0 +1,31 @@ +WIFI: + _modify: + RX_CTRL: + description: Controls the reception of frames + access: read-write + fields: + RX_DESCR_RELOAD: + bitOffset: 0 + bitWidth: 1 + description: Instruct the hardware to reload the RX descriptors + RX_ENABLE: + bitOffset: 31 + bitWidth: 1 + description: Enable frame reception + RX_DMA_LIST: + _delete: DUMMY + _add: + RX_DESCR_BASE: + description: base address of the RX DMA list + addressOffset: 0x0 + acccess: read-write + + RX_DESCR_NEXT: + description: next item in the RX DMA list + addressOffset: 0x4 + access: read-write + + RX_DESCR_LAST: + description: last item in RX DMA list + addressOffset: 0x8 + access: read-write diff --git a/common_patches/wifi/rx_filter_masked.yaml b/common_patches/wifi/rx_filter_masked.yaml new file mode 100644 index 000000000..d007f5df5 --- /dev/null +++ b/common_patches/wifi/rx_filter_masked.yaml @@ -0,0 +1,63 @@ +WIFI: + _modify: + INTERFACE_RX_CONTROL%s: + acccess: read-write + description: Controls RX for an interface + fields: + BSSID_CHECK: + bitOffset: 1 + bitWidth: 1 + access: read-write + description: Check BSSID for filtering + SCAN_MODE: + bitOffset: 4 + bitWidth: 1 + access: read-write + description: Receive beacon frames + DATA_AND_MGMT_MODE: + bitOffset: 8 + bitWidth: 1 + access: read-write + description: Receive everything except control frames + FILTER_BANK%s: + _delete: DUMMY + _add: + ADDR_LOW%s: + dim: 4 + dimIncrement: 0x8 + description: First 4 bytes of BSSID MAC address filter + addressOffset: 0x0 + access: read-write + ADDR_HIGH%s: + dim: 4 + dimIncrement: 0x8 + description: last 2 bytes of BSSID MAC address filter + addressOffset: 0x4 + access: read-write + fields: + ADDR: + bitOffset: 0 + bitWidth: 16 + access: read-write + MASK_LOW%s: + dim: 4 + dimIncrement: 0x8 + description: First 4 bytes of BSSID MAC address filter mask + addressOffset: 0x20 + access: read-write + MASK_HIGH%s: + dim: 4 + dimIncrement: 0x8 + description: last 2 bytes of BSSID MAC address filter mask + addressOffset: 0x24 + access: read-write + fields: + MASK: + bitOffset: 0 + bitWidth: 16 + access: read-write + ENABLED: + bitOffset: 16 + bitWidth: 1 + access: read-write + diff --git a/common_patches/wifi/tx.yaml b/common_patches/wifi/tx.yaml new file mode 100644 index 000000000..44bfacf90 --- /dev/null +++ b/common_patches/wifi/tx.yaml @@ -0,0 +1,150 @@ +WIFI: + TXQ_STATE: + _delete: DUMMY + _add: + TX_ERROR_CLEAR: + description: Clear the error status of a slot + addressOffset: 0x0 + access: write + fields: + SLOT_COLLISION: + bitOffset: 0 + bitWidth: 5 + SLOT_TIMEOUT: + bitOffset: 0x10 + bitWidth: 5 + + TX_ERROR_STATUS: + description: Error status of a slot + addressOffset: 0x4 + access: read + fields: + SLOT_COLLISION: + bitOffset: 0 + bitWidth: 5 + SLOT_TIMEOUT: + bitOffset: 0x10 + bitWidth: 5 + + TX_COMPLETE_CLEAR: + description: Clear the completion status of a slot + addressOffset: 0x8 + access: write + fields: + SLOTS: + bitOffset: 0 + bitWidth: 5 + + TX_COMPLETE_STATUS: + description: Completion status of a slot + addressOffset: 0xc + access: read + fields: + SLOTS: + bitOffset: 0 + bitWidth: 5 + TX_SLOT_CONFIG%s: + _delete: DUMMY + _add: + CONFIG: + description: Config + addressOffset: 0x0 + access: read-write + fields: + TIMEOUT: + bitOffset: 0 + bitWidth: 12 + access: read-write + BACKOFF_TIME: + bitOffset: 12 + bitWidth: 10 + access: read-write + AIFSN: + bitOffset: 24 + bitWidth: 4 + access: read-write + PLCP0: + description: PLCP0 + addressOffset: 0x4 + access: read-write + fields: + DMA_ADDR: + description: Bottom bits of address of dma_item + bitOffset: 0 + bitWidth: 20 + access: read-write + WAIT_FOR_ACK: + description: Enables ACK timeouts + bitOffset: 28 + bitWidth: 1 + access: read-write + SLOT_VALID: + description: Marks this slot as valid + bitOffset: 30 + bitWidth: 1 + access: read-write + SLOT_ENABLED: + description: Marks this slot as ready for transmission + bitOffset: 31 + bitWidth: 1 + access: read-write + _modify: + PLCP1%s: + description: PLCP1 + access: read-write + fields: + LEN: + description: Length of packet (in bytes) + bitOffset: 0 + bitWidth: 12 + access: read-write + RATE: + description: Packet rate (see wifi_phy_rate_t) + bitOffset: 12 + bitWidth: 5 + access: read-write + KEY_SLOT_ID: + description: Key slot to use for encryption + bitOffset: 17 + bitWidth: 5 + access: read-write + IS_80211_N: + description: Bit indicating if this is 802.11n + bitOffset: 25 + bitWidth: 1 + access: read-write + BANDWIDTH: + description: Zero indicates 20MHz and one indicates 40MHz + bitOffset: 28 + bitWidth: 1 + access: read-write + INTERFACE_ID: + description: ID of the interface this transmission is from + bitOffset: 30 + bitWidth: 2 + access: read-write + PLCP2%s: + description: PLCP2 + access: read-write + fields: + UNKNOWN: + description: meaning unknown, set to one for TX + bitOffset: 5 + bitWidth: 1 + HT_SIG%s: + description: HT-SIG field in HT preamble + access: read-write + HT_UNKNOWN%s: + description: exact meaning and name unknown, related to HT + access: read-write + fields: + LENGTH: + description: The length of the PPDU + bitOffset: 0x0 + bitWidth: 20 + access: write + DURATION%s: + description: duration of the frame exchange + access: read-write + PMD%s: + access: read-write diff --git a/esp32/src/wifi.rs b/esp32/src/wifi.rs index 9f602c531..4b2d0b639 100644 --- a/esp32/src/wifi.rs +++ b/esp32/src/wifi.rs @@ -5,34 +5,28 @@ pub struct RegisterBlock { filter_bank: [FILTER_BANK; 2], _reserved1: [u8; 0x04], rx_ctrl: RX_CTRL, - rx_descr_base: RX_DESCR_BASE, - rx_descr_next: RX_DESCR_NEXT, - rx_descr_last: RX_DESCR_LAST, - _reserved5: [u8; 0x44], - unknown_rx_policy: [UNKNOWN_RX_POLICY; 2], - _reserved6: [u8; 0x01dc], + rx_dma_list: RX_DMA_LIST, + _reserved3: [u8; 0x44], + interface_rx_control: [INTERFACE_RX_CONTROL; 4], + _reserved4: [u8; 0x01d4], hw_stat_ack_int: HW_STAT_ACK_INT, hw_stat_rts_int: HW_STAT_RTS_INT, hw_stat_cts_int: HW_STAT_CTS_INT, hw_stat_rifs_int: HW_STAT_RIFS_INT, hw_stat_rx_success: HW_STAT_RX_SUCCESS, hw_stat_rx_end: HW_STAT_RX_END, - _reserved12: [u8; 0x04], + _reserved10: [u8; 0x04], hw_stat_hop_err: HW_STAT_HOP_ERR, hw_stat_full2: HW_STAT_FULL2, hw_stat_block_err: HW_STAT_BLOCK_ERR, - _reserved15: [u8; 0x0964], - wifi_int_status: WIFI_INT_STATUS, - wifi_int_clear: WIFI_INT_CLEAR, - _reserved17: [u8; 0x68], + _reserved13: [u8; 0x0964], + mac_interrupt: MAC_INTERRUPT, + _reserved14: [u8; 0x68], ctrl: CTRL, - tx_error_clear: TX_ERROR_CLEAR, - tx_error_status: TX_ERROR_STATUS, - tx_complete_clear: TX_COMPLETE_CLEAR, - tx_complete_status: TX_COMPLETE_STATUS, - _reserved22: [u8; 0x30], + txq_state: TXQ_STATE, + _reserved16: [u8; 0x30], tx_slot_config: [TX_SLOT_CONFIG; 5], - _reserved23: [u8; 0x34], + _reserved17: [u8; 0x34], hw_stat_tx_rts: HW_STAT_TX_RTS, hw_stat_tx_cts: HW_STAT_TX_CTS, hw_stat_tx_ack: HW_STAT_TX_ACK, @@ -40,10 +34,18 @@ pub struct RegisterBlock { hw_stat_trigger: HW_STAT_TRIGGER, hw_stat_tx_hung: HW_STAT_TX_HUNG, hw_stat_panic: HW_STAT_PANIC, - _reserved30: [u8; 0x03f4], - tx_slot_parameters: [TX_SLOT_PARAMETERS; 5], - _reserved31: [u8; 0x016c], - crypto_key_entry: [CRYPTO_KEY_ENTRY; 16], + _reserved24: [u8; 0x03f4], + plcp1: (), + _reserved25: [u8; 0x04], + plcp2: (), + _reserved26: [u8; 0x04], + ht_sig: (), + _reserved27: [u8; 0x04], + ht_unknown: (), + _reserved28: [u8; 0x04], + duration: (), + _reserved29: [u8; 0x08], + pmd: (), } impl RegisterBlock { #[doc = "0x00..0x80 - Filter banks for frame reception. Bank zero is for the BSSID and bank one for the RA. Each filter bank has registers for two interfaces."] @@ -62,31 +64,21 @@ impl RegisterBlock { pub const fn rx_ctrl(&self) -> &RX_CTRL { &self.rx_ctrl } - #[doc = "0x88 - base address of the RX DMA list"] + #[doc = "0x88..0x94 - RX_DMA_LIST"] #[inline(always)] - pub const fn rx_descr_base(&self) -> &RX_DESCR_BASE { - &self.rx_descr_base + pub const fn rx_dma_list(&self) -> &RX_DMA_LIST { + &self.rx_dma_list } - #[doc = "0x8c - next item in the RX DMA list"] + #[doc = "0xd8..0xe8 - Controls RX for an interface"] #[inline(always)] - pub const fn rx_descr_next(&self) -> &RX_DESCR_NEXT { - &self.rx_descr_next - } - #[doc = "0x90 - last item in RX DMA list"] - #[inline(always)] - pub const fn rx_descr_last(&self) -> &RX_DESCR_LAST { - &self.rx_descr_last - } - #[doc = "0xd8..0xe0 - "] - #[inline(always)] - pub const fn unknown_rx_policy(&self, n: usize) -> &UNKNOWN_RX_POLICY { - &self.unknown_rx_policy[n] + pub const fn interface_rx_control(&self, n: usize) -> &INTERFACE_RX_CONTROL { + &self.interface_rx_control[n] } #[doc = "Iterator for array of:"] - #[doc = "0xd8..0xe0 - "] + #[doc = "0xd8..0xe8 - Controls RX for an interface"] #[inline(always)] - pub fn unknown_rx_policy_iter(&self) -> impl Iterator { - self.unknown_rx_policy.iter() + pub fn interface_rx_control_iter(&self) -> impl Iterator { + self.interface_rx_control.iter() } #[doc = "0x2bc - "] #[inline(always)] @@ -133,40 +125,20 @@ impl RegisterBlock { pub const fn hw_stat_block_err(&self) -> &HW_STAT_BLOCK_ERR { &self.hw_stat_block_err } - #[doc = "0xc48 - Interrupt status of WIFI peripheral"] + #[doc = "0xc48..0xc50 - Status and clear for the Wi-Fi MAC interrupt"] #[inline(always)] - pub const fn wifi_int_status(&self) -> &WIFI_INT_STATUS { - &self.wifi_int_status - } - #[doc = "0xc4c - Interrupt status clear of WIFI peripheral"] - #[inline(always)] - pub const fn wifi_int_clear(&self) -> &WIFI_INT_CLEAR { - &self.wifi_int_clear + pub const fn mac_interrupt(&self) -> &MAC_INTERRUPT { + &self.mac_interrupt } #[doc = "0xcb8 - Exact name and meaning unknown, used for initializing the MAC"] #[inline(always)] pub const fn ctrl(&self) -> &CTRL { &self.ctrl } - #[doc = "0xcbc - Clear the error status of a slot"] - #[inline(always)] - pub const fn tx_error_clear(&self) -> &TX_ERROR_CLEAR { - &self.tx_error_clear - } - #[doc = "0xcc0 - Error status of a slot"] - #[inline(always)] - pub const fn tx_error_status(&self) -> &TX_ERROR_STATUS { - &self.tx_error_status - } - #[doc = "0xcc4 - Clear the completion status of a slot"] + #[doc = "0xcbc..0xccc - State of transmission queues"] #[inline(always)] - pub const fn tx_complete_clear(&self) -> &TX_COMPLETE_CLEAR { - &self.tx_complete_clear - } - #[doc = "0xcc8 - Completion status of a slot"] - #[inline(always)] - pub const fn tx_complete_status(&self) -> &TX_COMPLETE_STATUS { - &self.tx_complete_status + pub const fn txq_state(&self) -> &TXQ_STATE { + &self.txq_state } #[doc = "0xcfc..0xd24 - Used to configure the TX slot."] #[inline(always)] @@ -214,49 +186,165 @@ impl RegisterBlock { pub const fn hw_stat_panic(&self) -> &HW_STAT_PANIC { &self.hw_stat_panic } - #[doc = "0x1168..0x1294 - Used to set transmission parameters for the slot"] + #[doc = "0x1168..0x117c - PLCP1"] #[inline(always)] - pub const fn tx_slot_parameters(&self, n: usize) -> &TX_SLOT_PARAMETERS { - &self.tx_slot_parameters[n] + pub const fn plcp1(&self, n: usize) -> &PLCP1 { + #[allow(clippy::no_effect)] + [(); 5][n]; + unsafe { + &*core::ptr::from_ref(self) + .cast::() + .add(4456) + .add(60 * n) + .cast() + } } #[doc = "Iterator for array of:"] - #[doc = "0x1168..0x1294 - Used to set transmission parameters for the slot"] - #[inline(always)] - pub fn tx_slot_parameters_iter(&self) -> impl Iterator { - self.tx_slot_parameters.iter() + #[doc = "0x1168..0x117c - PLCP1"] + #[inline(always)] + pub fn plcp1_iter(&self) -> impl Iterator { + (0..5).map(move |n| unsafe { + &*core::ptr::from_ref(self) + .cast::() + .add(4456) + .add(60 * n) + .cast() + }) + } + #[doc = "0x116c..0x1180 - PLCP2"] + #[inline(always)] + pub const fn plcp2(&self, n: usize) -> &PLCP2 { + #[allow(clippy::no_effect)] + [(); 5][n]; + unsafe { + &*core::ptr::from_ref(self) + .cast::() + .add(4460) + .add(60 * n) + .cast() + } } - #[doc = "0x1400..0x1680 - The cryptographic keys, to be used by the MAC"] - #[inline(always)] - pub const fn crypto_key_entry(&self, n: usize) -> &CRYPTO_KEY_ENTRY { - &self.crypto_key_entry[n] + #[doc = "Iterator for array of:"] + #[doc = "0x116c..0x1180 - PLCP2"] + #[inline(always)] + pub fn plcp2_iter(&self) -> impl Iterator { + (0..5).map(move |n| unsafe { + &*core::ptr::from_ref(self) + .cast::() + .add(4460) + .add(60 * n) + .cast() + }) + } + #[doc = "0x1170..0x1184 - HT-SIG field in HT preamble"] + #[inline(always)] + pub const fn ht_sig(&self, n: usize) -> &HT_SIG { + #[allow(clippy::no_effect)] + [(); 5][n]; + unsafe { + &*core::ptr::from_ref(self) + .cast::() + .add(4464) + .add(60 * n) + .cast() + } + } + #[doc = "Iterator for array of:"] + #[doc = "0x1170..0x1184 - HT-SIG field in HT preamble"] + #[inline(always)] + pub fn ht_sig_iter(&self) -> impl Iterator { + (0..5).map(move |n| unsafe { + &*core::ptr::from_ref(self) + .cast::() + .add(4464) + .add(60 * n) + .cast() + }) + } + #[doc = "0x1174..0x1188 - exact meaning and name unknown, related to HT"] + #[inline(always)] + pub const fn ht_unknown(&self, n: usize) -> &HT_UNKNOWN { + #[allow(clippy::no_effect)] + [(); 5][n]; + unsafe { + &*core::ptr::from_ref(self) + .cast::() + .add(4468) + .add(60 * n) + .cast() + } + } + #[doc = "Iterator for array of:"] + #[doc = "0x1174..0x1188 - exact meaning and name unknown, related to HT"] + #[inline(always)] + pub fn ht_unknown_iter(&self) -> impl Iterator { + (0..5).map(move |n| unsafe { + &*core::ptr::from_ref(self) + .cast::() + .add(4468) + .add(60 * n) + .cast() + }) + } + #[doc = "0x1178..0x118c - duration of the frame exchange"] + #[inline(always)] + pub const fn duration(&self, n: usize) -> &DURATION { + #[allow(clippy::no_effect)] + [(); 5][n]; + unsafe { + &*core::ptr::from_ref(self) + .cast::() + .add(4472) + .add(60 * n) + .cast() + } + } + #[doc = "Iterator for array of:"] + #[doc = "0x1178..0x118c - duration of the frame exchange"] + #[inline(always)] + pub fn duration_iter(&self) -> impl Iterator { + (0..5).map(move |n| unsafe { + &*core::ptr::from_ref(self) + .cast::() + .add(4472) + .add(60 * n) + .cast() + }) + } + #[doc = "0x1180..0x1194 - "] + #[inline(always)] + pub const fn pmd(&self, n: usize) -> &PMD { + #[allow(clippy::no_effect)] + [(); 5][n]; + unsafe { + &*core::ptr::from_ref(self) + .cast::() + .add(4480) + .add(60 * n) + .cast() + } } #[doc = "Iterator for array of:"] - #[doc = "0x1400..0x1680 - The cryptographic keys, to be used by the MAC"] + #[doc = "0x1180..0x1194 - "] #[inline(always)] - pub fn crypto_key_entry_iter(&self) -> impl Iterator { - self.crypto_key_entry.iter() + pub fn pmd_iter(&self) -> impl Iterator { + (0..5).map(move |n| unsafe { + &*core::ptr::from_ref(self) + .cast::() + .add(4480) + .add(60 * n) + .cast() + }) } } #[doc = "RX_CTRL (rw) register accessor: Controls the reception of frames\n\nYou can [`read`](crate::Reg::read) this register and get [`rx_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_ctrl`] module"] pub type RX_CTRL = crate::Reg; #[doc = "Controls the reception of frames"] pub mod rx_ctrl; -#[doc = "RX_DESCR_BASE (rw) register accessor: base address of the RX DMA list\n\nYou can [`read`](crate::Reg::read) this register and get [`rx_descr_base::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx_descr_base::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_descr_base`] module"] -pub type RX_DESCR_BASE = crate::Reg; -#[doc = "base address of the RX DMA list"] -pub mod rx_descr_base; -#[doc = "RX_DESCR_NEXT (rw) register accessor: next item in the RX DMA list\n\nYou can [`read`](crate::Reg::read) this register and get [`rx_descr_next::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx_descr_next::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_descr_next`] module"] -pub type RX_DESCR_NEXT = crate::Reg; -#[doc = "next item in the RX DMA list"] -pub mod rx_descr_next; -#[doc = "RX_DESCR_LAST (rw) register accessor: last item in RX DMA list\n\nYou can [`read`](crate::Reg::read) this register and get [`rx_descr_last::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx_descr_last::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_descr_last`] module"] -pub type RX_DESCR_LAST = crate::Reg; -#[doc = "last item in RX DMA list"] -pub mod rx_descr_last; -#[doc = "UNKNOWN_RX_POLICY (rw) register accessor: \n\nYou can [`read`](crate::Reg::read) this register and get [`unknown_rx_policy::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`unknown_rx_policy::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@unknown_rx_policy`] module"] -pub type UNKNOWN_RX_POLICY = crate::Reg; -#[doc = ""] -pub mod unknown_rx_policy; +#[doc = "INTERFACE_RX_CONTROL (rw) register accessor: Controls RX for an interface\n\nYou can [`read`](crate::Reg::read) this register and get [`interface_rx_control::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interface_rx_control::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@interface_rx_control`] module"] +pub type INTERFACE_RX_CONTROL = crate::Reg; +#[doc = "Controls RX for an interface"] +pub mod interface_rx_control; #[doc = "HW_STAT_ACK_INT (rw) register accessor: \n\nYou can [`read`](crate::Reg::read) this register and get [`hw_stat_ack_int::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hw_stat_ack_int::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hw_stat_ack_int`] module"] pub type HW_STAT_ACK_INT = crate::Reg; #[doc = ""] @@ -293,34 +381,34 @@ pub mod hw_stat_full2; pub type HW_STAT_BLOCK_ERR = crate::Reg; #[doc = ""] pub mod hw_stat_block_err; -#[doc = "WIFI_INT_STATUS (rw) register accessor: Interrupt status of WIFI peripheral\n\nYou can [`read`](crate::Reg::read) this register and get [`wifi_int_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wifi_int_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wifi_int_status`] module"] -pub type WIFI_INT_STATUS = crate::Reg; -#[doc = "Interrupt status of WIFI peripheral"] -pub mod wifi_int_status; -#[doc = "WIFI_INT_CLEAR (rw) register accessor: Interrupt status clear of WIFI peripheral\n\nYou can [`read`](crate::Reg::read) this register and get [`wifi_int_clear::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wifi_int_clear::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wifi_int_clear`] module"] -pub type WIFI_INT_CLEAR = crate::Reg; -#[doc = "Interrupt status clear of WIFI peripheral"] -pub mod wifi_int_clear; #[doc = "CTRL (rw) register accessor: Exact name and meaning unknown, used for initializing the MAC\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`] module"] pub type CTRL = crate::Reg; #[doc = "Exact name and meaning unknown, used for initializing the MAC"] pub mod ctrl; -#[doc = "TX_ERROR_CLEAR (rw) register accessor: Clear the error status of a slot\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_error_clear::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_error_clear::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_error_clear`] module"] -pub type TX_ERROR_CLEAR = crate::Reg; -#[doc = "Clear the error status of a slot"] -pub mod tx_error_clear; -#[doc = "TX_ERROR_STATUS (rw) register accessor: Error status of a slot\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_error_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_error_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_error_status`] module"] -pub type TX_ERROR_STATUS = crate::Reg; -#[doc = "Error status of a slot"] -pub mod tx_error_status; -#[doc = "TX_COMPLETE_CLEAR (rw) register accessor: Clear the completion status of a slot\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_complete_clear::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_complete_clear::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_complete_clear`] module"] -pub type TX_COMPLETE_CLEAR = crate::Reg; -#[doc = "Clear the completion status of a slot"] -pub mod tx_complete_clear; -#[doc = "TX_COMPLETE_STATUS (rw) register accessor: Completion status of a slot\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_complete_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_complete_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_complete_status`] module"] -pub type TX_COMPLETE_STATUS = crate::Reg; -#[doc = "Completion status of a slot"] -pub mod tx_complete_status; +#[doc = "PLCP1 (rw) register accessor: PLCP1\n\nYou can [`read`](crate::Reg::read) this register and get [`plcp1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`plcp1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@plcp1`] module"] +pub type PLCP1 = crate::Reg; +#[doc = "PLCP1"] +pub mod plcp1; +#[doc = "PLCP2 (rw) register accessor: PLCP2\n\nYou can [`read`](crate::Reg::read) this register and get [`plcp2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`plcp2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@plcp2`] module"] +pub type PLCP2 = crate::Reg; +#[doc = "PLCP2"] +pub mod plcp2; +#[doc = "HT_SIG (rw) register accessor: HT-SIG field in HT preamble\n\nYou can [`read`](crate::Reg::read) this register and get [`ht_sig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ht_sig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ht_sig`] module"] +pub type HT_SIG = crate::Reg; +#[doc = "HT-SIG field in HT preamble"] +pub mod ht_sig; +#[doc = "HT_UNKNOWN (rw) register accessor: exact meaning and name unknown, related to HT\n\nYou can [`read`](crate::Reg::read) this register and get [`ht_unknown::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ht_unknown::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ht_unknown`] module"] +pub type HT_UNKNOWN = crate::Reg; +#[doc = "exact meaning and name unknown, related to HT"] +pub mod ht_unknown; +#[doc = "DURATION (rw) register accessor: duration of the frame exchange\n\nYou can [`read`](crate::Reg::read) this register and get [`duration::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`duration::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@duration`] module"] +pub type DURATION = crate::Reg; +#[doc = "duration of the frame exchange"] +pub mod duration; +#[doc = "PMD (rw) register accessor: \n\nYou can [`read`](crate::Reg::read) this register and get [`pmd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pmd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pmd`] module"] +pub type PMD = crate::Reg; +#[doc = ""] +pub mod pmd; #[doc = "HW_STAT_TX_RTS (rw) register accessor: \n\nYou can [`read`](crate::Reg::read) this register and get [`hw_stat_tx_rts::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hw_stat_tx_rts::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hw_stat_tx_rts`] module"] pub type HW_STAT_TX_RTS = crate::Reg; #[doc = ""] @@ -354,18 +442,23 @@ pub use self::filter_bank::FILTER_BANK; #[doc = r"Cluster"] #[doc = "Filter banks for frame reception. Bank zero is for the BSSID and bank one for the RA. Each filter bank has registers for two interfaces."] pub mod filter_bank; +#[doc = "RX_DMA_LIST"] +pub use self::rx_dma_list::RX_DMA_LIST; +#[doc = r"Cluster"] +#[doc = "RX_DMA_LIST"] +pub mod rx_dma_list; +#[doc = "Status and clear for the Wi-Fi MAC interrupt"] +pub use self::mac_interrupt::MAC_INTERRUPT; +#[doc = r"Cluster"] +#[doc = "Status and clear for the Wi-Fi MAC interrupt"] +pub mod mac_interrupt; +#[doc = "State of transmission queues"] +pub use self::txq_state::TXQ_STATE; +#[doc = r"Cluster"] +#[doc = "State of transmission queues"] +pub mod txq_state; #[doc = "Used to configure the TX slot."] pub use self::tx_slot_config::TX_SLOT_CONFIG; #[doc = r"Cluster"] #[doc = "Used to configure the TX slot."] pub mod tx_slot_config; -#[doc = "Used to set transmission parameters for the slot"] -pub use self::tx_slot_parameters::TX_SLOT_PARAMETERS; -#[doc = r"Cluster"] -#[doc = "Used to set transmission parameters for the slot"] -pub mod tx_slot_parameters; -#[doc = "The cryptographic keys, to be used by the MAC"] -pub use self::crypto_key_entry::CRYPTO_KEY_ENTRY; -#[doc = r"Cluster"] -#[doc = "The cryptographic keys, to be used by the MAC"] -pub mod crypto_key_entry; diff --git a/esp32/src/wifi/crypto_key_entry.rs b/esp32/src/wifi/crypto_key_entry.rs deleted file mode 100644 index 0c503284b..000000000 --- a/esp32/src/wifi/crypto_key_entry.rs +++ /dev/null @@ -1,28 +0,0 @@ -#[repr(C)] -#[cfg_attr(feature = "impl-register-debug", derive(Debug))] -#[doc = "The cryptographic keys, to be used by the MAC"] -pub struct CRYPTO_KEY_ENTRY { - addr_low: ADDR_LOW, - addr_high: ADDR_HIGH, - _reserved_end: [u8; 0x20], -} -impl CRYPTO_KEY_ENTRY { - #[doc = "0x00 - "] - #[inline(always)] - pub const fn addr_low(&self) -> &ADDR_LOW { - &self.addr_low - } - #[doc = "0x04 - "] - #[inline(always)] - pub const fn addr_high(&self) -> &ADDR_HIGH { - &self.addr_high - } -} -#[doc = "ADDR_LOW (rw) register accessor: \n\nYou can [`read`](crate::Reg::read) this register and get [`addr_low::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`addr_low::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@addr_low`] module"] -pub type ADDR_LOW = crate::Reg; -#[doc = ""] -pub mod addr_low; -#[doc = "ADDR_HIGH (rw) register accessor: \n\nYou can [`read`](crate::Reg::read) this register and get [`addr_high::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`addr_high::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@addr_high`] module"] -pub type ADDR_HIGH = crate::Reg; -#[doc = ""] -pub mod addr_high; diff --git a/esp32/src/wifi/crypto_key_entry/addr_high.rs b/esp32/src/wifi/crypto_key_entry/addr_high.rs deleted file mode 100644 index e5fe437e9..000000000 --- a/esp32/src/wifi/crypto_key_entry/addr_high.rs +++ /dev/null @@ -1,92 +0,0 @@ -#[doc = "Register `ADDR_HIGH` reader"] -pub type R = crate::R; -#[doc = "Register `ADDR_HIGH` writer"] -pub type W = crate::W; -#[doc = "Field `ADDR` reader - "] -pub type ADDR_R = crate::FieldReader; -#[doc = "Field `ADDR` writer - "] -pub type ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `ALGORITHM` reader - "] -pub type ALGORITHM_R = crate::FieldReader; -#[doc = "Field `ALGORITHM` writer - "] -pub type ALGORITHM_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "Field `INTERFACE` reader - "] -pub type INTERFACE_R = crate::FieldReader; -#[doc = "Field `INTERFACE` writer - "] -pub type INTERFACE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `SUPPLICANT_KEY_INDEX` reader - "] -pub type SUPPLICANT_KEY_INDEX_R = crate::FieldReader; -#[doc = "Field `SUPPLICANT_KEY_INDEX` writer - "] -pub type SUPPLICANT_KEY_INDEX_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -impl R { - #[doc = "Bits 0:15"] - #[inline(always)] - pub fn addr(&self) -> ADDR_R { - ADDR_R::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 18:20"] - #[inline(always)] - pub fn algorithm(&self) -> ALGORITHM_R { - ALGORITHM_R::new(((self.bits >> 18) & 7) as u8) - } - #[doc = "Bits 24:25"] - #[inline(always)] - pub fn interface(&self) -> INTERFACE_R { - INTERFACE_R::new(((self.bits >> 24) & 3) as u8) - } - #[doc = "Bits 30:31"] - #[inline(always)] - pub fn supplicant_key_index(&self) -> SUPPLICANT_KEY_INDEX_R { - SUPPLICANT_KEY_INDEX_R::new(((self.bits >> 30) & 3) as u8) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("ADDR_HIGH") - .field("addr", &self.addr()) - .field("algorithm", &self.algorithm()) - .field("interface", &self.interface()) - .field("supplicant_key_index", &self.supplicant_key_index()) - .finish() - } -} -impl W { - #[doc = "Bits 0:15"] - #[inline(always)] - pub fn addr(&mut self) -> ADDR_W { - ADDR_W::new(self, 0) - } - #[doc = "Bits 18:20"] - #[inline(always)] - pub fn algorithm(&mut self) -> ALGORITHM_W { - ALGORITHM_W::new(self, 18) - } - #[doc = "Bits 24:25"] - #[inline(always)] - pub fn interface(&mut self) -> INTERFACE_W { - INTERFACE_W::new(self, 24) - } - #[doc = "Bits 30:31"] - #[inline(always)] - pub fn supplicant_key_index(&mut self) -> SUPPLICANT_KEY_INDEX_W { - SUPPLICANT_KEY_INDEX_W::new(self, 30) - } -} -#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`addr_high::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`addr_high::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ADDR_HIGH_SPEC; -impl crate::RegisterSpec for ADDR_HIGH_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`addr_high::R`](R) reader structure"] -impl crate::Readable for ADDR_HIGH_SPEC {} -#[doc = "`write(|w| ..)` method takes [`addr_high::W`](W) writer structure"] -impl crate::Writable for ADDR_HIGH_SPEC { - type Safety = crate::Unsafe; - const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; -} -#[doc = "`reset()` method sets ADDR_HIGH to value 0"] -impl crate::Resettable for ADDR_HIGH_SPEC { - const RESET_VALUE: u32 = 0; -} diff --git a/esp32/src/wifi/tx_slot_parameters/duration.rs b/esp32/src/wifi/duration.rs similarity index 89% rename from esp32/src/wifi/tx_slot_parameters/duration.rs rename to esp32/src/wifi/duration.rs index 4dd9bf06c..a08a3d9a3 100644 --- a/esp32/src/wifi/tx_slot_parameters/duration.rs +++ b/esp32/src/wifi/duration.rs @@ -1,6 +1,6 @@ -#[doc = "Register `DURATION` reader"] +#[doc = "Register `DURATION%s` reader"] pub type R = crate::R; -#[doc = "Register `DURATION` writer"] +#[doc = "Register `DURATION%s` writer"] pub type W = crate::W; #[cfg(feature = "impl-register-debug")] impl core::fmt::Debug for R { @@ -22,7 +22,7 @@ impl crate::Writable for DURATION_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } -#[doc = "`reset()` method sets DURATION to value 0"] +#[doc = "`reset()` method sets DURATION%s to value 0"] impl crate::Resettable for DURATION_SPEC { const RESET_VALUE: u32 = 0; } diff --git a/esp32/src/wifi/filter_bank.rs b/esp32/src/wifi/filter_bank.rs index 72db6cbb9..52f451206 100644 --- a/esp32/src/wifi/filter_bank.rs +++ b/esp32/src/wifi/filter_bank.rs @@ -12,24 +12,24 @@ pub struct FILTER_BANK { _reserved_end: [u8; 0x1c], } impl FILTER_BANK { - #[doc = "0x00..0x08 - First 4 bytes of BSSID MAC address filter"] + #[doc = "0x00..0x10 - First 4 bytes of BSSID MAC address filter"] #[inline(always)] pub const fn addr_low(&self, n: usize) -> &ADDR_LOW { #[allow(clippy::no_effect)] - [(); 2][n]; + [(); 4][n]; unsafe { &*core::ptr::from_ref(self).cast::().add(8 * n).cast() } } #[doc = "Iterator for array of:"] - #[doc = "0x00..0x08 - First 4 bytes of BSSID MAC address filter"] + #[doc = "0x00..0x10 - First 4 bytes of BSSID MAC address filter"] #[inline(always)] pub fn addr_low_iter(&self) -> impl Iterator { - (0..2).map(move |n| unsafe { &*core::ptr::from_ref(self).cast::().add(8 * n).cast() }) + (0..4).map(move |n| unsafe { &*core::ptr::from_ref(self).cast::().add(8 * n).cast() }) } - #[doc = "0x04..0x0c - last 2 bytes of BSSID MAC address filter"] + #[doc = "0x04..0x14 - last 2 bytes of BSSID MAC address filter"] #[inline(always)] pub const fn addr_high(&self, n: usize) -> &ADDR_HIGH { #[allow(clippy::no_effect)] - [(); 2][n]; + [(); 4][n]; unsafe { &*core::ptr::from_ref(self) .cast::() @@ -39,10 +39,10 @@ impl FILTER_BANK { } } #[doc = "Iterator for array of:"] - #[doc = "0x04..0x0c - last 2 bytes of BSSID MAC address filter"] + #[doc = "0x04..0x14 - last 2 bytes of BSSID MAC address filter"] #[inline(always)] pub fn addr_high_iter(&self) -> impl Iterator { - (0..2).map(move |n| unsafe { + (0..4).map(move |n| unsafe { &*core::ptr::from_ref(self) .cast::() .add(4) @@ -50,11 +50,11 @@ impl FILTER_BANK { .cast() }) } - #[doc = "0x20..0x28 - First 4 bytes of BSSID MAC address filter mask"] + #[doc = "0x20..0x30 - First 4 bytes of BSSID MAC address filter mask"] #[inline(always)] pub const fn mask_low(&self, n: usize) -> &MASK_LOW { #[allow(clippy::no_effect)] - [(); 2][n]; + [(); 4][n]; unsafe { &*core::ptr::from_ref(self) .cast::() @@ -64,10 +64,10 @@ impl FILTER_BANK { } } #[doc = "Iterator for array of:"] - #[doc = "0x20..0x28 - First 4 bytes of BSSID MAC address filter mask"] + #[doc = "0x20..0x30 - First 4 bytes of BSSID MAC address filter mask"] #[inline(always)] pub fn mask_low_iter(&self) -> impl Iterator { - (0..2).map(move |n| unsafe { + (0..4).map(move |n| unsafe { &*core::ptr::from_ref(self) .cast::() .add(32) @@ -75,11 +75,11 @@ impl FILTER_BANK { .cast() }) } - #[doc = "0x24..0x2c - last 2 bytes of BSSID MAC address filter mask"] + #[doc = "0x24..0x34 - last 2 bytes of BSSID MAC address filter mask"] #[inline(always)] pub const fn mask_high(&self, n: usize) -> &MASK_HIGH { #[allow(clippy::no_effect)] - [(); 2][n]; + [(); 4][n]; unsafe { &*core::ptr::from_ref(self) .cast::() @@ -89,10 +89,10 @@ impl FILTER_BANK { } } #[doc = "Iterator for array of:"] - #[doc = "0x24..0x2c - last 2 bytes of BSSID MAC address filter mask"] + #[doc = "0x24..0x34 - last 2 bytes of BSSID MAC address filter mask"] #[inline(always)] pub fn mask_high_iter(&self) -> impl Iterator { - (0..2).map(move |n| unsafe { + (0..4).map(move |n| unsafe { &*core::ptr::from_ref(self) .cast::() .add(36) diff --git a/esp32/src/wifi/tx_slot_parameters/ht_sig.rs b/esp32/src/wifi/ht_sig.rs similarity index 90% rename from esp32/src/wifi/tx_slot_parameters/ht_sig.rs rename to esp32/src/wifi/ht_sig.rs index 98c75905e..9801fb009 100644 --- a/esp32/src/wifi/tx_slot_parameters/ht_sig.rs +++ b/esp32/src/wifi/ht_sig.rs @@ -1,6 +1,6 @@ -#[doc = "Register `HT_SIG` reader"] +#[doc = "Register `HT_SIG%s` reader"] pub type R = crate::R; -#[doc = "Register `HT_SIG` writer"] +#[doc = "Register `HT_SIG%s` writer"] pub type W = crate::W; #[cfg(feature = "impl-register-debug")] impl core::fmt::Debug for R { @@ -22,7 +22,7 @@ impl crate::Writable for HT_SIG_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } -#[doc = "`reset()` method sets HT_SIG to value 0"] +#[doc = "`reset()` method sets HT_SIG%s to value 0"] impl crate::Resettable for HT_SIG_SPEC { const RESET_VALUE: u32 = 0; } diff --git a/esp32/src/wifi/tx_slot_parameters/ht_unknown.rs b/esp32/src/wifi/ht_unknown.rs similarity index 93% rename from esp32/src/wifi/tx_slot_parameters/ht_unknown.rs rename to esp32/src/wifi/ht_unknown.rs index fa76ba6f8..a447a3b1b 100644 --- a/esp32/src/wifi/tx_slot_parameters/ht_unknown.rs +++ b/esp32/src/wifi/ht_unknown.rs @@ -1,6 +1,6 @@ -#[doc = "Register `HT_UNKNOWN` reader"] +#[doc = "Register `HT_UNKNOWN%s` reader"] pub type R = crate::R; -#[doc = "Register `HT_UNKNOWN` writer"] +#[doc = "Register `HT_UNKNOWN%s` writer"] pub type W = crate::W; #[doc = "Field `LENGTH` reader - The length of the PPDU"] pub type LENGTH_R = crate::FieldReader; @@ -41,7 +41,7 @@ impl crate::Writable for HT_UNKNOWN_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } -#[doc = "`reset()` method sets HT_UNKNOWN to value 0"] +#[doc = "`reset()` method sets HT_UNKNOWN%s to value 0"] impl crate::Resettable for HT_UNKNOWN_SPEC { const RESET_VALUE: u32 = 0; } diff --git a/esp32/src/wifi/interface_rx_control.rs b/esp32/src/wifi/interface_rx_control.rs new file mode 100644 index 000000000..a79916d98 --- /dev/null +++ b/esp32/src/wifi/interface_rx_control.rs @@ -0,0 +1,77 @@ +#[doc = "Register `INTERFACE_RX_CONTROL%s` reader"] +pub type R = crate::R; +#[doc = "Register `INTERFACE_RX_CONTROL%s` writer"] +pub type W = crate::W; +#[doc = "Field `BSSID_CHECK` reader - Check BSSID for filtering"] +pub type BSSID_CHECK_R = crate::BitReader; +#[doc = "Field `BSSID_CHECK` writer - Check BSSID for filtering"] +pub type BSSID_CHECK_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SCAN_MODE` reader - Receive beacon frames"] +pub type SCAN_MODE_R = crate::BitReader; +#[doc = "Field `SCAN_MODE` writer - Receive beacon frames"] +pub type SCAN_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DATA_AND_MGMT_MODE` reader - Receive everything except control frames"] +pub type DATA_AND_MGMT_MODE_R = crate::BitReader; +#[doc = "Field `DATA_AND_MGMT_MODE` writer - Receive everything except control frames"] +pub type DATA_AND_MGMT_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 1 - Check BSSID for filtering"] + #[inline(always)] + pub fn bssid_check(&self) -> BSSID_CHECK_R { + BSSID_CHECK_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 4 - Receive beacon frames"] + #[inline(always)] + pub fn scan_mode(&self) -> SCAN_MODE_R { + SCAN_MODE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 8 - Receive everything except control frames"] + #[inline(always)] + pub fn data_and_mgmt_mode(&self) -> DATA_AND_MGMT_MODE_R { + DATA_AND_MGMT_MODE_R::new(((self.bits >> 8) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INTERFACE_RX_CONTROL") + .field("bssid_check", &self.bssid_check()) + .field("scan_mode", &self.scan_mode()) + .field("data_and_mgmt_mode", &self.data_and_mgmt_mode()) + .finish() + } +} +impl W { + #[doc = "Bit 1 - Check BSSID for filtering"] + #[inline(always)] + pub fn bssid_check(&mut self) -> BSSID_CHECK_W { + BSSID_CHECK_W::new(self, 1) + } + #[doc = "Bit 4 - Receive beacon frames"] + #[inline(always)] + pub fn scan_mode(&mut self) -> SCAN_MODE_W { + SCAN_MODE_W::new(self, 4) + } + #[doc = "Bit 8 - Receive everything except control frames"] + #[inline(always)] + pub fn data_and_mgmt_mode(&mut self) -> DATA_AND_MGMT_MODE_W { + DATA_AND_MGMT_MODE_W::new(self, 8) + } +} +#[doc = "Controls RX for an interface\n\nYou can [`read`](crate::Reg::read) this register and get [`interface_rx_control::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interface_rx_control::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTERFACE_RX_CONTROL_SPEC; +impl crate::RegisterSpec for INTERFACE_RX_CONTROL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`interface_rx_control::R`](R) reader structure"] +impl crate::Readable for INTERFACE_RX_CONTROL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`interface_rx_control::W`](W) writer structure"] +impl crate::Writable for INTERFACE_RX_CONTROL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INTERFACE_RX_CONTROL%s to value 0"] +impl crate::Resettable for INTERFACE_RX_CONTROL_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32/src/wifi/mac_interrupt.rs b/esp32/src/wifi/mac_interrupt.rs new file mode 100644 index 000000000..2eb370cfc --- /dev/null +++ b/esp32/src/wifi/mac_interrupt.rs @@ -0,0 +1,27 @@ +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +#[doc = "Status and clear for the Wi-Fi MAC interrupt"] +pub struct MAC_INTERRUPT { + wifi_int_status: WIFI_INT_STATUS, + wifi_int_clear: WIFI_INT_CLEAR, +} +impl MAC_INTERRUPT { + #[doc = "0x00 - Interrupt status of WIFI peripheral"] + #[inline(always)] + pub const fn wifi_int_status(&self) -> &WIFI_INT_STATUS { + &self.wifi_int_status + } + #[doc = "0x04 - Interrupt status clear of WIFI peripheral"] + #[inline(always)] + pub const fn wifi_int_clear(&self) -> &WIFI_INT_CLEAR { + &self.wifi_int_clear + } +} +#[doc = "WIFI_INT_STATUS (rw) register accessor: Interrupt status of WIFI peripheral\n\nYou can [`read`](crate::Reg::read) this register and get [`wifi_int_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wifi_int_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wifi_int_status`] module"] +pub type WIFI_INT_STATUS = crate::Reg; +#[doc = "Interrupt status of WIFI peripheral"] +pub mod wifi_int_status; +#[doc = "WIFI_INT_CLEAR (rw) register accessor: Interrupt status clear of WIFI peripheral\n\nYou can [`read`](crate::Reg::read) this register and get [`wifi_int_clear::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wifi_int_clear::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wifi_int_clear`] module"] +pub type WIFI_INT_CLEAR = crate::Reg; +#[doc = "Interrupt status clear of WIFI peripheral"] +pub mod wifi_int_clear; diff --git a/esp32/src/wifi/wifi_int_clear.rs b/esp32/src/wifi/mac_interrupt/wifi_int_clear.rs similarity index 100% rename from esp32/src/wifi/wifi_int_clear.rs rename to esp32/src/wifi/mac_interrupt/wifi_int_clear.rs diff --git a/esp32/src/wifi/mac_interrupt/wifi_int_status.rs b/esp32/src/wifi/mac_interrupt/wifi_int_status.rs new file mode 100644 index 000000000..a0f172405 --- /dev/null +++ b/esp32/src/wifi/mac_interrupt/wifi_int_status.rs @@ -0,0 +1,28 @@ +#[doc = "Register `WIFI_INT_STATUS` reader"] +pub type R = crate::R; +#[doc = "Register `WIFI_INT_STATUS` writer"] +pub type W = crate::W; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Interrupt status of WIFI peripheral\n\nYou can [`read`](crate::Reg::read) this register and get [`wifi_int_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wifi_int_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WIFI_INT_STATUS_SPEC; +impl crate::RegisterSpec for WIFI_INT_STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`wifi_int_status::R`](R) reader structure"] +impl crate::Readable for WIFI_INT_STATUS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`wifi_int_status::W`](W) writer structure"] +impl crate::Writable for WIFI_INT_STATUS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets WIFI_INT_STATUS to value 0"] +impl crate::Resettable for WIFI_INT_STATUS_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32/src/wifi/tx_slot_parameters/plcp1.rs b/esp32/src/wifi/plcp1.rs similarity index 58% rename from esp32/src/wifi/tx_slot_parameters/plcp1.rs rename to esp32/src/wifi/plcp1.rs index 5cf2c642f..a0b87f20a 100644 --- a/esp32/src/wifi/tx_slot_parameters/plcp1.rs +++ b/esp32/src/wifi/plcp1.rs @@ -1,6 +1,6 @@ -#[doc = "Register `PLCP1` reader"] +#[doc = "Register `PLCP1%s` reader"] pub type R = crate::R; -#[doc = "Register `PLCP1` writer"] +#[doc = "Register `PLCP1%s` writer"] pub type W = crate::W; #[doc = "Field `LEN` reader - Length of packet (in bytes)"] pub type LEN_R = crate::FieldReader; @@ -10,14 +10,22 @@ pub type LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; pub type RATE_R = crate::FieldReader; #[doc = "Field `RATE` writer - Packet rate (see wifi_phy_rate_t)"] pub type RATE_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `KEY_SLOT_ID` reader - Key slot to use for encryption"] +pub type KEY_SLOT_ID_R = crate::FieldReader; +#[doc = "Field `KEY_SLOT_ID` writer - Key slot to use for encryption"] +pub type KEY_SLOT_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; #[doc = "Field `IS_80211_N` reader - Bit indicating if this is 802.11n"] pub type IS_80211_N_R = crate::BitReader; #[doc = "Field `IS_80211_N` writer - Bit indicating if this is 802.11n"] pub type IS_80211_N_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `UNKNOWN_ENABLE` reader - meaning unknown, set to one for TX"] -pub type UNKNOWN_ENABLE_R = crate::FieldReader; -#[doc = "Field `UNKNOWN_ENABLE` writer - meaning unknown, set to one for TX"] -pub type UNKNOWN_ENABLE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `BANDWIDTH` reader - Zero indicates 20MHz and one indicates 40MHz"] +pub type BANDWIDTH_R = crate::BitReader; +#[doc = "Field `BANDWIDTH` writer - Zero indicates 20MHz and one indicates 40MHz"] +pub type BANDWIDTH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INTERFACE_ID` reader - ID of the interface this transmission is from"] +pub type INTERFACE_ID_R = crate::FieldReader; +#[doc = "Field `INTERFACE_ID` writer - ID of the interface this transmission is from"] +pub type INTERFACE_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:11 - Length of packet (in bytes)"] #[inline(always)] @@ -29,15 +37,25 @@ impl R { pub fn rate(&self) -> RATE_R { RATE_R::new(((self.bits >> 12) & 0x1f) as u8) } + #[doc = "Bits 17:21 - Key slot to use for encryption"] + #[inline(always)] + pub fn key_slot_id(&self) -> KEY_SLOT_ID_R { + KEY_SLOT_ID_R::new(((self.bits >> 17) & 0x1f) as u8) + } #[doc = "Bit 25 - Bit indicating if this is 802.11n"] #[inline(always)] pub fn is_80211_n(&self) -> IS_80211_N_R { IS_80211_N_R::new(((self.bits >> 25) & 1) != 0) } - #[doc = "Bits 28:29 - meaning unknown, set to one for TX"] + #[doc = "Bit 28 - Zero indicates 20MHz and one indicates 40MHz"] + #[inline(always)] + pub fn bandwidth(&self) -> BANDWIDTH_R { + BANDWIDTH_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bits 30:31 - ID of the interface this transmission is from"] #[inline(always)] - pub fn unknown_enable(&self) -> UNKNOWN_ENABLE_R { - UNKNOWN_ENABLE_R::new(((self.bits >> 28) & 3) as u8) + pub fn interface_id(&self) -> INTERFACE_ID_R { + INTERFACE_ID_R::new(((self.bits >> 30) & 3) as u8) } } #[cfg(feature = "impl-register-debug")] @@ -46,8 +64,10 @@ impl core::fmt::Debug for R { f.debug_struct("PLCP1") .field("len", &self.len()) .field("rate", &self.rate()) + .field("key_slot_id", &self.key_slot_id()) .field("is_80211_n", &self.is_80211_n()) - .field("unknown_enable", &self.unknown_enable()) + .field("bandwidth", &self.bandwidth()) + .field("interface_id", &self.interface_id()) .finish() } } @@ -62,15 +82,25 @@ impl W { pub fn rate(&mut self) -> RATE_W { RATE_W::new(self, 12) } + #[doc = "Bits 17:21 - Key slot to use for encryption"] + #[inline(always)] + pub fn key_slot_id(&mut self) -> KEY_SLOT_ID_W { + KEY_SLOT_ID_W::new(self, 17) + } #[doc = "Bit 25 - Bit indicating if this is 802.11n"] #[inline(always)] pub fn is_80211_n(&mut self) -> IS_80211_N_W { IS_80211_N_W::new(self, 25) } - #[doc = "Bits 28:29 - meaning unknown, set to one for TX"] + #[doc = "Bit 28 - Zero indicates 20MHz and one indicates 40MHz"] + #[inline(always)] + pub fn bandwidth(&mut self) -> BANDWIDTH_W { + BANDWIDTH_W::new(self, 28) + } + #[doc = "Bits 30:31 - ID of the interface this transmission is from"] #[inline(always)] - pub fn unknown_enable(&mut self) -> UNKNOWN_ENABLE_W { - UNKNOWN_ENABLE_W::new(self, 28) + pub fn interface_id(&mut self) -> INTERFACE_ID_W { + INTERFACE_ID_W::new(self, 30) } } #[doc = "PLCP1\n\nYou can [`read`](crate::Reg::read) this register and get [`plcp1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`plcp1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] @@ -86,7 +116,7 @@ impl crate::Writable for PLCP1_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } -#[doc = "`reset()` method sets PLCP1 to value 0"] +#[doc = "`reset()` method sets PLCP1%s to value 0"] impl crate::Resettable for PLCP1_SPEC { const RESET_VALUE: u32 = 0; } diff --git a/esp32/src/wifi/tx_slot_parameters/plcp2.rs b/esp32/src/wifi/plcp2.rs similarity index 93% rename from esp32/src/wifi/tx_slot_parameters/plcp2.rs rename to esp32/src/wifi/plcp2.rs index 96de00ea2..330aef254 100644 --- a/esp32/src/wifi/tx_slot_parameters/plcp2.rs +++ b/esp32/src/wifi/plcp2.rs @@ -1,6 +1,6 @@ -#[doc = "Register `PLCP2` reader"] +#[doc = "Register `PLCP2%s` reader"] pub type R = crate::R; -#[doc = "Register `PLCP2` writer"] +#[doc = "Register `PLCP2%s` writer"] pub type W = crate::W; #[doc = "Field `UNKNOWN` reader - meaning unknown, set to one for TX"] pub type UNKNOWN_R = crate::BitReader; @@ -41,7 +41,7 @@ impl crate::Writable for PLCP2_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } -#[doc = "`reset()` method sets PLCP2 to value 0"] +#[doc = "`reset()` method sets PLCP2%s to value 0"] impl crate::Resettable for PLCP2_SPEC { const RESET_VALUE: u32 = 0; } diff --git a/esp32/src/wifi/tx_slot_parameters/pmd.rs b/esp32/src/wifi/pmd.rs similarity index 90% rename from esp32/src/wifi/tx_slot_parameters/pmd.rs rename to esp32/src/wifi/pmd.rs index e1aecad6d..db78b5e20 100644 --- a/esp32/src/wifi/tx_slot_parameters/pmd.rs +++ b/esp32/src/wifi/pmd.rs @@ -1,6 +1,6 @@ -#[doc = "Register `PMD` reader"] +#[doc = "Register `PMD%s` reader"] pub type R = crate::R; -#[doc = "Register `PMD` writer"] +#[doc = "Register `PMD%s` writer"] pub type W = crate::W; #[cfg(feature = "impl-register-debug")] impl core::fmt::Debug for R { @@ -22,7 +22,7 @@ impl crate::Writable for PMD_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } -#[doc = "`reset()` method sets PMD to value 0"] +#[doc = "`reset()` method sets PMD%s to value 0"] impl crate::Resettable for PMD_SPEC { const RESET_VALUE: u32 = 0; } diff --git a/esp32/src/wifi/rx_dma_list.rs b/esp32/src/wifi/rx_dma_list.rs new file mode 100644 index 000000000..86fe02f79 --- /dev/null +++ b/esp32/src/wifi/rx_dma_list.rs @@ -0,0 +1,37 @@ +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +#[doc = "RX_DMA_LIST"] +pub struct RX_DMA_LIST { + rx_descr_base: RX_DESCR_BASE, + rx_descr_next: RX_DESCR_NEXT, + rx_descr_last: RX_DESCR_LAST, +} +impl RX_DMA_LIST { + #[doc = "0x00 - base address of the RX DMA list"] + #[inline(always)] + pub const fn rx_descr_base(&self) -> &RX_DESCR_BASE { + &self.rx_descr_base + } + #[doc = "0x04 - next item in the RX DMA list"] + #[inline(always)] + pub const fn rx_descr_next(&self) -> &RX_DESCR_NEXT { + &self.rx_descr_next + } + #[doc = "0x08 - last item in RX DMA list"] + #[inline(always)] + pub const fn rx_descr_last(&self) -> &RX_DESCR_LAST { + &self.rx_descr_last + } +} +#[doc = "RX_DESCR_BASE (rw) register accessor: base address of the RX DMA list\n\nYou can [`read`](crate::Reg::read) this register and get [`rx_descr_base::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx_descr_base::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_descr_base`] module"] +pub type RX_DESCR_BASE = crate::Reg; +#[doc = "base address of the RX DMA list"] +pub mod rx_descr_base; +#[doc = "RX_DESCR_NEXT (rw) register accessor: next item in the RX DMA list\n\nYou can [`read`](crate::Reg::read) this register and get [`rx_descr_next::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx_descr_next::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_descr_next`] module"] +pub type RX_DESCR_NEXT = crate::Reg; +#[doc = "next item in the RX DMA list"] +pub mod rx_descr_next; +#[doc = "RX_DESCR_LAST (rw) register accessor: last item in RX DMA list\n\nYou can [`read`](crate::Reg::read) this register and get [`rx_descr_last::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx_descr_last::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_descr_last`] module"] +pub type RX_DESCR_LAST = crate::Reg; +#[doc = "last item in RX DMA list"] +pub mod rx_descr_last; diff --git a/esp32/src/wifi/rx_descr_base.rs b/esp32/src/wifi/rx_dma_list/rx_descr_base.rs similarity index 100% rename from esp32/src/wifi/rx_descr_base.rs rename to esp32/src/wifi/rx_dma_list/rx_descr_base.rs diff --git a/esp32/src/wifi/rx_descr_last.rs b/esp32/src/wifi/rx_dma_list/rx_descr_last.rs similarity index 100% rename from esp32/src/wifi/rx_descr_last.rs rename to esp32/src/wifi/rx_dma_list/rx_descr_last.rs diff --git a/esp32/src/wifi/rx_descr_next.rs b/esp32/src/wifi/rx_dma_list/rx_descr_next.rs similarity index 100% rename from esp32/src/wifi/rx_descr_next.rs rename to esp32/src/wifi/rx_dma_list/rx_descr_next.rs diff --git a/esp32/src/wifi/tx_slot_config/config.rs b/esp32/src/wifi/tx_slot_config/config.rs index bb05683ad..abd5d6adf 100644 --- a/esp32/src/wifi/tx_slot_config/config.rs +++ b/esp32/src/wifi/tx_slot_config/config.rs @@ -2,13 +2,62 @@ pub type R = crate::R; #[doc = "Register `CONFIG` writer"] pub type W = crate::W; +#[doc = "Field `TIMEOUT` reader - "] +pub type TIMEOUT_R = crate::FieldReader; +#[doc = "Field `TIMEOUT` writer - "] +pub type TIMEOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +#[doc = "Field `BACKOFF_TIME` reader - "] +pub type BACKOFF_TIME_R = crate::FieldReader; +#[doc = "Field `BACKOFF_TIME` writer - "] +pub type BACKOFF_TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +#[doc = "Field `AIFSN` reader - "] +pub type AIFSN_R = crate::FieldReader; +#[doc = "Field `AIFSN` writer - "] +pub type AIFSN_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:11"] + #[inline(always)] + pub fn timeout(&self) -> TIMEOUT_R { + TIMEOUT_R::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bits 12:21"] + #[inline(always)] + pub fn backoff_time(&self) -> BACKOFF_TIME_R { + BACKOFF_TIME_R::new(((self.bits >> 12) & 0x03ff) as u16) + } + #[doc = "Bits 24:27"] + #[inline(always)] + pub fn aifsn(&self) -> AIFSN_R { + AIFSN_R::new(((self.bits >> 24) & 0x0f) as u8) + } +} #[cfg(feature = "impl-register-debug")] impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) + f.debug_struct("CONFIG") + .field("timeout", &self.timeout()) + .field("backoff_time", &self.backoff_time()) + .field("aifsn", &self.aifsn()) + .finish() + } +} +impl W { + #[doc = "Bits 0:11"] + #[inline(always)] + pub fn timeout(&mut self) -> TIMEOUT_W { + TIMEOUT_W::new(self, 0) + } + #[doc = "Bits 12:21"] + #[inline(always)] + pub fn backoff_time(&mut self) -> BACKOFF_TIME_W { + BACKOFF_TIME_W::new(self, 12) + } + #[doc = "Bits 24:27"] + #[inline(always)] + pub fn aifsn(&mut self) -> AIFSN_W { + AIFSN_W::new(self, 24) } } -impl W {} #[doc = "Config\n\nYou can [`read`](crate::Reg::read) this register and get [`config::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`config::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CONFIG_SPEC; impl crate::RegisterSpec for CONFIG_SPEC { diff --git a/esp32/src/wifi/tx_slot_config/plcp0.rs b/esp32/src/wifi/tx_slot_config/plcp0.rs index f5e7d1bfc..c8f4e5a73 100644 --- a/esp32/src/wifi/tx_slot_config/plcp0.rs +++ b/esp32/src/wifi/tx_slot_config/plcp0.rs @@ -6,20 +6,38 @@ pub type W = crate::W; pub type DMA_ADDR_R = crate::FieldReader; #[doc = "Field `DMA_ADDR` writer - Bottom bits of address of dma_item"] pub type DMA_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>; -#[doc = "Field `FLAGS` reader - Flags for the SLOT"] -pub type FLAGS_R = crate::FieldReader; -#[doc = "Field `FLAGS` writer - Flags for the SLOT"] -pub type FLAGS_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +#[doc = "Field `WAIT_FOR_ACK` reader - Enables ACK timeouts"] +pub type WAIT_FOR_ACK_R = crate::BitReader; +#[doc = "Field `WAIT_FOR_ACK` writer - Enables ACK timeouts"] +pub type WAIT_FOR_ACK_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SLOT_VALID` reader - Marks this slot as valid"] +pub type SLOT_VALID_R = crate::BitReader; +#[doc = "Field `SLOT_VALID` writer - Marks this slot as valid"] +pub type SLOT_VALID_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SLOT_ENABLED` reader - Marks this slot as ready for transmission"] +pub type SLOT_ENABLED_R = crate::BitReader; +#[doc = "Field `SLOT_ENABLED` writer - Marks this slot as ready for transmission"] +pub type SLOT_ENABLED_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:19 - Bottom bits of address of dma_item"] #[inline(always)] pub fn dma_addr(&self) -> DMA_ADDR_R { DMA_ADDR_R::new(self.bits & 0x000f_ffff) } - #[doc = "Bits 20:31 - Flags for the SLOT"] + #[doc = "Bit 28 - Enables ACK timeouts"] #[inline(always)] - pub fn flags(&self) -> FLAGS_R { - FLAGS_R::new(((self.bits >> 20) & 0x0fff) as u16) + pub fn wait_for_ack(&self) -> WAIT_FOR_ACK_R { + WAIT_FOR_ACK_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 30 - Marks this slot as valid"] + #[inline(always)] + pub fn slot_valid(&self) -> SLOT_VALID_R { + SLOT_VALID_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Marks this slot as ready for transmission"] + #[inline(always)] + pub fn slot_enabled(&self) -> SLOT_ENABLED_R { + SLOT_ENABLED_R::new(((self.bits >> 31) & 1) != 0) } } #[cfg(feature = "impl-register-debug")] @@ -27,7 +45,9 @@ impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("PLCP0") .field("dma_addr", &self.dma_addr()) - .field("flags", &self.flags()) + .field("wait_for_ack", &self.wait_for_ack()) + .field("slot_valid", &self.slot_valid()) + .field("slot_enabled", &self.slot_enabled()) .finish() } } @@ -37,10 +57,20 @@ impl W { pub fn dma_addr(&mut self) -> DMA_ADDR_W { DMA_ADDR_W::new(self, 0) } - #[doc = "Bits 20:31 - Flags for the SLOT"] + #[doc = "Bit 28 - Enables ACK timeouts"] + #[inline(always)] + pub fn wait_for_ack(&mut self) -> WAIT_FOR_ACK_W { + WAIT_FOR_ACK_W::new(self, 28) + } + #[doc = "Bit 30 - Marks this slot as valid"] + #[inline(always)] + pub fn slot_valid(&mut self) -> SLOT_VALID_W { + SLOT_VALID_W::new(self, 30) + } + #[doc = "Bit 31 - Marks this slot as ready for transmission"] #[inline(always)] - pub fn flags(&mut self) -> FLAGS_W { - FLAGS_W::new(self, 20) + pub fn slot_enabled(&mut self) -> SLOT_ENABLED_W { + SLOT_ENABLED_W::new(self, 31) } } #[doc = "PLCP0\n\nYou can [`read`](crate::Reg::read) this register and get [`plcp0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`plcp0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] diff --git a/esp32/src/wifi/tx_slot_parameters.rs b/esp32/src/wifi/tx_slot_parameters.rs deleted file mode 100644 index 29df047b7..000000000 --- a/esp32/src/wifi/tx_slot_parameters.rs +++ /dev/null @@ -1,69 +0,0 @@ -#[repr(C)] -#[cfg_attr(feature = "impl-register-debug", derive(Debug))] -#[doc = "Used to set transmission parameters for the slot"] -pub struct TX_SLOT_PARAMETERS { - plcp1: PLCP1, - plcp2: PLCP2, - ht_sig: HT_SIG, - ht_unknown: HT_UNKNOWN, - duration: DURATION, - _reserved5: [u8; 0x04], - pmd: PMD, - _reserved_end: [u8; 0x20], -} -impl TX_SLOT_PARAMETERS { - #[doc = "0x00 - PLCP1"] - #[inline(always)] - pub const fn plcp1(&self) -> &PLCP1 { - &self.plcp1 - } - #[doc = "0x04 - PLCP2"] - #[inline(always)] - pub const fn plcp2(&self) -> &PLCP2 { - &self.plcp2 - } - #[doc = "0x08 - HT-SIG field in HT preamble"] - #[inline(always)] - pub const fn ht_sig(&self) -> &HT_SIG { - &self.ht_sig - } - #[doc = "0x0c - exact meaning and name unknown, related to HT"] - #[inline(always)] - pub const fn ht_unknown(&self) -> &HT_UNKNOWN { - &self.ht_unknown - } - #[doc = "0x10 - duration of the frame exchange"] - #[inline(always)] - pub const fn duration(&self) -> &DURATION { - &self.duration - } - #[doc = "0x18 - "] - #[inline(always)] - pub const fn pmd(&self) -> &PMD { - &self.pmd - } -} -#[doc = "PLCP1 (rw) register accessor: PLCP1\n\nYou can [`read`](crate::Reg::read) this register and get [`plcp1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`plcp1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@plcp1`] module"] -pub type PLCP1 = crate::Reg; -#[doc = "PLCP1"] -pub mod plcp1; -#[doc = "PLCP2 (rw) register accessor: PLCP2\n\nYou can [`read`](crate::Reg::read) this register and get [`plcp2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`plcp2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@plcp2`] module"] -pub type PLCP2 = crate::Reg; -#[doc = "PLCP2"] -pub mod plcp2; -#[doc = "HT_SIG (rw) register accessor: HT-SIG field in HT preamble\n\nYou can [`read`](crate::Reg::read) this register and get [`ht_sig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ht_sig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ht_sig`] module"] -pub type HT_SIG = crate::Reg; -#[doc = "HT-SIG field in HT preamble"] -pub mod ht_sig; -#[doc = "HT_UNKNOWN (rw) register accessor: exact meaning and name unknown, related to HT\n\nYou can [`read`](crate::Reg::read) this register and get [`ht_unknown::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ht_unknown::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ht_unknown`] module"] -pub type HT_UNKNOWN = crate::Reg; -#[doc = "exact meaning and name unknown, related to HT"] -pub mod ht_unknown; -#[doc = "DURATION (rw) register accessor: duration of the frame exchange\n\nYou can [`read`](crate::Reg::read) this register and get [`duration::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`duration::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@duration`] module"] -pub type DURATION = crate::Reg; -#[doc = "duration of the frame exchange"] -pub mod duration; -#[doc = "PMD (rw) register accessor: \n\nYou can [`read`](crate::Reg::read) this register and get [`pmd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pmd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pmd`] module"] -pub type PMD = crate::Reg; -#[doc = ""] -pub mod pmd; diff --git a/esp32/src/wifi/txq_state.rs b/esp32/src/wifi/txq_state.rs new file mode 100644 index 000000000..57fa611b2 --- /dev/null +++ b/esp32/src/wifi/txq_state.rs @@ -0,0 +1,47 @@ +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +#[doc = "State of transmission queues"] +pub struct TXQ_STATE { + tx_error_clear: TX_ERROR_CLEAR, + tx_error_status: TX_ERROR_STATUS, + tx_complete_clear: TX_COMPLETE_CLEAR, + tx_complete_status: TX_COMPLETE_STATUS, +} +impl TXQ_STATE { + #[doc = "0x00 - Clear the error status of a slot"] + #[inline(always)] + pub const fn tx_error_clear(&self) -> &TX_ERROR_CLEAR { + &self.tx_error_clear + } + #[doc = "0x04 - Error status of a slot"] + #[inline(always)] + pub const fn tx_error_status(&self) -> &TX_ERROR_STATUS { + &self.tx_error_status + } + #[doc = "0x08 - Clear the completion status of a slot"] + #[inline(always)] + pub const fn tx_complete_clear(&self) -> &TX_COMPLETE_CLEAR { + &self.tx_complete_clear + } + #[doc = "0x0c - Completion status of a slot"] + #[inline(always)] + pub const fn tx_complete_status(&self) -> &TX_COMPLETE_STATUS { + &self.tx_complete_status + } +} +#[doc = "TX_ERROR_CLEAR (rw) register accessor: Clear the error status of a slot\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_error_clear::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_error_clear::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_error_clear`] module"] +pub type TX_ERROR_CLEAR = crate::Reg; +#[doc = "Clear the error status of a slot"] +pub mod tx_error_clear; +#[doc = "TX_ERROR_STATUS (rw) register accessor: Error status of a slot\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_error_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_error_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_error_status`] module"] +pub type TX_ERROR_STATUS = crate::Reg; +#[doc = "Error status of a slot"] +pub mod tx_error_status; +#[doc = "TX_COMPLETE_CLEAR (rw) register accessor: Clear the completion status of a slot\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_complete_clear::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_complete_clear::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_complete_clear`] module"] +pub type TX_COMPLETE_CLEAR = crate::Reg; +#[doc = "Clear the completion status of a slot"] +pub mod tx_complete_clear; +#[doc = "TX_COMPLETE_STATUS (rw) register accessor: Completion status of a slot\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_complete_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_complete_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_complete_status`] module"] +pub type TX_COMPLETE_STATUS = crate::Reg; +#[doc = "Completion status of a slot"] +pub mod tx_complete_status; diff --git a/esp32/src/wifi/tx_complete_clear.rs b/esp32/src/wifi/txq_state/tx_complete_clear.rs similarity index 100% rename from esp32/src/wifi/tx_complete_clear.rs rename to esp32/src/wifi/txq_state/tx_complete_clear.rs diff --git a/esp32/src/wifi/tx_complete_status.rs b/esp32/src/wifi/txq_state/tx_complete_status.rs similarity index 100% rename from esp32/src/wifi/tx_complete_status.rs rename to esp32/src/wifi/txq_state/tx_complete_status.rs diff --git a/esp32/src/wifi/tx_error_clear.rs b/esp32/src/wifi/txq_state/tx_error_clear.rs similarity index 100% rename from esp32/src/wifi/tx_error_clear.rs rename to esp32/src/wifi/txq_state/tx_error_clear.rs diff --git a/esp32/src/wifi/tx_error_status.rs b/esp32/src/wifi/txq_state/tx_error_status.rs similarity index 100% rename from esp32/src/wifi/tx_error_status.rs rename to esp32/src/wifi/txq_state/tx_error_status.rs diff --git a/esp32/src/wifi/unknown_rx_policy.rs b/esp32/src/wifi/unknown_rx_policy.rs deleted file mode 100644 index 855d52111..000000000 --- a/esp32/src/wifi/unknown_rx_policy.rs +++ /dev/null @@ -1,28 +0,0 @@ -#[doc = "Register `UNKNOWN_RX_POLICY%s` reader"] -pub type R = crate::R; -#[doc = "Register `UNKNOWN_RX_POLICY%s` writer"] -pub type W = crate::W; -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) - } -} -impl W {} -#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`unknown_rx_policy::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`unknown_rx_policy::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct UNKNOWN_RX_POLICY_SPEC; -impl crate::RegisterSpec for UNKNOWN_RX_POLICY_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`unknown_rx_policy::R`](R) reader structure"] -impl crate::Readable for UNKNOWN_RX_POLICY_SPEC {} -#[doc = "`write(|w| ..)` method takes [`unknown_rx_policy::W`](W) writer structure"] -impl crate::Writable for UNKNOWN_RX_POLICY_SPEC { - type Safety = crate::Unsafe; - const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; -} -#[doc = "`reset()` method sets UNKNOWN_RX_POLICY%s to value 0"] -impl crate::Resettable for UNKNOWN_RX_POLICY_SPEC { - const RESET_VALUE: u32 = 0; -} diff --git a/esp32/src/wifi/wifi_int_status.rs b/esp32/src/wifi/wifi_int_status.rs deleted file mode 100644 index 2cabed589..000000000 --- a/esp32/src/wifi/wifi_int_status.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `WIFI_INT_STATUS` reader"] -pub type R = crate::R; -#[doc = "Register `WIFI_INT_STATUS` writer"] -pub type W = crate::W; -#[doc = "Field `TXQ_COMPLETE` reader - Indicates the completion of a transmission"] -pub type TXQ_COMPLETE_R = crate::BitReader; -#[doc = "Field `TXQ_COMPLETE` writer - Indicates the completion of a transmission"] -pub type TXQ_COMPLETE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TXQ_COLLISION` reader - Indicates a collision, while transmitting"] -pub type TXQ_COLLISION_R = crate::BitReader; -#[doc = "Field `TXQ_COLLISION` writer - Indicates a collision, while transmitting"] -pub type TXQ_COLLISION_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TXQ_TIMEOUT` reader - Indicates a timeout, while transmitting"] -pub type TXQ_TIMEOUT_R = crate::BitReader; -#[doc = "Field `TXQ_TIMEOUT` writer - Indicates a timeout, while transmitting"] -pub type TXQ_TIMEOUT_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 7 - Indicates the completion of a transmission"] - #[inline(always)] - pub fn txq_complete(&self) -> TXQ_COMPLETE_R { - TXQ_COMPLETE_R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - Indicates a collision, while transmitting"] - #[inline(always)] - pub fn txq_collision(&self) -> TXQ_COLLISION_R { - TXQ_COLLISION_R::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 19 - Indicates a timeout, while transmitting"] - #[inline(always)] - pub fn txq_timeout(&self) -> TXQ_TIMEOUT_R { - TXQ_TIMEOUT_R::new(((self.bits >> 19) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("WIFI_INT_STATUS") - .field("txq_complete", &self.txq_complete()) - .field("txq_collision", &self.txq_collision()) - .field("txq_timeout", &self.txq_timeout()) - .finish() - } -} -impl W { - #[doc = "Bit 7 - Indicates the completion of a transmission"] - #[inline(always)] - pub fn txq_complete(&mut self) -> TXQ_COMPLETE_W { - TXQ_COMPLETE_W::new(self, 7) - } - #[doc = "Bit 8 - Indicates a collision, while transmitting"] - #[inline(always)] - pub fn txq_collision(&mut self) -> TXQ_COLLISION_W { - TXQ_COLLISION_W::new(self, 8) - } - #[doc = "Bit 19 - Indicates a timeout, while transmitting"] - #[inline(always)] - pub fn txq_timeout(&mut self) -> TXQ_TIMEOUT_W { - TXQ_TIMEOUT_W::new(self, 19) - } -} -#[doc = "Interrupt status of WIFI peripheral\n\nYou can [`read`](crate::Reg::read) this register and get [`wifi_int_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wifi_int_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct WIFI_INT_STATUS_SPEC; -impl crate::RegisterSpec for WIFI_INT_STATUS_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`wifi_int_status::R`](R) reader structure"] -impl crate::Readable for WIFI_INT_STATUS_SPEC {} -#[doc = "`write(|w| ..)` method takes [`wifi_int_status::W`](W) writer structure"] -impl crate::Writable for WIFI_INT_STATUS_SPEC { - type Safety = crate::Unsafe; - const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; -} -#[doc = "`reset()` method sets WIFI_INT_STATUS to value 0"] -impl crate::Resettable for WIFI_INT_STATUS_SPEC { - const RESET_VALUE: u32 = 0; -} diff --git a/esp32/svd/patches/esp32-wifi.yaml b/esp32/svd/patches/esp32-wifi.yaml index ed7d208e6..7a41fa72f 100644 --- a/esp32/svd/patches/esp32-wifi.yaml +++ b/esp32/svd/patches/esp32-wifi.yaml @@ -1,9 +1,3 @@ - - -# This is a patch against the SVD provided by Espressif -# Patchfile for use with https://github.com/rust-embedded/svdtools -# Expects the svd repo to be cloned in the directory next to this repo -# Then run `svd patch esp32-wifi.yaml` in this directory, the patched file will be in ../svd/svd/ _add: WIFI: description: MAC controller for Wi-Fi peripheral @@ -15,42 +9,14 @@ _add: size: 0x2100 usage: registers registers: - RX_CTRL: - description: Controls the reception of frames addressOffset: 0x84 - access: read-write - fields: - RX_DESCR_RELOAD: - bitOffset: 0 - bitWidth: 1 - description: Instruct the hardware to reload the RX descriptors - RX_ENABLE: - bitOffset: 31 - bitWidth: 1 - description: Enable frame reception - - RX_DESCR_BASE: - description: base address of the RX DMA list - addressOffset: 0x88 - acccess: read-write - - RX_DESCR_NEXT: - description: next item in the RX DMA list - addressOffset: 0x8c - access: read-write - - RX_DESCR_LAST: - description: last item in RX DMA list - addressOffset: 0x90 - access: read-write - - UNKNOWN_RX_POLICY%s: - dim: 2 + INTERFACE_RX_CONTROL%s: + dim: 4 dimIncrement: 4 addressOffset: 0xd8 access: read-write - + HW_STAT_ACK_INT: addressOffset: 0x2bc access: read @@ -74,11 +40,11 @@ _add: HW_STAT_RX_END: addressOffset: 0x2d0 access: read - + HW_STAT_HOP_ERR: addressOffset: 0x2d8 access: read - + HW_STAT_FULL2: addressOffset: 0x2dc access: read @@ -86,76 +52,35 @@ _add: HW_STAT_BLOCK_ERR: addressOffset: 0x2e0 access: read - - WIFI_INT_STATUS: - description: Interrupt status of WIFI peripheral - addressOffset: 0xc48 - access: read - fields: - TXQ_COMPLETE: - description: Indicates the completion of a transmission - bitOffset: 7 - bitWidth: 1 - TXQ_COLLISION: - description: Indicates a collision, while transmitting - bitOffset: 8 - bitWidth: 1 - TXQ_TIMEOUT: - description: Indicates a timeout, while transmitting - bitOffset: 19 - bitWidth: 1 - - WIFI_INT_CLEAR: - description: Interrupt status clear of WIFI peripheral - addressOffset: 0xc4c - access: write CTRL: description: Exact name and meaning unknown, used for initializing the MAC addressOffset: 0xcb8 access: read-write - - TX_ERROR_CLEAR: - description: Clear the error status of a slot - addressOffset: 0xcbc - access: write - fields: - SLOT_COLLISION: - bitOffset: 0 - bitWidth: 5 - SLOT_TIMEOUT: - bitOffset: 0x10 - bitWidth: 5 - - TX_ERROR_STATUS: - description: Error status of a slot - addressOffset: 0xcc0 - access: read - fields: - SLOT_COLLISION: - bitOffset: 0 - bitWidth: 5 - SLOT_TIMEOUT: - bitOffset: 0x10 - bitWidth: 5 - - TX_COMPLETE_CLEAR: - description: Clear the completion status of a slot - addressOffset: 0xcc4 - access: write - fields: - SLOTS: - bitOffset: 0 - bitWidth: 5 - - TX_COMPLETE_STATUS: - description: Completion status of a slot - addressOffset: 0xcc8 - access: read - fields: - SLOTS: - bitOffset: 0 - bitWidth: 5 + PLCP1%s: + dim: 5 + dimIncrement: 0x3c + addressOffset: 0x1168 + PLCP2%s: + dim: 5 + dimIncrement: 0x3c + addressOffset: 0x116c + HT_SIG%s: + dim: 5 + dimIncrement: 0x3c + addressOffset: 0x1170 + HT_UNKNOWN%s: + dim: 5 + dimIncrement: 0x3c + addressOffset: 0x1174 + DURATION%s: + dim: 5 + dimIncrement: 0x3c + addressOffset: 0x1178 + PMD%s: + dim: 5 + dimIncrement: 0x3c + addressOffset: 0x1180 HW_STAT_TX_RTS: addressOffset: 0xd58 @@ -197,124 +122,35 @@ WIFI: Each filter bank has registers for two interfaces. " registers: - ADDR_LOW%s: - dim: 2 - dimIncrement: 0x8 - description: First 4 bytes of BSSID MAC address filter + DUMMY: + addressOffset: 0x0 + RX_DMA_LIST: + addressOffset: 0x88 + registers: + DUMMY: + addressOffset: 0x0 + MAC_INTERRUPT: + addressOffset: 0xc48 + description: Status and clear for the Wi-Fi MAC interrupt + registers: + DUMMY: + addressOffset: 0x0 + TXQ_STATE: + addressOffset: 0xcbc + description: State of transmission queues + registers: + DUMMY: addressOffset: 0x0 - access: read-write - ADDR_HIGH%s: - dim: 2 - dimIncrement: 0x8 - description: last 2 bytes of BSSID MAC address filter - addressOffset: 0x4 - access: read-write - fields: - ADDR: - bitOffset: 0 - bitWidth: 16 - access: read-write - MASK_LOW%s: - dim: 2 - dimIncrement: 0x8 - description: First 4 bytes of BSSID MAC address filter mask - addressOffset: 0x20 - access: read-write - MASK_HIGH%s: - dim: 2 - dimIncrement: 0x8 - description: last 2 bytes of BSSID MAC address filter mask - addressOffset: 0x24 - access: read-write - fields: - MASK: - bitOffset: 0 - bitWidth: 16 - access: read-write - ENABLED: - bitOffset: 16 - bitWidth: 1 - access: read-write TX_SLOT_CONFIG%s: dim: 5 dimIncrement: 0x8 description: Used to configure the TX slot. addressOffset: 0xcfc - access: read-write - registers: - CONFIG: - description: Config - addressOffset: 0x0 - access: read-write - PLCP0: - description: PLCP0 - addressOffset: 0x4 - access: read-write - fields: - DMA_ADDR: - description: Bottom bits of address of dma_item - bitOffset: 0 - bitWidth: 20 - access: write - FLAGS: - description: Flags for the SLOT - bitOffset: 20 - bitWidth: 12 - access: read-write - TX_SLOT_PARAMETERS%s: - dim: 5 - dimIncrement: 0x3c - addressOffset: 0x1168 - description: Used to set transmission parameters for the slot registers: - PLCP1: - description: PLCP1 + DUMMY: addressOffset: 0x0 - access: read-write - fields: - LEN: - description: Length of packet (in bytes) - bitOffset: 0 - bitWidth: 12 - RATE: - description: Packet rate (see wifi_phy_rate_t) - bitOffset: 12 - bitWidth: 5 - IS_80211_N: - description: Bit indicating if this is 802.11n - bitOffset: 25 - bitWidth: 1 - UNKNOWN_ENABLE: - description: meaning unknown, set to one for TX - bitOffset: 28 - bitWidth: 2 - PLCP2: - description: PLCP2 - addressOffset: 0x4 - access: read-write - fields: - UNKNOWN: - description: meaning unknown, set to one for TX - bitOffset: 5 - bitWidth: 1 - HT_SIG: - description: HT-SIG field in HT preamble - addressOffset: 0x8 - access: read-write - HT_UNKNOWN: - description: exact meaning and name unknown, related to HT - addressOffset: 0xc - access: read-write - fields: - LENGTH: - description: The length of the PPDU - bitOffset: 0x0 - bitWidth: 20 - access: write - DURATION: - description: duration of the frame exchange - addressOffset: 0x10 - access: read-write - PMD: - addressOffset: 0x18 - access: read-write +_include: + - "../../../common_patches/wifi/rx.yaml" + - "../../../common_patches/wifi/rx_filter_masked.yaml" + - "../../../common_patches/wifi/tx.yaml" + - "../../../common_patches/wifi/mac_interrupt.yaml" diff --git a/esp32s2/src/lib.rs b/esp32s2/src/lib.rs index 2195e05cd..e27abfa81 100644 --- a/esp32s2/src/lib.rs +++ b/esp32s2/src/lib.rs @@ -2649,6 +2649,52 @@ impl core::fmt::Debug for CRYPTO_DMA { } #[doc = "Crypto DMA Controller"] pub mod crypto_dma; +#[doc = "MAC controller for Wi-Fi peripheral"] +pub struct WIFI { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for WIFI {} +impl WIFI { + #[doc = r"Pointer to the register block"] + pub const PTR: *const wifi::RegisterBlock = 0x6003_3000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const wifi::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for WIFI { + type Target = wifi::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for WIFI { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("WIFI").finish() + } +} +#[doc = "MAC controller for Wi-Fi peripheral"] +pub mod wifi; #[no_mangle] static mut DEVICE_PERIPHERALS: bool = false; #[doc = r" All the peripherals."] @@ -2744,6 +2790,8 @@ pub struct Peripherals { pub COPY_DMA: COPY_DMA, #[doc = "CRYPTO_DMA"] pub CRYPTO_DMA: CRYPTO_DMA, + #[doc = "WIFI"] + pub WIFI: WIFI, } impl Peripherals { #[doc = r" Returns all the peripherals *once*."] @@ -2811,6 +2859,7 @@ impl Peripherals { XTS_AES: XTS_AES::steal(), COPY_DMA: COPY_DMA::steal(), CRYPTO_DMA: CRYPTO_DMA::steal(), + WIFI: WIFI::steal(), } } } diff --git a/esp32s2/src/wifi.rs b/esp32s2/src/wifi.rs new file mode 100644 index 000000000..e781a275e --- /dev/null +++ b/esp32s2/src/wifi.rs @@ -0,0 +1,315 @@ +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +#[doc = "Register block"] +pub struct RegisterBlock { + filter_bank: [FILTER_BANK; 2], + _reserved1: [u8; 0x08], + rx_ctrl: RX_CTRL, + _reserved2: [u8; 0x04], + rx_dma_list: RX_DMA_LIST, + _reserved3: [u8; 0x44], + interface_rx_control: [INTERFACE_RX_CONTROL; 4], + _reserved4: [u8; 0x0b4c], + mac_interrupt: MAC_INTERRUPT, + _reserved5: [u8; 0x58], + txq_state: TXQ_STATE, + _reserved6: [u8; 0x0c], + ctrl: CTRL, + _reserved7: [u8; 0x20], + tx_slot_config: [TX_SLOT_CONFIG; 5], + _reserved8: [u8; 0x0464], + plcp1: (), + _reserved9: [u8; 0x04], + plcp2: (), + _reserved10: [u8; 0x04], + ht_sig: (), + _reserved11: [u8; 0x04], + ht_unknown: (), + _reserved12: [u8; 0x04], + duration: (), + _reserved13: [u8; 0x08], + pmd: (), + _reserved14: [u8; 0x1020], + pwr_interrupt: PWR_INTERRUPT, +} +impl RegisterBlock { + #[doc = "0x00..0x80 - Filter banks for frame reception. Bank zero is for the BSSID and bank one for the RA. Each filter bank has registers for two interfaces."] + #[inline(always)] + pub const fn filter_bank(&self, n: usize) -> &FILTER_BANK { + &self.filter_bank[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x00..0x80 - Filter banks for frame reception. Bank zero is for the BSSID and bank one for the RA. Each filter bank has registers for two interfaces."] + #[inline(always)] + pub fn filter_bank_iter(&self) -> impl Iterator { + self.filter_bank.iter() + } + #[doc = "0x88 - Controls the reception of frames"] + #[inline(always)] + pub const fn rx_ctrl(&self) -> &RX_CTRL { + &self.rx_ctrl + } + #[doc = "0x90..0x9c - RX_DMA_LIST"] + #[inline(always)] + pub const fn rx_dma_list(&self) -> &RX_DMA_LIST { + &self.rx_dma_list + } + #[doc = "0xe0..0xf0 - Controls RX for an interface"] + #[inline(always)] + pub const fn interface_rx_control(&self, n: usize) -> &INTERFACE_RX_CONTROL { + &self.interface_rx_control[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0xe0..0xf0 - Controls RX for an interface"] + #[inline(always)] + pub fn interface_rx_control_iter(&self) -> impl Iterator { + self.interface_rx_control.iter() + } + #[doc = "0xc3c..0xc44 - Status and clear for the WIFI_MAC interrupt"] + #[inline(always)] + pub const fn mac_interrupt(&self) -> &MAC_INTERRUPT { + &self.mac_interrupt + } + #[doc = "0xc9c..0xcac - State of transmission queues"] + #[inline(always)] + pub const fn txq_state(&self) -> &TXQ_STATE { + &self.txq_state + } + #[doc = "0xcb8 - Exact name and meaning unknown, used for initializing the MAC"] + #[inline(always)] + pub const fn ctrl(&self) -> &CTRL { + &self.ctrl + } + #[doc = "0xcdc..0xd04 - Used to configure the TX slot."] + #[inline(always)] + pub const fn tx_slot_config(&self, n: usize) -> &TX_SLOT_CONFIG { + &self.tx_slot_config[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0xcdc..0xd04 - Used to configure the TX slot."] + #[inline(always)] + pub fn tx_slot_config_iter(&self) -> impl Iterator { + self.tx_slot_config.iter() + } + #[doc = "0x1168..0x117c - PLCP1"] + #[inline(always)] + pub const fn plcp1(&self, n: usize) -> &PLCP1 { + #[allow(clippy::no_effect)] + [(); 5][n]; + unsafe { + &*core::ptr::from_ref(self) + .cast::() + .add(4456) + .add(60 * n) + .cast() + } + } + #[doc = "Iterator for array of:"] + #[doc = "0x1168..0x117c - PLCP1"] + #[inline(always)] + pub fn plcp1_iter(&self) -> impl Iterator { + (0..5).map(move |n| unsafe { + &*core::ptr::from_ref(self) + .cast::() + .add(4456) + .add(60 * n) + .cast() + }) + } + #[doc = "0x116c..0x1180 - PLCP2"] + #[inline(always)] + pub const fn plcp2(&self, n: usize) -> &PLCP2 { + #[allow(clippy::no_effect)] + [(); 5][n]; + unsafe { + &*core::ptr::from_ref(self) + .cast::() + .add(4460) + .add(60 * n) + .cast() + } + } + #[doc = "Iterator for array of:"] + #[doc = "0x116c..0x1180 - PLCP2"] + #[inline(always)] + pub fn plcp2_iter(&self) -> impl Iterator { + (0..5).map(move |n| unsafe { + &*core::ptr::from_ref(self) + .cast::() + .add(4460) + .add(60 * n) + .cast() + }) + } + #[doc = "0x1170..0x1184 - HT-SIG field in HT preamble"] + #[inline(always)] + pub const fn ht_sig(&self, n: usize) -> &HT_SIG { + #[allow(clippy::no_effect)] + [(); 5][n]; + unsafe { + &*core::ptr::from_ref(self) + .cast::() + .add(4464) + .add(60 * n) + .cast() + } + } + #[doc = "Iterator for array of:"] + #[doc = "0x1170..0x1184 - HT-SIG field in HT preamble"] + #[inline(always)] + pub fn ht_sig_iter(&self) -> impl Iterator { + (0..5).map(move |n| unsafe { + &*core::ptr::from_ref(self) + .cast::() + .add(4464) + .add(60 * n) + .cast() + }) + } + #[doc = "0x1174..0x1188 - exact meaning and name unknown, related to HT"] + #[inline(always)] + pub const fn ht_unknown(&self, n: usize) -> &HT_UNKNOWN { + #[allow(clippy::no_effect)] + [(); 5][n]; + unsafe { + &*core::ptr::from_ref(self) + .cast::() + .add(4468) + .add(60 * n) + .cast() + } + } + #[doc = "Iterator for array of:"] + #[doc = "0x1174..0x1188 - exact meaning and name unknown, related to HT"] + #[inline(always)] + pub fn ht_unknown_iter(&self) -> impl Iterator { + (0..5).map(move |n| unsafe { + &*core::ptr::from_ref(self) + .cast::() + .add(4468) + .add(60 * n) + .cast() + }) + } + #[doc = "0x1178..0x118c - duration of the frame exchange"] + #[inline(always)] + pub const fn duration(&self, n: usize) -> &DURATION { + #[allow(clippy::no_effect)] + [(); 5][n]; + unsafe { + &*core::ptr::from_ref(self) + .cast::() + .add(4472) + .add(60 * n) + .cast() + } + } + #[doc = "Iterator for array of:"] + #[doc = "0x1178..0x118c - duration of the frame exchange"] + #[inline(always)] + pub fn duration_iter(&self) -> impl Iterator { + (0..5).map(move |n| unsafe { + &*core::ptr::from_ref(self) + .cast::() + .add(4472) + .add(60 * n) + .cast() + }) + } + #[doc = "0x1180..0x1194 - "] + #[inline(always)] + pub const fn pmd(&self, n: usize) -> &PMD { + #[allow(clippy::no_effect)] + [(); 5][n]; + unsafe { + &*core::ptr::from_ref(self) + .cast::() + .add(4480) + .add(60 * n) + .cast() + } + } + #[doc = "Iterator for array of:"] + #[doc = "0x1180..0x1194 - "] + #[inline(always)] + pub fn pmd_iter(&self) -> impl Iterator { + (0..5).map(move |n| unsafe { + &*core::ptr::from_ref(self) + .cast::() + .add(4480) + .add(60 * n) + .cast() + }) + } + #[doc = "0x21a0..0x21a8 - Status and clear for the WIFI_PWR interrupt"] + #[inline(always)] + pub const fn pwr_interrupt(&self) -> &PWR_INTERRUPT { + &self.pwr_interrupt + } +} +#[doc = "RX_CTRL (rw) register accessor: Controls the reception of frames\n\nYou can [`read`](crate::Reg::read) this register and get [`rx_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_ctrl`] module"] +pub type RX_CTRL = crate::Reg; +#[doc = "Controls the reception of frames"] +pub mod rx_ctrl; +#[doc = "INTERFACE_RX_CONTROL (rw) register accessor: Controls RX for an interface\n\nYou can [`read`](crate::Reg::read) this register and get [`interface_rx_control::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interface_rx_control::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@interface_rx_control`] module"] +pub type INTERFACE_RX_CONTROL = crate::Reg; +#[doc = "Controls RX for an interface"] +pub mod interface_rx_control; +#[doc = "CTRL (rw) register accessor: Exact name and meaning unknown, used for initializing the MAC\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`] module"] +pub type CTRL = crate::Reg; +#[doc = "Exact name and meaning unknown, used for initializing the MAC"] +pub mod ctrl; +#[doc = "PLCP1 (rw) register accessor: PLCP1\n\nYou can [`read`](crate::Reg::read) this register and get [`plcp1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`plcp1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@plcp1`] module"] +pub type PLCP1 = crate::Reg; +#[doc = "PLCP1"] +pub mod plcp1; +#[doc = "PLCP2 (rw) register accessor: PLCP2\n\nYou can [`read`](crate::Reg::read) this register and get [`plcp2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`plcp2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@plcp2`] module"] +pub type PLCP2 = crate::Reg; +#[doc = "PLCP2"] +pub mod plcp2; +#[doc = "HT_SIG (rw) register accessor: HT-SIG field in HT preamble\n\nYou can [`read`](crate::Reg::read) this register and get [`ht_sig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ht_sig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ht_sig`] module"] +pub type HT_SIG = crate::Reg; +#[doc = "HT-SIG field in HT preamble"] +pub mod ht_sig; +#[doc = "HT_UNKNOWN (rw) register accessor: exact meaning and name unknown, related to HT\n\nYou can [`read`](crate::Reg::read) this register and get [`ht_unknown::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ht_unknown::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ht_unknown`] module"] +pub type HT_UNKNOWN = crate::Reg; +#[doc = "exact meaning and name unknown, related to HT"] +pub mod ht_unknown; +#[doc = "DURATION (rw) register accessor: duration of the frame exchange\n\nYou can [`read`](crate::Reg::read) this register and get [`duration::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`duration::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@duration`] module"] +pub type DURATION = crate::Reg; +#[doc = "duration of the frame exchange"] +pub mod duration; +#[doc = "PMD (rw) register accessor: \n\nYou can [`read`](crate::Reg::read) this register and get [`pmd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pmd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pmd`] module"] +pub type PMD = crate::Reg; +#[doc = ""] +pub mod pmd; +#[doc = "Filter banks for frame reception. Bank zero is for the BSSID and bank one for the RA. Each filter bank has registers for two interfaces."] +pub use self::filter_bank::FILTER_BANK; +#[doc = r"Cluster"] +#[doc = "Filter banks for frame reception. Bank zero is for the BSSID and bank one for the RA. Each filter bank has registers for two interfaces."] +pub mod filter_bank; +#[doc = "RX_DMA_LIST"] +pub use self::rx_dma_list::RX_DMA_LIST; +#[doc = r"Cluster"] +#[doc = "RX_DMA_LIST"] +pub mod rx_dma_list; +#[doc = "Status and clear for the WIFI_MAC interrupt"] +pub use self::mac_interrupt::MAC_INTERRUPT; +#[doc = r"Cluster"] +#[doc = "Status and clear for the WIFI_MAC interrupt"] +pub mod mac_interrupt; +#[doc = "Status and clear for the WIFI_PWR interrupt"] +pub use self::pwr_interrupt::PWR_INTERRUPT; +#[doc = r"Cluster"] +#[doc = "Status and clear for the WIFI_PWR interrupt"] +pub mod pwr_interrupt; +#[doc = "State of transmission queues"] +pub use self::txq_state::TXQ_STATE; +#[doc = r"Cluster"] +#[doc = "State of transmission queues"] +pub mod txq_state; +#[doc = "Used to configure the TX slot."] +pub use self::tx_slot_config::TX_SLOT_CONFIG; +#[doc = r"Cluster"] +#[doc = "Used to configure the TX slot."] +pub mod tx_slot_config; diff --git a/esp32s2/src/wifi/ctrl.rs b/esp32s2/src/wifi/ctrl.rs new file mode 100644 index 000000000..0f45f772e --- /dev/null +++ b/esp32s2/src/wifi/ctrl.rs @@ -0,0 +1,28 @@ +#[doc = "Register `CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `CTRL` writer"] +pub type W = crate::W; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Exact name and meaning unknown, used for initializing the MAC\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"] +impl crate::Readable for CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32s2/src/wifi/duration.rs b/esp32s2/src/wifi/duration.rs new file mode 100644 index 000000000..a08a3d9a3 --- /dev/null +++ b/esp32s2/src/wifi/duration.rs @@ -0,0 +1,28 @@ +#[doc = "Register `DURATION%s` reader"] +pub type R = crate::R; +#[doc = "Register `DURATION%s` writer"] +pub type W = crate::W; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "duration of the frame exchange\n\nYou can [`read`](crate::Reg::read) this register and get [`duration::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`duration::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DURATION_SPEC; +impl crate::RegisterSpec for DURATION_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`duration::R`](R) reader structure"] +impl crate::Readable for DURATION_SPEC {} +#[doc = "`write(|w| ..)` method takes [`duration::W`](W) writer structure"] +impl crate::Writable for DURATION_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DURATION%s to value 0"] +impl crate::Resettable for DURATION_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32s2/src/wifi/filter_bank.rs b/esp32s2/src/wifi/filter_bank.rs new file mode 100644 index 000000000..52f451206 --- /dev/null +++ b/esp32s2/src/wifi/filter_bank.rs @@ -0,0 +1,119 @@ +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +#[doc = "Filter banks for frame reception. Bank zero is for the BSSID and bank one for the RA. Each filter bank has registers for two interfaces."] +pub struct FILTER_BANK { + addr_low: (), + _reserved1: [u8; 0x04], + addr_high: (), + _reserved2: [u8; 0x1c], + mask_low: (), + _reserved3: [u8; 0x04], + mask_high: (), + _reserved_end: [u8; 0x1c], +} +impl FILTER_BANK { + #[doc = "0x00..0x10 - First 4 bytes of BSSID MAC address filter"] + #[inline(always)] + pub const fn addr_low(&self, n: usize) -> &ADDR_LOW { + #[allow(clippy::no_effect)] + [(); 4][n]; + unsafe { &*core::ptr::from_ref(self).cast::().add(8 * n).cast() } + } + #[doc = "Iterator for array of:"] + #[doc = "0x00..0x10 - First 4 bytes of BSSID MAC address filter"] + #[inline(always)] + pub fn addr_low_iter(&self) -> impl Iterator { + (0..4).map(move |n| unsafe { &*core::ptr::from_ref(self).cast::().add(8 * n).cast() }) + } + #[doc = "0x04..0x14 - last 2 bytes of BSSID MAC address filter"] + #[inline(always)] + pub const fn addr_high(&self, n: usize) -> &ADDR_HIGH { + #[allow(clippy::no_effect)] + [(); 4][n]; + unsafe { + &*core::ptr::from_ref(self) + .cast::() + .add(4) + .add(8 * n) + .cast() + } + } + #[doc = "Iterator for array of:"] + #[doc = "0x04..0x14 - last 2 bytes of BSSID MAC address filter"] + #[inline(always)] + pub fn addr_high_iter(&self) -> impl Iterator { + (0..4).map(move |n| unsafe { + &*core::ptr::from_ref(self) + .cast::() + .add(4) + .add(8 * n) + .cast() + }) + } + #[doc = "0x20..0x30 - First 4 bytes of BSSID MAC address filter mask"] + #[inline(always)] + pub const fn mask_low(&self, n: usize) -> &MASK_LOW { + #[allow(clippy::no_effect)] + [(); 4][n]; + unsafe { + &*core::ptr::from_ref(self) + .cast::() + .add(32) + .add(8 * n) + .cast() + } + } + #[doc = "Iterator for array of:"] + #[doc = "0x20..0x30 - First 4 bytes of BSSID MAC address filter mask"] + #[inline(always)] + pub fn mask_low_iter(&self) -> impl Iterator { + (0..4).map(move |n| unsafe { + &*core::ptr::from_ref(self) + .cast::() + .add(32) + .add(8 * n) + .cast() + }) + } + #[doc = "0x24..0x34 - last 2 bytes of BSSID MAC address filter mask"] + #[inline(always)] + pub const fn mask_high(&self, n: usize) -> &MASK_HIGH { + #[allow(clippy::no_effect)] + [(); 4][n]; + unsafe { + &*core::ptr::from_ref(self) + .cast::() + .add(36) + .add(8 * n) + .cast() + } + } + #[doc = "Iterator for array of:"] + #[doc = "0x24..0x34 - last 2 bytes of BSSID MAC address filter mask"] + #[inline(always)] + pub fn mask_high_iter(&self) -> impl Iterator { + (0..4).map(move |n| unsafe { + &*core::ptr::from_ref(self) + .cast::() + .add(36) + .add(8 * n) + .cast() + }) + } +} +#[doc = "ADDR_LOW (rw) register accessor: First 4 bytes of BSSID MAC address filter\n\nYou can [`read`](crate::Reg::read) this register and get [`addr_low::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`addr_low::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@addr_low`] module"] +pub type ADDR_LOW = crate::Reg; +#[doc = "First 4 bytes of BSSID MAC address filter"] +pub mod addr_low; +#[doc = "ADDR_HIGH (rw) register accessor: last 2 bytes of BSSID MAC address filter\n\nYou can [`read`](crate::Reg::read) this register and get [`addr_high::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`addr_high::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@addr_high`] module"] +pub type ADDR_HIGH = crate::Reg; +#[doc = "last 2 bytes of BSSID MAC address filter"] +pub mod addr_high; +#[doc = "MASK_LOW (rw) register accessor: First 4 bytes of BSSID MAC address filter mask\n\nYou can [`read`](crate::Reg::read) this register and get [`mask_low::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mask_low::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mask_low`] module"] +pub type MASK_LOW = crate::Reg; +#[doc = "First 4 bytes of BSSID MAC address filter mask"] +pub mod mask_low; +#[doc = "MASK_HIGH (rw) register accessor: last 2 bytes of BSSID MAC address filter mask\n\nYou can [`read`](crate::Reg::read) this register and get [`mask_high::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mask_high::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mask_high`] module"] +pub type MASK_HIGH = crate::Reg; +#[doc = "last 2 bytes of BSSID MAC address filter mask"] +pub mod mask_high; diff --git a/esp32s2/src/wifi/filter_bank/addr_high.rs b/esp32s2/src/wifi/filter_bank/addr_high.rs new file mode 100644 index 000000000..519efd8d7 --- /dev/null +++ b/esp32s2/src/wifi/filter_bank/addr_high.rs @@ -0,0 +1,47 @@ +#[doc = "Register `ADDR_HIGH%s` reader"] +pub type R = crate::R; +#[doc = "Register `ADDR_HIGH%s` writer"] +pub type W = crate::W; +#[doc = "Field `ADDR` reader - "] +pub type ADDR_R = crate::FieldReader; +#[doc = "Field `ADDR` writer - "] +pub type ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ADDR_HIGH") + .field("addr", &self.addr()) + .finish() + } +} +impl W { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W::new(self, 0) + } +} +#[doc = "last 2 bytes of BSSID MAC address filter\n\nYou can [`read`](crate::Reg::read) this register and get [`addr_high::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`addr_high::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ADDR_HIGH_SPEC; +impl crate::RegisterSpec for ADDR_HIGH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`addr_high::R`](R) reader structure"] +impl crate::Readable for ADDR_HIGH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`addr_high::W`](W) writer structure"] +impl crate::Writable for ADDR_HIGH_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ADDR_HIGH%s to value 0"] +impl crate::Resettable for ADDR_HIGH_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32/src/wifi/crypto_key_entry/addr_low.rs b/esp32s2/src/wifi/filter_bank/addr_low.rs similarity index 59% rename from esp32/src/wifi/crypto_key_entry/addr_low.rs rename to esp32s2/src/wifi/filter_bank/addr_low.rs index 5c2d5c2c0..bfd170679 100644 --- a/esp32/src/wifi/crypto_key_entry/addr_low.rs +++ b/esp32s2/src/wifi/filter_bank/addr_low.rs @@ -1,6 +1,6 @@ -#[doc = "Register `ADDR_LOW` reader"] +#[doc = "Register `ADDR_LOW%s` reader"] pub type R = crate::R; -#[doc = "Register `ADDR_LOW` writer"] +#[doc = "Register `ADDR_LOW%s` writer"] pub type W = crate::W; #[cfg(feature = "impl-register-debug")] impl core::fmt::Debug for R { @@ -9,7 +9,7 @@ impl core::fmt::Debug for R { } } impl W {} -#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`addr_low::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`addr_low::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +#[doc = "First 4 bytes of BSSID MAC address filter\n\nYou can [`read`](crate::Reg::read) this register and get [`addr_low::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`addr_low::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ADDR_LOW_SPEC; impl crate::RegisterSpec for ADDR_LOW_SPEC { type Ux = u32; @@ -22,7 +22,7 @@ impl crate::Writable for ADDR_LOW_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } -#[doc = "`reset()` method sets ADDR_LOW to value 0"] +#[doc = "`reset()` method sets ADDR_LOW%s to value 0"] impl crate::Resettable for ADDR_LOW_SPEC { const RESET_VALUE: u32 = 0; } diff --git a/esp32s2/src/wifi/filter_bank/mask_high.rs b/esp32s2/src/wifi/filter_bank/mask_high.rs new file mode 100644 index 000000000..f35ccfa1a --- /dev/null +++ b/esp32s2/src/wifi/filter_bank/mask_high.rs @@ -0,0 +1,62 @@ +#[doc = "Register `MASK_HIGH%s` reader"] +pub type R = crate::R; +#[doc = "Register `MASK_HIGH%s` writer"] +pub type W = crate::W; +#[doc = "Field `MASK` reader - "] +pub type MASK_R = crate::FieldReader; +#[doc = "Field `MASK` writer - "] +pub type MASK_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `ENABLED` reader - "] +pub type ENABLED_R = crate::BitReader; +#[doc = "Field `ENABLED` writer - "] +pub type ENABLED_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn mask(&self) -> MASK_R { + MASK_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn enabled(&self) -> ENABLED_R { + ENABLED_R::new(((self.bits >> 16) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MASK_HIGH") + .field("mask", &self.mask()) + .field("enabled", &self.enabled()) + .finish() + } +} +impl W { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn mask(&mut self) -> MASK_W { + MASK_W::new(self, 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn enabled(&mut self) -> ENABLED_W { + ENABLED_W::new(self, 16) + } +} +#[doc = "last 2 bytes of BSSID MAC address filter mask\n\nYou can [`read`](crate::Reg::read) this register and get [`mask_high::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mask_high::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MASK_HIGH_SPEC; +impl crate::RegisterSpec for MASK_HIGH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mask_high::R`](R) reader structure"] +impl crate::Readable for MASK_HIGH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mask_high::W`](W) writer structure"] +impl crate::Writable for MASK_HIGH_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MASK_HIGH%s to value 0"] +impl crate::Resettable for MASK_HIGH_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32s2/src/wifi/filter_bank/mask_low.rs b/esp32s2/src/wifi/filter_bank/mask_low.rs new file mode 100644 index 000000000..db9554f12 --- /dev/null +++ b/esp32s2/src/wifi/filter_bank/mask_low.rs @@ -0,0 +1,28 @@ +#[doc = "Register `MASK_LOW%s` reader"] +pub type R = crate::R; +#[doc = "Register `MASK_LOW%s` writer"] +pub type W = crate::W; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "First 4 bytes of BSSID MAC address filter mask\n\nYou can [`read`](crate::Reg::read) this register and get [`mask_low::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mask_low::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MASK_LOW_SPEC; +impl crate::RegisterSpec for MASK_LOW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mask_low::R`](R) reader structure"] +impl crate::Readable for MASK_LOW_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mask_low::W`](W) writer structure"] +impl crate::Writable for MASK_LOW_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MASK_LOW%s to value 0"] +impl crate::Resettable for MASK_LOW_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32s2/src/wifi/ht_sig.rs b/esp32s2/src/wifi/ht_sig.rs new file mode 100644 index 000000000..9801fb009 --- /dev/null +++ b/esp32s2/src/wifi/ht_sig.rs @@ -0,0 +1,28 @@ +#[doc = "Register `HT_SIG%s` reader"] +pub type R = crate::R; +#[doc = "Register `HT_SIG%s` writer"] +pub type W = crate::W; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "HT-SIG field in HT preamble\n\nYou can [`read`](crate::Reg::read) this register and get [`ht_sig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ht_sig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HT_SIG_SPEC; +impl crate::RegisterSpec for HT_SIG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ht_sig::R`](R) reader structure"] +impl crate::Readable for HT_SIG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ht_sig::W`](W) writer structure"] +impl crate::Writable for HT_SIG_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets HT_SIG%s to value 0"] +impl crate::Resettable for HT_SIG_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32s2/src/wifi/ht_unknown.rs b/esp32s2/src/wifi/ht_unknown.rs new file mode 100644 index 000000000..a447a3b1b --- /dev/null +++ b/esp32s2/src/wifi/ht_unknown.rs @@ -0,0 +1,47 @@ +#[doc = "Register `HT_UNKNOWN%s` reader"] +pub type R = crate::R; +#[doc = "Register `HT_UNKNOWN%s` writer"] +pub type W = crate::W; +#[doc = "Field `LENGTH` reader - The length of the PPDU"] +pub type LENGTH_R = crate::FieldReader; +#[doc = "Field `LENGTH` writer - The length of the PPDU"] +pub type LENGTH_W<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>; +impl R { + #[doc = "Bits 0:19 - The length of the PPDU"] + #[inline(always)] + pub fn length(&self) -> LENGTH_R { + LENGTH_R::new(self.bits & 0x000f_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HT_UNKNOWN") + .field("length", &self.length()) + .finish() + } +} +impl W { + #[doc = "Bits 0:19 - The length of the PPDU"] + #[inline(always)] + pub fn length(&mut self) -> LENGTH_W { + LENGTH_W::new(self, 0) + } +} +#[doc = "exact meaning and name unknown, related to HT\n\nYou can [`read`](crate::Reg::read) this register and get [`ht_unknown::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ht_unknown::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HT_UNKNOWN_SPEC; +impl crate::RegisterSpec for HT_UNKNOWN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ht_unknown::R`](R) reader structure"] +impl crate::Readable for HT_UNKNOWN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ht_unknown::W`](W) writer structure"] +impl crate::Writable for HT_UNKNOWN_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets HT_UNKNOWN%s to value 0"] +impl crate::Resettable for HT_UNKNOWN_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32s2/src/wifi/interface_rx_control.rs b/esp32s2/src/wifi/interface_rx_control.rs new file mode 100644 index 000000000..a79916d98 --- /dev/null +++ b/esp32s2/src/wifi/interface_rx_control.rs @@ -0,0 +1,77 @@ +#[doc = "Register `INTERFACE_RX_CONTROL%s` reader"] +pub type R = crate::R; +#[doc = "Register `INTERFACE_RX_CONTROL%s` writer"] +pub type W = crate::W; +#[doc = "Field `BSSID_CHECK` reader - Check BSSID for filtering"] +pub type BSSID_CHECK_R = crate::BitReader; +#[doc = "Field `BSSID_CHECK` writer - Check BSSID for filtering"] +pub type BSSID_CHECK_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SCAN_MODE` reader - Receive beacon frames"] +pub type SCAN_MODE_R = crate::BitReader; +#[doc = "Field `SCAN_MODE` writer - Receive beacon frames"] +pub type SCAN_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DATA_AND_MGMT_MODE` reader - Receive everything except control frames"] +pub type DATA_AND_MGMT_MODE_R = crate::BitReader; +#[doc = "Field `DATA_AND_MGMT_MODE` writer - Receive everything except control frames"] +pub type DATA_AND_MGMT_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 1 - Check BSSID for filtering"] + #[inline(always)] + pub fn bssid_check(&self) -> BSSID_CHECK_R { + BSSID_CHECK_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 4 - Receive beacon frames"] + #[inline(always)] + pub fn scan_mode(&self) -> SCAN_MODE_R { + SCAN_MODE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 8 - Receive everything except control frames"] + #[inline(always)] + pub fn data_and_mgmt_mode(&self) -> DATA_AND_MGMT_MODE_R { + DATA_AND_MGMT_MODE_R::new(((self.bits >> 8) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INTERFACE_RX_CONTROL") + .field("bssid_check", &self.bssid_check()) + .field("scan_mode", &self.scan_mode()) + .field("data_and_mgmt_mode", &self.data_and_mgmt_mode()) + .finish() + } +} +impl W { + #[doc = "Bit 1 - Check BSSID for filtering"] + #[inline(always)] + pub fn bssid_check(&mut self) -> BSSID_CHECK_W { + BSSID_CHECK_W::new(self, 1) + } + #[doc = "Bit 4 - Receive beacon frames"] + #[inline(always)] + pub fn scan_mode(&mut self) -> SCAN_MODE_W { + SCAN_MODE_W::new(self, 4) + } + #[doc = "Bit 8 - Receive everything except control frames"] + #[inline(always)] + pub fn data_and_mgmt_mode(&mut self) -> DATA_AND_MGMT_MODE_W { + DATA_AND_MGMT_MODE_W::new(self, 8) + } +} +#[doc = "Controls RX for an interface\n\nYou can [`read`](crate::Reg::read) this register and get [`interface_rx_control::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interface_rx_control::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTERFACE_RX_CONTROL_SPEC; +impl crate::RegisterSpec for INTERFACE_RX_CONTROL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`interface_rx_control::R`](R) reader structure"] +impl crate::Readable for INTERFACE_RX_CONTROL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`interface_rx_control::W`](W) writer structure"] +impl crate::Writable for INTERFACE_RX_CONTROL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INTERFACE_RX_CONTROL%s to value 0"] +impl crate::Resettable for INTERFACE_RX_CONTROL_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32s2/src/wifi/mac_interrupt.rs b/esp32s2/src/wifi/mac_interrupt.rs new file mode 100644 index 000000000..cac6361c0 --- /dev/null +++ b/esp32s2/src/wifi/mac_interrupt.rs @@ -0,0 +1,27 @@ +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +#[doc = "Status and clear for the WIFI_MAC interrupt"] +pub struct MAC_INTERRUPT { + wifi_int_status: WIFI_INT_STATUS, + wifi_int_clear: WIFI_INT_CLEAR, +} +impl MAC_INTERRUPT { + #[doc = "0x00 - Interrupt status of WIFI peripheral"] + #[inline(always)] + pub const fn wifi_int_status(&self) -> &WIFI_INT_STATUS { + &self.wifi_int_status + } + #[doc = "0x04 - Interrupt status clear of WIFI peripheral"] + #[inline(always)] + pub const fn wifi_int_clear(&self) -> &WIFI_INT_CLEAR { + &self.wifi_int_clear + } +} +#[doc = "WIFI_INT_STATUS (rw) register accessor: Interrupt status of WIFI peripheral\n\nYou can [`read`](crate::Reg::read) this register and get [`wifi_int_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wifi_int_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wifi_int_status`] module"] +pub type WIFI_INT_STATUS = crate::Reg; +#[doc = "Interrupt status of WIFI peripheral"] +pub mod wifi_int_status; +#[doc = "WIFI_INT_CLEAR (rw) register accessor: Interrupt status clear of WIFI peripheral\n\nYou can [`read`](crate::Reg::read) this register and get [`wifi_int_clear::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wifi_int_clear::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wifi_int_clear`] module"] +pub type WIFI_INT_CLEAR = crate::Reg; +#[doc = "Interrupt status clear of WIFI peripheral"] +pub mod wifi_int_clear; diff --git a/esp32s2/src/wifi/mac_interrupt/wifi_int_clear.rs b/esp32s2/src/wifi/mac_interrupt/wifi_int_clear.rs new file mode 100644 index 000000000..691fb12a0 --- /dev/null +++ b/esp32s2/src/wifi/mac_interrupt/wifi_int_clear.rs @@ -0,0 +1,28 @@ +#[doc = "Register `WIFI_INT_CLEAR` reader"] +pub type R = crate::R; +#[doc = "Register `WIFI_INT_CLEAR` writer"] +pub type W = crate::W; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Interrupt status clear of WIFI peripheral\n\nYou can [`read`](crate::Reg::read) this register and get [`wifi_int_clear::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wifi_int_clear::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WIFI_INT_CLEAR_SPEC; +impl crate::RegisterSpec for WIFI_INT_CLEAR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`wifi_int_clear::R`](R) reader structure"] +impl crate::Readable for WIFI_INT_CLEAR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`wifi_int_clear::W`](W) writer structure"] +impl crate::Writable for WIFI_INT_CLEAR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets WIFI_INT_CLEAR to value 0"] +impl crate::Resettable for WIFI_INT_CLEAR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32s2/src/wifi/mac_interrupt/wifi_int_status.rs b/esp32s2/src/wifi/mac_interrupt/wifi_int_status.rs new file mode 100644 index 000000000..a0f172405 --- /dev/null +++ b/esp32s2/src/wifi/mac_interrupt/wifi_int_status.rs @@ -0,0 +1,28 @@ +#[doc = "Register `WIFI_INT_STATUS` reader"] +pub type R = crate::R; +#[doc = "Register `WIFI_INT_STATUS` writer"] +pub type W = crate::W; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Interrupt status of WIFI peripheral\n\nYou can [`read`](crate::Reg::read) this register and get [`wifi_int_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wifi_int_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WIFI_INT_STATUS_SPEC; +impl crate::RegisterSpec for WIFI_INT_STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`wifi_int_status::R`](R) reader structure"] +impl crate::Readable for WIFI_INT_STATUS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`wifi_int_status::W`](W) writer structure"] +impl crate::Writable for WIFI_INT_STATUS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets WIFI_INT_STATUS to value 0"] +impl crate::Resettable for WIFI_INT_STATUS_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32s2/src/wifi/plcp1.rs b/esp32s2/src/wifi/plcp1.rs new file mode 100644 index 000000000..a0b87f20a --- /dev/null +++ b/esp32s2/src/wifi/plcp1.rs @@ -0,0 +1,122 @@ +#[doc = "Register `PLCP1%s` reader"] +pub type R = crate::R; +#[doc = "Register `PLCP1%s` writer"] +pub type W = crate::W; +#[doc = "Field `LEN` reader - Length of packet (in bytes)"] +pub type LEN_R = crate::FieldReader; +#[doc = "Field `LEN` writer - Length of packet (in bytes)"] +pub type LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +#[doc = "Field `RATE` reader - Packet rate (see wifi_phy_rate_t)"] +pub type RATE_R = crate::FieldReader; +#[doc = "Field `RATE` writer - Packet rate (see wifi_phy_rate_t)"] +pub type RATE_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `KEY_SLOT_ID` reader - Key slot to use for encryption"] +pub type KEY_SLOT_ID_R = crate::FieldReader; +#[doc = "Field `KEY_SLOT_ID` writer - Key slot to use for encryption"] +pub type KEY_SLOT_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `IS_80211_N` reader - Bit indicating if this is 802.11n"] +pub type IS_80211_N_R = crate::BitReader; +#[doc = "Field `IS_80211_N` writer - Bit indicating if this is 802.11n"] +pub type IS_80211_N_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BANDWIDTH` reader - Zero indicates 20MHz and one indicates 40MHz"] +pub type BANDWIDTH_R = crate::BitReader; +#[doc = "Field `BANDWIDTH` writer - Zero indicates 20MHz and one indicates 40MHz"] +pub type BANDWIDTH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INTERFACE_ID` reader - ID of the interface this transmission is from"] +pub type INTERFACE_ID_R = crate::FieldReader; +#[doc = "Field `INTERFACE_ID` writer - ID of the interface this transmission is from"] +pub type INTERFACE_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:11 - Length of packet (in bytes)"] + #[inline(always)] + pub fn len(&self) -> LEN_R { + LEN_R::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bits 12:16 - Packet rate (see wifi_phy_rate_t)"] + #[inline(always)] + pub fn rate(&self) -> RATE_R { + RATE_R::new(((self.bits >> 12) & 0x1f) as u8) + } + #[doc = "Bits 17:21 - Key slot to use for encryption"] + #[inline(always)] + pub fn key_slot_id(&self) -> KEY_SLOT_ID_R { + KEY_SLOT_ID_R::new(((self.bits >> 17) & 0x1f) as u8) + } + #[doc = "Bit 25 - Bit indicating if this is 802.11n"] + #[inline(always)] + pub fn is_80211_n(&self) -> IS_80211_N_R { + IS_80211_N_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 28 - Zero indicates 20MHz and one indicates 40MHz"] + #[inline(always)] + pub fn bandwidth(&self) -> BANDWIDTH_R { + BANDWIDTH_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bits 30:31 - ID of the interface this transmission is from"] + #[inline(always)] + pub fn interface_id(&self) -> INTERFACE_ID_R { + INTERFACE_ID_R::new(((self.bits >> 30) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PLCP1") + .field("len", &self.len()) + .field("rate", &self.rate()) + .field("key_slot_id", &self.key_slot_id()) + .field("is_80211_n", &self.is_80211_n()) + .field("bandwidth", &self.bandwidth()) + .field("interface_id", &self.interface_id()) + .finish() + } +} +impl W { + #[doc = "Bits 0:11 - Length of packet (in bytes)"] + #[inline(always)] + pub fn len(&mut self) -> LEN_W { + LEN_W::new(self, 0) + } + #[doc = "Bits 12:16 - Packet rate (see wifi_phy_rate_t)"] + #[inline(always)] + pub fn rate(&mut self) -> RATE_W { + RATE_W::new(self, 12) + } + #[doc = "Bits 17:21 - Key slot to use for encryption"] + #[inline(always)] + pub fn key_slot_id(&mut self) -> KEY_SLOT_ID_W { + KEY_SLOT_ID_W::new(self, 17) + } + #[doc = "Bit 25 - Bit indicating if this is 802.11n"] + #[inline(always)] + pub fn is_80211_n(&mut self) -> IS_80211_N_W { + IS_80211_N_W::new(self, 25) + } + #[doc = "Bit 28 - Zero indicates 20MHz and one indicates 40MHz"] + #[inline(always)] + pub fn bandwidth(&mut self) -> BANDWIDTH_W { + BANDWIDTH_W::new(self, 28) + } + #[doc = "Bits 30:31 - ID of the interface this transmission is from"] + #[inline(always)] + pub fn interface_id(&mut self) -> INTERFACE_ID_W { + INTERFACE_ID_W::new(self, 30) + } +} +#[doc = "PLCP1\n\nYou can [`read`](crate::Reg::read) this register and get [`plcp1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`plcp1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PLCP1_SPEC; +impl crate::RegisterSpec for PLCP1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`plcp1::R`](R) reader structure"] +impl crate::Readable for PLCP1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`plcp1::W`](W) writer structure"] +impl crate::Writable for PLCP1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PLCP1%s to value 0"] +impl crate::Resettable for PLCP1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32s2/src/wifi/plcp2.rs b/esp32s2/src/wifi/plcp2.rs new file mode 100644 index 000000000..330aef254 --- /dev/null +++ b/esp32s2/src/wifi/plcp2.rs @@ -0,0 +1,47 @@ +#[doc = "Register `PLCP2%s` reader"] +pub type R = crate::R; +#[doc = "Register `PLCP2%s` writer"] +pub type W = crate::W; +#[doc = "Field `UNKNOWN` reader - meaning unknown, set to one for TX"] +pub type UNKNOWN_R = crate::BitReader; +#[doc = "Field `UNKNOWN` writer - meaning unknown, set to one for TX"] +pub type UNKNOWN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 5 - meaning unknown, set to one for TX"] + #[inline(always)] + pub fn unknown(&self) -> UNKNOWN_R { + UNKNOWN_R::new(((self.bits >> 5) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PLCP2") + .field("unknown", &self.unknown()) + .finish() + } +} +impl W { + #[doc = "Bit 5 - meaning unknown, set to one for TX"] + #[inline(always)] + pub fn unknown(&mut self) -> UNKNOWN_W { + UNKNOWN_W::new(self, 5) + } +} +#[doc = "PLCP2\n\nYou can [`read`](crate::Reg::read) this register and get [`plcp2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`plcp2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PLCP2_SPEC; +impl crate::RegisterSpec for PLCP2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`plcp2::R`](R) reader structure"] +impl crate::Readable for PLCP2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`plcp2::W`](W) writer structure"] +impl crate::Writable for PLCP2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PLCP2%s to value 0"] +impl crate::Resettable for PLCP2_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32s2/src/wifi/pmd.rs b/esp32s2/src/wifi/pmd.rs new file mode 100644 index 000000000..db78b5e20 --- /dev/null +++ b/esp32s2/src/wifi/pmd.rs @@ -0,0 +1,28 @@ +#[doc = "Register `PMD%s` reader"] +pub type R = crate::R; +#[doc = "Register `PMD%s` writer"] +pub type W = crate::W; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`pmd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pmd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PMD_SPEC; +impl crate::RegisterSpec for PMD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pmd::R`](R) reader structure"] +impl crate::Readable for PMD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pmd::W`](W) writer structure"] +impl crate::Writable for PMD_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PMD%s to value 0"] +impl crate::Resettable for PMD_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32s2/src/wifi/pwr_interrupt.rs b/esp32s2/src/wifi/pwr_interrupt.rs new file mode 100644 index 000000000..da65cc301 --- /dev/null +++ b/esp32s2/src/wifi/pwr_interrupt.rs @@ -0,0 +1,27 @@ +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +#[doc = "Status and clear for the WIFI_PWR interrupt"] +pub struct PWR_INTERRUPT { + pwr_int_status: PWR_INT_STATUS, + pwr_int_clear: PWR_INT_CLEAR, +} +impl PWR_INTERRUPT { + #[doc = "0x00 - Interrupt status for the WIFI_PWR interrupt"] + #[inline(always)] + pub const fn pwr_int_status(&self) -> &PWR_INT_STATUS { + &self.pwr_int_status + } + #[doc = "0x04 - Interrupt status clear for the WIFI_PWR interrupt"] + #[inline(always)] + pub const fn pwr_int_clear(&self) -> &PWR_INT_CLEAR { + &self.pwr_int_clear + } +} +#[doc = "PWR_INT_STATUS (rw) register accessor: Interrupt status for the WIFI_PWR interrupt\n\nYou can [`read`](crate::Reg::read) this register and get [`pwr_int_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwr_int_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwr_int_status`] module"] +pub type PWR_INT_STATUS = crate::Reg; +#[doc = "Interrupt status for the WIFI_PWR interrupt"] +pub mod pwr_int_status; +#[doc = "PWR_INT_CLEAR (rw) register accessor: Interrupt status clear for the WIFI_PWR interrupt\n\nYou can [`read`](crate::Reg::read) this register and get [`pwr_int_clear::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwr_int_clear::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwr_int_clear`] module"] +pub type PWR_INT_CLEAR = crate::Reg; +#[doc = "Interrupt status clear for the WIFI_PWR interrupt"] +pub mod pwr_int_clear; diff --git a/esp32s2/src/wifi/pwr_interrupt/pwr_int_clear.rs b/esp32s2/src/wifi/pwr_interrupt/pwr_int_clear.rs new file mode 100644 index 000000000..6d2bce981 --- /dev/null +++ b/esp32s2/src/wifi/pwr_interrupt/pwr_int_clear.rs @@ -0,0 +1,28 @@ +#[doc = "Register `PWR_INT_CLEAR` reader"] +pub type R = crate::R; +#[doc = "Register `PWR_INT_CLEAR` writer"] +pub type W = crate::W; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Interrupt status clear for the WIFI_PWR interrupt\n\nYou can [`read`](crate::Reg::read) this register and get [`pwr_int_clear::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwr_int_clear::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PWR_INT_CLEAR_SPEC; +impl crate::RegisterSpec for PWR_INT_CLEAR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pwr_int_clear::R`](R) reader structure"] +impl crate::Readable for PWR_INT_CLEAR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pwr_int_clear::W`](W) writer structure"] +impl crate::Writable for PWR_INT_CLEAR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PWR_INT_CLEAR to value 0"] +impl crate::Resettable for PWR_INT_CLEAR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32s2/src/wifi/pwr_interrupt/pwr_int_status.rs b/esp32s2/src/wifi/pwr_interrupt/pwr_int_status.rs new file mode 100644 index 000000000..2c226edb7 --- /dev/null +++ b/esp32s2/src/wifi/pwr_interrupt/pwr_int_status.rs @@ -0,0 +1,28 @@ +#[doc = "Register `PWR_INT_STATUS` reader"] +pub type R = crate::R; +#[doc = "Register `PWR_INT_STATUS` writer"] +pub type W = crate::W; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Interrupt status for the WIFI_PWR interrupt\n\nYou can [`read`](crate::Reg::read) this register and get [`pwr_int_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwr_int_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PWR_INT_STATUS_SPEC; +impl crate::RegisterSpec for PWR_INT_STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pwr_int_status::R`](R) reader structure"] +impl crate::Readable for PWR_INT_STATUS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pwr_int_status::W`](W) writer structure"] +impl crate::Writable for PWR_INT_STATUS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PWR_INT_STATUS to value 0"] +impl crate::Resettable for PWR_INT_STATUS_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32s2/src/wifi/rx_ctrl.rs b/esp32s2/src/wifi/rx_ctrl.rs new file mode 100644 index 000000000..299a84e46 --- /dev/null +++ b/esp32s2/src/wifi/rx_ctrl.rs @@ -0,0 +1,62 @@ +#[doc = "Register `RX_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `RX_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `RX_DESCR_RELOAD` reader - Instruct the hardware to reload the RX descriptors"] +pub type RX_DESCR_RELOAD_R = crate::BitReader; +#[doc = "Field `RX_DESCR_RELOAD` writer - Instruct the hardware to reload the RX descriptors"] +pub type RX_DESCR_RELOAD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_ENABLE` reader - Enable frame reception"] +pub type RX_ENABLE_R = crate::BitReader; +#[doc = "Field `RX_ENABLE` writer - Enable frame reception"] +pub type RX_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Instruct the hardware to reload the RX descriptors"] + #[inline(always)] + pub fn rx_descr_reload(&self) -> RX_DESCR_RELOAD_R { + RX_DESCR_RELOAD_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 31 - Enable frame reception"] + #[inline(always)] + pub fn rx_enable(&self) -> RX_ENABLE_R { + RX_ENABLE_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RX_CTRL") + .field("rx_descr_reload", &self.rx_descr_reload()) + .field("rx_enable", &self.rx_enable()) + .finish() + } +} +impl W { + #[doc = "Bit 0 - Instruct the hardware to reload the RX descriptors"] + #[inline(always)] + pub fn rx_descr_reload(&mut self) -> RX_DESCR_RELOAD_W { + RX_DESCR_RELOAD_W::new(self, 0) + } + #[doc = "Bit 31 - Enable frame reception"] + #[inline(always)] + pub fn rx_enable(&mut self) -> RX_ENABLE_W { + RX_ENABLE_W::new(self, 31) + } +} +#[doc = "Controls the reception of frames\n\nYou can [`read`](crate::Reg::read) this register and get [`rx_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RX_CTRL_SPEC; +impl crate::RegisterSpec for RX_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rx_ctrl::R`](R) reader structure"] +impl crate::Readable for RX_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rx_ctrl::W`](W) writer structure"] +impl crate::Writable for RX_CTRL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets RX_CTRL to value 0"] +impl crate::Resettable for RX_CTRL_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32s2/src/wifi/rx_dma_list.rs b/esp32s2/src/wifi/rx_dma_list.rs new file mode 100644 index 000000000..86fe02f79 --- /dev/null +++ b/esp32s2/src/wifi/rx_dma_list.rs @@ -0,0 +1,37 @@ +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +#[doc = "RX_DMA_LIST"] +pub struct RX_DMA_LIST { + rx_descr_base: RX_DESCR_BASE, + rx_descr_next: RX_DESCR_NEXT, + rx_descr_last: RX_DESCR_LAST, +} +impl RX_DMA_LIST { + #[doc = "0x00 - base address of the RX DMA list"] + #[inline(always)] + pub const fn rx_descr_base(&self) -> &RX_DESCR_BASE { + &self.rx_descr_base + } + #[doc = "0x04 - next item in the RX DMA list"] + #[inline(always)] + pub const fn rx_descr_next(&self) -> &RX_DESCR_NEXT { + &self.rx_descr_next + } + #[doc = "0x08 - last item in RX DMA list"] + #[inline(always)] + pub const fn rx_descr_last(&self) -> &RX_DESCR_LAST { + &self.rx_descr_last + } +} +#[doc = "RX_DESCR_BASE (rw) register accessor: base address of the RX DMA list\n\nYou can [`read`](crate::Reg::read) this register and get [`rx_descr_base::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx_descr_base::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_descr_base`] module"] +pub type RX_DESCR_BASE = crate::Reg; +#[doc = "base address of the RX DMA list"] +pub mod rx_descr_base; +#[doc = "RX_DESCR_NEXT (rw) register accessor: next item in the RX DMA list\n\nYou can [`read`](crate::Reg::read) this register and get [`rx_descr_next::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx_descr_next::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_descr_next`] module"] +pub type RX_DESCR_NEXT = crate::Reg; +#[doc = "next item in the RX DMA list"] +pub mod rx_descr_next; +#[doc = "RX_DESCR_LAST (rw) register accessor: last item in RX DMA list\n\nYou can [`read`](crate::Reg::read) this register and get [`rx_descr_last::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx_descr_last::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_descr_last`] module"] +pub type RX_DESCR_LAST = crate::Reg; +#[doc = "last item in RX DMA list"] +pub mod rx_descr_last; diff --git a/esp32s2/src/wifi/rx_dma_list/rx_descr_base.rs b/esp32s2/src/wifi/rx_dma_list/rx_descr_base.rs new file mode 100644 index 000000000..82707cba8 --- /dev/null +++ b/esp32s2/src/wifi/rx_dma_list/rx_descr_base.rs @@ -0,0 +1,28 @@ +#[doc = "Register `RX_DESCR_BASE` reader"] +pub type R = crate::R; +#[doc = "Register `RX_DESCR_BASE` writer"] +pub type W = crate::W; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "base address of the RX DMA list\n\nYou can [`read`](crate::Reg::read) this register and get [`rx_descr_base::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx_descr_base::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RX_DESCR_BASE_SPEC; +impl crate::RegisterSpec for RX_DESCR_BASE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rx_descr_base::R`](R) reader structure"] +impl crate::Readable for RX_DESCR_BASE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rx_descr_base::W`](W) writer structure"] +impl crate::Writable for RX_DESCR_BASE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets RX_DESCR_BASE to value 0"] +impl crate::Resettable for RX_DESCR_BASE_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32s2/src/wifi/rx_dma_list/rx_descr_last.rs b/esp32s2/src/wifi/rx_dma_list/rx_descr_last.rs new file mode 100644 index 000000000..d72fdb89e --- /dev/null +++ b/esp32s2/src/wifi/rx_dma_list/rx_descr_last.rs @@ -0,0 +1,28 @@ +#[doc = "Register `RX_DESCR_LAST` reader"] +pub type R = crate::R; +#[doc = "Register `RX_DESCR_LAST` writer"] +pub type W = crate::W; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "last item in RX DMA list\n\nYou can [`read`](crate::Reg::read) this register and get [`rx_descr_last::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx_descr_last::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RX_DESCR_LAST_SPEC; +impl crate::RegisterSpec for RX_DESCR_LAST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rx_descr_last::R`](R) reader structure"] +impl crate::Readable for RX_DESCR_LAST_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rx_descr_last::W`](W) writer structure"] +impl crate::Writable for RX_DESCR_LAST_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets RX_DESCR_LAST to value 0"] +impl crate::Resettable for RX_DESCR_LAST_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32s2/src/wifi/rx_dma_list/rx_descr_next.rs b/esp32s2/src/wifi/rx_dma_list/rx_descr_next.rs new file mode 100644 index 000000000..5af1d9910 --- /dev/null +++ b/esp32s2/src/wifi/rx_dma_list/rx_descr_next.rs @@ -0,0 +1,28 @@ +#[doc = "Register `RX_DESCR_NEXT` reader"] +pub type R = crate::R; +#[doc = "Register `RX_DESCR_NEXT` writer"] +pub type W = crate::W; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "next item in the RX DMA list\n\nYou can [`read`](crate::Reg::read) this register and get [`rx_descr_next::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx_descr_next::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RX_DESCR_NEXT_SPEC; +impl crate::RegisterSpec for RX_DESCR_NEXT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rx_descr_next::R`](R) reader structure"] +impl crate::Readable for RX_DESCR_NEXT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rx_descr_next::W`](W) writer structure"] +impl crate::Writable for RX_DESCR_NEXT_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets RX_DESCR_NEXT to value 0"] +impl crate::Resettable for RX_DESCR_NEXT_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32s2/src/wifi/tx_slot_config.rs b/esp32s2/src/wifi/tx_slot_config.rs new file mode 100644 index 000000000..0be327650 --- /dev/null +++ b/esp32s2/src/wifi/tx_slot_config.rs @@ -0,0 +1,27 @@ +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +#[doc = "Used to configure the TX slot."] +pub struct TX_SLOT_CONFIG { + config: CONFIG, + plcp0: PLCP0, +} +impl TX_SLOT_CONFIG { + #[doc = "0x00 - Config"] + #[inline(always)] + pub const fn config(&self) -> &CONFIG { + &self.config + } + #[doc = "0x04 - PLCP0"] + #[inline(always)] + pub const fn plcp0(&self) -> &PLCP0 { + &self.plcp0 + } +} +#[doc = "CONFIG (rw) register accessor: Config\n\nYou can [`read`](crate::Reg::read) this register and get [`config::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`config::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@config`] module"] +pub type CONFIG = crate::Reg; +#[doc = "Config"] +pub mod config; +#[doc = "PLCP0 (rw) register accessor: PLCP0\n\nYou can [`read`](crate::Reg::read) this register and get [`plcp0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`plcp0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@plcp0`] module"] +pub type PLCP0 = crate::Reg; +#[doc = "PLCP0"] +pub mod plcp0; diff --git a/esp32s2/src/wifi/tx_slot_config/config.rs b/esp32s2/src/wifi/tx_slot_config/config.rs new file mode 100644 index 000000000..abd5d6adf --- /dev/null +++ b/esp32s2/src/wifi/tx_slot_config/config.rs @@ -0,0 +1,77 @@ +#[doc = "Register `CONFIG` reader"] +pub type R = crate::R; +#[doc = "Register `CONFIG` writer"] +pub type W = crate::W; +#[doc = "Field `TIMEOUT` reader - "] +pub type TIMEOUT_R = crate::FieldReader; +#[doc = "Field `TIMEOUT` writer - "] +pub type TIMEOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +#[doc = "Field `BACKOFF_TIME` reader - "] +pub type BACKOFF_TIME_R = crate::FieldReader; +#[doc = "Field `BACKOFF_TIME` writer - "] +pub type BACKOFF_TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +#[doc = "Field `AIFSN` reader - "] +pub type AIFSN_R = crate::FieldReader; +#[doc = "Field `AIFSN` writer - "] +pub type AIFSN_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:11"] + #[inline(always)] + pub fn timeout(&self) -> TIMEOUT_R { + TIMEOUT_R::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bits 12:21"] + #[inline(always)] + pub fn backoff_time(&self) -> BACKOFF_TIME_R { + BACKOFF_TIME_R::new(((self.bits >> 12) & 0x03ff) as u16) + } + #[doc = "Bits 24:27"] + #[inline(always)] + pub fn aifsn(&self) -> AIFSN_R { + AIFSN_R::new(((self.bits >> 24) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CONFIG") + .field("timeout", &self.timeout()) + .field("backoff_time", &self.backoff_time()) + .field("aifsn", &self.aifsn()) + .finish() + } +} +impl W { + #[doc = "Bits 0:11"] + #[inline(always)] + pub fn timeout(&mut self) -> TIMEOUT_W { + TIMEOUT_W::new(self, 0) + } + #[doc = "Bits 12:21"] + #[inline(always)] + pub fn backoff_time(&mut self) -> BACKOFF_TIME_W { + BACKOFF_TIME_W::new(self, 12) + } + #[doc = "Bits 24:27"] + #[inline(always)] + pub fn aifsn(&mut self) -> AIFSN_W { + AIFSN_W::new(self, 24) + } +} +#[doc = "Config\n\nYou can [`read`](crate::Reg::read) this register and get [`config::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`config::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CONFIG_SPEC; +impl crate::RegisterSpec for CONFIG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`config::R`](R) reader structure"] +impl crate::Readable for CONFIG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`config::W`](W) writer structure"] +impl crate::Writable for CONFIG_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CONFIG to value 0"] +impl crate::Resettable for CONFIG_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32s2/src/wifi/tx_slot_config/plcp0.rs b/esp32s2/src/wifi/tx_slot_config/plcp0.rs new file mode 100644 index 000000000..c8f4e5a73 --- /dev/null +++ b/esp32s2/src/wifi/tx_slot_config/plcp0.rs @@ -0,0 +1,92 @@ +#[doc = "Register `PLCP0` reader"] +pub type R = crate::R; +#[doc = "Register `PLCP0` writer"] +pub type W = crate::W; +#[doc = "Field `DMA_ADDR` reader - Bottom bits of address of dma_item"] +pub type DMA_ADDR_R = crate::FieldReader; +#[doc = "Field `DMA_ADDR` writer - Bottom bits of address of dma_item"] +pub type DMA_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>; +#[doc = "Field `WAIT_FOR_ACK` reader - Enables ACK timeouts"] +pub type WAIT_FOR_ACK_R = crate::BitReader; +#[doc = "Field `WAIT_FOR_ACK` writer - Enables ACK timeouts"] +pub type WAIT_FOR_ACK_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SLOT_VALID` reader - Marks this slot as valid"] +pub type SLOT_VALID_R = crate::BitReader; +#[doc = "Field `SLOT_VALID` writer - Marks this slot as valid"] +pub type SLOT_VALID_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SLOT_ENABLED` reader - Marks this slot as ready for transmission"] +pub type SLOT_ENABLED_R = crate::BitReader; +#[doc = "Field `SLOT_ENABLED` writer - Marks this slot as ready for transmission"] +pub type SLOT_ENABLED_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:19 - Bottom bits of address of dma_item"] + #[inline(always)] + pub fn dma_addr(&self) -> DMA_ADDR_R { + DMA_ADDR_R::new(self.bits & 0x000f_ffff) + } + #[doc = "Bit 28 - Enables ACK timeouts"] + #[inline(always)] + pub fn wait_for_ack(&self) -> WAIT_FOR_ACK_R { + WAIT_FOR_ACK_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 30 - Marks this slot as valid"] + #[inline(always)] + pub fn slot_valid(&self) -> SLOT_VALID_R { + SLOT_VALID_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Marks this slot as ready for transmission"] + #[inline(always)] + pub fn slot_enabled(&self) -> SLOT_ENABLED_R { + SLOT_ENABLED_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PLCP0") + .field("dma_addr", &self.dma_addr()) + .field("wait_for_ack", &self.wait_for_ack()) + .field("slot_valid", &self.slot_valid()) + .field("slot_enabled", &self.slot_enabled()) + .finish() + } +} +impl W { + #[doc = "Bits 0:19 - Bottom bits of address of dma_item"] + #[inline(always)] + pub fn dma_addr(&mut self) -> DMA_ADDR_W { + DMA_ADDR_W::new(self, 0) + } + #[doc = "Bit 28 - Enables ACK timeouts"] + #[inline(always)] + pub fn wait_for_ack(&mut self) -> WAIT_FOR_ACK_W { + WAIT_FOR_ACK_W::new(self, 28) + } + #[doc = "Bit 30 - Marks this slot as valid"] + #[inline(always)] + pub fn slot_valid(&mut self) -> SLOT_VALID_W { + SLOT_VALID_W::new(self, 30) + } + #[doc = "Bit 31 - Marks this slot as ready for transmission"] + #[inline(always)] + pub fn slot_enabled(&mut self) -> SLOT_ENABLED_W { + SLOT_ENABLED_W::new(self, 31) + } +} +#[doc = "PLCP0\n\nYou can [`read`](crate::Reg::read) this register and get [`plcp0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`plcp0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PLCP0_SPEC; +impl crate::RegisterSpec for PLCP0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`plcp0::R`](R) reader structure"] +impl crate::Readable for PLCP0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`plcp0::W`](W) writer structure"] +impl crate::Writable for PLCP0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PLCP0 to value 0"] +impl crate::Resettable for PLCP0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32s2/src/wifi/txq_state.rs b/esp32s2/src/wifi/txq_state.rs new file mode 100644 index 000000000..57fa611b2 --- /dev/null +++ b/esp32s2/src/wifi/txq_state.rs @@ -0,0 +1,47 @@ +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +#[doc = "State of transmission queues"] +pub struct TXQ_STATE { + tx_error_clear: TX_ERROR_CLEAR, + tx_error_status: TX_ERROR_STATUS, + tx_complete_clear: TX_COMPLETE_CLEAR, + tx_complete_status: TX_COMPLETE_STATUS, +} +impl TXQ_STATE { + #[doc = "0x00 - Clear the error status of a slot"] + #[inline(always)] + pub const fn tx_error_clear(&self) -> &TX_ERROR_CLEAR { + &self.tx_error_clear + } + #[doc = "0x04 - Error status of a slot"] + #[inline(always)] + pub const fn tx_error_status(&self) -> &TX_ERROR_STATUS { + &self.tx_error_status + } + #[doc = "0x08 - Clear the completion status of a slot"] + #[inline(always)] + pub const fn tx_complete_clear(&self) -> &TX_COMPLETE_CLEAR { + &self.tx_complete_clear + } + #[doc = "0x0c - Completion status of a slot"] + #[inline(always)] + pub const fn tx_complete_status(&self) -> &TX_COMPLETE_STATUS { + &self.tx_complete_status + } +} +#[doc = "TX_ERROR_CLEAR (rw) register accessor: Clear the error status of a slot\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_error_clear::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_error_clear::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_error_clear`] module"] +pub type TX_ERROR_CLEAR = crate::Reg; +#[doc = "Clear the error status of a slot"] +pub mod tx_error_clear; +#[doc = "TX_ERROR_STATUS (rw) register accessor: Error status of a slot\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_error_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_error_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_error_status`] module"] +pub type TX_ERROR_STATUS = crate::Reg; +#[doc = "Error status of a slot"] +pub mod tx_error_status; +#[doc = "TX_COMPLETE_CLEAR (rw) register accessor: Clear the completion status of a slot\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_complete_clear::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_complete_clear::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_complete_clear`] module"] +pub type TX_COMPLETE_CLEAR = crate::Reg; +#[doc = "Clear the completion status of a slot"] +pub mod tx_complete_clear; +#[doc = "TX_COMPLETE_STATUS (rw) register accessor: Completion status of a slot\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_complete_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_complete_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_complete_status`] module"] +pub type TX_COMPLETE_STATUS = crate::Reg; +#[doc = "Completion status of a slot"] +pub mod tx_complete_status; diff --git a/esp32s2/src/wifi/txq_state/tx_complete_clear.rs b/esp32s2/src/wifi/txq_state/tx_complete_clear.rs new file mode 100644 index 000000000..b9e394c5b --- /dev/null +++ b/esp32s2/src/wifi/txq_state/tx_complete_clear.rs @@ -0,0 +1,47 @@ +#[doc = "Register `TX_COMPLETE_CLEAR` reader"] +pub type R = crate::R; +#[doc = "Register `TX_COMPLETE_CLEAR` writer"] +pub type W = crate::W; +#[doc = "Field `SLOTS` reader - "] +pub type SLOTS_R = crate::FieldReader; +#[doc = "Field `SLOTS` writer - "] +pub type SLOTS_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +impl R { + #[doc = "Bits 0:4"] + #[inline(always)] + pub fn slots(&self) -> SLOTS_R { + SLOTS_R::new((self.bits & 0x1f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TX_COMPLETE_CLEAR") + .field("slots", &self.slots()) + .finish() + } +} +impl W { + #[doc = "Bits 0:4"] + #[inline(always)] + pub fn slots(&mut self) -> SLOTS_W { + SLOTS_W::new(self, 0) + } +} +#[doc = "Clear the completion status of a slot\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_complete_clear::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_complete_clear::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TX_COMPLETE_CLEAR_SPEC; +impl crate::RegisterSpec for TX_COMPLETE_CLEAR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`tx_complete_clear::R`](R) reader structure"] +impl crate::Readable for TX_COMPLETE_CLEAR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tx_complete_clear::W`](W) writer structure"] +impl crate::Writable for TX_COMPLETE_CLEAR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TX_COMPLETE_CLEAR to value 0"] +impl crate::Resettable for TX_COMPLETE_CLEAR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32s2/src/wifi/txq_state/tx_complete_status.rs b/esp32s2/src/wifi/txq_state/tx_complete_status.rs new file mode 100644 index 000000000..9da99f9fa --- /dev/null +++ b/esp32s2/src/wifi/txq_state/tx_complete_status.rs @@ -0,0 +1,47 @@ +#[doc = "Register `TX_COMPLETE_STATUS` reader"] +pub type R = crate::R; +#[doc = "Register `TX_COMPLETE_STATUS` writer"] +pub type W = crate::W; +#[doc = "Field `SLOTS` reader - "] +pub type SLOTS_R = crate::FieldReader; +#[doc = "Field `SLOTS` writer - "] +pub type SLOTS_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +impl R { + #[doc = "Bits 0:4"] + #[inline(always)] + pub fn slots(&self) -> SLOTS_R { + SLOTS_R::new((self.bits & 0x1f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TX_COMPLETE_STATUS") + .field("slots", &self.slots()) + .finish() + } +} +impl W { + #[doc = "Bits 0:4"] + #[inline(always)] + pub fn slots(&mut self) -> SLOTS_W { + SLOTS_W::new(self, 0) + } +} +#[doc = "Completion status of a slot\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_complete_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_complete_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TX_COMPLETE_STATUS_SPEC; +impl crate::RegisterSpec for TX_COMPLETE_STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`tx_complete_status::R`](R) reader structure"] +impl crate::Readable for TX_COMPLETE_STATUS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tx_complete_status::W`](W) writer structure"] +impl crate::Writable for TX_COMPLETE_STATUS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TX_COMPLETE_STATUS to value 0"] +impl crate::Resettable for TX_COMPLETE_STATUS_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32s2/src/wifi/txq_state/tx_error_clear.rs b/esp32s2/src/wifi/txq_state/tx_error_clear.rs new file mode 100644 index 000000000..9bc5c4cc7 --- /dev/null +++ b/esp32s2/src/wifi/txq_state/tx_error_clear.rs @@ -0,0 +1,62 @@ +#[doc = "Register `TX_ERROR_CLEAR` reader"] +pub type R = crate::R; +#[doc = "Register `TX_ERROR_CLEAR` writer"] +pub type W = crate::W; +#[doc = "Field `SLOT_COLLISION` reader - "] +pub type SLOT_COLLISION_R = crate::FieldReader; +#[doc = "Field `SLOT_COLLISION` writer - "] +pub type SLOT_COLLISION_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `SLOT_TIMEOUT` reader - "] +pub type SLOT_TIMEOUT_R = crate::FieldReader; +#[doc = "Field `SLOT_TIMEOUT` writer - "] +pub type SLOT_TIMEOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +impl R { + #[doc = "Bits 0:4"] + #[inline(always)] + pub fn slot_collision(&self) -> SLOT_COLLISION_R { + SLOT_COLLISION_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 16:20"] + #[inline(always)] + pub fn slot_timeout(&self) -> SLOT_TIMEOUT_R { + SLOT_TIMEOUT_R::new(((self.bits >> 16) & 0x1f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TX_ERROR_CLEAR") + .field("slot_collision", &self.slot_collision()) + .field("slot_timeout", &self.slot_timeout()) + .finish() + } +} +impl W { + #[doc = "Bits 0:4"] + #[inline(always)] + pub fn slot_collision(&mut self) -> SLOT_COLLISION_W { + SLOT_COLLISION_W::new(self, 0) + } + #[doc = "Bits 16:20"] + #[inline(always)] + pub fn slot_timeout(&mut self) -> SLOT_TIMEOUT_W { + SLOT_TIMEOUT_W::new(self, 16) + } +} +#[doc = "Clear the error status of a slot\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_error_clear::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_error_clear::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TX_ERROR_CLEAR_SPEC; +impl crate::RegisterSpec for TX_ERROR_CLEAR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`tx_error_clear::R`](R) reader structure"] +impl crate::Readable for TX_ERROR_CLEAR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tx_error_clear::W`](W) writer structure"] +impl crate::Writable for TX_ERROR_CLEAR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TX_ERROR_CLEAR to value 0"] +impl crate::Resettable for TX_ERROR_CLEAR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32s2/src/wifi/txq_state/tx_error_status.rs b/esp32s2/src/wifi/txq_state/tx_error_status.rs new file mode 100644 index 000000000..3106d1fe4 --- /dev/null +++ b/esp32s2/src/wifi/txq_state/tx_error_status.rs @@ -0,0 +1,62 @@ +#[doc = "Register `TX_ERROR_STATUS` reader"] +pub type R = crate::R; +#[doc = "Register `TX_ERROR_STATUS` writer"] +pub type W = crate::W; +#[doc = "Field `SLOT_COLLISION` reader - "] +pub type SLOT_COLLISION_R = crate::FieldReader; +#[doc = "Field `SLOT_COLLISION` writer - "] +pub type SLOT_COLLISION_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `SLOT_TIMEOUT` reader - "] +pub type SLOT_TIMEOUT_R = crate::FieldReader; +#[doc = "Field `SLOT_TIMEOUT` writer - "] +pub type SLOT_TIMEOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +impl R { + #[doc = "Bits 0:4"] + #[inline(always)] + pub fn slot_collision(&self) -> SLOT_COLLISION_R { + SLOT_COLLISION_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 16:20"] + #[inline(always)] + pub fn slot_timeout(&self) -> SLOT_TIMEOUT_R { + SLOT_TIMEOUT_R::new(((self.bits >> 16) & 0x1f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TX_ERROR_STATUS") + .field("slot_collision", &self.slot_collision()) + .field("slot_timeout", &self.slot_timeout()) + .finish() + } +} +impl W { + #[doc = "Bits 0:4"] + #[inline(always)] + pub fn slot_collision(&mut self) -> SLOT_COLLISION_W { + SLOT_COLLISION_W::new(self, 0) + } + #[doc = "Bits 16:20"] + #[inline(always)] + pub fn slot_timeout(&mut self) -> SLOT_TIMEOUT_W { + SLOT_TIMEOUT_W::new(self, 16) + } +} +#[doc = "Error status of a slot\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_error_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_error_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TX_ERROR_STATUS_SPEC; +impl crate::RegisterSpec for TX_ERROR_STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`tx_error_status::R`](R) reader structure"] +impl crate::Readable for TX_ERROR_STATUS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tx_error_status::W`](W) writer structure"] +impl crate::Writable for TX_ERROR_STATUS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TX_ERROR_STATUS to value 0"] +impl crate::Resettable for TX_ERROR_STATUS_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32s2/svd/patches/esp32s2-wifi.yaml b/esp32s2/svd/patches/esp32s2-wifi.yaml new file mode 100644 index 000000000..f0e0a4035 --- /dev/null +++ b/esp32s2/svd/patches/esp32s2-wifi.yaml @@ -0,0 +1,96 @@ +_add: + WIFI: + description: MAC controller for Wi-Fi peripheral + groupName: WIFI + baseAddress: 0x60033000 + size: 32 + addressBlock: + offset: 0x0 + size: 0x2200 + usage: registers + registers: + RX_CTRL: + addressOffset: 0x88 + INTERFACE_RX_CONTROL%s: + dim: 4 + dimIncrement: 4 + addressOffset: 0xe0 + CTRL: + description: Exact name and meaning unknown, used for initializing the MAC + addressOffset: 0xcb8 + access: read-write + PLCP1%s: + dim: 5 + dimIncrement: 0x3c + addressOffset: 0x1168 + PLCP2%s: + dim: 5 + dimIncrement: 0x3c + addressOffset: 0x116c + HT_SIG%s: + dim: 5 + dimIncrement: 0x3c + addressOffset: 0x1170 + HT_UNKNOWN%s: + dim: 5 + dimIncrement: 0x3c + addressOffset: 0x1174 + DURATION%s: + dim: 5 + dimIncrement: 0x3c + addressOffset: 0x1178 + PMD%s: + dim: 5 + dimIncrement: 0x3c + addressOffset: 0x1180 +WIFI: + _add: + _clusters: + FILTER_BANK%s: + dim: 2 + dimIncrement: 0x40 + addressOffset: 0x0 + description: " + Filter banks for frame reception. Bank zero is for the BSSID and bank one for the RA. + Each filter bank has registers for two interfaces. + " + registers: + DUMMY: + addressOffset: 0x0 + RX_DMA_LIST: + addressOffset: 0x90 + registers: + DUMMY: + addressOffset: 0x0 + MAC_INTERRUPT: + addressOffset: 0xc3c + description: Status and clear for the WIFI_MAC interrupt + registers: + DUMMY: + addressOffset: 0x0 + PWR_INTERRUPT: + addressOffset: 0x21a0 + description: Status and clear for the WIFI_PWR interrupt + registers: + DUMMY: + addressOffset: 0x0 + TXQ_STATE: + addressOffset: 0xc9c + description: State of transmission queues + registers: + DUMMY: + addressOffset: 0x0 + TX_SLOT_CONFIG%s: + dim: 5 + dimIncrement: 0x8 + description: Used to configure the TX slot. + addressOffset: 0xcdc + registers: + DUMMY: + addressOffset: 0x0 +_include: + - "../../../common_patches/wifi/rx.yaml" + - "../../../common_patches/wifi/rx_filter_masked.yaml" + - "../../../common_patches/wifi/tx.yaml" + - "../../../common_patches/wifi/mac_interrupt.yaml" + - "../../../common_patches/wifi/pwr_interrupt.yaml" diff --git a/esp32s2/svd/patches/esp32s2.yaml b/esp32s2/svd/patches/esp32s2.yaml index f034fbdcc..7dd0b269a 100644 --- a/esp32s2/svd/patches/esp32s2.yaml +++ b/esp32s2/svd/patches/esp32s2.yaml @@ -1409,3 +1409,5 @@ RSA: _modify: INTERRUPT_ENA: name: INT_ENA +_include: + - "esp32s2-wifi.yaml"