diff --git a/esp-lp-hal/CHANGELOG.md b/esp-lp-hal/CHANGELOG.md index 2e99f20a31..19a444a222 100644 --- a/esp-lp-hal/CHANGELOG.md +++ b/esp-lp-hal/CHANGELOG.md @@ -12,6 +12,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0 ### Changed - Bump MSRV to 1.84 (#2951) +- Fix gpio `input_state` and `output_state` for the ESP32-S3 and ESP32-S2 (#3191) ### Fixed diff --git a/esp-lp-hal/src/gpio.rs b/esp-lp-hal/src/gpio.rs index 9a3bfe5f00..3cbf151190 100644 --- a/esp-lp-hal/src/gpio.rs +++ b/esp-lp-hal/src/gpio.rs @@ -39,7 +39,15 @@ pub struct Input; impl Input { /// Read the input state/level of the pin. pub fn input_state(&self) -> bool { - (unsafe { &*LpIo::PTR }.in_().read().bits() >> PIN) & 0x1 != 0 + cfg_if::cfg_if! { + if #[cfg(feature = "esp32c6")] { + (unsafe { &*LpIo::PTR }.in_().read().bits() >> PIN) & 0x1 != 0 + } else if #[cfg(feature = "esp32s2")] { + (unsafe { &*LpIo::PTR }.in_().read().gpio_in_next().bits() >> PIN) & 0x1 != 0 + } else if #[cfg(feature = "esp32s3")] { + (unsafe { &*LpIo::PTR }.in_().read().next().bits() >> PIN) & 0x1 != 0 + } + } } } @@ -49,7 +57,15 @@ pub struct Output; impl Output { /// Read the output state/level of the pin. pub fn output_state(&self) -> bool { - (unsafe { &*LpIo::PTR }.out().read().bits() >> PIN) & 0x1 != 0 + cfg_if::cfg_if! { + if #[cfg(feature = "esp32c6")] { + (unsafe { &*LpIo::PTR }.out().read().bits() >> PIN) & 0x1 != 0 + } else if #[cfg(feature = "esp32s2")] { + (unsafe { &*LpIo::PTR }.out().read().gpio_out_data().bits() >> PIN) & 0x1 != 0 + } else if #[cfg(feature = "esp32s3")] { + (unsafe { &*LpIo::PTR }.out().read().data().bits() >> PIN) & 0x1 != 0 + } + } } /// Set the output state/level of the pin.