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Fix NaxRISCV Bare Metal Demo and small fix for demo.py make routine #2170

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Fix NaxRISCV Bare Metal Demo and small fix for demo.py make routine #2170

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64d54ad
Update crt0.S
BMorgan1296 Jan 29, 2025
add318b
Update demo.py make routine.
BMorgan1296 Jan 29, 2025
cd5dbd2
Merge pull request #1 from BMorgan1296/BMorgan1296-patch-1-1
BMorgan1296 Jan 29, 2025
78f8e88
Merge pull request #2 from BMorgan1296/BMorgan1296-patch-1
BMorgan1296 Jan 29, 2025
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3 changes: 1 addition & 2 deletions litex/soc/cores/cpu/naxriscv/crt0.S
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Original file line number Diff line number Diff line change
Expand Up @@ -124,8 +124,7 @@ bss_loop:
bss_done:

call plic_init // initialize external interrupt controller
li t0, 0x800 // external interrupt sources only (using LiteX timer);
// NOTE: must still enable mstatus.MIE!
li t0, 0x808 // external interrupt sources (using LiteX timer) and enable mstatus.MIE.
csrw mie,t0

call main
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2 changes: 1 addition & 1 deletion litex/soc/software/demo/demo.py
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Expand Up @@ -31,7 +31,7 @@ def main():

# Compile demo
build_path = args.build_path if os.path.isabs(args.build_path) else os.path.join("..", args.build_path)
os.system(f"export BUILD_DIR={build_path} && {'export WITH_CXX=1 &&' if args.with_cxx else ''} cd demo && make")
os.system(f"export BUILD_DIR={build_path} && {'export WITH_CXX=1 &&' if args.with_cxx else ''} cd demo && make clean && make") # Clean demo before make to handle case when switching to a different CPU.

# Copy demo.bin
os.system("cp demo/demo.bin ./")
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