gen: fhdl: expression: resolve slice completly #2161
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resolve slice completly, to reduce complexity in the verilog files. Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
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Nice! Thanks @maass-hamburg, this makes sense and indeed reduce complexity. |
enjoy-digital
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Jan 20, 2025
Ex: python3 -m litex_boards.targets.lambdaconcept_ecpix5 --build --cpu-type rocket --cpu-variant linux --cpu-num-cores 1 --cpu-mem-width 2 --sys-clk-freq 50e6 --with-ethernet --with-sdcard --yosys-flow3
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@enjoy-digital lowering slices is still needed, if it is used together with Cat(). I moved the logic of this inside the lowerer: m-labs/migen#301 |
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resolve slice completly, to reduce complexity
in the verilog files.