integration/soc/jtag: Switch JTAGPHY to sys_clk/simplify.

litex/soc/integration/soc.py

@@ -1440,10 +1440,7 @@ def add_uart(self, name="uart", uart_name="serial", baudrate=115200, fifo_depth=
         # JTAG UART.
         elif uart_name in ["jtag_uart"]:
             from litex.soc.cores.jtag import JTAGPHY
-            # Run JTAG-UART in sys_jtag clk domain similar to sys clk domain but without sys_rst.
-            self.cd_sys_jtag = ClockDomain()
-            self.comb += self.cd_sys_jtag.clk.eq(ClockSignal("sys"))
-            uart_phy = JTAGPHY(device=self.platform.device, clock_domain="sys_jtag", platform=self.platform)
+            uart_phy = JTAGPHY(device=self.platform.device, platform=self.platform)
             uart     = UART(uart_phy, **uart_kwargs)
 
         # Sim.