Skip to content

Commit

Permalink
soc/interconnect/packet: Add **kwargs to Arbiter/Dispatcher to allow …
Browse files Browse the repository at this point in the history
…specifying keep/omit parameters for connection.
  • Loading branch information
enjoy-digital committed Feb 28, 2024
1 parent fea3a7e commit 42c1046
Showing 1 changed file with 5 additions and 5 deletions.
10 changes: 5 additions & 5 deletions litex/soc/interconnect/packet.py
Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
#
# This file is part of LiteX.
#
# Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>
# Copyright (c) 2015-2024 Florent Kermarrec <florent@enjoy-digital.fr>
# Copyright (c) 2019 Vamsi K Vytla <vkvytla@lbl.gov>
# SPDX-License-Identifier: BSD-2-Clause

Expand Down Expand Up @@ -37,12 +37,12 @@ def __init__(self, endpoint):
# Arbiter ------------------------------------------------------------------------------------------

class Arbiter(LiteXModule):
def __init__(self, masters, slave):
def __init__(self, masters, slave, **kwargs):
if len(masters) == 0:
pass
elif len(masters) == 1:
self.grant = Signal()
self.comb += masters.pop().connect(slave)
self.comb += masters.pop().connect(slave, **kwargs)
else:
self.rr = RoundRobin(len(masters))
self.grant = self.rr.grant
Expand All @@ -57,11 +57,11 @@ def __init__(self, masters, slave):
# Dispatcher ---------------------------------------------------------------------------------------

class Dispatcher(LiteXModule):
def __init__(self, master, slaves, one_hot=False):
def __init__(self, master, slaves, one_hot=False, **kwargs):
if len(slaves) == 0:
self.sel = Signal()
elif len(slaves) == 1 and not one_hot:
self.comb += master.connect(slaves.pop())
self.comb += master.connect(slaves.pop(), **kwargs)
self.sel = Signal()
else:
if one_hot:
Expand Down

0 comments on commit 42c1046

Please sign in to comment.