build: io: allow in clk to be different on SDR/DDR Tristate

allow in clk to be different on SDR/DDR Tristate. Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
enjoy-digital · Jan 14, 2025 · 2299b23 · 2299b23
1 parent a5c39e1
commit 2299b23
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Showing 6 changed files with 40 additions and 34 deletions.
diff --git a/litex/build/altera/common.py b/litex/build/altera/common.py
@@ -230,14 +230,14 @@ def lower(dr):
 # Agilex5 SDRTristate ------------------------------------------------------------------------------
 
 class Agilex5SDRTristateImpl(Module):
-    def __init__(self, io, o, oe, i, clk):
+    def __init__(self, io, o, oe, i, clk, in_clk):
         _i  = Signal().like(i)
         _o  = Signal().like(o)
         _oe = Signal().like(oe)
         self.specials += [
             SDRIO(o, _o, clk),
             SDRIO(oe, _oe, clk),
-            SDRIO(_i, i, clk)
+            SDRIO(_i, i, in_clk)
         ]
 
         for j in range(len(io)):
@@ -258,7 +258,7 @@ def __init__(self, io, o, oe, i, clk):
 class Agilex5SDRTristate(Module):
     @staticmethod
     def lower(dr):
-        return Agilex5SDRTristateImpl(dr.io, dr.o, dr.oe, dr.i, dr.clk)
+        return Agilex5SDRTristateImpl(dr.io, dr.o, dr.oe, dr.i, dr.clk, dr.in_clk)
 
 # Agilex5 Special Overrides ------------------------------------------------------------------------
 

diff --git a/litex/build/efinix/common.py b/litex/build/efinix/common.py
@@ -303,9 +303,10 @@ def lower(dr):
 # Efinix DDRTristate -------------------------------------------------------------------------------
 
 class EfinixDDRTristateImpl(LiteXModule):
-    def __init__(self, io, o1, o2, oe1, oe2, i1, i2, clk):
+    def __init__(self, io, o1, o2, oe1, oe2, i1, i2, clk, in_clk):
         assert oe2 is None
         clk, out_clk_inv = check_clk_inverted(clk)
+        in_clk, in_clk_inv = check_clk_inverted(in_clk)
         assert_is_signal_or_clocksignal(clk)
         platform     = LiteXContext.platform
         if len(io) == 1:
@@ -335,11 +336,11 @@ def __init__(self, io, o1, o2, oe1, oe2, i1, i2, clk):
             "properties"     : io_prop,
             "size"           : len(io),
             "in_reg"         : "DDIO_RESYNC",
-            "in_clk_pin"     : clk,
+            "in_clk_pin"     : in_clk,
             "out_reg"        : "DDIO_RESYNC",
             "out_clk_pin"    : clk,
             "oe_reg"         : "REG",
-            "in_clk_inv"     : out_clk_inv,
+            "in_clk_inv"     : in_clk_inv,
             "out_clk_inv"    : out_clk_inv,
             "drive_strength" : io_prop_dict.get("DRIVE_STRENGTH", "4")
         }
@@ -349,13 +350,14 @@ def __init__(self, io, o1, o2, oe1, oe2, i1, i2, clk):
 class EfinixDDRTristate:
     @staticmethod
     def lower(dr):
-        return EfinixDDRTristateImpl(dr.io, dr.o1, dr.o2, dr.oe1, dr.oe2, dr.i1, dr.i2, dr.clk, **dr.kwargs)
+        return EfinixDDRTristateImpl(dr.io, dr.o1, dr.o2, dr.oe1, dr.oe2, dr.i1, dr.i2, dr.clk, dr.in_clk)
 
 # Efinix SDRTristate -------------------------------------------------------------------------------
 
 class EfinixSDRTristateImpl(LiteXModule):
-    def __init__(self, io, o, oe, i, clk):
+    def __init__(self, io, o, oe, i, clk, in_clk):
         clk, out_clk_inv = check_clk_inverted(clk)
+        in_clk, in_clk_inv = check_clk_inverted(in_clk)
         assert_is_signal_or_clocksignal(clk)
         platform     = LiteXContext.platform
         if len(io) == 1:
@@ -385,12 +387,12 @@ def __init__(self, io, o, oe, i, clk):
             "properties"     : io_prop,
             "size"           : len(io),
             "in_reg"         : "REG",
-            "in_clk_pin"     : clk,
+            "in_clk_pin"     : in_clk,
             "out_reg"        : "REG",
             "out_clk_pin"    : clk,
             "const_output"   : const_output,
             "oe_reg"         : "REG",
-            "in_clk_inv"     : out_clk_inv,
+            "in_clk_inv"     : in_clk_inv,
             "out_clk_inv"    : out_clk_inv,
             "drive_strength" : io_prop_dict.get("DRIVE_STRENGTH", "4")
         }
@@ -401,7 +403,7 @@ def __init__(self, io, o, oe, i, clk):
 class EfinixSDRTristate(LiteXModule):
     @staticmethod
     def lower(dr):
-        return EfinixSDRTristateImpl(dr.io, dr.o, dr.oe, dr.i, dr.clk, **dr.kwargs)
+        return EfinixSDRTristateImpl(dr.io, dr.o, dr.oe, dr.i, dr.clk, dr.in_clk)
 
 # Efinix SDROutput ---------------------------------------------------------------------------------
 

diff --git a/litex/build/gowin/common.py b/litex/build/gowin/common.py
@@ -167,14 +167,14 @@ def lower(dr):
 # Gw5A SDRTristate ---------------------------------------------------------------------------------
 
 class Gw5ASDRTristateImpl(Module):
-    def __init__(self, io, o, oe, i, clk):
+    def __init__(self, io, o, oe, i, clk, in_clk):
         _o    = Signal().like(o)
         _oe_n = Signal().like(oe)
         _i    = Signal().like(i)
         self.specials += [
             SDROutput(o, _o, clk),
             SDROutput(~oe, _oe_n, clk),
-            SDRInput(_i, i, clk),
+            SDRInput(_i, i, in_clk),
         ]
         for j in range(len(io)):
             self.specials += Instance("IOBUF",
@@ -188,7 +188,7 @@ def __init__(self, io, o, oe, i, clk):
 class Gw5ASDRTristate:
     @staticmethod
     def lower(dr):
-        return Gw5ASDRTristateImpl(dr.io, dr.o, dr.oe, dr.i, dr.clk)
+        return Gw5ASDRTristateImpl(dr.io, dr.o, dr.oe, dr.i, dr.clk, dr.in_clk)
 
 # Gw5A Special Overrides ---------------------------------------------------------------------------
 

diff --git a/litex/build/io.py b/litex/build/io.py
@@ -108,23 +108,24 @@ class SDROutput(SDRIO): pass
 # SDR Tristate -------------------------------------------------------------------------------------
 
 class InferedSDRTristate(Module):
-    def __init__(self, io, o, oe, i, clk):
+    def __init__(self, io, o, oe, i, clk, in_clk):
         _o  = Signal().like(o)
         _oe = Signal().like(oe)
         _i  = Signal().like(i)
         self.specials   += SDROutput(o, _o, clk)
-        self.specials   += SDRInput(_i, i, clk)
+        self.specials   += SDRInput(_i, i, in_clk)
         self.submodules += InferedSDRIO(oe, _oe, clk)
         self.specials   += Tristate(io, _o, _oe, _i)
 
 class SDRTristate(Special):
-    def __init__(self, io, o, oe, i, clk=None):
+    def __init__(self, io, o, oe, i, clk=None, in_clk=None):
         Special.__init__(self)
         self.io  = wrap(io)
         self.o   = wrap(o)
         self.oe  = wrap(oe)
         self.i   = wrap(i)
         self.clk = wrap(clk) if clk is not None else ClockSignal()
+        self.in_clk = wrap(in_clk) if in_clk is not None else self.clk
         assert len(self.i) == len(self.o) == len(self.oe)
 
     def iter_expressions(self):
@@ -133,10 +134,11 @@ def iter_expressions(self):
         yield self, "oe" , SPECIAL_INPUT
         yield self, "i"  , SPECIAL_OUTPUT
         yield self, "clk", SPECIAL_INPUT
+        yield self, "in_clk", SPECIAL_INPUT
 
     @staticmethod
     def lower(dr):
-        return InferedSDRTristate(dr.io, dr.o, dr.oe, dr.i, dr.clk)
+        return InferedSDRTristate(dr.io, dr.o, dr.oe, dr.i, dr.clk, dr.in_clk)
 
 # DDR Input/Output ---------------------------------------------------------------------------------
 
@@ -184,17 +186,17 @@ def lower(dr):
 # DDR Tristate -------------------------------------------------------------------------------------
 
 class InferedDDRTristate(Module):
-    def __init__(self, io, o1, o2, oe1, oe2, i1, i2, clk):
+    def __init__(self, io, o1, o2, oe1, oe2, i1, i2, clk, in_clk):
         _o  = Signal().like(o1)
         _oe = Signal().like(oe1)
         _i  = Signal().like(i1)
         self.specials += DDROutput(o1, o2, _o, clk)
         self.specials += DDROutput(oe1, oe2, _oe, clk) if oe2 is not None else SDROutput(oe1, _oe, clk)
-        self.specials += DDRInput(_i, i1, i2, clk)
+        self.specials += DDRInput(_i, i1, i2, in_clk)
         self.specials += Tristate(io, _o, _oe, _i)
 
 class DDRTristate(Special):
-    def __init__(self, io, o1, o2, oe1, oe2=None, i1=None, i2=None, clk=None):
+    def __init__(self, io, o1, o2, oe1, oe2=None, i1=None, i2=None, clk=None, in_clk=None):
         Special.__init__(self)
         self.io  = io
         self.o1  = o1
@@ -204,6 +206,7 @@ def __init__(self, io, o1, o2, oe1, oe2=None, i1=None, i2=None, clk=None):
         self.i1  = i1 if i1 is not None else Signal()
         self.i2  = i2 if i2 is not None else Signal()
         self.clk = clk if clk is not None else ClockSignal()
+        self.in_clk = in_clk if in_clk is not None else self.clk
 
     def iter_expressions(self):
         yield self, "io" , SPECIAL_INOUT
@@ -214,10 +217,11 @@ def iter_expressions(self):
         yield self, "i1" , SPECIAL_OUTPUT
         yield self, "i2" , SPECIAL_OUTPUT
         yield self, "clk", SPECIAL_INPUT
+        yield self, "in_clk", SPECIAL_INPUT
 
     @staticmethod
     def lower(dr):
-        return InferedDDRTristate(dr.io, dr.o1, dr.o2, dr.oe1, dr.oe2, dr.i1, dr.i2, dr.clk)
+        return InferedDDRTristate(dr.io, dr.o1, dr.o2, dr.oe1, dr.oe2, dr.i1, dr.i2, dr.clk, dr.in_clk)
 
 # Clock Reset Generator ----------------------------------------------------------------------------
 

diff --git a/litex/build/lattice/common.py b/litex/build/lattice/common.py
@@ -332,21 +332,21 @@ def lower(dr):
 # NX DDR Tristate ----------------------------------------------------------------------------------
 
 class LatticeNXDDRTristateImpl(Module):
-    def __init__(self, io, o1, o2, oe1, oe2, i1, i2, clk):
+    def __init__(self, io, o1, o2, oe1, oe2, i1, i2, clk, in_clk):
         assert oe2 is None
         _o  = Signal().like(o1)
         _oe = Signal().like(oe1)
         _i  = Signal().like(i1)
         self.specials += DDROutput(o1, o2, _o, clk)
         self.specials += SDROutput(oe1, _oe, clk)
-        self.specials += DDRInput(_i, i1, i2, clk)
+        self.specials += DDRInput(_i, i1, i2, in_clk)
         self.specials += Tristate(io, _o, _oe, _i)
         _oe.attr.add("syn_useioff")
 
 class LatticeNXDDRTristate:
     @staticmethod
     def lower(dr):
-        return LatticeNXDDRTristateImpl(dr.io, dr.o1, dr.o2, dr.oe1, dr.oe2, dr.i1, dr.i2, dr.clk)
+        return LatticeNXDDRTristateImpl(dr.io, dr.o1, dr.o2, dr.oe1, dr.oe2, dr.i1, dr.i2, dr.clk, dr.in_clk)
 
 # NX Special Overrides -----------------------------------------------------------------------------
 
@@ -533,12 +533,12 @@ def lower(dr):
 # iCE40 SDR Tristate -------------------------------------------------------------------------------
 
 class LatticeiCE40SDRTristateImpl(Module):
-    def __init__(self, io, o, oe, i, clk):
+    def __init__(self, io, o, oe, i, clk, in_clk):
         for j in range(len(io)):
             self.specials += Instance("SB_IO",
                 p_PIN_TYPE      = C(0b110100, 6), # PIN_OUTPUT_REGISTERED_ENABLE_REGISTERED + PIN_INPUT_REGISTERED
                 io_PACKAGE_PIN  = io[j],
-                i_INPUT_CLK     = clk,
+                i_INPUT_CLK     = in_clk,
                 i_OUTPUT_CLK    = clk,
                 i_OUTPUT_ENABLE = oe[j],
                 i_D_OUT_0       = o[j] ,
@@ -548,7 +548,7 @@ def __init__(self, io, o, oe, i, clk):
 class LatticeiCE40SDRTristate(Module):
     @staticmethod
     def lower(dr):
-        return LatticeiCE40SDRTristateImpl(dr.io, dr.o, dr.oe, dr.i, dr.clk)
+        return LatticeiCE40SDRTristateImpl(dr.io, dr.o, dr.oe, dr.i, dr.clk, dr.in_clk)
 
 # iCE40 Trellis Special Overrides ------------------------------------------------------------------
 

diff --git a/litex/build/xilinx/common.py b/litex/build/xilinx/common.py
@@ -137,13 +137,13 @@ def lower(dr):
 # Common SDRTristate -------------------------------------------------------------------------------
 
 class XilinxSDRTristateImpl(Module):
-    def __init__(self, io, o, oe, i, clk):
+    def __init__(self, io, o, oe, i, clk, in_clk):
         _o    = Signal().like(o)
         _oe_n = Signal().like(oe)
         _i    = Signal().like(i)
         self.specials += SDROutput(o, _o, clk)
         self.specials += SDROutput(~oe, _oe_n, clk)
-        self.specials += SDRInput(_i, i, clk)
+        self.specials += SDRInput(_i, i, in_clk)
         for j in range(len(io)):
             self.specials += Instance("IOBUF",
                 io_IO = io[j],
@@ -155,18 +155,18 @@ def __init__(self, io, o, oe, i, clk):
 class XilinxSDRTristate:
     @staticmethod
     def lower(dr):
-        return XilinxSDRTristateImpl(dr.io, dr.o, dr.oe, dr.i, dr.clk)
+        return XilinxSDRTristateImpl(dr.io, dr.o, dr.oe, dr.i, dr.clk, dr.in_clk)
 
 # Common DDRTristate -------------------------------------------------------------------------------
 
 class XilinxDDRTristateImpl(Module):
-    def __init__(self, io, o1, o2, oe1, oe2, i1, i2, clk):
+    def __init__(self, io, o1, o2, oe1, oe2, i1, i2, clk, in_clk):
         _o    = Signal().like(o1)
         _oe_n = Signal().like(oe1)
         _i    = Signal().like(i1)
         self.specials += DDROutput(o1, o2, _o, clk)
         self.specials += DDROutput(~oe1, ~oe2, _oe_n, clk) if oe2 is not None else SDROutput(~oe1, _oe_n, clk)
-        self.specials += DDRInput(_i, i1, i2, clk)
+        self.specials += DDRInput(_i, i1, i2, clk, in_clk)
         for j in range(len(io)):
             self.specials += Instance("IOBUF",
                 io_IO = io[j],
@@ -178,7 +178,7 @@ def __init__(self, io, o1, o2, oe1, oe2, i1, i2, clk):
 class XilinxDDRTristate:
     @staticmethod
     def lower(dr):
-        return XilinxDDRTristateImpl(dr.io, dr.o1, dr.o2, dr.oe1, dr.oe2, dr.i1, dr.i2, dr.clk)
+        return XilinxDDRTristateImpl(dr.io, dr.o1, dr.o2, dr.oe1, dr.oe2, dr.i1, dr.i2, dr.clk, dr.in_clk)
 
 # Common Special Overrides -------------------------------------------------------------------------