fix: use VERILOG_INCLUDE_DIRS in Verilator.Lint (#661)

Signed-off-by: fkwilken <fkwilken@gmail.com>
efabless · Feb 13, 2025 · 22d3a65 · 22d3a65
1 parent e88bfa2
commit 22d3a65
Showing 1 changed file with 8 additions and 0 deletions.
diff --git a/openlane/steps/verilator.py b/openlane/steps/verilator.py
@@ -42,6 +42,11 @@ class Lint(Step):
             List[Path],
             "The paths of the design's Verilog files.",
         ),
+        Variable(
+            "VERILOG_INCLUDE_DIRS",
+            Optional[List[Path]],
+            "Specifies the Verilog `include` directories.",
+        ),
         Variable(
             "VERILOG_POWER_DEFINE",
             Optional[str],
@@ -158,6 +163,9 @@ def run(self, state_in: State, **kwargs) -> Tuple[ViewsUpdate, MetricsUpdate]:
         if self.config["LINTER_ERROR_ON_LATCH"]:
             extra_args.append("--Werror-LATCH")
 
+        if include_dirs := self.config["VERILOG_INCLUDE_DIRS"]:
+            extra_args.extend([f"-I{dir}" for dir in include_dirs])
+
         for define in defines:
             extra_args.append(f"+define+{define}")