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vivado_31180.backup.jou
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#-----------------------------------------------------------
# Vivado v2020.2 (64-bit)
# SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020
# IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020
# Start of session at: Sun May 8 20:46:58 2022
# Process ID: 31180
# Current directory: E:/FPGA_Workspace/Simple RISC
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent18564 E:\FPGA_Workspace\Simple RISC\simple_risc.xpr
# Log file: E:/FPGA_Workspace/Simple RISC/vivado.log
# Journal file: E:/FPGA_Workspace/Simple RISC\vivado.jou
#-----------------------------------------------------------
start_gui
open_project {E:/FPGA_Workspace/Simple RISC/simple_risc.xpr}
update_compile_order -fileset sources_1
add_files {{E:/FPGA_Workspace/Simple RISC/simple_risc.srcs/sources_1/new/ram_test.v} {E:/FPGA_Workspace/Simple RISC/simple_risc.srcs/sources_1/new/rom_test.v} {E:/FPGA_Workspace/Simple RISC/simple_risc.srcs/sources_1/new/clock_manager.v} {E:/FPGA_Workspace/Simple RISC/simple_risc.srcs/sources_1/new/condition_control.v} {E:/FPGA_Workspace/Simple RISC/simple_risc.srcs/sources_1/new/address_multiplexer.v} {E:/FPGA_Workspace/Simple RISC/simple_risc.srcs/sources_1/new/addr_decode.v} {E:/FPGA_Workspace/Simple RISC/simple_risc.srcs/sources_1/new/accumulator.v} {E:/FPGA_Workspace/Simple RISC/simple_risc.srcs/sources_1/new/command_register.v} {E:/FPGA_Workspace/Simple RISC/simple_risc.srcs/sources_1/new/data_controller.v} {E:/FPGA_Workspace/Simple RISC/simple_risc.srcs/sources_1/new/program_counter.v} {E:/FPGA_Workspace/Simple RISC/simple_risc.srcs/sources_1/new/risc_cpu.v} {E:/FPGA_Workspace/Simple RISC/simple_risc.srcs/sources_1/new/alu.v}}
update_compile_order -fileset sources_1
export_ip_user_files -of_objects [get_files {{E:/FPGA_Workspace/Simple RISC/simple_risc.srcs/sources_1/new/addr_decode.v}}] -no_script -reset -force -quiet
export_ip_user_files -of_objects [get_files {{E:/FPGA_Workspace/Simple RISC/simple_risc.srcs/sources_1/new/ram_test.v}}] -no_script -reset -force -quiet
export_ip_user_files -of_objects [get_files {{E:/FPGA_Workspace/Simple RISC/simple_risc.srcs/sources_1/new/rom_test.v}}] -no_script -reset -force -quiet
remove_files {{E:/FPGA_Workspace/Simple RISC/simple_risc.srcs/sources_1/new/addr_decode.v} {E:/FPGA_Workspace/Simple RISC/simple_risc.srcs/sources_1/new/ram_test.v} {E:/FPGA_Workspace/Simple RISC/simple_risc.srcs/sources_1/new/rom_test.v}}
export_ip_user_files -of_objects [get_files {{C:/Users/lenovo/Desktop/Simple RISC/simple_risc.srcs/sources_1/new/accumulator.v}}] -no_script -reset -force -quiet
export_ip_user_files -of_objects [get_files {{C:/Users/lenovo/Desktop/Simple RISC/simple_risc.srcs/sources_1/new/address_multiplexer.v}}] -no_script -reset -force -quiet
export_ip_user_files -of_objects [get_files {{C:/Users/lenovo/Desktop/Simple RISC/simple_risc.srcs/sources_1/new/alu.v}}] -no_script -reset -force -quiet
export_ip_user_files -of_objects [get_files {{C:/Users/lenovo/Desktop/Simple RISC/simple_risc.srcs/sources_1/new/clock_manager.v}}] -no_script -reset -force -quiet
export_ip_user_files -of_objects [get_files {{C:/Users/lenovo/Desktop/Simple RISC/simple_risc.srcs/sources_1/new/command_register.v}}] -no_script -reset -force -quiet
export_ip_user_files -of_objects [get_files {{C:/Users/lenovo/Desktop/Simple RISC/simple_risc.srcs/sources_1/new/condition_control.v}}] -no_script -reset -force -quiet
export_ip_user_files -of_objects [get_files {{C:/Users/lenovo/Desktop/Simple RISC/simple_risc.srcs/sources_1/new/data_controller.v}}] -no_script -reset -force -quiet
export_ip_user_files -of_objects [get_files {{C:/Users/lenovo/Desktop/Simple RISC/simple_risc.srcs/sources_1/new/program_counter.v}}] -no_script -reset -force -quiet
export_ip_user_files -of_objects [get_files {{C:/Users/lenovo/Desktop/Simple RISC/simple_risc.srcs/sources_1/new/risc_cpu.v}}] -no_script -reset -force -quiet
remove_files {{C:/Users/lenovo/Desktop/Simple RISC/simple_risc.srcs/sources_1/new/accumulator.v} {C:/Users/lenovo/Desktop/Simple RISC/simple_risc.srcs/sources_1/new/address_multiplexer.v} {C:/Users/lenovo/Desktop/Simple RISC/simple_risc.srcs/sources_1/new/alu.v} {C:/Users/lenovo/Desktop/Simple RISC/simple_risc.srcs/sources_1/new/clock_manager.v} {C:/Users/lenovo/Desktop/Simple RISC/simple_risc.srcs/sources_1/new/command_register.v} {C:/Users/lenovo/Desktop/Simple RISC/simple_risc.srcs/sources_1/new/condition_control.v} {C:/Users/lenovo/Desktop/Simple RISC/simple_risc.srcs/sources_1/new/data_controller.v} {C:/Users/lenovo/Desktop/Simple RISC/simple_risc.srcs/sources_1/new/program_counter.v} {C:/Users/lenovo/Desktop/Simple RISC/simple_risc.srcs/sources_1/new/risc_cpu.v}}
launch_simulation
source risc_cpu_tb.tcl
run all
run all
run all
open_wave_config {E:/FPGA_Workspace/Simple RISC/risc_cpu_tb_behav.wcfg}
close_sim