diff --git a/boards/catie/zest_core_stm32l4a6rg/sixtron_connector.dtsi b/boards/catie/zest_core_stm32l4a6rg/sixtron_connector.dtsi
index 0458667..ce42db4 100644
--- a/boards/catie/zest_core_stm32l4a6rg/sixtron_connector.dtsi
+++ b/boards/catie/zest_core_stm32l4a6rg/sixtron_connector.dtsi
@@ -25,7 +25,7 @@
                    <PWM1 0 &gpioa 10 0>,
                    <PWM2 0 &gpioa 9 0>,
                    <PWM3 0 &gpiob 0 0>,
-                   <ICAP 0 &gpiob 1 0>,
+                   <ICAPT 0 &gpiob 1 0>,
                    <WKUP 0 &gpioc 13 0>,
                    <ADC1 0 &gpioc 2 0>,
                    <ADC2 0 &gpioc 3 0>,
@@ -67,21 +67,29 @@
     		pwms = <&pwm3 3 1000000 PWM_POLARITY_NORMAL>;
     	};
     };
+
+    sixtron_connector_1_adc: sixtron-connector-1-adc {
+        compatible = "sixtron-adc";
+        #io-channel-cells = <1>;
+        io-channel-map = <ADC1 &adc1 3>,
+                         <ADC2 &adc1 4>,
+                         <ADC3 &adc1 5>,
+                         <ADC4 &adc1 6>;
+    };
 };
 
 sixtron_connector_1_i2c: &i2c3 {};
 sixtron_connector_1_uart: &usart2 {};
 sixtron_connector_1_spi: &spi2 {};
-sixtron_connector_1_adc: &adc1 {};
 sixtron_connector_1_dac: &dac1 {};
 
 sixtron_i2c: &sixtron_connector_1_i2c {};
 sixtron_uart: &sixtron_connector_1_uart {};
 sixtron_spi: &sixtron_connector_1_spi {};
-sixtron_adc: &sixtron_connector_1_adc {};
 sixtron_dac: &sixtron_connector_1_dac {};
 sixtron_pwm1: &sixtron_connector_1_pwm1 {};
 sixtron_pwm2: &sixtron_connector_1_pwm2 {};
 sixtron_pwm3: &sixtron_connector_1_pwm3 {};
+sixtron_adc: &sixtron_connector_1_adc {};
 
 sixtron_connector: &sixtron_connector_1 {};
diff --git a/boards/catie/zest_core_stm32l4a6rg/zest_core_stm32l4a6rg.dts b/boards/catie/zest_core_stm32l4a6rg/zest_core_stm32l4a6rg.dts
index 2bcd4e1..f692fe8 100644
--- a/boards/catie/zest_core_stm32l4a6rg/zest_core_stm32l4a6rg.dts
+++ b/boards/catie/zest_core_stm32l4a6rg/zest_core_stm32l4a6rg.dts
@@ -121,6 +121,84 @@
 	st,adc-clock-source = <SYNC>;
 	st,adc-prescaler = <4>;
 	status = "okay";
+
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	channel@3 {
+		reg = <3>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+	};
+
+	channel@4 {
+		reg = <4>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+	};
+
+	channel@5 {
+		reg = <5>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+	};
+
+	channel@6 {
+		reg = <6>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+	};
+};
+
+&adc2 {
+	pinctrl-0 = <&adc2_in3_pc2 &adc2_in4_pc3 &adc2_in5_pa0 &adc2_in6_pa1>;
+	pinctrl-names = "default";
+	st,adc-clock-source = <SYNC>;
+	st,adc-prescaler = <4>;
+	status = "okay";
+
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	channel@3 {
+		reg = <3>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+	};
+
+	channel@4 {
+		reg = <4>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+	};
+
+	channel@5 {
+		reg = <5>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+	};
+
+	channel@6 {
+		reg = <6>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+	};
 };
 
 &dac1 {