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Fix infinite recursion due to recursive functions/tasks
Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
1 parent 4877627 commit d6ea5b9

6 files changed

+60
-3
lines changed

src/V3AstNodes.cpp

+4-1
Original file line numberDiff line numberDiff line change
@@ -76,7 +76,10 @@ bool AstNodeFTaskRef::isPure() {
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// cached.
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return false;
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} else {
79-
if (!m_purity.isCached()) m_purity.set(this->getPurityRecurse());
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if (!m_purity.isCached()) {
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m_purity.set(true);
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m_purity.set(this->getPurityRecurse());
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}
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return m_purity.get();
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}
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}

src/V3Hasher.cpp

+8-2
Original file line numberDiff line numberDiff line change
@@ -38,8 +38,8 @@ class HasherVisitor final : public VNVisitorConst {
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V3Hash hashNodeAndIterate(AstNode* nodep, bool hashDType, bool hashChildren,
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std::function<void()>&& f) {
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// See comments in visit(AstCFunc) about this breaking recursion
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if (m_cacheInUser4 && nodep->user4()) {
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// See comments in visit(AstCFunc/AstNodeFTask) about this breaking recursion
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if (nodep->user4()) {
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return V3Hash{nodep->user4()};
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} else {
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VL_RESTORER(m_hash);
@@ -470,7 +470,13 @@ class HasherVisitor final : public VNVisitorConst {
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}
471471
void visit(AstNodeFTask* nodep) override {
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m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [this, nodep]() { //
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// We might be in a recursive function, if so on *second* call
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// here we need to break what would be an infinite loop.
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m_hash += nodep->name();
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nodep->user4(true); // Set this "first" call
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// So that a second call will then exit hashNodeAndIterate
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// Having a constant in the hash just means the recursion will
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// end, it shouldn't change the NodeFTask having a unique hash itself.
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});
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}
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void visit(AstModport* nodep) override {
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,18 @@
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#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2023 by Wilson Snyder. This program is free software; you
6+
# can redistribute it and/or modify it under the terms of either the GNU
7+
# Lesser General Public License Version 3 or the Perl Artistic License
8+
# Version 2.0.
9+
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(vlt => 1);
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lint(
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verilator_flags2 => ["--no-unlimited-stack -Wno-lint"],
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);
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ok(1);
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1;
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,11 @@
1+
class axi_trans;
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function void pre_randomize();
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pre_randomize();
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endfunction
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endclass
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module t;
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axi_trans axi_txn;
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task body();
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int _ = axi_txn.randomize() with {1 == 1;};
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endtask
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endmodule
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,18 @@
1+
#!/usr/bin/env perl
2+
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
3+
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
4+
#
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# Copyright 2023 by Wilson Snyder. This program is free software; you
6+
# can redistribute it and/or modify it under the terms of either the GNU
7+
# Lesser General Public License Version 3 or the Perl Artistic License
8+
# Version 2.0.
9+
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
10+
11+
scenarios(vlt => 1);
12+
13+
lint(
14+
verilator_flags2 => ["--no-unlimited-stack"],
15+
);
16+
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ok(1);
18+
1;
Original file line numberDiff line numberDiff line change
@@ -0,0 +1 @@
1+
task t;t;endtask

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